From 90a24b9d737c54b3a20d1a3d0a2e2cd872a442ee Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Wed, 7 Oct 2020 12:52:36 -0700 Subject: drm/i915/display: Ignore IGNORE_PSR2_HW_TRACKING for platforms without sel fetch MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For platforms without selective fetch this register is reserved so do not write 0 to it. Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20201007195238.53955-1-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915/display/intel_psr.c') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8a9d0bdde1bf..4e09ae61d4aa 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -942,7 +942,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, intel_de_write(dev_priv, EXITLINE(cpu_transcoder), val); } - if (HAS_PSR_HW_TRACKING(dev_priv)) + if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) intel_de_rmw(dev_priv, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING, dev_priv->psr.psr2_sel_fetch_enabled ? IGNORE_PSR2_HW_TRACKING : 0); -- cgit From 5c90660fcc452824b767744f3f4e09a335ce8f91 Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Wed, 7 Oct 2020 12:52:37 -0700 Subject: drm/i915/display: Check PSR parameter and flag only in state compute phase MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Due to the debugfs flag, has_psr2 in CRTC state could have a different value than psr.psr2_enabled and it was causing PSR2 subfeatures(DC3CO and selective fetch) to be set to not a expected state. So here only taking in consideration the parameter and debugfs flag when computing PSR state, this way the CRTC state will also have the correct state. intel_psr_fastset_force() was already broken as intel_psr_compute_config() was already only enabling PSR when psr_global_enabled() and all other PSR requirements are met. So some changes was required in this function, now it iterates over all connectors, if it is a eDP connector and is active force a modeset in the CRTC driving this connector, what will cause the new PSR state to be set based on the debugfs flag. v2: - end connector iterator in error cases Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20201007195238.53955-2-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 73 ++++++++++++++++++-------------- 1 file changed, 41 insertions(+), 32 deletions(-) (limited to 'drivers/gpu/drm/i915/display/intel_psr.c') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4e09ae61d4aa..02f74b0ddec1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -91,19 +91,14 @@ static bool psr_global_enabled(struct drm_i915_private *i915) } } -static bool intel_psr2_enabled(struct drm_i915_private *dev_priv, - const struct intel_crtc_state *crtc_state) +static bool psr2_global_enabled(struct drm_i915_private *dev_priv) { - /* Cannot enable DSC and PSR2 simultaneously */ - drm_WARN_ON(&dev_priv->drm, crtc_state->dsc.compression_enable && - crtc_state->has_psr2); - switch (dev_priv->psr.debug & I915_PSR_DEBUG_MODE_MASK) { case I915_PSR_DEBUG_DISABLE: case I915_PSR_DEBUG_FORCE_PSR1: return false; default: - return crtc_state->has_psr2; + return true; } } @@ -729,6 +724,11 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } + if (!psr2_global_enabled(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); + return false; + } + /* * DSC and PSR2 cannot be enabled simultaneously. If a requested * resolution requires DSC to be enabled, priority is given to DSC @@ -817,8 +817,11 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (intel_dp != dev_priv->psr.dp) return; - if (!psr_global_enabled(dev_priv)) + if (!psr_global_enabled(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); return; + } + /* * HSW spec explicitly says PSR is tied to port A. * BDW+ platforms have a instance of PSR registers per transcoder but @@ -959,7 +962,7 @@ static void intel_psr_enable_locked(struct drm_i915_private *dev_priv, drm_WARN_ON(&dev_priv->drm, dev_priv->psr.enabled); - dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state); + dev_priv->psr.psr2_enabled = crtc_state->has_psr2; dev_priv->psr.busy_frontbuffer_bits = 0; dev_priv->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; dev_priv->psr.dc3co_enabled = !!crtc_state->dc3co_exitline; @@ -1029,15 +1032,7 @@ void intel_psr_enable(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, dev_priv->drrs.dp); mutex_lock(&dev_priv->psr.lock); - - if (!psr_global_enabled(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, "PSR disabled by flag\n"); - goto unlock; - } - intel_psr_enable_locked(dev_priv, crtc_state, conn_state); - -unlock: mutex_unlock(&dev_priv->psr.lock); } @@ -1222,8 +1217,8 @@ void intel_psr_update(struct intel_dp *intel_dp, mutex_lock(&dev_priv->psr.lock); - enable = crtc_state->has_psr && psr_global_enabled(dev_priv); - psr2_enable = intel_psr2_enabled(dev_priv, crtc_state); + enable = crtc_state->has_psr; + psr2_enable = crtc_state->has_psr2; if (enable == psr->enabled && psr2_enable == psr->psr2_enabled) { /* Force a PSR exit when enabling CRC to avoid CRC timeouts */ @@ -1320,11 +1315,12 @@ static bool __psr_wait_for_idle_locked(struct drm_i915_private *dev_priv) static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) { + struct drm_connector_list_iter conn_iter; struct drm_device *dev = &dev_priv->drm; struct drm_modeset_acquire_ctx ctx; struct drm_atomic_state *state; - struct intel_crtc *crtc; - int err; + struct drm_connector *conn; + int err = 0; state = drm_atomic_state_alloc(dev); if (!state) @@ -1334,25 +1330,38 @@ static int intel_psr_fastset_force(struct drm_i915_private *dev_priv) state->acquire_ctx = &ctx; retry: - for_each_intel_crtc(dev, crtc) { - struct intel_crtc_state *crtc_state = - intel_atomic_get_crtc_state(state, crtc); - if (IS_ERR(crtc_state)) { - err = PTR_ERR(crtc_state); - goto error; + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(conn, &conn_iter) { + struct drm_connector_state *conn_state; + struct drm_crtc_state *crtc_state; + + if (conn->connector_type != DRM_MODE_CONNECTOR_eDP) + continue; + + conn_state = drm_atomic_get_connector_state(state, conn); + if (IS_ERR(conn_state)) { + err = PTR_ERR(conn_state); + break; } - if (crtc_state->hw.active && crtc_state->has_psr) { - /* Mark mode as changed to trigger a pipe->update() */ - crtc_state->uapi.mode_changed = true; + if (!conn_state->crtc) + continue; + + crtc_state = drm_atomic_get_crtc_state(state, conn_state->crtc); + if (IS_ERR(crtc_state)) { + err = PTR_ERR(crtc_state); break; } + + /* Mark mode as changed to trigger a pipe->update() */ + crtc_state->mode_changed = true; } + drm_connector_list_iter_end(&conn_iter); - err = drm_atomic_commit(state); + if (err == 0) + err = drm_atomic_commit(state); -error: if (err == -EDEADLK) { drm_atomic_state_clear(state); err = drm_modeset_backoff(&ctx); -- cgit From 0bcbcba78269f425a8d258be59d918ee2a36724b Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Wed, 7 Oct 2020 12:52:38 -0700 Subject: drm/i915/display: Program PSR2 selective fetch registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Another step towards PSR2 selective fetch, here programming plane selective fetch registers and MAN_TRK_CTL enabling selective fetch but for now it is fetching the whole area of the planes. The damaged area calculation will come as next and final step. v2: - removed warn on when no plane is visible in state - removed calculations using plane damaged area in intel_psr2_program_plane_sel_fetch() v3: - do not shift 16 positions the plane dst coordinates, only src is shifted v4: - only setting PLANE_SEL_FETCH_CTL_ENABLE and MCURSOR_MODE in PLANE_SEL_FETCH_CTL v5: - not masking bits for cursor BSpec: 55229 Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Reviewed-by: Gwan-gyeong Mun Link: https://patchwork.freedesktop.org/patch/msgid/20201007195238.53955-3-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 10 ++- drivers/gpu/drm/i915/display/intel_psr.c | 117 +++++++++++++++++++++++++-- drivers/gpu/drm/i915/display/intel_psr.h | 10 ++- drivers/gpu/drm/i915/display/intel_sprite.c | 3 + 4 files changed, 131 insertions(+), 9 deletions(-) (limited to 'drivers/gpu/drm/i915/display/intel_psr.c') diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 19bed7a91192..7b8634eb674d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -11869,6 +11869,9 @@ static void i9xx_update_cursor(struct intel_plane *plane, if (INTEL_GEN(dev_priv) >= 9) skl_write_cursor_wm(plane, crtc_state); + if (!needs_modeset(crtc_state)) + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, 0); + if (plane->cursor.base != base || plane->cursor.size != fbc_ctl || plane->cursor.cntl != cntl) { @@ -12880,8 +12883,11 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, } - if (!mode_changed) - intel_psr2_sel_fetch_update(state, crtc); + if (!mode_changed) { + ret = intel_psr2_sel_fetch_update(state, crtc); + if (ret) + return ret; + } return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 02f74b0ddec1..a591a475f148 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1166,6 +1166,38 @@ static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) intel_psr_exit(dev_priv); } +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state, + int color_plane) +{ + struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + enum pipe pipe = plane->pipe; + u32 val; + + if (!crtc_state->enable_psr2_sel_fetch) + return; + + val = plane_state ? plane_state->ctl : 0; + val &= plane->id == PLANE_CURSOR ? val : PLANE_SEL_FETCH_CTL_ENABLE; + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), val); + if (!val || plane->id == PLANE_CURSOR) + return; + + val = plane_state->uapi.dst.y1 << 16 | plane_state->uapi.dst.x1; + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_POS(pipe, plane->id), val); + + val = plane_state->color_plane[color_plane].y << 16; + val |= plane_state->color_plane[color_plane].x; + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), + val); + + /* Sizes are 0 based */ + val = ((drm_rect_height(&plane_state->uapi.src) >> 16) - 1) << 16; + val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; + intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); +} + void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -1180,16 +1212,91 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st crtc_state->psr2_man_track_ctl); } -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, - struct intel_crtc *crtc) +static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state, + struct drm_rect *clip, bool full_update) +{ + u32 val = PSR2_MAN_TRK_CTL_ENABLE; + + if (full_update) { + val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; + goto exit; + } + + if (clip->y1 == -1) + goto exit; + + val |= PSR2_MAN_TRK_CTL_SF_PARTIAL_FRAME_UPDATE; + val |= PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(clip->y1 / 4 + 1); + val |= PSR2_MAN_TRK_CTL_SU_REGION_END_ADDR(DIV_ROUND_UP(clip->y2, 4) + 1); +exit: + crtc_state->psr2_man_track_ctl = val; +} + +static void clip_area_update(struct drm_rect *overlap_damage_area, + struct drm_rect *damage_area) +{ + if (overlap_damage_area->y1 == -1) { + overlap_damage_area->y1 = damage_area->y1; + overlap_damage_area->y2 = damage_area->y2; + return; + } + + if (damage_area->y1 < overlap_damage_area->y1) + overlap_damage_area->y1 = damage_area->y1; + + if (damage_area->y2 > overlap_damage_area->y2) + overlap_damage_area->y2 = damage_area->y2; +} + +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, + struct intel_crtc *crtc) { struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + struct intel_plane_state *new_plane_state, *old_plane_state; + struct drm_rect pipe_clip = { .y1 = -1 }; + struct intel_plane *plane; + bool full_update = false; + int i, ret; if (!crtc_state->enable_psr2_sel_fetch) - return; + return 0; + + ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); + if (ret) + return ret; + + for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state, + new_plane_state, i) { + struct drm_rect temp; + + if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc) + continue; - crtc_state->psr2_man_track_ctl = PSR2_MAN_TRK_CTL_ENABLE | - PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME; + /* + * TODO: Not clear how to handle planes with negative position, + * also planes are not updated if they have a negative X + * position so for now doing a full update in this cases + */ + if (new_plane_state->uapi.dst.y1 < 0 || + new_plane_state->uapi.dst.x1 < 0) { + full_update = true; + break; + } + + if (!new_plane_state->uapi.visible) + continue; + + /* + * For now doing a selective fetch in the whole plane area, + * optimizations will come in the future. + */ + temp.y1 = new_plane_state->uapi.dst.y1; + temp.y2 = new_plane_state->uapi.dst.y2; + clip_area_update(&pipe_clip, &temp); + } + + psr2_man_trk_ctl_calc(crtc_state, &pipe_clip, full_update); + return 0; } /** diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 6a83c8e682e6..3eca9dcec3c0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -15,6 +15,8 @@ struct intel_crtc_state; struct intel_dp; struct intel_crtc; struct intel_atomic_state; +struct intel_plane_state; +struct intel_plane; #define CAN_PSR(dev_priv) (HAS_PSR(dev_priv) && dev_priv->psr.sink_support) void intel_psr_init_dpcd(struct intel_dp *intel_dp); @@ -45,8 +47,12 @@ void intel_psr_atomic_check(struct drm_connector *connector, struct drm_connector_state *old_state, struct drm_connector_state *new_state); void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp); -void intel_psr2_sel_fetch_update(struct intel_atomic_state *state, - struct intel_crtc *crtc); +int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state); +void intel_psr2_program_plane_sel_fetch(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state, + const struct intel_plane_state *plane_state, + int color_plane); #endif /* __INTEL_PSR_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index af6a0ad9a43d..3ae7470c1b8b 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -731,6 +731,9 @@ skl_program_plane(struct intel_plane *plane, intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id), (plane_state->color_plane[1].y << 16) | plane_state->color_plane[1].x); + if (!drm_atomic_crtc_needs_modeset(&crtc_state->uapi)) + intel_psr2_program_plane_sel_fetch(plane, crtc_state, plane_state, color_plane); + /* * The control register self-arms if the plane was previously * disabled. Try to make the plane enable atomic by writing -- cgit From 71c1a4998320962f7b8362b2c5ee36610d49e8fb Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Fri, 2 Oct 2020 16:16:27 -0700 Subject: drm/i915/tgl/psr: Fix glitches when doing frontbuffer modifications MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Writes to CURSURFLIVE in TGL are causing IOMMU errors and visual glitches that are often reproduced when executing CPU intensive workloads while a eDP 4K panel is attached. Manually exiting PSR causes the frontbuffer to be updated without glitches and the IOMMU errors are also gone but this comes at the cost of less time with PSR active. So using this workaround until this issue is root caused and a better fix is found. The current code is already ready to enable PSR after this exit if there is not other frontbuffer modifications. Adding a new if block in psr_force_hw_tracking_exit() instead of reuse the else/gen8- block because the plan is to revert this workaround as soon as a better solution is found. Cc: Gwan-gyeong Mun Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Tested-by: Gwan-gyeong Mun Reviewed-by: Gwan-gyeong Mun Link: https://patchwork.freedesktop.org/patch/msgid/20201002231627.24528-1-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915/display/intel_psr.c') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a591a475f148..b2544102e7b1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1147,7 +1147,21 @@ void intel_psr_disable(struct intel_dp *intel_dp, static void psr_force_hw_tracking_exit(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 9) + if (IS_TIGERLAKE(dev_priv)) + /* + * Writes to CURSURFLIVE in TGL are causing IOMMU errors and + * visual glitches that are often reproduced when executing + * CPU intensive workloads while a eDP 4K panel is attached. + * + * Manually exiting PSR causes the frontbuffer to be updated + * without glitches and the IOMMU errors are also gone but + * this comes at the cost of less time with PSR active. + * + * So using this workaround until this issue is root caused + * and a better fix is found. + */ + intel_psr_exit(dev_priv); + else if (INTEL_GEN(dev_priv) >= 9) /* * Display WA #0884: skl+ * This documented WA for bxt can be safely applied -- cgit From 00e5deb5c4f5fe367311465e720e65cfa1178792 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 27 Oct 2020 18:09:28 +0200 Subject: drm/i915: Fix encoder lookup during PSR atomic check The atomic check hooks must look up the encoder to be used with a connector from the connector's atomic state, and not assume that it's the connector's current attached encoder. The latter one can change under the atomic check func, or can be unset yet as in the case of MST connectors. This fixes [ 7.940719] Oops: 0000 [#1] SMP NOPTI [ 7.944407] CPU: 2 PID: 143 Comm: kworker/2:2 Not tainted 5.6.0-1023-oem #23-Ubuntu [ 7.952102] Hardware name: Dell Inc. Latitude 7320/, BIOS 88.87.11 09/07/2020 [ 7.959278] Workqueue: events output_poll_execute [drm_kms_helper] [ 7.965511] RIP: 0010:intel_psr_atomic_check+0x37/0xa0 [i915] [ 7.971327] Code: 80 2d 06 00 00 20 74 42 80 b8 34 71 00 00 00 74 39 48 8b 72 08 48 85 f6 74 30 80 b8 f8 71 00 00 00 74 27 4c 8b 87 80 04 00 00 <41> 8b 78 78 83 ff 08 77 19 31 c9 83 ff 05 77 19 48 81 c1 20 01 00 [ 7.977541] input: PS/2 Generic Mouse as /devices/platform/i8042/serio1/input/input5 [ 7.990154] RSP: 0018:ffffb864c073fac8 EFLAGS: 00010202 [ 7.990155] RAX: ffff8c5d55ce0000 RBX: ffff8c5d54519000 RCX: 0000000000000000 [ 7.990155] RDX: ffff8c5d55cb30c0 RSI: ffff8c5d89a0c800 RDI: ffff8c5d55fcf800 [ 7.990156] RBP: ffffb864c073fac8 R08: 0000000000000000 R09: ffff8c5d55d9f3a0 [ 7.990156] R10: ffff8c5d55cb30c0 R11: 0000000000000009 R12: ffff8c5d55fcf800 [ 7.990156] R13: ffff8c5d55cb30c0 R14: ffff8c5d56989cc0 R15: ffff8c5d56989cc0 [ 7.990158] FS: 0000000000000000(0000) GS:ffff8c5d8e480000(0000) knlGS:0000000000000000 [ 8.047193] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 8.052970] CR2: 0000000000000078 CR3: 0000000856500005 CR4: 0000000000760ee0 [ 8.060137] PKRU: 55555554 [ 8.062867] Call Trace: [ 8.065361] intel_digital_connector_atomic_check+0x53/0x130 [i915] [ 8.071703] intel_dp_mst_atomic_check+0x5b/0x200 [i915] [ 8.077074] drm_atomic_helper_check_modeset+0x1db/0x790 [drm_kms_helper] [ 8.083942] intel_atomic_check+0x92/0xc50 [i915] [ 8.088705] ? drm_plane_check_pixel_format+0x4f/0xb0 [drm] [ 8.094345] ? drm_atomic_plane_check+0x7a/0x3a0 [drm] [ 8.099548] drm_atomic_check_only+0x2b1/0x450 [drm] [ 8.104573] drm_atomic_commit+0x18/0x50 [drm] [ 8.109070] drm_client_modeset_commit_atomic+0x1c9/0x200 [drm] [ 8.115056] drm_client_modeset_commit_force+0x55/0x160 [drm] [ 8.120866] drm_fb_helper_restore_fbdev_mode_unlocked+0x54/0xb0 [drm_kms_helper] [ 8.128415] drm_fb_helper_set_par+0x34/0x50 [drm_kms_helper] [ 8.134225] drm_fb_helper_hotplug_event.part.0+0xb4/0xe0 [drm_kms_helper] [ 8.141150] drm_fb_helper_hotplug_event+0x1c/0x30 [drm_kms_helper] [ 8.147481] intel_fbdev_output_poll_changed+0x6f/0xa0 [i915] [ 8.153287] drm_kms_helper_hotplug_event+0x2c/0x40 [drm_kms_helper] [ 8.159709] output_poll_execute+0x1aa/0x1c0 [drm_kms_helper] [ 8.165506] process_one_work+0x1e8/0x3b0 [ 8.169561] worker_thread+0x4d/0x400 [ 8.173249] kthread+0x104/0x140 [ 8.176515] ? process_one_work+0x3b0/0x3b0 [ 8.180726] ? kthread_park+0x90/0x90 [ 8.184416] ret_from_fork+0x1f/0x40 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/2361 References: https://gitlab.freedesktop.org/drm/intel/-/issues/2486 Reported-by: William Tseng Reported-by: Cooper Chiou Cc: Signed-off-by: Imre Deak Reviewed-by: Anshuman Gupta Link: https://patchwork.freedesktop.org/patch/msgid/20201027160928.3665377-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/i915/display/intel_psr.c') diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b2544102e7b1..1576c3722d0b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1884,7 +1884,7 @@ void intel_psr_atomic_check(struct drm_connector *connector, return; intel_connector = to_intel_connector(connector); - dig_port = enc_to_dig_port(intel_attached_encoder(intel_connector)); + dig_port = enc_to_dig_port(to_intel_encoder(new_state->best_encoder)); if (dev_priv->psr.dp != &dig_port->dp) return; -- cgit From 66186acbd94c4fdd43012a1f075ca381ada56150 Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Mon, 2 Nov 2020 14:10:48 -0800 Subject: drm/i915/display: Use initial_fastset_check() to compute and apply the initial PSR state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the previous approach to force compute the initial PSR state after i915 take over from firmware by the better and recently added initial_fastset_check() hook. Cc: Imre Deak Signed-off-by: José Roberto de Souza Reviewed-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20201102221048.104294-1-jose.souza@intel.com --- drivers/gpu/drm/i915/display/intel_atomic.c | 1 - drivers/gpu/drm/i915/display/intel_display.c | 2 -- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++ drivers/gpu/drm/i915/display/intel_psr.c | 41 ---------------------------- drivers/gpu/drm/i915/display/intel_psr.h | 4 --- drivers/gpu/drm/i915/i915_drv.h | 1 - 6 files changed, 6 insertions(+), 49 deletions(-) (limited to 'drivers/gpu/drm/i915/display/intel_psr.c') diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 86be032bcf96..63d8d6840655 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -133,7 +133,6 @@ int intel_digital_connector_atomic_check(struct drm_connector *conn, struct drm_crtc_state *crtc_state; intel_hdcp_atomic_check(conn, old_state, new_state); - intel_psr_atomic_check(conn, old_state, new_state); if (!new_state->crtc) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 19a4d81558c5..8c4687b19814 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -18373,8 +18373,6 @@ int intel_modeset_init(struct drm_i915_private *i915) intel_init_ipc(i915); - intel_psr_set_force_mode_changed(i915->psr.dp); - return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index cf09aca7607b..3b0dbda5919a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3778,6 +3778,12 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, return false; } + if (CAN_PSR(i915) && intel_dp_is_edp(intel_dp)) { + drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n"); + crtc_state->uapi.mode_changed = true; + return false; + } + return true; } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1576c3722d0b..b3631b722de3 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1024,8 +1024,6 @@ void intel_psr_enable(struct intel_dp *intel_dp, if (!CAN_PSR(dev_priv) || dev_priv->psr.dp != intel_dp) return; - dev_priv->psr.force_mode_changed = false; - if (!crtc_state->has_psr) return; @@ -1334,8 +1332,6 @@ void intel_psr_update(struct intel_dp *intel_dp, if (!CAN_PSR(dev_priv) || READ_ONCE(psr->dp) != intel_dp) return; - dev_priv->psr.force_mode_changed = false; - mutex_lock(&dev_priv->psr.lock); enable = crtc_state->has_psr; @@ -1869,40 +1865,3 @@ bool intel_psr_enabled(struct intel_dp *intel_dp) return ret; } - -void intel_psr_atomic_check(struct drm_connector *connector, - struct drm_connector_state *old_state, - struct drm_connector_state *new_state) -{ - struct drm_i915_private *dev_priv = to_i915(connector->dev); - struct intel_connector *intel_connector; - struct intel_digital_port *dig_port; - struct drm_crtc_state *crtc_state; - - if (!CAN_PSR(dev_priv) || !new_state->crtc || - !dev_priv->psr.force_mode_changed) - return; - - intel_connector = to_intel_connector(connector); - dig_port = enc_to_dig_port(to_intel_encoder(new_state->best_encoder)); - if (dev_priv->psr.dp != &dig_port->dp) - return; - - crtc_state = drm_atomic_get_new_crtc_state(new_state->state, - new_state->crtc); - crtc_state->mode_changed = true; -} - -void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp) -{ - struct drm_i915_private *dev_priv; - - if (!intel_dp) - return; - - dev_priv = dp_to_i915(intel_dp); - if (!CAN_PSR(dev_priv) || intel_dp != dev_priv->psr.dp) - return; - - dev_priv->psr.force_mode_changed = true; -} diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 3eca9dcec3c0..0a517978e8af 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -43,10 +43,6 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp); int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state, u32 *out_value); bool intel_psr_enabled(struct intel_dp *intel_dp); -void intel_psr_atomic_check(struct drm_connector *connector, - struct drm_connector_state *old_state, - struct drm_connector_state *new_state); -void intel_psr_set_force_mode_changed(struct intel_dp *intel_dp); int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, struct intel_crtc *crtc); void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d7765b31fbef..80940887d250 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -508,7 +508,6 @@ struct i915_psr { bool dc3co_enabled; u32 dc3co_exit_delay; struct delayed_work dc3co_work; - bool force_mode_changed; struct drm_dp_vsc_sdp vsc; }; -- cgit