From e371e19c10a264bd72c2ff1d21e2167b994710d1 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Thu, 18 Apr 2019 12:42:32 -0400 Subject: drm/amd/display: Disable cursor when offscreen in negative direction [Why] When x or y is negative we set the x and y values to 0 and compensate with a positive cursor hotspot in DM since DC expects positive cursor values. When x or y is less than or equal to the maximum cursor width or height the cursor hotspot is clamped so the hotspot doesn't exceed the cursor size: if (x < 0) { xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1); x = 0; } if (y < 0) { yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1); y = 0; } This incorrectly forces the cursor to be at least 1 pixel on the screen in either direction when x or y is sufficiently negative. [How] Just disable the cursor when it goes far enough off the screen in one of these directions. This fixes kms_cursor_crc@cursor-256x256-offscreen. Signed-off-by: Nicholas Kazlauskas Reviewed-by: Sun peng Li Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 995f9df66142..1e8b51d21fea 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4945,12 +4945,12 @@ static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, int x, y; int xorigin = 0, yorigin = 0; - if (!crtc || !plane->state->fb) { - position->enable = false; - position->x = 0; - position->y = 0; + position->enable = false; + position->x = 0; + position->y = 0; + + if (!crtc || !plane->state->fb) return 0; - } if ((plane->state->crtc_w > amdgpu_crtc->max_cursor_width) || (plane->state->crtc_h > amdgpu_crtc->max_cursor_height)) { @@ -4964,6 +4964,10 @@ static int get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, x = plane->state->crtc_x; y = plane->state->crtc_y; + if (x <= -amdgpu_crtc->max_cursor_width || + y <= -amdgpu_crtc->max_cursor_height) + return 0; + if (crtc->primary->state) { /* avivo cursor are offset into the total surface */ x += crtc->primary->state->src_x >> 16; -- cgit From 1894478ad1f8fd7366edc5cee49ee9caea0e3d52 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 25 Apr 2019 11:02:30 -0400 Subject: drm/amd/display: Fill plane attrs only for valid pxl format [Why] In fill_plane_buffer_attributes() we calculate chroma/luma assuming that the surface_pixel_format is always valid. If it's not the case, there's a risk of divide by zero error. [How] Check if format valid before calculating pixel format attributes Signed-off-by: Roman Li Reviewed-by: David Francis Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1e8b51d21fea..c6713432935e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2584,7 +2584,7 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, address->type = PLN_ADDR_TYPE_GRAPHICS; address->grph.addr.low_part = lower_32_bits(afb->address); address->grph.addr.high_part = upper_32_bits(afb->address); - } else { + } else if (format < SURFACE_PIXEL_FORMAT_INVALID) { uint64_t chroma_addr = afb->address + fb->offsets[1]; plane_size->video.luma_size.x = 0; -- cgit From a7669aff77649a34b0601aef87879095caed7a5f Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Mon, 29 Apr 2019 09:39:15 -0400 Subject: drm/amd/display: Don't load DMCU for Raven 1 (v2) [WHY] Some early Raven boards had a bad SBIOS that doesn't play nicely with the DMCU FW. We thought the issues were fixed by ignoring errors on DMCU load but that doesn't seem to be the case. We've still seen reports of users unable to boot their systems at all. [HOW] Disable DMCU load on Raven 1. Only load it for Raven 2 and Picasso. v2: Fix ifdef (Alex) Signed-off-by: Harry Wentland Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c6713432935e..8d53aced6c9f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -29,6 +29,7 @@ #include "dm_services_types.h" #include "dc.h" #include "dc/inc/core_types.h" +#include "dal_asic_id.h" #include "vid.h" #include "amdgpu.h" @@ -640,7 +641,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) static int load_dmcu_fw(struct amdgpu_device *adev) { - const char *fw_name_dmcu; + const char *fw_name_dmcu = NULL; int r; const struct dmcu_firmware_header_v1_0 *hdr; @@ -663,7 +664,14 @@ static int load_dmcu_fw(struct amdgpu_device *adev) case CHIP_VEGA20: return 0; case CHIP_RAVEN: - fw_name_dmcu = FIRMWARE_RAVEN_DMCU; +#if defined(CONFIG_DRM_AMD_DC_DCN1_01) + if (ASICREV_IS_PICASSO(adev->external_rev_id)) + fw_name_dmcu = FIRMWARE_RAVEN_DMCU; + else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) + fw_name_dmcu = FIRMWARE_RAVEN_DMCU; + else +#endif + return 0; break; default: DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); -- cgit From 1825fd34e8ed026911c6de6d7be7bd2d1ff8101a Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Wed, 22 May 2019 12:00:54 -0400 Subject: drm/amd/display: Switch the custom "max bpc" property to the DRM prop [Why] The custom "max bpc" property was added to limit color depth while the DRM one was still being merged. It's been a few kernel versions since then and this TODO was still sticking around. [How] Attach the DRM max bpc property to the connector and drop all of our custom property management. Set the max bpc to 8 by default since DRM defaults to the max in the range which would be 16 in this case. No behavioral changes are intended with this patch, it should just be a refactor. v2: Don't force 8bpc when no state is given Cc: Leo Li Cc: Harry Wentland Signed-off-by: Nicholas Kazlauskas Acked-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 2 -- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 29 ++++++++++------------- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 - 4 files changed, 12 insertions(+), 24 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index b083b219b1a9..30e6ad8a90bb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -631,10 +631,6 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev) amdgpu_dither_enum_list, sz); if (amdgpu_device_has_dc_support(adev)) { - adev->mode_info.max_bpc_property = - drm_property_create_range(adev->ddev, 0, "max bpc", 8, 16); - if (!adev->mode_info.max_bpc_property) - return -ENOMEM; adev->mode_info.abm_level_property = drm_property_create_range(adev->ddev, 0, "abm level", 0, 4); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 2e9e3db778c6..eb9975f4decb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -331,8 +331,6 @@ struct amdgpu_mode_info { struct drm_property *audio_property; /* FMT dithering */ struct drm_property *dither_property; - /* maximum number of bits per channel for monitor color */ - struct drm_property *max_bpc_property; /* Adaptive Backlight Modulation (power feature) */ struct drm_property *abm_level_property; /* hardcoded DFP edid from BIOS */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8d53aced6c9f..acb894ae6013 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2969,14 +2969,14 @@ static void update_stream_scaling_settings(const struct drm_display_mode *mode, static enum dc_color_depth convert_color_depth_from_display_info(const struct drm_connector *connector) { - struct dm_connector_state *dm_conn_state = - to_dm_connector_state(connector->state); uint32_t bpc = connector->display_info.bpc; - /* TODO: Remove this when there's support for max_bpc in drm */ - if (dm_conn_state && bpc > dm_conn_state->max_bpc) - /* Round down to nearest even number. */ - bpc = dm_conn_state->max_bpc - (dm_conn_state->max_bpc & 1); + /* TODO: Use passed in state instead of the current state. */ + if (connector->state) { + bpc = connector->state->max_bpc; + /* Round down to the nearest even number. */ + bpc = bpc - (bpc & 1); + } switch (bpc) { case 0: @@ -3618,9 +3618,6 @@ int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector, } else if (property == adev->mode_info.underscan_property) { dm_new_state->underscan_enable = val; ret = 0; - } else if (property == adev->mode_info.max_bpc_property) { - dm_new_state->max_bpc = val; - ret = 0; } else if (property == adev->mode_info.abm_level_property) { dm_new_state->abm_level = val; ret = 0; @@ -3666,9 +3663,6 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, } else if (property == adev->mode_info.underscan_property) { *val = dm_state->underscan_enable; ret = 0; - } else if (property == adev->mode_info.max_bpc_property) { - *val = dm_state->max_bpc; - ret = 0; } else if (property == adev->mode_info.abm_level_property) { *val = dm_state->abm_level; ret = 0; @@ -3725,7 +3719,6 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) state->underscan_enable = false; state->underscan_hborder = 0; state->underscan_vborder = 0; - state->max_bpc = 8; __drm_atomic_helper_connector_reset(connector, &state->base); } @@ -3751,7 +3744,6 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) new_state->underscan_enable = state->underscan_enable; new_state->underscan_hborder = state->underscan_hborder; new_state->underscan_vborder = state->underscan_vborder; - new_state->max_bpc = state->max_bpc; return &new_state->base; } @@ -4672,9 +4664,12 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_object_attach_property(&aconnector->base.base, adev->mode_info.underscan_vborder_property, 0); - drm_object_attach_property(&aconnector->base.base, - adev->mode_info.max_bpc_property, - 0); + + drm_connector_attach_max_bpc_property(&aconnector->base, 8, 16); + + /* This defaults to the max in the range, but we want 8bpc. */ + aconnector->base.state->max_bpc = 8; + aconnector->base.state->max_requested_bpc = 8; if (connector_type == DRM_MODE_CONNECTOR_eDP && dc_is_dmcu_initialized(adev->dm.dc)) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 978ff14a7d45..b0ce44422e90 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -304,7 +304,6 @@ struct dm_connector_state { enum amdgpu_rmx_type scaling; uint8_t underscan_vborder; uint8_t underscan_hborder; - uint8_t max_bpc; bool underscan_enable; bool freesync_capable; uint8_t abm_level; -- cgit From 42ba01fc30e6f84e7433879052474e716237ab33 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Wed, 22 May 2019 12:00:55 -0400 Subject: drm/amd/display: Use new connector state when getting color depth [Why] The current state on the connector is queried when getting the max bpc rather than the new state. This means that a new max bpc value can only currently take effect on the commit *after* it changes. The new state should be passed in instead. [How] Pass down the dm_state as drm state to where we do color depth lookup. The passed in state can still be NULL when called from amdgpu_dm_connector_mode_valid, so make sure that we have reasonable defaults in place. That should probably be addressed at some point. This change now (correctly) causes a modeset to occur when changing the max bpc for a connector. v2: Drop extra TODO. Cc: Leo Li Cc: Harry Wentland Signed-off-by: Nicholas Kazlauskas Acked-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 27 +++++++++++++---------- 1 file changed, 15 insertions(+), 12 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index acb894ae6013..340404f78034 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2967,13 +2967,13 @@ static void update_stream_scaling_settings(const struct drm_display_mode *mode, } static enum dc_color_depth -convert_color_depth_from_display_info(const struct drm_connector *connector) +convert_color_depth_from_display_info(const struct drm_connector *connector, + const struct drm_connector_state *state) { uint32_t bpc = connector->display_info.bpc; - /* TODO: Use passed in state instead of the current state. */ - if (connector->state) { - bpc = connector->state->max_bpc; + if (state) { + bpc = state->max_bpc; /* Round down to the nearest even number. */ bpc = bpc - (bpc & 1); } @@ -3094,11 +3094,12 @@ static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_ } -static void -fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, - const struct drm_display_mode *mode_in, - const struct drm_connector *connector, - const struct dc_stream_state *old_stream) +static void fill_stream_properties_from_drm_display_mode( + struct dc_stream_state *stream, + const struct drm_display_mode *mode_in, + const struct drm_connector *connector, + const struct drm_connector_state *connector_state, + const struct dc_stream_state *old_stream) { struct dc_crtc_timing *timing_out = &stream->timing; const struct drm_display_info *info = &connector->display_info; @@ -3121,7 +3122,7 @@ fill_stream_properties_from_drm_display_mode(struct dc_stream_state *stream, timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE; timing_out->display_color_depth = convert_color_depth_from_display_info( - connector); + connector, connector_state); timing_out->scan_type = SCANNING_TYPE_NODATA; timing_out->hdmi_vic = 0; @@ -3318,6 +3319,8 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, { struct drm_display_mode *preferred_mode = NULL; struct drm_connector *drm_connector; + const struct drm_connector_state *con_state = + dm_state ? &dm_state->base : NULL; struct dc_stream_state *stream = NULL; struct drm_display_mode mode = *drm_mode; bool native_mode_found = false; @@ -3390,10 +3393,10 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, */ if (!scale || mode_refresh != preferred_refresh) fill_stream_properties_from_drm_display_mode(stream, - &mode, &aconnector->base, NULL); + &mode, &aconnector->base, con_state, NULL); else fill_stream_properties_from_drm_display_mode(stream, - &mode, &aconnector->base, old_stream); + &mode, &aconnector->base, con_state, old_stream); update_stream_scaling_settings(&mode, dm_state, stream); -- cgit From f1e5e913028669c2bbac6664b8f01cb124349692 Mon Sep 17 00:00:00 2001 From: Yogesh Mohan Marimuthu Date: Fri, 17 May 2019 15:46:58 +0530 Subject: drm/amdgpu: sort probed modes before adding common modes [Why] There are monitors which can have more than one preferred mode set. There are chances in these monitors that if common modes are added in function amdgpu_dm_connector_add_common_modes(), these common modes can be calculated with different preferred mode than the one used in function decide_crtc_timing_for_drm_display_mode(). The preferred mode can be different because after common modes are added, the mode list is sorted and this changes the order of preferred modes in the list. The first mode in the list with preferred flag set is selected as preferred mode. Due to this the preferred mode selected varies. If same preferred mode is not selected in common mode calculation and crtc timing, then during mode set instead of setting preferred timing, common mode timing will be applied which can cause "out of range" message in the monitor with monitor blanking out. [How] Sort the modes before adding common modes. The same sorting function is called during common mode addition and deciding crtc timing. Signed-off-by: Yogesh Mohan Marimuthu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 340404f78034..c3e78039d1e6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4588,6 +4588,15 @@ static void amdgpu_dm_connector_ddc_get_modes(struct drm_connector *connector, amdgpu_dm_connector->num_modes = drm_add_edid_modes(connector, edid); + /* sorting the probed modes before calling function + * amdgpu_dm_get_native_mode() since EDID can have + * more than one preferred mode. The modes that are + * later in the probed mode list could be of higher + * and preferred resolution. For example, 3840x2160 + * resolution in base EDID preferred timing and 4096x2160 + * preferred resolution in DID extension block later. + */ + drm_mode_sort(&connector->probed_modes); amdgpu_dm_get_native_mode(connector); } else { amdgpu_dm_connector->num_modes = 0; -- cgit From c8bdf2b63e5b6b31b3b4826b8e87c0c2f6b650ff Mon Sep 17 00:00:00 2001 From: Emily Deng Date: Mon, 27 May 2019 11:12:51 +0800 Subject: drm/amdgpu: fix unload driver fail MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dc_destroy should be called amdgpu_cgs_destroy_device, as it will use cgs context to read or write registers. Signed-off-by: Emily Deng Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c3e78039d1e6..53b76e0de940 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -616,6 +616,10 @@ error: static void amdgpu_dm_fini(struct amdgpu_device *adev) { amdgpu_dm_destroy_drm_device(&adev->dm); + + /* DC Destroy TODO: Replace destroy DAL */ + if (adev->dm.dc) + dc_destroy(&adev->dm.dc); /* * TODO: pageflip, vlank interrupt * @@ -630,9 +634,6 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) mod_freesync_destroy(adev->dm.freesync_module); adev->dm.freesync_module = NULL; } - /* DC Destroy TODO: Replace destroy DAL */ - if (adev->dm.dc) - dc_destroy(&adev->dm.dc); mutex_destroy(&adev->dm.dc_lock); -- cgit From e63e2491ad92036e844230b6373ae07923552f6c Mon Sep 17 00:00:00 2001 From: Eryk Brol Date: Tue, 23 Apr 2019 11:53:52 -0400 Subject: drm/amd/display: Ensure DRR triggers in BP [Why] In the previous implementation DRR event sometimes came in during FP2 region which is a keep-out zone. This would cause the frame not to latch until the next frame which resulted in heavy flicker. To fix this we need to make sure that it triggers in the BP. [How] 1. Remove DRR programming during flip 2. Setup manual trigger for DRR event and trigger it after surface programming is complete Signed-off-by: Eryk Brol Reviewed-by: Aric Cyr Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 24 ++++++++++++---- drivers/gpu/drm/amd/display/dc/core/dc.c | 23 ++++++++++------ drivers/gpu/drm/amd/display/dc/dc_stream.h | 1 - .../drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c | 4 +-- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 32 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h | 31 +++++++++++++++++---- .../drm/amd/display/dc/inc/hw/timing_generator.h | 3 ++ 7 files changed, 96 insertions(+), 22 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 53b76e0de940..64dff3fc1f7b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5127,6 +5127,11 @@ static void update_freesync_state_on_stream( amdgpu_dm_vrr_active(new_crtc_state)) { mod_freesync_handle_v_update(dm->freesync_module, new_stream, &vrr_params); + + /* Need to call this before the frame ends. */ + dc_stream_adjust_vmin_vmax(dm->dc, + new_crtc_state->stream, + &vrr_params.adjust); } } @@ -5465,11 +5470,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, } if (acrtc_state->stream) { - - if (acrtc_state->freesync_timing_changed) - bundle->stream_update.adjust = - &acrtc_state->stream->adjust; - if (acrtc_state->freesync_vrr_info_changed) bundle->stream_update.vrr_infopacket = &acrtc_state->stream->vrr_infopacket; @@ -5490,6 +5490,20 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) bundle->stream_update.abm_level = &acrtc_state->abm_level; + /* + * If FreeSync state on the stream has changed then we need to + * re-adjust the min/max bounds now that DC doesn't handle this + * as part of commit. + */ + if (amdgpu_dm_vrr_active(dm_old_crtc_state) != + amdgpu_dm_vrr_active(acrtc_state)) { + spin_lock_irqsave(&pcrtc->dev->event_lock, flags); + dc_stream_adjust_vmin_vmax( + dm->dc, acrtc_state->stream, + &acrtc_state->vrr_params.adjust); + spin_unlock_irqrestore(&pcrtc->dev->event_lock, flags); + } + mutex_lock(&dm->dc_lock); dc_commit_updates_for_stream(dm->dc, bundle->surface_updates, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 79c3a372584f..5012b6755dc8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -263,7 +263,7 @@ bool dc_stream_adjust_vmin_vmax(struct dc *dc, for (i = 0; i < MAX_PIPES; i++) { struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i]; - if (pipe->stream == stream && pipe->stream_res.stream_enc) { + if (pipe->stream == stream && pipe->stream_res.tg) { pipe->stream->adjust = *adjust; dc->hwss.set_drr(&pipe, 1, @@ -1745,13 +1745,6 @@ static void commit_planes_do_stream_update(struct dc *dc, pipe_ctx->stream && pipe_ctx->stream == stream) { - /* Fast update*/ - // VRR program can be done as part of FAST UPDATE - if (stream_update->adjust) - dc->hwss.set_drr(&pipe_ctx, 1, - stream_update->adjust->v_total_min, - stream_update->adjust->v_total_max); - if (stream_update->periodic_interrupt0 && dc->hwss.setup_periodic_interrupt) dc->hwss.setup_periodic_interrupt(pipe_ctx, VLINE0); @@ -1909,6 +1902,20 @@ static void commit_planes_for_stream(struct dc *dc, dc->hwss.pipe_control_lock(dc, top_pipe_to_program, false); } + + // Fire manual trigger + for (i = 0; i < dc->res_pool->pipe_count; i++) { + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->top_pipe || + !pipe_ctx->stream || + pipe_ctx->stream != stream || + !srf_updates[i].flip_addr) + continue; + + if (pipe_ctx->stream_res.tg->funcs->program_manual_trigger) + pipe_ctx->stream_res.tg->funcs->program_manual_trigger(pipe_ctx->stream_res.tg); + } } void dc_commit_updates_for_stream(struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 189bdab929a5..4da138ded8b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -172,7 +172,6 @@ struct dc_stream_update { struct periodic_interrupt_config *periodic_interrupt0; struct periodic_interrupt_config *periodic_interrupt1; - struct dc_crtc_timing_adjust *adjust; struct dc_info_packet *vrr_infopacket; struct dc_info_packet *vsc_infopacket; struct dc_info_packet *vsp_infopacket; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c index 7ee3c60cdc18..b5ca1764e2a2 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c @@ -2506,8 +2506,8 @@ static void set_drr(struct pipe_ctx **pipe_ctx, { int i = 0; struct drr_params params = {0}; - // DRR should set trigger event to monitor surface update event - unsigned int event_triggers = 0x80; + // DRR set trigger event mapped to OTG_TRIG_A (bit 11) for manual control flow + unsigned int event_triggers = 0x800; params.vertical_total_max = vmax; params.vertical_total_min = vmin; diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c index 533b0f3cf6c3..e4b850a2d31f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c @@ -791,6 +791,32 @@ void optc1_set_static_screen_control( OTG_STATIC_SCREEN_FRAME_COUNT, 2); } +void optc1_setup_manual_trigger(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_SET(OTG_GLOBAL_CONTROL2, 0, + MANUAL_FLOW_CONTROL_SEL, optc->inst); + + REG_SET_8(OTG_TRIGA_CNTL, 0, + OTG_TRIGA_SOURCE_SELECT, 22, + OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst, + OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1, + OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0, + OTG_TRIGA_POLARITY_SELECT, 0, + OTG_TRIGA_FREQUENCY_SELECT, 0, + OTG_TRIGA_DELAY, 0, + OTG_TRIGA_CLEAR, 1); +} + +void optc1_program_manual_trigger(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + + REG_SET(OTG_MANUAL_FLOW_CONTROL, 0, + MANUAL_FLOW_CONTROL, 1); +} + /** ***************************************************************************** @@ -823,6 +849,10 @@ void optc1_set_drr( OTG_FORCE_LOCK_ON_EVENT, 0, OTG_SET_V_TOTAL_MIN_MASK_EN, 0, OTG_SET_V_TOTAL_MIN_MASK, 0); + + // Setup manual flow control for EOF via TRIG_A + optc->funcs->setup_manual_trigger(optc); + } else { REG_UPDATE_4(OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, 0, @@ -1458,6 +1488,8 @@ static const struct timing_generator_funcs dcn10_tg_funcs = { .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, .set_vtg_params = optc1_set_vtg_params, + .program_manual_trigger = optc1_program_manual_trigger, + .setup_manual_trigger = optc1_setup_manual_trigger }; void dcn10_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h index 70fd56fa56c5..444c56c8104f 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h @@ -85,13 +85,17 @@ SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ - SR(GSL_SOURCE_SELECT) + SR(GSL_SOURCE_SELECT),\ + SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ + SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst) + #define TG_COMMON_REG_LIST_DCN1_0(inst) \ TG_COMMON_REG_LIST_DCN(inst),\ SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\ SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\ - SRI(OTG_TEST_PATTERN_COLOR, OTG, inst) + SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\ + SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst) struct dcn_optc_registers { @@ -125,6 +129,8 @@ struct dcn_optc_registers { uint32_t OTG_V_TOTAL_MIN; uint32_t OTG_V_TOTAL_CONTROL; uint32_t OTG_TRIGA_CNTL; + uint32_t OTG_TRIGA_MANUAL_TRIG; + uint32_t OTG_MANUAL_FLOW_CONTROL; uint32_t OTG_FORCE_COUNT_NOW_CNTL; uint32_t OTG_STATIC_SCREEN_CONTROL; uint32_t OTG_STATUS_FRAME_COUNT; @@ -215,6 +221,11 @@ struct dcn_optc_registers { SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ + SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ + SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ @@ -271,8 +282,8 @@ struct dcn_optc_registers { SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ - SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh) - + SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ + SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ @@ -287,7 +298,8 @@ struct dcn_optc_registers { SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\ SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\ SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\ - SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh) + SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\ + SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\ #define TG_REG_FIELD_LIST_DCN1_0(type) \ type VSTARTUP_START;\ @@ -343,6 +355,11 @@ struct dcn_optc_registers { type OTG_TRIGA_SOURCE_PIPE_SELECT;\ type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\ type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\ + type OTG_TRIGA_POLARITY_SELECT;\ + type OTG_TRIGA_FREQUENCY_SELECT;\ + type OTG_TRIGA_DELAY;\ + type OTG_TRIGA_CLEAR;\ + type OTG_TRIGA_MANUAL_TRIG;\ type OTG_STATIC_SCREEN_EVENT_MASK;\ type OTG_STATIC_SCREEN_FRAME_COUNT;\ type OTG_FRAME_COUNT;\ @@ -421,7 +438,9 @@ struct dcn_optc_registers { type OTG_CRC0_WINDOWB_Y_END;\ type GSL0_READY_SOURCE_SEL;\ type GSL1_READY_SOURCE_SEL;\ - type GSL2_READY_SOURCE_SEL; + type GSL2_READY_SOURCE_SEL;\ + type MANUAL_FLOW_CONTROL;\ + type MANUAL_FLOW_CONTROL_SEL; #define TG_REG_FIELD_LIST(type) \ diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 0b8c6896581f..a89d0cf59cca 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -238,6 +238,9 @@ struct timing_generator_funcs { bool (*get_crc)(struct timing_generator *tg, uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); + void (*program_manual_trigger)(struct timing_generator *optc); + void (*setup_manual_trigger)(struct timing_generator *optc); + void (*set_vtg_params)(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); }; -- cgit From 7316c4ad299663a16ca9ce13e5e817b4ca760809 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Wed, 1 May 2019 10:26:09 -0400 Subject: drm/amd/display: Reset planes for color management changes [Why] For commits with allow_modeset=false and CRTC degamma changes the planes aren't reset. This results in incorrect rendering. [How] Reset the planes when color management has changed on the CRTC. Technically this will include regamma changes as well, but it doesn't really after legacy userspace since those commit with allow_modeset=true. Signed-off-by: Nicholas Kazlauskas Reviewed-by: Harry Wentland Acked-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 64dff3fc1f7b..95d5966479e9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6354,6 +6354,10 @@ static bool should_reset_plane(struct drm_atomic_state *state, if (!new_crtc_state) return true; + /* CRTC Degamma changes currently require us to recreate planes. */ + if (new_crtc_state->color_mgmt_changed) + return true; + if (drm_atomic_crtc_needs_modeset(new_crtc_state)) return true; -- cgit From 526c654a8a0641d4289bf65effde4d6095bd8384 Mon Sep 17 00:00:00 2001 From: Emily Deng Date: Fri, 31 May 2019 17:35:27 +0800 Subject: drm/amdgpu/display: Fix reload driver error Issue: Will have follow error when reload driver: [ 3986.567739] sysfs: cannot create duplicate filename '/devices/pci0000:00/0000:00:07.0/drm_dp_aux_dev' [ 3986.567743] CPU: 6 PID: 1767 Comm: modprobe Tainted: G OE 5.0.0-rc1-custom #1 [ 3986.567745] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 3986.567746] Call Trace: ...... [ 3986.567808] drm_dp_aux_register_devnode+0xdc/0x140 [drm_kms_helper] ...... [ 3986.569081] kobject_add_internal failed for drm_dp_aux_dev with -EEXIST, don't try to register things with the same name in the same directory. Reproduce sequences: 1.modprobe amdgpu 2.modprobe -r amdgpu 3.modprobe amdgpu Root cause: When unload driver, it doesn't unregister aux. v2: Don't use has_aux Signed-off-by: Emily Deng Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 95d5966479e9..d3e7755b86bf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3675,6 +3675,13 @@ int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector, return ret; } +static void amdgpu_dm_connector_unregister(struct drm_connector *connector) +{ + struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector); + + drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); +} + static void amdgpu_dm_connector_destroy(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -3703,6 +3710,11 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux); drm_connector_unregister(connector); drm_connector_cleanup(connector); + if (aconnector->i2c) { + i2c_del_adapter(&aconnector->i2c->base); + kfree(aconnector->i2c); + } + kfree(connector); } @@ -3760,7 +3772,8 @@ static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, .atomic_set_property = amdgpu_dm_connector_atomic_set_property, - .atomic_get_property = amdgpu_dm_connector_atomic_get_property + .atomic_get_property = amdgpu_dm_connector_atomic_get_property, + .early_unregister = amdgpu_dm_connector_unregister }; static int get_modes(struct drm_connector *connector) -- cgit From 0f257b09531b47baa8dd5bb4aa213a602f1f308c Mon Sep 17 00:00:00 2001 From: Chunming Zhou Date: Tue, 7 May 2019 19:45:31 +0800 Subject: drm/amd/display: use ttm_eu_reserve_buffers instead of amdgpu_bo_reserve v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add ticket for display bo, so that it can preempt busy bo. v2: fix stupid rebase error Signed-off-by: Chunming Zhou Reviewed-by: Christian König Tested-by: Pierre-Eric Pelloux-Prayer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d3e7755b86bf..33e39888211c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4107,6 +4107,9 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, struct amdgpu_device *adev; struct amdgpu_bo *rbo; struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old; + struct list_head list; + struct ttm_validate_buffer tv; + struct ww_acquire_ctx ticket; uint64_t tiling_flags; uint32_t domain; int r; @@ -4123,9 +4126,17 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, obj = new_state->fb->obj[0]; rbo = gem_to_amdgpu_bo(obj); adev = amdgpu_ttm_adev(rbo->tbo.bdev); - r = amdgpu_bo_reserve(rbo, false); - if (unlikely(r != 0)) + INIT_LIST_HEAD(&list); + + tv.bo = &rbo->tbo; + tv.num_shared = 1; + list_add(&tv.head, &list); + + r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true); + if (r) { + dev_err(adev->dev, "fail to reserve bo (%d)\n", r); return r; + } if (plane->type != DRM_PLANE_TYPE_CURSOR) domain = amdgpu_display_supported_domains(adev); @@ -4136,21 +4147,21 @@ static int dm_plane_helper_prepare_fb(struct drm_plane *plane, if (unlikely(r != 0)) { if (r != -ERESTARTSYS) DRM_ERROR("Failed to pin framebuffer with error %d\n", r); - amdgpu_bo_unreserve(rbo); + ttm_eu_backoff_reservation(&ticket, &list); return r; } r = amdgpu_ttm_alloc_gart(&rbo->tbo); if (unlikely(r != 0)) { amdgpu_bo_unpin(rbo); - amdgpu_bo_unreserve(rbo); + ttm_eu_backoff_reservation(&ticket, &list); DRM_ERROR("%p bind failed\n", rbo); return r; } amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); - amdgpu_bo_unreserve(rbo); + ttm_eu_backoff_reservation(&ticket, &list); afb->address = amdgpu_bo_gpu_offset(rbo); -- cgit From 88694af9e4d1feaf635c23844833960f8958af78 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 28 May 2019 15:08:35 -0400 Subject: drm/amd/display: Expose HDR output metadata for supported connectors [Why] For userspace to send static HDR metadata to the display we need to attach the property on the connector and send it to DC. [How] The property is attached to HDMI and DP connectors. Since the metadata isn't actually available when creating the connector this isn't a property we can dynamically support based on the extension block being available or not. When the HDR metadata is changed a modeset will be forced for now. We need to switch from 8bpc to 10bpc in most cases anyway, and we want to fully exit HDR mode when userspace gives us a NULL metadata, so this isn't completely unnecessary. The requirement can later be reduced to just entering and exiting HDR or switching max bpc. Cc: Harry Wentland Signed-off-by: Nicholas Kazlauskas Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Link: https://patchwork.freedesktop.org/patch/msgid/20190528190836.10738-2-nicholas.kazlauskas@amd.com --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 125 ++++++++++++++++++++++ 1 file changed, 125 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 995f9df66142..eb31acca7ed6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3871,6 +3871,121 @@ fail: return result; } +static int fill_hdr_info_packet(const struct drm_connector_state *state, + struct dc_info_packet *out) +{ + struct hdmi_drm_infoframe frame; + unsigned char buf[30]; /* 26 + 4 */ + ssize_t len; + int ret, i; + + memset(out, 0, sizeof(*out)); + + if (!state->hdr_output_metadata) + return 0; + + ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state); + if (ret) + return ret; + + len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf)); + if (len < 0) + return (int)len; + + /* Static metadata is a fixed 26 bytes + 4 byte header. */ + if (len != 30) + return -EINVAL; + + /* Prepare the infopacket for DC. */ + switch (state->connector->connector_type) { + case DRM_MODE_CONNECTOR_HDMIA: + out->hb0 = 0x87; /* type */ + out->hb1 = 0x01; /* version */ + out->hb2 = 0x1A; /* length */ + out->sb[0] = buf[3]; /* checksum */ + i = 1; + break; + + case DRM_MODE_CONNECTOR_DisplayPort: + case DRM_MODE_CONNECTOR_eDP: + out->hb0 = 0x00; /* sdp id, zero */ + out->hb1 = 0x87; /* type */ + out->hb2 = 0x1D; /* payload len - 1 */ + out->hb3 = (0x13 << 2); /* sdp version */ + out->sb[0] = 0x01; /* version */ + out->sb[1] = 0x1A; /* length */ + i = 2; + break; + + default: + return -EINVAL; + } + + memcpy(&out->sb[i], &buf[4], 26); + out->valid = true; + + print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb, + sizeof(out->sb), false); + + return 0; +} + +static bool +is_hdr_metadata_different(const struct drm_connector_state *old_state, + const struct drm_connector_state *new_state) +{ + struct drm_property_blob *old_blob = old_state->hdr_output_metadata; + struct drm_property_blob *new_blob = new_state->hdr_output_metadata; + + if (old_blob != new_blob) { + if (old_blob && new_blob && + old_blob->length == new_blob->length) + return memcmp(old_blob->data, new_blob->data, + old_blob->length); + + return true; + } + + return false; +} + +static int +amdgpu_dm_connector_atomic_check(struct drm_connector *conn, + struct drm_connector_state *new_con_state) +{ + struct drm_atomic_state *state = new_con_state->state; + struct drm_connector_state *old_con_state = + drm_atomic_get_old_connector_state(state, conn); + struct drm_crtc *crtc = new_con_state->crtc; + struct drm_crtc_state *new_crtc_state; + int ret; + + if (!crtc) + return 0; + + if (is_hdr_metadata_different(old_con_state, new_con_state)) { + struct dc_info_packet hdr_infopacket; + + ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket); + if (ret) + return ret; + + new_crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(new_crtc_state)) + return PTR_ERR(new_crtc_state); + + /* + * DC considers the stream backends changed if the + * static metadata changes. Forcing the modeset also + * gives a simple way for userspace to switch from + * 8bpc to 10bpc when setting the metadata. + */ + new_crtc_state->mode_changed = true; + } + + return 0; +} + static const struct drm_connector_helper_funcs amdgpu_dm_connector_helper_funcs = { /* @@ -3881,6 +3996,7 @@ amdgpu_dm_connector_helper_funcs = { */ .get_modes = get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, + .atomic_check = amdgpu_dm_connector_atomic_check, }; static void dm_crtc_helper_disable(struct drm_crtc *crtc) @@ -4677,6 +4793,10 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, if (connector_type == DRM_MODE_CONNECTOR_HDMIA || connector_type == DRM_MODE_CONNECTOR_DisplayPort || connector_type == DRM_MODE_CONNECTOR_eDP) { + drm_object_attach_property( + &aconnector->base.base, + dm->ddev->mode_config.hdr_output_metadata_property, 0); + drm_connector_attach_vrr_capable_property( &aconnector->base); } @@ -6141,6 +6261,11 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; + ret = fill_hdr_info_packet(drm_new_conn_state, + &new_stream->hdr_static_metadata); + if (ret) + goto fail; + if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { new_crtc_state->mode_changed = false; -- cgit From b232d4ed92eafb0d31adc01ee7a86c1309394418 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 28 May 2019 15:08:36 -0400 Subject: drm/amd/display: Only force modesets when toggling HDR [Why] We can issue HDR static metadata as part of stream updates for non-modesets as long as we force a modeset when entering or exiting HDR. This avoids unnecessary blanking for simple metadata updates. [How] When changing scaling and abm for the stream also check if HDR has changed and send the stream update. This will only happen in non-modeset cases. Cc: Harry Wentland Signed-off-by: Nicholas Kazlauskas Signed-off-by: Harry Wentland Reviewed-by: Harry Wentland Link: https://patchwork.freedesktop.org/patch/msgid/20190528190836.10738-3-nicholas.kazlauskas@amd.com --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 34 +++++++++++++++++++---- 1 file changed, 28 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index eb31acca7ed6..443b13ec268d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3978,9 +3978,16 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, * DC considers the stream backends changed if the * static metadata changes. Forcing the modeset also * gives a simple way for userspace to switch from - * 8bpc to 10bpc when setting the metadata. + * 8bpc to 10bpc when setting the metadata to enter + * or exit HDR. + * + * Changing the static metadata after it's been + * set is permissible, however. So only force a + * modeset if we're entering or exiting HDR. */ - new_crtc_state->mode_changed = true; + new_crtc_state->mode_changed = + !old_con_state->hdr_output_metadata || + !new_con_state->hdr_output_metadata; } return 0; @@ -5881,7 +5888,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); struct dc_surface_update dummy_updates[MAX_SURFACES]; struct dc_stream_update stream_update; + struct dc_info_packet hdr_packet; struct dc_stream_status *status = NULL; + bool abm_changed, hdr_changed, scaling_changed; memset(&dummy_updates, 0, sizeof(dummy_updates)); memset(&stream_update, 0, sizeof(stream_update)); @@ -5898,11 +5907,19 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); - if (!is_scaling_state_different(dm_new_con_state, dm_old_con_state) && - (dm_new_crtc_state->abm_level == dm_old_crtc_state->abm_level)) + scaling_changed = is_scaling_state_different(dm_new_con_state, + dm_old_con_state); + + abm_changed = dm_new_crtc_state->abm_level != + dm_old_crtc_state->abm_level; + + hdr_changed = + is_hdr_metadata_different(old_con_state, new_con_state); + + if (!scaling_changed && !abm_changed && !hdr_changed) continue; - if (is_scaling_state_different(dm_new_con_state, dm_old_con_state)) { + if (scaling_changed) { update_stream_scaling_settings(&dm_new_con_state->base.crtc->mode, dm_new_con_state, (struct dc_stream_state *)dm_new_crtc_state->stream); @@ -5910,12 +5927,17 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) stream_update.dst = dm_new_crtc_state->stream->dst; } - if (dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level) { + if (abm_changed) { dm_new_crtc_state->stream->abm_level = dm_new_crtc_state->abm_level; stream_update.abm_level = &dm_new_crtc_state->abm_level; } + if (hdr_changed) { + fill_hdr_info_packet(new_con_state, &hdr_packet); + stream_update.hdr_static_metadata = &hdr_packet; + } + status = dc_stream_get_status(dm_new_crtc_state->stream); WARN_ON(!status); WARN_ON(!status->plane_count); -- cgit From 621b325aa8b2c3d3ec9ef8a95d5581e74d5568f2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 31 May 2019 11:34:57 -0500 Subject: drm/amdgpu/display: Drop some new CONFIG_DRM_AMD_DC_DCN1_01 guards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These got added back by subsequent merges accidently. Reviewed-by: Harry Wentland Reviewed-by: Nicholas Kazlauskas Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 -- drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 4 ---- 2 files changed, 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 33e39888211c..b5a5cfae7ba1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -665,13 +665,11 @@ static int load_dmcu_fw(struct amdgpu_device *adev) case CHIP_VEGA20: return 0; case CHIP_RAVEN: -#if defined(CONFIG_DRM_AMD_DC_DCN1_01) if (ASICREV_IS_PICASSO(adev->external_rev_id)) fw_name_dmcu = FIRMWARE_RAVEN_DMCU; else if (ASICREV_IS_RAVEN2(adev->external_rev_id)) fw_name_dmcu = FIRMWARE_RAVEN_DMCU; else -#endif return 0; break; default: diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index 08b27c775cd4..eb2204d42337 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -105,14 +105,10 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p #if defined(CONFIG_DRM_AMD_DC_DCN1_0) case FAMILY_RV: - -#if defined(CONFIG_DRM_AMD_DC_DCN1_01) if (ASICREV_IS_RAVEN2(asic_id.hw_internal_rev)) { rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); break; } -#endif /* DCN1_01 */ - if (ASICREV_IS_RAVEN(asic_id.hw_internal_rev) || ASICREV_IS_PICASSO(asic_id.hw_internal_rev)) { rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); -- cgit From 09d21852a6f3bd8f96c0eb2d7bd9a3b8706f8bcd Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Mon, 10 Jun 2019 00:07:55 +0200 Subject: drm/amd: drop use of drmP.h in display/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop all uses of drmP.h in drm/amd/display/. Fix fallout. Signed-off-by: Sam Ravnborg Reviewed-by: Alex Deucher Cc: "Christian König" Cc: "David (ChunMing) Zhou" Cc: David Airlie Cc: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-9-sam@ravnborg.org --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 1 - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 2 -- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c | 1 - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c | 1 - 5 files changed, 3 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 443b13ec268d..3a723e553a19 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -53,15 +53,17 @@ #include #include #include +#include #include -#include #include #include #include #include #include +#include #include +#include #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "ivsrcid/irqsrcs_dcn_1_0.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index e6cd67342df8..97b2c3b16bef 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -28,7 +28,6 @@ #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index fd22b4474dbf..1b59d3d42f7b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -23,8 +23,6 @@ * */ -#include - #include "dm_services_types.h" #include "dc.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c index 350e7a620d45..b37e8c9653e1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c @@ -24,7 +24,6 @@ #include #include -#include #include #include #include "dm_services.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c index d915e8c8769b..022da5d45d4d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c @@ -26,7 +26,6 @@ #include #include -#include #include #include #include "dm_services.h" -- cgit From 7e93094945016492f6cb3660b2960d4b027eab51 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 11 Jun 2019 11:54:05 -0500 Subject: drm/amd/display: Don't set mode_changed=false if the stream was removed [Why] When switching from vt to desktop with EDID emulation we can receive an atomic commit such that we have a crtc where mode_changed = true. During the dm_update_crtc_state disable pass we remove the stream from the context and free it on the dm_new_crtc_state. During the enable pass we compare the new provisional stream to the dm_old_crtc_state->stream and determine that the stream is unchanged and no scaling has been changed. Following this, new_crtc_state->mode_changed is then set to false. The connectors haven't changed and the CRTC active state hasn't changed so drm_atomic_crtc_needs_modeset returns false, so we jump to skip_modeset and we hit: BUG_ON(dm_new_crtc_state->stream == NULL); ...since the old stream is gone from the context and the new stream is also still NULL. [How] Ensure that we still a stream to reuse before checking if we can reuse the old stream without a full modeset. Signed-off-by: Nicholas Kazlauskas Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 86308d7b5b3f..d8947fe5117c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6344,7 +6344,17 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, if (ret) goto fail; - if (dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && + /* + * If we already removed the old stream from the context + * (and set the new stream to NULL) then we can't reuse + * the old stream even if the stream and scaling are unchanged. + * We'll hit the BUG_ON and black screen. + * + * TODO: Refactor this function to allow this check to work + * in all conditions. + */ + if (dm_new_crtc_state->stream && + dc_is_stream_unchanged(new_stream, dm_old_crtc_state->stream) && dc_is_stream_scaling_unchanged(new_stream, dm_old_crtc_state->stream)) { new_crtc_state->mode_changed = false; DRM_DEBUG_DRIVER("Mode change not required, setting mode_changed to %d", -- cgit From f04bee34d6e35df26cbb2d65e801adfd0d8fe20d Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 4 Jun 2019 15:21:14 -0400 Subject: drm/amd/display: Always allocate initial connector state state [Why] Unlike our regular connectors, MST connectors don't start off with an initial connector state. This causes a NULL pointer dereference to occur when attaching the bpc property since it tries to modify the connector state. We need an initial connector state on the connector to avoid the crash. [How] Use our reset helper to allocate an initial state and reset the values to their defaults. We were already doing this before, just not for MST connectors. Signed-off-by: Nicholas Kazlauskas Reviewed-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d8947fe5117c..d3c39ff6d7e2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4778,6 +4778,13 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, { struct amdgpu_device *adev = dm->ddev->dev_private; + /* + * Some of the properties below require access to state, like bpc. + * Allocate some default initial connector state with our reset helper. + */ + if (aconnector->base.funcs->reset) + aconnector->base.funcs->reset(&aconnector->base); + aconnector->connector_id = link_index; aconnector->dc_link = link; aconnector->base.interlace_allowed = false; @@ -4967,9 +4974,6 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, &aconnector->base, &amdgpu_dm_connector_helper_funcs); - if (aconnector->base.funcs->reset) - aconnector->base.funcs->reset(&aconnector->base); - amdgpu_dm_connector_init_helper( dm, aconnector, -- cgit From 01933ba42d3d9fd0917573a752b81267ec231849 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Wed, 5 Jun 2019 12:33:59 -0400 Subject: drm/amd/display: Use current connector state if NULL when checking bpc [Why] The old logic for checking which output depth to use relied on using the current connector state rather than the new proposed state. This was a problem when performing atomic commits since we weren't verifying it against the incoming max_requested_bpc. But switching this to only use the new state and not the current state breaks filtering modes - it'll always assume that the maximum bpc supported by the display is in use, which will cause certain modes like 1440p@144Hz to be filtered even when using 8bpc. [How] Still use the connector->state if we aren't passed an explicit state. This will respect the max_bpc the user currently has when filtering modes. Also remember to reset the default max_requested_bpc to 8 whenever connector reset is called to retain old behavior when using the new property. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110845 Signed-off-by: Nicholas Kazlauskas Acked-by: Alex Deucher Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d3c39ff6d7e2..5c83c441877a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2971,6 +2971,9 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, { uint32_t bpc = connector->display_info.bpc; + if (!state) + state = connector->state; + if (state) { bpc = state->max_bpc; /* Round down to the nearest even number. */ @@ -3733,6 +3736,7 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) state->underscan_enable = false; state->underscan_hborder = 0; state->underscan_vborder = 0; + state->base.max_requested_bpc = 8; __drm_atomic_helper_connector_reset(connector, &state->base); } -- cgit From 37fb6e8a96fbc9c809c58f9490267ffe7101ac33 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Fri, 7 Jun 2019 11:16:55 -0400 Subject: drm/amd/display: Enable fast plane updates when state->allow_modeset = true [Why] Whenever the a modeset is allowed (but not neccessarily required) we currently recreate all the planes in the state. Most IGT tests and legacy IOCTLs create atomic commits with this flag set, so the pipes are often unnecessarily reprogrammed. Poor performance and stuttering can occur when many of these commits are frequently issued. This flag was needed when the appropriate conditions for checking whether the planes needed a reset were not in place, but should_reset_plane should cover everything needed now. [How] Drop the check for state->allow_modeset in should_reset_plane. All planes on a CRTC should reset in the following conditions: - The CRTC needs a modeset - The CRTC degamma changes - Planes are added or removed to the CRTC These conditions are all covered in should_reset_plane. We still can't drop the format change check in should_reset_plane since fill_dc_plane_info_and_addr isn't called when validating the state, so we can't tell if a FULL update is needed or not. Signed-off-by: Nicholas Kazlauskas Reviewed-by: David Francis Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 -------- 1 file changed, 8 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5c83c441877a..f09407162d41 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6519,14 +6519,6 @@ static bool should_reset_plane(struct drm_atomic_state *state, struct drm_crtc_state *new_crtc_state; int i; - /* - * TODO: Remove this hack once the checks below are sufficient - * enough to determine when we need to reset all the planes on - * the stream. - */ - if (state->allow_modeset) - return true; - /* Exit early if we know that we're adding or removing the plane. */ if (old_plane_state->crtc != new_plane_state->crtc) return true; -- cgit From c3e50f89006cca9c422c9b3cf83c6dd84bc91f52 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Thu, 6 Jun 2019 08:53:12 -0400 Subject: drm/amd/display: Set default ABM level to module parameter [Why] The module parameter to specify the default ABM level is now defined, so hook it up in DM. [How] On connector reset specify the default level. DC will program this as part of the modeset since it gets passed onto the stream in dm_update_crtc_state. It's only set for eDP connectors, but it doesn't matter if this is specified for connectors or hardware that doesn't support ABM. It's DC's responsibility to check that ABM can be set or adjusted, and DC does check that the DMCU firmware is running and if there's backlight control available. Signed-off-by: Nicholas Kazlauskas Reviewed-by: David Francis Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f09407162d41..6c709f922f66 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3738,6 +3738,9 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) state->underscan_vborder = 0; state->base.max_requested_bpc = 8; + if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) + state->abm_level = amdgpu_dm_abm_level; + __drm_atomic_helper_connector_reset(connector, &state->base); } } -- cgit From 7cd4b70091a5cfa1f58d3a529535304a116acc95 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Thu, 9 May 2019 12:14:58 -0400 Subject: drm/amd/display: Rework CRTC color management [Why] To prepare for the upcoming DRM plane color management properties we need to correct a lot of wrong behavior and assumptions made for CRTC color management. The documentation added by this commit in amdgpu_dm_color explains how the HW color pipeline works and its limitations with the DRM interface. The current implementation does the following wrong: - Implicit sRGB DGM when no CRTC DGM is set - Implicit sRGB RGM when no CRTC RGM is set - No way to specify a non-linear DGM matrix that produces correct output - No way to specify a correct RGM when a linear DGM is used We had workarounds for passing kms_color tests but not all of the behavior we had wrong was covered by these tests (especially when it comes to non-linear DGM). Testing both DGM and RGM at the same time isn't something kms_color tests well either. [How] The specifics for how color management works in AMDGPU and the new behavior can be found by reading the documentation added to amdgpu_dm_color.c from this patch. All of the incorrect cases from the old implementation have been addressed for the atomic interface, but there still a few TODOs for the legacy one. Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI. The result looks correct from visual inspection but the CRC no longer matches. For reference, the test was previously doing the following: linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ... Now the test is doing: linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ... Signed-off-by: Nicholas Kazlauskas Reviewed-by: Sun peng Li Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 473 ++++++++++++++------- 3 files changed, 356 insertions(+), 159 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6c709f922f66..87cc2eb08939 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2857,6 +2857,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, struct drm_plane_state *plane_state, struct drm_crtc_state *crtc_state) { + struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); const struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(plane_state->fb); struct dc_scaling_info scaling_info; @@ -2901,13 +2902,11 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, * Always set input transfer function, since plane state is refreshed * every time. */ - ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state); - if (ret) { - dc_transfer_func_release(dc_plane_state->in_transfer_func); - dc_plane_state->in_transfer_func = NULL; - } + ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); + if (ret) + return ret; - return ret; + return 0; } static void update_stream_scaling_settings(const struct drm_display_mode *mode, @@ -3482,6 +3481,8 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) state->vrr_supported = cur->vrr_supported; state->freesync_config = cur->freesync_config; state->crc_enabled = cur->crc_enabled; + state->cm_has_degamma = cur->cm_has_degamma; + state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; /* TODO Duplicate dc_stream after objects are stream object is flattened */ @@ -5643,8 +5644,18 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, bundle->stream_update.dst = acrtc_state->stream->dst; } - if (new_pcrtc_state->color_mgmt_changed) - bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func; + if (new_pcrtc_state->color_mgmt_changed) { + /* + * TODO: This isn't fully correct since we've actually + * already modified the stream in place. + */ + bundle->stream_update.gamut_remap = + &acrtc_state->stream->gamut_remap_matrix; + bundle->stream_update.output_csc_transform = + &acrtc_state->stream->csc_color_matrix; + bundle->stream_update.out_transfer_func = + acrtc_state->stream->out_transfer_func; + } acrtc_state->stream->abm_level = acrtc_state->abm_level; if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) @@ -6494,10 +6505,9 @@ skip_modeset: */ if (dm_new_crtc_state->base.color_mgmt_changed || drm_atomic_crtc_needs_modeset(new_crtc_state)) { - ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state); + ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); if (ret) goto fail; - amdgpu_dm_set_ctm(dm_new_crtc_state); } /* Update Freesync settings. */ @@ -6792,6 +6802,8 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, new_dm_plane_state->dc_state->in_transfer_func; stream_update.gamut_remap = &new_dm_crtc_state->stream->gamut_remap_matrix; + stream_update.output_csc_transform = + &new_dm_crtc_state->stream->csc_color_matrix; stream_update.out_transfer_func = new_dm_crtc_state->stream->out_transfer_func; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b0ce44422e90..642defb5ea30 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -271,6 +271,9 @@ struct dm_crtc_state { struct drm_crtc_state base; struct dc_stream_state *stream; + bool cm_has_degamma; + bool cm_is_degamma_srgb; + int active_planes; bool interrupts_enabled; @@ -360,10 +363,9 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 void amdgpu_dm_init_color_mod(void); -int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, - struct dc_plane_state *dc_plane_state); -void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc); -int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc); +int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); +int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct dc_plane_state *dc_plane_state); extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 7258c992a2bf..b43bb7f90e4e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -27,6 +27,47 @@ #include "amdgpu_dm.h" #include "dc.h" #include "modules/color/color_gamma.h" +#include "basics/conversion.h" + +/* + * The DC interface to HW gives us the following color management blocks + * per pipe (surface): + * + * - Input gamma LUT (de-normalized) + * - Input CSC (normalized) + * - Surface degamma LUT (normalized) + * - Surface CSC (normalized) + * - Surface regamma LUT (normalized) + * - Output CSC (normalized) + * + * But these aren't a direct mapping to DRM color properties. The current DRM + * interface exposes CRTC degamma, CRTC CTM and CRTC regamma while our hardware + * is essentially giving: + * + * Plane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM + * + * The input gamma LUT block isn't really applicable here since it operates + * on the actual input data itself rather than the HW fp representation. The + * input and output CSC blocks are technically available to use as part of + * the DC interface but are typically used internally by DC for conversions + * between color spaces. These could be blended together with user + * adjustments in the future but for now these should remain untouched. + * + * The pipe blending also happens after these blocks so we don't actually + * support any CRTC props with correct blending with multiple planes - but we + * can still support CRTC color management properties in DM in most single + * plane cases correctly with clever management of the DC interface in DM. + * + * As per DRM documentation, blocks should be in hardware bypass when their + * respective property is set to NULL. A linear DGM/RGM LUT should also + * considered as putting the respective block into bypass mode. + * + * This means that the following + * configuration is assumed to be the default: + * + * Plane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... + * CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypass + */ #define MAX_DRM_LUT_VALUE 0xFFFF @@ -41,6 +82,13 @@ void amdgpu_dm_init_color_mod(void) setup_x_points_distribution(); } +/* Extracts the DRM lut and lut size from a blob. */ +static const struct drm_color_lut * +__extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size) +{ + *size = blob ? drm_color_lut_size(blob) : 0; + return blob ? (struct drm_color_lut *)blob->data : NULL; +} /* * Return true if the given lut is a linear mapping of values, i.e. it acts @@ -50,7 +98,7 @@ void amdgpu_dm_init_color_mod(void) * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in * [0, MAX_COLOR_LUT_ENTRIES) */ -static bool __is_lut_linear(struct drm_color_lut *lut, uint32_t size) +static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size) { int i; uint32_t expected; @@ -75,9 +123,8 @@ static bool __is_lut_linear(struct drm_color_lut *lut, uint32_t size) * Convert the drm_color_lut to dc_gamma. The conversion depends on the size * of the lut - whether or not it's legacy. */ -static void __drm_lut_to_dc_gamma(struct drm_color_lut *lut, - struct dc_gamma *gamma, - bool is_legacy) +static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, + struct dc_gamma *gamma, bool is_legacy) { uint32_t r, g, b; int i; @@ -107,103 +154,16 @@ static void __drm_lut_to_dc_gamma(struct drm_color_lut *lut, } } -/** - * amdgpu_dm_set_regamma_lut: Set regamma lut for the given CRTC. - * @crtc: amdgpu_dm crtc state - * - * Update the underlying dc_stream_state's output transfer function (OTF) in - * preparation for hardware commit. If no lut is specified by user, we default - * to SRGB. - * - * RETURNS: - * 0 on success, -ENOMEM if memory cannot be allocated to calculate the OTF. - */ -int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc) -{ - struct drm_property_blob *blob = crtc->base.gamma_lut; - struct dc_stream_state *stream = crtc->stream; - struct amdgpu_device *adev = (struct amdgpu_device *) - crtc->base.state->dev->dev_private; - struct drm_color_lut *lut; - uint32_t lut_size; - struct dc_gamma *gamma = NULL; - enum dc_transfer_func_type old_type = stream->out_transfer_func->type; - - bool ret; - - if (!blob && adev->asic_type <= CHIP_RAVEN) { - /* By default, use the SRGB predefined curve.*/ - stream->out_transfer_func->type = TF_TYPE_PREDEFINED; - stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; - return 0; - } - - if (blob) { - lut = (struct drm_color_lut *)blob->data; - lut_size = blob->length / sizeof(struct drm_color_lut); - - gamma = dc_create_gamma(); - if (!gamma) - return -ENOMEM; - - gamma->num_entries = lut_size; - if (gamma->num_entries == MAX_COLOR_LEGACY_LUT_ENTRIES) - gamma->type = GAMMA_RGB_256; - else if (gamma->num_entries == MAX_COLOR_LUT_ENTRIES) - gamma->type = GAMMA_CS_TFM_1D; - else { - /* Invalid lut size */ - dc_gamma_release(&gamma); - return -EINVAL; - } - - /* Convert drm_lut into dc_gamma */ - __drm_lut_to_dc_gamma(lut, gamma, gamma->type == GAMMA_RGB_256); - } - - /* predefined gamma ROM only exist for RAVEN and pre-RAVEN ASIC, - * set canRomBeUsed accordingly - */ - stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; - ret = mod_color_calculate_regamma_params(stream->out_transfer_func, - gamma, true, adev->asic_type <= CHIP_RAVEN, NULL); - - if (gamma) - dc_gamma_release(&gamma); - - if (!ret) { - stream->out_transfer_func->type = old_type; - DRM_ERROR("Out of memory when calculating regamma params\n"); - return -ENOMEM; - } - - return 0; -} - -/** - * amdgpu_dm_set_ctm: Set the color transform matrix for the given CRTC. - * @crtc: amdgpu_dm crtc state - * - * Update the underlying dc_stream_state's gamut remap matrix in preparation - * for hardware commit. If no matrix is specified by user, gamut remap will be - * disabled. +/* + * Converts a DRM CTM to a DC CSC float matrix. + * The matrix needs to be a 3x4 (12 entry) matrix. */ -void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc) +static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, + struct fixed31_32 *matrix) { - - struct drm_property_blob *blob = crtc->base.ctm; - struct dc_stream_state *stream = crtc->stream; - struct drm_color_ctm *ctm; int64_t val; int i; - if (!blob) { - stream->gamut_remap_matrix.enable_remap = false; - return; - } - - stream->gamut_remap_matrix.enable_remap = true; - ctm = (struct drm_color_ctm *)blob->data; /* * DRM gives a 3x3 matrix, but DC wants 3x4. Assuming we're operating * with homogeneous coordinates, augment the matrix with 0's. @@ -215,83 +175,306 @@ void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc) for (i = 0; i < 12; i++) { /* Skip 4th element */ if (i % 4 == 3) { - stream->gamut_remap_matrix.matrix[i] = dc_fixpt_zero; + matrix[i] = dc_fixpt_zero; continue; } /* gamut_remap_matrix[i] = ctm[i - floor(i/4)] */ - val = ctm->matrix[i - (i/4)]; + val = ctm->matrix[i - (i / 4)]; /* If negative, convert to 2's complement. */ if (val & (1ULL << 63)) val = -(val & ~(1ULL << 63)); - stream->gamut_remap_matrix.matrix[i].value = val; + matrix[i].value = val; } } +/* Calculates the legacy transfer function - only for sRGB input space. */ +static int __set_legacy_tf(struct dc_transfer_func *func, + const struct drm_color_lut *lut, uint32_t lut_size, + bool has_rom) +{ + struct dc_gamma *gamma = NULL; + bool res; -/** - * amdgpu_dm_set_degamma_lut: Set degamma lut for the given CRTC. - * @crtc: amdgpu_dm crtc state - * - * Update the underlying dc_stream_state's input transfer function (ITF) in - * preparation for hardware commit. If no lut is specified by user, we default - * to SRGB degamma. - * - * We support degamma bypass, predefined SRGB, and custom degamma - * - * RETURNS: - * 0 on success - * -EINVAL if crtc_state has a degamma_lut of invalid size - * -ENOMEM if gamma allocation fails - */ -int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, - struct dc_plane_state *dc_plane_state) + ASSERT(lut && lut_size == MAX_COLOR_LEGACY_LUT_ENTRIES); + + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->type = GAMMA_RGB_256; + gamma->num_entries = lut_size; + __drm_lut_to_dc_gamma(lut, gamma, true); + + res = mod_color_calculate_regamma_params(func, gamma, true, has_rom, + NULL); + + return res ? 0 : -ENOMEM; +} + +/* Calculates the output transfer function based on expected input space. */ +static int __set_output_tf(struct dc_transfer_func *func, + const struct drm_color_lut *lut, uint32_t lut_size, + bool has_rom) { - struct drm_property_blob *blob = crtc_state->degamma_lut; - struct drm_color_lut *lut; - uint32_t lut_size; - struct dc_gamma *gamma; - bool ret; - - if (!blob) { - /* Default to SRGB */ - dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED; - dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_SRGB; - return 0; - } + struct dc_gamma *gamma = NULL; + bool res; - lut = (struct drm_color_lut *)blob->data; - if (__is_lut_linear(lut, MAX_COLOR_LUT_ENTRIES)) { - dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; - dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; - return 0; - } + ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES); gamma = dc_create_gamma(); if (!gamma) return -ENOMEM; - lut_size = blob->length / sizeof(struct drm_color_lut); gamma->num_entries = lut_size; - if (gamma->num_entries == MAX_COLOR_LUT_ENTRIES) + __drm_lut_to_dc_gamma(lut, gamma, false); + + if (func->tf == TRANSFER_FUNCTION_LINEAR) { + /* + * Color module doesn't like calculating regamma params + * on top of a linear input. But degamma params can be used + * instead to simulate this. + */ gamma->type = GAMMA_CUSTOM; - else { - dc_gamma_release(&gamma); - return -EINVAL; + res = mod_color_calculate_degamma_params(func, gamma, true); + } else { + /* + * Assume sRGB. The actual mapping will depend on whether the + * input was legacy or not. + */ + gamma->type = GAMMA_CS_TFM_1D; + res = mod_color_calculate_regamma_params(func, gamma, false, + has_rom, NULL); } + dc_gamma_release(&gamma); + + return res ? 0 : -ENOMEM; +} + +/* Caculates the input transfer function based on expected input space. */ +static int __set_input_tf(struct dc_transfer_func *func, + const struct drm_color_lut *lut, uint32_t lut_size) +{ + struct dc_gamma *gamma = NULL; + bool res; + + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->type = GAMMA_CUSTOM; + gamma->num_entries = lut_size; + __drm_lut_to_dc_gamma(lut, gamma, false); - dc_plane_state->in_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; - ret = mod_color_calculate_degamma_params(dc_plane_state->in_transfer_func, gamma, true); + res = mod_color_calculate_degamma_params(func, gamma, true); dc_gamma_release(&gamma); - if (!ret) { - dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; - DRM_ERROR("Out of memory when calculating degamma params\n"); - return -ENOMEM; + + return res ? 0 : -ENOMEM; +} + +/** + * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. + * @crtc: amdgpu_dm crtc state + * + * With no plane level color management properties we're free to use any + * of the HW blocks as long as the CRTC CTM always comes before the + * CRTC RGM and after the CRTC DGM. + * + * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear. + * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear. + * The CRTC CTM will be placed in the gamut remap block if it is non-linear. + * + * The RGM block is typically more fully featured and accurate across + * all ASICs - DCE can't support a custom non-linear CRTC DGM. + * + * For supporting both plane level color management and CRTC level color + * management at once we have to either restrict the usage of CRTC properties + * or blend adjustments together. + * + * Returns 0 on success. + */ +int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) +{ + struct dc_stream_state *stream = crtc->stream; + struct amdgpu_device *adev = + (struct amdgpu_device *)crtc->base.state->dev->dev_private; + bool has_rom = adev->asic_type <= CHIP_RAVEN; + struct drm_color_ctm *ctm = NULL; + const struct drm_color_lut *degamma_lut, *regamma_lut; + uint32_t degamma_size, regamma_size; + bool has_regamma, has_degamma; + bool is_legacy; + int r; + + degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, °amma_size); + if (degamma_lut && degamma_size != MAX_COLOR_LUT_ENTRIES) + return -EINVAL; + + regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, ®amma_size); + if (regamma_lut && regamma_size != MAX_COLOR_LUT_ENTRIES && + regamma_size != MAX_COLOR_LEGACY_LUT_ENTRIES) + return -EINVAL; + + has_degamma = + degamma_lut && !__is_lut_linear(degamma_lut, degamma_size); + + has_regamma = + regamma_lut && !__is_lut_linear(regamma_lut, regamma_size); + + is_legacy = regamma_size == MAX_COLOR_LEGACY_LUT_ENTRIES; + + /* Reset all adjustments. */ + crtc->cm_has_degamma = false; + crtc->cm_is_degamma_srgb = false; + + /* Setup regamma and degamma. */ + if (is_legacy) { + /* + * Legacy regamma forces us to use the sRGB RGM as a base. + * This also means we can't use linear DGM since DGM needs + * to use sRGB as a base as well, resulting in incorrect CRTC + * DGM and CRTC CTM. + * + * TODO: Just map this to the standard regamma interface + * instead since this isn't really right. One of the cases + * where this setup currently fails is trying to do an + * inverse color ramp in legacy userspace. + */ + crtc->cm_is_degamma_srgb = true; + stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; + + r = __set_legacy_tf(stream->out_transfer_func, regamma_lut, + regamma_size, has_rom); + if (r) + return r; + } else if (has_regamma) { + /* CRTC RGM goes into RGM LUT. */ + stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + + r = __set_output_tf(stream->out_transfer_func, regamma_lut, + regamma_size, has_rom); + if (r) + return r; + } else { + /* + * No CRTC RGM means we can just put the block into bypass + * since we don't have any plane level adjustments using it. + */ + stream->out_transfer_func->type = TF_TYPE_BYPASS; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + } + + /* + * CRTC DGM goes into DGM LUT. It would be nice to place it + * into the RGM since it's a more featured block but we'd + * have to place the CTM in the OCSC in that case. + */ + crtc->cm_has_degamma = has_degamma; + + /* Setup CRTC CTM. */ + if (crtc->base.ctm) { + ctm = (struct drm_color_ctm *)crtc->base.ctm->data; + + /* + * Gamut remapping must be used for gamma correction + * since it comes before the regamma correction. + * + * OCSC could be used for gamma correction, but we'd need to + * blend the adjustments together with the required output + * conversion matrix - so just use the gamut remap block + * for now. + */ + __drm_ctm_to_dc_matrix(ctm, stream->gamut_remap_matrix.matrix); + + stream->gamut_remap_matrix.enable_remap = true; + stream->csc_color_matrix.enable_adjustment = false; + } else { + /* Bypass CTM. */ + stream->gamut_remap_matrix.enable_remap = false; + stream->csc_color_matrix.enable_adjustment = false; } return 0; } +/** + * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. + * @crtc: amdgpu_dm crtc state + * @ dc_plane_state: target DC surface + * + * Update the underlying dc_stream_state's input transfer function (ITF) in + * preparation for hardware commit. The transfer function used depends on + * the prepartion done on the stream for color management. + * + * Returns 0 on success. + */ +int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct dc_plane_state *dc_plane_state) +{ + const struct drm_color_lut *degamma_lut; + uint32_t degamma_size; + int r; + + if (crtc->cm_has_degamma) { + degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, + °amma_size); + ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES); + + dc_plane_state->in_transfer_func->type = + TF_TYPE_DISTRIBUTED_POINTS; + + /* + * This case isn't fully correct, but also fairly + * uncommon. This is userspace trying to use a + * legacy gamma LUT + atomic degamma LUT + * at the same time. + * + * Legacy gamma requires the input to be in linear + * space, so that means we need to apply an sRGB + * degamma. But color module also doesn't support + * a user ramp in this case so the degamma will + * be lost. + * + * Even if we did support it, it's still not right: + * + * Input -> CRTC DGM -> sRGB DGM -> CRTC CTM -> + * sRGB RGM -> CRTC RGM -> Output + * + * The CSC will be done in the wrong space since + * we're applying an sRGB DGM on top of the CRTC + * DGM. + * + * TODO: Don't use the legacy gamma interface and just + * map these to the atomic one instead. + */ + if (crtc->cm_is_degamma_srgb) + dc_plane_state->in_transfer_func->tf = + TRANSFER_FUNCTION_SRGB; + else + dc_plane_state->in_transfer_func->tf = + TRANSFER_FUNCTION_LINEAR; + + r = __set_input_tf(dc_plane_state->in_transfer_func, + degamma_lut, degamma_size); + if (r) + return r; + } else if (crtc->cm_is_degamma_srgb) { + /* + * For legacy gamma support we need the regamma input + * in linear space. Assume that the input is sRGB. + */ + dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED; + dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_SRGB; + } else { + /* ...Otherwise we can just bypass the DGM block. */ + dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; + dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + } + + return 0; +} -- cgit From 4be8be78b7d848544b7c4b0191791c7e5c2e2236 Mon Sep 17 00:00:00 2001 From: Greg Kroah-Hartman Date: Thu, 13 Jun 2019 15:20:12 +0200 Subject: amdgpu_dm: no need to check return value of debugfs_create functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When calling debugfs functions, there is no need to ever check the return value. The function can work or not, but the code logic should never do something different based on this. Cc: Harry Wentland Cc: Leo Li Cc: Alex Deucher Cc: "Christian König" Cc: "David (ChunMing) Zhou" Cc: David Airlie Cc: Daniel Vetter Cc: Nicholas Kazlauskas Cc: David Francis Cc: Mario Kleiner Cc: Bhawanpreet Lakha Cc: Anthony Koo Cc: hersen wu Cc: "Leo (Hanghong) Ma" Cc: amd-gfx@lists.freedesktop.org Cc: dri-devel@lists.freedesktop.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +--- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 35 +++++++--------------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h | 2 +- 3 files changed, 12 insertions(+), 31 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 87cc2eb08939..35530f612713 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4994,11 +4994,7 @@ static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm, drm_connector_register(&aconnector->base); #if defined(CONFIG_DEBUG_FS) - res = connector_debugfs_init(aconnector); - if (res) { - DRM_ERROR("Failed to create debugfs for connector"); - goto out_free; - } + connector_debugfs_init(aconnector); aconnector->debugfs_dpcd_address = 0; aconnector->debugfs_dpcd_size = 0; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index a3e362fa6747..406129e67e79 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -940,25 +940,19 @@ static const struct { {"aux_dpcd_data", &dp_dpcd_data_debugfs_fops} }; -int connector_debugfs_init(struct amdgpu_dm_connector *connector) +void connector_debugfs_init(struct amdgpu_dm_connector *connector) { int i; - struct dentry *ent, *dir = connector->base.debugfs_entry; + struct dentry *dir = connector->base.debugfs_entry; if (connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort || connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { for (i = 0; i < ARRAY_SIZE(dp_debugfs_entries); i++) { - ent = debugfs_create_file(dp_debugfs_entries[i].name, - 0644, - dir, - connector, - dp_debugfs_entries[i].fops); - if (IS_ERR(ent)) - return PTR_ERR(ent); + debugfs_create_file(dp_debugfs_entries[i].name, + 0644, dir, connector, + dp_debugfs_entries[i].fops); } } - - return 0; } /* @@ -1101,7 +1095,7 @@ int dtn_debugfs_init(struct amdgpu_device *adev) }; struct drm_minor *minor = adev->ddev->primary; - struct dentry *ent, *root = minor->debugfs_root; + struct dentry *root = minor->debugfs_root; int ret; ret = amdgpu_debugfs_add_files(adev, amdgpu_dm_debugfs_list, @@ -1109,20 +1103,11 @@ int dtn_debugfs_init(struct amdgpu_device *adev) if (ret) return ret; - ent = debugfs_create_file( - "amdgpu_dm_dtn_log", - 0644, - root, - adev, - &dtn_log_fops); - - if (IS_ERR(ent)) - return PTR_ERR(ent); + debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, + &dtn_log_fops); - ent = debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, - adev, &visual_confirm_fops); - if (IS_ERR(ent)) - return PTR_ERR(ent); + debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, + &visual_confirm_fops); return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h index bdef1587b0a0..5e5b2b2afa31 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.h @@ -29,7 +29,7 @@ #include "amdgpu.h" #include "amdgpu_dm.h" -int connector_debugfs_init(struct amdgpu_dm_connector *connector); +void connector_debugfs_init(struct amdgpu_dm_connector *connector); int dtn_debugfs_init(struct amdgpu_device *adev); #endif -- cgit From 51e857af9f3f1ab78be10ff6bf5c4a8a56f4e4d6 Mon Sep 17 00:00:00 2001 From: Sean Paul Date: Thu, 13 Jun 2019 20:27:00 -0400 Subject: drm/amdgpu: Fix connector atomic_check compilation fail MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I missed amdgpu in my connnector_helper_funcs->atomic_check conversion, which is understandably causing compilation failures. Fixes: 6f3b62781bbd ("drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state") Cc: Daniel Vetter Cc: Ville Syrjälä Cc: Jani Nikula Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Ben Skeggs Cc: Laurent Pinchart Cc: Kieran Bingham Cc: Eric Anholt Cc: Laurent Pinchart [for rcar lvds] Cc: Sean Paul Cc: Maarten Lankhorst Cc: Maxime Ripard Cc: Sean Paul Cc: David Airlie Cc: Lyude Paul Cc: Karol Herbst Cc: Ilia Mirkin Cc: dri-devel@lists.freedesktop.org Cc: intel-gfx@lists.freedesktop.org Cc: linux-renesas-soc@vger.kernel.org Reported-by: Chris Wilson Signed-off-by: Sean Paul Signed-off-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20190614002713.141340-1-sean@poorly.run --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3a723e553a19..3d5e828c3d28 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3953,9 +3953,10 @@ is_hdr_metadata_different(const struct drm_connector_state *old_state, static int amdgpu_dm_connector_atomic_check(struct drm_connector *conn, - struct drm_connector_state *new_con_state) + struct drm_atomic_state *state) { - struct drm_atomic_state *state = new_con_state->state; + struct drm_connector_state *new_con_state = + drm_atomic_get_new_connector_state(state, conn); struct drm_connector_state *old_con_state = drm_atomic_get_old_connector_state(state, conn); struct drm_crtc *crtc = new_con_state->crtc; -- cgit From 70a1efac712caf5c47fad1eed06353303860fe2d Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Thu, 20 Jun 2019 08:30:09 -0400 Subject: Revert "drm/amd/display: Enable fast plane updates when state->allow_modeset = true" This reverts commit ebc8c6f18322ad54275997a888ca1731d74b711f. There are still missing corner cases with cursor interaction and these fast plane updates on Picasso and Raven2 leading to endless PSTATE warnings for typical desktop usage depending on the userspace. This change should be reverted until these issues have been resolved. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110949 Signed-off-by: Nicholas Kazlauskas Reviewed-by: David Francis Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 35530f612713..6bea5fe19b19 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6528,6 +6528,14 @@ static bool should_reset_plane(struct drm_atomic_state *state, struct drm_crtc_state *new_crtc_state; int i; + /* + * TODO: Remove this hack once the checks below are sufficient + * enough to determine when we need to reset all the planes on + * the stream. + */ + if (state->allow_modeset) + return true; + /* Exit early if we know that we're adding or removing the plane. */ if (old_plane_state->crtc != new_plane_state->crtc) return true; -- cgit From ecbc382c9fdf19b4e0e1ee4702923a39133b864e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 17 Jun 2019 13:08:40 -0500 Subject: Revert "drm/amd/display: Rework CRTC color management" This reverts commit 7cd4b70091a5cfa1f58d3a529535304a116acc95. Revert this to apply the version that includes DCN2 support. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 473 +++++++-------------- 3 files changed, 159 insertions(+), 356 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6bea5fe19b19..95ec4450f2c5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2857,7 +2857,6 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, struct drm_plane_state *plane_state, struct drm_crtc_state *crtc_state) { - struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); const struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(plane_state->fb); struct dc_scaling_info scaling_info; @@ -2902,11 +2901,13 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, * Always set input transfer function, since plane state is refreshed * every time. */ - ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); - if (ret) - return ret; + ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state); + if (ret) { + dc_transfer_func_release(dc_plane_state->in_transfer_func); + dc_plane_state->in_transfer_func = NULL; + } - return 0; + return ret; } static void update_stream_scaling_settings(const struct drm_display_mode *mode, @@ -3481,8 +3482,6 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) state->vrr_supported = cur->vrr_supported; state->freesync_config = cur->freesync_config; state->crc_enabled = cur->crc_enabled; - state->cm_has_degamma = cur->cm_has_degamma; - state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; /* TODO Duplicate dc_stream after objects are stream object is flattened */ @@ -5640,18 +5639,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, bundle->stream_update.dst = acrtc_state->stream->dst; } - if (new_pcrtc_state->color_mgmt_changed) { - /* - * TODO: This isn't fully correct since we've actually - * already modified the stream in place. - */ - bundle->stream_update.gamut_remap = - &acrtc_state->stream->gamut_remap_matrix; - bundle->stream_update.output_csc_transform = - &acrtc_state->stream->csc_color_matrix; - bundle->stream_update.out_transfer_func = - acrtc_state->stream->out_transfer_func; - } + if (new_pcrtc_state->color_mgmt_changed) + bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func; acrtc_state->stream->abm_level = acrtc_state->abm_level; if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) @@ -6501,9 +6490,10 @@ skip_modeset: */ if (dm_new_crtc_state->base.color_mgmt_changed || drm_atomic_crtc_needs_modeset(new_crtc_state)) { - ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); + ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state); if (ret) goto fail; + amdgpu_dm_set_ctm(dm_new_crtc_state); } /* Update Freesync settings. */ @@ -6806,8 +6796,6 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, new_dm_plane_state->dc_state->in_transfer_func; stream_update.gamut_remap = &new_dm_crtc_state->stream->gamut_remap_matrix; - stream_update.output_csc_transform = - &new_dm_crtc_state->stream->csc_color_matrix; stream_update.out_transfer_func = new_dm_crtc_state->stream->out_transfer_func; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 642defb5ea30..b0ce44422e90 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -271,9 +271,6 @@ struct dm_crtc_state { struct drm_crtc_state base; struct dc_stream_state *stream; - bool cm_has_degamma; - bool cm_is_degamma_srgb; - int active_planes; bool interrupts_enabled; @@ -363,9 +360,10 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 void amdgpu_dm_init_color_mod(void); -int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); -int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, - struct dc_plane_state *dc_plane_state); +int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, + struct dc_plane_state *dc_plane_state); +void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc); +int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc); extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index b43bb7f90e4e..7258c992a2bf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -27,47 +27,6 @@ #include "amdgpu_dm.h" #include "dc.h" #include "modules/color/color_gamma.h" -#include "basics/conversion.h" - -/* - * The DC interface to HW gives us the following color management blocks - * per pipe (surface): - * - * - Input gamma LUT (de-normalized) - * - Input CSC (normalized) - * - Surface degamma LUT (normalized) - * - Surface CSC (normalized) - * - Surface regamma LUT (normalized) - * - Output CSC (normalized) - * - * But these aren't a direct mapping to DRM color properties. The current DRM - * interface exposes CRTC degamma, CRTC CTM and CRTC regamma while our hardware - * is essentially giving: - * - * Plane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM - * - * The input gamma LUT block isn't really applicable here since it operates - * on the actual input data itself rather than the HW fp representation. The - * input and output CSC blocks are technically available to use as part of - * the DC interface but are typically used internally by DC for conversions - * between color spaces. These could be blended together with user - * adjustments in the future but for now these should remain untouched. - * - * The pipe blending also happens after these blocks so we don't actually - * support any CRTC props with correct blending with multiple planes - but we - * can still support CRTC color management properties in DM in most single - * plane cases correctly with clever management of the DC interface in DM. - * - * As per DRM documentation, blocks should be in hardware bypass when their - * respective property is set to NULL. A linear DGM/RGM LUT should also - * considered as putting the respective block into bypass mode. - * - * This means that the following - * configuration is assumed to be the default: - * - * Plane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... - * CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypass - */ #define MAX_DRM_LUT_VALUE 0xFFFF @@ -82,13 +41,6 @@ void amdgpu_dm_init_color_mod(void) setup_x_points_distribution(); } -/* Extracts the DRM lut and lut size from a blob. */ -static const struct drm_color_lut * -__extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size) -{ - *size = blob ? drm_color_lut_size(blob) : 0; - return blob ? (struct drm_color_lut *)blob->data : NULL; -} /* * Return true if the given lut is a linear mapping of values, i.e. it acts @@ -98,7 +50,7 @@ __extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size) * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in * [0, MAX_COLOR_LUT_ENTRIES) */ -static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size) +static bool __is_lut_linear(struct drm_color_lut *lut, uint32_t size) { int i; uint32_t expected; @@ -123,8 +75,9 @@ static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size) * Convert the drm_color_lut to dc_gamma. The conversion depends on the size * of the lut - whether or not it's legacy. */ -static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, - struct dc_gamma *gamma, bool is_legacy) +static void __drm_lut_to_dc_gamma(struct drm_color_lut *lut, + struct dc_gamma *gamma, + bool is_legacy) { uint32_t r, g, b; int i; @@ -154,16 +107,103 @@ static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, } } -/* - * Converts a DRM CTM to a DC CSC float matrix. - * The matrix needs to be a 3x4 (12 entry) matrix. +/** + * amdgpu_dm_set_regamma_lut: Set regamma lut for the given CRTC. + * @crtc: amdgpu_dm crtc state + * + * Update the underlying dc_stream_state's output transfer function (OTF) in + * preparation for hardware commit. If no lut is specified by user, we default + * to SRGB. + * + * RETURNS: + * 0 on success, -ENOMEM if memory cannot be allocated to calculate the OTF. */ -static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, - struct fixed31_32 *matrix) +int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc) { + struct drm_property_blob *blob = crtc->base.gamma_lut; + struct dc_stream_state *stream = crtc->stream; + struct amdgpu_device *adev = (struct amdgpu_device *) + crtc->base.state->dev->dev_private; + struct drm_color_lut *lut; + uint32_t lut_size; + struct dc_gamma *gamma = NULL; + enum dc_transfer_func_type old_type = stream->out_transfer_func->type; + + bool ret; + + if (!blob && adev->asic_type <= CHIP_RAVEN) { + /* By default, use the SRGB predefined curve.*/ + stream->out_transfer_func->type = TF_TYPE_PREDEFINED; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; + return 0; + } + + if (blob) { + lut = (struct drm_color_lut *)blob->data; + lut_size = blob->length / sizeof(struct drm_color_lut); + + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->num_entries = lut_size; + if (gamma->num_entries == MAX_COLOR_LEGACY_LUT_ENTRIES) + gamma->type = GAMMA_RGB_256; + else if (gamma->num_entries == MAX_COLOR_LUT_ENTRIES) + gamma->type = GAMMA_CS_TFM_1D; + else { + /* Invalid lut size */ + dc_gamma_release(&gamma); + return -EINVAL; + } + + /* Convert drm_lut into dc_gamma */ + __drm_lut_to_dc_gamma(lut, gamma, gamma->type == GAMMA_RGB_256); + } + + /* predefined gamma ROM only exist for RAVEN and pre-RAVEN ASIC, + * set canRomBeUsed accordingly + */ + stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; + ret = mod_color_calculate_regamma_params(stream->out_transfer_func, + gamma, true, adev->asic_type <= CHIP_RAVEN, NULL); + + if (gamma) + dc_gamma_release(&gamma); + + if (!ret) { + stream->out_transfer_func->type = old_type; + DRM_ERROR("Out of memory when calculating regamma params\n"); + return -ENOMEM; + } + + return 0; +} + +/** + * amdgpu_dm_set_ctm: Set the color transform matrix for the given CRTC. + * @crtc: amdgpu_dm crtc state + * + * Update the underlying dc_stream_state's gamut remap matrix in preparation + * for hardware commit. If no matrix is specified by user, gamut remap will be + * disabled. + */ +void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc) +{ + + struct drm_property_blob *blob = crtc->base.ctm; + struct dc_stream_state *stream = crtc->stream; + struct drm_color_ctm *ctm; int64_t val; int i; + if (!blob) { + stream->gamut_remap_matrix.enable_remap = false; + return; + } + + stream->gamut_remap_matrix.enable_remap = true; + ctm = (struct drm_color_ctm *)blob->data; /* * DRM gives a 3x3 matrix, but DC wants 3x4. Assuming we're operating * with homogeneous coordinates, augment the matrix with 0's. @@ -175,306 +215,83 @@ static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, for (i = 0; i < 12; i++) { /* Skip 4th element */ if (i % 4 == 3) { - matrix[i] = dc_fixpt_zero; + stream->gamut_remap_matrix.matrix[i] = dc_fixpt_zero; continue; } /* gamut_remap_matrix[i] = ctm[i - floor(i/4)] */ - val = ctm->matrix[i - (i / 4)]; + val = ctm->matrix[i - (i/4)]; /* If negative, convert to 2's complement. */ if (val & (1ULL << 63)) val = -(val & ~(1ULL << 63)); - matrix[i].value = val; + stream->gamut_remap_matrix.matrix[i].value = val; } } -/* Calculates the legacy transfer function - only for sRGB input space. */ -static int __set_legacy_tf(struct dc_transfer_func *func, - const struct drm_color_lut *lut, uint32_t lut_size, - bool has_rom) -{ - struct dc_gamma *gamma = NULL; - bool res; - - ASSERT(lut && lut_size == MAX_COLOR_LEGACY_LUT_ENTRIES); - gamma = dc_create_gamma(); - if (!gamma) - return -ENOMEM; - - gamma->type = GAMMA_RGB_256; - gamma->num_entries = lut_size; - __drm_lut_to_dc_gamma(lut, gamma, true); - - res = mod_color_calculate_regamma_params(func, gamma, true, has_rom, - NULL); - - return res ? 0 : -ENOMEM; -} - -/* Calculates the output transfer function based on expected input space. */ -static int __set_output_tf(struct dc_transfer_func *func, - const struct drm_color_lut *lut, uint32_t lut_size, - bool has_rom) +/** + * amdgpu_dm_set_degamma_lut: Set degamma lut for the given CRTC. + * @crtc: amdgpu_dm crtc state + * + * Update the underlying dc_stream_state's input transfer function (ITF) in + * preparation for hardware commit. If no lut is specified by user, we default + * to SRGB degamma. + * + * We support degamma bypass, predefined SRGB, and custom degamma + * + * RETURNS: + * 0 on success + * -EINVAL if crtc_state has a degamma_lut of invalid size + * -ENOMEM if gamma allocation fails + */ +int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, + struct dc_plane_state *dc_plane_state) { - struct dc_gamma *gamma = NULL; - bool res; + struct drm_property_blob *blob = crtc_state->degamma_lut; + struct drm_color_lut *lut; + uint32_t lut_size; + struct dc_gamma *gamma; + bool ret; + + if (!blob) { + /* Default to SRGB */ + dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED; + dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_SRGB; + return 0; + } - ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES); + lut = (struct drm_color_lut *)blob->data; + if (__is_lut_linear(lut, MAX_COLOR_LUT_ENTRIES)) { + dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; + dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + return 0; + } gamma = dc_create_gamma(); if (!gamma) return -ENOMEM; + lut_size = blob->length / sizeof(struct drm_color_lut); gamma->num_entries = lut_size; - __drm_lut_to_dc_gamma(lut, gamma, false); - - if (func->tf == TRANSFER_FUNCTION_LINEAR) { - /* - * Color module doesn't like calculating regamma params - * on top of a linear input. But degamma params can be used - * instead to simulate this. - */ + if (gamma->num_entries == MAX_COLOR_LUT_ENTRIES) gamma->type = GAMMA_CUSTOM; - res = mod_color_calculate_degamma_params(func, gamma, true); - } else { - /* - * Assume sRGB. The actual mapping will depend on whether the - * input was legacy or not. - */ - gamma->type = GAMMA_CS_TFM_1D; - res = mod_color_calculate_regamma_params(func, gamma, false, - has_rom, NULL); + else { + dc_gamma_release(&gamma); + return -EINVAL; } - dc_gamma_release(&gamma); - - return res ? 0 : -ENOMEM; -} - -/* Caculates the input transfer function based on expected input space. */ -static int __set_input_tf(struct dc_transfer_func *func, - const struct drm_color_lut *lut, uint32_t lut_size) -{ - struct dc_gamma *gamma = NULL; - bool res; - - gamma = dc_create_gamma(); - if (!gamma) - return -ENOMEM; - - gamma->type = GAMMA_CUSTOM; - gamma->num_entries = lut_size; - __drm_lut_to_dc_gamma(lut, gamma, false); - res = mod_color_calculate_degamma_params(func, gamma, true); + dc_plane_state->in_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; + ret = mod_color_calculate_degamma_params(dc_plane_state->in_transfer_func, gamma, true); dc_gamma_release(&gamma); - - return res ? 0 : -ENOMEM; -} - -/** - * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. - * @crtc: amdgpu_dm crtc state - * - * With no plane level color management properties we're free to use any - * of the HW blocks as long as the CRTC CTM always comes before the - * CRTC RGM and after the CRTC DGM. - * - * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear. - * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear. - * The CRTC CTM will be placed in the gamut remap block if it is non-linear. - * - * The RGM block is typically more fully featured and accurate across - * all ASICs - DCE can't support a custom non-linear CRTC DGM. - * - * For supporting both plane level color management and CRTC level color - * management at once we have to either restrict the usage of CRTC properties - * or blend adjustments together. - * - * Returns 0 on success. - */ -int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) -{ - struct dc_stream_state *stream = crtc->stream; - struct amdgpu_device *adev = - (struct amdgpu_device *)crtc->base.state->dev->dev_private; - bool has_rom = adev->asic_type <= CHIP_RAVEN; - struct drm_color_ctm *ctm = NULL; - const struct drm_color_lut *degamma_lut, *regamma_lut; - uint32_t degamma_size, regamma_size; - bool has_regamma, has_degamma; - bool is_legacy; - int r; - - degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, °amma_size); - if (degamma_lut && degamma_size != MAX_COLOR_LUT_ENTRIES) - return -EINVAL; - - regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, ®amma_size); - if (regamma_lut && regamma_size != MAX_COLOR_LUT_ENTRIES && - regamma_size != MAX_COLOR_LEGACY_LUT_ENTRIES) - return -EINVAL; - - has_degamma = - degamma_lut && !__is_lut_linear(degamma_lut, degamma_size); - - has_regamma = - regamma_lut && !__is_lut_linear(regamma_lut, regamma_size); - - is_legacy = regamma_size == MAX_COLOR_LEGACY_LUT_ENTRIES; - - /* Reset all adjustments. */ - crtc->cm_has_degamma = false; - crtc->cm_is_degamma_srgb = false; - - /* Setup regamma and degamma. */ - if (is_legacy) { - /* - * Legacy regamma forces us to use the sRGB RGM as a base. - * This also means we can't use linear DGM since DGM needs - * to use sRGB as a base as well, resulting in incorrect CRTC - * DGM and CRTC CTM. - * - * TODO: Just map this to the standard regamma interface - * instead since this isn't really right. One of the cases - * where this setup currently fails is trying to do an - * inverse color ramp in legacy userspace. - */ - crtc->cm_is_degamma_srgb = true; - stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; - stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; - - r = __set_legacy_tf(stream->out_transfer_func, regamma_lut, - regamma_size, has_rom); - if (r) - return r; - } else if (has_regamma) { - /* CRTC RGM goes into RGM LUT. */ - stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; - stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; - - r = __set_output_tf(stream->out_transfer_func, regamma_lut, - regamma_size, has_rom); - if (r) - return r; - } else { - /* - * No CRTC RGM means we can just put the block into bypass - * since we don't have any plane level adjustments using it. - */ - stream->out_transfer_func->type = TF_TYPE_BYPASS; - stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; - } - - /* - * CRTC DGM goes into DGM LUT. It would be nice to place it - * into the RGM since it's a more featured block but we'd - * have to place the CTM in the OCSC in that case. - */ - crtc->cm_has_degamma = has_degamma; - - /* Setup CRTC CTM. */ - if (crtc->base.ctm) { - ctm = (struct drm_color_ctm *)crtc->base.ctm->data; - - /* - * Gamut remapping must be used for gamma correction - * since it comes before the regamma correction. - * - * OCSC could be used for gamma correction, but we'd need to - * blend the adjustments together with the required output - * conversion matrix - so just use the gamut remap block - * for now. - */ - __drm_ctm_to_dc_matrix(ctm, stream->gamut_remap_matrix.matrix); - - stream->gamut_remap_matrix.enable_remap = true; - stream->csc_color_matrix.enable_adjustment = false; - } else { - /* Bypass CTM. */ - stream->gamut_remap_matrix.enable_remap = false; - stream->csc_color_matrix.enable_adjustment = false; - } - - return 0; -} - -/** - * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. - * @crtc: amdgpu_dm crtc state - * @ dc_plane_state: target DC surface - * - * Update the underlying dc_stream_state's input transfer function (ITF) in - * preparation for hardware commit. The transfer function used depends on - * the prepartion done on the stream for color management. - * - * Returns 0 on success. - */ -int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, - struct dc_plane_state *dc_plane_state) -{ - const struct drm_color_lut *degamma_lut; - uint32_t degamma_size; - int r; - - if (crtc->cm_has_degamma) { - degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, - °amma_size); - ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES); - - dc_plane_state->in_transfer_func->type = - TF_TYPE_DISTRIBUTED_POINTS; - - /* - * This case isn't fully correct, but also fairly - * uncommon. This is userspace trying to use a - * legacy gamma LUT + atomic degamma LUT - * at the same time. - * - * Legacy gamma requires the input to be in linear - * space, so that means we need to apply an sRGB - * degamma. But color module also doesn't support - * a user ramp in this case so the degamma will - * be lost. - * - * Even if we did support it, it's still not right: - * - * Input -> CRTC DGM -> sRGB DGM -> CRTC CTM -> - * sRGB RGM -> CRTC RGM -> Output - * - * The CSC will be done in the wrong space since - * we're applying an sRGB DGM on top of the CRTC - * DGM. - * - * TODO: Don't use the legacy gamma interface and just - * map these to the atomic one instead. - */ - if (crtc->cm_is_degamma_srgb) - dc_plane_state->in_transfer_func->tf = - TRANSFER_FUNCTION_SRGB; - else - dc_plane_state->in_transfer_func->tf = - TRANSFER_FUNCTION_LINEAR; - - r = __set_input_tf(dc_plane_state->in_transfer_func, - degamma_lut, degamma_size); - if (r) - return r; - } else if (crtc->cm_is_degamma_srgb) { - /* - * For legacy gamma support we need the regamma input - * in linear space. Assume that the input is sRGB. - */ - dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED; - dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_SRGB; - } else { - /* ...Otherwise we can just bypass the DGM block. */ + if (!ret) { dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; - dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + DRM_ERROR("Out of memory when calculating degamma params\n"); + return -ENOMEM; } return 0; } + -- cgit From 5527cd064012937915306806bcbb9de01f77b132 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Tue, 5 Mar 2019 19:52:22 +0800 Subject: drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/ interrupt source packet definitions for the display block (DCN). Signed-off-by: Hawking Zhang Reviewed-by: Jack Xiao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- .../amd/display/dc/irq/dcn10/irq_service_dcn10.c | 2 +- .../drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h | 1134 ++++++++++++++++++++ .../gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h | 1134 -------------------- 4 files changed, 1136 insertions(+), 1136 deletions(-) create mode 100644 drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h delete mode 100644 drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 95ec4450f2c5..7e03847154d3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -65,7 +65,7 @@ #include #if defined(CONFIG_DRM_AMD_DC_DCN1_0) -#include "ivsrcid/irqsrcs_dcn_1_0.h" +#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" #include "dcn/dcn_1_0_offset.h" #include "dcn/dcn_1_0_sh_mask.h" diff --git a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c index 10ac6deff5ff..d179e4d8c485 100644 --- a/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c +++ b/drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c @@ -36,7 +36,7 @@ #include "irq_service_dcn10.h" -#include "ivsrcid/irqsrcs_dcn_1_0.h" +#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" enum dc_irq_source to_dal_irq_source_dcn10( struct irq_service *irq_service, diff --git a/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h new file mode 100644 index 000000000000..ac9fa3a9bd07 --- /dev/null +++ b/drivers/gpu/drm/amd/include/ivsrcid/dcn/irqsrcs_dcn_1_0.h @@ -0,0 +1,1134 @@ +/* + * Copyright 2017 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ + +#ifndef __IRQSRCS_DCN_1_0_H__ +#define __IRQSRCS_DCN_1_0_H__ + + +#define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_I2C_SW_DONE 0 + +#define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE 1 + +#define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2 + +#define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE 3 + +#define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4 + +#define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE 5 + +#define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE 6 + +#define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE 7 + +#define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8 + +#define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST 9 + +#define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST 10 + +#define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST 11 + +#define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST 12 + +#define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST 13 + +#define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST 14 + +#define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST 15 + +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS 7 + +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS 8 + +#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS 7 + +#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS 8 + +#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS 7 + +#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS 8 + +#define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT 12 + +#define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DMCU_INTERNAL_INT 13 + +#define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DMCU_SCP_INT 14 + +#define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT 0 + +#define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT 1 + +#define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT 2 + +#define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT 3 + +#define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT 4 + +#define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT 5 + +#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse +#define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS 6 + +#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level +#define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS 7 + +#define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse +#define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT 1 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT 0 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT 1 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT 2 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT 3 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT 4 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT 5 + +#define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT 6 + +#define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT 7 + +#define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_HPD1_INT 0 + +#define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_HPD2_INT 1 + +#define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_HPD3_INT 2 + +#define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_HPD4_INT 3 + +#define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_HPD5_INT 4 + +#define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_HPD6_INT 5 + +#define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_HPD1_RX_INT 6 + +#define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_HPD2_RX_INT 7 + +#define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_HPD3_RX_INT 8 + +#define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_HPD4_RX_INT 9 + +#define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_HPD5_RX_INT 10 + +#define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_HPD6_RX_INT 11 + +#define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET 0 + +#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 2 + +#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 3 + +#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 4 + +#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 5 + +#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 6 + +#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 7 + +#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 8 + +#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 9 + +#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0 + +#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 1 + +#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 2 + +#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 3 + +#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 4 + +#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 5 + +#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 6 + +#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 7 + +#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0 + +#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 1 + +#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 2 + +#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 3 + +#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 4 + +#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 5 + +#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 6 + +#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse +#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 7 + +#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE 0 + +#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR 1 + +#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE 2 + +#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR 3 + +#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE 4 + +#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR 5 + +#define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE 0 + +#define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE 1 + +#define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE 2 + +#define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE 3 + +#define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE 4 + +#define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE 5 + +#define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level +#define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE 6 + +#define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE 7 + +#define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0 + +#define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 1 + +#define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 2 + +#define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 3 + +#define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 4 + +#define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 5 + +#define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level +#define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 6 + +#define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level +#define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 7 + +#define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_AUX1_SW_DONE 0 + +#define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__DC_AUX1_LS_DONE 1 + +#define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_AUX2_SW_DONE 2 + +#define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__DC_AUX2_LS_DONE 3 + +#define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_AUX3_SW_DONE 4 + +#define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__DC_AUX3_LS_DONE 5 + +#define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_AUX4_SW_DONE 6 + +#define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__DC_AUX4_LS_DONE 7 + +#define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_AUX5_SW_DONE 8 + +#define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__DC_AUX5_LS_DONE 9 + +#define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_AUX6_SW_DONE 10 + +#define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level +#define DCN_1_0__CTXID__DC_AUX6_LS_DONE 11 + +#define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__VGA_CRT_INT 12 + +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS 1 + +#define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt 0 + +#define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt 1 + +#define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 2 + +#define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 3 + +#define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS 4 + +#define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS 5 + +#define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS 6 + +#define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS 7 + +#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE 0x13 // AUX4 GTC sync lock complete AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE 0 + +#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR 1 + +#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE 2 + +#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR 3 + +#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE 4 + +#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level +#define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR 5 + +#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT 0 + +#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT 1 + +#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT 2 + +#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT 3 + +#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT 4 + +#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT 5 + +#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT 6 + +#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT 7 + +#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT 8 + +#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT 9 + +#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT 10 + +#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT 11 + +#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT 12 + +#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT 13 + +#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT 14 + +#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT 15 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int 0 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int 1 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int 2 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int 3 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int 4 + +#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level +#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int 5 + +#define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level +#define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT 6 + +#define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level +#define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT 7 + +#define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level +#define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT 8 + +#define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level +#define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT 9 + +#define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT 10 + +#define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level +#define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT 11 + +#define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT 0 + +#define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT 1 + +#define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT 2 + +#define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT 3 + +#define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT 4 + +#define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT 5 + +#define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT 6 + +#define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT 7 + +#define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG1_CPU_SS_INT 0 + +#define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE 1 + +#define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG2_CPU_SS_INT 2 + +#define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE 3 + +#define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG3_CPU_SS_INT 4 + +#define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE 5 + +#define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG4_CPU_SS_INT 6 + +#define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE 7 + +#define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG5_CPU_SS_INT 8 + +#define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE 9 + +#define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__OTG6_CPU_SS_INT 10 + +#define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse +#define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE 11 + +#define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE 0x18 // D1 : OTG V_update OTG1_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE 0x19 // D2 : OTG V_update OTG2_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE 0x1A // D3 : OTG V_update OTG3_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE 0x1B // D4 : OTG V_update OTG4_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE 0x1C // D5 : OTG V_update OTG5_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE 0x1D // D6 : OTG V_update OTG6_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse + +#define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__CTXID__DC_D1_VBLANK 0 + +#define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__CTXID__DC_D1_VLINE1 1 + +#define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__CTXID__DC_D1_VLINE2 2 + +#define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__DC_D2_VBLANK 3 + +#define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__DC_D2_VLINE1 4 + +#define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__DC_D2_VLINE2 5 + +#define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR 6 + +#define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR 7 + +#define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR 8 + +#define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR 9 + +#define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR 10 + +#define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR 11 + +#define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR 12 + +#define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR 13 + +#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse +#define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level +#define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_VBLANK 9 + +#define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_VLINE1 10 + +#define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__DC_D3_VLINE2 11 + +#define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_VBLANK 12 + +#define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_VLINE1 13 + +#define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D4_VLINE2 14 + +#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse +#define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level +#define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_VBLANK 9 + +#define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_VLINE1 10 + +#define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D5_VLINE2 11 + +#define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_VBLANK 12 + +#define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_VLINE1 13 + +#define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_VLINE2 14 + +#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse +#define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level +#define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D7_VBLANK 9 + +#define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D7_VLINE1 10 + +#define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D7_VLINE2 11 + +#define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D8_VBLANK 12 + +#define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D8_VLINE1 13 + +#define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__DC_D8_VLINE2 14 + +#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse +#define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse +#define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse +#define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level +#define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse +#define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level +#define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse +#define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level +#define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse +#define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level +#define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse +#define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level +#define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse +#define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level +#define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse +#define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level +#define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse +#define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level +#define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse +#define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level +#define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level +#define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT 0 + +#define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W 1 + +#define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE 2 + +#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A 3 + +#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B 4 + +#define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP 5 + +#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL 6 + +#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL 7 + +#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL 8 + +#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 + +#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 + +#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 + +#define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse +#define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT 12 + +#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level +#define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level +#define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse +#define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS 0 + +#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level +#define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS 1 + +#define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP 0x3C // "OTG0 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG1_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP 0x3D // "OTG1 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG2_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP 0x3E // "OTG2 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG3_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP 0x3F // "OTG3 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG4_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP 0x40 // "OTG4 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG5_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP 0x41 // "OTG5 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG6_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse + +#define DCN_1_0__SRCID__DC_D1_OTG_VREADY 0x42 // "OTG0 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG1_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D2_OTG_VREADY 0x43 // "OTG1 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG2_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D3_OTG_VREADY 0x44 // "OTG2 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG3_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D4_OTG_VREADY 0x45 // "OTG3 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG4_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D5_OTG_VREADY 0x46 // "OTG4 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG5_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse +#define DCN_1_0__SRCID__DC_D6_OTG_VREADY 0x47 // "OTG5 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG6_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse + +#define DCN_1_0__SRCID__OTG0_VSYNC_NOM 0x48 // OTG0 vsync nom interrupt OTG1_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse +#define DCN_1_0__SRCID__OTG1_VSYNC_NOM 0x49 // OTG1 vsync nom interrupt OTG2_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse +#define DCN_1_0__SRCID__OTG2_VSYNC_NOM 0x4A // OTG2 vsync nom interrupt OTG3_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse +#define DCN_1_0__SRCID__OTG3_VSYNC_NOM 0x4B // OTG3 vsync nom interrupt OTG4_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse +#define DCN_1_0__SRCID__OTG4_VSYNC_NOM 0x4C // OTG4 vsync nom interrupt OTG5_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse +#define DCN_1_0__SRCID__OTG5_VSYNC_NOM 0x4D // OTG5 vsync nom interrupt OTG6_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse + +#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT 0 + +#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT 1 + +#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT 2 + +#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT 3 + +#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT 4 + +#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT 5 + +#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT 6 + +#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT 7 + +#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT 8 + +#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT 9 + +#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT 10 + +#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT 11 + +#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT 12 + +#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT 13 + +#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT 14 + +#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level +#define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT 15 + +#define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT 0x4F // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP0_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT 0x50 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP1_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT 0x51 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP2_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT 0x52 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP3_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT 0x53 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP4_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT 0x54 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP5_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT 0x55 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP6_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT 0x56 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP7_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse + +#define DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x57 // "OTG0 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse +#define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x58 // "OTG1 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse +#define DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x59 // "OTG2 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse +#define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5A // "OTG3 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse +#define DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5B // "OTG4 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse +#define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5C // "OTG5 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse + +#define DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT 0x5D // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP0_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT 0x5E // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP1_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT 0x5F // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP2_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT 0x60 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP3_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT 0x61 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP4_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT 0x62 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP5_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse +#define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse + + +#endif // __IRQSRCS_DCN_1_0_H__ diff --git a/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h b/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h deleted file mode 100644 index ac9fa3a9bd07..000000000000 --- a/drivers/gpu/drm/amd/include/ivsrcid/irqsrcs_dcn_1_0.h +++ /dev/null @@ -1,1134 +0,0 @@ -/* - * Copyright 2017 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __IRQSRCS_DCN_1_0_H__ -#define __IRQSRCS_DCN_1_0_H__ - - -#define DCN_1_0__SRCID__DC_I2C_SW_DONE 1 // DC_I2C SW done DC_I2C_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DC_I2C_SW_DONE 0 - -#define DCN_1_0__SRCID__DC_I2C_DDC1_HW_DONE 1 // DC_I2C DDC1 HW done DOUT_IHC_I2C_DDC1_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level -#define DCN_1_0__CTXID__DC_I2C_DDC1_HW_DONE 1 - -#define DCN_1_0__SRCID__DC_I2C_DDC2_HW_DONE 1 // DC_I2C DDC2 HW done DOUT_IHC_I2C_DDC2_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level -#define DCN_1_0__CTXID__DC_I2C_DDC2_HW_DONE 2 - -#define DCN_1_0__SRCID__DC_I2C_DDC3_HW_DONE 1 // DC_I2C DDC3 HW done DOUT_IHC_I2C_DDC3_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level -#define DCN_1_0__CTXID__DC_I2C_DDC3_HW_DONE 3 - -#define DCN_1_0__SRCID__DC_I2C_DDC4_HW_DONE 1 // DC_I2C_DDC4 HW done DOUT_IHC_I2C_DDC4_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level -#define DCN_1_0__CTXID__DC_I2C_DDC4_HW_DONE 4 - -#define DCN_1_0__SRCID__DC_I2C_DDC5_HW_DONE 1 // DC_I2C_DDC5 HW done DOUT_IHC_I2C_DDC5_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level -#define DCN_1_0__CTXID__DC_I2C_DDC5_HW_DONE 5 - -#define DCN_1_0__SRCID__DC_I2C_DDC6_HW_DONE 1 // DC_I2C_DDC6 HW done DOUT_IHC_I2C_DDC6_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level -#define DCN_1_0__CTXID__DC_I2C_DDC6_HW_DONE 6 - -#define DCN_1_0__SRCID__DC_I2C_DDCVGA_HW_DONE 1 // DC_I2C_DDCVGA HW done DOUT_IHC_I2C_DDCVGA_HW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level -#define DCN_1_0__CTXID__DC_I2C_DDCVGA_HW_DONE 7 - -#define DCN_1_0__SRCID__DC_I2C_DDC1_READ_REQUEST 1 // DC_I2C DDC1 read request DC_I2C_DDC1_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse -#define DCN_1_0__CTXID__DC_I2C_DDC1_READ_REQUEST 8 - -#define DCN_1_0__SRCID__DC_I2C_DDC2_READ_REQUEST 1 // DC_I2C DDC2 read request DC_I2C_DDC2_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse -#define DCN_1_0__CTXID__DC_I2C_DDC2_READ_REQUEST 9 - -#define DCN_1_0__SRCID__DC_I2C_DDC3_READ_REQUEST 1 // DC_I2C DDC3 read request DC_I2C_DDC3_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse -#define DCN_1_0__CTXID__DC_I2C_DDC3_READ_REQUEST 10 - -#define DCN_1_0__SRCID__DC_I2C_DDC4_READ_REQUEST 1 // DC_I2C_DDC4 read request DC_I2C_DDC4_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse -#define DCN_1_0__CTXID__DC_I2C_DDC4_READ_REQUEST 11 - -#define DCN_1_0__SRCID__DC_I2C_DDC5_READ_REQUEST 1 // DC_I2C_DDC5 read request DC_I2C_DDC5_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse -#define DCN_1_0__CTXID__DC_I2C_DDC5_READ_REQUEST 12 - -#define DCN_1_0__SRCID__DC_I2C_DDC6_READ_REQUEST 1 // DC_I2C_DDC6 read request DC_I2C_DDC6_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse -#define DCN_1_0__CTXID__DC_I2C_DDC6_READ_REQUEST 13 - -#define DCN_1_0__SRCID__DC_I2C_DDCVGA_READ_REQUEST 1 // DC_I2C_DDCVGA read request DC_I2C_VGA_READ_REQUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse -#define DCN_1_0__CTXID__DC_I2C_DDCVGA_READ_REQUEST 14 - -#define DCN_1_0__SRCID__GENERIC_I2C_DDC_READ_REQUEST 1 // GENERIC_I2C_DDC read request GENERIC_I2C_DDC_READ_REUEST_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse -#define DCN_1_0__CTXID__GENERIC_I2C_DDC_READ_REQUEST 15 - -#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT0_STATUS 2 // DCCG perfmon counter0 interrupt DCCG_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse -#define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT0_STATUS 7 - -#define DCN_1_0__SRCID__DCCG_PERFCOUNTER_INT1_STATUS 2 // DCCG perfmon counter1 interrupt DCCG_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level -#define DCN_1_0__CTXID__DCCG_PERFCOUNTER_INT1_STATUS 8 - -#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT0_STATUS 3 // DMU perfmon counter0 interrupt DMU_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse -#define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT0_STATUS 7 - -#define DCN_1_0__SRCID__DMU_PERFCOUNTER_INT1_STATUS 3 // DMU perfmon counter1 interrupt DMU_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level -#define DCN_1_0__CTXID__DMU_PERFCOUNTER_INT1_STATUS 8 - -#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT0_STATUS 4 // DIO perfmon counter0 interrupt DIO_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse -#define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT0_STATUS 7 - -#define DCN_1_0__SRCID__DIO_PERFCOUNTER_INT1_STATUS 4 // DIO perfmon counter1 interrupt DIO_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level -#define DCN_1_0__CTXID__DIO_PERFCOUNTER_INT1_STATUS 8 - -#define DCN_1_0__SRCID__RBBMIF_TIMEOUT_INT 5 // RBBMIF timeout interrupt RBBMIF_IHC_TIMEOUT_INTERRUPT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__RBBMIF_TIMEOUT_INT 12 - -#define DCN_1_0__SRCID__DMCU_INTERNAL_INT 5 // DMCU execution exception DMCU_UC_INTERNAL_INT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DMCU_INTERNAL_INT 13 - -#define DCN_1_0__SRCID__DMCU_SCP_INT 5 // DMCU Slave Communication Port Interrupt DMCU_SCP_INT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DMCU_SCP_INT 14 - -#define DCN_1_0__SRCID__DMCU_ABM0_HG_READY_INT 6 // ABM histogram ready interrupt ABM0_HG_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DMCU_ABM0_HG_READY_INT 0 - -#define DCN_1_0__SRCID__DMCU_ABM0_LS_READY_INT 6 // ABM luma stat ready interrupt ABM0_LS_READY_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DMCU_ABM0_LS_READY_INT 1 - -#define DCN_1_0__SRCID__DMCU_ABM0_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM0_BL_UPDATE_INT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DMCU_ABM0_BL_UPDATE_INT 2 - -#define DCN_1_0__SRCID__DMCU_ABM1_HG_READY_INT 6 // ABM histogram ready interrupt ABM1_HG_READY_INT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DMCU_ABM1_HG_READY_INT 3 - -#define DCN_1_0__SRCID__DMCU_ABM1_LS_READY_INT 6 // ABM luma stat ready interrupt ABM1_LS_READY_INT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DMCU_ABM1_LS_READY_INT 4 - -#define DCN_1_0__SRCID__DMCU_ABM1_BL_UPDATE_INT 6 // ABM Backlight update interrupt ABM1_BL_UPDATE_INT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DMCU_ABM1_BL_UPDATE_INT 5 - -#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT0_STATUS 6 // WB0 perfmon counter0 interrupt WB0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level / Pulse -#define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT0_STATUS 6 - -#define DCN_1_0__SRCID__WB0_PERFCOUNTER_INT1_STATUS 6 // WB0 perfmon counter1 interrupt WB0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE7 Level -#define DCN_1_0__CTXID__WB0_PERFCOUNTER_INT1_STATUS 7 - -#define DCN_1_0__SRCID__DPDBG_FIFO_OVERFLOW_INT 7 // DP debug FIFO overflow interrupt DPDBG_IHC_FIFO_OVERFLOW_INT DISP_INTERRUPT_STATUS_CONTINUE21 Level / Pulse -#define DCN_1_0__CTXID__DPDBG_FIFO_OVERFLOW_INT 1 - -#define DCN_1_0__SRCID__DCIO_DPCS_TXA_ERROR_INT 8 // DPCS TXA error interrupt DCIO_DPCS_TXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse -#define DCN_1_0__CTXID__DCIO_DPCS_TXA_ERROR_INT 0 - -#define DCN_1_0__SRCID__DCIO_DPCS_TXB_ERROR_INT 8 // DPCS TXB error interrupt DCIO_DPCS_TXB_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse -#define DCN_1_0__CTXID__DCIO_DPCS_TXB_ERROR_INT 1 - -#define DCN_1_0__SRCID__DCIO_DPCS_TXC_ERROR_INT 8 // DPCS TXC error interrupt DCIO_DPCS_TXC_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse -#define DCN_1_0__CTXID__DCIO_DPCS_TXC_ERROR_INT 2 - -#define DCN_1_0__SRCID__DCIO_DPCS_TXD_ERROR_INT 8 // DPCS TXD error interrupt DCIO_DPCS_TXD_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse -#define DCN_1_0__CTXID__DCIO_DPCS_TXD_ERROR_INT 3 - -#define DCN_1_0__SRCID__DCIO_DPCS_TXE_ERROR_INT 8 // DPCS TXE error interrupt DCIO_DPCS_TXE_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse -#define DCN_1_0__CTXID__DCIO_DPCS_TXE_ERROR_INT 4 - -#define DCN_1_0__SRCID__DCIO_DPCS_TXF_ERROR_INT 8 // DPCS TXF error interrupt DCIO_DPCS_TXF_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse -#define DCN_1_0__CTXID__DCIO_DPCS_TXF_ERROR_INT 5 - -#define DCN_1_0__SRCID__DCIO_DPCS_TXG_ERROR_INT 8 // DPCS TXG error interrupt DCIO_DPCS_TXG_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse -#define DCN_1_0__CTXID__DCIO_DPCS_TXG_ERROR_INT 6 - -#define DCN_1_0__SRCID__DCIO_DPCS_RXA_ERROR_INT 8 // DPCS RXA error interrupt DCIO_DPCS_RXA_IHC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse -#define DCN_1_0__CTXID__DCIO_DPCS_RXA_ERROR_INT 7 - -#define DCN_1_0__SRCID__DC_HPD1_INT 9 // Hot Plug Detection 1 DC_HPD1_INTERRUPT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DC_HPD1_INT 0 - -#define DCN_1_0__SRCID__DC_HPD2_INT 9 // Hot Plug Detection 2 DC_HPD2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level -#define DCN_1_0__CTXID__DC_HPD2_INT 1 - -#define DCN_1_0__SRCID__DC_HPD3_INT 9 // Hot Plug Detection 3 DC_HPD3_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level -#define DCN_1_0__CTXID__DC_HPD3_INT 2 - -#define DCN_1_0__SRCID__DC_HPD4_INT 9 // Hot Plug Detection 4 DC_HPD4_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level -#define DCN_1_0__CTXID__DC_HPD4_INT 3 - -#define DCN_1_0__SRCID__DC_HPD5_INT 9 // Hot Plug Detection 5 DC_HPD5_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level -#define DCN_1_0__CTXID__DC_HPD5_INT 4 - -#define DCN_1_0__SRCID__DC_HPD6_INT 9 // Hot Plug Detection 6 DC_HPD6_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level -#define DCN_1_0__CTXID__DC_HPD6_INT 5 - -#define DCN_1_0__SRCID__DC_HPD1_RX_INT 9 // Hot Plug Detection RX interrupt 1 DC_HPD1_RX_INTERRUPT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DC_HPD1_RX_INT 6 - -#define DCN_1_0__SRCID__DC_HPD2_RX_INT 9 // Hot Plug Detection RX interrupt 2 DC_HPD2_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level -#define DCN_1_0__CTXID__DC_HPD2_RX_INT 7 - -#define DCN_1_0__SRCID__DC_HPD3_RX_INT 9 // Hot Plug Detection RX interrupt 3 DC_HPD3_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level -#define DCN_1_0__CTXID__DC_HPD3_RX_INT 8 - -#define DCN_1_0__SRCID__DC_HPD4_RX_INT 9 // Hot Plug Detection RX interrupt 4 DC_HPD4_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level -#define DCN_1_0__CTXID__DC_HPD4_RX_INT 9 - -#define DCN_1_0__SRCID__DC_HPD5_RX_INT 9 // Hot Plug Detection RX interrupt 5 DC_HPD5_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level -#define DCN_1_0__CTXID__DC_HPD5_RX_INT 10 - -#define DCN_1_0__SRCID__DC_HPD6_RX_INT 9 // Hot Plug Detection RX interrupt 6 DC_HPD6_RX_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level -#define DCN_1_0__CTXID__DC_HPD6_RX_INT 11 - -#define DCN_1_0__SRCID__DC_DAC_A_AUTO_DET 0xA // DAC A auto - detection DACA_AUTODETECT_GENERITE_INTERRUPT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DC_DAC_A_AUTO_DET 0 - -#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint0 format changed AZ_IHC_ENDPOINT0_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_FMT_CHANGED_INT 2 - -#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint1 format changed AZ_IHC_ENDPOINT1_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_FMT_CHANGED_INT 3 - -#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint2 format changed AZ_IHC_ENDPOINT2_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_FMT_CHANGED_INT 4 - -#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint3 format changed AZ_IHC_ENDPOINT3_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_FMT_CHANGED_INT 5 - -#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint4 format changed AZ_IHC_ENDPOINT4_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_FMT_CHANGED_INT 6 - -#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint5 format changed AZ_IHC_ENDPOINT5_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_FMT_CHANGED_INT 7 - -#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint6 format changed AZ_IHC_ENDPOINT6_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_FMT_CHANGED_INT 8 - -#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 0xA // AZ Endpoint7 format changed AZ_IHC_ENDPOINT7_AUDIO_FORMAT_CHANGED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_FMT_CHANGED_INT 9 - -#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0xB // AZ Endpoint0 enabled AZ_IHC_ENDPOINT0_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_ENABLED_INT 0 - -#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 0xB // AZ Endpoint1 enabled AZ_IHC_ENDPOINT1_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_ENABLED_INT 1 - -#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 0xB // AZ Endpoint2 enabled AZ_IHC_ENDPOINT2_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_ENABLED_INT 2 - -#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 0xB // AZ Endpoint3 enabled AZ_IHC_ENDPOINT3_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_ENABLED_INT 3 - -#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 0xB // AZ Endpoint4 enabled AZ_IHC_ENDPOINT4_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_ENABLED_INT 4 - -#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 0xB // AZ Endpoint5 enabled AZ_IHC_ENDPOINT5_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_ENABLED_INT 5 - -#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 0xB // AZ Endpoint6 enabled AZ_IHC_ENDPOINT6_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_ENABLED_INT 6 - -#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 0xB // AZ Endpoint7 enabled AZ_IHC_ENDPOINT7_AUDIO_ENABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_ENABLED_INT 7 - -#define DCN_1_0__SRCID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0xC // AZ Endpoint0 disabled AZ_IHC_ENDPOINT0_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT0_AUDIO_DISABLED_INT 0 - -#define DCN_1_0__SRCID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 0xC // AZ Endpoint1 disabled AZ_IHC_ENDPOINT1_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT1_AUDIO_DISABLED_INT 1 - -#define DCN_1_0__SRCID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 0xC // AZ Endpoint2 disabled AZ_IHC_ENDPOINT2_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT2_AUDIO_DISABLED_INT 2 - -#define DCN_1_0__SRCID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 0xC // AZ Endpoint3 disabled AZ_IHC_ENDPOINT3_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT3_AUDIO_DISABLED_INT 3 - -#define DCN_1_0__SRCID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 0xC // AZ Endpoint4 disabled AZ_IHC_ENDPOINT4_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT4_AUDIO_DISABLED_INT 4 - -#define DCN_1_0__SRCID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 0xC // AZ Endpoint5 disabled AZ_IHC_ENDPOINT5_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT5_AUDIO_DISABLED_INT 5 - -#define DCN_1_0__SRCID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 0xC // AZ Endpoint6 disabled AZ_IHC_ENDPOINT6_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT6_AUDIO_DISABLED_INT 6 - -#define DCN_1_0__SRCID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 0xC // AZ Endpoint7 disabled AZ_IHC_ENDPOINT7_AUDIO_DISABLED_INT DISP_INTERRUPT_STATUS_CONTINUE19 Level / Pulse -#define DCN_1_0__CTXID__AZ_ENDPOINT7_AUDIO_DISABLED_INT 7 - -#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_LOCK_DONE 0xD // AUX1 GTC sync lock complete AUX1_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_LOCK_DONE 0 - -#define DCN_1_0__SRCID__DC_AUX1_GTC_SYNC_ERROR 0xD // AUX1 GTC sync error occurred AUX1_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX1_GTC_SYNC_ERROR 1 - -#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_LOCK_DONE 0xD // AUX2 GTC sync lock complete AUX2_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_LOCK_DONE 2 - -#define DCN_1_0__SRCID__DC_AUX2_GTC_SYNC_ERROR 0xD // AUX2 GTC sync error occurred AUX2_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX2_GTC_SYNC_ERROR 3 - -#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_LOCK_DONE 0xD // AUX3 GTC sync lock complete AUX3_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_LOCK_DONE 4 - -#define DCN_1_0__SRCID__DC_AUX3_GTC_SYNC_ERROR 0xD // AUX3 GTC sync error occurred AUX3_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX3_GTC_SYNC_ERROR 5 - -#define DCN_1_0__SRCID__DC_DIGA_VID_STRM_DISABLE 0xE // DIGA vid stream disable DIGA_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DC_DIGA_VID_STRM_DISABLE 0 - -#define DCN_1_0__SRCID__DC_DIGB_VID_STRM_DISABLE 0xE // DIGB vid stream disable DIGB_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level -#define DCN_1_0__CTXID__DC_DIGB_VID_STRM_DISABLE 1 - -#define DCN_1_0__SRCID__DC_DIGC_VID_STRM_DISABLE 0xE // DIGC vid stream disable DIGC_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level -#define DCN_1_0__CTXID__DC_DIGC_VID_STRM_DISABLE 2 - -#define DCN_1_0__SRCID__DC_DIGD_VID_STRM_DISABLE 0xE // DIGD vid stream disable DIGD_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level -#define DCN_1_0__CTXID__DC_DIGD_VID_STRM_DISABLE 3 - -#define DCN_1_0__SRCID__DC_DIGE_VID_STRM_DISABLE 0xE // DIGE vid stream disable DIGE_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level -#define DCN_1_0__CTXID__DC_DIGE_VID_STRM_DISABLE 4 - -#define DCN_1_0__SRCID__DC_DIGF_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGF_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level -#define DCN_1_0__CTXID__DC_DIGF_VID_STRM_DISABLE 5 - -#define DCN_1_0__SRCID__DC_DIGG_VID_STRM_DISABLE 0xE // DIGF vid stream disable DIGG_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level -#define DCN_1_0__CTXID__DC_DIGG_VID_STRM_DISABLE 6 - -#define DCN_1_0__SRCID__DC_DIGH_VID_STRM_DISABLE 0xE // DIGH_DP_VID_STREAM_DISABLE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level -#define DCN_1_0__CTXID__DC_DIGH_VID_STRM_DISABLE 7 - -#define DCN_1_0__SRCID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0xF // DIGA - Fast Training Complete DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DC_DIGA_FAST_TRAINING_COMPLETE_INT 0 - -#define DCN_1_0__SRCID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 0xF // DIGB - Fast Training Complete DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level -#define DCN_1_0__CTXID__DC_DIGB_FAST_TRAINING_COMPLETE_INT 1 - -#define DCN_1_0__SRCID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 0xF // DIGC - Fast Training Complete DIGC_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level -#define DCN_1_0__CTXID__DC_DIGC_FAST_TRAINING_COMPLETE_INT 2 - -#define DCN_1_0__SRCID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 0xF // DIGD - Fast Training Complete DIGD_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level -#define DCN_1_0__CTXID__DC_DIGD_FAST_TRAINING_COMPLETE_INT 3 - -#define DCN_1_0__SRCID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 0xF // DIGE - Fast Training Complete DIGE_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level -#define DCN_1_0__CTXID__DC_DIGE_FAST_TRAINING_COMPLETE_INT 4 - -#define DCN_1_0__SRCID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 0xF // DIGF - Fast Training Complete DIGF_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level -#define DCN_1_0__CTXID__DC_DIGF_FAST_TRAINING_COMPLETE_INT 5 - -#define DCN_1_0__SRCID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 0xF // DIGG_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE19 Level -#define DCN_1_0__CTXID__DC_DIGG_FAST_TRAINING_COMPLETE_INT 6 - -#define DCN_1_0__SRCID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 0xF // DIGH_DP_FAST_TRAINING_COMPLETE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE21 Level -#define DCN_1_0__CTXID__DC_DIGH_FAST_TRAINING_COMPLETE_INT 7 - -#define DCN_1_0__SRCID__DC_AUX1_SW_DONE 0x10 // AUX1 sw done AUX1_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DC_AUX1_SW_DONE 0 - -#define DCN_1_0__SRCID__DC_AUX1_LS_DONE 0x10 // AUX1 ls done AUX1_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__DC_AUX1_LS_DONE 1 - -#define DCN_1_0__SRCID__DC_AUX2_SW_DONE 0x10 // AUX2 sw done AUX2_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level -#define DCN_1_0__CTXID__DC_AUX2_SW_DONE 2 - -#define DCN_1_0__SRCID__DC_AUX2_LS_DONE 0x10 // AUX2 ls done AUX2_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level -#define DCN_1_0__CTXID__DC_AUX2_LS_DONE 3 - -#define DCN_1_0__SRCID__DC_AUX3_SW_DONE 0x10 // AUX3 sw done AUX3_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level -#define DCN_1_0__CTXID__DC_AUX3_SW_DONE 4 - -#define DCN_1_0__SRCID__DC_AUX3_LS_DONE 0x10 // AUX3 ls done AUX3_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level -#define DCN_1_0__CTXID__DC_AUX3_LS_DONE 5 - -#define DCN_1_0__SRCID__DC_AUX4_SW_DONE 0x10 // AUX4 sw done AUX4_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level -#define DCN_1_0__CTXID__DC_AUX4_SW_DONE 6 - -#define DCN_1_0__SRCID__DC_AUX4_LS_DONE 0x10 // AUX4 ls done AUX4_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level -#define DCN_1_0__CTXID__DC_AUX4_LS_DONE 7 - -#define DCN_1_0__SRCID__DC_AUX5_SW_DONE 0x10 // AUX5 sw done AUX5_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level -#define DCN_1_0__CTXID__DC_AUX5_SW_DONE 8 - -#define DCN_1_0__SRCID__DC_AUX5_LS_DONE 0x10 // AUX5 ls done AUX5_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level -#define DCN_1_0__CTXID__DC_AUX5_LS_DONE 9 - -#define DCN_1_0__SRCID__DC_AUX6_SW_DONE 0x10 // AUX6 sw done AUX6_SW_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level -#define DCN_1_0__CTXID__DC_AUX6_SW_DONE 10 - -#define DCN_1_0__SRCID__DC_AUX6_LS_DONE 0x10 // AUX6 ls done AUX6_LS_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level -#define DCN_1_0__CTXID__DC_AUX6_LS_DONE 11 - -#define DCN_1_0__SRCID__VGA_CRT_INT 0x10 // VGA Vblank VGA_IHC_VGA_CRT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level -#define DCN_1_0__CTXID__VGA_CRT_INT 12 - -#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT0_STATUS 0x11 // DCCG perfmon2 counter0 interrupt DCCG_PERFMON2_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse -#define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT0_STATUS 0 - -#define DCN_1_0__SRCID__DCCG_PERFCOUNTER2_INT1_STATUS 0x11 // DCCG perfmon2 counter1 interrupt DCCG_PERFMON2_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE10 Level -#define DCN_1_0__CTXID__DCCG_PERFCOUNTER2_INT1_STATUS 1 - -#define DCN_1_0__SRCID__BUFMGR_CWB0_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__BUFMGR_CWB0_IHIF_interrupt 0 - -#define DCN_1_0__SRCID__BUFMGR_CWB1_IHIF_interrupt 0x12 // mcif_wb_client(buffer manager) MCIF_CWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__BUFMGR_CWB1_IHIF_interrupt 1 - -#define DCN_1_0__SRCID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB0_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__MCIF0_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 2 - -#define DCN_1_0__SRCID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 0x12 // MCIF WB client(buffer manager) MCIF_DWB1_IHIF_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__MCIF1_BUFMGR_SW_CONTROL_MCIF_BUFMGR_SW_INT 3 - -#define DCN_1_0__SRCID__SISCL0_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL0_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level -#define DCN_1_0__CTXID__SISCL0_COEF_RAM_CONFLICT_STATUS 4 - -#define DCN_1_0__SRCID__SISCL0_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL0_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level -#define DCN_1_0__CTXID__SISCL0_OVERFLOW_STATUS 5 - -#define DCN_1_0__SRCID__SISCL1_COEF_RAM_CONFLICT_STATUS 0x12 // WB host conflict interrupt WBSCL1_HOST_CONFLICT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level -#define DCN_1_0__CTXID__SISCL1_COEF_RAM_CONFLICT_STATUS 6 - -#define DCN_1_0__SRCID__SISCL1_OVERFLOW_STATUS 0x12 // WB data overflow interrupt WBSCL1_DATA_OVERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level -#define DCN_1_0__CTXID__SISCL1_OVERFLOW_STATUS 7 - -#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_LOCK_DONE 0x13 // AUX4 GTC sync lock complete AUX4_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_LOCK_DONE 0 - -#define DCN_1_0__SRCID__DC_AUX4_GTC_SYNC_ERROR 0x13 // AUX4 GTC sync error occurred AUX4_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX4_GTC_SYNC_ERROR 1 - -#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_LOCK_DONE 0x13 // AUX5 GTC sync lock complete AUX5_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_LOCK_DONE 2 - -#define DCN_1_0__SRCID__DC_AUX5_GTC_SYNC_ERROR 0x13 // AUX5 GTC sync error occurred AUX5_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX5_GTC_SYNC_ERROR 3 - -#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_LOCK_DONE 0x13 // AUX6 GTC sync lock complete AUX6_GTC_SYNC_LOCK_DONE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_LOCK_DONE 4 - -#define DCN_1_0__SRCID__DC_AUX6_GTC_SYNC_ERROR 0x13 // AUX6 GTC sync error occurred AUX6_GTC_SYNC_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE6 Level -#define DCN_1_0__CTXID__DC_AUX6_GTC_SYNC_ERROR 5 - -#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_UP_INT 0x14 // Display pipe0 power up interrupt DCPG_IHC_DOMAIN0_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__DCPG_DCFE0_POWER_UP_INT 0 - -#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_UP_INT 0x14 // Display pipe1 power up interrupt DCPG_IHC_DOMAIN1_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__DCPG_DCFE1_POWER_UP_INT 1 - -#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_UP_INT 0x14 // Display pipe2 power up interrupt DCPG_IHC_DOMAIN2_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__DCPG_DCFE2_POWER_UP_INT 2 - -#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_UP_INT 0x14 // Display pipe3 power up interrupt DCPG_IHC_DOMAIN3_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__DCPG_DCFE3_POWER_UP_INT 3 - -#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_UP_INT 0x14 // Display pipe4 power up interrupt DCPG_IHC_DOMAIN4_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__DCPG_DCFE4_POWER_UP_INT 4 - -#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_UP_INT 0x14 // Display pipe5 power up interrupt DCPG_IHC_DOMAIN5_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__DCPG_DCFE5_POWER_UP_INT 5 - -#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_UP_INT 0x14 // Display pipe6 power up interrupt DCPG_IHC_DOMAIN6_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__DCPG_DCFE6_POWER_UP_INT 6 - -#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_UP_INT 0x14 // Display pipe7 power up interrupt DCPG_IHC_DOMAIN7_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__DCPG_DCFE7_POWER_UP_INT 7 - -#define DCN_1_0__SRCID__DCPG_DCFE0_POWER_DOWN_INT 0x14 // Display pipe0 power down interrupt DCPG_IHC_DOMAIN0_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level -#define DCN_1_0__CTXID__DCPG_DCFE0_POWER_DOWN_INT 8 - -#define DCN_1_0__SRCID__DCPG_DCFE1_POWER_DOWN_INT 0x14 // Display pipe1 power down interrupt DCPG_IHC_DOMAIN1_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level -#define DCN_1_0__CTXID__DCPG_DCFE1_POWER_DOWN_INT 9 - -#define DCN_1_0__SRCID__DCPG_DCFE2_POWER_DOWN_INT 0x14 // Display pipe2 power down interrupt DCPG_IHC_DOMAIN2_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level -#define DCN_1_0__CTXID__DCPG_DCFE2_POWER_DOWN_INT 10 - -#define DCN_1_0__SRCID__DCPG_DCFE3_POWER_DOWN_INT 0x14 // Display pipe3 power down interrupt DCPG_IHC_DOMAIN3_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level -#define DCN_1_0__CTXID__DCPG_DCFE3_POWER_DOWN_INT 11 - -#define DCN_1_0__SRCID__DCPG_DCFE4_POWER_DOWN_INT 0x14 // Display pipe4 power down interrupt DCPG_IHC_DOMAIN4_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level -#define DCN_1_0__CTXID__DCPG_DCFE4_POWER_DOWN_INT 12 - -#define DCN_1_0__SRCID__DCPG_DCFE5_POWER_DOWN_INT 0x14 // Display pipe5 power down interrupt DCPG_IHC_DOMAIN5_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level -#define DCN_1_0__CTXID__DCPG_DCFE5_POWER_DOWN_INT 13 - -#define DCN_1_0__SRCID__DCPG_DCFE6_POWER_DOWN_INT 0x14 // Display pipe6 power down interrupt DCPG_IHC_DOMAIN6_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level -#define DCN_1_0__CTXID__DCPG_DCFE6_POWER_DOWN_INT 14 - -#define DCN_1_0__SRCID__DCPG_DCFE7_POWER_DOWN_INT 0x14 // Display pipe7 power down interrupt DCPG_IHC_DOMAIN7_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level -#define DCN_1_0__CTXID__DCPG_DCFE7_POWER_DOWN_INT 15 - -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg0_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG0_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level -#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg0_latch_int 0 - -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg1_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG1_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level -#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg1_latch_int 1 - -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg2_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG2_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level -#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg2_latch_int 2 - -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg3_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG3_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level -#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg3_latch_int 3 - -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg4_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG4_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level -#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg4_latch_int 4 - -#define DCN_1_0__SRCID__DCCG_IHC_VSYNC_otg5_latch_int 0x15 // an interrupt that is triggered when the time(number of refclk cycles) of a programmable number of frames is counted.The counting starts / end at VSYNC rising edge or falling edge.DCCG_IHC_VSYNC_OTG5_LATCH_INT DISP_INTERRUPT_STATUS_CONTINUE10 Level -#define DCN_1_0__CTXID__DCCG_IHC_VSYNC_otg5_latch_int 5 - -#define DCN_1_0__SRCID__OPTC0_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC1_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS Level -#define DCN_1_0__CTXID__OPTC0_DATA_UNDERFLOW_INT 6 - -#define DCN_1_0__SRCID__OPTC1_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC2_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level -#define DCN_1_0__CTXID__OPTC1_DATA_UNDERFLOW_INT 7 - -#define DCN_1_0__SRCID__OPTC2_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC3_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level -#define DCN_1_0__CTXID__OPTC2_DATA_UNDERFLOW_INT 8 - -#define DCN_1_0__SRCID__OPTC3_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC4_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level -#define DCN_1_0__CTXID__OPTC3_DATA_UNDERFLOW_INT 9 - -#define DCN_1_0__SRCID__OPTC4_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC5_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level -#define DCN_1_0__CTXID__OPTC4_DATA_UNDERFLOW_INT 10 - -#define DCN_1_0__SRCID__OPTC5_DATA_UNDERFLOW_INT 0x15 // D0 ODM data underflow interrupt OPTC6_DATA_UNDERFLOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level -#define DCN_1_0__CTXID__OPTC5_DATA_UNDERFLOW_INT 11 - -#define DCN_1_0__SRCID__MPCC0_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC0_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level -#define DCN_1_0__CTXID__MPCC0_STALL_INTERRUPT 0 - -#define DCN_1_0__SRCID__MPCC1_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC1_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level -#define DCN_1_0__CTXID__MPCC1_STALL_INTERRUPT 1 - -#define DCN_1_0__SRCID__MPCC2_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC2_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level -#define DCN_1_0__CTXID__MPCC2_STALL_INTERRUPT 2 - -#define DCN_1_0__SRCID__MPCC3_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC3_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level -#define DCN_1_0__CTXID__MPCC3_STALL_INTERRUPT 3 - -#define DCN_1_0__SRCID__MPCC4_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC4_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level -#define DCN_1_0__CTXID__MPCC4_STALL_INTERRUPT 4 - -#define DCN_1_0__SRCID__MPCC5_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC5_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level -#define DCN_1_0__CTXID__MPCC5_STALL_INTERRUPT 5 - -#define DCN_1_0__SRCID__MPCC6_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC6_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level -#define DCN_1_0__CTXID__MPCC6_STALL_INTERRUPT 6 - -#define DCN_1_0__SRCID__MPCC7_STALL_INTERRUPT 0x16 // Indicate no pixel was available to be sent when OPP asked for MPCC7_STALL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level -#define DCN_1_0__CTXID__MPCC7_STALL_INTERRUPT 7 - -#define DCN_1_0__SRCID__OTG1_CPU_SS_INT 0x17 // D1: OTG Static Screen interrupt OTG1_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__OTG1_CPU_SS_INT 0 - -#define DCN_1_0__SRCID__OTG1_RANGE_TIMING_UPDATE 0x17 // D1 : OTG range timing OTG1_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse -#define DCN_1_0__CTXID__OTG1_RANGE_TIMING_UPDATE 1 - -#define DCN_1_0__SRCID__OTG2_CPU_SS_INT 0x17 // D2 : OTG Static Screen interrupt OTG2_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__OTG2_CPU_SS_INT 2 - -#define DCN_1_0__SRCID__OTG2_RANGE_TIMING_UPDATE 0x17 // D2 : OTG range timing OTG2_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse -#define DCN_1_0__CTXID__OTG2_RANGE_TIMING_UPDATE 3 - -#define DCN_1_0__SRCID__OTG3_CPU_SS_INT 0x17 // D3 : OTG Static Screen interrupt OTG3_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__OTG3_CPU_SS_INT 4 - -#define DCN_1_0__SRCID__OTG3_RANGE_TIMING_UPDATE 0x17 // D3 : OTG range timing OTG3_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse -#define DCN_1_0__CTXID__OTG3_RANGE_TIMING_UPDATE 5 - -#define DCN_1_0__SRCID__OTG4_CPU_SS_INT 0x17 // D4 : OTG Static Screen interrupt OTG4_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__OTG4_CPU_SS_INT 6 - -#define DCN_1_0__SRCID__OTG4_RANGE_TIMING_UPDATE 0x17 // D4 : OTG range timing OTG4_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse -#define DCN_1_0__CTXID__OTG4_RANGE_TIMING_UPDATE 7 - -#define DCN_1_0__SRCID__OTG5_CPU_SS_INT 0x17 // D5 : OTG Static Screen interrupt OTG5_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__OTG5_CPU_SS_INT 8 - -#define DCN_1_0__SRCID__OTG5_RANGE_TIMING_UPDATE 0x17 // D5 : OTG range timing OTG5_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse -#define DCN_1_0__CTXID__OTG5_RANGE_TIMING_UPDATE 9 - -#define DCN_1_0__SRCID__OTG6_CPU_SS_INT 0x17 // D6 : OTG Static Screen interrupt OTG6_IHC_CPU_SS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__OTG6_CPU_SS_INT 10 - -#define DCN_1_0__SRCID__OTG6_RANGE_TIMING_UPDATE 0x17 // D6 : OTG range timing OTG6_IHC_RANGE_TIMING_UPDATE DISP_INTERRUPT_STATUS_CONTINUE10 Level / Pulse -#define DCN_1_0__CTXID__OTG6_RANGE_TIMING_UPDATE 11 - -#define DCN_1_0__SRCID__DC_D1_OTG_V_UPDATE 0x18 // D1 : OTG V_update OTG1_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D2_OTG_V_UPDATE 0x19 // D2 : OTG V_update OTG2_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D3_OTG_V_UPDATE 0x1A // D3 : OTG V_update OTG3_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D4_OTG_V_UPDATE 0x1B // D4 : OTG V_update OTG4_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D5_OTG_V_UPDATE 0x1C // D5 : OTG V_update OTG5_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D6_OTG_V_UPDATE 0x1D // D6 : OTG V_update OTG6_IHC_V_UPDATE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse - -#define DCN_1_0__SRCID__DC_D1_OTG_SNAPSHOT 0x1E // D1 : OTG snapshot OTG1_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse -#define DCN_1_0__CTXID__DC_D1_OTG_SNAPSHOT 0 - -#define DCN_1_0__SRCID__DC_D1_FORCE_CNT_W 0x1E // D1 : Force - count--w OTG1_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse -#define DCN_1_0__CTXID__DC_D1_FORCE_CNT_W 1 - -#define DCN_1_0__SRCID__DC_D1_FORCE_VSYNC_NXT_LINE 0x1E // D1 : Force - Vsync - next - line OTG1_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse -#define DCN_1_0__CTXID__DC_D1_FORCE_VSYNC_NXT_LINE 2 - -#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_A 0x1E // D1 : OTG external trigger A OTG1_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse -#define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_A 3 - -#define DCN_1_0__SRCID__DC_D1_OTG_EXTT_TRG_B 0x1E // D1 : OTG external trigger B OTG1_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse -#define DCN_1_0__CTXID__DC_D1_OTG_EXTT_TRG_B 4 - -#define DCN_1_0__SRCID__DC_D1_OTG_GSL_VSYNC_GAP 0x1E // D1 : gsl_vsync_gap_interrupt_frame_delay OTG1_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__DC_D1_OTG_GSL_VSYNC_GAP 5 - -#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL 0x1E // D1 : OTG vertical interrupt 0 OTG1_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT0_CONTROL 6 - -#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT1_CONTROL 0x1E // D1 : OTG vertical interrupt 1 OTG1_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT1_CONTROL 7 - -#define DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT2_CONTROL 0x1E // D1 : OTG vertical interrupt 2 OTG1_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__OTG1_VERTICAL_INTERRUPT2_CONTROL 8 - -#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync loss interrupt OTG1_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 - -#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync interrupt OTG1_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 - -#define DCN_1_0__SRCID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1E // D1 : OTG ext sync signal interrupt OTG1_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__OTG1_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 - -#define DCN_1_0__SRCID__OTG1_SET_VTOTAL_MIN_EVENT_INT 0x1E // D1 : OTG DRR event occurred interrupt OTG1_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS Level / Pulse -#define DCN_1_0__CTXID__OTG1_SET_VTOTAL_MIN_EVENT_INT 12 - -#define DCN_1_0__SRCID__DC_D2_OTG_SNAPSHOT 0x1F // D2 : OTG snapshot OTG2_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__DC_D2_OTG_SNAPSHOT 0 - -#define DCN_1_0__SRCID__DC_D2_FORCE_CNT_W 0x1F // D2 : Force - count--w OTG2_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__DC_D2_FORCE_CNT_W 1 - -#define DCN_1_0__SRCID__DC_D2_FORCE_VSYNC_NXT_LINE 0x1F // D2 : Force - Vsync - next - line OTG2_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__DC_D2_FORCE_VSYNC_NXT_LINE 2 - -#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_A 0x1F // D2 : OTG external trigger A OTG2_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_A 3 - -#define DCN_1_0__SRCID__DC_D2_OTG_EXTT_TRG_B 0x1F // D2 : OTG external trigger B OTG2_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__DC_D2_OTG_EXTT_TRG_B 4 - -#define DCN_1_0__SRCID__DC_D2_OTG_GSL_VSYNC_GAP 0x1F // D2 : gsl_vsync_gap_interrupt_frame_delay OTG2_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__DC_D2_OTG_GSL_VSYNC_GAP 5 - -#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL 0x1F // D2 : OTG vertical interrupt 0 OTG2_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT0_CONTROL 6 - -#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT1_CONTROL 0x1F // D2 : OTG vertical interrupt 1 OTG2_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT1_CONTROL 7 - -#define DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT2_CONTROL 0x1F // D2 : OTG vertical interrupt 2 OTG2_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__OTG2_VERTICAL_INTERRUPT2_CONTROL 8 - -#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync loss interrupt OTG2_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 - -#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync interrupt OTG2_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 - -#define DCN_1_0__SRCID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x1F // D2 : OTG ext sync signal interrupt OTG2_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__OTG2_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 - -#define DCN_1_0__SRCID__OTG2_SET_VTOTAL_MIN_EVENT_INT 0x1F // D2 : OTG DRR event occurred interrupt OTG2_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__CTXID__OTG2_SET_VTOTAL_MIN_EVENT_INT 12 - -#define DCN_1_0__SRCID__DC_D3_OTG_SNAPSHOT 0x20 // D3 : OTG snapshot OTG3_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__DC_D3_OTG_SNAPSHOT 0 - -#define DCN_1_0__SRCID__DC_D3_FORCE_CNT_W 0x20 // D3 : Force - count--w OTG3_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__DC_D3_FORCE_CNT_W 1 - -#define DCN_1_0__SRCID__DC_D3_FORCE_VSYNC_NXT_LINE 0x20 // D3 : Force - Vsync - next - line OTG3_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__DC_D3_FORCE_VSYNC_NXT_LINE 2 - -#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_A 0x20 // D3 : OTG external trigger A OTG3_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_A 3 - -#define DCN_1_0__SRCID__DC_D3_OTG_EXTT_TRG_B 0x20 // D3 : OTG external trigger B OTG3_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__DC_D3_OTG_EXTT_TRG_B 4 - -#define DCN_1_0__SRCID__DC_D3_OTG_GSL_VSYNC_GAP 0x20 // D3 : gsl_vsync_gap_interrupt_frame_delay OTG3_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__DC_D3_OTG_GSL_VSYNC_GAP 5 - -#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL 0x20 // D3 : OTG vertical interrupt 0 OTG3_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT0_CONTROL 6 - -#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT1_CONTROL 0x20 // D3 : OTG vertical interrupt 1 OTG3_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT1_CONTROL 7 - -#define DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT2_CONTROL 0x20 // D3 : OTG vertical interrupt 2 OTG3_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__OTG3_VERTICAL_INTERRUPT2_CONTROL 8 - -#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync loss interrupt OTG3_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 - -#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync interrupt OTG3_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 - -#define DCN_1_0__SRCID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x20 // D3 : OTG ext sync signal interrupt OTG3_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__OTG3_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 - -#define DCN_1_0__SRCID__OTG3_SET_VTOTAL_MIN_EVENT_INT 0x20 // D3 : OTG DRR event occurred interrupt OTG3_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__CTXID__OTG3_SET_VTOTAL_MIN_EVENT_INT 12 - -#define DCN_1_0__SRCID__DC_D4_OTG_SNAPSHOT 0x21 // D4 : OTG snapshot OTG4_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__DC_D4_OTG_SNAPSHOT 0 - -#define DCN_1_0__SRCID__DC_D4_FORCE_CNT_W 0x21 // D4 : Force - count--w OTG4_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__DC_D4_FORCE_CNT_W 1 - -#define DCN_1_0__SRCID__DC_D4_FORCE_VSYNC_NXT_LINE 0x21 // D4 : Force - Vsync - next - line OTG4_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__DC_D4_FORCE_VSYNC_NXT_LINE 2 - -#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_A 0x21 // D4 : OTG external trigger A OTG4_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_A 3 - -#define DCN_1_0__SRCID__DC_D4_OTG_EXTT_TRG_B 0x21 // D4 : OTG external trigger B OTG4_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__DC_D4_OTG_EXTT_TRG_B 4 - -#define DCN_1_0__SRCID__DC_D4_OTG_GSL_VSYNC_GAP 0x21 // D4 : gsl_vsync_gap_interrupt_frame_delay OTG4_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__DC_D4_OTG_GSL_VSYNC_GAP 5 - -#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL 0x21 // D4 : OTG vertical interrupt 0 OTG4_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT0_CONTROL 6 - -#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT1_CONTROL 0x21 // D4 : OTG vertical interrupt 1 OTG4_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT1_CONTROL 7 - -#define DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT2_CONTROL 0x21 // D4 : OTG vertical interrupt 2 OTG4_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__OTG4_VERTICAL_INTERRUPT2_CONTROL 8 - -#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync loss interrupt OTG4_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 - -#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync interrupt OTG4_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 - -#define DCN_1_0__SRCID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x21 // D4 : OTG ext sync signal interrupt OTG4_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__OTG4_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 - -#define DCN_1_0__SRCID__OTG4_SET_VTOTAL_MIN_EVENT_INT 0x21 // D4 : OTG DRR event occurred interrupt OTG4_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__CTXID__OTG4_SET_VTOTAL_MIN_EVENT_INT 12 - -#define DCN_1_0__SRCID__DC_D5_OTG_SNAPSHOT 0x22 // D5 : OTG snapshot OTG5_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__DC_D5_OTG_SNAPSHOT 0 - -#define DCN_1_0__SRCID__DC_D5_FORCE_CNT_W 0x22 // D5 : Force - count--w OTG5_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__DC_D5_FORCE_CNT_W 1 - -#define DCN_1_0__SRCID__DC_D5_FORCE_VSYNC_NXT_LINE 0x22 // D5 : Force - Vsync - next - line OTG5_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__DC_D5_FORCE_VSYNC_NXT_LINE 2 - -#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_A 0x22 // D5 : OTG external trigger A OTG5_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_A 3 - -#define DCN_1_0__SRCID__DC_D5_OTG_EXTT_TRG_B 0x22 // D5 : OTG external trigger B OTG5_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__DC_D5_OTG_EXTT_TRG_B 4 - -#define DCN_1_0__SRCID__DC_D5_OTG_GSL_VSYNC_GAP 0x22 // D5 : gsl_vsync_gap_interrupt_frame_delay OTG5_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__DC_D5_OTG_GSL_VSYNC_GAP 5 - -#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL 0x22 // D5 : OTG vertical interrupt 0 OTG5_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT0_CONTROL 6 - -#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT1_CONTROL 0x22 // D5 : OTG vertical interrupt 1 OTG5_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT1_CONTROL 7 - -#define DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT2_CONTROL 0x22 // D5 : OTG vertical interrupt 2 OTG5_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__OTG5_VERTICAL_INTERRUPT2_CONTROL 8 - -#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync loss interrupt OTG5_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 - -#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync interrupt OTG5_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 - -#define DCN_1_0__SRCID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x22 // D5 : OTG ext sync signal interrupt OTG5_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__OTG5_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 - -#define DCN_1_0__SRCID__OTG5_SET_VTOTAL_MIN_EVENT_INT 0x22 // D5 : OTG DRR event occurred interrupt OTG5_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__CTXID__OTG5_SET_VTOTAL_MIN_EVENT_INT 12 - -#define DCN_1_0__SRCID__DC_D1_VBLANK 0x23 // D1 : VBlank HUBP0_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse -#define DCN_1_0__CTXID__DC_D1_VBLANK 0 - -#define DCN_1_0__SRCID__DC_D1_VLINE1 0x23 // D1 : Vline HUBP0_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse -#define DCN_1_0__CTXID__DC_D1_VLINE1 1 - -#define DCN_1_0__SRCID__DC_D1_VLINE2 0x23 // D1 : Vline2 HUBP0_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse -#define DCN_1_0__CTXID__DC_D1_VLINE2 2 - -#define DCN_1_0__SRCID__DC_D2_VBLANK 0x23 // D2 : Vblank HUBP1_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse -#define DCN_1_0__CTXID__DC_D2_VBLANK 3 - -#define DCN_1_0__SRCID__DC_D2_VLINE1 0x23 // D2 : Vline HUBP1_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse -#define DCN_1_0__CTXID__DC_D2_VLINE1 4 - -#define DCN_1_0__SRCID__DC_D2_VLINE2 0x23 // D2 : Vline2 HUBP1_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse -#define DCN_1_0__CTXID__DC_D2_VLINE2 5 - -#define DCN_1_0__SRCID__HUBP0_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP0_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__HUBP0_IHC_VM_CONTEXT_ERROR 6 - -#define DCN_1_0__SRCID__HUBP1_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP1_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level -#define DCN_1_0__CTXID__HUBP1_IHC_VM_CONTEXT_ERROR 7 - -#define DCN_1_0__SRCID__HUBP2_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP2_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level -#define DCN_1_0__CTXID__HUBP2_IHC_VM_CONTEXT_ERROR 8 - -#define DCN_1_0__SRCID__HUBP3_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP3_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level -#define DCN_1_0__CTXID__HUBP3_IHC_VM_CONTEXT_ERROR 9 - -#define DCN_1_0__SRCID__HUBP4_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP4_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level -#define DCN_1_0__CTXID__HUBP4_IHC_VM_CONTEXT_ERROR 10 - -#define DCN_1_0__SRCID__HUBP5_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP5_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level -#define DCN_1_0__CTXID__HUBP5_IHC_VM_CONTEXT_ERROR 11 - -#define DCN_1_0__SRCID__HUBP6_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP6_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level -#define DCN_1_0__CTXID__HUBP6_IHC_VM_CONTEXT_ERROR 12 - -#define DCN_1_0__SRCID__HUBP7_IHC_VM_CONTEXT_ERROR 0x23 // "Reports three types of fault that may occur during memory address translation in HUBPREQ: HUBP7_IHC_VM_CONTEXT_ERROR_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level -#define DCN_1_0__CTXID__HUBP7_IHC_VM_CONTEXT_ERROR 13 - -#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT0_STATUS 0x24 // DPP0 perfmon counter0 interrupt DPP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse -#define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__DPP0_PERFCOUNTER_INT1_STATUS 0x24 // DPP0 perfmon counter1 interrupt DPP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level -#define DCN_1_0__CTXID__DPP0_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__DC_D3_VBLANK 0x24 // D3 : VBlank HUBP2_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse -#define DCN_1_0__CTXID__DC_D3_VBLANK 9 - -#define DCN_1_0__SRCID__DC_D3_VLINE1 0x24 // D3 : Vline HUBP2_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse -#define DCN_1_0__CTXID__DC_D3_VLINE1 10 - -#define DCN_1_0__SRCID__DC_D3_VLINE2 0x24 // D3 : Vline2 HUBP2_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse -#define DCN_1_0__CTXID__DC_D3_VLINE2 11 - -#define DCN_1_0__SRCID__DC_D4_VBLANK 0x24 // D4 : Vblank HUBP3_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D4_VBLANK 12 - -#define DCN_1_0__SRCID__DC_D4_VLINE1 0x24 // D4 : Vline HUBP3_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D4_VLINE1 13 - -#define DCN_1_0__SRCID__DC_D4_VLINE2 0x24 // D4 : Vline2 HUBP3_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D4_VLINE2 14 - -#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT0_STATUS 0x25 // DPP1 perfmon counter0 interrupt DPP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse -#define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__DPP1_PERFCOUNTER_INT1_STATUS 0x25 // DPP1 perfmon counter1 interrupt DPP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level -#define DCN_1_0__CTXID__DPP1_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__DC_D5_VBLANK 0x25 // D5 : VBlank HUBP4_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D5_VBLANK 9 - -#define DCN_1_0__SRCID__DC_D5_VLINE1 0x25 // D5 : Vline HUBP4_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D5_VLINE1 10 - -#define DCN_1_0__SRCID__DC_D5_VLINE2 0x25 // D5 : Vline2 HUBP4_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D5_VLINE2 11 - -#define DCN_1_0__SRCID__DC_D6_VBLANK 0x25 // D6 : Vblank HUBP5_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D6_VBLANK 12 - -#define DCN_1_0__SRCID__DC_D6_VLINE1 0x25 // D6 : Vline HUBP5_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D6_VLINE1 13 - -#define DCN_1_0__SRCID__DC_D6_VLINE2 0x25 // D6 : Vline2 HUBP5_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D6_VLINE2 14 - -#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT0_STATUS 0x26 // DPP2 perfmon counter0 interrupt DPP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level / Pulse -#define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__DPP2_PERFCOUNTER_INT1_STATUS 0x26 // DPP2 perfmon counter1 interrupt DPP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE8 Level -#define DCN_1_0__CTXID__DPP2_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__DC_D7_VBLANK 0x26 // D7 : VBlank HUBP6_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D7_VBLANK 9 - -#define DCN_1_0__SRCID__DC_D7_VLINE1 0x26 // D7 : Vline HUBP6_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D7_VLINE1 10 - -#define DCN_1_0__SRCID__DC_D7_VLINE2 0x26 // D7 : Vline2 HUBP6_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D7_VLINE2 11 - -#define DCN_1_0__SRCID__DC_D8_VBLANK 0x26 // D8 : Vblank HUBP7_IHC_VBLANK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D8_VBLANK 12 - -#define DCN_1_0__SRCID__DC_D8_VLINE1 0x26 // D8 : Vline HUBP7_IHC_VLINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D8_VLINE1 13 - -#define DCN_1_0__SRCID__DC_D8_VLINE2 0x26 // D8 : Vline2 HUBP7_IHC_VLINE2_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__DC_D8_VLINE2 14 - -#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT0_STATUS 0x27 // DPP3 perfmon counter0 interrupt DPP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse -#define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__DPP3_PERFCOUNTER_INT1_STATUS 0x27 // DPP3 perfmon counter1 interrupt DPP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level -#define DCN_1_0__CTXID__DPP3_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT0_STATUS 0x28 // DPP4 perfmon counter0 interrupt DPP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse -#define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__DPP4_PERFCOUNTER_INT1_STATUS 0x28 // DPP4 perfmon counter1 interrupt DPP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level -#define DCN_1_0__CTXID__DPP4_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT0_STATUS 0x29 // DPP5 perfmon counter0 interrupt DPP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level / Pulse -#define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__DPP5_PERFCOUNTER_INT1_STATUS 0x29 // DPP5 perfmon counter1 interrupt DPP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE9 Level -#define DCN_1_0__CTXID__DPP5_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT0_STATUS 0x2A // DPP6 perfmon counter0 interrupt DPP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse -#define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__DPP6_PERFCOUNTER_INT1_STATUS 0x2A // DPP6 perfmon counter1 interrupt DPP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level -#define DCN_1_0__CTXID__DPP6_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT0_STATUS 0x2B // DPP7 perfmon counter0 interrupt DPP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse -#define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__DPP7_PERFCOUNTER_INT1_STATUS 0x2B // DPP7 perfmon counter1 interrupt DPP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level -#define DCN_1_0__CTXID__DPP7_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT0_STATUS 0x2C // HUBP0 perfmon counter0 interrupt HUBP0_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse -#define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__HUBP0_PERFCOUNTER_INT1_STATUS 0x2C // HUBP0 perfmon counter1 interrupt HUBP0_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__HUBP0_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT0_STATUS 0x2D // HUBP1 perfmon counter0 interrupt HUBP1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse -#define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__HUBP1_PERFCOUNTER_INT1_STATUS 0x2D // HUBP1 perfmon counter1 interrupt HUBP1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level -#define DCN_1_0__CTXID__HUBP1_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT0_STATUS 0x2E // HUBP2 perfmon counter0 interrupt HUBP2_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse -#define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__HUBP2_PERFCOUNTER_INT1_STATUS 0x2E // HUBP2 perfmon counter1 interrupt HUBP2_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level -#define DCN_1_0__CTXID__HUBP2_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT0_STATUS 0x2F // HUBP3 perfmon counter0 interrupt HUBP3_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level / Pulse -#define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__HUBP3_PERFCOUNTER_INT1_STATUS 0x2F // HUBP3 perfmon counter1 interrupt HUBP3_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE14 Level -#define DCN_1_0__CTXID__HUBP3_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT0_STATUS 0x30 // HUBP4 perfmon counter0 interrupt HUBP4_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse -#define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__HUBP4_PERFCOUNTER_INT1_STATUS 0x30 // HUBP4 perfmon counter1 interrupt HUBP4_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level -#define DCN_1_0__CTXID__HUBP4_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT0_STATUS 0x31 // HUBP5 perfmon counter0 interrupt HUBP5_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse -#define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__HUBP5_PERFCOUNTER_INT1_STATUS 0x31 // HUBP5 perfmon counter1 interrupt HUBP5_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level -#define DCN_1_0__CTXID__HUBP5_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT0_STATUS 0x32 // HUBP6 perfmon counter0 interrupt HUBP6_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level / Pulse -#define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__HUBP6_PERFCOUNTER_INT1_STATUS 0x32 // HUBP6 perfmon counter1 interrupt HUBP6_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE15 Level -#define DCN_1_0__CTXID__HUBP6_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT0_STATUS 0x33 // HUBP7 perfmon counter0 interrupt HUBP7_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level / Pulse -#define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__HUBP7_PERFCOUNTER_INT1_STATUS 0x33 // HUBP7 perfmon counter1 interrupt HUBP7_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE16 Level -#define DCN_1_0__CTXID__HUBP7_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT0_STATUS 0x34 // WB1 perfmon counter0 interrupt WB1_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level / Pulse -#define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__WB1_PERFCOUNTER_INT1_STATUS 0x34 // WB1 perfmon counter1 interrupt WB1_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE11 Level -#define DCN_1_0__CTXID__WB1_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT0_STATUS 0x35 // HUBBUB perfmon counter0 interrupt HUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level / Pulse -#define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__HUBBUB_PERFCOUNTER_INT1_STATUS 0x35 // HUBBUB perfmon counter1 interrupt HUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE13 Level -#define DCN_1_0__CTXID__HUBBUB_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT0_STATUS 0x36 // MPC perfmon counter0 interrupt MPC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level / Pulse -#define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__MPC_PERFCOUNTER_INT1_STATUS 0x36 // MPC perfmon counter1 interrupt MPC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE12 Level -#define DCN_1_0__CTXID__MPC_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT0_STATUS 0x37 // OPP perfmon counter0 interrupt OPP_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__OPP_PERFCOUNTER_INT1_STATUS 0x37 // OPP perfmon counter1 interrupt OPP_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level -#define DCN_1_0__CTXID__OPP_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__DC_D6_OTG_SNAPSHOT 0x38 // D6: OTG snapshot OTG6_IHC_SNAPSHOT_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__DC_D6_OTG_SNAPSHOT 0 - -#define DCN_1_0__SRCID__DC_D6_FORCE_CNT_W 0x38 // D6 : Force - count--w OTG6_IHC_FORCE_COUNT_NOW_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__DC_D6_FORCE_CNT_W 1 - -#define DCN_1_0__SRCID__DC_D6_FORCE_VSYNC_NXT_LINE 0x38 // D6 : Force - Vsync - next - line OTG6_IHC_FORCE_VSYNC_NEXT_LINE_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__DC_D6_FORCE_VSYNC_NXT_LINE 2 - -#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_A 0x38 // D6 : OTG external trigger A OTG6_IHC_TRIGA_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_A 3 - -#define DCN_1_0__SRCID__DC_D6_OTG_EXTT_TRG_B 0x38 // D6 : OTG external trigger B OTG6_IHC_TRIGB_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__DC_D6_OTG_EXTT_TRG_B 4 - -#define DCN_1_0__SRCID__DC_D6_OTG_GSL_VSYNC_GAP 0x38 // D6 : gsl_vsync_gap_interrupt_frame_delay OTG6_IHC_GSL_VSYNC_GAP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__CTXID__DC_D6_OTG_GSL_VSYNC_GAP 5 - -#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL 0x38 // D6 : OTG vertical interrupt 0 OTG6_IHC_VERTICAL_INTERRUPT0 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT0_CONTROL 6 - -#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT1_CONTROL 0x38 // D6 : OTG vertical interrupt 1 OTG6_IHC_VERTICAL_INTERRUPT1 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT1_CONTROL 7 - -#define DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT2_CONTROL 0x38 // D6 : OTG vertical interrupt 2 OTG6_IHC_VERTICAL_INTERRUPT2 DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__OTG6_VERTICAL_INTERRUPT2_CONTROL 8 - -#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync loss interrupt OTG6_IHC_EXT_TIMING_SYNC_LOSS_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_LOSS_INTERRUPT_CONTROL 9 - -#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync interrupt OTG6_IHC_EXT_TIMING_SYNC_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_INTERRUPT_CONTROL 10 - -#define DCN_1_0__SRCID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 0x38 // D6 : OTG ext sync signal interrupt OTG6_IHC_EXT_TIMING_SYNC_SIGNAL_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__OTG6_EXT_TIMING_SYNC_SIGNAL_INTERRUPT_CONTROL 11 - -#define DCN_1_0__SRCID__OTG6_SET_VTOTAL_MIN_EVENT_INT 0x38 // D : OTG DRR event occurred interrupt OTG6_IHC_SET_V_TOTAL_MIN_EVENT_OCCURED_INT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse -#define DCN_1_0__CTXID__OTG6_SET_VTOTAL_MIN_EVENT_INT 12 - -#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT0_STATUS 0x39 // OPTC perfmon counter0 interrupt OPTC_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__OPTC_PERFCOUNTER_INT1_STATUS 0x39 // OPTC perfmon counter1 interrupt OPTC_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level -#define DCN_1_0__CTXID__OPTC_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0x3A // MMHUBBUB perfmon counter0 interrupt MMHUBBUB_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 0x3A // MMHUBBUB perfmon counter1 interrupt MMHUBBUB_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level -#define DCN_1_0__CTXID__MMHUBBUB_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT0_STATUS 0x3B // AZ perfmon counter0 interrupt AZ_PERFMON_COUNTER0_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level / Pulse -#define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT0_STATUS 0 - -#define DCN_1_0__SRCID__AZ_PERFCOUNTER_INT1_STATUS 0x3B // AZ perfmon counter1 interrupt AZ_PERFMON_COUNTER1_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE18 Level -#define DCN_1_0__CTXID__AZ_PERFCOUNTER_INT1_STATUS 1 - -#define DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP 0x3C // "OTG0 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG1_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP 0x3D // "OTG1 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG2_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP 0x3E // "OTG2 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG3_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP 0x3F // "OTG3 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG4_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP 0x40 // "OTG4 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG5_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP 0x41 // "OTG5 VSTARTUP event occurred interrupt, VSTARTUP event indicates a start of new frame" OTG6_IHC_VSTARTUP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse - -#define DCN_1_0__SRCID__DC_D1_OTG_VREADY 0x42 // "OTG0 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG1_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D2_OTG_VREADY 0x43 // "OTG1 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG2_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D3_OTG_VREADY 0x44 // "OTG2 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG3_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D4_OTG_VREADY 0x45 // "OTG3 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG4_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D5_OTG_VREADY 0x46 // "OTG4 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG5_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse -#define DCN_1_0__SRCID__DC_D6_OTG_VREADY 0x47 // "OTG5 VREADY event occurred interrupt, VREADY event, VREADY event indicates the time DCHUB can start to request data for new frame" OTG6_IHC_VREADY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE20 Level / Pulse - -#define DCN_1_0__SRCID__OTG0_VSYNC_NOM 0x48 // OTG0 vsync nom interrupt OTG1_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS Level / Pulse -#define DCN_1_0__SRCID__OTG1_VSYNC_NOM 0x49 // OTG1 vsync nom interrupt OTG2_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE Level / Pulse -#define DCN_1_0__SRCID__OTG2_VSYNC_NOM 0x4A // OTG2 vsync nom interrupt OTG3_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE2 Level / Pulse -#define DCN_1_0__SRCID__OTG3_VSYNC_NOM 0x4B // OTG3 vsync nom interrupt OTG4_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE3 Level / Pulse -#define DCN_1_0__SRCID__OTG4_VSYNC_NOM 0x4C // OTG4 vsync nom interrupt OTG5_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE4 Level / Pulse -#define DCN_1_0__SRCID__OTG5_VSYNC_NOM 0x4D // OTG5 vsync nom interrupt OTG6_IHC_VSYNC_NOM_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE5 Level / Pulse - -#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_UP_INT 0x4E // Display pipe0 power up interrupt DCPG_IHC_DOMAIN8_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE8_POWER_UP_INT 0 - -#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_UP_INT 0x4E // Display pipe1 power up interrupt DCPG_IHC_DOMAIN9_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE9_POWER_UP_INT 1 - -#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_UP_INT 0x4E // Display pipe2 power up interrupt DCPG_IHC_DOMAIN10_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE10_POWER_UP_INT 2 - -#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_UP_INT 0x4E // Display pipe3 power up interrupt DCPG_IHC_DOMAIN11_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE11_POWER_UP_INT 3 - -#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_UP_INT 0x4E // Display pipe4 power up interrupt DCPG_IHC_DOMAIN12_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE12_POWER_UP_INT 4 - -#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_UP_INT 0x4E // Display pipe5 power up interrupt DCPG_IHC_DOMAIN13_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE13_POWER_UP_INT 5 - -#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_UP_INT 0x4E // Display pipe6 power up interrupt DCPG_IHC_DOMAIN14_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE14_POWER_UP_INT 6 - -#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_UP_INT 0x4E // Display pipe7 power up interrupt DCPG_IHC_DOMAIN15_POWER_UP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE15_POWER_UP_INT 7 - -#define DCN_1_0__SRCID__DCPG_DCFE8_POWER_DOWN_INT 0x4E // Display pipe0 power down interrupt DCPG_IHC_DOMAIN8_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE8_POWER_DOWN_INT 8 - -#define DCN_1_0__SRCID__DCPG_DCFE9_POWER_DOWN_INT 0x4E // Display pipe1 power down interrupt DCPG_IHC_DOMAIN9_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE9_POWER_DOWN_INT 9 - -#define DCN_1_0__SRCID__DCPG_DCFE10_POWER_DOWN_INT 0x4E // Display pipe2 power down interrupt DCPG_IHC_DOMAIN10_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE10_POWER_DOWN_INT 10 - -#define DCN_1_0__SRCID__DCPG_DCFE11_POWER_DOWN_INT 0x4E // Display pipe3 power down interrupt DCPG_IHC_DOMAIN11_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE11_POWER_DOWN_INT 11 - -#define DCN_1_0__SRCID__DCPG_DCFE12_POWER_DOWN_INT 0x4E // Display pipe4 power down interrupt DCPG_IHC_DOMAIN12_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE12_POWER_DOWN_INT 12 - -#define DCN_1_0__SRCID__DCPG_DCFE13_POWER_DOWN_INT 0x4E // Display pipe5 power down interrupt DCPG_IHC_DOMAIN13_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE13_POWER_DOWN_INT 13 - -#define DCN_1_0__SRCID__DCPG_DCFE14_POWER_DOWN_INT 0x4E // Display pipe6 power down interrupt DCPG_IHC_DOMAIN14_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE14_POWER_DOWN_INT 14 - -#define DCN_1_0__SRCID__DCPG_DCFE15_POWER_DOWN_INT 0x4E // Display pipe7 power down interrupt DCPG_IHC_DOMAIN15_POWER_DOWN_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level -#define DCN_1_0__CTXID__DCPG_DCFE15_POWER_DOWN_INT 15 - -#define DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT 0x4F // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP0_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT 0x50 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP1_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT 0x51 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP2_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT 0x52 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP3_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT 0x53 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP4_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT 0x54 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP5_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP6_FLIP_INTERRUPT 0x55 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP6_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP7_FLIP_INTERRUPT 0x56 // Flip interrupt is generated when flip request is accepted by flip logic and surface is flipped from old surface to new surface.HUBP7_IHC_FLIP_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse - -#define DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x57 // "OTG0 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse -#define DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x58 // "OTG1 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse -#define DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x59 // "OTG2 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse -#define DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5A // "OTG3 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse -#define DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5B // "OTG4 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse -#define DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT 0x5C // "OTG5 VUPDATE event without lock interrupt, VUPDATE is update event for double buffered registers" OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE22 Level / Pulse - -#define DCN_1_0__SRCID__HUBP0_FLIP_AWAY_INTERRUPT 0x5D // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP0_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP1_FLIP_AWAY_INTERRUPT 0x5E // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP1_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP2_FLIP_AWAY_INTERRUPT 0x5F // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP2_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP3_FLIP_AWAY_INTERRUPT 0x60 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP3_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP4_FLIP_AWAY_INTERRUPT 0x61 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP4_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP5_FLIP_AWAY_INTERRUPT 0x62 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP5_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP6_FLIP_AWAY_INTERRUPT 0x63 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP6_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse -#define DCN_1_0__SRCID__HUBP7_FLIP_AWAY_INTERRUPT 0x64 // Flip_away interrupt is generated when all data for old surface is returned and old surface is not used again after the surface flip.HUBP7_IHC_FLIP_AWAY_INTERRUPT DISP_INTERRUPT_STATUS_CONTINUE17 Level / Pulse - - -#endif // __IRQSRCS_DCN_1_0_H__ -- cgit From 48321c3dde79f7f2db5000febddf70df3620c445 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Tue, 7 May 2019 14:34:21 -0500 Subject: drm/amd/display: Read soc_bounding_box from gpu_info (v2) [WHY] We don't want to expose sensitive ASIC information before ASIC release. [HOW] Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it at driver load. v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex) Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 63 +++++++++++++++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++ drivers/gpu/drm/amd/display/dc/dc.h | 9 ++++ 5 files changed, 91 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2ec572838d9f..df51b3ed2da9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1432,7 +1432,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) adev->gfx.cu_info.max_scratch_slots_per_cu = le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu); adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size); - if (hdr->version_minor == 1) { + if (hdr->version_minor >= 1) { const struct gpu_info_firmware_v1_1 *gpu_info_fw = (const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); @@ -1441,6 +1441,14 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) adev->gfx.config.num_packer_per_sc = le32_to_cpu(gpu_info_fw->num_packer_per_sc); } +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + if (hdr->version_minor == 2) { + const struct gpu_info_firmware_v1_2 *gpu_info_fw = + (const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data + + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); + adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box; + } +#endif break; } default: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 07f035937650..52b024917075 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -210,6 +210,69 @@ struct gpu_info_firmware_v1_1 { uint32_t num_packer_per_sc; }; +struct gpu_info_voltage_scaling_v1_0 { + int state; + uint32_t dscclk_mhz; + uint32_t dcfclk_mhz; + uint32_t socclk_mhz; + uint32_t dram_speed_mts; + uint32_t fabricclk_mhz; + uint32_t dispclk_mhz; + uint32_t phyclk_mhz; + uint32_t dppclk_mhz; +}; + +struct gpu_info_soc_bounding_box_v1_0 { + uint32_t sr_exit_time_us; + uint32_t sr_enter_plus_exit_time_us; + uint32_t urgent_latency_us; + uint32_t urgent_latency_pixel_data_only_us; + uint32_t urgent_latency_pixel_mixed_with_vm_data_us; + uint32_t urgent_latency_vm_data_only_us; + uint32_t writeback_latency_us; + uint32_t ideal_dram_bw_after_urgent_percent; + uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly + uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; + uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only; + uint32_t max_avg_sdp_bw_use_normal_percent; + uint32_t max_avg_dram_bw_use_normal_percent; + unsigned int max_request_size_bytes; + uint32_t downspread_percent; + uint32_t dram_page_open_time_ns; + uint32_t dram_rw_turnaround_time_ns; + uint32_t dram_return_buffer_per_channel_bytes; + uint32_t dram_channel_width_bytes; + uint32_t fabric_datapath_to_dcn_data_return_bytes; + uint32_t dcn_downspread_percent; + uint32_t dispclk_dppclk_vco_speed_mhz; + uint32_t dfs_vco_period_ps; + unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; + unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; + unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; + unsigned int round_trip_ping_latency_dcfclk_cycles; + unsigned int urgent_out_of_order_return_per_channel_bytes; + unsigned int channel_interleave_bytes; + unsigned int num_banks; + unsigned int num_chans; + unsigned int vmm_page_size_bytes; + uint32_t dram_clock_change_latency_us; + uint32_t writeback_dram_clock_change_latency_us; + unsigned int return_bus_width_bytes; + unsigned int voltage_override; + uint32_t xfc_bus_transport_time_us; + uint32_t xfc_xbuf_latency_tolerance_us; + int use_urgent_burst_bw; + unsigned int num_states; + struct gpu_info_voltage_scaling_v1_0 clock_limits[8]; +}; + +/* gpu info payload + * version_major=1, version_minor=1 */ +struct gpu_info_firmware_v1_2 { + struct gpu_info_firmware_v1_1 v1_1; + struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box; +}; + /* version_major=1, version_minor=0 */ struct gpu_info_firmware_header_v1_0 { struct common_firmware_header header; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7e03847154d3..eeaf84e40dc1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -557,6 +557,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) init_data.flags.fbc_support = true; init_data.flags.power_down_display_on_boot = true; +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + init_data.soc_bounding_box = adev->dm.soc_bounding_box; +#endif /* Display Core create. */ adev->dm.dc = dc_create(&init_data); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b0ce44422e90..59d2584e556e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -206,6 +206,13 @@ struct amdgpu_display_manager { const struct firmware *fw_dmcu; uint32_t dmcu_fw_version; +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + /** + * gpu_info FW provided soc bounding box struct or 0 if not + * available in FW + */ + const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; +#endif }; struct amdgpu_dm_connector { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index c4bd9216dd61..e28b7fee4840 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -373,6 +373,7 @@ struct dc_bounding_box_overrides { struct dc_state; struct resource_pool; struct dce_hwseq; +struct gpu_info_soc_bounding_box_v1_0; struct dc { struct dc_versions versions; struct dc_caps caps; @@ -451,6 +452,14 @@ struct dc_init_data { struct dc_config flags; uint32_t log_mask; + +#ifdef CONFIG_DRM_AMD_DC_DCN2_0 + /** + * gpu_info FW provided soc bounding box struct or 0 if not + * available in FW + */ + const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box; +#endif }; struct dc_callback_init { -- cgit From 476e955dd679673c81c35f383ffff8f7dbd70d97 Mon Sep 17 00:00:00 2001 From: Harry Wentland Date: Fri, 22 Feb 2019 16:52:52 -0500 Subject: drm/amd/display: Hook DCN2 into amdgpu_dm and expose as config (v2) Enable DCN2 support in DM (Display Manager). v2: fix spurious raven change (Alex) Signed-off-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/Kconfig | 9 +++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++++++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 2 +- 3 files changed, 24 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 5c826faae240..df951cbb4c6c 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -16,6 +16,15 @@ config DRM_AMD_DC_DCN1_0 help RV family support for display engine +config DRM_AMD_DC_DCN2_0 + bool "DCN 2.0 family" + default y + depends on DRM_AMD_DC && X86 + depends on DRM_AMD_DC_DCN1_0 + help + Choose this option if you want to have + Navi support for display engine + config DEBUG_KERNEL_DC bool "Enable kgdb break in DC" depends on DRM_AMD_DC diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index eeaf84e40dc1..5971aef4f033 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -666,6 +666,7 @@ static int load_dmcu_fw(struct amdgpu_device *adev) case CHIP_VEGA10: case CHIP_VEGA12: case CHIP_VEGA20: + case CHIP_NAVI10: return 0; case CHIP_RAVEN: if (ASICREV_IS_PICASSO(adev->external_rev_id)) @@ -2210,6 +2211,9 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) break; #if defined(CONFIG_DRM_AMD_DC_DCN1_0) case CHIP_RAVEN: +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case CHIP_NAVI10: +#endif if (dcn10_register_irq_handlers(dm->adev)) { DRM_ERROR("DM: Failed to initialize IRQ\n"); goto fail; @@ -2362,6 +2366,13 @@ static int dm_early_init(void *handle) adev->mode_info.num_hpd = 4; adev->mode_info.num_dig = 4; break; +#endif +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + case CHIP_NAVI10: + adev->mode_info.num_crtc = 6; + adev->mode_info.num_hpd = 6; + adev->mode_info.num_dig = 6; + break; #endif default: DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type); @@ -2655,6 +2666,9 @@ fill_plane_buffer_attributes(struct amdgpu_device *adev, if (adev->asic_type == CHIP_VEGA10 || adev->asic_type == CHIP_VEGA12 || adev->asic_type == CHIP_VEGA20 || +#if defined(CONFIG_DRM_AMD_DC_DCN2_0) + adev->asic_type == CHIP_NAVI10 || +#endif adev->asic_type == CHIP_RAVEN) { /* Fill GFX9 params */ tiling_info->gfx9.num_pipes = diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 7258c992a2bf..75b6a2ac910b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -166,7 +166,7 @@ int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc) */ stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; ret = mod_color_calculate_regamma_params(stream->out_transfer_func, - gamma, true, adev->asic_type <= CHIP_RAVEN, NULL); + gamma, true, adev->asic_type <= CHIP_NAVI10, NULL); if (gamma) dc_gamma_release(&gamma); -- cgit From 96cb7cf13d8530099c256c053648ad576588c387 Mon Sep 17 00:00:00 2001 From: hersen wu Date: Thu, 28 Feb 2019 16:35:24 -0500 Subject: drm/amd/display: disable dcn20 abm feature for bring up [WHY] dcn20 enable usb-c dp ALT mode in dmcu. There is bug when enable abm feature which cause system crash. dal team will debug this bug later. [HOW] disable dcn abm feature for dcn20. Signed-off-by: hersen wu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5971aef4f033..72d14f680932 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -781,7 +781,7 @@ static int dm_late_init(void *handle) unsigned int linear_lut[16]; int i; struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu; - bool ret; + bool ret = false; for (i = 0; i < 16; i++) linear_lut[i] = 0xFFFF * i / 15; @@ -792,10 +792,13 @@ static int dm_late_init(void *handle) params.backlight_lut_array_size = 16; params.backlight_lut_array = linear_lut; - ret = dmcu_load_iram(dmcu, params); + /* todo will enable for navi10 */ + if (adev->asic_type <= CHIP_RAVEN) { + ret = dmcu_load_iram(dmcu, params); - if (!ret) - return -EINVAL; + if (!ret) + return -EINVAL; + } return detect_mst_link_for_all_connectors(adev->ddev); } -- cgit From 78ad75f8d77a1a5dd99d8d8dae66c49113bd0bd7 Mon Sep 17 00:00:00 2001 From: Thomas Lim Date: Tue, 7 May 2019 15:08:22 -0500 Subject: drm/amd/display: Add power down display on boot flag [Why] Due to the generic introduction of seamless boot, the display is no longer blanked upon boot. However, this causes corruption on some systems that does not lock the memory in the non-secure boot case, resulting in brief corruption on boot due to garbage being written into the frame buffer. [How] Add a flag, read during DC init, to determine whether display should be blanked on boot. Default to true. Signed-off-by: Thomas Lim Reviewed-by: Aric Cyr Acked-by: Anthony Koo Acked-by: Leo Li Acked-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 72d14f680932..3eaae98b1320 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -557,6 +557,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) init_data.flags.fbc_support = true; init_data.flags.power_down_display_on_boot = true; + #ifdef CONFIG_DRM_AMD_DC_DCN2_0 init_data.soc_bounding_box = adev->dm.soc_bounding_box; #endif -- cgit From 39a4eb853f9ac85e9b042874ef5fa12c8e20e440 Mon Sep 17 00:00:00 2001 From: Wenjing Liu Date: Thu, 16 May 2019 13:01:51 -0400 Subject: drm/amd/display: update DSC MST DP virtual DPCD peer device enumeration policy [why] Current policy assumes virtual DPCD peer device as an individual MST branch device with 1 input and 1 output. However this is only true for virtual DP-to-DP peer device. In general there are three types of virtual DP peer devices. 1. Sink peer device with virtual DPCD. 2. Virtual DP-to-DP Peer device with virtual DPCD. 3. Virtual DP-to-HDMI Protocol Converter Peer Device with Virtual DPCD. So we should break the assumption and handle all three types. [how] DP-to-DP peer device will have virtual DPCD cap upstream. Sink peer device will have virtual DPCD on the logical port. Dp to HDMI protocol converter peer device will have virtual DPCD on its converter port. For DSC capable Synaptics non VGA port we workaround by enumerating a virutal DPCD peer device on its upstream even if it doesn't have one. Signed-off-by: Wenjing Liu Reviewed-by: Jun Lei Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++ drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 95 ++---------- drivers/gpu/drm/amd/display/dc/dc.h | 19 ++- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 115 +++++++++++++- drivers/gpu/drm/amd/display/dc/dc_dsc.h | 6 + drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 5 +- drivers/gpu/drm/amd/display/include/dpcd_structs.h | 168 --------------------- 7 files changed, 161 insertions(+), 261 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/include/dpcd_structs.h (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3eaae98b1320..07967497fb34 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3421,6 +3421,20 @@ create_stream_for_sink(struct amdgpu_dm_connector *aconnector, fill_stream_properties_from_drm_display_mode(stream, &mode, &aconnector->base, con_state, old_stream); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + /* stream->timing.flags.DSC = 0; */ + /* */ + /* if (aconnector->dc_link && */ + /* aconnector->dc_link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT #<{(|&& */ + /* aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.is_dsc_supported|)}>#) */ + /* if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc, */ + /* &aconnector->dc_link->dpcd_caps.dsc_caps, */ + /* dc_link_bandwidth_kbps(aconnector->dc_link, dc_link_get_link_cap(aconnector->dc_link)), */ + /* &stream->timing, */ + /* &stream->timing.dsc_cfg)) */ + /* stream->timing.flags.DSC = 1; */ +#endif + update_stream_scaling_settings(&mode, dm_state, stream); fill_audio_info( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index 017f88c9f2e4..056be4c34a98 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2382,10 +2382,6 @@ static bool retrieve_link_cap(struct dc_link *link) uint32_t read_dpcd_retry_cnt = 3; int i; struct dp_sink_hw_fw_revision dp_hw_fw_revision; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT - uint8_t dsc_data[16]; /* DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT + 1 == 16 */ - struct dsc_dec_dpcd_caps *dsc_dec_caps; -#endif memset(dpcd_data, '\0', sizeof(dpcd_data)); memset(&down_strm_port_count, @@ -2558,93 +2554,26 @@ static bool retrieve_link_cap(struct dc_link *link) sizeof(dp_hw_fw_revision.ieee_fw_rev)); #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT - dsc_dec_caps = &link->dpcd_caps.dsc_sink_caps; - memset(dsc_dec_caps, '\0', sizeof(*dsc_dec_caps)); - memset(&link->dpcd_caps.dsc_sink_caps, '\0', - sizeof(link->dpcd_caps.dsc_sink_caps)); + memset(&link->dpcd_caps.dsc_caps, '\0', + sizeof(link->dpcd_caps.dsc_caps)); memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); /* Read DSC and FEC sink capabilities if DP revision is 1.4 and up */ if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14) { - status = core_link_read_dpcd( - link, - DP_DSC_SUPPORT, - dsc_data, - sizeof(dsc_data)); - if (status == DC_OK) { - DC_LOG_DSC("DSC DPCD capability read at link %d:", - link->link_index); - DC_LOG_DSC("\t%02x %02x %02x %02x", - dsc_data[0], dsc_data[1], - dsc_data[2], dsc_data[3]); - DC_LOG_DSC("\t%02x %02x %02x %02x", - dsc_data[4], dsc_data[5], - dsc_data[6], dsc_data[7]); - DC_LOG_DSC("\t%02x %02x %02x %02x", - dsc_data[8], dsc_data[9], - dsc_data[10], dsc_data[11]); - DC_LOG_DSC("\t%02x %02x %02x %02x", - dsc_data[12], dsc_data[13], - dsc_data[14], dsc_data[15]); - } else { - dm_error("%s: Read DSC dpcd data failed.\n", __func__); - return false; - } - - if (dc_dsc_parse_dsc_dpcd(dsc_data, NULL, - dsc_dec_caps)) { - DC_LOG_DSC("DSC DPCD capabilities parsed at link %d:", - link->link_index); - DC_LOG_DSC("\tis_dsc_supported:\t%d", - dsc_dec_caps->is_dsc_supported); - DC_LOG_DSC("\tdsc_version:\t%d", dsc_dec_caps->dsc_version); - DC_LOG_DSC("\trc_buffer_size:\t%d", - dsc_dec_caps->rc_buffer_size); - DC_LOG_DSC("\tslice_caps1:\t0x%x20", - dsc_dec_caps->slice_caps1.raw); - DC_LOG_DSC("\tslice_caps2:\t0x%x20", - dsc_dec_caps->slice_caps2.raw); - DC_LOG_DSC("\tlb_bit_depth:\t%d", - dsc_dec_caps->lb_bit_depth); - DC_LOG_DSC("\tis_block_pred_supported:\t%d", - dsc_dec_caps->is_block_pred_supported); - DC_LOG_DSC("\tedp_max_bits_per_pixel:\t%d", - dsc_dec_caps->edp_max_bits_per_pixel); - DC_LOG_DSC("\tcolor_formats:\t%d", - dsc_dec_caps->color_formats.raw); - DC_LOG_DSC("\tcolor_depth:\t%d", - dsc_dec_caps->color_depth.raw); - DC_LOG_DSC("\tthroughput_mode_0_mps:\t%d", - dsc_dec_caps->throughput_mode_0_mps); - DC_LOG_DSC("\tthroughput_mode_1_mps:\t%d", - dsc_dec_caps->throughput_mode_1_mps); - DC_LOG_DSC("\tmax_slice_width:\t%d", - dsc_dec_caps->max_slice_width); - DC_LOG_DSC("\tbpp_increment_div:\t%d", - dsc_dec_caps->bpp_increment_div); - DC_LOG_DSC("\tbranch_overall_throughput_0_mps:\t%d", - dsc_dec_caps->branch_overall_throughput_0_mps); - DC_LOG_DSC("\tbranch_overall_throughput_1_mps:\t%d", - dsc_dec_caps->branch_overall_throughput_1_mps); - DC_LOG_DSC("\tbranch_max_line_width:\t%d", - dsc_dec_caps->branch_max_line_width); - } else { - /* Some sinks return bogus DSC DPCD data - * when they don't support DSC. - */ - dm_error("%s: DSC DPCD data doesn't make sense. " - "DSC will be disabled.\n", __func__); - memset(&link->dpcd_caps.dsc_sink_caps, '\0', - sizeof(link->dpcd_caps.dsc_sink_caps)); - } - status = core_link_read_dpcd( link, DP_FEC_CAPABILITY, &link->dpcd_caps.fec_cap.raw, sizeof(link->dpcd_caps.fec_cap.raw)); - if (status != DC_OK) - dm_error("%s: Read FEC dpcd register failed.\n", - __func__); + status = core_link_read_dpcd( + link, + DP_DSC_SUPPORT, + link->dpcd_caps.dsc_caps.dsc_basic_caps.raw, + sizeof(link->dpcd_caps.dsc_caps.dsc_basic_caps.raw)); + status = core_link_read_dpcd( + link, + DP_DSC_BRANCH_OVERALL_THROUGHPUT_0, + link->dpcd_caps.dsc_caps.dsc_ext_caps.raw, + sizeof(link->dpcd_caps.dsc_caps.dsc_ext_caps.raw)); } #endif diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 80c118f0d6da..252eba2ee116 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -910,8 +910,8 @@ struct dpcd_caps { bool dpcd_display_control_capable; bool ext_receiver_cap_field_present; #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT - union fec_capability fec_cap; - struct dsc_dec_dpcd_caps dsc_sink_caps; + union dpcd_fec_capability fec_cap; + struct dpcd_dsc_capabilities dsc_caps; #endif }; @@ -933,6 +933,14 @@ struct dc_container_id { }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +struct dc_sink_dsc_caps { + // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), + // 'false' if they are sink's DSC caps + bool is_virtual_dpcd_dsc; + struct dsc_dec_dpcd_caps dsc_dec_caps; +}; +#endif /* * The sink structure contains EDID and other display device properties @@ -948,12 +956,7 @@ struct dc_sink { bool converter_disable_audio; #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT - struct dc_sink_dsc_caps { - // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), - // 'false' if they are sink's DSC caps - bool is_virtual_dpcd_dsc; - struct dsc_dec_dpcd_caps dsc_dec_caps; - } sink_dsc_caps; + struct dc_sink_dsc_caps sink_dsc_caps; #endif /* private to DC core */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 6892bf80c9e0..dfcec4d3e9c0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -514,7 +514,7 @@ union test_misc { #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* FEC capability DPCD register field bits-*/ -union fec_capability { +union dpcd_fec_capability { struct { uint8_t FEC_CAPABLE:1; uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; @@ -524,6 +524,119 @@ union fec_capability { } bits; uint8_t raw; }; + +/* DSC capability DPCD register field bits-*/ +struct dpcd_dsc_support { + uint8_t DSC_SUPPORT :1; + uint8_t DSC_PASSTHROUGH_SUPPORT :1; + uint8_t RESERVED :6; +}; + +struct dpcd_dsc_algorithm_revision { + uint8_t DSC_VERSION_MAJOR :4; + uint8_t DSC_VERSION_MINOR :4; +}; + +struct dpcd_dsc_rc_buffer_block_size { + uint8_t RC_BLOCK_BUFFER_SIZE :2; + uint8_t RESERVED :6; +}; + +struct dpcd_dsc_slice_capability1 { + uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; + uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; + uint8_t RESERVED :1; + uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; + uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; + uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; + uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; + uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; +}; + +struct dpcd_dsc_line_buffer_bit_depth { + uint8_t LINE_BUFFER_BIT_DEPTH :4; + uint8_t RESERVED :4; +}; + +struct dpcd_dsc_block_prediction_support { + uint8_t BLOCK_PREDICTION_SUPPORT:1; + uint8_t RESERVED :7; +}; + +struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { + uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; + uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; + uint8_t RESERVED :2; +}; + +struct dpcd_dsc_decoder_color_format_capabilities { + uint8_t RGB_SUPPORT :1; + uint8_t Y_CB_CR_444_SUPPORT :1; + uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; + uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; + uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; + uint8_t RESERVED :3; +}; + +struct dpcd_dsc_decoder_color_depth_capabilities { + uint8_t RESERVED0 :1; + uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; + uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; + uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; + uint8_t RESERVED1 :4; +}; + +struct dpcd_peak_dsc_throughput_dsc_sink { + uint8_t THROUGHPUT_MODE_0:4; + uint8_t THROUGHPUT_MODE_1:4; +}; + +struct dpcd_dsc_slice_capabilities_2 { + uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; + uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; + uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; + uint8_t RESERVED :5; +}; + +struct dpcd_bits_per_pixel_increment{ + uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; + uint8_t RESERVED :5; +}; +union dpcd_dsc_basic_capabilities { + struct { + struct dpcd_dsc_support dsc_support; + struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; + struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; + uint8_t dsc_rc_buffer_size; + struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; + struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; + struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; + struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; + struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; + struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; + struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; + uint8_t dsc_maximum_slice_width; + struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; + uint8_t reserved; + struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; + } fields; + uint8_t raw[16]; +}; + +union dpcd_dsc_ext_capabilities { + struct { + uint8_t BRANCH_OVERALL_THROUGHPUT_0; + uint8_t BRANCH_OVERALL_THROUGHPUT_1; + uint8_t BRANCH_MAX_LINE_WIDTH; + } fields; + uint8_t raw[3]; +}; + +struct dpcd_dsc_capabilities { + union dpcd_dsc_basic_capabilities dsc_basic_caps; + union dpcd_dsc_ext_capabilities dsc_ext_caps; +}; + #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ #endif /* DC_DP_TYPES_H */ diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index 6de3bc9162ea..6e42209f0e20 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -25,6 +25,12 @@ * Author: AMD */ +/* put it here temporarily until linux has the new addresses official defined */ +/* DP Extended DSC Capabilities */ +#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */ +#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1 +#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2 + struct dc_dsc_bw_range { uint32_t min_kbps; /* Bandwidth if min_target_bpp_x16 is used */ uint32_t min_target_bpp_x16; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 252c3d0a2555..96b18bb3b1cc 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -725,9 +725,12 @@ done: bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data, const uint8_t *dpcd_dsc_ext_data, struct dsc_dec_dpcd_caps *dsc_sink_caps) { + if (!dpcd_dsc_basic_data) + return false; + dsc_sink_caps->is_dsc_supported = (dpcd_dsc_basic_data[DP_DSC_SUPPORT - DP_DSC_SUPPORT] & DP_DSC_DECOMPRESSION_IS_SUPPORTED) != 0; if (!dsc_sink_caps->is_dsc_supported) - return true; + return false; dsc_sink_caps->dsc_version = dpcd_dsc_basic_data[DP_DSC_REV - DP_DSC_SUPPORT]; diff --git a/drivers/gpu/drm/amd/display/include/dpcd_structs.h b/drivers/gpu/drm/amd/display/include/dpcd_structs.h deleted file mode 100644 index ca9c5e0c062f..000000000000 --- a/drivers/gpu/drm/amd/display/include/dpcd_structs.h +++ /dev/null @@ -1,168 +0,0 @@ -/* - * dpcd_structs.h - * - * Created on: Oct 31, 2018 - * Author: jlei - */ - -#ifndef DAL_INCLUDE_DPCD_STRUCTS_H_ -#define DAL_INCLUDE_DPCD_STRUCTS_H_ - -struct dpcd_receive_port0_cap01 { - union { - struct { - // Byte 0 - unsigned char reserved0 :1; // Bit0 - unsigned char local_edid_present :1; - unsigned char associated_to_preceding_port :1; - unsigned char hblank_expansion_capable :1; - unsigned char buffer_size_unit :1; // Bit4 - unsigned char buffer_size_per_port :1; - unsigned char reserved1 :2; - - // Byte 1 - unsigned char buffer_size :8; - } fields; - unsigned char raw[2]; - }; -}; - -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT - -struct dpcd_dsc_basic_capabilities { - union { - struct { - // Byte 0 - struct { - unsigned char dsc_support :1; // Bit0 - unsigned char dsc_passthrough_support :1; // Bit1 - unsigned char reserved :6; - } dsc_support; - - // Byte 1 - struct { - unsigned char dsc_version_major :4; - unsigned char dsc_version_minor :4; - } dsc_algorithm_revision; - - // Byte 2 - struct { - unsigned char rc_block_buffer_size :2; - unsigned char reserved :6; - } dsc_rc_buffer_block_size; - - // Byte 3 - unsigned char dsc_rc_buffer_size; - - // Byte 4 - struct { - unsigned char one_slice_per_dp_dsc_sink_device :1; // Bit0 - unsigned char two_slices_per_dp_dsc_sink_device :1; - unsigned char reserved :1; - unsigned char four_slices_per_dp_dsc_sink_device :1; - unsigned char six_slices_per_dp_dsc_sink_device :1; // Bit 4 - unsigned char eight_slices_per_dp_dsc_sink_device :1; - unsigned char ten_slices_per_dp_dsc_sink_device :1; - unsigned char twelve_slices_per_dp_dsc_sink_device :1; - } dsc_slice_capabilities_1; - - // Byte 5 - struct { - unsigned char line_buffer_bit_depth :4; - unsigned char reserved :4; - } dsc_line_buffer_bit_depth; - - // Byte 6 - struct { - unsigned char block_prediction_support :1; - unsigned char reserved :7; - } dsc_block_prediction_support; - - // Byte 7,8 - struct { - unsigned char maximum_bits_per_pixel_supported_by_the_decompressor_low :7; - unsigned char maximum_bits_per_pixel_supported_by_the_decompressor_high :7; - } maximum_bits_per_pixel_supported_by_the_decompressor; - - // Byte 9 - struct { - unsigned char rgb_support :1; // Bit0 - unsigned char y_cb_cr_444_support :1; - unsigned char y_cb_cr_simple_422_support :1; - unsigned char y_cb_cr_native_422_support :1; - unsigned char y_cb_cr_native_420_support :1; // Bit 4 - unsigned char reserved :3; - } dsc_decoder_color_format_capabilities; - - // Byte 10 - struct { - unsigned char reserved0 :1; // Bit0 - unsigned char eight_bits_per_color_support :1; - unsigned char ten_bits_per_color_support :1; - unsigned char twelve_bits_per_color_support :1; - unsigned char reserved1 :4; // Bit 4 - } dsc_decoder_color_depth_capabilities; - - // Byte 11 - struct { - unsigned char throughput_mode_0 :4; - unsigned char throughput_mode_1 :4; - } peak_dsc_throughput_dsc_sink; - - // Byte 12 - unsigned char dsc_maximum_slice_width; - - // Byte 13 - struct { - unsigned char sixteen_slices_per_dsc_sink_device :1; - unsigned char twenty_slices_per_dsc_sink_device :1; - unsigned char twentyfour_slices_per_dsc_sink_device :1; - unsigned char reserved :5; - } dsc_slice_capabilities_2; - - // Byte 14 - unsigned char reserved; - - // Byte 15 - struct { - unsigned char increment_of_bits_per_pixel_supported :3; - unsigned char reserved :5; - } bits_per_pixel_increment; - } fields; - unsigned char raw[16]; - }; -}; - -struct dpcd_dsc_ext_capabilities { - union { - struct { - unsigned char branch_overall_throughput_0; // Byte 0 - unsigned char branch_overall_throughput_1; // Byte 1 - unsigned char branch_max_line_width; // Byte 2 - } fields; - unsigned char raw[3]; - }; -}; - -struct dpcd_dsc_capabilities { - struct dpcd_dsc_basic_capabilities dsc_basic_caps; - struct dpcd_dsc_ext_capabilities dsc_ext_caps; -}; - -struct dpcd_fec_capability { - union { - struct { - // Byte 0 - unsigned char fec_capable :1; // Bit0 - unsigned char uncorrected_block_error_count_capable :1; - unsigned char corrected_block_error_count_capable :1; - unsigned char bit_error_count_capable :1; - unsigned char reserved :4; // Bit4 - } fields; - unsigned char raw[1]; - }; -}; - -#endif - -#endif /* DAL_INCLUDE_DPCD_STRUCTS_H_ */ -- cgit From cf020d49b3c4ef6ab6f26be3dbf2f36b3df9f797 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Thu, 9 May 2019 12:14:58 -0400 Subject: drm/amd/display: Rework CRTC color management [Why] To prepare for the upcoming DRM plane color management properties we need to correct a lot of wrong behavior and assumptions made for CRTC color management. The documentation added by this commit in amdgpu_dm_color explains how the HW color pipeline works and its limitations with the DRM interface. The current implementation does the following wrong: - Implicit sRGB DGM when no CRTC DGM is set - Implicit sRGB RGM when no CRTC RGM is set - No way to specify a non-linear DGM matrix that produces correct output - No way to specify a correct RGM when a linear DGM is used We had workarounds for passing kms_color tests but not all of the behavior we had wrong was covered by these tests (especially when it comes to non-linear DGM). Testing both DGM and RGM at the same time isn't something kms_color tests well either. [How] The specifics for how color management works in AMDGPU and the new behavior can be found by reading the documentation added to amdgpu_dm_color.c from this patch. All of the incorrect cases from the old implementation have been addressed for the atomic interface, but there still a few TODOs for the legacy one. Note: this does cause regressions for kms_color@pipe-a-ctm-* over HDMI. The result looks correct from visual inspection but the CRC no longer matches. For reference, the test was previously doing the following: linear degamma -> CTM -> sRGB regamma -> RGB to YUV (709) -> ... Now the test is doing: linear degamma -> CTM -> linear regamma -> RGB to YUV (709) -> ... Signed-off-by: Nicholas Kazlauskas Reviewed-by: Sun peng Li Acked-by: Bhawanpreet Lakha Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 10 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_color.c | 473 ++++++++++++++------- 3 files changed, 356 insertions(+), 159 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 07967497fb34..58d7bbc5ada7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2878,6 +2878,7 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, struct drm_plane_state *plane_state, struct drm_crtc_state *crtc_state) { + struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); const struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(plane_state->fb); struct dc_scaling_info scaling_info; @@ -2922,13 +2923,11 @@ static int fill_dc_plane_attributes(struct amdgpu_device *adev, * Always set input transfer function, since plane state is refreshed * every time. */ - ret = amdgpu_dm_set_degamma_lut(crtc_state, dc_plane_state); - if (ret) { - dc_transfer_func_release(dc_plane_state->in_transfer_func); - dc_plane_state->in_transfer_func = NULL; - } + ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state); + if (ret) + return ret; - return ret; + return 0; } static void update_stream_scaling_settings(const struct drm_display_mode *mode, @@ -3517,6 +3516,8 @@ dm_crtc_duplicate_state(struct drm_crtc *crtc) state->vrr_supported = cur->vrr_supported; state->freesync_config = cur->freesync_config; state->crc_enabled = cur->crc_enabled; + state->cm_has_degamma = cur->cm_has_degamma; + state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb; /* TODO Duplicate dc_stream after objects are stream object is flattened */ @@ -5674,8 +5675,18 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, bundle->stream_update.dst = acrtc_state->stream->dst; } - if (new_pcrtc_state->color_mgmt_changed) - bundle->stream_update.out_transfer_func = acrtc_state->stream->out_transfer_func; + if (new_pcrtc_state->color_mgmt_changed) { + /* + * TODO: This isn't fully correct since we've actually + * already modified the stream in place. + */ + bundle->stream_update.gamut_remap = + &acrtc_state->stream->gamut_remap_matrix; + bundle->stream_update.output_csc_transform = + &acrtc_state->stream->csc_color_matrix; + bundle->stream_update.out_transfer_func = + acrtc_state->stream->out_transfer_func; + } acrtc_state->stream->abm_level = acrtc_state->abm_level; if (acrtc_state->abm_level != dm_old_crtc_state->abm_level) @@ -6525,10 +6536,9 @@ skip_modeset: */ if (dm_new_crtc_state->base.color_mgmt_changed || drm_atomic_crtc_needs_modeset(new_crtc_state)) { - ret = amdgpu_dm_set_regamma_lut(dm_new_crtc_state); + ret = amdgpu_dm_update_crtc_color_mgmt(dm_new_crtc_state); if (ret) goto fail; - amdgpu_dm_set_ctm(dm_new_crtc_state); } /* Update Freesync settings. */ @@ -6831,6 +6841,8 @@ dm_determine_update_type_for_commit(struct amdgpu_display_manager *dm, new_dm_plane_state->dc_state->in_transfer_func; stream_update.gamut_remap = &new_dm_crtc_state->stream->gamut_remap_matrix; + stream_update.output_csc_transform = + &new_dm_crtc_state->stream->csc_color_matrix; stream_update.out_transfer_func = new_dm_crtc_state->stream->out_transfer_func; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 59d2584e556e..b2ae6560279c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -278,6 +278,9 @@ struct dm_crtc_state { struct drm_crtc_state base; struct dc_stream_state *stream; + bool cm_has_degamma; + bool cm_is_degamma_srgb; + int active_planes; bool interrupts_enabled; @@ -367,10 +370,9 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); #define MAX_COLOR_LEGACY_LUT_ENTRIES 256 void amdgpu_dm_init_color_mod(void); -int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, - struct dc_plane_state *dc_plane_state); -void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc); -int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc); +int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc); +int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct dc_plane_state *dc_plane_state); extern const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c index 75b6a2ac910b..b43bb7f90e4e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_color.c @@ -27,6 +27,47 @@ #include "amdgpu_dm.h" #include "dc.h" #include "modules/color/color_gamma.h" +#include "basics/conversion.h" + +/* + * The DC interface to HW gives us the following color management blocks + * per pipe (surface): + * + * - Input gamma LUT (de-normalized) + * - Input CSC (normalized) + * - Surface degamma LUT (normalized) + * - Surface CSC (normalized) + * - Surface regamma LUT (normalized) + * - Output CSC (normalized) + * + * But these aren't a direct mapping to DRM color properties. The current DRM + * interface exposes CRTC degamma, CRTC CTM and CRTC regamma while our hardware + * is essentially giving: + * + * Plane CTM -> Plane degamma -> Plane CTM -> Plane regamma -> Plane CTM + * + * The input gamma LUT block isn't really applicable here since it operates + * on the actual input data itself rather than the HW fp representation. The + * input and output CSC blocks are technically available to use as part of + * the DC interface but are typically used internally by DC for conversions + * between color spaces. These could be blended together with user + * adjustments in the future but for now these should remain untouched. + * + * The pipe blending also happens after these blocks so we don't actually + * support any CRTC props with correct blending with multiple planes - but we + * can still support CRTC color management properties in DM in most single + * plane cases correctly with clever management of the DC interface in DM. + * + * As per DRM documentation, blocks should be in hardware bypass when their + * respective property is set to NULL. A linear DGM/RGM LUT should also + * considered as putting the respective block into bypass mode. + * + * This means that the following + * configuration is assumed to be the default: + * + * Plane DGM Bypass -> Plane CTM Bypass -> Plane RGM Bypass -> ... + * CRTC DGM Bypass -> CRTC CTM Bypass -> CRTC RGM Bypass + */ #define MAX_DRM_LUT_VALUE 0xFFFF @@ -41,6 +82,13 @@ void amdgpu_dm_init_color_mod(void) setup_x_points_distribution(); } +/* Extracts the DRM lut and lut size from a blob. */ +static const struct drm_color_lut * +__extract_blob_lut(const struct drm_property_blob *blob, uint32_t *size) +{ + *size = blob ? drm_color_lut_size(blob) : 0; + return blob ? (struct drm_color_lut *)blob->data : NULL; +} /* * Return true if the given lut is a linear mapping of values, i.e. it acts @@ -50,7 +98,7 @@ void amdgpu_dm_init_color_mod(void) * f(a) = (0xFF00/MAX_COLOR_LUT_ENTRIES-1)a; for integer a in * [0, MAX_COLOR_LUT_ENTRIES) */ -static bool __is_lut_linear(struct drm_color_lut *lut, uint32_t size) +static bool __is_lut_linear(const struct drm_color_lut *lut, uint32_t size) { int i; uint32_t expected; @@ -75,9 +123,8 @@ static bool __is_lut_linear(struct drm_color_lut *lut, uint32_t size) * Convert the drm_color_lut to dc_gamma. The conversion depends on the size * of the lut - whether or not it's legacy. */ -static void __drm_lut_to_dc_gamma(struct drm_color_lut *lut, - struct dc_gamma *gamma, - bool is_legacy) +static void __drm_lut_to_dc_gamma(const struct drm_color_lut *lut, + struct dc_gamma *gamma, bool is_legacy) { uint32_t r, g, b; int i; @@ -107,103 +154,16 @@ static void __drm_lut_to_dc_gamma(struct drm_color_lut *lut, } } -/** - * amdgpu_dm_set_regamma_lut: Set regamma lut for the given CRTC. - * @crtc: amdgpu_dm crtc state - * - * Update the underlying dc_stream_state's output transfer function (OTF) in - * preparation for hardware commit. If no lut is specified by user, we default - * to SRGB. - * - * RETURNS: - * 0 on success, -ENOMEM if memory cannot be allocated to calculate the OTF. - */ -int amdgpu_dm_set_regamma_lut(struct dm_crtc_state *crtc) -{ - struct drm_property_blob *blob = crtc->base.gamma_lut; - struct dc_stream_state *stream = crtc->stream; - struct amdgpu_device *adev = (struct amdgpu_device *) - crtc->base.state->dev->dev_private; - struct drm_color_lut *lut; - uint32_t lut_size; - struct dc_gamma *gamma = NULL; - enum dc_transfer_func_type old_type = stream->out_transfer_func->type; - - bool ret; - - if (!blob && adev->asic_type <= CHIP_RAVEN) { - /* By default, use the SRGB predefined curve.*/ - stream->out_transfer_func->type = TF_TYPE_PREDEFINED; - stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; - return 0; - } - - if (blob) { - lut = (struct drm_color_lut *)blob->data; - lut_size = blob->length / sizeof(struct drm_color_lut); - - gamma = dc_create_gamma(); - if (!gamma) - return -ENOMEM; - - gamma->num_entries = lut_size; - if (gamma->num_entries == MAX_COLOR_LEGACY_LUT_ENTRIES) - gamma->type = GAMMA_RGB_256; - else if (gamma->num_entries == MAX_COLOR_LUT_ENTRIES) - gamma->type = GAMMA_CS_TFM_1D; - else { - /* Invalid lut size */ - dc_gamma_release(&gamma); - return -EINVAL; - } - - /* Convert drm_lut into dc_gamma */ - __drm_lut_to_dc_gamma(lut, gamma, gamma->type == GAMMA_RGB_256); - } - - /* predefined gamma ROM only exist for RAVEN and pre-RAVEN ASIC, - * set canRomBeUsed accordingly - */ - stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; - ret = mod_color_calculate_regamma_params(stream->out_transfer_func, - gamma, true, adev->asic_type <= CHIP_NAVI10, NULL); - - if (gamma) - dc_gamma_release(&gamma); - - if (!ret) { - stream->out_transfer_func->type = old_type; - DRM_ERROR("Out of memory when calculating regamma params\n"); - return -ENOMEM; - } - - return 0; -} - -/** - * amdgpu_dm_set_ctm: Set the color transform matrix for the given CRTC. - * @crtc: amdgpu_dm crtc state - * - * Update the underlying dc_stream_state's gamut remap matrix in preparation - * for hardware commit. If no matrix is specified by user, gamut remap will be - * disabled. +/* + * Converts a DRM CTM to a DC CSC float matrix. + * The matrix needs to be a 3x4 (12 entry) matrix. */ -void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc) +static void __drm_ctm_to_dc_matrix(const struct drm_color_ctm *ctm, + struct fixed31_32 *matrix) { - - struct drm_property_blob *blob = crtc->base.ctm; - struct dc_stream_state *stream = crtc->stream; - struct drm_color_ctm *ctm; int64_t val; int i; - if (!blob) { - stream->gamut_remap_matrix.enable_remap = false; - return; - } - - stream->gamut_remap_matrix.enable_remap = true; - ctm = (struct drm_color_ctm *)blob->data; /* * DRM gives a 3x3 matrix, but DC wants 3x4. Assuming we're operating * with homogeneous coordinates, augment the matrix with 0's. @@ -215,83 +175,306 @@ void amdgpu_dm_set_ctm(struct dm_crtc_state *crtc) for (i = 0; i < 12; i++) { /* Skip 4th element */ if (i % 4 == 3) { - stream->gamut_remap_matrix.matrix[i] = dc_fixpt_zero; + matrix[i] = dc_fixpt_zero; continue; } /* gamut_remap_matrix[i] = ctm[i - floor(i/4)] */ - val = ctm->matrix[i - (i/4)]; + val = ctm->matrix[i - (i / 4)]; /* If negative, convert to 2's complement. */ if (val & (1ULL << 63)) val = -(val & ~(1ULL << 63)); - stream->gamut_remap_matrix.matrix[i].value = val; + matrix[i].value = val; } } +/* Calculates the legacy transfer function - only for sRGB input space. */ +static int __set_legacy_tf(struct dc_transfer_func *func, + const struct drm_color_lut *lut, uint32_t lut_size, + bool has_rom) +{ + struct dc_gamma *gamma = NULL; + bool res; -/** - * amdgpu_dm_set_degamma_lut: Set degamma lut for the given CRTC. - * @crtc: amdgpu_dm crtc state - * - * Update the underlying dc_stream_state's input transfer function (ITF) in - * preparation for hardware commit. If no lut is specified by user, we default - * to SRGB degamma. - * - * We support degamma bypass, predefined SRGB, and custom degamma - * - * RETURNS: - * 0 on success - * -EINVAL if crtc_state has a degamma_lut of invalid size - * -ENOMEM if gamma allocation fails - */ -int amdgpu_dm_set_degamma_lut(struct drm_crtc_state *crtc_state, - struct dc_plane_state *dc_plane_state) + ASSERT(lut && lut_size == MAX_COLOR_LEGACY_LUT_ENTRIES); + + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->type = GAMMA_RGB_256; + gamma->num_entries = lut_size; + __drm_lut_to_dc_gamma(lut, gamma, true); + + res = mod_color_calculate_regamma_params(func, gamma, true, has_rom, + NULL); + + return res ? 0 : -ENOMEM; +} + +/* Calculates the output transfer function based on expected input space. */ +static int __set_output_tf(struct dc_transfer_func *func, + const struct drm_color_lut *lut, uint32_t lut_size, + bool has_rom) { - struct drm_property_blob *blob = crtc_state->degamma_lut; - struct drm_color_lut *lut; - uint32_t lut_size; - struct dc_gamma *gamma; - bool ret; - - if (!blob) { - /* Default to SRGB */ - dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED; - dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_SRGB; - return 0; - } + struct dc_gamma *gamma = NULL; + bool res; - lut = (struct drm_color_lut *)blob->data; - if (__is_lut_linear(lut, MAX_COLOR_LUT_ENTRIES)) { - dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; - dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; - return 0; - } + ASSERT(lut && lut_size == MAX_COLOR_LUT_ENTRIES); gamma = dc_create_gamma(); if (!gamma) return -ENOMEM; - lut_size = blob->length / sizeof(struct drm_color_lut); gamma->num_entries = lut_size; - if (gamma->num_entries == MAX_COLOR_LUT_ENTRIES) + __drm_lut_to_dc_gamma(lut, gamma, false); + + if (func->tf == TRANSFER_FUNCTION_LINEAR) { + /* + * Color module doesn't like calculating regamma params + * on top of a linear input. But degamma params can be used + * instead to simulate this. + */ gamma->type = GAMMA_CUSTOM; - else { - dc_gamma_release(&gamma); - return -EINVAL; + res = mod_color_calculate_degamma_params(func, gamma, true); + } else { + /* + * Assume sRGB. The actual mapping will depend on whether the + * input was legacy or not. + */ + gamma->type = GAMMA_CS_TFM_1D; + res = mod_color_calculate_regamma_params(func, gamma, false, + has_rom, NULL); } + dc_gamma_release(&gamma); + + return res ? 0 : -ENOMEM; +} + +/* Caculates the input transfer function based on expected input space. */ +static int __set_input_tf(struct dc_transfer_func *func, + const struct drm_color_lut *lut, uint32_t lut_size) +{ + struct dc_gamma *gamma = NULL; + bool res; + + gamma = dc_create_gamma(); + if (!gamma) + return -ENOMEM; + + gamma->type = GAMMA_CUSTOM; + gamma->num_entries = lut_size; + __drm_lut_to_dc_gamma(lut, gamma, false); - dc_plane_state->in_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; - ret = mod_color_calculate_degamma_params(dc_plane_state->in_transfer_func, gamma, true); + res = mod_color_calculate_degamma_params(func, gamma, true); dc_gamma_release(&gamma); - if (!ret) { - dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; - DRM_ERROR("Out of memory when calculating degamma params\n"); - return -ENOMEM; + + return res ? 0 : -ENOMEM; +} + +/** + * amdgpu_dm_update_crtc_color_mgmt: Maps DRM color management to DC stream. + * @crtc: amdgpu_dm crtc state + * + * With no plane level color management properties we're free to use any + * of the HW blocks as long as the CRTC CTM always comes before the + * CRTC RGM and after the CRTC DGM. + * + * The CRTC RGM block will be placed in the RGM LUT block if it is non-linear. + * The CRTC DGM block will be placed in the DGM LUT block if it is non-linear. + * The CRTC CTM will be placed in the gamut remap block if it is non-linear. + * + * The RGM block is typically more fully featured and accurate across + * all ASICs - DCE can't support a custom non-linear CRTC DGM. + * + * For supporting both plane level color management and CRTC level color + * management at once we have to either restrict the usage of CRTC properties + * or blend adjustments together. + * + * Returns 0 on success. + */ +int amdgpu_dm_update_crtc_color_mgmt(struct dm_crtc_state *crtc) +{ + struct dc_stream_state *stream = crtc->stream; + struct amdgpu_device *adev = + (struct amdgpu_device *)crtc->base.state->dev->dev_private; + bool has_rom = adev->asic_type <= CHIP_RAVEN; + struct drm_color_ctm *ctm = NULL; + const struct drm_color_lut *degamma_lut, *regamma_lut; + uint32_t degamma_size, regamma_size; + bool has_regamma, has_degamma; + bool is_legacy; + int r; + + degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, °amma_size); + if (degamma_lut && degamma_size != MAX_COLOR_LUT_ENTRIES) + return -EINVAL; + + regamma_lut = __extract_blob_lut(crtc->base.gamma_lut, ®amma_size); + if (regamma_lut && regamma_size != MAX_COLOR_LUT_ENTRIES && + regamma_size != MAX_COLOR_LEGACY_LUT_ENTRIES) + return -EINVAL; + + has_degamma = + degamma_lut && !__is_lut_linear(degamma_lut, degamma_size); + + has_regamma = + regamma_lut && !__is_lut_linear(regamma_lut, regamma_size); + + is_legacy = regamma_size == MAX_COLOR_LEGACY_LUT_ENTRIES; + + /* Reset all adjustments. */ + crtc->cm_has_degamma = false; + crtc->cm_is_degamma_srgb = false; + + /* Setup regamma and degamma. */ + if (is_legacy) { + /* + * Legacy regamma forces us to use the sRGB RGM as a base. + * This also means we can't use linear DGM since DGM needs + * to use sRGB as a base as well, resulting in incorrect CRTC + * DGM and CRTC CTM. + * + * TODO: Just map this to the standard regamma interface + * instead since this isn't really right. One of the cases + * where this setup currently fails is trying to do an + * inverse color ramp in legacy userspace. + */ + crtc->cm_is_degamma_srgb = true; + stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB; + + r = __set_legacy_tf(stream->out_transfer_func, regamma_lut, + regamma_size, has_rom); + if (r) + return r; + } else if (has_regamma) { + /* CRTC RGM goes into RGM LUT. */ + stream->out_transfer_func->type = TF_TYPE_DISTRIBUTED_POINTS; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + + r = __set_output_tf(stream->out_transfer_func, regamma_lut, + regamma_size, has_rom); + if (r) + return r; + } else { + /* + * No CRTC RGM means we can just put the block into bypass + * since we don't have any plane level adjustments using it. + */ + stream->out_transfer_func->type = TF_TYPE_BYPASS; + stream->out_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + } + + /* + * CRTC DGM goes into DGM LUT. It would be nice to place it + * into the RGM since it's a more featured block but we'd + * have to place the CTM in the OCSC in that case. + */ + crtc->cm_has_degamma = has_degamma; + + /* Setup CRTC CTM. */ + if (crtc->base.ctm) { + ctm = (struct drm_color_ctm *)crtc->base.ctm->data; + + /* + * Gamut remapping must be used for gamma correction + * since it comes before the regamma correction. + * + * OCSC could be used for gamma correction, but we'd need to + * blend the adjustments together with the required output + * conversion matrix - so just use the gamut remap block + * for now. + */ + __drm_ctm_to_dc_matrix(ctm, stream->gamut_remap_matrix.matrix); + + stream->gamut_remap_matrix.enable_remap = true; + stream->csc_color_matrix.enable_adjustment = false; + } else { + /* Bypass CTM. */ + stream->gamut_remap_matrix.enable_remap = false; + stream->csc_color_matrix.enable_adjustment = false; } return 0; } +/** + * amdgpu_dm_update_plane_color_mgmt: Maps DRM color management to DC plane. + * @crtc: amdgpu_dm crtc state + * @ dc_plane_state: target DC surface + * + * Update the underlying dc_stream_state's input transfer function (ITF) in + * preparation for hardware commit. The transfer function used depends on + * the prepartion done on the stream for color management. + * + * Returns 0 on success. + */ +int amdgpu_dm_update_plane_color_mgmt(struct dm_crtc_state *crtc, + struct dc_plane_state *dc_plane_state) +{ + const struct drm_color_lut *degamma_lut; + uint32_t degamma_size; + int r; + + if (crtc->cm_has_degamma) { + degamma_lut = __extract_blob_lut(crtc->base.degamma_lut, + °amma_size); + ASSERT(degamma_size == MAX_COLOR_LUT_ENTRIES); + + dc_plane_state->in_transfer_func->type = + TF_TYPE_DISTRIBUTED_POINTS; + + /* + * This case isn't fully correct, but also fairly + * uncommon. This is userspace trying to use a + * legacy gamma LUT + atomic degamma LUT + * at the same time. + * + * Legacy gamma requires the input to be in linear + * space, so that means we need to apply an sRGB + * degamma. But color module also doesn't support + * a user ramp in this case so the degamma will + * be lost. + * + * Even if we did support it, it's still not right: + * + * Input -> CRTC DGM -> sRGB DGM -> CRTC CTM -> + * sRGB RGM -> CRTC RGM -> Output + * + * The CSC will be done in the wrong space since + * we're applying an sRGB DGM on top of the CRTC + * DGM. + * + * TODO: Don't use the legacy gamma interface and just + * map these to the atomic one instead. + */ + if (crtc->cm_is_degamma_srgb) + dc_plane_state->in_transfer_func->tf = + TRANSFER_FUNCTION_SRGB; + else + dc_plane_state->in_transfer_func->tf = + TRANSFER_FUNCTION_LINEAR; + + r = __set_input_tf(dc_plane_state->in_transfer_func, + degamma_lut, degamma_size); + if (r) + return r; + } else if (crtc->cm_is_degamma_srgb) { + /* + * For legacy gamma support we need the regamma input + * in linear space. Assume that the input is sRGB. + */ + dc_plane_state->in_transfer_func->type = TF_TYPE_PREDEFINED; + dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_SRGB; + } else { + /* ...Otherwise we can just bypass the DGM block. */ + dc_plane_state->in_transfer_func->type = TF_TYPE_BYPASS; + dc_plane_state->in_transfer_func->tf = TRANSFER_FUNCTION_LINEAR; + } + + return 0; +} -- cgit From ed9656fbc8b5b13a2350d9a7eb70f1b8d55e5803 Mon Sep 17 00:00:00 2001 From: Ernst Sjöstrand Date: Mon, 24 Jun 2019 17:15:42 +0200 Subject: drm/amd/amdgpu: Check stream in amdgpu_dm_commit_planes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reported by smatch: amdgpu_dm.c:5637 amdgpu_dm_commit_planes() error: we previously assumed 'acrtc_state->stream' could be null This seems to be checked for null pretty consistently elsewhere. Signed-off-by: Ernst Sjöstrand Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4c70a0803b85..df08ea172595 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5671,7 +5671,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, } /* Update the planes if changed or disable if we don't have any. */ - if (planes_count || acrtc_state->active_planes == 0) { + if ((planes_count || acrtc_state->active_planes == 0) && + acrtc_state->stream) { if (new_pcrtc_state->mode_changed) { bundle->stream_update.src = acrtc_state->stream->src; bundle->stream_update.dst = acrtc_state->stream->dst; -- cgit From 843747253b427a579b360850e133f700b8bb5e0c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 2 Jul 2019 11:39:50 -0500 Subject: drm/amdgpu/display: fix interrupt client id for navi All asics newer than vega10 use client ids, so simplify the check. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index df08ea172595..0242d693f4f6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1535,10 +1535,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev) int i; unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY; - if (adev->asic_type == CHIP_VEGA10 || - adev->asic_type == CHIP_VEGA12 || - adev->asic_type == CHIP_VEGA20 || - adev->asic_type == CHIP_RAVEN) + if (adev->asic_type >= CHIP_VEGA10) client_id = SOC15_IH_CLIENTID_DCE; int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT; -- cgit From 6ce8f316673f61416738e6df7329ca508a607762 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Thu, 11 Jul 2019 14:31:46 -0500 Subject: drm/amd/display: Add drm_audio_component support to amdgpu_dm [Why] The drm_audio_component can be used to give pin ELD notifications directly to the sound driver. This fixes audio endpoints disappearing due to missing unsolicited notifications. [How] Send the notification via the audio component whenever we enable or disable audio state on a stream. This matches what i915 does with their drm_audio_component and what Takashi Iwai's proposed hack for radeon/amdpgu did. This is a bit delayed in when the notification actually occurs, however. We wait until after all the programming is complete rather than sending the notification mid sequence. Particular care is needed for the get ELD callback since it can happen outside the locking and fencing DRM does for atomic commits. Cc: Leo Li Cc: Harry Wentland Signed-off-by: Nicholas Kazlauskas Reviewed-by: Alex Deucher Reviewed-by: Takashi Iwai Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/Kconfig | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 222 ++++++++++++++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 25 +++ 3 files changed, 248 insertions(+) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/Kconfig b/drivers/gpu/drm/amd/display/Kconfig index 7073cfcf04e8..f954bf61af28 100644 --- a/drivers/gpu/drm/amd/display/Kconfig +++ b/drivers/gpu/drm/amd/display/Kconfig @@ -5,6 +5,7 @@ menu "Display Engine Configuration" config DRM_AMD_DC bool "AMD DC - Enable new display engine" default y + select SND_HDA_COMPONENT if SND_HDA_CORE select DRM_AMD_DC_DCN1_0 if X86 && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) help Choose this option if you want to use the new display engine diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0242d693f4f6..4a29f72334d0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -56,6 +56,7 @@ #include #include #include +#include #include #include @@ -65,6 +66,7 @@ #include #include #include +#include #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h" @@ -508,6 +510,139 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector) } +static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, + int pipe, bool *enabled, + unsigned char *buf, int max_bytes) +{ + struct drm_device *dev = dev_get_drvdata(kdev); + struct amdgpu_device *adev = dev->dev_private; + struct drm_connector *connector; + struct drm_connector_list_iter conn_iter; + struct amdgpu_dm_connector *aconnector; + int ret = 0; + + *enabled = false; + + mutex_lock(&adev->dm.audio_lock); + + drm_connector_list_iter_begin(dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + aconnector = to_amdgpu_dm_connector(connector); + if (aconnector->audio_inst != port) + continue; + + *enabled = true; + ret = drm_eld_size(connector->eld); + memcpy(buf, connector->eld, min(max_bytes, ret)); + + break; + } + drm_connector_list_iter_end(&conn_iter); + + mutex_unlock(&adev->dm.audio_lock); + + DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled); + + return ret; +} + +static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = { + .get_eld = amdgpu_dm_audio_component_get_eld, +}; + +static int amdgpu_dm_audio_component_bind(struct device *kdev, + struct device *hda_kdev, void *data) +{ + struct drm_device *dev = dev_get_drvdata(kdev); + struct amdgpu_device *adev = dev->dev_private; + struct drm_audio_component *acomp = data; + + acomp->ops = &amdgpu_dm_audio_component_ops; + acomp->dev = kdev; + adev->dm.audio_component = acomp; + + return 0; +} + +static void amdgpu_dm_audio_component_unbind(struct device *kdev, + struct device *hda_kdev, void *data) +{ + struct drm_device *dev = dev_get_drvdata(kdev); + struct amdgpu_device *adev = dev->dev_private; + struct drm_audio_component *acomp = data; + + acomp->ops = NULL; + acomp->dev = NULL; + adev->dm.audio_component = NULL; +} + +static const struct component_ops amdgpu_dm_audio_component_bind_ops = { + .bind = amdgpu_dm_audio_component_bind, + .unbind = amdgpu_dm_audio_component_unbind, +}; + +static int amdgpu_dm_audio_init(struct amdgpu_device *adev) +{ + int i, ret; + + if (!amdgpu_audio) + return 0; + + adev->mode_info.audio.enabled = true; + + adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count; + + for (i = 0; i < adev->mode_info.audio.num_pins; i++) { + adev->mode_info.audio.pin[i].channels = -1; + adev->mode_info.audio.pin[i].rate = -1; + adev->mode_info.audio.pin[i].bits_per_sample = -1; + adev->mode_info.audio.pin[i].status_bits = 0; + adev->mode_info.audio.pin[i].category_code = 0; + adev->mode_info.audio.pin[i].connected = false; + adev->mode_info.audio.pin[i].id = + adev->dm.dc->res_pool->audios[i]->inst; + adev->mode_info.audio.pin[i].offset = 0; + } + + ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops); + if (ret < 0) + return ret; + + adev->dm.audio_registered = true; + + return 0; +} + +static void amdgpu_dm_audio_fini(struct amdgpu_device *adev) +{ + if (!amdgpu_audio) + return; + + if (!adev->mode_info.audio.enabled) + return; + + if (adev->dm.audio_registered) { + component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops); + adev->dm.audio_registered = false; + } + + /* TODO: Disable audio? */ + + adev->mode_info.audio.enabled = false; +} + +void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) +{ + struct drm_audio_component *acomp = adev->dm.audio_component; + + if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) { + DRM_DEBUG_KMS("Notify ELD: %d\n", pin); + + acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr, + pin, -1); + } +} + static int amdgpu_dm_init(struct amdgpu_device *adev) { struct dc_init_data init_data; @@ -518,6 +653,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) memset(&init_data, 0, sizeof(init_data)); mutex_init(&adev->dm.dc_lock); + mutex_init(&adev->dm.audio_lock); if(amdgpu_dm_irq_init(adev)) { DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); @@ -621,6 +757,8 @@ error: static void amdgpu_dm_fini(struct amdgpu_device *adev) { + amdgpu_dm_audio_fini(adev); + amdgpu_dm_destroy_drm_device(&adev->dm); /* DC Destroy TODO: Replace destroy DAL */ @@ -641,6 +779,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } + mutex_destroy(&adev->dm.audio_lock); mutex_destroy(&adev->dm.dc_lock); return; @@ -1888,6 +2027,10 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) if (r) return r; + r = amdgpu_dm_audio_init(adev); + if (r) + return r; + return 0; } @@ -4834,6 +4977,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, aconnector->base.stereo_allowed = false; aconnector->base.dpms = DRM_MODE_DPMS_OFF; aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ + aconnector->audio_inst = -1; mutex_init(&aconnector->hpd_lock); /* @@ -5728,6 +5872,81 @@ cleanup: kfree(bundle); } +static void amdgpu_dm_commit_audio(struct drm_device *dev, + struct drm_atomic_state *state) +{ + struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_dm_connector *aconnector; + struct drm_connector *connector; + struct drm_connector_state *old_con_state, *new_con_state; + struct drm_crtc_state *new_crtc_state; + struct dm_crtc_state *new_dm_crtc_state; + const struct dc_stream_status *status; + int i, inst; + + /* Notify device removals. */ + for_each_oldnew_connector_in_state(state, connector, old_con_state, new_con_state, i) { + if (old_con_state->crtc != new_con_state->crtc) { + /* CRTC changes require notification. */ + goto notify; + } + + if (!new_con_state->crtc) + continue; + + new_crtc_state = drm_atomic_get_new_crtc_state( + state, new_con_state->crtc); + + if (!new_crtc_state) + continue; + + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + continue; + + notify: + aconnector = to_amdgpu_dm_connector(connector); + + mutex_lock(&adev->dm.audio_lock); + inst = aconnector->audio_inst; + aconnector->audio_inst = -1; + mutex_unlock(&adev->dm.audio_lock); + + amdgpu_dm_audio_eld_notify(adev, inst); + } + + /* Notify audio device additions. */ + for_each_new_connector_in_state(state, connector, new_con_state, i) { + if (!new_con_state->crtc) + continue; + + new_crtc_state = drm_atomic_get_new_crtc_state( + state, new_con_state->crtc); + + if (!new_crtc_state) + continue; + + if (!drm_atomic_crtc_needs_modeset(new_crtc_state)) + continue; + + new_dm_crtc_state = to_dm_crtc_state(new_crtc_state); + if (!new_dm_crtc_state->stream) + continue; + + status = dc_stream_get_status(new_dm_crtc_state->stream); + if (!status) + continue; + + aconnector = to_amdgpu_dm_connector(connector); + + mutex_lock(&adev->dm.audio_lock); + inst = status->audio_inst; + aconnector->audio_inst = inst; + mutex_unlock(&adev->dm.audio_lock); + + amdgpu_dm_audio_eld_notify(adev, inst); + } +} + /* * Enable interrupts on CRTCs that are newly active, undergone * a modeset, or have active planes again. @@ -6106,6 +6325,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) /* Enable interrupts for CRTCs going from 0 to n active planes. */ amdgpu_dm_enable_crtc_interrupts(dev, state, false); + /* Update audio instances for each connector. */ + amdgpu_dm_commit_audio(dev, state); + /* * send vblank event on all events not handled in flip and * mark consumed event for drm_atomic_helper_commit_hw_done diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index baca5dc22b92..b89cbbfcc0e9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -143,6 +143,28 @@ struct amdgpu_display_manager { */ struct mutex dc_lock; + /** + * @audio_lock: + * + * Guards access to audio instance changes. + */ + struct mutex audio_lock; + + /** + * @audio_component: + * + * Used to notify ELD changes to sound driver. + */ + struct drm_audio_component *audio_component; + + /** + * @audio_registered: + * + * True if the audio component has been registered + * successfully, false otherwise. + */ + bool audio_registered; + /** * @irq_handler_list_low_tab: * @@ -254,6 +276,9 @@ struct amdgpu_dm_connector { int max_vfreq ; int pixel_clock_mhz; + /* Audio instance - protected by audio_lock. */ + int audio_inst; + struct mutex hpd_lock; bool fake_enable; -- cgit From ec6e491353b9024d4b1a65c48b21e3bc0faeae4e Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Wed, 21 Aug 2019 11:27:13 -0400 Subject: drm/amd/display: Calculate bpc based on max_requested_bpc [Why] The only place where state->max_bpc is updated on the connector is at the start of atomic check during drm_atomic_connector_check. It isn't updated when adding the connectors to the atomic state after the fact. It also doesn't necessarily reflect the right value when called in amdgpu during mode validation outside of atomic check. This can cause the wrong bpc to be used even if the max_requested_bpc is the correct value. [How] Don't rely on state->max_bpc reflecting the real bpc value and just do the min(...) based on display info bpc and max_requested_bpc. Fixes: 01933ba42d3d ("drm/amd/display: Use current connector state if NULL when checking bpc") Signed-off-by: Nicholas Kazlauskas Reviewed-by: Leo Li Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c') diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4a29f72334d0..45be7a2132bb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3131,13 +3131,25 @@ static enum dc_color_depth convert_color_depth_from_display_info(const struct drm_connector *connector, const struct drm_connector_state *state) { - uint32_t bpc = connector->display_info.bpc; + uint8_t bpc = (uint8_t)connector->display_info.bpc; + + /* Assume 8 bpc by default if no bpc is specified. */ + bpc = bpc ? bpc : 8; if (!state) state = connector->state; if (state) { - bpc = state->max_bpc; + /* + * Cap display bpc based on the user requested value. + * + * The value for state->max_bpc may not correctly updated + * depending on when the connector gets added to the state + * or if this was called outside of atomic check, so it + * can't be used directly. + */ + bpc = min(bpc, state->max_requested_bpc); + /* Round down to the nearest even number. */ bpc = bpc - (bpc & 1); } -- cgit