From fdf2f6c56e5e289c7d7e726b676aba25643b39a0 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Mon, 10 Jun 2019 00:07:56 +0200 Subject: drm/amd: drop use of drmP.h in amdgpu/amdgpu* MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop use of drmP.h in all files named amdgpu* in drm/amd/amdgpu/ Fix fallout. Signed-off-by: Sam Ravnborg Reviewed-by: Alex Deucher Cc: "Christian König" Cc: "David (ChunMing) Zhou" Cc: David Airlie Cc: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20190609220757.10862-10-sam@ravnborg.org --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 1 - 1 file changed, 1 deletion(-) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 523b8ab6b04e..eedecaf4c804 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -22,7 +22,6 @@ * Authors: Alex Deucher */ -#include #include "amdgpu.h" #include "amdgpu_atombios.h" #include "amdgpu_i2c.h" -- cgit From bca325280d1f17a84a8af70cb840ab5fcdb8d062 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Wed, 27 Mar 2019 11:46:31 +0800 Subject: drm/amd: add gfxoff support on navi10 add the gfxoff interface to navi10,it's disabled by default. Signed-off-by: Kenneth Feng Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h | 7 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 +++- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 5 ++++- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 16 ++++++++++++++++ 5 files changed, 46 insertions(+), 6 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 523b8ab6b04e..b5397135c417 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -920,3 +920,23 @@ int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) else return (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low)); } + +int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) +{ + int ret = 0; + bool swsmu = is_support_sw_smu(adev); + + switch (block_type) { + case AMD_IP_BLOCK_TYPE_GFX: + if (swsmu) + ret = smu_gfx_off_control(&adev->smu, gate); + else + ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( + (adev)->powerplay.pp_handle, block_type, gate)); + break; + default: + break; + } + + return ret; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index 521dbd0d9af8..1c5c0fd76dbf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h @@ -355,10 +355,6 @@ enum amdgpu_pcie_gen { ((adev)->powerplay.pp_funcs->set_clockgating_by_smu(\ (adev)->powerplay.pp_handle, msg_id)) -#define amdgpu_dpm_set_powergating_by_smu(adev, block_type, gate) \ - ((adev)->powerplay.pp_funcs->set_powergating_by_smu(\ - (adev)->powerplay.pp_handle, block_type, gate)) - #define amdgpu_dpm_get_power_profile_mode(adev, buf) \ ((adev)->powerplay.pp_funcs->get_power_profile_mode(\ (adev)->powerplay.pp_handle, buf)) @@ -520,6 +516,9 @@ enum amdgpu_pcie_gen amdgpu_get_pcie_gen_support(struct amdgpu_device *adev, struct amd_vce_state* amdgpu_get_vce_clock_state(void *handle, u32 idx); +int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, + uint32_t block_type, bool gate); + extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low); extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 61fca1e9a86b..bc2630f9a72c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -547,7 +547,9 @@ void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable) if (!(adev->pm.pp_feature & PP_GFXOFF_MASK)) return; - if (!adev->powerplay.pp_funcs || !adev->powerplay.pp_funcs->set_powergating_by_smu) + if (!is_support_sw_smu(adev) && + (!adev->powerplay.pp_funcs || + !adev->powerplay.pp_funcs->set_powergating_by_smu)) return; diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index 386991b558fd..0577a1f8920a 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -553,7 +553,7 @@ struct smu_funcs int (*set_fan_speed_percent)(struct smu_context *smu, uint32_t speed); int (*set_fan_speed_rpm)(struct smu_context *smu, uint32_t speed); int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate); - + int (*gfx_off_control)(struct smu_context *smu, bool enable); }; #define smu_init_microcode(smu) \ @@ -592,6 +592,9 @@ struct smu_funcs ((smu)->funcs->set_tool_table_location ? (smu)->funcs->set_tool_table_location((smu)) : 0) #define smu_notify_memory_pool_location(smu) \ ((smu)->funcs->notify_memory_pool_location ? (smu)->funcs->notify_memory_pool_location((smu)) : 0) +#define smu_gfx_off_control(smu, enable) \ + ((smu)->funcs->gfx_off_control ? (smu)->funcs->gfx_off_control((smu), (enable)) : 0) + #define smu_write_watermarks_table(smu) \ ((smu)->funcs->write_watermarks_table ? (smu)->funcs->write_watermarks_table((smu)) : 0) #define smu_set_last_dcef_min_deep_sleep_clk(smu) \ diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 7e09d1ff2050..d8379e421848 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -1547,6 +1547,21 @@ smu_v11_0_set_watermarks_for_clock_ranges(struct smu_context *smu, struct return ret; } +static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) +{ + int ret = 0; + + mutex_lock(&smu->mutex); + if (enable) + ret = smu_send_smc_msg(smu, SMU_MSG_AllowGfxOff); + else + ret = smu_send_smc_msg(smu, SMU_MSG_DisallowGfxOff); + mutex_unlock(&smu->mutex); + + return ret; +} + + static int smu_v11_0_get_clock_ranges(struct smu_context *smu, uint32_t *clock, PPCLK_e clock_select, @@ -1919,6 +1934,7 @@ static const struct smu_funcs smu_v11_0_funcs = { .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent, .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm, .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate, + .gfx_off_control = smu_v11_0_gfx_off_control, }; void smu_v11_0_set_smu_funcs(struct smu_context *smu) -- cgit From 576851345b677b28617217f5d97920f62eab471e Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Tue, 4 Jun 2019 17:38:42 +0800 Subject: drm/amd/powerplay: remove smu callback funciton get_mclk(get_sclk) remove smu callback: get_mclk, get_sclk. because the function smu_get_dpm_freq_range has the same function. Signed-off-by: Kevin Wang Reviewed-by: Evan Quan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 30 +++++++-- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 34 +++++++++-- drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h | 6 -- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 85 -------------------------- 4 files changed, 52 insertions(+), 103 deletions(-) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index b5397135c417..6c2ec8123178 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -907,18 +907,36 @@ amdgpu_get_vce_clock_state(void *handle, u32 idx) int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low) { - if (is_support_sw_smu(adev)) - return smu_get_sclk(&adev->smu, low); - else + uint32_t clk_freq; + int ret = 0; + if (is_support_sw_smu(adev)) { + ret = smu_get_dpm_freq_range(&adev->smu, SMU_GFXCLK, + low ? &clk_freq : NULL, + !low ? &clk_freq : NULL); + if (ret) + return 0; + return clk_freq * 100; + + } else { return (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (low)); + } } int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low) { - if (is_support_sw_smu(adev)) - return smu_get_mclk(&adev->smu, low); - else + uint32_t clk_freq; + int ret = 0; + if (is_support_sw_smu(adev)) { + ret = smu_get_dpm_freq_range(&adev->smu, SMU_UCLK, + low ? &clk_freq : NULL, + !low ? &clk_freq : NULL); + if (ret) + return 0; + return clk_freq * 100; + + } else { return (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (low)); + } } int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block_type, bool gate) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 3cb71668e523..4d7aeee91bc8 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -135,30 +135,52 @@ int smu_get_dpm_freq_range(struct smu_context *smu, enum smu_clk_type clk_type, if (!min && !max) return -EINVAL; + switch (clk_type) { + case SMU_UCLK: + if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { + pr_warn("uclk dpm is not enabled\n"); + return 0; + } + break; + case SMU_GFXCLK: + if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { + pr_warn("gfxclk dpm is not enabled\n"); + return 0; + } + break; + default: + break; + } + + mutex_lock(&smu->mutex); clk_id = smu_clk_get_index(smu, clk_type); - if (clk_id < 0) - return clk_id; + if (clk_id < 0) { + ret = -EINVAL; + goto failed; + } param = (clk_id & 0xffff) << 16; if (max) { ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param); if (ret) - return ret; + goto failed; ret = smu_read_smc_arg(smu, max); if (ret) - return ret; + goto failed; } if (min) { ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param); if (ret) - return ret; + goto failed; ret = smu_read_smc_arg(smu, min); if (ret) - return ret; + goto failed; } +failed: + mutex_unlock(&smu->mutex); return ret; } diff --git a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h index 5e49b38ddd0d..58861c0340b9 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h @@ -679,8 +679,6 @@ struct smu_funcs int (*update_od8_settings)(struct smu_context *smu, uint32_t index, uint32_t value); - uint32_t (*get_sclk)(struct smu_context *smu, bool low); - uint32_t (*get_mclk)(struct smu_context *smu, bool low); int (*get_current_rpm)(struct smu_context *smu, uint32_t *speed); uint32_t (*get_fan_control_mode)(struct smu_context *smu); int (*set_fan_control_mode)(struct smu_context *smu, uint32_t mode); @@ -881,10 +879,6 @@ struct smu_funcs ((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0) #define smu_dpm_set_vce_enable(smu, enable) \ ((smu)->ppt_funcs->dpm_set_vce_enable ? (smu)->ppt_funcs->dpm_set_vce_enable((smu), (enable)) : 0) -#define smu_get_sclk(smu, low) \ - ((smu)->funcs->get_sclk ? (smu)->funcs->get_sclk((smu), (low)) : 0) -#define smu_get_mclk(smu, low) \ - ((smu)->funcs->get_mclk ? (smu)->funcs->get_mclk((smu), (low)) : 0) #define smu_set_xgmi_pstate(smu, pstate) \ ((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0) #define smu_set_ppfeature_status(smu, ppfeatures) \ diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c index 3200d8c729dd..e77cfb96fc56 100644 --- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c +++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c @@ -1351,89 +1351,6 @@ static int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable) return ret; } - -static int smu_v11_0_get_clock_ranges(struct smu_context *smu, - uint32_t *clock, - enum smu_clk_type clock_select, - bool max) -{ - int ret; - *clock = 0; - if (max) { - ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, - smu_clk_get_index(smu, clock_select) << 16); - if (ret) { - pr_err("[GetClockRanges] Failed to get max clock from SMC!\n"); - return ret; - } - smu_read_smc_arg(smu, clock); - } else { - ret = smu_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, - smu_clk_get_index(smu, clock_select) << 16); - if (ret) { - pr_err("[GetClockRanges] Failed to get min clock from SMC!\n"); - return ret; - } - smu_read_smc_arg(smu, clock); - } - - return 0; -} - -static uint32_t smu_v11_0_dpm_get_sclk(struct smu_context *smu, bool low) -{ - uint32_t gfx_clk; - int ret; - - if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) { - pr_err("[GetSclks]: gfxclk dpm not enabled!\n"); - return -EPERM; - } - - if (low) { - ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, false); - if (ret) { - pr_err("[GetSclks]: fail to get min SMU_GFXCLK\n"); - return ret; - } - } else { - ret = smu_v11_0_get_clock_ranges(smu, &gfx_clk, SMU_GFXCLK, true); - if (ret) { - pr_err("[GetSclks]: fail to get max SMU_GFXCLK\n"); - return ret; - } - } - - return (gfx_clk * 100); -} - -static uint32_t smu_v11_0_dpm_get_mclk(struct smu_context *smu, bool low) -{ - uint32_t mem_clk; - int ret; - - if (!smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) { - pr_err("[GetMclks]: memclk dpm not enabled!\n"); - return -EPERM; - } - - if (low) { - ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_UCLK, false); - if (ret) { - pr_err("[GetMclks]: fail to get min SMU_UCLK\n"); - return ret; - } - } else { - ret = smu_v11_0_get_clock_ranges(smu, &mem_clk, SMU_GFXCLK, true); - if (ret) { - pr_err("[GetMclks]: fail to get max SMU_UCLK\n"); - return ret; - } - } - - return (mem_clk * 100); -} - static int smu_v11_0_set_od8_default_settings(struct smu_context *smu, bool initialize) { @@ -1778,8 +1695,6 @@ static const struct smu_funcs smu_v11_0_funcs = { .set_deep_sleep_dcefclk = smu_v11_0_set_deep_sleep_dcefclk, .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request, .set_watermarks_for_clock_ranges = smu_v11_0_set_watermarks_for_clock_ranges, - .get_sclk = smu_v11_0_dpm_get_sclk, - .get_mclk = smu_v11_0_dpm_get_mclk, .set_od8_default_settings = smu_v11_0_set_od8_default_settings, .update_od8_settings = smu_v11_0_update_od8_settings, .get_current_rpm = smu_v11_0_get_current_rpm, -- cgit From 73c86d628d6aa3d7162094ef1f0503bda17b506e Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 24 Jun 2019 19:26:00 +0800 Subject: drm/amdgpu: fix modprobe failure for uvd_4/5/6 For uvd_4/5/6, amdgpu driver will only power on them when there are jobs assigned to decode/enc rings.uvd_4/5/6 dpm was broken since amdgpu_dpm_set_powergating_by_smu only covers gfx block. The change would add more IP block support in amdgpu_dpm_set_powergating_by_smu For GFX/UVD/VCN/VCE, if the new SMU driver is supported, invoke new power gate helper function smu_dpm_set_power_gate, otherwise, fallback to legacy powerplay helper function pp_set_powergating_by_smu. For other IP blocks always invoke legacy powerplay helper function. Signed-off-by: Hawking Zhang Reviewed-by: Tianci Yin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c | 11 ++++++++++- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 3 +++ 2 files changed, 13 insertions(+), 1 deletion(-) (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c') diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c index 6c2ec8123178..f082b2547b83 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c @@ -946,12 +946,21 @@ int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev, uint32_t block switch (block_type) { case AMD_IP_BLOCK_TYPE_GFX: + case AMD_IP_BLOCK_TYPE_UVD: + case AMD_IP_BLOCK_TYPE_VCN: + case AMD_IP_BLOCK_TYPE_VCE: if (swsmu) - ret = smu_gfx_off_control(&adev->smu, gate); + ret = smu_dpm_set_power_gate(&adev->smu, block_type, gate); else ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( (adev)->powerplay.pp_handle, block_type, gate)); break; + case AMD_IP_BLOCK_TYPE_GMC: + case AMD_IP_BLOCK_TYPE_ACP: + case AMD_IP_BLOCK_TYPE_SDMA: + ret = ((adev)->powerplay.pp_funcs->set_powergating_by_smu( + (adev)->powerplay.pp_handle, block_type, gate)); + break; default: break; } diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c index 8bf42f80f253..5aa0594fb53f 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -233,6 +233,9 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type, case AMD_IP_BLOCK_TYPE_VCE: ret = smu_dpm_set_vce_enable(smu, gate); break; + case AMD_IP_BLOCK_TYPE_GFX: + ret = smu_gfx_off_control(smu, gate); + break; default: break; } -- cgit