From 46a57afdd70c17cf15b2077c5ea611913f80f85f Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Wed, 7 Oct 2015 11:08:57 +0200 Subject: drivers: clk: st: PLL rate change implementation for DVFS Change A9 PLL rate, as per requirement from the cpufreq framework, for DVFS. For rate change, the A9 clock needs to be temporarily sourced from PLL external to A9 and then sourced back to A9-PLL Signed-off-by: Pankaj Dev Signed-off-by: Gabriel Fernandez Signed-off-by: Stephen Boyd --- drivers/clk/st/clkgen.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'drivers/clk/st/clkgen.h') diff --git a/drivers/clk/st/clkgen.h b/drivers/clk/st/clkgen.h index 35c863295268..f7ec2d9139d6 100644 --- a/drivers/clk/st/clkgen.h +++ b/drivers/clk/st/clkgen.h @@ -9,6 +9,8 @@ Copyright (C) 2014 STMicroelectronics #ifndef __CLKGEN_INFO_H #define __CLKGEN_INFO_H +extern spinlock_t clkgen_a9_lock; + struct clkgen_field { unsigned int offset; unsigned int mask; -- cgit v1.2.3-73-gaa49b