From 3530570fd43632b60b00e5ea17519d2bd69d1434 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 27 Sep 2006 13:28:23 +0900 Subject: sh: Kill off dead code for SE and SystemH boards. Some of these have suffered some bitrot, and so there is some degree of dead code that has been left sitting around, clean it up.. Signed-off-by: Paul Mundt --- arch/sh/boards/renesas/systemh/io.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'arch/sh/boards/renesas/systemh/io.c') diff --git a/arch/sh/boards/renesas/systemh/io.c b/arch/sh/boards/renesas/systemh/io.c index cf979011aa94..85511576d414 100644 --- a/arch/sh/boards/renesas/systemh/io.c +++ b/arch/sh/boards/renesas/systemh/io.c @@ -15,7 +15,7 @@ #include #include -#include "../../drivers/pci/pci-sh7751.h" +#include "../../../drivers/pci/pci-sh7751.h" /* * The 7751 SystemH Engine uses the built-in PCI controller (PCIC) -- cgit From 373e68b5472d421cbd2703e7a77caf053f78c005 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 27 Sep 2006 15:41:24 +0900 Subject: sh: Board updates for I/O routine rework. This updates the various boards for some of the recent I/O routine updates. Signed-off-by: Paul Mundt --- arch/sh/Makefile | 3 - arch/sh/boards/renesas/hs7751rvoip/io.c | 159 +++++++++++++++++------------ arch/sh/boards/renesas/hs7751rvoip/setup.c | 5 +- arch/sh/boards/renesas/systemh/io.c | 96 ++--------------- arch/sh/boards/renesas/systemh/irq.c | 2 +- arch/sh/boards/renesas/systemh/setup.c | 14 +-- arch/sh/boards/se/7300/io.c | 8 +- arch/sh/boards/se/7300/irq.c | 2 +- arch/sh/boards/se/7300/led.c | 18 +--- arch/sh/boards/se/7300/setup.c | 3 +- arch/sh/boards/se/73180/setup.c | 3 +- arch/sh/boards/se/770x/io.c | 52 ++-------- arch/sh/boards/se/770x/irq.c | 2 +- arch/sh/boards/se/770x/led.c | 2 +- arch/sh/boards/se/770x/mach.c | 7 +- arch/sh/boards/se/770x/setup.c | 2 +- arch/sh/boards/se/7751/io.c | 26 ++--- arch/sh/boards/se/7751/irq.c | 2 +- arch/sh/boards/se/7751/led.c | 3 +- arch/sh/boards/se/7751/mach.c | 8 +- arch/sh/boards/se/7751/setup.c | 6 +- arch/sh/boards/sh03/setup.c | 25 ++--- arch/sh/boards/snapgear/io.c | 63 ++---------- arch/sh/boards/snapgear/rtc.c | 3 - arch/sh/boards/snapgear/setup.c | 97 +----------------- arch/sh/boards/titan/io.c | 4 +- arch/sh/cchips/Kconfig | 6 +- arch/sh/kernel/cf-enabler.c | 7 +- drivers/net/stnic.c | 2 +- include/asm-sh/hs7751rvoip/hs7751rvoip.h | 3 + include/asm-sh/mc146818rtc.h | 2 +- include/asm-sh/se.h | 80 +++++++++++++++ include/asm-sh/se/io.h | 35 ------- include/asm-sh/se/se.h | 77 -------------- include/asm-sh/se7300.h | 64 ++++++++++++ include/asm-sh/se7300/io.h | 29 ------ include/asm-sh/se7300/se7300.h | 61 ----------- include/asm-sh/se73180.h | 65 ++++++++++++ include/asm-sh/se73180/io.h | 32 ------ include/asm-sh/se73180/se73180.h | 62 ----------- include/asm-sh/se7751.h | 71 +++++++++++++ include/asm-sh/se7751/io.h | 42 -------- include/asm-sh/se7751/se7751.h | 68 ------------ include/asm-sh/sh03/io.h | 10 +- include/asm-sh/snapgear.h | 79 ++++++++++++++ include/asm-sh/snapgear/io.h | 92 ----------------- include/asm-sh/systemh/7751systemh.h | 68 ------------ include/asm-sh/systemh/io.h | 43 -------- include/asm-sh/systemh7751.h | 71 +++++++++++++ 49 files changed, 607 insertions(+), 1077 deletions(-) create mode 100644 include/asm-sh/se.h delete mode 100644 include/asm-sh/se/io.h delete mode 100644 include/asm-sh/se/se.h create mode 100644 include/asm-sh/se7300.h delete mode 100644 include/asm-sh/se7300/io.h delete mode 100644 include/asm-sh/se7300/se7300.h create mode 100644 include/asm-sh/se73180.h delete mode 100644 include/asm-sh/se73180/io.h delete mode 100644 include/asm-sh/se73180/se73180.h create mode 100644 include/asm-sh/se7751.h delete mode 100644 include/asm-sh/se7751/io.h delete mode 100644 include/asm-sh/se7751/se7751.h create mode 100644 include/asm-sh/snapgear.h delete mode 100644 include/asm-sh/snapgear/io.h delete mode 100644 include/asm-sh/systemh/7751systemh.h delete mode 100644 include/asm-sh/systemh/io.h create mode 100644 include/asm-sh/systemh7751.h (limited to 'arch/sh/boards/renesas/systemh/io.c') diff --git a/arch/sh/Makefile b/arch/sh/Makefile index 55dcba2c06fc..65676c33822e 100644 --- a/arch/sh/Makefile +++ b/arch/sh/Makefile @@ -111,10 +111,7 @@ machdir-$(CONFIG_SH_UNKNOWN) := unknown incdir-y := $(notdir $(machdir-y)) -incdir-$(CONFIG_SH_SOLUTION_ENGINE) := se incdir-$(CONFIG_SH_7751_SOLUTION_ENGINE) := se7751 -incdir-$(CONFIG_SH_7300_SOLUTION_ENGINE) := se7300 -incdir-$(CONFIG_SH_73180_SOLUTION_ENGINE) := se73180 incdir-$(CONFIG_SH_HP6XX) := hp6xx ifneq ($(machdir-y),) diff --git a/arch/sh/boards/renesas/hs7751rvoip/io.c b/arch/sh/boards/renesas/hs7751rvoip/io.c index edecf107fc13..ecdce7ef6a34 100644 --- a/arch/sh/boards/renesas/hs7751rvoip/io.c +++ b/arch/sh/boards/renesas/hs7751rvoip/io.c @@ -21,10 +21,8 @@ #include #include "../../../drivers/pci/pci-sh7751.h" -extern void *area5_io8_base; /* Area 5 8bit I/O Base address */ extern void *area6_io8_base; /* Area 6 8bit I/O Base address */ extern void *area5_io16_base; /* Area 5 16bit I/O Base address */ -extern void *area6_io16_base; /* Area 6 16bit I/O Base address */ /* * The 7751R HS7751RVoIP uses the built-in PCI controller (PCIC) @@ -37,16 +35,10 @@ extern void *area6_io16_base; /* Area 6 16bit I/O Base address */ #define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR) #define PCI_IO_AREA SH7751_PCI_IO_BASE #define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE - #define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) -#if defined(CONFIG_HS7751RVOIP_CODEC) #define CODEC_IO_BASE 0x1000 -#endif - -#define maybebadio(name,port) \ - printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \ - #name, (port), (__u32) __builtin_return_address(0)) +#define CODEC_IOMAP(a) ((unsigned long)area6_io8_base + ((a) - CODEC_IO_BASE)) static inline void delay(void) { @@ -61,7 +53,7 @@ static inline unsigned long port2adr(unsigned int port) else return ((unsigned long)area5_io16_base + 0x800 + ((port-0x1f0) << 1)); else - maybebadio(port2adr, (unsigned long)port); + maybebadio((unsigned long)port); return port; } @@ -109,15 +101,15 @@ codec_port(unsigned long port) unsigned char hs7751rvoip_inb(unsigned long port) { if (PXSEG(port)) - return *(volatile unsigned char *)port; + return ctrl_inb(port); #if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) - return *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE)); + return ctrl_inb(CODEC_IOMAP(port)); #endif else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - return *(volatile unsigned char *)PCI_IOMAP(port); + return ctrl_inb(PCI_IOMAP(port)); else - return (*(volatile unsigned short *)port2adr(port) & 0xff); + return ctrl_inw(port2adr(port)) & 0xff; } unsigned char hs7751rvoip_inb_p(unsigned long port) @@ -125,15 +117,15 @@ unsigned char hs7751rvoip_inb_p(unsigned long port) unsigned char v; if (PXSEG(port)) - v = *(volatile unsigned char *)port; + v = ctrl_inb(port); #if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) - v = *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE)); + v = ctrl_inb(CODEC_IOMAP(port)); #endif else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - v = *(volatile unsigned char *)PCI_IOMAP(port); + v = ctrl_inb(PCI_IOMAP(port)); else - v = (*(volatile unsigned short *)port2adr(port) & 0xff); + v = ctrl_inw(port2adr(port)) & 0xff; delay(); return v; } @@ -141,22 +133,22 @@ unsigned char hs7751rvoip_inb_p(unsigned long port) unsigned short hs7751rvoip_inw(unsigned long port) { if (PXSEG(port)) - return *(volatile unsigned short *)port; + return ctrl_inw(port); else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - return *(volatile unsigned short *)PCI_IOMAP(port); + return ctrl_inw(PCI_IOMAP(port)); else - maybebadio(inw, port); + maybebadio(port); return 0; } unsigned int hs7751rvoip_inl(unsigned long port) { if (PXSEG(port)) - return *(volatile unsigned long *)port; + return ctrl_inl(port); else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - return *(volatile unsigned long *)PCI_IOMAP(port); + return ctrl_inl(PCI_IOMAP(port)); else - maybebadio(inl, port); + maybebadio(port); return 0; } @@ -164,137 +156,168 @@ void hs7751rvoip_outb(unsigned char value, unsigned long port) { if (PXSEG(port)) - *(volatile unsigned char *)port = value; + ctrl_outb(value, port); #if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) - *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE)) = value; + ctrl_outb(value, CODEC_IOMAP(port)); #endif else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - *(unsigned char *)PCI_IOMAP(port) = value; + ctrl_outb(value, PCI_IOMAP(port)); else - *(volatile unsigned short *)port2adr(port) = value; + ctrl_outb(value, port2adr(port)); } void hs7751rvoip_outb_p(unsigned char value, unsigned long port) { if (PXSEG(port)) - *(volatile unsigned char *)port = value; + ctrl_outb(value, port); #if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) - *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE)) = value; + ctrl_outb(value, CODEC_IOMAP(port)); #endif else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - *(unsigned char *)PCI_IOMAP(port) = value; + ctrl_outb(value, PCI_IOMAP(port)); else - *(volatile unsigned short *)port2adr(port) = value; + ctrl_outw(value, port2adr(port)); + delay(); } void hs7751rvoip_outw(unsigned short value, unsigned long port) { if (PXSEG(port)) - *(volatile unsigned short *)port = value; + ctrl_outw(value, port); else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - *(unsigned short *)PCI_IOMAP(port) = value; + ctrl_outw(value, PCI_IOMAP(port)); else - maybebadio(outw, port); + maybebadio(port); } void hs7751rvoip_outl(unsigned int value, unsigned long port) { if (PXSEG(port)) - *(volatile unsigned long *)port = value; + ctrl_outl(value, port); else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - *((unsigned long *)PCI_IOMAP(port)) = value; + ctrl_outl(value, PCI_IOMAP(port)); else - maybebadio(outl, port); + maybebadio(port); } void hs7751rvoip_insb(unsigned long port, void *addr, unsigned long count) { + u8 *buf = addr; + if (PXSEG(port)) - while (count--) *((unsigned char *) addr)++ = *(volatile unsigned char *)port; + while (count--) + *buf++ = ctrl_inb(port); #if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) - while (count--) *((unsigned char *) addr)++ = *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE)); + while (count--) + *buf++ = ctrl_inb(CODEC_IOMAP(port)); #endif else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { - volatile __u8 *bp = (__u8 *)PCI_IOMAP(port); + volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port); - while (count--) *((volatile unsigned char *) addr)++ = *bp; + while (count--) + *buf++ = *bp; } else { - volatile __u16 *p = (volatile unsigned short *)port2adr(port); + volatile u16 *p = (volatile u16 *)port2adr(port); - while (count--) *((unsigned char *) addr)++ = *p & 0xff; + while (count--) + *buf++ = *p & 0xff; } } void hs7751rvoip_insw(unsigned long port, void *addr, unsigned long count) { - volatile __u16 *p; + volatile u16 *p; + u16 *buf = addr; if (PXSEG(port)) - p = (volatile unsigned short *)port; + p = (volatile u16 *)port; else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - p = (volatile unsigned short *)PCI_IOMAP(port); + p = (volatile u16 *)PCI_IOMAP(port); else - p = (volatile unsigned short *)port2adr(port); - while (count--) *((__u16 *) addr)++ = *p; + p = (volatile u16 *)port2adr(port); + while (count--) + *buf++ = *p; } void hs7751rvoip_insl(unsigned long port, void *addr, unsigned long count) { + if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { - volatile __u32 *p = (__u32 *)PCI_IOMAP(port); + volatile u32 *p = (volatile u32 *)PCI_IOMAP(port); + u32 *buf = addr; - while (count--) *((__u32 *) addr)++ = *p; + while (count--) + *buf++ = *p; } else - maybebadio(insl, port); + maybebadio(port); } void hs7751rvoip_outsb(unsigned long port, const void *addr, unsigned long count) { + const u8 *buf = addr; + if (PXSEG(port)) - while (count--) *(volatile unsigned char *)port = *((unsigned char *) addr)++; + while (count--) + ctrl_outb(*buf++, port); #if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) - while (count--) *(volatile unsigned char *)((unsigned long)area6_io8_base+(port-CODEC_IO_BASE)) = *((unsigned char *) addr)++; + while (count--) + ctrl_outb(*buf++, CODEC_IOMAP(port)); #endif else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { - volatile __u8 *bp = (__u8 *)PCI_IOMAP(port); + volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port); - while (count--) *bp = *((volatile unsigned char *) addr)++; + while (count--) + *bp = *buf++; } else { - volatile __u16 *p = (volatile unsigned short *)port2adr(port); + volatile u16 *p = (volatile u16 *)port2adr(port); - while (count--) *p = *((unsigned char *) addr)++; + while (count--) + *p = *buf++; } } void hs7751rvoip_outsw(unsigned long port, const void *addr, unsigned long count) { - volatile __u16 *p; + volatile u16 *p; + const u16 *buf = addr; if (PXSEG(port)) - p = (volatile unsigned short *)port; + p = (volatile u16 *)port; else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - p = (volatile unsigned short *)PCI_IOMAP(port); + p = (volatile u16 *)PCI_IOMAP(port); else - p = (volatile unsigned short *)port2adr(port); - while (count--) *p = *((__u16 *) addr)++; + p = (volatile u16 *)port2adr(port); + + while (count--) + *p = *buf++; } void hs7751rvoip_outsl(unsigned long port, const void *addr, unsigned long count) { + const u32 *buf = addr; + if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { - volatile __u32 *p = (__u32 *)PCI_IOMAP(port); + volatile u32 *p = (volatile u32 *)PCI_IOMAP(port); - while (count--) *p = *((__u32 *) addr)++; + while (count--) + *p = *buf++; } else - maybebadio(outsl, port); + maybebadio(port); } -unsigned long hs7751rvoip_isa_port2addr(unsigned long offset) +void __iomem *hs7751rvoip_ioport_map(unsigned long port, unsigned int size) { - return port2adr(offset); + if (PXSEG(port)) + return (void __iomem *)port; + else if (unlikely(codec_port(port) && (size == 1))) + return (void __iomem *)CODEC_IOMAP(port); + else if (CHECK_SH7751_PCIIO(port)) + return (void __iomem *)PCI_IOMAP(port); + + return (void __iomem *)port2adr(port); } diff --git a/arch/sh/boards/renesas/hs7751rvoip/setup.c b/arch/sh/boards/renesas/hs7751rvoip/setup.c index aa51bda931f6..a2cbcc5d530f 100644 --- a/arch/sh/boards/renesas/hs7751rvoip/setup.c +++ b/arch/sh/boards/renesas/hs7751rvoip/setup.c @@ -17,9 +17,8 @@ #include #include #include -#include -#include #include +#include #include #include #include @@ -60,8 +59,8 @@ struct sh_machine_vector mv_hs7751rvoip __initmv = { .mv_outsw = hs7751rvoip_outsw, .mv_outsl = hs7751rvoip_outsl, - .mv_isa_port2addr = hs7751rvoip_isa_port2addr, .mv_init_irq = hs7751rvoip_init_irq, + .mv_ioport_map = hs7751rvoip_ioport_map, }; ALIAS_MV(hs7751rvoip) diff --git a/arch/sh/boards/renesas/systemh/io.c b/arch/sh/boards/renesas/systemh/io.c index 85511576d414..0befd4f9894c 100644 --- a/arch/sh/boards/renesas/systemh/io.c +++ b/arch/sh/boards/renesas/systemh/io.c @@ -10,11 +10,10 @@ #include #include -#include +#include +#include #include #include - -#include #include "../../../drivers/pci/pci-sh7751.h" /* @@ -31,11 +30,6 @@ #define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) #define ETHER_IOMAP(adr) (0xB3000000 + (adr)) /*map to 16bits access area of smc lan chip*/ - -#define maybebadio(name,port) \ - printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \ - #name, (port), (__u32) __builtin_return_address(0)) - static inline void delay(void) { ctrl_inw(0xa0000000); @@ -46,11 +40,7 @@ port2adr(unsigned int port) { if (port >= 0x2000) return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); -#if 0 - else - return (volatile __u16 *) (PA_SUPERIO + (port << 1)); -#endif - maybebadio(name,(unsigned long)port); + maybebadio((unsigned long)port); return (volatile __u16*)port; } @@ -111,7 +101,7 @@ unsigned short sh7751systemh_inw(unsigned long port) else if (port <= 0x3F1) return *(volatile unsigned int *)ETHER_IOMAP(port); else - maybebadio(inw, port); + maybebadio(port); return 0; } @@ -126,7 +116,7 @@ unsigned int sh7751systemh_inl(unsigned long port) else if (port <= 0x3F1) return *(volatile unsigned int *)ETHER_IOMAP(port); else - maybebadio(inl, port); + maybebadio(port); return 0; } @@ -167,7 +157,7 @@ void sh7751systemh_outw(unsigned short value, unsigned long port) else if (port <= 0x3F1) *(volatile unsigned short *)ETHER_IOMAP(port) = value; else - maybebadio(outw, port); + maybebadio(port); } void sh7751systemh_outl(unsigned int value, unsigned long port) @@ -177,7 +167,7 @@ void sh7751systemh_outl(unsigned int value, unsigned long port) else if (CHECK_SH7751_PCIIO(port)) *((unsigned long*)PCI_IOMAP(port)) = value; else - maybebadio(outl, port); + maybebadio(port); } void sh7751systemh_insb(unsigned long port, void *addr, unsigned long count) @@ -194,7 +184,7 @@ void sh7751systemh_insw(unsigned long port, void *addr, unsigned long count) void sh7751systemh_insl(unsigned long port, void *addr, unsigned long count) { - maybebadio(insl, port); + maybebadio(port); } void sh7751systemh_outsb(unsigned long port, const void *addr, unsigned long count) @@ -211,73 +201,5 @@ void sh7751systemh_outsw(unsigned long port, const void *addr, unsigned long cou void sh7751systemh_outsl(unsigned long port, const void *addr, unsigned long count) { - maybebadio(outsw, port); -} - -/* For read/write calls, just copy generic (pass-thru); PCIMBR is */ -/* already set up. For a larger memory space, these would need to */ -/* reset PCIMBR as needed on a per-call basis... */ - -unsigned char sh7751systemh_readb(unsigned long addr) -{ - return *(volatile unsigned char*)addr; -} - -unsigned short sh7751systemh_readw(unsigned long addr) -{ - return *(volatile unsigned short*)addr; -} - -unsigned int sh7751systemh_readl(unsigned long addr) -{ - return *(volatile unsigned long*)addr; -} - -void sh7751systemh_writeb(unsigned char b, unsigned long addr) -{ - *(volatile unsigned char*)addr = b; -} - -void sh7751systemh_writew(unsigned short b, unsigned long addr) -{ - *(volatile unsigned short*)addr = b; -} - -void sh7751systemh_writel(unsigned int b, unsigned long addr) -{ - *(volatile unsigned long*)addr = b; -} - - - -/* Map ISA bus address to the real address. Only for PCMCIA. */ - -/* ISA page descriptor. */ -static __u32 sh_isa_memmap[256]; - -#if 0 -static int -sh_isa_mmap(__u32 start, __u32 length, __u32 offset) -{ - int idx; - - if (start >= 0x100000 || (start & 0xfff) || (length != 0x1000)) - return -1; - - idx = start >> 12; - sh_isa_memmap[idx] = 0xb8000000 + (offset &~ 0xfff); - printk("sh_isa_mmap: start %x len %x offset %x (idx %x paddr %x)\n", - start, length, offset, idx, sh_isa_memmap[idx]); - return 0; -} -#endif - -unsigned long -sh7751systemh_isa_port2addr(unsigned long offset) -{ - int idx; - - idx = (offset >> 12) & 0xff; - offset &= 0xfff; - return sh_isa_memmap[idx] + offset; + maybebadio(port); } diff --git a/arch/sh/boards/renesas/systemh/irq.c b/arch/sh/boards/renesas/systemh/irq.c index 8372d967f601..53731a0abb8f 100644 --- a/arch/sh/boards/renesas/systemh/irq.c +++ b/arch/sh/boards/renesas/systemh/irq.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include /* address of external interrupt mask register diff --git a/arch/sh/boards/renesas/systemh/setup.c b/arch/sh/boards/renesas/systemh/setup.c index 826fa3d7669c..433c7c3f35e2 100644 --- a/arch/sh/boards/renesas/systemh/setup.c +++ b/arch/sh/boards/renesas/systemh/setup.c @@ -15,9 +15,8 @@ * for more details. */ #include -#include -#include #include +#include extern void make_systemh_irq(unsigned int irq); @@ -31,8 +30,6 @@ const char *get_system_type(void) */ void __init init_7751systemh_IRQ(void) { -/* make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); LAN */ -/* make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-4); */ make_systemh_irq(0xb); /* Ethernet interrupt */ } @@ -60,15 +57,6 @@ struct sh_machine_vector mv_7751systemh __initmv = { .mv_outsw = sh7751systemh_outsw, .mv_outsl = sh7751systemh_outsl, - .mv_readb = sh7751systemh_readb, - .mv_readw = sh7751systemh_readw, - .mv_readl = sh7751systemh_readl, - .mv_writeb = sh7751systemh_writeb, - .mv_writew = sh7751systemh_writew, - .mv_writel = sh7751systemh_writel, - - .mv_isa_port2addr = sh7751systemh_isa_port2addr, - .mv_init_irq = init_7751systemh_IRQ, }; ALIAS_MV(7751systemh) diff --git a/arch/sh/boards/se/7300/io.c b/arch/sh/boards/se/7300/io.c index f449a94ddffd..8a03d7a52a7c 100644 --- a/arch/sh/boards/se/7300/io.c +++ b/arch/sh/boards/se/7300/io.c @@ -9,8 +9,8 @@ */ #include -#include #include +#include #define badio(fn, a) panic("bad i/o operation %s for %08lx.", #fn, a) @@ -99,6 +99,7 @@ bad_outb(struct iop *p, unsigned char value, unsigned long port) badio(inw, port); } +#ifdef CONFIG_SMC91X /* MSTLANEX01 LAN at 0xb400:0000 */ static struct iop laniop = { .start = 0x300, @@ -110,6 +111,7 @@ static struct iop laniop = { .outb = simple_outb, .outw = simple_outw, }; +#endif /* NE2000 pc card NIC */ static struct iop neiop = { @@ -123,6 +125,7 @@ static struct iop neiop = { .outw = simple_outw, }; +#ifdef CONFIG_IDE /* CF in CF slot */ static struct iop cfiop = { .base = 0xb0600000, @@ -132,12 +135,13 @@ static struct iop cfiop = { .outb = pcc_outb, .outw = simple_outw, }; +#endif static __inline__ struct iop * port2iop(unsigned long port) { if (0) ; -#if defined(CONFIG_SMC91111) +#if defined(CONFIG_SMC91X) else if (laniop.check(&laniop, port)) return &laniop; #endif diff --git a/arch/sh/boards/se/7300/irq.c b/arch/sh/boards/se/7300/irq.c index 216a78d1a108..ad1034f98a29 100644 --- a/arch/sh/boards/se/7300/irq.c +++ b/arch/sh/boards/se/7300/irq.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include /* * Initialize IRQ setting diff --git a/arch/sh/boards/se/7300/led.c b/arch/sh/boards/se/7300/led.c index ad51f0a9c1e3..4d03bb7774be 100644 --- a/arch/sh/boards/se/7300/led.c +++ b/arch/sh/boards/se/7300/led.c @@ -12,24 +12,10 @@ */ #include -#include - -static void -mach_led(int position, int value) -{ - volatile unsigned short *p = (volatile unsigned short *) PA_LED; - - if (value) { - *p |= (1 << 8); - } else { - *p &= ~(1 << 8); - } -} - +#include /* Cycle the LED's in the clasic Knightrider/Sun pattern */ -void -heartbeat_7300se(void) +void heartbeat_7300se(void) { static unsigned int cnt = 0, period = 0; volatile unsigned short *p = (volatile unsigned short *) PA_LED; diff --git a/arch/sh/boards/se/7300/setup.c b/arch/sh/boards/se/7300/setup.c index ebcd98d4c081..bb7e1a189be8 100644 --- a/arch/sh/boards/se/7300/setup.c +++ b/arch/sh/boards/se/7300/setup.c @@ -9,8 +9,7 @@ #include #include -#include -#include +#include void heartbeat_7300se(void); void init_7300se_IRQ(void); diff --git a/arch/sh/boards/se/73180/setup.c b/arch/sh/boards/se/73180/setup.c index cdb7b5f8d942..cddc7a2b858f 100644 --- a/arch/sh/boards/se/73180/setup.c +++ b/arch/sh/boards/se/73180/setup.c @@ -11,8 +11,7 @@ #include #include -#include -#include +#include void heartbeat_73180se(void); void init_73180se_IRQ(void); diff --git a/arch/sh/boards/se/770x/io.c b/arch/sh/boards/se/770x/io.c index 9a39ee963143..5102201c97ab 100644 --- a/arch/sh/boards/se/770x/io.c +++ b/arch/sh/boards/se/770x/io.c @@ -1,4 +1,4 @@ -/* $Id: io.c,v 1.5 2004/02/22 23:08:43 kkojima Exp $ +/* $Id: io.c,v 1.6 2006/01/04 17:53:54 lethal Exp $ * * linux/arch/sh/kernel/io_se.c * @@ -11,7 +11,7 @@ #include #include #include -#include +#include /* SH pcmcia io window base, start and end. */ int sh_pcic_io_wbase = 0xb8400000; @@ -52,10 +52,6 @@ shifted_port(unsigned long port) return 1; } -#define maybebadio(name,port) \ - printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \ - #name, (port), (__u32) __builtin_return_address(0)) - unsigned char se_inb(unsigned long port) { if (sh_pcic_io_start <= port && port <= sh_pcic_io_stop) @@ -86,13 +82,13 @@ unsigned short se_inw(unsigned long port) (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)) return *port2adr(port); else - maybebadio(inw, port); + maybebadio(port); return 0; } unsigned int se_inl(unsigned long port) { - maybebadio(inl, port); + maybebadio(port); return 0; } @@ -123,12 +119,12 @@ void se_outw(unsigned short value, unsigned long port) (sh_pcic_io_start <= port && port <= sh_pcic_io_stop)) *port2adr(port) = value; else - maybebadio(outw, port); + maybebadio(port); } void se_outl(unsigned int value, unsigned long port) { - maybebadio(outl, port); + maybebadio(port); } void se_insb(unsigned long port, void *addr, unsigned long count) @@ -159,7 +155,7 @@ void se_insw(unsigned long port, void *addr, unsigned long count) void se_insl(unsigned long port, void *addr, unsigned long count) { - maybebadio(insl, port); + maybebadio(port); } void se_outsb(unsigned long port, const void *addr, unsigned long count) @@ -190,37 +186,5 @@ void se_outsw(unsigned long port, const void *addr, unsigned long count) void se_outsl(unsigned long port, const void *addr, unsigned long count) { - maybebadio(outsw, port); -} - -/* Map ISA bus address to the real address. Only for PCMCIA. */ - -/* ISA page descriptor. */ -static __u32 sh_isa_memmap[256]; - -static int -sh_isa_mmap(__u32 start, __u32 length, __u32 offset) -{ - int idx; - - if (start >= 0x100000 || (start & 0xfff) || (length != 0x1000)) - return -1; - - idx = start >> 12; - sh_isa_memmap[idx] = 0xb8000000 + (offset &~ 0xfff); -#if 0 - printk("sh_isa_mmap: start %x len %x offset %x (idx %x paddr %x)\n", - start, length, offset, idx, sh_isa_memmap[idx]); -#endif - return 0; -} - -unsigned long -se_isa_port2addr(unsigned long offset) -{ - int idx; - - idx = (offset >> 12) & 0xff; - offset &= 0xfff; - return sh_isa_memmap[idx] + offset; + maybebadio(port); } diff --git a/arch/sh/boards/se/770x/irq.c b/arch/sh/boards/se/770x/irq.c index 3e558716ce10..cff6700bbafd 100644 --- a/arch/sh/boards/se/770x/irq.c +++ b/arch/sh/boards/se/770x/irq.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include /* * Initialize IRQ setting diff --git a/arch/sh/boards/se/770x/led.c b/arch/sh/boards/se/770x/led.c index 73e9848387ea..daf7b1ee786a 100644 --- a/arch/sh/boards/se/770x/led.c +++ b/arch/sh/boards/se/770x/led.c @@ -10,7 +10,7 @@ */ #include -#include +#include /* Cycle the LED's in the clasic Knightrider/Sun pattern */ void heartbeat_se(void) diff --git a/arch/sh/boards/se/770x/mach.c b/arch/sh/boards/se/770x/mach.c index 6ec07bd3dcf1..e8968b71c353 100644 --- a/arch/sh/boards/se/770x/mach.c +++ b/arch/sh/boards/se/770x/mach.c @@ -13,12 +13,9 @@ #include #include -#include - -#include +#include void heartbeat_se(void); -void setup_se(void); void init_se_IRQ(void); /* @@ -57,8 +54,6 @@ struct sh_machine_vector mv_se __initmv = { .mv_outsw = se_outsw, .mv_outsl = se_outsl, - .mv_isa_port2addr = se_isa_port2addr, - .mv_init_irq = init_se_IRQ, #ifdef CONFIG_HEARTBEAT .mv_heartbeat = heartbeat_se, diff --git a/arch/sh/boards/se/770x/setup.c b/arch/sh/boards/se/770x/setup.c index b6730ea57502..c9f75272e751 100644 --- a/arch/sh/boards/se/770x/setup.c +++ b/arch/sh/boards/se/770x/setup.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include /* diff --git a/arch/sh/boards/se/7751/io.c b/arch/sh/boards/se/7751/io.c index 99041b269261..0e8a3ba48316 100644 --- a/arch/sh/boards/se/7751/io.c +++ b/arch/sh/boards/se/7751/io.c @@ -1,4 +1,4 @@ -/* +/* * linux/arch/sh/kernel/io_7751se.c * * Copyright (C) 2001 Ian da Silva, Jeremy Siegel @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include @@ -52,10 +52,6 @@ int sh_pcic_io_dummy; #define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) -#define maybebadio(name,port) \ - printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \ - #name, (port), (__u32) __builtin_return_address(0)) - static inline void delay(void) { ctrl_inw(0xa0000000); @@ -66,11 +62,7 @@ port2adr(unsigned int port) { if (port >= 0x2000) return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); -#if 0 - else - return (volatile __u16 *) (PA_SUPERIO + (port << 1)); -#endif - maybebadio(name,(unsigned long)port); + maybebadio((unsigned long)port); return (volatile __u16*)port; } @@ -140,7 +132,7 @@ unsigned short sh7751se_inw(unsigned long port) else if (port >= 0x2000) return *port2adr(port); else - maybebadio(inw, port); + maybebadio(port); return 0; } @@ -153,7 +145,7 @@ unsigned int sh7751se_inl(unsigned long port) else if (port >= 0x2000) return *port2adr(port); else - maybebadio(inl, port); + maybebadio(port); return 0; } @@ -188,7 +180,7 @@ void sh7751se_outw(unsigned short value, unsigned long port) else if (port >= 0x2000) *port2adr(port) = value; else - maybebadio(outw, port); + maybebadio(port); } void sh7751se_outl(unsigned int value, unsigned long port) @@ -198,17 +190,17 @@ void sh7751se_outl(unsigned int value, unsigned long port) else if (CHECK_SH7751_PCIIO(port)) *((unsigned long*)PCI_IOMAP(port)) = value; else - maybebadio(outl, port); + maybebadio(port); } void sh7751se_insl(unsigned long port, void *addr, unsigned long count) { - maybebadio(insl, port); + maybebadio(port); } void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count) { - maybebadio(outsw, port); + maybebadio(port); } /* Map ISA bus address to the real address. Only for PCMCIA. */ diff --git a/arch/sh/boards/se/7751/irq.c b/arch/sh/boards/se/7751/irq.c index bf6c023615df..c607b0a48479 100644 --- a/arch/sh/boards/se/7751/irq.c +++ b/arch/sh/boards/se/7751/irq.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include /* * Initialize IRQ setting diff --git a/arch/sh/boards/se/7751/led.c b/arch/sh/boards/se/7751/led.c index 4405e26cf866..ff0355dea81b 100644 --- a/arch/sh/boards/se/7751/led.c +++ b/arch/sh/boards/se/7751/led.c @@ -8,9 +8,8 @@ * * This file contains Solution Engine specific LED code. */ - -#include #include +#include /* Cycle the LED's in the clasic Knightrider/Sun pattern */ void heartbeat_7751se(void) diff --git a/arch/sh/boards/se/7751/mach.c b/arch/sh/boards/se/7751/mach.c index 62d8d3e62590..1bb9047d863b 100644 --- a/arch/sh/boards/se/7751/mach.c +++ b/arch/sh/boards/se/7751/mach.c @@ -10,12 +10,8 @@ */ #include - #include -#include -#include - -#include +#include void heartbeat_7751se(void); void init_7751se_IRQ(void); @@ -44,8 +40,6 @@ struct sh_machine_vector mv_7751se __initmv = { .mv_insl = sh7751se_insl, .mv_outsl = sh7751se_outsl, - .mv_isa_port2addr = sh7751se_isa_port2addr, - .mv_init_irq = init_7751se_IRQ, #ifdef CONFIG_HEARTBEAT .mv_heartbeat = heartbeat_7751se, diff --git a/arch/sh/boards/se/7751/setup.c b/arch/sh/boards/se/7751/setup.c index 48dc5aee67d4..8b693105893c 100644 --- a/arch/sh/boards/se/7751/setup.c +++ b/arch/sh/boards/se/7751/setup.c @@ -1,4 +1,4 @@ -/* +/* * linux/arch/sh/kernel/setup_7751se.c * * Copyright (C) 2000 Kazumoto Kojima @@ -11,11 +11,9 @@ #include #include - -#include #include #include -#include +#include #ifdef CONFIG_SH_KGDB #include diff --git a/arch/sh/boards/sh03/setup.c b/arch/sh/boards/sh03/setup.c index 60290f8f289c..dab742a00c6f 100644 --- a/arch/sh/boards/sh03/setup.c +++ b/arch/sh/boards/sh03/setup.c @@ -7,22 +7,19 @@ #include #include -#include -#include #include +#include #include #include #include #include "../../drivers/pci/pci-sh7751.h" -extern void (*board_time_init)(void); - const char *get_system_type(void) { return "Interface CTP/PCI-SH03)"; } -void init_sh03_IRQ(void) +static void init_sh03_IRQ(void) { ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); @@ -34,24 +31,20 @@ void init_sh03_IRQ(void) extern void *cf_io_base; -unsigned long sh03_isa_port2addr(unsigned long port) +static void __iomem *sh03_ioport_map(unsigned long port, unsigned int size) { if (PXSEG(port)) - return port; + return (void __iomem *)port; /* CompactFlash (IDE) */ - if (((port >= 0x1f0) && (port <= 0x1f7)) || (port == 0x3f6)) { - return (unsigned long)cf_io_base + port; - } - return port + SH7751_PCI_IO_BASE; -} + if (((port >= 0x1f0) && (port <= 0x1f7)) || (port == 0x3f6)) + return (void __iomem *)((unsigned long)cf_io_base + port); -/* - * The Machine Vector - */ + return (void __iomem *)(port + SH7751_PCI_IO_BASE); +} struct sh_machine_vector mv_sh03 __initmv = { .mv_nr_irqs = 48, - .mv_isa_port2addr = sh03_isa_port2addr, + .mv_ioport_map = sh03_ioport_map, .mv_init_irq = init_sh03_IRQ, #ifdef CONFIG_HEARTBEAT diff --git a/arch/sh/boards/snapgear/io.c b/arch/sh/boards/snapgear/io.c index e2eb78fc381d..9f700b8392bb 100644 --- a/arch/sh/boards/snapgear/io.c +++ b/arch/sh/boards/snapgear/io.c @@ -28,39 +28,26 @@ unsigned short secureedge5410_ioport; /* * The SnapGear uses the built-in PCI controller (PCIC) * of the 7751 processor - */ + */ #define PCIIOBR (volatile long *)PCI_REG(SH7751_PCIIOBR) #define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR) #define PCI_IO_AREA SH7751_PCI_IO_BASE #define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE - #define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) - -#define maybebadio(name,port) \ - printk("bad PC-like io %s for port 0x%lx at 0x%08x\n", \ - #name, (port), (__u32) __builtin_return_address(0)) - - static inline void delay(void) { ctrl_inw(0xa0000000); } - static inline volatile __u16 *port2adr(unsigned int port) { -#if 0 - if (port >= 0x2000) - return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); -#endif - maybebadio(name,(unsigned long)port); + maybebadio((unsigned long)port); return (volatile __u16*)port; } - /* In case someone configures the kernel w/o PCI support: in that */ /* scenario, don't ever bother to check for PCI-window addresses */ @@ -115,7 +102,7 @@ unsigned short snapgear_inw(unsigned long port) else if (port >= 0x2000) return *port2adr(port); else - maybebadio(inw, port); + maybebadio(port); return 0; } @@ -129,7 +116,7 @@ unsigned int snapgear_inl(unsigned long port) else if (port >= 0x2000) return *port2adr(port); else - maybebadio(inl, port); + maybebadio(port); return 0; } @@ -167,7 +154,7 @@ void snapgear_outw(unsigned short value, unsigned long port) else if (port >= 0x2000) *port2adr(port) = value; else - maybebadio(outw, port); + maybebadio(port); } @@ -178,49 +165,15 @@ void snapgear_outl(unsigned int value, unsigned long port) else if (CHECK_SH7751_PCIIO(port)) *((unsigned long*)PCI_IOMAP(port)) = value; else - maybebadio(outl, port); + maybebadio(port); } void snapgear_insl(unsigned long port, void *addr, unsigned long count) { - maybebadio(insl, port); + maybebadio(port); } void snapgear_outsl(unsigned long port, const void *addr, unsigned long count) { - maybebadio(outsw, port); -} - -/* Map ISA bus address to the real address. Only for PCMCIA. */ - - -/* ISA page descriptor. */ -static __u32 sh_isa_memmap[256]; - - -#if 0 -static int sh_isa_mmap(__u32 start, __u32 length, __u32 offset) -{ - int idx; - - if (start >= 0x100000 || (start & 0xfff) || (length != 0x1000)) - return -1; - - idx = start >> 12; - sh_isa_memmap[idx] = 0xb8000000 + (offset &~ 0xfff); -#if 0 - printk("sh_isa_mmap: start %x len %x offset %x (idx %x paddr %x)\n", - start, length, offset, idx, sh_isa_memmap[idx]); -#endif - return 0; -} -#endif - -unsigned long snapgear_isa_port2addr(unsigned long offset) -{ - int idx; - - idx = (offset >> 12) & 0xff; - offset &= 0xfff; - return sh_isa_memmap[idx] + offset; + maybebadio(port); } diff --git a/arch/sh/boards/snapgear/rtc.c b/arch/sh/boards/snapgear/rtc.c index b71e009da35c..287bc4ed3ac7 100644 --- a/arch/sh/boards/snapgear/rtc.c +++ b/arch/sh/boards/snapgear/rtc.c @@ -17,10 +17,7 @@ #include #include #include - #include -#include -#include /****************************************************************************/ diff --git a/arch/sh/boards/snapgear/setup.c b/arch/sh/boards/snapgear/setup.c index f1f7c70c9402..66ce32f8b13c 100644 --- a/arch/sh/boards/snapgear/setup.c +++ b/arch/sh/boards/snapgear/setup.c @@ -1,5 +1,4 @@ -/****************************************************************************/ -/* +/* * linux/arch/sh/boards/snapgear/setup.c * * Copyright (C) 2002 David McCullough @@ -12,8 +11,6 @@ * Modified for 7751 Solution Engine by * Ian da Silva and Jeremy Siegel, 2001. */ -/****************************************************************************/ - #include #include #include @@ -21,14 +18,13 @@ #include #include #include - #include -#include +#include #include #include +#include #include -extern void (*board_time_init)(void); extern void secureedge5410_rtc_init(void); extern void pcibios_init(void); @@ -85,91 +81,6 @@ static void __init init_snapgear_IRQ(void) make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); } -/****************************************************************************/ -/* - * Fast poll interrupt simulator. - */ - -/* - * Leave all of the fast timer/fast poll stuff commented out for now, since - * it's not clear whether it actually works or not. Since it wasn't being used - * at all in 2.4, we'll assume it's not sane for 2.6 either.. -- PFM - */ -#if 0 -#define FAST_POLL 1000 -//#define FAST_POLL_INTR - -#define FASTTIMER_IRQ 17 -#define FASTTIMER_IPR_ADDR INTC_IPRA -#define FASTTIMER_IPR_POS 2 -#define FASTTIMER_PRIORITY 3 - -#ifdef FAST_POLL_INTR -#define TMU1_TCR_INIT 0x0020 -#else -#define TMU1_TCR_INIT 0 -#endif -#define TMU_TSTR_INIT 1 -#define TMU1_TCR_CALIB 0x0000 - - -#ifdef FAST_POLL_INTR -static void fast_timer_irq(int irq, void *dev_instance, struct pt_regs *regs) -{ - unsigned long timer_status; - timer_status = ctrl_inw(TMU1_TCR); - timer_status &= ~0x100; - ctrl_outw(timer_status, TMU1_TCR); -} -#endif - -/* - * return the current ticks on the fast timer - */ - -unsigned long fast_timer_count(void) -{ - return(ctrl_inl(TMU1_TCNT)); -} - -/* - * setup a fast timer for profiling etc etc - */ - -static void setup_fast_timer() -{ - unsigned long interval; - -#ifdef FAST_POLL_INTR - interval = (current_cpu_data.module_clock/4 + FAST_POLL/2) / FAST_POLL; - - make_ipr_irq(FASTTIMER_IRQ, FASTTIMER_IPR_ADDR, FASTTIMER_IPR_POS, - FASTTIMER_PRIORITY); - - printk("SnapGear: %dHz fast timer on IRQ %d\n",FAST_POLL,FASTTIMER_IRQ); - - if (request_irq(FASTTIMER_IRQ, fast_timer_irq, 0, "SnapGear fast timer", - NULL) != 0) - printk("%s(%d): request_irq() failed?\n", __FILE__, __LINE__); -#else - printk("SnapGear: fast timer running\n",FAST_POLL,FASTTIMER_IRQ); - interval = 0xffffffff; -#endif - - ctrl_outb(ctrl_inb(TMU_TSTR) & ~0x2, TMU_TSTR); /* disable timer 1 */ - ctrl_outw(TMU1_TCR_INIT, TMU1_TCR); - ctrl_outl(interval, TMU1_TCOR); - ctrl_outl(interval, TMU1_TCNT); - ctrl_outb(ctrl_inb(TMU_TSTR) | 0x2, TMU_TSTR); /* enable timer 1 */ - - printk("Timer count 1 = 0x%x\n", fast_timer_count()); - udelay(1000); - printk("Timer count 2 = 0x%x\n", fast_timer_count()); -} -#endif - -/****************************************************************************/ - const char *get_system_type(void) { return "SnapGear SecureEdge5410"; @@ -196,8 +107,6 @@ struct sh_machine_vector mv_snapgear __initmv = { .mv_outw_p = snapgear_outw, .mv_outl_p = snapgear_outl, - .mv_isa_port2addr = snapgear_isa_port2addr, - .mv_init_irq = init_snapgear_IRQ, }; ALIAS_MV(snapgear) diff --git a/arch/sh/boards/titan/io.c b/arch/sh/boards/titan/io.c index b886fd233a66..48f3494f55b1 100644 --- a/arch/sh/boards/titan/io.c +++ b/arch/sh/boards/titan/io.c @@ -30,10 +30,10 @@ static inline void delay(void) ctrl_inw(0xa0000000); } -static inline volatile u16 *port2adr(unsigned int port) +static inline unsigned int port2adr(unsigned int port) { maybebadio((unsigned long)port); - return (volatile u16*)port; + return port; } u8 titan_inb(unsigned long port) diff --git a/arch/sh/cchips/Kconfig b/arch/sh/cchips/Kconfig index 155d139884c3..0582ca8346b6 100644 --- a/arch/sh/cchips/Kconfig +++ b/arch/sh/cchips/Kconfig @@ -65,6 +65,11 @@ config HD64461_IRQ Do not change this unless you know what you are doing. +config HD64461_IOBASE + hex "HD64461 start address" + depends on HD64461 + default "0xb0000000" + config HD64461_ENABLER bool "HD64461 PCMCIA enabler" depends on HD64461 @@ -73,7 +78,6 @@ config HD64461_ENABLER via the HD64461 companion chip. Otherwise, say N. - config HD64465_IOBASE hex "HD64465 start address" depends on HD64465 diff --git a/arch/sh/kernel/cf-enabler.c b/arch/sh/kernel/cf-enabler.c index c9b823d1d073..3e5fa1e24df0 100644 --- a/arch/sh/kernel/cf-enabler.c +++ b/arch/sh/kernel/cf-enabler.c @@ -10,7 +10,8 @@ */ #include - +#include +#include #include #include @@ -32,8 +33,6 @@ /* SH4 can't access PCMCIA interface through P2 area. * we must remap it with appropreate attribute bit of the page set. * this part is based on Greg Banks' hd64465_ss.c implementation - Masahiro Abe */ -#include -#include #if defined(CONFIG_CF_AREA6) #define slot_no 0 @@ -84,7 +83,7 @@ static int __init cf_init_default(void) } #if defined(CONFIG_SH_SOLUTION_ENGINE) -#include +#include /* * SolutionEngine diff --git a/drivers/net/stnic.c b/drivers/net/stnic.c index 3fd7a4fee665..e6f90427160c 100644 --- a/drivers/net/stnic.c +++ b/drivers/net/stnic.c @@ -19,7 +19,7 @@ #include #include -#include +#include #include #ifdef CONFIG_SH_STANDARD_BIOS #include diff --git a/include/asm-sh/hs7751rvoip/hs7751rvoip.h b/include/asm-sh/hs7751rvoip/hs7751rvoip.h index 857cc2ebbc69..69faf0171473 100644 --- a/include/asm-sh/hs7751rvoip/hs7751rvoip.h +++ b/include/asm-sh/hs7751rvoip/hs7751rvoip.h @@ -44,6 +44,9 @@ #define IRQ_RINGING 4 /* Ringing IRQ */ #define IRQ_CODEC 5 /* CODEC IRQ */ +#define __IO_PREFIX hs7751rvoip +#include + /* arch/sh/boards/renesas/hs7751rvoip/irq.c */ void init_hs7751rvoip_IRQ(void); diff --git a/include/asm-sh/mc146818rtc.h b/include/asm-sh/mc146818rtc.h index 1707cfb2915d..adc6e67c6b75 100644 --- a/include/asm-sh/mc146818rtc.h +++ b/include/asm-sh/mc146818rtc.h @@ -24,7 +24,7 @@ #define CMOS_WRITE(val,addr) __CMOS_WRITE(val,addr,b) #elif defined(CONFIG_SH_SECUREEDGE5410) -#include +#include #define RTC_PORT(n) SECUREEDGE_IOPORT_ADDR #define CMOS_READ(addr) secureedge5410_cmos_read(addr) diff --git a/include/asm-sh/se.h b/include/asm-sh/se.h new file mode 100644 index 000000000000..a1832154a3aa --- /dev/null +++ b/include/asm-sh/se.h @@ -0,0 +1,80 @@ +#ifndef __ASM_SH_HITACHI_SE_H +#define __ASM_SH_HITACHI_SE_H + +/* + * linux/include/asm-sh/hitachi_se.h + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine support + */ + +/* Box specific addresses. */ + +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_FROM 0x01000000 /* EPROM */ +#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 + +#define PA_EXT4 0x12000000 +#define PA_EXT4_SIZE 0x02000000 +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ + +#define PA_83902 0xb0000000 /* DP83902A */ +#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */ +#define PA_83902_RST 0xb0080000 /* DP83902A reset port */ + +#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */ +#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */ +#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */ +#define PA_LED 0xb0c00000 /* LED */ +#if defined(CONFIG_CPU_SUBTYPE_SH7705) +#define PA_BCR 0xb0e00000 +#else +#define PA_BCR 0xb1400000 /* FPGA */ +#endif + +#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ +#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) + +#define BCR_ILCRA (PA_BCR + 0) +#define BCR_ILCRB (PA_BCR + 2) +#define BCR_ILCRC (PA_BCR + 4) +#define BCR_ILCRD (PA_BCR + 6) +#define BCR_ILCRE (PA_BCR + 8) +#define BCR_ILCRF (PA_BCR + 10) +#define BCR_ILCRG (PA_BCR + 12) + +#if defined(CONFIG_CPU_SUBTYPE_SH7705) +#define IRQ_STNIC 12 +#else +#define IRQ_STNIC 10 +#endif + +#define __IO_PREFIX se +#include + +#endif /* __ASM_SH_HITACHI_SE_H */ diff --git a/include/asm-sh/se/io.h b/include/asm-sh/se/io.h deleted file mode 100644 index 9eeb86cd6cef..000000000000 --- a/include/asm-sh/se/io.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * include/asm-sh/io_se.h - * - * Copyright 2000 Stuart Menefy (stuart.menefy@st.com) - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * IO functions for an Hitachi SolutionEngine - */ - -#ifndef _ASM_SH_IO_SE_H -#define _ASM_SH_IO_SE_H - -extern unsigned char se_inb(unsigned long port); -extern unsigned short se_inw(unsigned long port); -extern unsigned int se_inl(unsigned long port); - -extern void se_outb(unsigned char value, unsigned long port); -extern void se_outw(unsigned short value, unsigned long port); -extern void se_outl(unsigned int value, unsigned long port); - -extern unsigned char se_inb_p(unsigned long port); -extern void se_outb_p(unsigned char value, unsigned long port); - -extern void se_insb(unsigned long port, void *addr, unsigned long count); -extern void se_insw(unsigned long port, void *addr, unsigned long count); -extern void se_insl(unsigned long port, void *addr, unsigned long count); -extern void se_outsb(unsigned long port, const void *addr, unsigned long count); -extern void se_outsw(unsigned long port, const void *addr, unsigned long count); -extern void se_outsl(unsigned long port, const void *addr, unsigned long count); - -extern unsigned long se_isa_port2addr(unsigned long offset); - -#endif /* _ASM_SH_IO_SE_H */ diff --git a/include/asm-sh/se/se.h b/include/asm-sh/se/se.h deleted file mode 100644 index 791c5da0388a..000000000000 --- a/include/asm-sh/se/se.h +++ /dev/null @@ -1,77 +0,0 @@ -#ifndef __ASM_SH_HITACHI_SE_H -#define __ASM_SH_HITACHI_SE_H - -/* - * linux/include/asm-sh/hitachi_se.h - * - * Copyright (C) 2000 Kazumoto Kojima - * - * Hitachi SolutionEngine support - */ - -/* Box specific addresses. */ - -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_FROM 0x01000000 /* EPROM */ -#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 - -#define PA_EXT4 0x12000000 -#define PA_EXT4_SIZE 0x02000000 -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ - -#define PA_83902 0xb0000000 /* DP83902A */ -#define PA_83902_IF 0xb0040000 /* DP83902A remote io port */ -#define PA_83902_RST 0xb0080000 /* DP83902A reset port */ - -#define PA_SUPERIO 0xb0400000 /* SMC37C935A super io chip */ -#define PA_DIPSW0 0xb0800000 /* Dip switch 5,6 */ -#define PA_DIPSW1 0xb0800002 /* Dip switch 7,8 */ -#define PA_LED 0xb0c00000 /* LED */ -#if defined(CONFIG_CPU_SUBTYPE_SH7705) -#define PA_BCR 0xb0e00000 -#else -#define PA_BCR 0xb1400000 /* FPGA */ -#endif - -#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controller */ -#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) - -#define BCR_ILCRA (PA_BCR + 0) -#define BCR_ILCRB (PA_BCR + 2) -#define BCR_ILCRC (PA_BCR + 4) -#define BCR_ILCRD (PA_BCR + 6) -#define BCR_ILCRE (PA_BCR + 8) -#define BCR_ILCRF (PA_BCR + 10) -#define BCR_ILCRG (PA_BCR + 12) - -#if defined(CONFIG_CPU_SUBTYPE_SH7705) -#define IRQ_STNIC 12 -#else -#define IRQ_STNIC 10 -#endif - -#endif /* __ASM_SH_HITACHI_SE_H */ diff --git a/include/asm-sh/se7300.h b/include/asm-sh/se7300.h new file mode 100644 index 000000000000..4e24edccb30d --- /dev/null +++ b/include/asm-sh/se7300.h @@ -0,0 +1,64 @@ +#ifndef __ASM_SH_HITACHI_SE7300_H +#define __ASM_SH_HITACHI_SE7300_H + +/* + * linux/include/asm-sh/se/se7300.h + * + * Copyright (C) 2003 Takashi Kusuda + * + * SH-Mobile SolutionEngine 7300 support + */ + +/* Box specific addresses. */ + +/* Area 0 */ +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ +#define PA_FROM 0x00400000 /* Flash ROM */ +#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ +#define PA_SRAM 0x00800000 /* SRAM */ +#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ +/* Area 1 */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +/* Area 2 */ +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +/* Area 3 */ +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 +/* Area 4 */ +#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ +#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ +#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) +#define PA_LED 0xb0800000 /* LED */ +#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ +#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */ +#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */ +#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */ +/* Area 5 */ +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +/* Area 6 */ +#define PA_LCD1 0xb8000000 +#define PA_LCD2 0xb8800000 + +#define __IO_PREFIX sh7300se +#include + +#endif /* __ASM_SH_HITACHI_SE7300_H */ diff --git a/include/asm-sh/se7300/io.h b/include/asm-sh/se7300/io.h deleted file mode 100644 index c6af85529714..000000000000 --- a/include/asm-sh/se7300/io.h +++ /dev/null @@ -1,29 +0,0 @@ -/* - * include/asm-sh/se7300/io.h - * - * Copyright (C) 2003 Takashi Kusuda - * IO functions for SH-Mobile(SH7300) SolutionEngine - */ - -#ifndef _ASM_SH_IO_7300SE_H -#define _ASM_SH_IO_7300SE_H - -extern unsigned char sh7300se_inb(unsigned long port); -extern unsigned short sh7300se_inw(unsigned long port); -extern unsigned int sh7300se_inl(unsigned long port); - -extern void sh7300se_outb(unsigned char value, unsigned long port); -extern void sh7300se_outw(unsigned short value, unsigned long port); -extern void sh7300se_outl(unsigned int value, unsigned long port); - -extern unsigned char sh7300se_inb_p(unsigned long port); -extern void sh7300se_outb_p(unsigned char value, unsigned long port); - -extern void sh7300se_insb(unsigned long port, void *addr, unsigned long count); -extern void sh7300se_insw(unsigned long port, void *addr, unsigned long count); -extern void sh7300se_insl(unsigned long port, void *addr, unsigned long count); -extern void sh7300se_outsb(unsigned long port, const void *addr, unsigned long count); -extern void sh7300se_outsw(unsigned long port, const void *addr, unsigned long count); -extern void sh7300se_outsl(unsigned long port, const void *addr, unsigned long count); - -#endif /* _ASM_SH_IO_7300SE_H */ diff --git a/include/asm-sh/se7300/se7300.h b/include/asm-sh/se7300/se7300.h deleted file mode 100644 index 3ec1ded86c97..000000000000 --- a/include/asm-sh/se7300/se7300.h +++ /dev/null @@ -1,61 +0,0 @@ -#ifndef __ASM_SH_HITACHI_SE7300_H -#define __ASM_SH_HITACHI_SE7300_H - -/* - * linux/include/asm-sh/se/se7300.h - * - * Copyright (C) 2003 Takashi Kusuda - * - * SH-Mobile SolutionEngine 7300 support - */ - -/* Box specific addresses. */ - -/* Area 0 */ -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ -#define PA_FROM 0x00400000 /* Flash ROM */ -#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ -#define PA_SRAM 0x00800000 /* SRAM */ -#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ -/* Area 1 */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -/* Area 2 */ -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -/* Area 3 */ -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 -/* Area 4 */ -#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ -#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ -#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) -#define PA_LED 0xb0800000 /* LED */ -#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ -#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */ -#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */ -#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */ -/* Area 5 */ -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -/* Area 6 */ -#define PA_LCD1 0xb8000000 -#define PA_LCD2 0xb8800000 - -#endif /* __ASM_SH_HITACHI_SE7300_H */ diff --git a/include/asm-sh/se73180.h b/include/asm-sh/se73180.h new file mode 100644 index 000000000000..3a4acb3e38a1 --- /dev/null +++ b/include/asm-sh/se73180.h @@ -0,0 +1,65 @@ +#ifndef __ASM_SH_HITACHI_SE73180_H +#define __ASM_SH_HITACHI_SE73180_H + +/* + * include/asm-sh/se/se73180.h + * + * Copyright (C) 2003 Takashi Kusuda + * + * SH-Mobile SolutionEngine 73180 support + */ + +/* Box specific addresses. */ + +/* Area 0 */ +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ +#define PA_FROM 0x00400000 /* Flash ROM */ +#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ +#define PA_SRAM 0x00800000 /* SRAM */ +#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ +/* Area 1 */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +/* Area 2 */ +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +/* Area 3 */ +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 +/* Area 4 */ +#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ +#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ +#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) +#define PA_LED 0xb0C00000 /* LED */ +#define LED_SHIFT 0 +#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ +#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */ +#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */ +#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */ +/* Area 5 */ +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +/* Area 6 */ +#define PA_LCD1 0xb8000000 +#define PA_LCD2 0xb8800000 + +#define __IO_PREFIX sh73180se +#include + +#endif /* __ASM_SH_HITACHI_SE73180_H */ diff --git a/include/asm-sh/se73180/io.h b/include/asm-sh/se73180/io.h deleted file mode 100644 index c9cb1b9412c6..000000000000 --- a/include/asm-sh/se73180/io.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * include/asm-sh/se73180/io.h - * - * Copyright (C) 2003 Takashi Kusuda - * Based on include/asm-sh/se7300/io.h - * - * IO functions for SH-Mobile3(SH73180) SolutionEngine - * - */ - -#ifndef _ASM_SH_IO_73180SE_H -#define _ASM_SH_IO_73180SE_H - -extern unsigned char sh73180se_inb(unsigned long port); -extern unsigned short sh73180se_inw(unsigned long port); -extern unsigned int sh73180se_inl(unsigned long port); - -extern void sh73180se_outb(unsigned char value, unsigned long port); -extern void sh73180se_outw(unsigned short value, unsigned long port); -extern void sh73180se_outl(unsigned int value, unsigned long port); - -extern unsigned char sh73180se_inb_p(unsigned long port); -extern void sh73180se_outb_p(unsigned char value, unsigned long port); - -extern void sh73180se_insb(unsigned long port, void *addr, unsigned long count); -extern void sh73180se_insw(unsigned long port, void *addr, unsigned long count); -extern void sh73180se_insl(unsigned long port, void *addr, unsigned long count); -extern void sh73180se_outsb(unsigned long port, const void *addr, unsigned long count); -extern void sh73180se_outsw(unsigned long port, const void *addr, unsigned long count); -extern void sh73180se_outsl(unsigned long port, const void *addr, unsigned long count); - -#endif /* _ASM_SH_IO_73180SE_H */ diff --git a/include/asm-sh/se73180/se73180.h b/include/asm-sh/se73180/se73180.h deleted file mode 100644 index f5b93e39e768..000000000000 --- a/include/asm-sh/se73180/se73180.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef __ASM_SH_HITACHI_SE73180_H -#define __ASM_SH_HITACHI_SE73180_H - -/* - * include/asm-sh/se/se73180.h - * - * Copyright (C) 2003 Takashi Kusuda - * - * SH-Mobile SolutionEngine 73180 support - */ - -/* Box specific addresses. */ - -/* Area 0 */ -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte(Actually 2MB) */ -#define PA_FROM 0x00400000 /* Flash ROM */ -#define PA_FROM_SIZE 0x00400000 /* Flash size 4M byte */ -#define PA_SRAM 0x00800000 /* SRAM */ -#define PA_FROM_SIZE 0x00400000 /* SRAM size 4M byte */ -/* Area 1 */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -/* Area 2 */ -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -/* Area 3 */ -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 -/* Area 4 */ -#define PA_PCIC 0x10000000 /* MR-SHPC-01 PCMCIA */ -#define PA_MRSHPC 0xb03fffe0 /* MR-SHPC-01 PCMCIA controller */ -#define PA_MRSHPC_MW1 0xb0400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb0500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb0600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) -#define PA_LED 0xb0C00000 /* LED */ -#define LED_SHIFT 0 -#define PA_DIPSW 0xb0900000 /* Dip switch 31 */ -#define PA_EPLD_MODESET 0xb0a00000 /* FPGA Mode set register */ -#define PA_EPLD_ST1 0xb0a80000 /* FPGA Interrupt status register1 */ -#define PA_EPLD_ST2 0xb0ac0000 /* FPGA Interrupt status register2 */ -/* Area 5 */ -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -/* Area 6 */ -#define PA_LCD1 0xb8000000 -#define PA_LCD2 0xb8800000 - -#endif /* __ASM_SH_HITACHI_SE73180_H */ diff --git a/include/asm-sh/se7751.h b/include/asm-sh/se7751.h new file mode 100644 index 000000000000..88cd379d9084 --- /dev/null +++ b/include/asm-sh/se7751.h @@ -0,0 +1,71 @@ +#ifndef __ASM_SH_HITACHI_7751SE_H +#define __ASM_SH_HITACHI_7751SE_H + +/* + * linux/include/asm-sh/hitachi_7751se.h + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SolutionEngine support + + * Modified for 7751 Solution Engine by + * Ian da Silva and Jeremy Siegel, 2001. + */ + +/* Box specific addresses. */ + +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_FROM 0x01000000 /* EPROM */ +#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 + +#define PA_EXT4 0x12000000 +#define PA_EXT4_SIZE 0x02000000 +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ + +#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ +#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ +#define PA_LED 0xba000000 /* LED */ +#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ + +#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */ +#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_MODE (PA_MRSHPC + 4) +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) + +#define BCR_ILCRA (PA_BCR + 0) +#define BCR_ILCRB (PA_BCR + 2) +#define BCR_ILCRC (PA_BCR + 4) +#define BCR_ILCRD (PA_BCR + 6) +#define BCR_ILCRE (PA_BCR + 8) +#define BCR_ILCRF (PA_BCR + 10) +#define BCR_ILCRG (PA_BCR + 12) + +#define IRQ_79C973 13 + +#define __IO_PREFIX sh7751se +#include + +#endif /* __ASM_SH_HITACHI_7751SE_H */ diff --git a/include/asm-sh/se7751/io.h b/include/asm-sh/se7751/io.h deleted file mode 100644 index 78d8f5744bc5..000000000000 --- a/include/asm-sh/se7751/io.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * include/asm-sh/io_7751se.h - * - * Modified version of io_se.h for the 7751se-specific functions. - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * IO functions for an Hitachi SolutionEngine - */ - -#ifndef _ASM_SH_IO_7751SE_H -#define _ASM_SH_IO_7751SE_H - -extern unsigned char sh7751se_inb(unsigned long port); -extern unsigned short sh7751se_inw(unsigned long port); -extern unsigned int sh7751se_inl(unsigned long port); - -extern void sh7751se_outb(unsigned char value, unsigned long port); -extern void sh7751se_outw(unsigned short value, unsigned long port); -extern void sh7751se_outl(unsigned int value, unsigned long port); - -extern unsigned char sh7751se_inb_p(unsigned long port); -extern void sh7751se_outb_p(unsigned char value, unsigned long port); - -extern void sh7751se_insb(unsigned long port, void *addr, unsigned long count); -extern void sh7751se_insw(unsigned long port, void *addr, unsigned long count); -extern void sh7751se_insl(unsigned long port, void *addr, unsigned long count); -extern void sh7751se_outsb(unsigned long port, const void *addr, unsigned long count); -extern void sh7751se_outsw(unsigned long port, const void *addr, unsigned long count); -extern void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count); - -extern unsigned char sh7751se_readb(unsigned long addr); -extern unsigned short sh7751se_readw(unsigned long addr); -extern unsigned int sh7751se_readl(unsigned long addr); -extern void sh7751se_writeb(unsigned char b, unsigned long addr); -extern void sh7751se_writew(unsigned short b, unsigned long addr); -extern void sh7751se_writel(unsigned int b, unsigned long addr); - -extern unsigned long sh7751se_isa_port2addr(unsigned long offset); - -#endif /* _ASM_SH_IO_7751SE_H */ diff --git a/include/asm-sh/se7751/se7751.h b/include/asm-sh/se7751/se7751.h deleted file mode 100644 index 738e22bebdfb..000000000000 --- a/include/asm-sh/se7751/se7751.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef __ASM_SH_HITACHI_7751SE_H -#define __ASM_SH_HITACHI_7751SE_H - -/* - * linux/include/asm-sh/hitachi_7751se.h - * - * Copyright (C) 2000 Kazumoto Kojima - * - * Hitachi SolutionEngine support - - * Modified for 7751 Solution Engine by - * Ian da Silva and Jeremy Siegel, 2001. - */ - -/* Box specific addresses. */ - -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_FROM 0x01000000 /* EPROM */ -#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 - -#define PA_EXT4 0x12000000 -#define PA_EXT4_SIZE 0x02000000 -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ - -#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ -#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ -#define PA_LED 0xba000000 /* LED */ -#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ - -#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */ -#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_MODE (PA_MRSHPC + 4) -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) - -#define BCR_ILCRA (PA_BCR + 0) -#define BCR_ILCRB (PA_BCR + 2) -#define BCR_ILCRC (PA_BCR + 4) -#define BCR_ILCRD (PA_BCR + 6) -#define BCR_ILCRE (PA_BCR + 8) -#define BCR_ILCRF (PA_BCR + 10) -#define BCR_ILCRG (PA_BCR + 12) - -#define IRQ_79C973 13 - -#endif /* __ASM_SH_HITACHI_7751SE_H */ diff --git a/include/asm-sh/sh03/io.h b/include/asm-sh/sh03/io.h index 25792e9831ea..df3b187ef883 100644 --- a/include/asm-sh/sh03/io.h +++ b/include/asm-sh/sh03/io.h @@ -33,14 +33,6 @@ #define IRL3_IPR_POS 0 #define IRL3_PRIORITY 4 - -extern unsigned long sh03_isa_port2addr(unsigned long offset); - -extern void setup_sh03(void); -extern void init_sh03_IRQ(void); -extern void heartbeat_sh03(void); - -extern void sh03_rtc_gettimeofday(struct timeval *tv); -extern int sh03_rtc_settimeofday(const struct timeval *tv); +void heartbeat_sh03(void); #endif /* _ASM_SH_IO_SH03_H */ diff --git a/include/asm-sh/snapgear.h b/include/asm-sh/snapgear.h new file mode 100644 index 000000000000..6b5e4ddc073a --- /dev/null +++ b/include/asm-sh/snapgear.h @@ -0,0 +1,79 @@ +/* + * include/asm-sh/snapgear/io.h + * + * Modified version of io_se.h for the snapgear-specific functions. + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + * + * IO functions for a SnapGear + */ + +#ifndef _ASM_SH_IO_SNAPGEAR_H +#define _ASM_SH_IO_SNAPGEAR_H + +#if defined(CONFIG_CPU_SH4) +/* + * The external interrupt lines, these take up ints 0 - 15 inclusive + * depending on the priority for the interrupt. In fact the priority + * is the interrupt :-) + */ + +#define IRL0_IRQ 2 +#define IRL0_IPR_ADDR INTC_IPRD +#define IRL0_IPR_POS 3 +#define IRL0_PRIORITY 13 + +#define IRL1_IRQ 5 +#define IRL1_IPR_ADDR INTC_IPRD +#define IRL1_IPR_POS 2 +#define IRL1_PRIORITY 10 + +#define IRL2_IRQ 8 +#define IRL2_IPR_ADDR INTC_IPRD +#define IRL2_IPR_POS 1 +#define IRL2_PRIORITY 7 + +#define IRL3_IRQ 11 +#define IRL3_IPR_ADDR INTC_IPRD +#define IRL3_IPR_POS 0 +#define IRL3_PRIORITY 4 +#endif + +#define __IO_PREFIX snapgear +#include + +#ifdef CONFIG_SH_SECUREEDGE5410 +/* + * We need to remember what was written to the ioport as some bits + * are shared with other functions and you cannot read back what was + * written :-| + * + * Bit Read Write + * ----------------------------------------------- + * D0 DCD on ttySC1 power + * D1 Reset Switch heatbeat + * D2 ttySC0 CTS (7100) LAN + * D3 - WAN + * D4 ttySC0 DCD (7100) CONSOLE + * D5 - ONLINE + * D6 - VPN + * D7 - DTR on ttySC1 + * D8 - ttySC0 RTS (7100) + * D9 - ttySC0 DTR (7100) + * D10 - RTC SCLK + * D11 RTC DATA RTC DATA + * D12 - RTS RESET + */ + +#define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000) +extern unsigned short secureedge5410_ioport; + +#define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \ + (secureedge5410_ioport = \ + ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) +#define SECUREEDGE_READ_IOPORT() \ + ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817)) +#endif + +#endif /* _ASM_SH_IO_SNAPGEAR_H */ diff --git a/include/asm-sh/snapgear/io.h b/include/asm-sh/snapgear/io.h deleted file mode 100644 index bfa97ac06280..000000000000 --- a/include/asm-sh/snapgear/io.h +++ /dev/null @@ -1,92 +0,0 @@ -/* - * include/asm-sh/snapgear/io.h - * - * Modified version of io_se.h for the snapgear-specific functions. - * - * May be copied or modified under the terms of the GNU General Public - * License. See linux/COPYING for more information. - * - * IO functions for a SnapGear - */ - -#ifndef _ASM_SH_IO_SNAPGEAR_H -#define _ASM_SH_IO_SNAPGEAR_H - -#if defined(CONFIG_CPU_SH4) -/* - * The external interrupt lines, these take up ints 0 - 15 inclusive - * depending on the priority for the interrupt. In fact the priority - * is the interrupt :-) - */ - -#define IRL0_IRQ 2 -#define IRL0_IPR_ADDR INTC_IPRD -#define IRL0_IPR_POS 3 -#define IRL0_PRIORITY 13 - -#define IRL1_IRQ 5 -#define IRL1_IPR_ADDR INTC_IPRD -#define IRL1_IPR_POS 2 -#define IRL1_PRIORITY 10 - -#define IRL2_IRQ 8 -#define IRL2_IPR_ADDR INTC_IPRD -#define IRL2_IPR_POS 1 -#define IRL2_PRIORITY 7 - -#define IRL3_IRQ 11 -#define IRL3_IPR_ADDR INTC_IPRD -#define IRL3_IPR_POS 0 -#define IRL3_PRIORITY 4 -#endif - -extern unsigned char snapgear_inb(unsigned long port); -extern unsigned short snapgear_inw(unsigned long port); -extern unsigned int snapgear_inl(unsigned long port); - -extern void snapgear_outb(unsigned char value, unsigned long port); -extern void snapgear_outw(unsigned short value, unsigned long port); -extern void snapgear_outl(unsigned int value, unsigned long port); - -extern unsigned char snapgear_inb_p(unsigned long port); -extern void snapgear_outb_p(unsigned char value, unsigned long port); - -extern void snapgear_insl(unsigned long port, void *addr, unsigned long count); -extern void snapgear_outsl(unsigned long port, const void *addr, unsigned long count); - -extern unsigned long snapgear_isa_port2addr(unsigned long offset); - -#ifdef CONFIG_SH_SECUREEDGE5410 -/* - * We need to remember what was written to the ioport as some bits - * are shared with other functions and you cannot read back what was - * written :-| - * - * Bit Read Write - * ----------------------------------------------- - * D0 DCD on ttySC1 power - * D1 Reset Switch heatbeat - * D2 ttySC0 CTS (7100) LAN - * D3 - WAN - * D4 ttySC0 DCD (7100) CONSOLE - * D5 - ONLINE - * D6 - VPN - * D7 - DTR on ttySC1 - * D8 - ttySC0 RTS (7100) - * D9 - ttySC0 DTR (7100) - * D10 - RTC SCLK - * D11 RTC DATA RTC DATA - * D12 - RTS RESET - */ - - #define SECUREEDGE_IOPORT_ADDR ((volatile short *) 0xb0000000) - extern unsigned short secureedge5410_ioport; - - #define SECUREEDGE_WRITE_IOPORT(val, mask) (*SECUREEDGE_IOPORT_ADDR = \ - (secureedge5410_ioport = \ - ((secureedge5410_ioport & ~(mask)) | ((val) & (mask))))) - #define SECUREEDGE_READ_IOPORT() \ - ((*SECUREEDGE_IOPORT_ADDR&0x0817) | (secureedge5410_ioport&~0x0817)) -#endif - -#endif /* _ASM_SH_IO_SNAPGEAR_H */ diff --git a/include/asm-sh/systemh/7751systemh.h b/include/asm-sh/systemh/7751systemh.h deleted file mode 100644 index 4170531bdbd9..000000000000 --- a/include/asm-sh/systemh/7751systemh.h +++ /dev/null @@ -1,68 +0,0 @@ -#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H -#define __ASM_SH_SYSTEMH_7751SYSTEMH_H - -/* - * linux/include/asm-sh/systemh/7751systemh.h - * - * Copyright (C) 2000 Kazumoto Kojima - * - * Hitachi SystemH support - - * Modified for 7751 SystemH by - * Jonathan Short, 2002. - */ - -/* Box specific addresses. */ - -#define PA_ROM 0x00000000 /* EPROM */ -#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_FROM 0x01000000 /* EPROM */ -#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ -#define PA_EXT1 0x04000000 -#define PA_EXT1_SIZE 0x04000000 -#define PA_EXT2 0x08000000 -#define PA_EXT2_SIZE 0x04000000 -#define PA_SDRAM 0x0c000000 -#define PA_SDRAM_SIZE 0x04000000 - -#define PA_EXT4 0x12000000 -#define PA_EXT4_SIZE 0x02000000 -#define PA_EXT5 0x14000000 -#define PA_EXT5_SIZE 0x04000000 -#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ - -#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ -#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ -#define PA_LED 0xba000000 /* LED */ -#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ - -#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */ -#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ -#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ -#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ -#define MRSHPC_MODE (PA_MRSHPC + 4) -#define MRSHPC_OPTION (PA_MRSHPC + 6) -#define MRSHPC_CSR (PA_MRSHPC + 8) -#define MRSHPC_ISR (PA_MRSHPC + 10) -#define MRSHPC_ICR (PA_MRSHPC + 12) -#define MRSHPC_CPWCR (PA_MRSHPC + 14) -#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) -#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) -#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) -#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) -#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) -#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) -#define MRSHPC_CDCR (PA_MRSHPC + 28) -#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) - -#define BCR_ILCRA (PA_BCR + 0) -#define BCR_ILCRB (PA_BCR + 2) -#define BCR_ILCRC (PA_BCR + 4) -#define BCR_ILCRD (PA_BCR + 6) -#define BCR_ILCRE (PA_BCR + 8) -#define BCR_ILCRF (PA_BCR + 10) -#define BCR_ILCRG (PA_BCR + 12) - -#define IRQ_79C973 13 - -#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */ diff --git a/include/asm-sh/systemh/io.h b/include/asm-sh/systemh/io.h deleted file mode 100644 index 327849b49db8..000000000000 --- a/include/asm-sh/systemh/io.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * include/asm-sh/systemh/io.h - * - * Stupid I/O definitions for SystemH, cloned from SE7751. - * - * Copyright (C) 2003 Paul Mundt - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - */ -#ifndef __ASM_SH_SYSTEMH_IO_H -#define __ASM_SH_SYSTEMH_IO_H - -extern unsigned char sh7751systemh_inb(unsigned long port); -extern unsigned short sh7751systemh_inw(unsigned long port); -extern unsigned int sh7751systemh_inl(unsigned long port); - -extern void sh7751systemh_outb(unsigned char value, unsigned long port); -extern void sh7751systemh_outw(unsigned short value, unsigned long port); -extern void sh7751systemh_outl(unsigned int value, unsigned long port); - -extern unsigned char sh7751systemh_inb_p(unsigned long port); -extern void sh7751systemh_outb_p(unsigned char value, unsigned long port); - -extern void sh7751systemh_insb(unsigned long port, void *addr, unsigned long count); -extern void sh7751systemh_insw(unsigned long port, void *addr, unsigned long count); -extern void sh7751systemh_insl(unsigned long port, void *addr, unsigned long count); -extern void sh7751systemh_outsb(unsigned long port, const void *addr, unsigned long count); -extern void sh7751systemh_outsw(unsigned long port, const void *addr, unsigned long count); -extern void sh7751systemh_outsl(unsigned long port, const void *addr, unsigned long count); - -extern unsigned char sh7751systemh_readb(unsigned long addr); -extern unsigned short sh7751systemh_readw(unsigned long addr); -extern unsigned int sh7751systemh_readl(unsigned long addr); -extern void sh7751systemh_writeb(unsigned char b, unsigned long addr); -extern void sh7751systemh_writew(unsigned short b, unsigned long addr); -extern void sh7751systemh_writel(unsigned int b, unsigned long addr); - -extern unsigned long sh7751systemh_isa_port2addr(unsigned long offset); - -#endif /* __ASM_SH_SYSTEMH_IO_H */ - diff --git a/include/asm-sh/systemh7751.h b/include/asm-sh/systemh7751.h new file mode 100644 index 000000000000..b143bb2a2ca7 --- /dev/null +++ b/include/asm-sh/systemh7751.h @@ -0,0 +1,71 @@ +#ifndef __ASM_SH_SYSTEMH_7751SYSTEMH_H +#define __ASM_SH_SYSTEMH_7751SYSTEMH_H + +/* + * linux/include/asm-sh/systemh/7751systemh.h + * + * Copyright (C) 2000 Kazumoto Kojima + * + * Hitachi SystemH support + + * Modified for 7751 SystemH by + * Jonathan Short, 2002. + */ + +/* Box specific addresses. */ + +#define PA_ROM 0x00000000 /* EPROM */ +#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_FROM 0x01000000 /* EPROM */ +#define PA_FROM_SIZE 0x00400000 /* EPROM size 4M byte */ +#define PA_EXT1 0x04000000 +#define PA_EXT1_SIZE 0x04000000 +#define PA_EXT2 0x08000000 +#define PA_EXT2_SIZE 0x04000000 +#define PA_SDRAM 0x0c000000 +#define PA_SDRAM_SIZE 0x04000000 + +#define PA_EXT4 0x12000000 +#define PA_EXT4_SIZE 0x02000000 +#define PA_EXT5 0x14000000 +#define PA_EXT5_SIZE 0x04000000 +#define PA_PCIC 0x18000000 /* MR-SHPC-01 PCMCIA */ + +#define PA_DIPSW0 0xb9000000 /* Dip switch 5,6 */ +#define PA_DIPSW1 0xb9000002 /* Dip switch 7,8 */ +#define PA_LED 0xba000000 /* LED */ +#define PA_BCR 0xbb000000 /* FPGA on the MS7751SE01 */ + +#define PA_MRSHPC 0xb83fffe0 /* MR-SHPC-01 PCMCIA controler */ +#define PA_MRSHPC_MW1 0xb8400000 /* MR-SHPC-01 memory window base */ +#define PA_MRSHPC_MW2 0xb8500000 /* MR-SHPC-01 attribute window base */ +#define PA_MRSHPC_IO 0xb8600000 /* MR-SHPC-01 I/O window base */ +#define MRSHPC_MODE (PA_MRSHPC + 4) +#define MRSHPC_OPTION (PA_MRSHPC + 6) +#define MRSHPC_CSR (PA_MRSHPC + 8) +#define MRSHPC_ISR (PA_MRSHPC + 10) +#define MRSHPC_ICR (PA_MRSHPC + 12) +#define MRSHPC_CPWCR (PA_MRSHPC + 14) +#define MRSHPC_MW0CR1 (PA_MRSHPC + 16) +#define MRSHPC_MW1CR1 (PA_MRSHPC + 18) +#define MRSHPC_IOWCR1 (PA_MRSHPC + 20) +#define MRSHPC_MW0CR2 (PA_MRSHPC + 22) +#define MRSHPC_MW1CR2 (PA_MRSHPC + 24) +#define MRSHPC_IOWCR2 (PA_MRSHPC + 26) +#define MRSHPC_CDCR (PA_MRSHPC + 28) +#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30) + +#define BCR_ILCRA (PA_BCR + 0) +#define BCR_ILCRB (PA_BCR + 2) +#define BCR_ILCRC (PA_BCR + 4) +#define BCR_ILCRD (PA_BCR + 6) +#define BCR_ILCRE (PA_BCR + 8) +#define BCR_ILCRF (PA_BCR + 10) +#define BCR_ILCRG (PA_BCR + 12) + +#define IRQ_79C973 13 + +#define __IO_PREFIX sh7751systemh +#include + +#endif /* __ASM_SH_SYSTEMH_7751SYSTEMH_H */ -- cgit From 959f85f8a3223c116bbe95dd8a9b207790b5d4d3 Mon Sep 17 00:00:00 2001 From: Paul Mundt Date: Wed, 27 Sep 2006 16:43:28 +0900 Subject: sh: Consolidated SH7751/SH7780 PCI support. This cleans up quite a lot of the PCI mess that we currently have, and attempts to consolidate the duplication in the SH7780 and SH7751 PCI controllers. Signed-off-by: Paul Mundt --- arch/sh/boards/landisk/Makefile | 2 - arch/sh/boards/landisk/io.c | 100 ++++------ arch/sh/boards/mpc1211/setup.c | 15 +- arch/sh/boards/renesas/hs7751rvoip/io.c | 116 ++++-------- arch/sh/boards/renesas/r7780rp/io.c | 103 ++++------ arch/sh/boards/renesas/rts7751r2d/io.c | 89 ++++----- arch/sh/boards/renesas/systemh/io.c | 67 ++----- arch/sh/boards/se/770x/io.c | 11 +- arch/sh/boards/se/7751/io.c | 145 +++----------- arch/sh/boards/sh03/setup.c | 6 +- arch/sh/boards/snapgear/io.c | 84 +++------ arch/sh/boards/titan/io.c | 65 +++---- arch/sh/cchips/hd6446x/hd64461/io.c | 9 +- arch/sh/drivers/pci/Makefile | 5 +- arch/sh/drivers/pci/fixups-dreamcast.c | 38 +--- arch/sh/drivers/pci/fixups-r7780rp.c | 38 ++-- arch/sh/drivers/pci/fixups-rts7751r2d.c | 24 +-- arch/sh/drivers/pci/fixups-sh03.c | 38 +--- arch/sh/drivers/pci/ops-bigsur.c | 18 +- arch/sh/drivers/pci/ops-landisk.c | 68 +++++++ arch/sh/drivers/pci/ops-r7780rp.c | 18 +- arch/sh/drivers/pci/ops-rts7751r2d.c | 13 +- arch/sh/drivers/pci/ops-sh4.c | 164 ++++++++++++++++ arch/sh/drivers/pci/ops-snapgear.c | 21 +-- arch/sh/drivers/pci/ops-titan.c | 16 +- arch/sh/drivers/pci/pci-auto.c | 10 - arch/sh/drivers/pci/pci-sh4.h | 180 ++++++++++++++++++ arch/sh/drivers/pci/pci-sh7751.c | 322 ++++++-------------------------- arch/sh/drivers/pci/pci-sh7751.h | 174 +---------------- arch/sh/drivers/pci/pci-sh7780.c | 270 ++++---------------------- arch/sh/drivers/pci/pci-sh7780.h | 94 +--------- arch/sh/drivers/pci/pci-st40.c | 19 -- arch/sh/drivers/pci/pci.c | 40 +++- arch/sh/kernel/cpu/sh4/Makefile | 3 + arch/sh/kernel/cpu/sh4/setup-sh7780.c | 79 ++++++++ include/asm-sh/io.h | 5 + include/asm-sh/pci.h | 35 +++- 37 files changed, 984 insertions(+), 1520 deletions(-) create mode 100644 arch/sh/drivers/pci/ops-landisk.c create mode 100644 arch/sh/drivers/pci/ops-sh4.c create mode 100644 arch/sh/drivers/pci/pci-sh4.h create mode 100644 arch/sh/kernel/cpu/sh4/setup-sh7780.c (limited to 'arch/sh/boards/renesas/systemh/io.c') diff --git a/arch/sh/boards/landisk/Makefile b/arch/sh/boards/landisk/Makefile index 60e75c6db0eb..89e4beb2ad47 100644 --- a/arch/sh/boards/landisk/Makefile +++ b/arch/sh/boards/landisk/Makefile @@ -3,5 +3,3 @@ # obj-y := setup.o io.o irq.o rtc.o landisk_pwb.o - -obj-$(CONFIG_PCI) += pci.o diff --git a/arch/sh/boards/landisk/io.c b/arch/sh/boards/landisk/io.c index aa6b145c9e8f..92498b4947d5 100644 --- a/arch/sh/boards/landisk/io.c +++ b/arch/sh/boards/landisk/io.c @@ -14,39 +14,16 @@ * modifed by kogiidena * 2005.03.03 */ - #include #include +#include #include #include #include -#include -#include -#include "../../drivers/pci/pci-sh7751.h" - extern void *area5_io_base; /* Area 5 I/O Base address */ extern void *area6_io_base; /* Area 6 I/O Base address */ -/* - * The 7751R LANDISK uses the built-in PCI controller (PCIC) - * of the 7751R processor, and has a SuperIO accessible via the PCI. - * The board also includes a PCMCIA controller on its memory bus, - * like the other Solution Engine boards. - */ - -#define PCIIOBR (volatile long *)PCI_REG(SH7751_PCIIOBR) -#define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR) -#define PCI_IO_AREA SH7751_PCI_IO_BASE -#define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE - -#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) - -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - static inline unsigned long port2adr(unsigned int port) { if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6) @@ -67,17 +44,6 @@ static inline unsigned long port2adr(unsigned int port) return port; } -/* In case someone configures the kernel w/o PCI support: in that */ -/* scenario, don't ever bother to check for PCI-window addresses */ - -/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */ -#if defined(CONFIG_PCI) -#define CHECK_SH7751_PCIIO(port) \ - ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7751_PCI_IO_SIZE))) -#else -#define CHECK_SH_7751_PCIIO(port) (0) -#endif - /* * General outline: remap really low stuff [eventually] to SuperIO, * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO) @@ -89,8 +55,8 @@ u8 landisk_inb(unsigned long port) { if (PXSEG(port)) return ctrl_inb(port); - else if (CHECK_SH7751_PCIIO(port)) - return ctrl_inb(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + return ctrl_inb(pci_ioaddr(port)); return ctrl_inw(port2adr(port)) & 0xff; } @@ -101,12 +67,12 @@ u8 landisk_inb_p(unsigned long port) if (PXSEG(port)) v = ctrl_inb(port); - else if (CHECK_SH7751_PCIIO(port)) - v = ctrl_inb(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + v = ctrl_inb(pci_ioaddr(port)); else v = ctrl_inw(port2adr(port)) & 0xff; - delay(); + ctrl_delay(); return v; } @@ -115,8 +81,8 @@ u16 landisk_inw(unsigned long port) { if (PXSEG(port)) return ctrl_inw(port); - else if (CHECK_SH7751_PCIIO(port)) - return ctrl_inw(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + return ctrl_inw(pci_ioaddr(port)); else maybebadio(port); @@ -127,8 +93,8 @@ u32 landisk_inl(unsigned long port) { if (PXSEG(port)) return ctrl_inl(port); - else if (CHECK_SH7751_PCIIO(port)) - return ctrl_inl(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + return ctrl_inl(pci_ioaddr(port)); else maybebadio(port); @@ -139,8 +105,8 @@ void landisk_outb(u8 value, unsigned long port) { if (PXSEG(port)) ctrl_outb(value, port); - else if (CHECK_SH7751_PCIIO(port)) - ctrl_outb(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + ctrl_outb(value, pci_ioaddr(port)); else ctrl_outw(value, port2adr(port)); } @@ -149,19 +115,19 @@ void landisk_outb_p(u8 value, unsigned long port) { if (PXSEG(port)) ctrl_outb(value, port); - else if (CHECK_SH7751_PCIIO(port)) - ctrl_outb(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + ctrl_outb(value, pci_ioaddr(port)); else ctrl_outw(value, port2adr(port)); - delay(); + ctrl_delay(); } void landisk_outw(u16 value, unsigned long port) { if (PXSEG(port)) ctrl_outw(value, port); - else if (CHECK_SH7751_PCIIO(port)) - ctrl_outw(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + ctrl_outw(value, pci_ioaddr(port)); else maybebadio(port); } @@ -170,8 +136,8 @@ void landisk_outl(u32 value, unsigned long port) { if (PXSEG(port)) ctrl_outl(value, port); - else if (CHECK_SH7751_PCIIO(port)) - ctrl_outl(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + ctrl_outl(value, pci_ioaddr(port)); else maybebadio(port); } @@ -184,8 +150,8 @@ void landisk_insb(unsigned long port, void *dst, unsigned long count) if (PXSEG(port)) { while (count--) *buf++ = *(volatile u8 *)port; - } else if (CHECK_SH7751_PCIIO(port)) { - volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port); + } else if (is_pci_ioaddr(port)) { + volatile u8 *bp = (volatile u8 *)pci_ioaddr(port); while (count--) *buf++ = *bp; @@ -203,8 +169,8 @@ void landisk_insw(unsigned long port, void *dst, unsigned long count) if (PXSEG(port)) p = (volatile u16 *)port; - else if (CHECK_SH7751_PCIIO(port)) - p = (volatile u16 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + p = (volatile u16 *)pci_ioaddr(port); else p = (volatile u16 *)port2adr(port); while (count--) @@ -215,8 +181,8 @@ void landisk_insl(unsigned long port, void *dst, unsigned long count) { u32 *buf = dst; - if (CHECK_SH7751_PCIIO(port)) { - volatile u32 *p = (volatile u32 *)PCI_IOMAP(port); + if (is_pci_ioaddr(port)) { + volatile u32 *p = (volatile u32 *)pci_ioaddr(port); while (count--) *buf++ = *p; @@ -232,8 +198,8 @@ void landisk_outsb(unsigned long port, const void *src, unsigned long count) if (PXSEG(port)) while (count--) ctrl_outb(*buf++, port); - else if (CHECK_SH7751_PCIIO(port)) { - volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) { + volatile u8 *bp = (volatile u8 *)pci_ioaddr(port); while (count--) *bp = *buf++; @@ -251,8 +217,8 @@ void landisk_outsw(unsigned long port, const void *src, unsigned long count) if (PXSEG(port)) p = (volatile u16 *)port; - else if (CHECK_SH7751_PCIIO(port)) - p = (volatile u16 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + p = (volatile u16 *)pci_ioaddr(port); else p = (volatile u16 *)port2adr(port); @@ -264,8 +230,8 @@ void landisk_outsl(unsigned long port, const void *src, unsigned long count) { const u32 *buf = src; - if (CHECK_SH7751_PCIIO(port)) { - volatile u32 *p = (volatile u32 *)PCI_IOMAP(port); + if (is_pci_ioaddr(port)) { + volatile u32 *p = (volatile u32 *)pci_ioaddr(port); while (count--) *p = *buf++; @@ -277,8 +243,8 @@ void __iomem *landisk_ioport_map(unsigned long port, unsigned int size) { if (PXSEG(port)) return (void __iomem *)port; - else if (CHECK_SH7751_PCIIO(port)) - return (void __iomem *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return (void __iomem *)pci_ioaddr(port); return (void __iomem *)port2adr(port); } diff --git a/arch/sh/boards/mpc1211/setup.c b/arch/sh/boards/mpc1211/setup.c index 2bfb221cc35c..a8c5180ae219 100644 --- a/arch/sh/boards/mpc1211/setup.c +++ b/arch/sh/boards/mpc1211/setup.c @@ -255,23 +255,12 @@ void __init init_mpc1211_IRQ(void) } } -/* - Initialize the board -*/ - - -static void delay (void) -{ - volatile unsigned short tmp; - tmp = *(volatile unsigned short *) 0xa0000000; -} - -static void delay1000 (void) +static void delay1000(void) { int i; for (i=0; i<1000; i++) - delay (); + ctrl_delay(); } static int put_smb_blk(unsigned char *p, int address, int command, int no) diff --git a/arch/sh/boards/renesas/hs7751rvoip/io.c b/arch/sh/boards/renesas/hs7751rvoip/io.c index ecdce7ef6a34..8c26550ca2e4 100644 --- a/arch/sh/boards/renesas/hs7751rvoip/io.c +++ b/arch/sh/boards/renesas/hs7751rvoip/io.c @@ -13,14 +13,11 @@ #include #include +#include #include #include #include -#include -#include -#include "../../../drivers/pci/pci-sh7751.h" - extern void *area6_io8_base; /* Area 6 8bit I/O Base address */ extern void *area5_io16_base; /* Area 5 16bit I/O Base address */ @@ -31,27 +28,17 @@ extern void *area5_io16_base; /* Area 5 16bit I/O Base address */ * like the other Solution Engine boards. */ -#define PCIIOBR (volatile long *)PCI_REG(SH7751_PCIIOBR) -#define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR) -#define PCI_IO_AREA SH7751_PCI_IO_BASE -#define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE -#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) - #define CODEC_IO_BASE 0x1000 #define CODEC_IOMAP(a) ((unsigned long)area6_io8_base + ((a) - CODEC_IO_BASE)) -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - static inline unsigned long port2adr(unsigned int port) { if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6) if (port == 0x3f6) return ((unsigned long)area5_io16_base + 0x0c); else - return ((unsigned long)area5_io16_base + 0x800 + ((port-0x1f0) << 1)); + return ((unsigned long)area5_io16_base + 0x800 + + ((port-0x1f0) << 1)); else maybebadio((unsigned long)port); return port; @@ -70,25 +57,10 @@ static inline int shifted_port(unsigned long port) } #if defined(CONFIG_HS7751RVOIP_CODEC) -static inline int -codec_port(unsigned long port) -{ - if (CODEC_IO_BASE <= port && port < (CODEC_IO_BASE+0x20)) - return 1; - else - return 0; -} -#endif - -/* In case someone configures the kernel w/o PCI support: in that */ -/* scenario, don't ever bother to check for PCI-window addresses */ - -/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */ -#if defined(CONFIG_PCI) -#define CHECK_SH7751_PCIIO(port) \ - ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7751_PCI_IO_SIZE))) +#define codec_port(port) \ + ((CODEC_IO_BASE <= (port)) && ((port) < (CODEC_IO_BASE + 0x20))) #else -#define CHECK_SH7751_PCIIO(port) (0) +#define codec_port(port) (0) #endif /* @@ -102,12 +74,10 @@ unsigned char hs7751rvoip_inb(unsigned long port) { if (PXSEG(port)) return ctrl_inb(port); -#if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) return ctrl_inb(CODEC_IOMAP(port)); -#endif - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - return ctrl_inb(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + return ctrl_inb(pci_ioaddr(port)); else return ctrl_inw(port2adr(port)) & 0xff; } @@ -118,15 +88,13 @@ unsigned char hs7751rvoip_inb_p(unsigned long port) if (PXSEG(port)) v = ctrl_inb(port); -#if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) v = ctrl_inb(CODEC_IOMAP(port)); -#endif - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - v = ctrl_inb(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + v = ctrl_inb(pci_ioaddr(port)); else v = ctrl_inw(port2adr(port)) & 0xff; - delay(); + ctrl_delay(); return v; } @@ -134,8 +102,8 @@ unsigned short hs7751rvoip_inw(unsigned long port) { if (PXSEG(port)) return ctrl_inw(port); - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - return ctrl_inw(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + return ctrl_inw(pci_ioaddr(port)); else maybebadio(port); return 0; @@ -145,8 +113,8 @@ unsigned int hs7751rvoip_inl(unsigned long port) { if (PXSEG(port)) return ctrl_inl(port); - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - return ctrl_inl(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + return ctrl_inl(pci_ioaddr(port)); else maybebadio(port); return 0; @@ -157,12 +125,10 @@ void hs7751rvoip_outb(unsigned char value, unsigned long port) if (PXSEG(port)) ctrl_outb(value, port); -#if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) ctrl_outb(value, CODEC_IOMAP(port)); -#endif - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - ctrl_outb(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + ctrl_outb(value, pci_ioaddr(port)); else ctrl_outb(value, port2adr(port)); } @@ -171,24 +137,22 @@ void hs7751rvoip_outb_p(unsigned char value, unsigned long port) { if (PXSEG(port)) ctrl_outb(value, port); -#if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) ctrl_outb(value, CODEC_IOMAP(port)); -#endif - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - ctrl_outb(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + ctrl_outb(value, pci_ioaddr(port)); else ctrl_outw(value, port2adr(port)); - delay(); + ctrl_delay(); } void hs7751rvoip_outw(unsigned short value, unsigned long port) { if (PXSEG(port)) ctrl_outw(value, port); - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - ctrl_outw(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + ctrl_outw(value, pci_ioaddr(port)); else maybebadio(port); } @@ -197,8 +161,8 @@ void hs7751rvoip_outl(unsigned int value, unsigned long port) { if (PXSEG(port)) ctrl_outl(value, port); - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - ctrl_outl(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + ctrl_outl(value, pci_ioaddr(port)); else maybebadio(port); } @@ -210,13 +174,11 @@ void hs7751rvoip_insb(unsigned long port, void *addr, unsigned long count) if (PXSEG(port)) while (count--) *buf++ = ctrl_inb(port); -#if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) while (count--) *buf++ = ctrl_inb(CODEC_IOMAP(port)); -#endif - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { - volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) { + volatile u8 *bp = (volatile u8 *)pci_ioaddr(port); while (count--) *buf++ = *bp; @@ -235,8 +197,8 @@ void hs7751rvoip_insw(unsigned long port, void *addr, unsigned long count) if (PXSEG(port)) p = (volatile u16 *)port; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - p = (volatile u16 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + p = (volatile u16 *)pci_ioaddr(port); else p = (volatile u16 *)port2adr(port); while (count--) @@ -246,8 +208,8 @@ void hs7751rvoip_insw(unsigned long port, void *addr, unsigned long count) void hs7751rvoip_insl(unsigned long port, void *addr, unsigned long count) { - if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { - volatile u32 *p = (volatile u32 *)PCI_IOMAP(port); + if (is_pci_ioaddr(port) || shifted_port(port)) { + volatile u32 *p = (volatile u32 *)pci_ioaddr(port); u32 *buf = addr; while (count--) @@ -263,13 +225,11 @@ void hs7751rvoip_outsb(unsigned long port, const void *addr, unsigned long count if (PXSEG(port)) while (count--) ctrl_outb(*buf++, port); -#if defined(CONFIG_HS7751RVOIP_CODEC) else if (codec_port(port)) while (count--) ctrl_outb(*buf++, CODEC_IOMAP(port)); -#endif - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { - volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) { + volatile u8 *bp = (volatile u8 *)pci_ioaddr(port); while (count--) *bp = *buf++; @@ -288,8 +248,8 @@ void hs7751rvoip_outsw(unsigned long port, const void *addr, unsigned long count if (PXSEG(port)) p = (volatile u16 *)port; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - p = (volatile u16 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + p = (volatile u16 *)pci_ioaddr(port); else p = (volatile u16 *)port2adr(port); @@ -301,8 +261,8 @@ void hs7751rvoip_outsl(unsigned long port, const void *addr, unsigned long count { const u32 *buf = addr; - if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { - volatile u32 *p = (volatile u32 *)PCI_IOMAP(port); + if (is_pci_ioaddr(port) || shifted_port(port)) { + volatile u32 *p = (volatile u32 *)pci_ioaddr(port); while (count--) *p = *buf++; @@ -316,8 +276,8 @@ void __iomem *hs7751rvoip_ioport_map(unsigned long port, unsigned int size) return (void __iomem *)port; else if (unlikely(codec_port(port) && (size == 1))) return (void __iomem *)CODEC_IOMAP(port); - else if (CHECK_SH7751_PCIIO(port)) - return (void __iomem *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return (void __iomem *)pci_ioaddr(port); return (void __iomem *)port2adr(port); } diff --git a/arch/sh/boards/renesas/r7780rp/io.c b/arch/sh/boards/renesas/r7780rp/io.c index f73ca3f0f5a1..db92d6e6ae99 100644 --- a/arch/sh/boards/renesas/r7780rp/io.c +++ b/arch/sh/boards/renesas/r7780rp/io.c @@ -1,6 +1,4 @@ /* - * linux/arch/sh/kernel/io_r7780rp.c - * * Copyright (C) 2001 Ian da Silva, Jeremy Siegel * Based largely on io_se.c. * @@ -10,37 +8,13 @@ * placeholder code from io_r7780rp.c left in with the * expectation of later SuperIO and PCMCIA access. */ - +#include #include #include #include #include #include -#include -#include -#include "../../../drivers/pci/pci-sh7780.h" - -/* - * The 7780 R7780RP-1 uses the built-in PCI controller (PCIC) - * of the 7780 processor, and has a SuperIO accessible via the PCI. - * The board also includes a PCMCIA controller on its memory bus, - * like the other Solution Engine boards. - */ - -#define SH7780_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */ -#define PCIIOBR (volatile long *)PCI_REG(SH7780_PCIIOBR) -#define PCIMBR (volatile long *)PCI_REG(SH7780_PCIMBR) -#define PCI_IO_AREA SH7780_PCI_IO_BASE -#define PCI_MEM_AREA SH7780_PCI_CONFIG_BASE - -#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7780_PCIIOBR_MASK)) - -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - static inline unsigned long port2adr(unsigned int port) { if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6) @@ -78,17 +52,6 @@ static inline int shifted_port(unsigned long port) return 1; } -/* In case someone configures the kernel w/o PCI support: in that */ -/* scenario, don't ever bother to check for PCI-window addresses */ - -/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */ -#if defined(CONFIG_PCI) -#define CHECK_SH7780_PCIIO(port) \ - ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7780_PCI_IO_SIZE))) -#else -#define CHECK_SH7780_PCIIO(port) (0) -#endif - #if defined(CONFIG_NE2000) || defined(CONFIG_NE2000_MODULE) #define CHECK_AX88796L_PORT(port) \ ((port >= AX88796L_IO_BASE) && (port < (AX88796L_IO_BASE+0x20))) @@ -109,8 +72,8 @@ u8 r7780rp_inb(unsigned long port) return ctrl_inw(port88796l(port, 0)) & 0xff; else if (PXSEG(port)) return ctrl_inb(port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - return ctrl_inb(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + return ctrl_inb(pci_ioaddr(port)); return ctrl_inw(port2adr(port)) & 0xff; } @@ -123,12 +86,12 @@ u8 r7780rp_inb_p(unsigned long port) v = ctrl_inw(port88796l(port, 0)) & 0xff; else if (PXSEG(port)) v = ctrl_inb(port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - v = ctrl_inb(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + v = ctrl_inb(pci_ioaddr(port)); else v = ctrl_inw(port2adr(port)) & 0xff; - delay(); + ctrl_delay(); return v; } @@ -139,8 +102,8 @@ u16 r7780rp_inw(unsigned long port) maybebadio(port); else if (PXSEG(port)) return ctrl_inw(port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - return ctrl_inw(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + return ctrl_inw(pci_ioaddr(port)); else maybebadio(port); @@ -153,8 +116,8 @@ u32 r7780rp_inl(unsigned long port) maybebadio(port); else if (PXSEG(port)) return ctrl_inl(port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - return ctrl_inl(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + return ctrl_inl(pci_ioaddr(port)); else maybebadio(port); @@ -167,8 +130,8 @@ void r7780rp_outb(u8 value, unsigned long port) ctrl_outw(value, port88796l(port, 0)); else if (PXSEG(port)) ctrl_outb(value, port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - ctrl_outb(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + ctrl_outb(value, pci_ioaddr(port)); else ctrl_outw(value, port2adr(port)); } @@ -179,12 +142,12 @@ void r7780rp_outb_p(u8 value, unsigned long port) ctrl_outw(value, port88796l(port, 0)); else if (PXSEG(port)) ctrl_outb(value, port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - ctrl_outb(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + ctrl_outb(value, pci_ioaddr(port)); else ctrl_outw(value, port2adr(port)); - delay(); + ctrl_delay(); } void r7780rp_outw(u16 value, unsigned long port) @@ -193,8 +156,8 @@ void r7780rp_outw(u16 value, unsigned long port) maybebadio(port); else if (PXSEG(port)) ctrl_outw(value, port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - ctrl_outw(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + ctrl_outw(value, pci_ioaddr(port)); else maybebadio(port); } @@ -205,8 +168,8 @@ void r7780rp_outl(u32 value, unsigned long port) maybebadio(port); else if (PXSEG(port)) ctrl_outl(value, port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - ctrl_outl(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port) || shifted_port(port)) + ctrl_outl(value, pci_ioaddr(port)); else maybebadio(port); } @@ -223,8 +186,8 @@ void r7780rp_insb(unsigned long port, void *dst, unsigned long count) } else if (PXSEG(port)) { while (count--) *buf++ = *(volatile u8 *)port; - } else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) { - volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port); + } else if (is_pci_ioaddr(port) || shifted_port(port)) { + volatile u8 *bp = (volatile u8 *)pci_ioaddr(port); while (count--) *buf++ = *bp; @@ -244,8 +207,8 @@ void r7780rp_insw(unsigned long port, void *dst, unsigned long count) p = (volatile u16 *)port88796l(port, 1); else if (PXSEG(port)) p = (volatile u16 *)port; - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - p = (volatile u16 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + p = (volatile u16 *)pci_ioaddr(port); else p = (volatile u16 *)port2adr(port); @@ -259,8 +222,8 @@ void r7780rp_insl(unsigned long port, void *dst, unsigned long count) if (CHECK_AX88796L_PORT(port)) maybebadio(port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) { - volatile u32 *p = (volatile u32 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) { + volatile u32 *p = (volatile u32 *)pci_ioaddr(port); while (count--) *buf++ = *p; @@ -280,8 +243,8 @@ void r7780rp_outsb(unsigned long port, const void *src, unsigned long count) } else if (PXSEG(port)) while (count--) ctrl_outb(*buf++, port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) { - volatile u8 *bp = (volatile u8 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) { + volatile u8 *bp = (volatile u8 *)pci_ioaddr(port); while (count--) *bp = *buf++; @@ -301,8 +264,8 @@ void r7780rp_outsw(unsigned long port, const void *src, unsigned long count) p = (volatile u16 *)port88796l(port, 1); else if (PXSEG(port)) p = (volatile u16 *)port; - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - p = (volatile u16 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + p = (volatile u16 *)pci_ioaddr(port); else p = (volatile u16 *)port2adr(port); @@ -316,8 +279,8 @@ void r7780rp_outsl(unsigned long port, const void *src, unsigned long count) if (CHECK_AX88796L_PORT(port)) maybebadio(port); - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) { - volatile u32 *p = (volatile u32 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) { + volatile u32 *p = (volatile u32 *)pci_ioaddr(port); while (count--) *p = *buf++; @@ -331,8 +294,8 @@ void __iomem *r7780rp_ioport_map(unsigned long port, unsigned int size) return (void __iomem *)port88796l(port, size > 1); else if (PXSEG(port)) return (void __iomem *)port; - else if (CHECK_SH7780_PCIIO(port) || shifted_port(port)) - return (void __iomem *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + return (void __iomem *)pci_ioaddr(port); return (void __iomem *)port2adr(port); } diff --git a/arch/sh/boards/renesas/rts7751r2d/io.c b/arch/sh/boards/renesas/rts7751r2d/io.c index 8dc2a2e2e5df..135aa0b5e62d 100644 --- a/arch/sh/boards/renesas/rts7751r2d/io.c +++ b/arch/sh/boards/renesas/rts7751r2d/io.c @@ -1,6 +1,4 @@ /* - * linux/arch/sh/kernel/io_rts7751r2d.c - * * Copyright (C) 2001 Ian da Silva, Jeremy Siegel * Based largely on io_se.c. * @@ -10,11 +8,9 @@ * placeholder code from io_rts7751r2d.c left in with the * expectation of later SuperIO and PCMCIA access. */ - #include #include #include -#include "../../../drivers/pci/pci-sh7751.h" #include #include #include @@ -26,18 +22,6 @@ * like the other Solution Engine boards. */ -#define PCIIOBR (volatile long *)PCI_REG(SH7751_PCIIOBR) -#define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR) -#define PCI_IO_AREA SH7751_PCI_IO_BASE -#define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE - -#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) - -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - static inline unsigned long port2adr(unsigned int port) { if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6) @@ -75,17 +59,6 @@ static inline int shifted_port(unsigned long port) return 1; } -/* In case someone configures the kernel w/o PCI support: in that */ -/* scenario, don't ever bother to check for PCI-window addresses */ - -/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */ -#if defined(CONFIG_PCI) -#define CHECK_SH7751_PCIIO(port) \ - ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7751_PCI_IO_SIZE))) -#else -#define CHECK_SH7751_PCIIO(port) (0) -#endif - #if defined(CONFIG_NE2000) || defined(CONFIG_NE2000_MODULE) #define CHECK_AX88796L_PORT(port) \ ((port >= AX88796L_IO_BASE) && (port < (AX88796L_IO_BASE+0x20))) @@ -106,8 +79,8 @@ unsigned char rts7751r2d_inb(unsigned long port) return (*(volatile unsigned short *)port88796l(port, 0)) & 0xff; else if (PXSEG(port)) return *(volatile unsigned char *)port; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - return *(volatile unsigned char *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + return *(volatile unsigned char *)pci_ioaddr(port); else return (*(volatile unsigned short *)port2adr(port) & 0xff); } @@ -120,11 +93,12 @@ unsigned char rts7751r2d_inb_p(unsigned long port) v = (*(volatile unsigned short *)port88796l(port, 0)) & 0xff; else if (PXSEG(port)) v = *(volatile unsigned char *)port; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - v = *(volatile unsigned char *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + v = *(volatile unsigned char *)pci_ioaddr(port); else v = (*(volatile unsigned short *)port2adr(port) & 0xff); - delay(); + + ctrl_delay(); return v; } @@ -135,8 +109,8 @@ unsigned short rts7751r2d_inw(unsigned long port) maybebadio(port); else if (PXSEG(port)) return *(volatile unsigned short *)port; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - return *(volatile unsigned short *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + return *(volatile unsigned short *)pci_ioaddr(port); else maybebadio(port); @@ -149,8 +123,8 @@ unsigned int rts7751r2d_inl(unsigned long port) maybebadio(port); else if (PXSEG(port)) return *(volatile unsigned long *)port; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - return *(volatile unsigned long *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + return *(volatile unsigned long *)pci_ioaddr(port); else maybebadio(port); @@ -163,8 +137,8 @@ void rts7751r2d_outb(unsigned char value, unsigned long port) *((volatile unsigned short *)port88796l(port, 0)) = value; else if (PXSEG(port)) *(volatile unsigned char *)port = value; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - *(volatile unsigned char *)PCI_IOMAP(port) = value; + else if (is_pci_ioaddr(port) || shifted_port(port)) + *(volatile unsigned char *)pci_ioaddr(port) = value; else *(volatile unsigned short *)port2adr(port) = value; } @@ -175,11 +149,12 @@ void rts7751r2d_outb_p(unsigned char value, unsigned long port) *((volatile unsigned short *)port88796l(port, 0)) = value; else if (PXSEG(port)) *(volatile unsigned char *)port = value; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - *(volatile unsigned char *)PCI_IOMAP(port) = value; + else if (is_pci_ioaddr(port) || shifted_port(port)) + *(volatile unsigned char *)pci_ioaddr(port) = value; else *(volatile unsigned short *)port2adr(port) = value; - delay(); + + ctrl_delay(); } void rts7751r2d_outw(unsigned short value, unsigned long port) @@ -188,8 +163,8 @@ void rts7751r2d_outw(unsigned short value, unsigned long port) maybebadio(port); else if (PXSEG(port)) *(volatile unsigned short *)port = value; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - *(volatile unsigned short *)PCI_IOMAP(port) = value; + else if (is_pci_ioaddr(port) || shifted_port(port)) + *(volatile unsigned short *)pci_ioaddr(port) = value; else maybebadio(port); } @@ -200,8 +175,8 @@ void rts7751r2d_outl(unsigned int value, unsigned long port) maybebadio(port); else if (PXSEG(port)) *(volatile unsigned long *)port = value; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - *(volatile unsigned long *)PCI_IOMAP(port) = value; + else if (is_pci_ioaddr(port) || shifted_port(port)) + *(volatile unsigned long *)pci_ioaddr(port) = value; else maybebadio(port); } @@ -219,8 +194,8 @@ void rts7751r2d_insb(unsigned long port, void *addr, unsigned long count) } else if (PXSEG(port)) while (count--) ctrl_outb(ctrl_inb(port), a++); - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { - bp = (__u8 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) { + bp = (__u8 *)pci_ioaddr(port); while (count--) ctrl_outb(*bp, a++); } else { @@ -239,8 +214,8 @@ void rts7751r2d_insw(unsigned long port, void *addr, unsigned long count) p = (volatile unsigned short *)port88796l(port, 1); else if (PXSEG(port)) p = (volatile unsigned short *)port; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - p = (volatile unsigned short *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + p = (volatile unsigned short *)pci_ioaddr(port); else p = (volatile unsigned short *)port2adr(port); while (count--) @@ -251,11 +226,11 @@ void rts7751r2d_insl(unsigned long port, void *addr, unsigned long count) { if (CHECK_AX88796L_PORT(port)) maybebadio(port); - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { + else if (is_pci_ioaddr(port) || shifted_port(port)) { unsigned long a = (unsigned long)addr; while (count--) { - ctrl_outl(ctrl_inl(PCI_IOMAP(port)), a); + ctrl_outl(ctrl_inl(pci_ioaddr(port)), a); a += 4; } } else @@ -275,8 +250,8 @@ void rts7751r2d_outsb(unsigned long port, const void *addr, unsigned long count) } else if (PXSEG(port)) while (count--) ctrl_outb(a++, port); - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { - bp = (__u8 *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) { + bp = (__u8 *)pci_ioaddr(port); while (count--) *bp = ctrl_inb(a++); } else { @@ -295,8 +270,8 @@ void rts7751r2d_outsw(unsigned long port, const void *addr, unsigned long count) p = (volatile unsigned short *)port88796l(port, 1); else if (PXSEG(port)) p = (volatile unsigned short *)port; - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) - p = (volatile unsigned short *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port) || shifted_port(port)) + p = (volatile unsigned short *)pci_ioaddr(port); else p = (volatile unsigned short *)port2adr(port); @@ -310,11 +285,11 @@ void rts7751r2d_outsl(unsigned long port, const void *addr, unsigned long count) { if (CHECK_AX88796L_PORT(port)) maybebadio(port); - else if (CHECK_SH7751_PCIIO(port) || shifted_port(port)) { + else if (is_pci_ioaddr(port) || shifted_port(port)) { unsigned long a = (unsigned long)addr; while (count--) { - ctrl_outl(ctrl_inl(a), PCI_IOMAP(port)); + ctrl_outl(ctrl_inl(a), pci_ioaddr(port)); a += 4; } } else diff --git a/arch/sh/boards/renesas/systemh/io.c b/arch/sh/boards/renesas/systemh/io.c index 0befd4f9894c..cde6e5d192c4 100644 --- a/arch/sh/boards/renesas/systemh/io.c +++ b/arch/sh/boards/renesas/systemh/io.c @@ -5,36 +5,16 @@ * Based largely on io_se.c. * * I/O routine for Hitachi 7751 Systemh. - * */ - #include #include #include #include #include #include -#include "../../../drivers/pci/pci-sh7751.h" - -/* - * The 7751 SystemH Engine uses the built-in PCI controller (PCIC) - * of the 7751 processor, and has a SuperIO accessible on its memory - * bus. - */ - -#define PCIIOBR (volatile long *)PCI_REG(SH7751_PCIIOBR) -#define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR) -#define PCI_IO_AREA SH7751_PCI_IO_BASE -#define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE -#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) #define ETHER_IOMAP(adr) (0xB3000000 + (adr)) /*map to 16bits access area of smc lan chip*/ -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - static inline volatile __u16 * port2adr(unsigned int port) { @@ -44,17 +24,6 @@ port2adr(unsigned int port) return (volatile __u16*)port; } -/* In case someone configures the kernel w/o PCI support: in that */ -/* scenario, don't ever bother to check for PCI-window addresses */ - -/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */ -#if defined(CONFIG_PCI) -#define CHECK_SH7751_PCIIO(port) \ - ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7751_PCI_IO_SIZE))) -#else -#define CHECK_SH7751_PCIIO(port) (0) -#endif - /* * General outline: remap really low stuff [eventually] to SuperIO, * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO) @@ -66,8 +35,8 @@ unsigned char sh7751systemh_inb(unsigned long port) { if (PXSEG(port)) return *(volatile unsigned char *)port; - else if (CHECK_SH7751_PCIIO(port)) - return *(volatile unsigned char *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return *(volatile unsigned char *)pci_ioaddr(port); else if (port <= 0x3F1) return *(volatile unsigned char *)ETHER_IOMAP(port); else @@ -80,13 +49,13 @@ unsigned char sh7751systemh_inb_p(unsigned long port) if (PXSEG(port)) v = *(volatile unsigned char *)port; - else if (CHECK_SH7751_PCIIO(port)) - v = *(volatile unsigned char *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + v = *(volatile unsigned char *)pci_ioaddr(port); else if (port <= 0x3F1) v = *(volatile unsigned char *)ETHER_IOMAP(port); else v = (*port2adr(port))&0xff; - delay(); + ctrl_delay(); return v; } @@ -94,8 +63,8 @@ unsigned short sh7751systemh_inw(unsigned long port) { if (PXSEG(port)) return *(volatile unsigned short *)port; - else if (CHECK_SH7751_PCIIO(port)) - return *(volatile unsigned short *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return *(volatile unsigned short *)pci_ioaddr(port); else if (port >= 0x2000) return *port2adr(port); else if (port <= 0x3F1) @@ -109,8 +78,8 @@ unsigned int sh7751systemh_inl(unsigned long port) { if (PXSEG(port)) return *(volatile unsigned long *)port; - else if (CHECK_SH7751_PCIIO(port)) - return *(volatile unsigned int *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return *(volatile unsigned int *)pci_ioaddr(port); else if (port >= 0x2000) return *port2adr(port); else if (port <= 0x3F1) @@ -125,8 +94,8 @@ void sh7751systemh_outb(unsigned char value, unsigned long port) if (PXSEG(port)) *(volatile unsigned char *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned char*)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned char*)pci_ioaddr(port)) = value; else if (port <= 0x3F1) *(volatile unsigned char *)ETHER_IOMAP(port) = value; else @@ -137,21 +106,21 @@ void sh7751systemh_outb_p(unsigned char value, unsigned long port) { if (PXSEG(port)) *(volatile unsigned char *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned char*)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned char*)pci_ioaddr(port)) = value; else if (port <= 0x3F1) *(volatile unsigned char *)ETHER_IOMAP(port) = value; else *(port2adr(port)) = value; - delay(); + ctrl_delay(); } void sh7751systemh_outw(unsigned short value, unsigned long port) { if (PXSEG(port)) *(volatile unsigned short *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned short *)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned short *)pci_ioaddr(port)) = value; else if (port >= 0x2000) *port2adr(port) = value; else if (port <= 0x3F1) @@ -164,8 +133,8 @@ void sh7751systemh_outl(unsigned int value, unsigned long port) { if (PXSEG(port)) *(volatile unsigned long *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned long*)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned long*)pci_ioaddr(port)) = value; else maybebadio(port); } diff --git a/arch/sh/boards/se/770x/io.c b/arch/sh/boards/se/770x/io.c index 5102201c97ab..9941949331ab 100644 --- a/arch/sh/boards/se/770x/io.c +++ b/arch/sh/boards/se/770x/io.c @@ -1,4 +1,4 @@ -/* $Id: io.c,v 1.6 2006/01/04 17:53:54 lethal Exp $ +/* $Id: io.c,v 1.7 2006/02/05 21:55:29 lethal Exp $ * * linux/arch/sh/kernel/io_se.c * @@ -20,11 +20,6 @@ int sh_pcic_io_stop; int sh_pcic_io_type; int sh_pcic_io_dummy; -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - /* MS7750 requires special versions of in*, out* routines, since PC-like io ports are located at upper half byte of 16-bit word which can be accessed only with 16-bit wide. */ @@ -72,7 +67,7 @@ unsigned char se_inb_p(unsigned long port) v = (*port2adr(port) >> 8); else v = (*port2adr(port))&0xff; - delay(); + ctrl_delay(); return v; } @@ -110,7 +105,7 @@ void se_outb_p(unsigned char value, unsigned long port) *(port2adr(port)) = value << 8; else *(port2adr(port)) = value; - delay(); + ctrl_delay(); } void se_outw(unsigned short value, unsigned long port) diff --git a/arch/sh/boards/se/7751/io.c b/arch/sh/boards/se/7751/io.c index 0e8a3ba48316..e8d846cec89d 100644 --- a/arch/sh/boards/se/7751/io.c +++ b/arch/sh/boards/se/7751/io.c @@ -1,6 +1,4 @@ /* - * linux/arch/sh/kernel/io_7751se.c - * * Copyright (C) 2001 Ian da Silva, Jeremy Siegel * Based largely on io_se.c. * @@ -10,55 +8,14 @@ * placeholder code from io_se.c left in with the * expectation of later SuperIO and PCMCIA access. */ - #include #include +#include #include #include #include -#include -#include "../../../drivers/pci/pci-sh7751.h" - -#if 0 -/****************************************************************** - * Variables from io_se.c, related to PCMCIA (not PCI); we're not - * compiling them in, and have removed references from functions - * which follow. [Many checked for IO ports in the range bounded - * by sh_pcic_io_start/stop, and used sh_pcic_io_wbase as offset. - * As start/stop are uninitialized, only port 0x0 would match?] - * When used, remember to adjust names to avoid clash with io_se? - *****************************************************************/ -/* SH pcmcia io window base, start and end. */ -int sh_pcic_io_wbase = 0xb8400000; -int sh_pcic_io_start; -int sh_pcic_io_stop; -int sh_pcic_io_type; -int sh_pcic_io_dummy; -/*************************************************************/ -#endif - -/* - * The 7751 Solution Engine uses the built-in PCI controller (PCIC) - * of the 7751 processor, and has a SuperIO accessible via the PCI. - * The board also includes a PCMCIA controller on its memory bus, - * like the other Solution Engine boards. - */ - -#define PCIIOBR (volatile long *)PCI_REG(SH7751_PCIIOBR) -#define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR) -#define PCI_IO_AREA SH7751_PCI_IO_BASE -#define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE - -#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) - -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - -static inline volatile __u16 * -port2adr(unsigned int port) +static inline volatile u16 *port2adr(unsigned int port) { if (port >= 0x2000) return (volatile __u16 *) (PA_MRSHPC + (port - 0x2000)); @@ -66,32 +23,6 @@ port2adr(unsigned int port) return (volatile __u16*)port; } -#if 0 -/* The 7751 Solution Engine seems to have everything hooked */ -/* up pretty normally (nothing on high-bytes only...) so this */ -/* shouldn't be needed */ -static inline int -shifted_port(unsigned long port) -{ - /* For IDE registers, value is not shifted */ - if ((0x1f0 <= port && port < 0x1f8) || port == 0x3f6) - return 0; - else - return 1; -} -#endif - -/* In case someone configures the kernel w/o PCI support: in that */ -/* scenario, don't ever bother to check for PCI-window addresses */ - -/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */ -#if defined(CONFIG_PCI) -#define CHECK_SH7751_PCIIO(port) \ - ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7751_PCI_IO_SIZE))) -#else -#define CHECK_SH7751_PCIIO(port) (0) -#endif - /* * General outline: remap really low stuff [eventually] to SuperIO, * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO) @@ -103,10 +34,10 @@ unsigned char sh7751se_inb(unsigned long port) { if (PXSEG(port)) return *(volatile unsigned char *)port; - else if (CHECK_SH7751_PCIIO(port)) - return *(volatile unsigned char *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return *(volatile unsigned char *)pci_ioaddr(port); else - return (*port2adr(port))&0xff; + return (*port2adr(port)) & 0xff; } unsigned char sh7751se_inb_p(unsigned long port) @@ -115,11 +46,11 @@ unsigned char sh7751se_inb_p(unsigned long port) if (PXSEG(port)) v = *(volatile unsigned char *)port; - else if (CHECK_SH7751_PCIIO(port)) - v = *(volatile unsigned char *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + v = *(volatile unsigned char *)pci_ioaddr(port); else - v = (*port2adr(port))&0xff; - delay(); + v = (*port2adr(port)) & 0xff; + ctrl_delay(); return v; } @@ -127,8 +58,8 @@ unsigned short sh7751se_inw(unsigned long port) { if (PXSEG(port)) return *(volatile unsigned short *)port; - else if (CHECK_SH7751_PCIIO(port)) - return *(volatile unsigned short *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return *(volatile unsigned short *)pci_ioaddr(port); else if (port >= 0x2000) return *port2adr(port); else @@ -140,8 +71,8 @@ unsigned int sh7751se_inl(unsigned long port) { if (PXSEG(port)) return *(volatile unsigned long *)port; - else if (CHECK_SH7751_PCIIO(port)) - return *(volatile unsigned int *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return *(volatile unsigned int *)pci_ioaddr(port); else if (port >= 0x2000) return *port2adr(port); else @@ -154,8 +85,8 @@ void sh7751se_outb(unsigned char value, unsigned long port) if (PXSEG(port)) *(volatile unsigned char *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned char*)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned char*)pci_ioaddr(port)) = value; else *(port2adr(port)) = value; } @@ -164,19 +95,19 @@ void sh7751se_outb_p(unsigned char value, unsigned long port) { if (PXSEG(port)) *(volatile unsigned char *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned char*)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned char*)pci_ioaddr(port)) = value; else *(port2adr(port)) = value; - delay(); + ctrl_delay(); } void sh7751se_outw(unsigned short value, unsigned long port) { if (PXSEG(port)) *(volatile unsigned short *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned short *)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned short *)pci_ioaddr(port)) = value; else if (port >= 0x2000) *port2adr(port) = value; else @@ -187,8 +118,8 @@ void sh7751se_outl(unsigned int value, unsigned long port) { if (PXSEG(port)) *(volatile unsigned long *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned long*)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned long*)pci_ioaddr(port)) = value; else maybebadio(port); } @@ -202,35 +133,3 @@ void sh7751se_outsl(unsigned long port, const void *addr, unsigned long count) { maybebadio(port); } - -/* Map ISA bus address to the real address. Only for PCMCIA. */ - -/* ISA page descriptor. */ -static __u32 sh_isa_memmap[256]; - -#if 0 -static int -sh_isa_mmap(__u32 start, __u32 length, __u32 offset) -{ - int idx; - - if (start >= 0x100000 || (start & 0xfff) || (length != 0x1000)) - return -1; - - idx = start >> 12; - sh_isa_memmap[idx] = 0xb8000000 + (offset &~ 0xfff); - printk("sh_isa_mmap: start %x len %x offset %x (idx %x paddr %x)\n", - start, length, offset, idx, sh_isa_memmap[idx]); - return 0; -} -#endif - -unsigned long -sh7751se_isa_port2addr(unsigned long offset) -{ - int idx; - - idx = (offset >> 12) & 0xff; - offset &= 0xfff; - return sh_isa_memmap[idx] + offset; -} diff --git a/arch/sh/boards/sh03/setup.c b/arch/sh/boards/sh03/setup.c index dab742a00c6f..7d31d6aed8a5 100644 --- a/arch/sh/boards/sh03/setup.c +++ b/arch/sh/boards/sh03/setup.c @@ -12,11 +12,10 @@ #include #include #include -#include "../../drivers/pci/pci-sh7751.h" const char *get_system_type(void) { - return "Interface CTP/PCI-SH03)"; + return "Interface (CTP/PCI-SH03)"; } static void init_sh03_IRQ(void) @@ -39,7 +38,7 @@ static void __iomem *sh03_ioport_map(unsigned long port, unsigned int size) if (((port >= 0x1f0) && (port <= 0x1f7)) || (port == 0x3f6)) return (void __iomem *)((unsigned long)cf_io_base + port); - return (void __iomem *)(port + SH7751_PCI_IO_BASE); + return (void __iomem *)(port + PCI_IO_BASE); } struct sh_machine_vector mv_sh03 __initmv = { @@ -51,7 +50,6 @@ struct sh_machine_vector mv_sh03 __initmv = { .mv_heartbeat = heartbeat_sh03, #endif }; - ALIAS_MV(sh03) /* arch/sh/boards/sh03/rtc.c */ diff --git a/arch/sh/boards/snapgear/io.c b/arch/sh/boards/snapgear/io.c index 9f700b8392bb..0f4824264557 100644 --- a/arch/sh/boards/snapgear/io.c +++ b/arch/sh/boards/snapgear/io.c @@ -1,6 +1,4 @@ -/* - * linux/arch/sh/kernel/io_7751se.c - * +/* * Copyright (C) 2002 David McCullough * Copyright (C) 2001 Ian da Silva, Jeremy Siegel * Based largely on io_se.c. @@ -11,54 +9,22 @@ * placeholder code from io_se.c left in with the * expectation of later SuperIO and PCMCIA access. */ - #include #include #include #include #include -#include -#include "../../drivers/pci/pci-sh7751.h" - #ifdef CONFIG_SH_SECUREEDGE5410 unsigned short secureedge5410_ioport; #endif -/* - * The SnapGear uses the built-in PCI controller (PCIC) - * of the 7751 processor - */ - -#define PCIIOBR (volatile long *)PCI_REG(SH7751_PCIIOBR) -#define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR) -#define PCI_IO_AREA SH7751_PCI_IO_BASE -#define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE - -#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) - -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - static inline volatile __u16 *port2adr(unsigned int port) { maybebadio((unsigned long)port); return (volatile __u16*)port; } -/* In case someone configures the kernel w/o PCI support: in that */ -/* scenario, don't ever bother to check for PCI-window addresses */ - -/* NOTE: WINDOW CHECK MAY BE A BIT OFF, HIGH PCIBIOS_MIN_IO WRAPS? */ -#if defined(CONFIG_PCI) -#define CHECK_SH7751_PCIIO(port) \ - ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7751_PCI_IO_SIZE))) -#else -#define CHECK_SH7751_PCIIO(port) (0) -#endif - /* * General outline: remap really low stuff [eventually] to SuperIO, * stuff in PCI IO space (at or above window at pci.h:PCIBIOS_MIN_IO) @@ -66,39 +32,36 @@ static inline volatile __u16 *port2adr(unsigned int port) * should be way beyond the window, and is used w/o translation for * compatibility. */ - unsigned char snapgear_inb(unsigned long port) { if (PXSEG(port)) return *(volatile unsigned char *)port; - else if (CHECK_SH7751_PCIIO(port)) - return *(volatile unsigned char *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return *(volatile unsigned char *)pci_ioaddr(port); else - return (*port2adr(port))&0xff; + return (*port2adr(port)) & 0xff; } - unsigned char snapgear_inb_p(unsigned long port) { unsigned char v; if (PXSEG(port)) v = *(volatile unsigned char *)port; - else if (CHECK_SH7751_PCIIO(port)) - v = *(volatile unsigned char *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + v = *(volatile unsigned char *)pci_ioaddr(port); else - v = (*port2adr(port))&0xff; - delay(); + v = (*port2adr(port))&0xff; + ctrl_delay(); return v; } - unsigned short snapgear_inw(unsigned long port) { if (PXSEG(port)) return *(volatile unsigned short *)port; - else if (CHECK_SH7751_PCIIO(port)) - return *(volatile unsigned short *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return *(volatile unsigned short *)pci_ioaddr(port); else if (port >= 0x2000) return *port2adr(port); else @@ -106,13 +69,12 @@ unsigned short snapgear_inw(unsigned long port) return 0; } - unsigned int snapgear_inl(unsigned long port) { if (PXSEG(port)) return *(volatile unsigned long *)port; - else if (CHECK_SH7751_PCIIO(port)) - return *(volatile unsigned int *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return *(volatile unsigned int *)pci_ioaddr(port); else if (port >= 0x2000) return *port2adr(port); else @@ -120,50 +82,46 @@ unsigned int snapgear_inl(unsigned long port) return 0; } - void snapgear_outb(unsigned char value, unsigned long port) { if (PXSEG(port)) *(volatile unsigned char *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned char*)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned char*)pci_ioaddr(port)) = value; else *(port2adr(port)) = value; } - void snapgear_outb_p(unsigned char value, unsigned long port) { if (PXSEG(port)) *(volatile unsigned char *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned char*)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned char*)pci_ioaddr(port)) = value; else *(port2adr(port)) = value; - delay(); + ctrl_delay(); } - void snapgear_outw(unsigned short value, unsigned long port) { if (PXSEG(port)) *(volatile unsigned short *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned short *)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned short *)pci_ioaddr(port)) = value; else if (port >= 0x2000) *port2adr(port) = value; else maybebadio(port); } - void snapgear_outl(unsigned int value, unsigned long port) { if (PXSEG(port)) *(volatile unsigned long *)port = value; - else if (CHECK_SH7751_PCIIO(port)) - *((unsigned long*)PCI_IOMAP(port)) = value; + else if (is_pci_ioaddr(port)) + *((unsigned long*)pci_ioaddr(port)) = value; else maybebadio(port); } diff --git a/arch/sh/boards/titan/io.c b/arch/sh/boards/titan/io.c index 48f3494f55b1..4730c1dd697d 100644 --- a/arch/sh/boards/titan/io.c +++ b/arch/sh/boards/titan/io.c @@ -1,34 +1,11 @@ /* * I/O routines for Titan */ - #include #include #include #include #include -#include "../../drivers/pci/pci-sh7751.h" - -#define PCIIOBR (volatile long *)PCI_REG(SH7751_PCIIOBR) -#define PCIMBR (volatile long *)PCI_REG(SH7751_PCIMBR) -#define PCI_IO_AREA SH7751_PCI_IO_BASE -#define PCI_MEM_AREA SH7751_PCI_CONFIG_BASE - -#define PCI_IOMAP(adr) (PCI_IO_AREA + (adr & ~SH7751_PCIIOBR_MASK)) - -#if defined(CONFIG_PCI) -#define CHECK_SH7751_PCIIO(port) \ - ((port >= PCIBIOS_MIN_IO) && (port < (PCIBIOS_MIN_IO + SH7751_PCI_IO_SIZE))) -#define CHECK_SH7751_PCIMEMIO(port) \ - ((port >= PCIBIOS_MIN_MEM) && (port < (PCIBIOS_MIN_MEM + SH7751_PCI_MEM_SIZE))) -#else -#define CHECK_SH7751_PCIIO(port) (0) -#endif - -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} static inline unsigned int port2adr(unsigned int port) { @@ -40,8 +17,8 @@ u8 titan_inb(unsigned long port) { if (PXSEG(port)) return ctrl_inb(port); - else if (CHECK_SH7751_PCIIO(port)) - return ctrl_inb(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + return ctrl_inb(pci_ioaddr(port)); return ctrl_inw(port2adr(port)) & 0xff; } @@ -51,11 +28,11 @@ u8 titan_inb_p(unsigned long port) if (PXSEG(port)) v = ctrl_inb(port); - else if (CHECK_SH7751_PCIIO(port)) - v = ctrl_inb(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + v = ctrl_inb(pci_ioaddr(port)); else v = ctrl_inw(port2adr(port)) & 0xff; - delay(); + ctrl_delay(); return v; } @@ -63,8 +40,8 @@ u16 titan_inw(unsigned long port) { if (PXSEG(port)) return ctrl_inw(port); - else if (CHECK_SH7751_PCIIO(port)) - return ctrl_inw(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + return ctrl_inw(pci_ioaddr(port)); else if (port >= 0x2000) return ctrl_inw(port2adr(port)); else @@ -76,8 +53,8 @@ u32 titan_inl(unsigned long port) { if (PXSEG(port)) return ctrl_inl(port); - else if (CHECK_SH7751_PCIIO(port)) - return ctrl_inl(PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + return ctrl_inl(pci_ioaddr(port)); else if (port >= 0x2000) return ctrl_inw(port2adr(port)); else @@ -89,8 +66,8 @@ void titan_outb(u8 value, unsigned long port) { if (PXSEG(port)) ctrl_outb(value, port); - else if (CHECK_SH7751_PCIIO(port)) - ctrl_outb(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + ctrl_outb(value, pci_ioaddr(port)); else ctrl_outw(value, port2adr(port)); } @@ -99,19 +76,19 @@ void titan_outb_p(u8 value, unsigned long port) { if (PXSEG(port)) ctrl_outb(value, port); - else if (CHECK_SH7751_PCIIO(port)) - ctrl_outb(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + ctrl_outb(value, pci_ioaddr(port)); else ctrl_outw(value, port2adr(port)); - delay(); + ctrl_delay(); } void titan_outw(u16 value, unsigned long port) { if (PXSEG(port)) ctrl_outw(value, port); - else if (CHECK_SH7751_PCIIO(port)) - ctrl_outw(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + ctrl_outw(value, pci_ioaddr(port)); else if (port >= 0x2000) ctrl_outw(value, port2adr(port)); else @@ -122,8 +99,8 @@ void titan_outl(u32 value, unsigned long port) { if (PXSEG(port)) ctrl_outl(value, port); - else if (CHECK_SH7751_PCIIO(port)) - ctrl_outl(value, PCI_IOMAP(port)); + else if (is_pci_ioaddr(port)) + ctrl_outl(value, pci_ioaddr(port)); else maybebadio(port); } @@ -140,10 +117,10 @@ void titan_outsl(unsigned long port, const void *src, unsigned long count) void __iomem *titan_ioport_map(unsigned long port, unsigned int size) { - if (PXSEG(port) || CHECK_SH7751_PCIMEMIO(port)) + if (PXSEG(port) || is_pci_memaddr(port)) return (void __iomem *)port; - else if (CHECK_SH7751_PCIIO(port)) - return (void __iomem *)PCI_IOMAP(port); + else if (is_pci_ioaddr(port)) + return (void __iomem *)pci_ioaddr(port); return (void __iomem *)port2adr(port); } diff --git a/arch/sh/cchips/hd6446x/hd64461/io.c b/arch/sh/cchips/hd6446x/hd64461/io.c index f77f18f2ba7f..7909a1b7b512 100644 --- a/arch/sh/cchips/hd6446x/hd64461/io.c +++ b/arch/sh/cchips/hd6446x/hd64461/io.c @@ -53,11 +53,6 @@ static __inline__ unsigned long PORT2ADDR(unsigned long port) return 0xa0000000 + (port & 0x1fffffff); } -static inline void delay(void) -{ - ctrl_inw(0xa0000000); -} - unsigned char hd64461_inb(unsigned long port) { return *(volatile unsigned char*)PORT2ADDR(port); @@ -66,7 +61,7 @@ unsigned char hd64461_inb(unsigned long port) unsigned char hd64461_inb_p(unsigned long port) { unsigned long v = *(volatile unsigned char*)PORT2ADDR(port); - delay(); + ctrl_delay(); return v; } @@ -88,7 +83,7 @@ void hd64461_outb(unsigned char b, unsigned long port) void hd64461_outb_p(unsigned char b, unsigned long port) { *(volatile unsigned char*)PORT2ADDR(port) = b; - delay(); + ctrl_delay(); } void hd64461_outw(unsigned short b, unsigned long port) diff --git a/arch/sh/drivers/pci/Makefile b/arch/sh/drivers/pci/Makefile index 3d8078f1c05f..9e00cb8a39e9 100644 --- a/arch/sh/drivers/pci/Makefile +++ b/arch/sh/drivers/pci/Makefile @@ -6,8 +6,8 @@ obj-y += pci.o obj-$(CONFIG_PCI_AUTO) += pci-auto.o obj-$(CONFIG_CPU_SUBTYPE_ST40STB1) += pci-st40.o -obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o -obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o +obj-$(CONFIG_CPU_SUBTYPE_SH7751) += pci-sh7751.o ops-sh4.o +obj-$(CONFIG_CPU_SUBTYPE_SH7780) += pci-sh7780.o ops-sh4.o obj-$(CONFIG_SH_DREAMCAST) += ops-dreamcast.o fixups-dreamcast.o \ dma-dreamcast.o @@ -17,3 +17,4 @@ obj-$(CONFIG_SH_RTS7751R2D) += ops-rts7751r2d.o fixups-rts7751r2d.o obj-$(CONFIG_SH_SH03) += ops-sh03.o fixups-sh03.o obj-$(CONFIG_SH_R7780RP) += ops-r7780rp.o fixups-r7780rp.o obj-$(CONFIG_SH_TITAN) += ops-titan.o +obj-$(CONFIG_SH_LANDISK) += ops-landisk.o diff --git a/arch/sh/drivers/pci/fixups-dreamcast.c b/arch/sh/drivers/pci/fixups-dreamcast.c index 63b1c6f4b8d2..c0af5f7ef414 100644 --- a/arch/sh/drivers/pci/fixups-dreamcast.c +++ b/arch/sh/drivers/pci/fixups-dreamcast.c @@ -4,7 +4,7 @@ * PCI fixups for the Sega Dreamcast * * Copyright (C) 2001, 2002 M. R. Brown - * Copyright (C) 2002, 2003 Paul Mundt + * Copyright (C) 2002, 2003, 2006 Paul Mundt * * This file originally bore the message (with enclosed-$): * Id: pci.c,v 1.3 2003/05/04 19:29:46 lethal Exp @@ -45,36 +45,16 @@ static void __init gapspci_fixup_resources(struct pci_dev *dev) printk("PCI: Failed resource fixup\n"); } } - DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, gapspci_fixup_resources); -void __init pcibios_fixup_bus(struct pci_bus *bus) +int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin) { - /* - * We don't have any sub bus to fix up, and this is a rather - * stupid place to put general device fixups. Don't do it. - * Use the pcibios_fixups table or suffer the consequences. + /* + * The interrupt routing semantics here are quite trivial. + * + * We basically only support one interrupt, so we only bother + * updating a device's interrupt line with this single shared + * interrupt. Keeps routing quite simple, doesn't it? */ + return GAPSPCI_IRQ; } - -void __init pcibios_fixup_irqs(void) -{ - struct pci_dev *dev = 0; - - for_each_pci_dev(dev) { - /* - * The interrupt routing semantics here are quite trivial. - * - * We basically only support one interrupt, so we only bother - * updating a device's interrupt line with this single shared - * interrupt. Keeps routing quite simple, doesn't it? - */ - printk(KERN_NOTICE "PCI: Fixing up IRQ routing for device %s\n", - pci_name(dev)); - - dev->irq = GAPSPCI_IRQ; - - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); - } -} - diff --git a/arch/sh/drivers/pci/fixups-r7780rp.c b/arch/sh/drivers/pci/fixups-r7780rp.c index b656b562ec99..3e321df65d22 100644 --- a/arch/sh/drivers/pci/fixups-r7780rp.c +++ b/arch/sh/drivers/pci/fixups-r7780rp.c @@ -4,36 +4,42 @@ * Highlander R7780RP-1 PCI fixups * * Copyright (C) 2003 Lineo uSolutions, Inc. - * Copyright (C) 2004 Paul Mundt + * Copyright (C) 2004 - 2006 Paul Mundt * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. */ -#include "pci-sh7780.h" +#include +#include "pci-sh4.h" #include int pci_fixup_pcic(void) { - outl(0x000043ff, PCI_REG(SH7780_PCIIMR)); - outl(0x0000380f, PCI_REG(SH7780_PCIAINTM)); + pci_write_reg(0x000043ff, SH4_PCIINTM); + pci_write_reg(0x0000380f, SH4_PCIAINTM); - outl(0xfbb00047, PCI_REG(SH7780_PCICMD)); - outl(0x00000000, PCI_REG(SH7780_PCIIBAR)); + pci_write_reg(0xfbb00047, SH7780_PCICMD); + pci_write_reg(0x00000000, SH7780_PCIIBAR); - outl(0x00011912, PCI_REG(SH7780_PCISVID)); - outl(0x08000000, PCI_REG(SH7780_PCICSCR0)); - outl(0x0000001b, PCI_REG(SH7780_PCICSAR0)); - outl(0xfd000000, PCI_REG(SH7780_PCICSCR1)); - outl(0x0000000f, PCI_REG(SH7780_PCICSAR1)); + pci_write_reg(0x00011912, SH7780_PCISVID); + pci_write_reg(0x08000000, SH7780_PCICSCR0); + pci_write_reg(0x0000001b, SH7780_PCICSAR0); + pci_write_reg(0xfd000000, SH7780_PCICSCR1); + pci_write_reg(0x0000000f, SH7780_PCICSAR1); - outl(0xfd000000, PCI_REG(SH7780_PCIMBR0)); - outl(0x00fc0000, PCI_REG(SH7780_PCIMBMR0)); + pci_write_reg(0xfd000000, SH7780_PCIMBR0); + pci_write_reg(0x00fc0000, SH7780_PCIMBMR0); + +#ifdef CONFIG_32BIT + pci_write_reg(0xc0000000, SH7780_PCIMBR2); + pci_write_reg(0x20000000 - SH7780_PCI_IO_SIZE, SH7780_PCIMBMR2); +#endif /* Set IOBR for windows containing area specified in pci.h */ - outl((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE-1)), PCI_REG(SH7780_PCIIOBR)); - outl(((SH7780_PCI_IO_SIZE-1) & (7<<18)), PCI_REG(SH7780_PCIIOBMR)); + pci_write_reg((PCIBIOS_MIN_IO & ~(SH7780_PCI_IO_SIZE - 1)), + SH7780_PCIIOBR); + pci_write_reg(((SH7780_PCI_IO_SIZE-1) & (7<<18)), SH7780_PCIIOBMR); return 0; } - diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c index 0c590fc7a081..e72ceb560d5b 100644 --- a/arch/sh/drivers/pci/fixups-rts7751r2d.c +++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c @@ -10,8 +10,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. */ -#include "pci-sh7751.h" -#include +#include "pci-sh4.h" #define PCIMCR_MRSET_OFF 0xBFFFFFFF #define PCIMCR_RFSH_OFF 0xFFFFFFFB @@ -22,22 +21,23 @@ int pci_fixup_pcic(void) bcr1 = inl(SH7751_BCR1); bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ - outl(bcr1, PCI_REG(SH7751_PCIBCR1)); + pci_write_reg(bcr1, SH4_PCIBCR1); /* Enable all interrupts, so we known what to fix */ - outl(0x0000c3ff, PCI_REG(SH7751_PCIINTM)); - outl(0x0000380f, PCI_REG(SH7751_PCIAINTM)); + pci_write_reg(0x0000c3ff, SH4_PCIINTM); + pci_write_reg(0x0000380f, SH4_PCIAINTM); - outl(0xfb900047, PCI_REG(SH7751_PCICONF1)); - outl(0xab000001, PCI_REG(SH7751_PCICONF4)); + pci_write_reg(0xfb900047, SH7751_PCICONF1); + pci_write_reg(0xab000001, SH7751_PCICONF4); mcr = inl(SH7751_MCR); mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; - outl(mcr, PCI_REG(SH7751_PCIMCR)); + pci_write_reg(mcr, SH4_PCIMCR); + + pci_write_reg(0x0c000000, SH7751_PCICONF5); + pci_write_reg(0xd0000000, SH7751_PCICONF6); + pci_write_reg(0x0c000000, SH4_PCILAR0); + pci_write_reg(0x00000000, SH4_PCILAR1); - outl(0x0c000000, PCI_REG(SH7751_PCICONF5)); - outl(0xd0000000, PCI_REG(SH7751_PCICONF6)); - outl(0x0c000000, PCI_REG(SH7751_PCILAR0)); - outl(0x00000000, PCI_REG(SH7751_PCILAR1)); return 0; } diff --git a/arch/sh/drivers/pci/fixups-sh03.c b/arch/sh/drivers/pci/fixups-sh03.c index 57ac26c2171f..2e8a18b7ee53 100644 --- a/arch/sh/drivers/pci/fixups-sh03.c +++ b/arch/sh/drivers/pci/fixups-sh03.c @@ -3,11 +3,7 @@ #include #include -/* - * IRQ functions - */ - -int __init pcibios_map_platform_irq(u8 slot, u8 pin, struct pci_dev *dev) +int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq; @@ -17,8 +13,9 @@ int __init pcibios_map_platform_irq(u8 slot, u8 pin, struct pci_dev *dev) case 8: return 5; /* eth1 */ case 6: return 2; /* PCI bridge */ default: - printk("PCI: Bad IRQ mapping request for slot %d\n", slot); - return 2; + printk(KERN_ERR "PCI: Bad IRQ mapping request " + "for slot %d\n", slot); + return 2; } } else { switch (pin) { @@ -32,30 +29,3 @@ int __init pcibios_map_platform_irq(u8 slot, u8 pin, struct pci_dev *dev) } return irq; } - -static u8 __init sh03_no_swizzle(struct pci_dev *dev, u8 *pin) -{ - /* no swizzling */ - return PCI_SLOT(dev->devfn); -} - -static int sh03_pci_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq = -1; - - /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */ - irq = pcibios_map_platform_irq(slot, pin, dev); - if( irq < 0 ) { - pr_debug("PCI: Error mapping IRQ on device %s\n", pci_name(dev)); - return irq; - } - - pr_debug("Setting IRQ for slot %s to %d\n", pci_name(dev), irq); - - return irq; -} - -void __init pcibios_fixup_irqs(void) -{ - pci_fixup_irqs(sh03_no_swizzle, sh03_pci_lookup_irq); -} diff --git a/arch/sh/drivers/pci/ops-bigsur.c b/arch/sh/drivers/pci/ops-bigsur.c index ae82c6ca05e5..5da501bd77b5 100644 --- a/arch/sh/drivers/pci/ops-bigsur.c +++ b/arch/sh/drivers/pci/ops-bigsur.c @@ -10,15 +10,12 @@ * * PCI initialization for the Hitachi Big Sur Evaluation Board */ - #include #include #include -#include #include - #include -#include "pci-sh7751.h" +#include "pci-sh4.h" #include #define BIGSUR_PCI_IO 0x4000 @@ -41,11 +38,11 @@ static struct resource sh7751_mem_resource = { extern struct pci_ops sh7751_pci_ops; struct pci_channel board_pci_channels[] = { - { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, + { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, { 0, } }; -static struct sh7751_pci_address_map sh7751_pci_map = { +static struct sh4_pci_address_map sh7751_pci_map = { .window0 = { .base = SH7751_CS3_BASE_ADDR, .size = BIGSUR_LSR0_SIZE, @@ -58,7 +55,7 @@ static struct sh7751_pci_address_map sh7751_pci_map = { }; /* - * Initialize the Big Sur PCI interface + * Initialize the Big Sur PCI interface * Setup hardware to be Central Funtion * Copy the BSR regs to the PCI interface * Setup PCI windows into local RAM @@ -68,15 +65,15 @@ int __init pcibios_init_platform(void) return sh7751_pcic_init(&sh7751_pci_map); } -int pcibios_map_platform_irq(u8 slot, u8 pin) +int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) { - /* + /* * The Big Sur can be used in a CPCI chassis, but the SH7751 PCI * interface is on the wrong end of the board so that it can also * support a V320 CPI interface chip... Therefor the IRQ mapping is * somewhat use dependent... I'l assume a linear map for now, i.e. * INTA=slot0,pin0... INTD=slot3,pin0... - */ + */ int irq = (slot + pin-1) % 4 + BIGSUR_SH7751_PCI_IRQ_BASE; PCIDBG(2, "PCI: Mapping Big Sur IRQ for slot %d, pin %c to irq %d\n", @@ -84,4 +81,3 @@ int pcibios_map_platform_irq(u8 slot, u8 pin) return irq; } - diff --git a/arch/sh/drivers/pci/ops-landisk.c b/arch/sh/drivers/pci/ops-landisk.c new file mode 100644 index 000000000000..ada301c21fe7 --- /dev/null +++ b/arch/sh/drivers/pci/ops-landisk.c @@ -0,0 +1,68 @@ +/* + * arch/sh/drivers/pci/ops-landisk.c + * + * PCI initialization for the I-O DATA Device, Inc. LANDISK board + * + * Copyright (C) 2006 kogiidena + * + * May be copied or modified under the terms of the GNU General Public + * License. See linux/COPYING for more information. + */ +#include +#include +#include +#include +#include +#include +#include "pci-sh4.h" + +static struct resource sh7751_io_resource = { + .name = "SH7751 IO", + .start = 0x4000, + .end = 0x4000 + SH7751_PCI_IO_SIZE - 1, + .flags = IORESOURCE_IO +}; + +static struct resource sh7751_mem_resource = { + .name = "SH7751 mem", + .start = SH7751_PCI_MEMORY_BASE, + .end = SH7751_PCI_MEMORY_BASE + SH7751_PCI_MEM_SIZE - 1, + .flags = IORESOURCE_MEM +}; + +struct pci_channel board_pci_channels[] = { + {&sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0x3ff}, + {NULL, NULL, NULL, 0, 0}, +}; + +static struct sh4_pci_address_map sh7751_pci_map = { + .window0 = { + .base = SH7751_CS3_BASE_ADDR, + .size = (64 << 20), /* 64MB */ + }, + + .flags = SH4_PCIC_NO_RESET, +}; + +int __init pcibios_init_platform(void) +{ + return sh7751_pcic_init(&sh7751_pci_map); +} + +int pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) +{ + /* + * slot0: pin1-4 = irq5,6,7,8 + * slot1: pin1-4 = irq6,7,8,5 + * slot2: pin1-4 = irq7,8,5,6 + * slot3: pin1-4 = irq8,5,6,7 + */ + int irq = ((slot + pin - 1) & 0x3) + 5; + + if ((slot | (pin - 1)) > 0x3) { + printk("PCI: Bad IRQ mapping request for slot %d pin %c\n", + slot, pin - 1 + 'A'); + return -1; + } + return irq; +} diff --git a/arch/sh/drivers/pci/ops-r7780rp.c b/arch/sh/drivers/pci/ops-r7780rp.c index 3254c4e917a9..554d5ed2c586 100644 --- a/arch/sh/drivers/pci/ops-r7780rp.c +++ b/arch/sh/drivers/pci/ops-r7780rp.c @@ -15,13 +15,11 @@ #include #include #include -#include - -#include -#include "pci-sh7780.h" #include +#include +#include "pci-sh4.h" -int __init pcibios_map_platform_irq(u8 slot, u8 pin) +int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) { switch (slot) { case 0: return IRQ_PCISLOT1; /* PCI Interrupt #1 */ @@ -29,7 +27,8 @@ int __init pcibios_map_platform_irq(u8 slot, u8 pin) case 2: return IRQ_PCISLOT3; /* PCI Interrupt #3 */ case 3: return IRQ_PCISLOT4; /* PCI Interrupt E4 */ default: - printk("PCI: Bad IRQ mapping request for slot %d, func %d\n", slot, pin-1); + printk(KERN_ERR "PCI: Bad IRQ mapping " + "request for slot %d, func %d\n", slot, pin-1); return -1; } } @@ -51,12 +50,12 @@ static struct resource sh7780_mem_resource = { extern struct pci_ops sh7780_pci_ops; struct pci_channel board_pci_channels[] = { - { &sh7780_pci_ops, &sh7780_io_resource, &sh7780_mem_resource, 0, 0xff }, + { &sh4_pci_ops, &sh7780_io_resource, &sh7780_mem_resource, 0, 0xff }, { NULL, NULL, NULL, 0, 0 }, }; EXPORT_SYMBOL(board_pci_channels); -static struct sh7780_pci_address_map sh7780_pci_map = { +static struct sh4_pci_address_map sh7780_pci_map = { .window0 = { .base = SH7780_CS2_BASE_ADDR, .size = 0x04000000, @@ -67,11 +66,10 @@ static struct sh7780_pci_address_map sh7780_pci_map = { .size = 0x04000000, }, - .flags = SH7780_PCIC_NO_RESET, + .flags = SH4_PCIC_NO_RESET, }; int __init pcibios_init_platform(void) { return sh7780_pcic_init(&sh7780_pci_map); } - diff --git a/arch/sh/drivers/pci/ops-rts7751r2d.c b/arch/sh/drivers/pci/ops-rts7751r2d.c index 83171d10141a..88f44e245424 100644 --- a/arch/sh/drivers/pci/ops-rts7751r2d.c +++ b/arch/sh/drivers/pci/ops-rts7751r2d.c @@ -17,12 +17,11 @@ #include #include #include - -#include -#include "pci-sh7751.h" #include +#include +#include "pci-sh4.h" -int __init pcibios_map_platform_irq(u8 slot, u8 pin) +int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) { switch (slot) { case 0: return IRQ_PCISLOT1; /* PCI Extend slot #1 */ @@ -52,12 +51,12 @@ static struct resource sh7751_mem_resource = { extern struct pci_ops sh7751_pci_ops; struct pci_channel board_pci_channels[] = { - { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, + { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, { NULL, NULL, NULL, 0, 0 }, }; EXPORT_SYMBOL(board_pci_channels); -static struct sh7751_pci_address_map sh7751_pci_map = { +static struct sh4_pci_address_map sh7751_pci_map = { .window0 = { .base = SH7751_CS3_BASE_ADDR, .size = 0x04000000, @@ -68,7 +67,7 @@ static struct sh7751_pci_address_map sh7751_pci_map = { .size = 0x00000000, /* Unused */ }, - .flags = SH7751_PCIC_NO_RESET, + .flags = SH4_PCIC_NO_RESET, }; int __init pcibios_init_platform(void) diff --git a/arch/sh/drivers/pci/ops-sh4.c b/arch/sh/drivers/pci/ops-sh4.c new file mode 100644 index 000000000000..2d4371009a5e --- /dev/null +++ b/arch/sh/drivers/pci/ops-sh4.c @@ -0,0 +1,164 @@ +/* + * Generic SH-4 / SH-4A PCIC operations (SH7751, SH7780). + * + * Copyright (C) 2002 - 2006 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License v2. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include "pci-sh4.h" + +/* + * Direct access to PCI hardware... + */ +#define CONFIG_CMD(bus, devfn, where) \ + P1SEGADDR((bus->number << 16) | (devfn << 8) | (where & ~3)) + +static DEFINE_SPINLOCK(sh4_pci_lock); + +/* + * Functions for accessing PCI configuration space with type 1 accesses + */ +static int sh4_pci_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + unsigned long flags; + u32 data; + + /* + * PCIPDR may only be accessed as 32 bit words, + * so we must do byte alignment by hand + */ + spin_lock_irqsave(&sh4_pci_lock, flags); + pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); + data = pci_read_reg(SH4_PCIPDR); + spin_unlock_irqrestore(&sh4_pci_lock, flags); + + switch (size) { + case 1: + *val = (data >> ((where & 3) << 3)) & 0xff; + break; + case 2: + *val = (data >> ((where & 2) << 3)) & 0xffff; + break; + case 4: + *val = data; + break; + default: + return PCIBIOS_FUNC_NOT_SUPPORTED; + } + + return PCIBIOS_SUCCESSFUL; +} + +/* + * Since SH4 only does 32bit access we'll have to do a read, + * mask,write operation. + * We'll allow an odd byte offset, though it should be illegal. + */ +static int sh4_pci_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + unsigned long flags; + int shift; + u32 data; + + spin_lock_irqsave(&sh4_pci_lock, flags); + pci_write_reg(CONFIG_CMD(bus, devfn, where), SH4_PCIPAR); + data = pci_read_reg(SH4_PCIPDR); + spin_unlock_irqrestore(&sh4_pci_lock, flags); + + switch (size) { + case 1: + shift = (where & 3) << 3; + data &= ~(0xff << shift); + data |= ((val & 0xff) << shift); + break; + case 2: + shift = (where & 2) << 3; + data &= ~(0xffff << shift); + data |= ((val & 0xffff) << shift); + break; + case 4: + data = val; + break; + default: + return PCIBIOS_FUNC_NOT_SUPPORTED; + } + + pci_write_reg(data, SH4_PCIPDR); + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops sh4_pci_ops = { + .read = sh4_pci_read, + .write = sh4_pci_write, +}; + +/* + * Not really related to pci_ops, but it's common and not worth shoving + * somewhere else for now.. + */ +static unsigned int pci_probe = PCI_PROBE_CONF1; + +int __init sh4_pci_check_direct(void) +{ + /* + * Check if configuration works. + */ + if (pci_probe & PCI_PROBE_CONF1) { + unsigned int tmp = pci_read_reg(SH4_PCIPAR); + + pci_write_reg(P1SEG, SH4_PCIPAR); + + if (pci_read_reg(SH4_PCIPAR) == P1SEG) { + pci_write_reg(tmp, SH4_PCIPAR); + printk(KERN_INFO "PCI: Using configuration type 1\n"); + request_region(PCI_REG(SH4_PCIPAR), 8, "PCI conf1"); + + return 0; + } + + pci_write_reg(tmp, SH4_PCIPAR); + } + + pr_debug("PCI: pci_check_direct failed\n"); + return -EINVAL; +} + +/* Handle generic fixups */ +static void __init pci_fixup_ide_bases(struct pci_dev *d) +{ + int i; + + /* + * PCI IDE controllers use non-standard I/O port decoding, respect it. + */ + if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) + return; + pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d)); + for(i = 0; i < 4; i++) { + struct resource *r = &d->resource[i]; + + if ((r->start & ~0x80) == 0x374) { + r->start |= 2; + r->end = r->start; + } + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); + +char * __init pcibios_setup(char *str) +{ + if (!strcmp(str, "off")) { + pci_probe = 0; + return NULL; + } + + return str; +} diff --git a/arch/sh/drivers/pci/ops-snapgear.c b/arch/sh/drivers/pci/ops-snapgear.c index 3cbd14dd28fe..53dd893d4e54 100644 --- a/arch/sh/drivers/pci/ops-snapgear.c +++ b/arch/sh/drivers/pci/ops-snapgear.c @@ -2,7 +2,7 @@ * arch/sh/drivers/pci/ops-snapgear.c * * Author: David McCullough - * + * * Ported to new API by Paul Mundt * * Highly leveraged from pci-bigsur.c, written by Dustin McIntire. @@ -12,15 +12,11 @@ * * PCI initialization for the SnapGear boards */ - #include #include #include -#include #include - -#include -#include "pci-sh7751.h" +#include "pci-sh4.h" #define SNAPGEAR_PCI_IO 0x4000 #define SNAPGEAR_PCI_MEM 0xfd000000 @@ -43,14 +39,12 @@ static struct resource sh7751_mem_resource = { .flags = IORESOURCE_MEM, }; -extern struct pci_ops sh7751_pci_ops; - struct pci_channel board_pci_channels[] = { - { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, + { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, { 0, } }; -static struct sh7751_pci_address_map sh7751_pci_map = { +static struct sh4_pci_address_map sh7751_pci_map = { .window0 = { .base = SH7751_CS2_BASE_ADDR, .size = SNAPGEAR_LSR0_SIZE, @@ -61,11 +55,11 @@ static struct sh7751_pci_address_map sh7751_pci_map = { .size = SNAPGEAR_LSR1_SIZE, }, - .flags = SH7751_PCIC_NO_RESET, + .flags = SH4_PCIC_NO_RESET, }; /* - * Initialize the SnapGear PCI interface + * Initialize the SnapGear PCI interface * Setup hardware to be Central Funtion * Copy the BSR regs to the PCI interface * Setup PCI windows into local RAM @@ -75,7 +69,7 @@ int __init pcibios_init_platform(void) return sh7751_pcic_init(&sh7751_pci_map); } -int __init pcibios_map_platform_irq(u8 slot, u8 pin) +int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) { int irq = -1; @@ -98,4 +92,3 @@ void __init pcibios_fixup(void) { /* Nothing to fixup .. */ } - diff --git a/arch/sh/drivers/pci/ops-titan.c b/arch/sh/drivers/pci/ops-titan.c index f76e4e963ac1..9c8b2027c35d 100644 --- a/arch/sh/drivers/pci/ops-titan.c +++ b/arch/sh/drivers/pci/ops-titan.c @@ -16,12 +16,11 @@ #include #include #include -#include #include #include -#include "pci-sh7751.h" +#include "pci-sh4.h" -int __init pcibios_map_platform_irq(u8 slot, u8 pin) +int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin) { int irq = -1; @@ -32,7 +31,8 @@ int __init pcibios_map_platform_irq(u8 slot, u8 pin) case 3: irq = TITAN_IRQ_MPCIB; break; /* mPCI B */ case 4: irq = TITAN_IRQ_USB; break; /* USB */ default: - printk(KERN_INFO "PCI: Bad IRQ mapping request for slot %d\n", slot); + printk(KERN_INFO "PCI: Bad IRQ mapping " + "request for slot %d\n", slot); return -1; } @@ -56,15 +56,13 @@ static struct resource sh7751_mem_resource = { .flags = IORESOURCE_MEM }; -extern struct pci_ops sh7751_pci_ops; - struct pci_channel board_pci_channels[] = { - { &sh7751_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, + { &sh4_pci_ops, &sh7751_io_resource, &sh7751_mem_resource, 0, 0xff }, { NULL, NULL, NULL, 0, 0 }, }; EXPORT_SYMBOL(board_pci_channels); -static struct sh7751_pci_address_map sh7751_pci_map = { +static struct sh4_pci_address_map sh7751_pci_map = { .window0 = { .base = SH7751_CS2_BASE_ADDR, .size = SH7751_MEM_REGION_SIZE*2, /* cs2 and cs3 */ @@ -75,7 +73,7 @@ static struct sh7751_pci_address_map sh7751_pci_map = { .size = SH7751_MEM_REGION_SIZE*2, }, - .flags = SH7751_PCIC_NO_RESET, + .flags = SH4_PCIC_NO_RESET, }; int __init pcibios_init_platform(void) diff --git a/arch/sh/drivers/pci/pci-auto.c b/arch/sh/drivers/pci/pci-auto.c index d55e46618549..ecf16344f94a 100644 --- a/arch/sh/drivers/pci/pci-auto.c +++ b/arch/sh/drivers/pci/pci-auto.c @@ -358,7 +358,6 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose, { u32 temp; -#if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D) && !defined(CONFIG_SH_R7780RP) /* * [jsun] we always bump up baselines a little, so that if there * nothing behind P2P bridge, we don't wind up overlapping IO/MEM @@ -366,7 +365,6 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose, */ pciauto_lower_memspc += 1; pciauto_lower_iospc += 1; -#endif /* * Configure subordinate bus number. The PCI subsystem @@ -392,11 +390,6 @@ pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose, * configured by this routine to happily live behind a * P2P bridge in a system. */ -#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_R7780RP) - pciauto_lower_memspc += 0x00400000; - pciauto_lower_iospc += 0x00004000; -#endif - /* Align memory and I/O to 4KB and 4 byte boundaries. */ pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1)) & ~(0x1000 - 1); @@ -467,9 +460,6 @@ pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus) if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) { DBG(" Bridge: primary=%.2x, secondary=%.2x\n", current_bus, sub_bus + 1); -#if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D) || defined(CONFIG_SH_R7780RP) - pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_1); -#endif pciauto_prescan_setup_bridge(hose, top_bus, current_bus, pci_devfn, sub_bus); DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n", diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h new file mode 100644 index 000000000000..5a61d6041f2c --- /dev/null +++ b/arch/sh/drivers/pci/pci-sh4.h @@ -0,0 +1,180 @@ +#ifndef __PCI_SH4_H +#define __PCI_SH4_H + +#ifdef CONFIG_CPU_SUBTYPE_SH7780 +#include "pci-sh7780.h" +#else +#include "pci-sh7751.h" +#endif + +#include + +/* startup values */ +#define PCI_PROBE_BIOS 1 +#define PCI_PROBE_CONF1 2 +#define PCI_PROBE_CONF2 4 +#define PCI_NO_SORT 0x100 +#define PCI_BIOS_SORT 0x200 +#define PCI_NO_CHECKS 0x400 +#define PCI_ASSIGN_ROMS 0x1000 +#define PCI_BIOS_IRQ_SCAN 0x2000 + +#define SH4_PCICR 0x100 /* PCI Control Register */ + #define SH4_PCICR_PREFIX 0xA5000000 /* CR prefix for write */ + #define SH4_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */ + #define SH4_PCICR_TRSB 0x00000200 /* Target Read Single */ + #define SH4_PCICR_BSWP 0x00000100 /* Target Byte Swap */ + #define SH4_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */ + #define SH4_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */ + #define SH4_PCICR_MD 0x00000030 /* MD9 and MD10 status */ + #define SH4_PCICR_SERR 0x00000008 /* SERR output assert */ + #define SH4_PCICR_INTA 0x00000004 /* INTA output assert */ + #define SH4_PCICR_PRST 0x00000002 /* PCI Reset Assert */ + #define SH4_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */ +#define SH4_PCILSR0 0x104 /* PCI Local Space Register0 */ +#define SH4_PCILSR1 0x108 /* PCI Local Space Register1 */ +#define SH4_PCILAR0 0x10C /* PCI Local Addr Register1 */ +#define SH4_PCILAR1 0x110 /* PCI Local Addr Register1 */ +#define SH4_PCIINT 0x114 /* PCI Interrupt Register */ + #define SH4_PCIINT_MLCK 0x00008000 /* Master Lock Error */ + #define SH4_PCIINT_TABT 0x00004000 /* Target Abort Error */ + #define SH4_PCIINT_TRET 0x00000200 /* Target Retry Error */ + #define SH4_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */ + #define SH4_PCIINT_PRTY 0x00000080 /* Address Parity Error */ + #define SH4_PCIINT_SERR 0x00000040 /* SERR Detection Error */ + #define SH4_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */ + #define SH4_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Err Det. */ + #define SH4_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */ + #define SH4_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */ + #define SH4_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */ + #define SH4_PCIINT_MRPD 0x00000001 /* Master Read PERR Detect */ +#define SH4_PCIINTM 0x118 /* PCI Interrupt Mask */ +#define SH4_PCIALR 0x11C /* Error Address Register */ +#define SH4_PCICLR 0x120 /* Error Command/Data */ + #define SH4_PCICLR_MPIO 0x80000000 + #define SH4_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */ + #define SH4_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */ + #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */ + #define SH4_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */ + #define SH4_PCICLR_TGT 0x04000000 /* Target Transfer Error */ + #define SH4_PCICLR_CMDL 0x0000000F /* PCI Command at Error */ +#define SH4_PCIAINT 0x130 /* Arbiter Interrupt Register */ + #define SH4_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */ + #define SH4_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */ + #define SH4_PCIAINT_MBTO 0x00001000 /* Master Bus Time Out */ + #define SH4_PCIAINT_TABT 0x00000008 /* Target Abort */ + #define SH4_PCIAINT_MABT 0x00000004 /* Master Abort */ + #define SH4_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */ + #define SH4_PCIAINT_WDPE 0x00000001 /* Write Data Parity Error */ +#define SH4_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ +#define SH4_PCIBMLR 0x138 /* Error Bus Master Register */ + #define SH4_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */ + #define SH4_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */ + #define SH4_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */ + #define SH4_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */ + #define SH4_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */ +#define SH4_PCIDMABT 0x140 /* DMA Transfer Arb. Register */ + #define SH4_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */ +#define SH4_PCIDPA0 0x180 /* DMA0 Transfer Addr. */ +#define SH4_PCIDLA0 0x184 /* DMA0 Local Addr. */ +#define SH4_PCIDTC0 0x188 /* DMA0 Transfer Cnt. */ +#define SH4_PCIDCR0 0x18C /* DMA0 Control Register */ + #define SH4_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */ + #define SH4_PCIDCR_MAST 0x00000100 /* DMA Termination Type */ + #define SH4_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/ + #define SH4_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */ + #define SH4_PCIDCR_LHLD 0x00000020 /* Local Address Control */ + #define SH4_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/ + #define SH4_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */ + #define SH4_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */ + #define SH4_PCIDCR_STOP 0x00000002 /* Force DMA Stop */ + #define SH4_PCIDCR_STRT 0x00000001 /* DMA Start */ +#define SH4_PCIDPA1 0x190 /* DMA1 Transfer Addr. */ +#define SH4_PCIDLA1 0x194 /* DMA1 Local Addr. */ +#define SH4_PCIDTC1 0x198 /* DMA1 Transfer Cnt. */ +#define SH4_PCIDCR1 0x19C /* DMA1 Control Register */ +#define SH4_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. */ +#define SH4_PCIDLA2 0x1A4 /* DMA2 Local Addr. */ +#define SH4_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. */ +#define SH4_PCIDCR2 0x1AC /* DMA2 Control Register */ +#define SH4_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. */ +#define SH4_PCIDLA3 0x1B4 /* DMA3 Local Addr. */ +#define SH4_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. */ +#define SH4_PCIDCR3 0x1BC /* DMA3 Control Register */ +#define SH4_PCIPAR 0x1C0 /* PIO Address Register */ + #define SH4_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */ + #define SH4_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */ + #define SH4_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */ + #define SH4_PCIPAR_REGAD 0x000000FC /* Register Address Number */ +#define SH4_PCIMBR 0x1C4 /* Memory Base Address */ + #define SH4_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */ + #define SH4_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */ +#define SH4_PCIIOBR 0x1C8 /* I/O Base Address Register */ + #define SH4_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */ + #define SH4_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */ +#define SH4_PCIPINT 0x1CC /* Power Mgmnt Int. Register */ + #define SH4_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */ + #define SH4_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */ +#define SH4_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */ +#define SH4_PCICLKR 0x1D4 /* Clock Ctrl. Register */ + #define SH4_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */ + #define SH4_PCICLKR_BCSTP 0x00000001 /* BCLK Clock Stop */ +/* For definitions of BCR, MCR see ... */ +#define SH4_PCIBCR1 0x1E0 /* Memory BCR1 Register */ + #define SH4_PCIMBR0 SH4_PCIBCR1 +#define SH4_PCIBCR2 0x1E4 /* Memory BCR2 Register */ + #define SH4_PCIMBMR0 SH4_PCIBCR2 +#define SH4_PCIWCR1 0x1E8 /* Wait Control 1 Register */ +#define SH4_PCIWCR2 0x1EC /* Wait Control 2 Register */ +#define SH4_PCIWCR3 0x1F0 /* Wait Control 3 Register */ + #define SH4_PCIMBR2 SH4_PCIWCR3 +#define SH4_PCIMCR 0x1F4 /* Memory Control Register */ +#define SH4_PCIBCR3 0x1f8 /* Memory BCR3 Register */ +#define SH4_PCIPCTR 0x200 /* Port Control Register */ + #define SH4_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */ + #define SH4_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */ + #define SH4_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */ + #define SH4_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */ + #define SH4_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */ + #define SH4_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */ + #define SH4_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */ + #define SH4_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */ + #define SH4_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */ +#define SH4_PCIPDTR 0x204 /* Port Data Register */ + #define SH4_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */ + #define SH4_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */ + #define SH4_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */ + #define SH4_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */ + #define SH4_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */ + #define SH4_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */ +#define SH4_PCIPDR 0x220 /* Port IO Data Register */ + +/* Flags */ +#define SH4_PCIC_NO_RESET 0x0001 + +/* arch/sh/kernel/drivers/pci/ops-sh4.c */ +extern struct pci_ops sh4_pci_ops; +int sh4_pci_check_direct(void); +int pci_fixup_pcic(void); + +struct sh4_pci_address_space { + unsigned long base; + unsigned long size; +}; + +struct sh4_pci_address_map { + struct sh4_pci_address_space window0; + struct sh4_pci_address_space window1; + unsigned long flags; +}; + +static inline void pci_write_reg(unsigned long val, unsigned long reg) +{ + outl(val, PCI_REG(reg)); +} + +static inline unsigned long pci_read_reg(unsigned long reg) +{ + return inl(PCI_REG(reg)); +} +#endif /* __PCI_SH4_H */ diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c index 65093ec1b55e..dbe837884983 100644 --- a/arch/sh/drivers/pci/pci-sh7751.c +++ b/arch/sh/drivers/pci/pci-sh7751.c @@ -15,180 +15,14 @@ #undef DEBUG -#include -#include #include #include -#include -#include +#include #include -#include #include - -#include +#include "pci-sh4.h" +#include #include -#include "pci-sh7751.h" - -static unsigned int pci_probe = PCI_PROBE_CONF1; -extern int pci_fixup_pcic(void); - -void pcibios_fixup_irqs(void) __attribute__ ((weak)); - -/* - * Direct access to PCI hardware... - */ - -#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) - -/* - * Functions for accessing PCI configuration space with type 1 accesses - */ -static int sh7751_pci_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - unsigned long flags; - u32 data; - - /* - * PCIPDR may only be accessed as 32 bit words, - * so we must do byte alignment by hand - */ - local_irq_save(flags); - outl(CONFIG_CMD(bus,devfn,where), PCI_REG(SH7751_PCIPAR)); - data = inl(PCI_REG(SH7751_PCIPDR)); - local_irq_restore(flags); - - switch (size) { - case 1: - *val = (data >> ((where & 3) << 3)) & 0xff; - break; - case 2: - *val = (data >> ((where & 2) << 3)) & 0xffff; - break; - case 4: - *val = data; - break; - default: - return PCIBIOS_FUNC_NOT_SUPPORTED; - } - - return PCIBIOS_SUCCESSFUL; -} - -/* - * Since SH7751 only does 32bit access we'll have to do a read, - * mask,write operation. - * We'll allow an odd byte offset, though it should be illegal. - */ -static int sh7751_pci_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - unsigned long flags; - int shift; - u32 data; - - local_irq_save(flags); - outl(CONFIG_CMD(bus,devfn,where), PCI_REG(SH7751_PCIPAR)); - data = inl(PCI_REG(SH7751_PCIPDR)); - local_irq_restore(flags); - - switch (size) { - case 1: - shift = (where & 3) << 3; - data &= ~(0xff << shift); - data |= ((val & 0xff) << shift); - break; - case 2: - shift = (where & 2) << 3; - data &= ~(0xffff << shift); - data |= ((val & 0xffff) << shift); - break; - case 4: - data = val; - break; - default: - return PCIBIOS_FUNC_NOT_SUPPORTED; - } - - outl(data, PCI_REG(SH7751_PCIPDR)); - - return PCIBIOS_SUCCESSFUL; -} - -#undef CONFIG_CMD - -struct pci_ops sh7751_pci_ops = { - .read = sh7751_pci_read, - .write = sh7751_pci_write, -}; - -static int __init pci_check_direct(void) -{ - unsigned int tmp, id; - - /* check for SH7751/SH7751R hardware */ - id = inl(SH7751_PCIREG_BASE+SH7751_PCICONF0); - if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) && - id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) { - pr_debug("PCI: This is not an SH7751(R) (%x)\n", id); - return -ENODEV; - } - - /* - * Check if configuration works. - */ - if (pci_probe & PCI_PROBE_CONF1) { - tmp = inl (PCI_REG(SH7751_PCIPAR)); - outl (0x80000000, PCI_REG(SH7751_PCIPAR)); - if (inl (PCI_REG(SH7751_PCIPAR)) == 0x80000000) { - outl (tmp, PCI_REG(SH7751_PCIPAR)); - printk(KERN_INFO "PCI: Using configuration type 1\n"); - request_region(PCI_REG(SH7751_PCIPAR), 8, "PCI conf1"); - return 0; - } - outl (tmp, PCI_REG(SH7751_PCIPAR)); - } - - pr_debug("PCI: pci_check_direct failed\n"); - return -EINVAL; -} - -/***************************************************************************************/ - -/* - * Handle bus scanning and fixups .... - */ - -static void __init pci_fixup_ide_bases(struct pci_dev *d) -{ - int i; - - /* - * PCI IDE controllers use non-standard I/O port decoding, respect it. - */ - if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) - return; - pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d)); - for(i=0; i<4; i++) { - struct resource *r = &d->resource[i]; - if ((r->start & ~0x80) == 0x374) { - r->start |= 2; - r->end = r->start; - } - } -} - -DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); - -/* - * Called after each bus is probed, but before its children - * are examined. - */ - -void __init pcibios_fixup_bus(struct pci_bus *b) -{ - pci_read_bridge_bases(b); -} /* * Initialization. Try all known PCI access methods. Note that we support @@ -196,25 +30,29 @@ void __init pcibios_fixup_bus(struct pci_bus *b) * to access config space. * * Note that the platform specific initialization (BSC registers, and memory - * space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it - * exitst and via the platform defined function pcibios_init_platform(). - * See pci_bigsur.c for implementation; - * - * The BIOS version of the pci functions is not yet implemented but it is left - * in for completeness. Currently an error will be genereated at compile time. + * space mapping) will be called via the platform defined function + * pcibios_init_platform(). */ - static int __init sh7751_pci_init(void) { + unsigned int id; int ret; pr_debug("PCI: Starting intialization.\n"); - if ((ret = pci_check_direct()) != 0) + + /* check for SH7751/SH7751R hardware */ + id = pci_read_reg(SH7751_PCICONF0); + if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) && + id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) { + pr_debug("PCI: This is not an SH7751(R) (%x)\n", id); + return -ENODEV; + } + + if ((ret = sh4_pci_check_direct()) != 0) return ret; return pcibios_init_platform(); } - subsys_initcall(sh7751_pci_init); static int __init __area_sdram_check(unsigned int area) @@ -228,7 +66,7 @@ static int __init __area_sdram_check(unsigned int area) area, word); return 0; } - outl(word, PCI_REG(SH7751_PCIBCR1)); + pci_write_reg(word, SH4_PCIBCR1); word = (u16)inw(SH7751_BCR2); /* check BCR2 for 32bit SDRAM interface*/ @@ -237,12 +75,12 @@ static int __init __area_sdram_check(unsigned int area) area, word); return 0; } - outl(word, PCI_REG(SH7751_PCIBCR2)); + pci_write_reg(word, SH4_PCIBCR2); return 1; } -int __init sh7751_pcic_init(struct sh7751_pci_address_map *map) +int __init sh7751_pcic_init(struct sh4_pci_address_map *map) { u32 reg; u32 word; @@ -251,39 +89,39 @@ int __init sh7751_pcic_init(struct sh7751_pci_address_map *map) reg = inl(SH7751_BCR1); reg |= 0x80000; outl(reg, SH7751_BCR1); - + /* Turn the clocks back on (not done in reset)*/ - outl(0, PCI_REG(SH7751_PCICLKR)); + pci_write_reg(0, SH4_PCICLKR); /* Clear Powerdown IRQ's (not done in reset) */ - word = SH7751_PCIPINT_D3 | SH7751_PCIPINT_D0; - outl(word, PCI_REG(SH7751_PCIPINT)); + word = SH4_PCIPINT_D3 | SH4_PCIPINT_D0; + pci_write_reg(word, SH4_PCIPINT); /* * This code is unused for some boards as it is done in the * bootloader and doing it here means the MAC addresses loaded * by the bootloader get lost. */ - if (!(map->flags & SH7751_PCIC_NO_RESET)) { + if (!(map->flags & SH4_PCIC_NO_RESET)) { /* toggle PCI reset pin */ - word = SH7751_PCICR_PREFIX | SH7751_PCICR_PRST; - outl(word,PCI_REG(SH7751_PCICR)); + word = SH4_PCICR_PREFIX | SH4_PCICR_PRST; + pci_write_reg(word, SH4_PCICR); /* Wait for a long time... not 1 sec. but long enough */ mdelay(100); - word = SH7751_PCICR_PREFIX; - outl(word,PCI_REG(SH7751_PCICR)); + word = SH4_PCICR_PREFIX; + pci_write_reg(word, SH4_PCICR); } - + /* set the command/status bits to: * Wait Cycle Control + Parity Enable + Bus Master + * Mem space enable */ word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER | SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES; - outl(word, PCI_REG(SH7751_PCICONF1)); + pci_write_reg(word, SH7751_PCICONF1); /* define this host as the host bridge */ - word = SH7751_PCI_HOST_BRIDGE << 24; - outl(word, PCI_REG(SH7751_PCICONF2)); + word = PCI_BASE_CLASS_BRIDGE << 24; + pci_write_reg(word, SH7751_PCICONF2); /* Set IO and Mem windows to local address * Make PCI and local address the same for easy 1 to 1 mapping @@ -291,46 +129,49 @@ int __init sh7751_pcic_init(struct sh7751_pci_address_map *map) * Window1 = map->window1.size @ cached area base = SDRAM */ word = map->window0.size - 1; - outl(word, PCI_REG(SH7751_PCILSR0)); + pci_write_reg(word, SH4_PCILSR0); word = map->window1.size - 1; - outl(word, PCI_REG(SH7751_PCILSR1)); + pci_write_reg(word, SH4_PCILSR1); /* Set the values on window 0 PCI config registers */ word = P2SEGADDR(map->window0.base); - outl(word, PCI_REG(SH7751_PCILAR0)); - outl(word, PCI_REG(SH7751_PCICONF5)); + pci_write_reg(word, SH4_PCILAR0); + pci_write_reg(word, SH7751_PCICONF5); /* Set the values on window 1 PCI config registers */ word = PHYSADDR(map->window1.base); - outl(word, PCI_REG(SH7751_PCILAR1)); - outl(word, PCI_REG(SH7751_PCICONF6)); + pci_write_reg(word, SH4_PCILAR1); + pci_write_reg(word, SH7751_PCICONF6); - /* Set the local 16MB PCI memory space window to + /* Set the local 16MB PCI memory space window to * the lowest PCI mapped address */ - word = PCIBIOS_MIN_MEM & SH7751_PCIMBR_MASK; - PCIDBG(2,"PCI: Setting upper bits of Memory window to 0x%x\n", word); - outl(word , PCI_REG(SH7751_PCIMBR)); + word = PCIBIOS_MIN_MEM & SH4_PCIMBR_MASK; + pr_debug("PCI: Setting upper bits of Memory window to 0x%x\n", word); + pci_write_reg(word , SH4_PCIMBR); /* Map IO space into PCI IO window * The IO window is 64K-PCIBIOS_MIN_IO in size - * IO addresses will be translated to the + * IO addresses will be translated to the * PCI IO window base address */ - PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO, - (64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO); + pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", + PCIBIOS_MIN_IO, (64 << 10), + SH4_PCI_IO_BASE + PCIBIOS_MIN_IO); - /* + /* * XXX: For now, leave this board-specific. In the event we have other * boards that need to do similar work, this can be wrapped. */ #ifdef CONFIG_SH_BIGSUR - bigsur_port_map(PCIBIOS_MIN_IO, (64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO,0); + bigsur_port_map(PCIBIOS_MIN_IO, (64 << 10), + SH4_PCI_IO_BASE + PCIBIOS_MIN_IO, 0); #endif - /* Make sure the MSB's of IO window are set to access PCI space correctly */ - word = PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK; - PCIDBG(2,"PCI: Setting upper bits of IO window to 0x%x\n", word); - outl(word, PCI_REG(SH7751_PCIIOBR)); - + /* Make sure the MSB's of IO window are set to access PCI space + * correctly */ + word = PCIBIOS_MIN_IO & SH4_PCIIOBR_MASK; + pr_debug("PCI: Setting upper bits of IO window to 0x%x\n", word); + pci_write_reg(word, SH4_PCIIOBR); + /* Set PCI WCRx, BCRx's, copy from BSC locations */ /* check BCR for SDRAM in specified area */ @@ -349,13 +190,13 @@ int __init sh7751_pcic_init(struct sh7751_pci_address_map *map) /* configure the wait control registers */ word = inl(SH7751_WCR1); - outl(word, PCI_REG(SH7751_PCIWCR1)); + pci_write_reg(word, SH4_PCIWCR1); word = inl(SH7751_WCR2); - outl(word, PCI_REG(SH7751_PCIWCR2)); + pci_write_reg(word, SH4_PCIWCR2); word = inl(SH7751_WCR3); - outl(word, PCI_REG(SH7751_PCIWCR3)); + pci_write_reg(word, SH4_PCIWCR3); word = inl(SH7751_MCR); - outl(word, PCI_REG(SH7751_PCIMCR)); + pci_write_reg(word, SH4_PCIMCR); /* NOTE: I'm ignoring the PCI error IRQs for now.. * TODO: add support for the internal error interrupts and @@ -368,49 +209,8 @@ int __init sh7751_pcic_init(struct sh7751_pci_address_map *map) /* SH7751 init done, set central function init complete */ /* use round robin mode to stop a device starving/overruning */ - word = SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN | SH7751_PCICR_ARBM; - outl(word,PCI_REG(SH7751_PCICR)); + word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_ARBM; + pci_write_reg(word, SH4_PCICR); return 1; } - -char * __init pcibios_setup(char *str) -{ - if (!strcmp(str, "off")) { - pci_probe = 0; - return NULL; - } - - return str; -} - -/* - * IRQ functions - */ -static u8 __init sh7751_no_swizzle(struct pci_dev *dev, u8 *pin) -{ - /* no swizzling */ - return PCI_SLOT(dev->devfn); -} - -static int sh7751_pci_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq = -1; - - /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */ - irq = pcibios_map_platform_irq(slot,pin); - if( irq < 0 ) { - pr_debug("PCI: Error mapping IRQ on device %s\n", pci_name(dev)); - return irq; - } - - pr_debug("Setting IRQ for slot %s to %d\n", pci_name(dev), irq); - - return irq; -} - -void __init pcibios_fixup_irqs(void) -{ - pci_fixup_irqs(sh7751_no_swizzle, sh7751_pci_lookup_irq); -} - diff --git a/arch/sh/drivers/pci/pci-sh7751.h b/arch/sh/drivers/pci/pci-sh7751.h index 1fee5cae10d1..68e3cb5e6bec 100644 --- a/arch/sh/drivers/pci/pci-sh7751.h +++ b/arch/sh/drivers/pci/pci-sh7751.h @@ -3,7 +3,7 @@ * * Dustin McIntire (dustin@sensoria.com) (c) 2001 * Paul Mundt (lethal@linux-sh.org) (c) 2003 - * + * * May be copied or modified under the terms of the GNU General Public * License. See linux/COPYING for more information. * @@ -12,28 +12,6 @@ #ifndef _PCI_SH7751_H_ #define _PCI_SH7751_H_ -#include - -/* set debug level 4=verbose...1=terse */ -//#define DEBUG_PCI 3 -#undef DEBUG_PCI - -#ifdef DEBUG_PCI -#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); } -#else -#define PCIDBG(n, x...) -#endif - -/* startup values */ -#define PCI_PROBE_BIOS 1 -#define PCI_PROBE_CONF1 2 -#define PCI_PROBE_CONF2 4 -#define PCI_NO_SORT 0x100 -#define PCI_BIOS_SORT 0x200 -#define PCI_NO_CHECKS 0x400 -#define PCI_ASSIGN_ROMS 0x1000 -#define PCI_BIOS_IRQ_SCAN 0x2000 - /* Platform Specific Values */ #define SH7751_VENDOR_ID 0x1054 #define SH7751_DEVICE_ID 0x3505 @@ -128,131 +106,6 @@ #define SH7751_PCICONF17_PMEN 0x00010000 /* PME Enable */ #define SH7751_PCICONF17_PWST 0x00000003 /* Power State */ /* SH7715 Internal PCI Registers */ -#define SH7751_PCICR 0x100 /* PCI Control Register */ - #define SH7751_PCICR_PREFIX 0xA5000000 /* CR prefix for write */ - #define SH7751_PCICR_TRSB 0x00000200 /* Target Read Single */ - #define SH7751_PCICR_BSWP 0x00000100 /* Target Byte Swap */ - #define SH7751_PCICR_PLUP 0x00000080 /* Enable PCI Pullup */ - #define SH7751_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */ - #define SH7751_PCICR_MD 0x00000030 /* MD9 and MD10 status */ - #define SH7751_PCICR_SERR 0x00000008 /* SERR output assert */ - #define SH7751_PCICR_INTA 0x00000004 /* INTA output assert */ - #define SH7751_PCICR_PRST 0x00000002 /* PCI Reset Assert */ - #define SH7751_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */ -#define SH7751_PCILSR0 0x104 /* PCI Local Space Register0 */ -#define SH7751_PCILSR1 0x108 /* PCI Local Space Register1 */ -#define SH7751_PCILAR0 0x10C /* PCI Local Address Register1 */ -#define SH7751_PCILAR1 0x110 /* PCI Local Address Register1 */ -#define SH7751_PCIINT 0x114 /* PCI Interrupt Register */ - #define SH7751_PCIINT_MLCK 0x00008000 /* Master Lock Error */ - #define SH7751_PCIINT_TABT 0x00004000 /* Target Abort Error */ - #define SH7751_PCIINT_TRET 0x00000200 /* Target Retry Error */ - #define SH7751_PCIINT_MFDE 0x00000100 /* Master Func. Disable Error */ - #define SH7751_PCIINT_PRTY 0x00000080 /* Address Parity Error */ - #define SH7751_PCIINT_SERR 0x00000040 /* SERR Detection Error */ - #define SH7751_PCIINT_TWDP 0x00000020 /* Tgt. Write Parity Error */ - #define SH7751_PCIINT_TRDP 0x00000010 /* Tgt. Read Parity Error Det. */ - #define SH7751_PCIINT_MTABT 0x00000008 /* Master-Tgt. Abort Error */ - #define SH7751_PCIINT_MMABT 0x00000004 /* Master-Master Abort Error */ - #define SH7751_PCIINT_MWPD 0x00000002 /* Master Write PERR Detect */ - #define SH7751_PCIINT_MRPD 0x00000002 /* Master Read PERR Detect */ -#define SH7751_PCIINTM 0x118 /* PCI Interrupt Mask Register */ -#define SH7751_PCIALR 0x11C /* Error Address Register */ -#define SH7751_PCICLR 0x120 /* Error Command/Data Register */ - #define SH7751_PCICLR_MPIO 0x80000000 /* Error Command/Data Register */ - #define SH7751_PCICLR_MDMA0 0x40000000 /* DMA0 Transfer Error */ - #define SH7751_PCICLR_MDMA1 0x20000000 /* DMA1 Transfer Error */ - #define SH7751_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */ - #define SH7751_PCICLR_MDMA3 0x08000000 /* DMA3 Transfer Error */ - #define SH7751_PCICLR_TGT 0x04000000 /* Target Transfer Error */ - #define SH7751_PCICLR_CMDL 0x0000000F /* PCI Command at Error */ -#define SH7751_PCIAINT 0x130 /* Arbiter Interrupt Register */ - #define SH7751_PCIAINT_MBKN 0x00002000 /* Master Broken Interrupt */ - #define SH7751_PCIAINT_TBTO 0x00001000 /* Target Bus Time Out */ - #define SH7751_PCIAINT_MBTO 0x00001000 /* Master Bus Time Out */ - #define SH7751_PCIAINT_TABT 0x00000008 /* Target Abort */ - #define SH7751_PCIAINT_MABT 0x00000004 /* Master Abort */ - #define SH7751_PCIAINT_RDPE 0x00000002 /* Read Data Parity Error */ - #define SH7751_PCIAINT_WDPE 0x00000002 /* Write Data Parity Error */ -#define SH7751_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ -#define SH7751_PCIBMLR 0x138 /* Error Bus Master Register */ - #define SH7751_PCIBMLR_REQ4 0x00000010 /* REQ4 bus master at error */ - #define SH7751_PCIBMLR_REQ3 0x00000008 /* REQ3 bus master at error */ - #define SH7751_PCIBMLR_REQ2 0x00000004 /* REQ2 bus master at error */ - #define SH7751_PCIBMLR_REQ1 0x00000002 /* REQ1 bus master at error */ - #define SH7751_PCIBMLR_REQ0 0x00000001 /* REQ0 bus master at error */ -#define SH7751_PCIDMABT 0x140 /* DMA Transfer Arb. Register */ - #define SH7751_PCIDMABT_RRBN 0x00000001 /* DMA Arbitor Round-Robin */ -#define SH7751_PCIDPA0 0x180 /* DMA0 Transfer Addr. Register */ -#define SH7751_PCIDLA0 0x184 /* DMA0 Local Addr. Register */ -#define SH7751_PCIDTC0 0x188 /* DMA0 Transfer Cnt. Register */ -#define SH7751_PCIDCR0 0x18C /* DMA0 Control Register */ - #define SH7751_PCIDCR_ALGN 0x00000600 /* DMA Alignment Mode */ - #define SH7751_PCIDCR_MAST 0x00000100 /* DMA Termination Type */ - #define SH7751_PCIDCR_INTM 0x00000080 /* DMA Interrupt Done Mask*/ - #define SH7751_PCIDCR_INTS 0x00000040 /* DMA Interrupt Done Status */ - #define SH7751_PCIDCR_LHLD 0x00000020 /* Local Address Control */ - #define SH7751_PCIDCR_PHLD 0x00000010 /* PCI Address Control*/ - #define SH7751_PCIDCR_IOSEL 0x00000008 /* PCI Address Space Type */ - #define SH7751_PCIDCR_DIR 0x00000004 /* DMA Transfer Direction */ - #define SH7751_PCIDCR_STOP 0x00000002 /* Force DMA Stop */ - #define SH7751_PCIDCR_STRT 0x00000001 /* DMA Start */ -#define SH7751_PCIDPA1 0x190 /* DMA1 Transfer Addr. Register */ -#define SH7751_PCIDLA1 0x194 /* DMA1 Local Addr. Register */ -#define SH7751_PCIDTC1 0x198 /* DMA1 Transfer Cnt. Register */ -#define SH7751_PCIDCR1 0x19C /* DMA1 Control Register */ -#define SH7751_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. Register */ -#define SH7751_PCIDLA2 0x1A4 /* DMA2 Local Addr. Register */ -#define SH7751_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. Register */ -#define SH7751_PCIDCR2 0x1AC /* DMA2 Control Register */ -#define SH7751_PCIDPA3 0x1B0 /* DMA3 Transfer Addr. Register */ -#define SH7751_PCIDLA3 0x1B4 /* DMA3 Local Addr. Register */ -#define SH7751_PCIDTC3 0x1B8 /* DMA3 Transfer Cnt. Register */ -#define SH7751_PCIDCR3 0x1BC /* DMA3 Control Register */ -#define SH7751_PCIPAR 0x1C0 /* PIO Address Register */ - #define SH7751_PCIPAR_CFGEN 0x80000000 /* Configuration Enable */ - #define SH7751_PCIPAR_BUSNO 0x00FF0000 /* Config. Bus Number */ - #define SH7751_PCIPAR_DEVNO 0x0000FF00 /* Config. Device Number */ - #define SH7751_PCIPAR_REGAD 0x000000FC /* Register Address Number */ -#define SH7751_PCIMBR 0x1C4 /* Memory Base Address Register */ - #define SH7751_PCIMBR_MASK 0xFF000000 /* Memory Space Mask */ - #define SH7751_PCIMBR_LOCK 0x00000001 /* Lock Memory Space */ -#define SH7751_PCIIOBR 0x1C8 /* I/O Base Address Register */ - #define SH7751_PCIIOBR_MASK 0xFFFC0000 /* IO Space Mask */ - #define SH7751_PCIIOBR_LOCK 0x00000001 /* Lock IO Space */ -#define SH7751_PCIPINT 0x1CC /* Power Mgmnt Int. Register */ - #define SH7751_PCIPINT_D3 0x00000002 /* D3 Pwr Mgmt. Interrupt */ - #define SH7751_PCIPINT_D0 0x00000001 /* D0 Pwr Mgmt. Interrupt */ -#define SH7751_PCIPINTM 0x1D0 /* Power Mgmnt Mask Register */ -#define SH7751_PCICLKR 0x1D4 /* Clock Ctrl. Register */ - #define SH7751_PCICLKR_PCSTP 0x00000002 /* PCI Clock Stop */ - #define SH7751_PCICLKR_BCSTP 0x00000002 /* BCLK Clock Stop */ -/* For definitions of BCR, MCR see ... */ -#define SH7751_PCIBCR1 0x1E0 /* Memory BCR1 Register */ -#define SH7751_PCIBCR2 0x1E4 /* Memory BCR2 Register */ -#define SH7751_PCIWCR1 0x1E8 /* Wait Control 1 Register */ -#define SH7751_PCIWCR2 0x1EC /* Wait Control 2 Register */ -#define SH7751_PCIWCR3 0x1F0 /* Wait Control 3 Register */ -#define SH7751_PCIMCR 0x1F4 /* Memory Control Register */ -#define SH7751_PCIBCR3 0x1f8 /* Memory BCR3 Register */ -#define SH7751_PCIPCTR 0x200 /* Port Control Register */ - #define SH7751_PCIPCTR_P2EN 0x000400000 /* Port 2 Enable */ - #define SH7751_PCIPCTR_P1EN 0x000200000 /* Port 1 Enable */ - #define SH7751_PCIPCTR_P0EN 0x000100000 /* Port 0 Enable */ - #define SH7751_PCIPCTR_P2UP 0x000000020 /* Port2 Pull Up Enable */ - #define SH7751_PCIPCTR_P2IO 0x000000010 /* Port2 Output Enable */ - #define SH7751_PCIPCTR_P1UP 0x000000008 /* Port1 Pull Up Enable */ - #define SH7751_PCIPCTR_P1IO 0x000000004 /* Port1 Output Enable */ - #define SH7751_PCIPCTR_P0UP 0x000000002 /* Port0 Pull Up Enable */ - #define SH7751_PCIPCTR_P0IO 0x000000001 /* Port0 Output Enable */ -#define SH7751_PCIPDTR 0x204 /* Port Data Register */ - #define SH7751_PCIPDTR_PB5 0x000000020 /* Port 5 Enable */ - #define SH7751_PCIPDTR_PB4 0x000000010 /* Port 4 Enable */ - #define SH7751_PCIPDTR_PB3 0x000000008 /* Port 3 Enable */ - #define SH7751_PCIPDTR_PB2 0x000000004 /* Port 2 Enable */ - #define SH7751_PCIPDTR_PB1 0x000000002 /* Port 1 Enable */ - #define SH7751_PCIPDTR_PB0 0x000000001 /* Port 0 Enable */ -#define SH7751_PCIPDR 0x220 /* Port IO Data Register */ /* Memory Control Registers */ #define SH7751_BCR1 0xFF800000 /* Memory BCR1 Register */ @@ -274,30 +127,9 @@ #define SH7751_CS5_BASE_ADDR (SH7751_CS4_BASE_ADDR + SH7751_MEM_REGION_SIZE) #define SH7751_CS6_BASE_ADDR (SH7751_CS5_BASE_ADDR + SH7751_MEM_REGION_SIZE) -/* General PCI values */ -#define SH7751_PCI_HOST_BRIDGE 0x6 - -/* Flags */ -#define SH7751_PCIC_NO_RESET 0x0001 - -/* External functions defined per platform i.e. Big Sur, SE... (these could be routed - * through the machine vectors... */ -extern int pcibios_init_platform(void); -extern int pcibios_map_platform_irq(u8 slot, u8 pin); - -struct sh7751_pci_address_space { - unsigned long base; - unsigned long size; -}; - -struct sh7751_pci_address_map { - struct sh7751_pci_address_space window0; - struct sh7751_pci_address_space window1; - unsigned long flags; -}; +struct sh4_pci_address_map; /* arch/sh/drivers/pci/pci-sh7751.c */ -extern int sh7751_pcic_init(struct sh7751_pci_address_map *map); +int sh7751_pcic_init(struct sh4_pci_address_map *map); #endif /* _PCI_SH7751_H_ */ - diff --git a/arch/sh/drivers/pci/pci-sh7780.c b/arch/sh/drivers/pci/pci-sh7780.c index e09721330ac2..bd3064a82087 100644 --- a/arch/sh/drivers/pci/pci-sh7780.c +++ b/arch/sh/drivers/pci/pci-sh7780.c @@ -20,197 +20,36 @@ #include #include #include -#include -#include #include -#include #include - -#include -#include -#include "pci-sh7780.h" - -static unsigned int pci_probe = PCI_PROBE_CONF1; -extern int pci_fixup_pcic(void); - -/* - * Direct access to PCI hardware... - */ - -#define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3)) - -/* - * Functions for accessing PCI configuration space with type 1 accesses - */ -static int sh7780_pci_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - unsigned long flags; - u32 data; - - /* - * PCIPDR may only be accessed as 32 bit words, - * so we must do byte alignment by hand - */ - local_irq_save(flags); - outl(CONFIG_CMD(bus, devfn, where), PCI_REG(SH7780_PCIPAR)); - data = inl(PCI_REG(SH7780_PCIPDR)); - local_irq_restore(flags); - - switch (size) { - case 1: - *val = (data >> ((where & 3) << 3)) & 0xff; - break; - case 2: - *val = (data >> ((where & 2) << 3)) & 0xffff; - break; - case 4: - *val = data; - break; - default: - return PCIBIOS_FUNC_NOT_SUPPORTED; - } - - return PCIBIOS_SUCCESSFUL; -} +#include "pci-sh4.h" /* - * Since SH7780 only does 32bit access we'll have to do a read, - * mask,write operation. - * We'll allow an odd byte offset, though it should be illegal. + * Initialization. Try all known PCI access methods. Note that we support + * using both PCI BIOS and direct access: in such cases, we use I/O ports + * to access config space. + * + * Note that the platform specific initialization (BSC registers, and memory + * space mapping) will be called via the platform defined function + * pcibios_init_platform(). */ -static int sh7780_pci_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) +static int __init sh7780_pci_init(void) { - unsigned long flags; - int shift; - u32 data; - - local_irq_save(flags); - outl(CONFIG_CMD(bus, devfn, where), PCI_REG(SH7780_PCIPAR)); - data = inl(PCI_REG(SH7780_PCIPDR)); - local_irq_restore(flags); - - switch (size) { - case 1: - shift = (where & 3) << 3; - data &= ~(0xff << shift); - data |= ((val & 0xff) << shift); - break; - case 2: - shift = (where & 2) << 3; - data &= ~(0xffff << shift); - data |= ((val & 0xffff) << shift); - break; - case 4: - data = val; - break; - default: - return PCIBIOS_FUNC_NOT_SUPPORTED; - } - - outl(data, PCI_REG(SH7780_PCIPDR)); - - return PCIBIOS_SUCCESSFUL; -} - -#undef CONFIG_CMD - -struct pci_ops sh7780_pci_ops = { - .read = sh7780_pci_read, - .write = sh7780_pci_write, -}; + unsigned int id; + int ret; -static int __init pci_check_direct(void) -{ - unsigned int tmp, id; + pr_debug("PCI: Starting intialization.\n"); outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */ /* check for SH7780/SH7780R hardware */ - id = inl(PCI_REG(SH7780_PCIVID)); + id = pci_read_reg(SH7780_PCIVID); if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) && (id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) { printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id); return -ENODEV; } - /* - * Check if configuration works. - */ - if (pci_probe & PCI_PROBE_CONF1) { - tmp = inl(PCI_REG(SH7780_PCIPAR)); - outl(0x80000000, PCI_REG(SH7780_PCIPAR)); - if (inl(PCI_REG(SH7780_PCIPAR)) == 0x80000000) { - outl(tmp, PCI_REG(SH7780_PCIPAR)); - printk(KERN_INFO "PCI: Using configuration type 1\n"); - request_region(PCI_REG(SH7780_PCIPAR), 8, "PCI conf1"); - return 0; - } - outl(tmp, PCI_REG(SH7780_PCIPAR)); - } - - pr_debug("PCI: pci_check_direct failed\n"); - return -EINVAL; -} - -/***************************************************************************************/ - -/* - * Handle bus scanning and fixups .... - */ - -static void __init pci_fixup_ide_bases(struct pci_dev *d) -{ - int i; - - /* - * PCI IDE controllers use non-standard I/O port decoding, respect it. - */ - if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE) - return; - pr_debug("PCI: IDE base address fixup for %s\n", pci_name(d)); - for(i=0; i<4; i++) { - struct resource *r = &d->resource[i]; - if ((r->start & ~0x80) == 0x374) { - r->start |= 2; - r->end = r->start; - } - } -} - -DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases); - -/* - * Called after each bus is probed, but before its children - * are examined. - */ - -void __init pcibios_fixup_bus(struct pci_bus *b) -{ - pci_read_bridge_bases(b); -} - -/* - * Initialization. Try all known PCI access methods. Note that we support - * using both PCI BIOS and direct access: in such cases, we use I/O ports - * to access config space. - * - * Note that the platform specific initialization (BSC registers, and memory - * space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it - * exists and via the platform defined function pcibios_init_platform(). - * See pci_bigsur.c for implementation; - * - * The BIOS version of the pci functions is not yet implemented but it is left - * in for completeness. Currently an error will be genereated at compile time. - */ - -static int __init sh7780_pci_init(void) -{ - int ret; - - pr_debug("PCI: Starting intialization.\n"); - /* Setup the INTC */ ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */ ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */ @@ -219,15 +58,14 @@ static int __init sh7780_pci_init(void) ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */ ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */ - if ((ret = pci_check_direct()) != 0) + if ((ret = sh4_pci_check_direct()) != 0) return ret; return pcibios_init_platform(); } - core_initcall(sh7780_pci_init); -int __init sh7780_pcic_init(struct sh7780_pci_address_map *map) +int __init sh7780_pcic_init(struct sh4_pci_address_map *map) { u32 word; @@ -236,25 +74,25 @@ int __init sh7780_pcic_init(struct sh7780_pci_address_map *map) * bootloader and doing it here means the MAC addresses loaded * by the bootloader get lost. */ - if (!(map->flags & SH7780_PCIC_NO_RESET)) { + if (!(map->flags & SH4_PCIC_NO_RESET)) { /* toggle PCI reset pin */ - word = SH7780_PCICR_PREFIX | SH7780_PCICR_PRST; - outl(word,PCI_REG(SH7780_PCICR)); + word = SH4_PCICR_PREFIX | SH4_PCICR_PRST; + pci_write_reg(word, SH4_PCICR); /* Wait for a long time... not 1 sec. but long enough */ mdelay(100); - word = SH7780_PCICR_PREFIX; - outl(word,PCI_REG(SH7780_PCICR)); + word = SH4_PCICR_PREFIX; + pci_write_reg(word, SH4_PCICR); } /* set the command/status bits to: * Wait Cycle Control + Parity Enable + Bus Master + * Mem space enable */ - outl(0x00000046, PCI_REG(SH7780_PCICMD)); + pci_write_reg(0x00000046, SH7780_PCICMD); /* define this host as the host bridge */ - word = SH7780_PCI_HOST_BRIDGE << 24; - outl(word, PCI_REG(SH7780_PCIRID)); + word = PCI_BASE_CLASS_BRIDGE << 24; + pci_write_reg(word, SH7780_PCIRID); /* Set IO and Mem windows to local address * Make PCI and local address the same for easy 1 to 1 mapping @@ -262,25 +100,26 @@ int __init sh7780_pcic_init(struct sh7780_pci_address_map *map) * Window1 = map->window1.size @ cached area base = SDRAM */ word = ((map->window0.size - 1) & 0x1ff00001) | 0x01; - outl(0x07f00001, PCI_REG(SH7780_PCILSR0)); + pci_write_reg(0x07f00001, SH4_PCILSR0); word = ((map->window1.size - 1) & 0x1ff00001) | 0x01; - outl(0x00000001, PCI_REG(SH7780_PCILSR1)); + pci_write_reg(0x00000001, SH4_PCILSR1); /* Set the values on window 0 PCI config registers */ word = P2SEGADDR(map->window0.base); - outl(0xa8000000, PCI_REG(SH7780_PCILAR0)); - outl(0x08000000, PCI_REG(SH7780_PCIMBAR0)); + pci_write_reg(0xa8000000, SH4_PCILAR0); + pci_write_reg(0x08000000, SH7780_PCIMBAR0); /* Set the values on window 1 PCI config registers */ word = P2SEGADDR(map->window1.base); - outl(0x00000000, PCI_REG(SH7780_PCILAR1)); - outl(0x00000000, PCI_REG(SH7780_PCIMBAR1)); + pci_write_reg(0x00000000, SH4_PCILAR1); + pci_write_reg(0x00000000, SH7780_PCIMBAR1); /* Map IO space into PCI IO window * The IO window is 64K-PCIBIOS_MIN_IO in size * IO addresses will be translated to the * PCI IO window base address */ - PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO, - (64*1024), SH7780_PCI_IO_BASE+PCIBIOS_MIN_IO); + pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", + PCIBIOS_MIN_IO, (64 << 10), + SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO); /* NOTE: I'm ignoring the PCI error IRQs for now.. * TODO: add support for the internal error interrupts and @@ -293,49 +132,8 @@ int __init sh7780_pcic_init(struct sh7780_pci_address_map *map) /* SH7780 init done, set central function init complete */ /* use round robin mode to stop a device starving/overruning */ - word = SH7780_PCICR_PREFIX | SH7780_PCICR_CFIN | /* SH7780_PCICR_ARBM |*/ SH7780_PCICR_FTO; - outl(word, PCI_REG(SH7780_PCICR)); + word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO; + pci_write_reg(word, SH4_PCICR); return 1; } - -char * __init pcibios_setup(char *str) -{ - if (!strcmp(str, "off")) { - pci_probe = 0; - return NULL; - } - - return str; -} - -/* - * IRQ functions - */ -static u8 __init sh7780_no_swizzle(struct pci_dev *dev, u8 *pin) -{ - /* no swizzling */ - return PCI_SLOT(dev->devfn); -} - -static int sh7780_pci_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq = -1; - - /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */ - irq = pcibios_map_platform_irq(slot,pin); - if( irq < 0 ) { - pr_debug("PCI: Error mapping IRQ on device %s\n", pci_name(dev)); - return irq; - } - - pr_debug("Setting IRQ for slot %s to %d\n", pci_name(dev), irq); - - return irq; -} - -void __init pcibios_fixup_irqs(void) -{ - pci_fixup_irqs(sh7780_no_swizzle, sh7780_pci_lookup_irq); -} - diff --git a/arch/sh/drivers/pci/pci-sh7780.h b/arch/sh/drivers/pci/pci-sh7780.h index 750d5d7753a2..f02d2180a4bc 100644 --- a/arch/sh/drivers/pci/pci-sh7780.h +++ b/arch/sh/drivers/pci/pci-sh7780.h @@ -12,28 +12,6 @@ #ifndef _PCI_SH7780_H_ #define _PCI_SH7780_H_ -#include - -/* set debug level 4=verbose...1=terse */ -//#define DEBUG_PCI 3 -#undef DEBUG_PCI - -#ifdef DEBUG_PCI -#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); } -#else -#define PCIDBG(n, x...) -#endif - -/* startup values */ -#define PCI_PROBE_BIOS 1 -#define PCI_PROBE_CONF1 2 -#define PCI_PROBE_CONF2 4 -#define PCI_NO_SORT 0x100 -#define PCI_BIOS_SORT 0x200 -#define PCI_NO_CHECKS 0x400 -#define PCI_ASSIGN_ROMS 0x1000 -#define PCI_BIOS_IRQ_SCAN 0x2000 - /* Platform Specific Values */ #define SH7780_VENDOR_ID 0x1912 #define SH7780_DEVICE_ID 0x0002 @@ -47,15 +25,12 @@ /* SH7780 Specific Values */ #define SH7780_PCI_CONFIG_BASE 0xFD000000 /* Config space base addr */ #define SH7780_PCI_CONFIG_SIZE 0x01000000 /* Config space size */ + #define SH7780_PCI_MEMORY_BASE 0xFD000000 /* Memory space base addr */ #define SH7780_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ -#if 1 + #define SH7780_PCI_IO_BASE 0xFE400000 /* IO space base address */ #define SH7780_PCI_IO_SIZE 0x00400000 /* Size of IO window */ -#else -#define SH7780_PCI_IO_BASE 0xFE200000 /* IO space base address */ -#define SH7780_PCI_IO_SIZE 0x00200000 /* Size of IO window */ -#endif #define SH7780_PCIREG_BASE 0xFE040000 /* PCI regs base address */ #define PCI_REG(n) (SH7780_PCIREG_BASE+n) @@ -90,44 +65,16 @@ #define SH7780_PCIPMCSR_BSE 0x046 #define SH7780_PCICDD 0x047 -/* SH7780 PCI Local Registers */ -#define SH7780_PCICR 0x100 /* PCI Control Register */ - #define SH7780_PCICR_PREFIX 0xA5000000 /* CR prefix for write */ - #define SH7780_PCICR_PFCS 0x00000800 /* TRDY/IRDY Enable */ - #define SH7780_PCICR_FTO 0x00000400 /* TRDY/IRDY Enable */ - #define SH7780_PCICR_PFE 0x00000200 /* Target Read Single */ - #define SH7780_PCICR_TBS 0x00000100 /* Target Byte Swap */ - #define SH7780_PCICR_ARBM 0x00000040 /* PCI Arbitration Mode */ - #define SH7780_PCICR_IOCS 0x00000004 /* INTA output assert */ - #define SH7780_PCICR_PRST 0x00000002 /* PCI Reset Assert */ - #define SH7780_PCICR_CFIN 0x00000001 /* Central Fun. Init Done */ -#define SH7780_PCILSR0 0x104 /* PCI Local Space Register0 */ -#define SH7780_PCILSR1 0x108 /* PCI Local Space Register1 */ -#define SH7780_PCILAR0 0x10C /* PCI Local Address Register1 */ -#define SH7780_PCILAR1 0x110 /* PCI Local Address Register1 */ -#define SH7780_PCIIR 0x114 /* PCI Interrupt Register */ -#define SH7780_PCIIMR 0x118 /* PCI Interrupt Mask Register */ -#define SH7780_PCIAIR 0x11C /* Error Address Register */ -#define SH7780_PCICIR 0x120 /* Error Command/Data Register */ -#define SH7780_PCIAINT 0x130 /* Arbiter Interrupt Register */ -#define SH7780_PCIAINTM 0x134 /* Arbiter Int. Mask Register */ -#define SH7780_PCIBMIR 0x138 /* Error Bus Master Register */ -#define SH7780_PCIPAR 0x1C0 /* PIO Address Register */ -#define SH7780_PCIPINT 0x1CC /* Power Management Int. Register */ -#define SH7780_PCIPINTM 0x1D0 /* Power Management Mask Register */ -#define SH7780_PCIMBR0 0x1E0 /* Memory Bank0 Register */ -#define SH7780_PCIMBMR0 0x1E4 /* Memory Bank0 Mask Register */ -#define SH7780_PCIMBR1 0x1E8 /* Memory Bank1 Register */ -#define SH7780_PCIMBMR1 0x1EC /* Memory Bank1 Mask Register */ -#define SH7780_PCIMBR2 0x1F0 /* Memory Bank2 Register */ -#define SH7780_PCIMBMR2 0x1F4 /* Memory Bank2 Mask Register */ -#define SH7780_PCIIOBR 0x1F8 /* Bank Register */ -#define SH7780_PCIIOBMR 0x1FC /* Bank Mask Register */ +#define SH7780_PCIMBR0 0x1E0 +#define SH7780_PCIMBMR0 0x1E4 +#define SH7780_PCIMBR2 0x1F0 +#define SH7780_PCIMBMR2 0x1F4 +#define SH7780_PCIIOBR 0x1F8 +#define SH7780_PCIIOBMR 0x1FC #define SH7780_PCICSCR0 0x210 /* Cache Snoop1 Cnt. Register */ #define SH7780_PCICSCR1 0x214 /* Cache Snoop2 Cnt. Register */ #define SH7780_PCICSAR0 0x218 /* Cache Snoop1 Addr. Register */ #define SH7780_PCICSAR1 0x21C /* Cache Snoop2 Addr. Register */ -#define SH7780_PCIPDR 0x220 /* Port IO Data Register */ /* General Memory Config Addresses */ #define SH7780_CS0_BASE_ADDR 0x0 @@ -139,30 +86,9 @@ #define SH7780_CS5_BASE_ADDR (SH7780_CS4_BASE_ADDR + SH7780_MEM_REGION_SIZE) #define SH7780_CS6_BASE_ADDR (SH7780_CS5_BASE_ADDR + SH7780_MEM_REGION_SIZE) -/* General PCI values */ -#define SH7780_PCI_HOST_BRIDGE 0x6 - -/* Flags */ -#define SH7780_PCIC_NO_RESET 0x0001 - -/* External functions defined per platform i.e. Big Sur, SE... (these could be routed - * through the machine vectors... */ -extern int pcibios_init_platform(void); -extern int pcibios_map_platform_irq(u8 slot, u8 pin); - -struct sh7780_pci_address_space { - unsigned long base; - unsigned long size; -}; - -struct sh7780_pci_address_map { - struct sh7780_pci_address_space window0; - struct sh7780_pci_address_space window1; - unsigned long flags; -}; +struct sh4_pci_address_map; /* arch/sh/drivers/pci/pci-sh7780.c */ -extern int sh7780_pcic_init(struct sh7780_pci_address_map *map); +int sh7780_pcic_init(struct sh4_pci_address_map *map); #endif /* _PCI_SH7780_H_ */ - diff --git a/arch/sh/drivers/pci/pci-st40.c b/arch/sh/drivers/pci/pci-st40.c index 7c81b8b65bb5..4ab5ea6b35fb 100644 --- a/arch/sh/drivers/pci/pci-st40.c +++ b/arch/sh/drivers/pci/pci-st40.c @@ -70,12 +70,6 @@ static void pci_set_rbar_region(unsigned int region, unsigned long localAddr, unsigned long pciOffset, unsigned long regionSize); -/* - * The pcibios_map_platform_irq function is defined in the appropriate - * board specific code and referenced here - */ -extern int __init pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin); - static __init void SetPCIPLL(void) { { @@ -422,13 +416,6 @@ struct pci_ops st40pci_config_ops = { /* Everything hangs off this */ static struct pci_bus *pci_root_bus; - -static u8 __init no_swizzle(struct pci_dev *dev, u8 * pin) -{ - return PCI_SLOT(dev->devfn); -} - - static int __init pcibios_init(void) { extern unsigned long memory_start, memory_end; @@ -465,17 +452,11 @@ static int __init pcibios_init(void) /* ok, do the scan man */ pci_root_bus = pci_scan_bus(0, &st40pci_config_ops, NULL); pci_assign_unassigned_resources(); - pci_fixup_irqs(no_swizzle, pcibios_map_platform_irq); return 0; } - subsys_initcall(pcibios_init); -void __init pcibios_fixup_bus(struct pci_bus *bus) -{ -} - /* * Publish a region of local address space over the PCI bus * to other devices. diff --git a/arch/sh/drivers/pci/pci.c b/arch/sh/drivers/pci/pci.c index 285dffd12bd8..7377a8a8e161 100644 --- a/arch/sh/drivers/pci/pci.c +++ b/arch/sh/drivers/pci/pci.c @@ -21,6 +21,26 @@ #include #include +static inline u8 bridge_swizzle(u8 pin, u8 slot) +{ + return (((pin - 1) + slot) % 4) + 1; +} + +static u8 __init simple_swizzle(struct pci_dev *dev, u8 *pinp) +{ + u8 pin = *pinp; + + while (dev->bus->parent) { + pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn)); + /* Move up the chain of bridges. */ + dev = dev->bus->self; + } + *pinp = pin; + + /* The slot is the slot of the last bridge. */ + return PCI_SLOT(dev->devfn); +} + static int __init pcibios_init(void) { struct pci_channel *p; @@ -36,19 +56,26 @@ static int __init pcibios_init(void) /* scan the buses */ busno = 0; - for (p= board_pci_channels; p->pci_ops != NULL; p++) { + for (p = board_pci_channels; p->pci_ops != NULL; p++) { bus = pci_scan_bus(busno, p->pci_ops, p); - busno = bus->subordinate+1; + busno = bus->subordinate + 1; } - /* board-specific fixups */ - pcibios_fixup_irqs(); + pci_fixup_irqs(simple_swizzle, pcibios_map_platform_irq); return 0; } - subsys_initcall(pcibios_init); +/* + * Called after each bus is probed, but before its children + * are examined. + */ +void __init pcibios_fixup_bus(struct pci_bus *bus) +{ + pci_read_bridge_bases(bus); +} + void pcibios_update_resource(struct pci_dev *dev, struct resource *root, struct resource *res, int resource) @@ -192,11 +219,10 @@ void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen) return NULL; } +EXPORT_SYMBOL(pci_iomap); void pci_iounmap(struct pci_dev *dev, void __iomem *addr) { iounmap(addr); } - -EXPORT_SYMBOL(pci_iomap); EXPORT_SYMBOL(pci_iounmap); diff --git a/arch/sh/kernel/cpu/sh4/Makefile b/arch/sh/kernel/cpu/sh4/Makefile index 3d5cafc71ae3..9611fab03b55 100644 --- a/arch/sh/kernel/cpu/sh4/Makefile +++ b/arch/sh/kernel/cpu/sh4/Makefile @@ -7,6 +7,9 @@ obj-y := ex.o probe.o obj-$(CONFIG_SH_FPU) += fpu.o obj-$(CONFIG_SH_STORE_QUEUES) += sq.o +# CPU subtype setup +obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o + # Primary on-chip clocks (common) clock-$(CONFIG_CPU_SH4) := clock-sh4.o clock-$(CONFIG_CPU_SUBTYPE_SH73180) := clock-sh73180.o diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7780.c b/arch/sh/kernel/cpu/sh4/setup-sh7780.c new file mode 100644 index 000000000000..72493f259edc --- /dev/null +++ b/arch/sh/kernel/cpu/sh4/setup-sh7780.c @@ -0,0 +1,79 @@ +/* + * SH7780 Setup + * + * Copyright (C) 2006 Paul Mundt + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include + +static struct resource rtc_resources[] = { + [0] = { + .start = 0xffe80000, + .end = 0xffe80000 + 0x58 - 1, + .flags = IORESOURCE_IO, + }, + [1] = { + /* Period IRQ */ + .start = 21, + .flags = IORESOURCE_IRQ, + }, + [2] = { + /* Carry IRQ */ + .start = 22, + .flags = IORESOURCE_IRQ, + }, + [3] = { + /* Alarm IRQ */ + .start = 23, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_device = { + .name = "sh-rtc", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_resources), + .resource = rtc_resources, +}; + +static struct plat_sci_port sci_platform_data[] = { + { + .mapbase = 0xffe00000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 40, 41, 43, 42 }, + }, { + .mapbase = 0xffe10000, + .flags = UPF_BOOT_AUTOCONF, + .type = PORT_SCIF, + .irqs = { 76, 77, 79, 78 }, + }, { + .flags = 0, + } +}; + +static struct platform_device sci_device = { + .name = "sh-sci", + .id = -1, + .dev = { + .platform_data = sci_platform_data, + }, +}; + +static struct platform_device *sh7780_devices[] __initdata = { + &rtc_device, + &sci_device, +}; + +static int __init sh7780_devices_setup(void) +{ + return platform_add_devices(sh7780_devices, + ARRAY_SIZE(sh7780_devices)); +} +__initcall(sh7780_devices_setup); diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index 894e64b2d5f0..27dba653cbe7 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -209,6 +209,11 @@ static inline void ctrl_outl(unsigned int b, unsigned long addr) *(volatile unsigned long*)addr = b; } +static inline void ctrl_delay(void) +{ + ctrl_inw(P2SEG); +} + #define IO_SPACE_LIMIT 0xffffffff /* diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h index 18a109de0f2e..6ccc948fe216 100644 --- a/include/asm-sh/pci.h +++ b/include/asm-sh/pci.h @@ -32,6 +32,34 @@ extern struct pci_channel board_pci_channels[]; #define PCIBIOS_MIN_IO board_pci_channels->io_resource->start #define PCIBIOS_MIN_MEM board_pci_channels->mem_resource->start +/* + * I/O routine helpers + */ +#ifdef CONFIG_CPU_SUBTYPE_SH7780 +#define PCI_IO_AREA 0xFE400000 +#define PCI_IO_SIZE 0x00400000 +#else +#define PCI_IO_AREA 0xFE240000 +#define PCI_IO_SIZE 0X00040000 +#endif + +#define PCI_MEM_SIZE 0x01000000 + +#define SH4_PCIIOBR_MASK 0xFFFC0000 +#define pci_ioaddr(addr) (PCI_IO_AREA + (addr & ~SH4_PCIIOBR_MASK)) + +#if defined(CONFIG_PCI) +#define is_pci_ioaddr(port) \ + (((port) >= PCIBIOS_MIN_IO) && \ + ((port) < (PCIBIOS_MIN_IO + PCI_IO_SIZE))) +#define is_pci_memaddr(port) \ + (((port) >= PCIBIOS_MIN_MEM) && \ + ((port) < (PCIBIOS_MIN_MEM + PCI_MEM_SIZE))) +#else +#define is_pci_ioaddr(port) (0) +#define is_pci_memaddr(port) (0) +#endif + struct pci_dev; extern void pcibios_set_master(struct pci_dev *dev); @@ -98,11 +126,12 @@ static inline void pci_dma_burst_advice(struct pci_dev *pdev, #endif /* Board-specific fixup routines. */ -extern void pcibios_fixup(void); -extern void pcibios_fixup_irqs(void); +void pcibios_fixup(void); +int pcibios_init_platform(void); +int pcibios_map_platform_irq(struct pci_dev *dev, u8 slot, u8 pin); #ifdef CONFIG_PCI_AUTO -extern int pciauto_assign_resources(int busno, struct pci_channel *hose); +int pciauto_assign_resources(int busno, struct pci_channel *hose); #endif static inline void pcibios_add_platform_entries(struct pci_dev *dev) -- cgit