From b0e0290bc47dd1bc8b1bd0c6b9ec0347564f3f21 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Nov 2023 09:04:16 +0100 Subject: arm64: dts: qcom: qdu1000: correct LLCC reg entries According to bindings and Linux driver there is no "multi_channel_register" address space for LLCC. The first "reg" entry is supposed to be llcc0_base since commit 43aa006e074c ("dt-bindings: arm: msm: Fix register regions used for LLCC banks"): qdu1000-idp.dtb: system-cache-controller@19200000: reg: [[0, 421527552, 0, 14155776], [0, 438304768, 0, 524288], [0, 572293416, 0, 4]] is too long qdu1000-idp.dtb: system-cache-controller@19200000: reg-names:0: 'llcc0_base' was expected qdu1000-idp.dtb: system-cache-controller@19200000: reg-names: ['llcc_base', 'llcc_broadcast_base', 'multi_channel_register'] is too long Signed-off-by: Krzysztof Kozlowski Acked-by: Mukesh Ojha Link: https://lore.kernel.org/r/20231107080417.16700-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) (limited to 'arch/arm64/boot/dts/qcom/qdu1000.dtsi') diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 1c0e5d271e91..618a101eb53a 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1446,11 +1446,9 @@ system-cache-controller@19200000 { compatible = "qcom,qdu1000-llcc"; reg = <0 0x19200000 0 0xd80000>, - <0 0x1a200000 0 0x80000>, - <0 0x221c8128 0 0x4>; - reg-names = "llcc_base", - "llcc_broadcast_base", - "multi_channel_register"; + <0 0x1a200000 0 0x80000>; + reg-names = "llcc0_base", + "llcc_broadcast_base"; interrupts = ; multi-ch-bit-off = <24 2>; }; -- cgit From 468cf125e4796e8ef9815e2d8d018f44cf8f1225 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 7 Nov 2023 09:04:17 +0100 Subject: arm64: dts: qcom: qdu1000-idp: drop unused LLCC multi-ch-bit-off There is no "multi-ch-bit-off" property in LLCC, according to bindings and Linux driver: qdu1000-idp.dtb: system-cache-controller@19200000: 'multi-ch-bit-off' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Acked-by: Mukesh Ojha Link: https://lore.kernel.org/r/20231107080417.16700-2-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arm64/boot/dts/qcom/qdu1000.dtsi') diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 618a101eb53a..89eff977d40e 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -1450,7 +1450,6 @@ reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = ; - multi-ch-bit-off = <24 2>; }; }; -- cgit From 66ec7b4f471300003c13b87a99bbd55255da5ba9 Mon Sep 17 00:00:00 2001 From: Imran Shaik Date: Thu, 23 Nov 2023 12:17:35 +0530 Subject: arm64: dts: qcom: qdu1000: Add ECPRI clock controller Add device node for ECPRI clock controller on qcom QDU1000 and QRU1000 SoCs. Signed-off-by: Imran Shaik Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20231123064735.2979802-5-quic_imrashai@quicinc.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/qdu1000.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm64/boot/dts/qcom/qdu1000.dtsi') diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi index 89eff977d40e..832f472c4b7a 100644 --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi @@ -381,6 +381,20 @@ #power-domain-cells = <1>; }; + ecpricc: clock-controller@280000 { + compatible = "qcom,qdu1000-ecpricc"; + reg = <0x0 0x00280000 0x0 0x31c00>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_ECPRI_CC_GPLL0_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL3_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL4_CLK_SRC>, + <&gcc GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + gpi_dma0: dma-controller@900000 { compatible = "qcom,qdu1000-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0x0 0x900000 0x0 0x60000>; -- cgit