From 9f5ead76d402f591ab810e71eae59ec28bf39eb9 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Wed, 1 Dec 2010 10:55:46 +0000 Subject: omap: PM debug: fix wake-on-timer debugfs dependency Wakeup-on-timer code does not have/need debugfs dependency. Move the function out of debugfs ifdef. Fixes compile error when CONFIG_DEBUG_FS is disabled but PM debug is enabled. Reported-by: Tony Lindgren Signed-off-by: Kevin Hilman Signed-off-by: Tony Lindgren --- arch/arm/mach-omap2/pm-debug.c | 34 +++++++++++++++++----------------- 1 file changed, 17 insertions(+), 17 deletions(-) (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 5e81517a7af2..a8afb610c7d8 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -161,6 +161,23 @@ void omap2_pm_dump(int mode, int resume, unsigned int us) printk(KERN_INFO "%-20s: 0x%08x\n", regs[i].name, regs[i].val); } +void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) +{ + u32 tick_rate, cycles; + + if (!seconds && !milliseconds) + return; + + tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); + cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; + omap_dm_timer_stop(gptimer_wakeup); + omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); + + pr_info("PM: Resume timer in %u.%03u secs" + " (%d ticks at %d ticks/sec.)\n", + seconds, milliseconds, cycles, tick_rate); +} + #ifdef CONFIG_DEBUG_FS #include #include @@ -354,23 +371,6 @@ void pm_dbg_update_time(struct powerdomain *pwrdm, int prev) pwrdm->timer = t; } -void omap2_pm_wakeup_on_timer(u32 seconds, u32 milliseconds) -{ - u32 tick_rate, cycles; - - if (!seconds && !milliseconds) - return; - - tick_rate = clk_get_rate(omap_dm_timer_get_fclk(gptimer_wakeup)); - cycles = tick_rate * seconds + tick_rate * milliseconds / 1000; - omap_dm_timer_stop(gptimer_wakeup); - omap_dm_timer_set_load_start(gptimer_wakeup, 0, 0xffffffff - cycles); - - pr_info("PM: Resume timer in %u.%03u secs" - " (%d ticks at %d ticks/sec.)\n", - seconds, milliseconds, cycles, tick_rate); -} - static int clkdm_dbg_show_counter(struct clockdomain *clkdm, void *user) { struct seq_file *s = (struct seq_file *)user; -- cgit From 59fb659b065f52fcc2deed293cfbfc58f890376c Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 15:30:55 -0700 Subject: OMAP2/3: PRCM: split OMAP2/3-specific PRCM code into OMAP2/3-specific files In preparation for adding OMAP4-specific PRCM accessor/mutator functions, split the existing OMAP2/3 PRCM code into OMAP2/3-specific files. Most of what was in mach-omap2/{cm,prm}.{c,h} has now been moved into mach-omap2/{cm,prm}2xxx_3xxx.{c,h}, since it was OMAP2xxx/3xxx-specific. This process also requires the #includes in each of these files to be changed to reference the new file name. As part of doing so, add some comments into plat-omap/sram.c and plat-omap/mcbsp.c, which use "sideways includes", to indicate that these users of the PRM/CM includes should not be doing so. Thanks to Felipe Contreras for comments on this patch. Signed-off-by: Paul Walmsley Cc: Jarkko Nikula Cc: Peter Ujfalusi Cc: Liam Girdwood Cc: Omar Ramirez Luna Acked-by: Omar Ramirez Luna Cc: Felipe Contreras Acked-by: Felipe Contreras Cc: Greg Kroah-Hartman Acked-by: Mark Brown Reviewed-by: Kevin Hilman Tested-by: Kevin Hilman Tested-by: Rajendra Nayak Tested-by: Santosh Shilimkar --- arch/arm/mach-omap2/Makefile | 11 +- arch/arm/mach-omap2/clkt2xxx_apll.c | 2 +- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 2 +- arch/arm/mach-omap2/clkt2xxx_osc.c | 2 +- arch/arm/mach-omap2/clkt2xxx_sys.c | 2 +- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 2 +- arch/arm/mach-omap2/clkt_dpll.c | 1 - arch/arm/mach-omap2/clock.c | 4 +- arch/arm/mach-omap2/clock2420_data.c | 4 +- arch/arm/mach-omap2/clock2430.c | 2 +- arch/arm/mach-omap2/clock2430_data.c | 4 +- arch/arm/mach-omap2/clock34xx.c | 2 +- arch/arm/mach-omap2/clock3517.c | 2 +- arch/arm/mach-omap2/clock3xxx.c | 4 +- arch/arm/mach-omap2/clock3xxx_data.c | 4 +- arch/arm/mach-omap2/clock44xx_data.c | 6 +- arch/arm/mach-omap2/clockdomain.c | 5 +- arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 4 +- arch/arm/mach-omap2/clockdomains44xx_data.c | 2 + arch/arm/mach-omap2/cm-regbits-24xx.h | 2 - arch/arm/mach-omap2/cm-regbits-34xx.h | 2 - arch/arm/mach-omap2/cm-regbits-44xx.h | 3 - arch/arm/mach-omap2/cm.c | 68 ----- arch/arm/mach-omap2/cm.h | 134 +-------- arch/arm/mach-omap2/cm2xxx_3xxx.c | 99 ++++++ arch/arm/mach-omap2/cm2xxx_3xxx.h | 131 ++++++++ arch/arm/mach-omap2/cm44xx.h | 1 + arch/arm/mach-omap2/cm4xxx.c | 2 +- arch/arm/mach-omap2/control.c | 4 +- arch/arm/mach-omap2/dpll3xxx.c | 4 +- arch/arm/mach-omap2/dsp.c | 11 +- arch/arm/mach-omap2/omap_hwmod.c | 5 +- arch/arm/mach-omap2/pm-debug.c | 4 +- arch/arm/mach-omap2/pm24xx.c | 4 +- arch/arm/mach-omap2/pm34xx.c | 4 +- arch/arm/mach-omap2/powerdomain.c | 3 + arch/arm/mach-omap2/powerdomain44xx.c | 1 + arch/arm/mach-omap2/powerdomains2xxx_data.c | 4 +- arch/arm/mach-omap2/powerdomains3xxx_data.c | 4 +- arch/arm/mach-omap2/powerdomains44xx_data.c | 1 - arch/arm/mach-omap2/prcm-common.h | 6 + arch/arm/mach-omap2/prcm.c | 88 +----- arch/arm/mach-omap2/prm-regbits-24xx.h | 2 +- arch/arm/mach-omap2/prm-regbits-34xx.h | 8 +- arch/arm/mach-omap2/prm-regbits-44xx.h | 2 - arch/arm/mach-omap2/prm.h | 352 +--------------------- arch/arm/mach-omap2/prm2xxx_3xxx.c | 51 +++- arch/arm/mach-omap2/prm2xxx_3xxx.h | 367 +++++++++++++++++++++++ arch/arm/mach-omap2/prm44xx.h | 1 + arch/arm/mach-omap2/sdrc.c | 2 - arch/arm/mach-omap2/sdrc2xxx.c | 2 +- arch/arm/mach-omap2/serial.c | 4 +- arch/arm/mach-omap2/sleep34xx.S | 4 +- arch/arm/mach-omap2/sram242x.S | 4 +- arch/arm/mach-omap2/sram243x.S | 4 +- arch/arm/mach-omap2/sram34xx.S | 2 +- arch/arm/plat-omap/include/plat/common.h | 2 + arch/arm/plat-omap/include/plat/prcm.h | 7 - arch/arm/plat-omap/mcbsp.c | 2 + arch/arm/plat-omap/sram.c | 5 +- drivers/staging/tidspbridge/core/_tiomap.h | 6 + 61 files changed, 763 insertions(+), 714 deletions(-) delete mode 100644 arch/arm/mach-omap2/cm.c create mode 100644 arch/arm/mach-omap2/cm2xxx_3xxx.c create mode 100644 arch/arm/mach-omap2/cm2xxx_3xxx.h create mode 100644 arch/arm/mach-omap2/prm2xxx_3xxx.h (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile index 2006deef0183..b2e4f7bcfa34 100644 --- a/arch/arm/mach-omap2/Makefile +++ b/arch/arm/mach-omap2/Makefile @@ -6,7 +6,7 @@ obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o pm.o \ common.o gpio.o dma.o wd_timer.o -omap-2-3-common = irq.o sdrc.o prm2xxx_3xxx.o +omap-2-3-common = irq.o sdrc.o hwmod-common = omap_hwmod.o \ omap_hwmod_common_data.o clock-common = clock.o clock_common_data.o \ @@ -72,9 +72,12 @@ endif endif # PRCM -obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm.o -obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm.o -obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm4xxx.o +obj-$(CONFIG_ARCH_OMAP2) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o +obj-$(CONFIG_ARCH_OMAP3) += prcm.o cm2xxx_3xxx.o prm2xxx_3xxx.o +# XXX The presence of cm2xxx_3xxx.o on the line below is temporary and +# will be removed once the OMAP4 part of the codebase is converted to +# use OMAP4-specific PRCM functions. +obj-$(CONFIG_ARCH_OMAP4) += prcm.o cm2xxx_3xxx.o cm4xxx.o # OMAP powerdomain framework powerdomain-common += powerdomain.o powerdomain-common.o diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 66e01acfd585..954d11f37542 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -26,7 +26,7 @@ #include "clock.h" #include "clock2xxx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" /* CM_CLKEN_PLL.EN_{54,96}M_PLL options (24XX) */ diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 019048434f13..530a76bc4a6c 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -32,7 +32,7 @@ #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" /* #define DOWN_VARIABLE_DPLL 1 */ /* Experimental */ diff --git a/arch/arm/mach-omap2/clkt2xxx_osc.c b/arch/arm/mach-omap2/clkt2xxx_osc.c index 2167be84a5bc..df7b80506483 100644 --- a/arch/arm/mach-omap2/clkt2xxx_osc.c +++ b/arch/arm/mach-omap2/clkt2xxx_osc.c @@ -27,7 +27,7 @@ #include "clock.h" #include "clock2xxx.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" static int omap2_enable_osc_ck(struct clk *clk) diff --git a/arch/arm/mach-omap2/clkt2xxx_sys.c b/arch/arm/mach-omap2/clkt2xxx_sys.c index 822b5a79f457..8693cfdac49a 100644 --- a/arch/arm/mach-omap2/clkt2xxx_sys.c +++ b/arch/arm/mach-omap2/clkt2xxx_sys.c @@ -26,7 +26,7 @@ #include "clock.h" #include "clock2xxx.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" void __iomem *prcm_clksrc_ctrl; diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index aef62918aaf0..f49f47d7457d 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -40,7 +40,7 @@ #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" const struct prcm_config *curr_prcm_set; diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 6ce512e902c6..337392c3f549 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c @@ -24,7 +24,6 @@ #include #include "clock.h" -#include "cm.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index b5babf5440e4..cda2f1da2e1f 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -29,9 +29,7 @@ #include #include "clock.h" -#include "prm.h" -#include "prm-regbits-24xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c index ed61ac2c6f7b..0b2471add7d2 100644 --- a/arch/arm/mach-omap2/clock2420_data.c +++ b/arch/arm/mach-omap2/clock2420_data.c @@ -22,8 +22,8 @@ #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" -#include "prm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" diff --git a/arch/arm/mach-omap2/clock2430.c b/arch/arm/mach-omap2/clock2430.c index 44d0cccc51a9..d87bc9cb2a36 100644 --- a/arch/arm/mach-omap2/clock2430.c +++ b/arch/arm/mach-omap2/clock2430.c @@ -25,7 +25,7 @@ #include "clock.h" #include "clock2xxx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" /** diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c index 1bded4e07489..570c26d81467 100644 --- a/arch/arm/mach-omap2/clock2430_data.c +++ b/arch/arm/mach-omap2/clock2430_data.c @@ -22,8 +22,8 @@ #include "clock.h" #include "clock2xxx.h" #include "opp2xxx.h" -#include "prm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" diff --git a/arch/arm/mach-omap2/clock34xx.c b/arch/arm/mach-omap2/clock34xx.c index 6febd5f11e85..287abc480924 100644 --- a/arch/arm/mach-omap2/clock34xx.c +++ b/arch/arm/mach-omap2/clock34xx.c @@ -25,7 +25,7 @@ #include "clock.h" #include "clock34xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" /** diff --git a/arch/arm/mach-omap2/clock3517.c b/arch/arm/mach-omap2/clock3517.c index b496a9305e1c..74116a3cf099 100644 --- a/arch/arm/mach-omap2/clock3517.c +++ b/arch/arm/mach-omap2/clock3517.c @@ -25,7 +25,7 @@ #include "clock.h" #include "clock3517.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" /* diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c index a447c4d2c28a..81f5fdb256dc 100644 --- a/arch/arm/mach-omap2/clock3xxx.c +++ b/arch/arm/mach-omap2/clock3xxx.c @@ -25,9 +25,9 @@ #include "clock.h" #include "clock3xxx.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-34xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" /* diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c index ee8aa39269f3..a179edb03c13 100644 --- a/arch/arm/mach-omap2/clock3xxx_data.c +++ b/arch/arm/mach-omap2/clock3xxx_data.c @@ -28,9 +28,9 @@ #include "clock36xx.h" #include "clock3517.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-34xx.h" #include "control.h" diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c index 254f341e4bd3..91ab6f223b80 100644 --- a/arch/arm/mach-omap2/clock44xx_data.c +++ b/arch/arm/mach-omap2/clock44xx_data.c @@ -33,11 +33,15 @@ #include "cm1_44xx.h" #include "cm2_44xx.h" #include "cm-regbits-44xx.h" -#include "prm.h" +#include "prm44xx.h" #include "prm44xx.h" #include "prm-regbits-44xx.h" #include "control.h" +/* OMAP4 modulemode control */ +#define OMAP4430_MODULEMODE_HWCTRL 0 +#define OMAP4430_MODULEMODE_SWCTRL 1 + /* Root clocks */ static struct clk extalt_clkin_ck = { diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 6fb61b1a0d46..a2142e0f1ef4 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -27,9 +27,10 @@ #include -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" #include #include diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index 8dadf754ff11..de1d3b759aee 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -36,8 +36,8 @@ #include #include -#include "cm.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" #include "cm-regbits-34xx.h" #include "cm-regbits-44xx.h" diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index d4a520603470..7fc81f651b5e 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -27,6 +27,8 @@ #include #include +#include "cm1_44xx.h" +#include "cm2_44xx.h" #include "cm1_44xx.h" #include "cm2_44xx.h" diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h index 9a106c04c4a0..0856f2bcee5d 100644 --- a/arch/arm/mach-omap2/cm-regbits-24xx.h +++ b/arch/arm/mach-omap2/cm-regbits-24xx.h @@ -14,8 +14,6 @@ * published by the Free Software Foundation. */ -#include "cm.h" - /* Bits shared between registers */ /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 4f959a7d881c..cd9ff8b6a109 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -14,8 +14,6 @@ * published by the Free Software Foundation. */ -#include "cm.h" - /* Bits shared between registers */ /* CM_FCLKEN1_CORE and CM_ICLKEN1_CORE shared bits */ diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h index 0b72be433776..9d47a05b17b4 100644 --- a/arch/arm/mach-omap2/cm-regbits-44xx.h +++ b/arch/arm/mach-omap2/cm-regbits-44xx.h @@ -22,9 +22,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H #define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H -#include "cm.h" - - /* * Used by CM_L3_1_DYNAMICDEP, CM_L3_1_DYNAMICDEP_RESTORE, CM_MPU_DYNAMICDEP, * CM_TESLA_DYNAMICDEP diff --git a/arch/arm/mach-omap2/cm.c b/arch/arm/mach-omap2/cm.c deleted file mode 100644 index 721c3b66740a..000000000000 --- a/arch/arm/mach-omap2/cm.c +++ /dev/null @@ -1,68 +0,0 @@ -/* - * OMAP2/3 CM module functions - * - * Copyright (C) 2009 Nokia Corporation - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -#include "cm.h" -#include "cm-regbits-24xx.h" -#include "cm-regbits-34xx.h" - -static const u8 cm_idlest_offs[] = { - CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 -}; - -/** - * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby - * @prcm_mod: PRCM module offset - * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) - * @idlest_shift: shift of the bit in the CM_IDLEST* register to check - * - * XXX document - */ -int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) -{ - int ena = 0, i = 0; - u8 cm_idlest_reg; - u32 mask; - - if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs))) - return -EINVAL; - - cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; - - mask = 1 << idlest_shift; - - if (cpu_is_omap24xx()) - ena = mask; - else if (cpu_is_omap34xx()) - ena = 0; - else - BUG(); - - /* XXX should be OMAP2 CM */ - omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), - MAX_MODULE_READY_TIME, i); - - return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; -} - diff --git a/arch/arm/mach-omap2/cm.h b/arch/arm/mach-omap2/cm.h index bf21375eee7a..a7bc096bd407 100644 --- a/arch/arm/mach-omap2/cm.h +++ b/arch/arm/mach-omap2/cm.h @@ -1,8 +1,5 @@ -#ifndef __ARCH_ASM_MACH_OMAP2_CM_H -#define __ARCH_ASM_MACH_OMAP2_CM_H - /* - * OMAP2/3 Clock Management (CM) register definitions + * OMAP2+ Clock Management prototypes * * Copyright (C) 2007-2009 Texas Instruments, Inc. * Copyright (C) 2007-2009 Nokia Corporation @@ -13,133 +10,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ - -#include "prcm-common.h" - -#define OMAP2420_CM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) -#define OMAP2430_CM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) -#define OMAP34XX_CM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) - - -#include "cm44xx.h" - -/* - * Architecture-specific global CM registers - * Use cm_{read,write}_reg() with these registers. - * These registers appear once per CM module. - */ - -#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) -#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) -#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) - -#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) - -/* - * Module specific CM registers from CM_BASE + domain offset - * Use cm_{read,write}_mod_reg() with these registers. - * These register offsets generally appear in more than one PRCM submodule. - */ - -/* Common between 24xx and 34xx */ - -#define CM_FCLKEN 0x0000 -#define CM_FCLKEN1 CM_FCLKEN -#define CM_CLKEN CM_FCLKEN -#define CM_ICLKEN 0x0010 -#define CM_ICLKEN1 CM_ICLKEN -#define CM_ICLKEN2 0x0014 -#define CM_ICLKEN3 0x0018 -#define CM_IDLEST 0x0020 -#define CM_IDLEST1 CM_IDLEST -#define CM_IDLEST2 0x0024 -#define CM_AUTOIDLE 0x0030 -#define CM_AUTOIDLE1 CM_AUTOIDLE -#define CM_AUTOIDLE2 0x0034 -#define CM_AUTOIDLE3 0x0038 -#define CM_CLKSEL 0x0040 -#define CM_CLKSEL1 CM_CLKSEL -#define CM_CLKSEL2 0x0044 -#define OMAP2_CM_CLKSTCTRL 0x0048 -#define OMAP4_CM_CLKSTCTRL 0x0000 - - -/* Architecture-specific registers */ - -#define OMAP24XX_CM_FCLKEN2 0x0004 -#define OMAP24XX_CM_ICLKEN4 0x001c -#define OMAP24XX_CM_AUTOIDLE4 0x003c - -#define OMAP2430_CM_IDLEST3 0x0028 - -#define OMAP3430_CM_CLKEN_PLL 0x0004 -#define OMAP3430ES2_CM_CLKEN2 0x0004 -#define OMAP3430ES2_CM_FCLKEN3 0x0008 -#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 -#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 -#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 -#define OMAP3430_CM_CLKSEL1 CM_CLKSEL -#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL -#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 -#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 -#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL -#define OMAP3430_CM_CLKSTST 0x004c -#define OMAP3430ES2_CM_CLKSEL4 0x004c -#define OMAP3430ES2_CM_CLKSEL5 0x0050 -#define OMAP3430_CM_CLKSEL2_EMU 0x0050 -#define OMAP3430_CM_CLKSEL3_EMU 0x0054 - -/* CM2.CEFUSE_CM2 register offsets */ - -/* OMAP4 modulemode control */ -#define OMAP4430_MODULEMODE_HWCTRL 0 -#define OMAP4430_MODULEMODE_SWCTRL 1 - -/* Clock management domain register get/set */ - -#ifndef __ASSEMBLER__ - -extern u32 cm_read_mod_reg(s16 module, u16 idx); -extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); -extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); - -extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, - u8 idlest_shift); -extern int omap4_cm_wait_module_ready(void __iomem *clkctrl_reg); - -static inline u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return cm_rmw_mod_reg_bits(bits, bits, module, idx); -} - -static inline u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return cm_rmw_mod_reg_bits(bits, 0x0, module, idx); -} - -#endif - -/* CM register bits shared between 24XX and 3430 */ - -/* CM_CLKSEL_GFX */ -#define OMAP_CLKSEL_GFX_SHIFT 0 -#define OMAP_CLKSEL_GFX_MASK (0x7 << 0) - -/* CM_ICLKEN_GFX */ -#define OMAP_EN_GFX_SHIFT 0 -#define OMAP_EN_GFX_MASK (1 << 0) - -/* CM_IDLEST_GFX */ -#define OMAP_ST_GFX_MASK (1 << 0) - - -/* CM_IDLEST indicator */ -#define OMAP24XX_CM_IDLEST_VAL 0 -#define OMAP34XX_CM_IDLEST_VAL 1 +#ifndef __ARCH_ASM_MACH_OMAP2_CM_H +#define __ARCH_ASM_MACH_OMAP2_CM_H /* * MAX_MODULE_READY_TIME: max duration in microseconds to wait for the diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c new file mode 100644 index 000000000000..5978ce426ec5 --- /dev/null +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -0,0 +1,99 @@ +/* + * OMAP2/3 CM module functions + * + * Copyright (C) 2009 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "cm-regbits-24xx.h" +#include "cm-regbits-34xx.h" + +static const u8 cm_idlest_offs[] = { + CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 +}; + + +u32 cm_read_mod_reg(s16 module, u16 idx) +{ + return __raw_readl(cm_base + module + idx); +} + +void cm_write_mod_reg(u32 val, s16 module, u16 idx) +{ + __raw_writel(val, cm_base + module + idx); +} + +/* Read-modify-write a register in a CM module. Caller must lock */ +u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +{ + u32 v; + + v = cm_read_mod_reg(module, idx); + v &= ~mask; + v |= bits; + cm_write_mod_reg(v, module, idx); + + return v; +} + +u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return cm_rmw_mod_reg_bits(bits, bits, module, idx); +} + +u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return cm_rmw_mod_reg_bits(bits, 0x0, module, idx); +} + +/** + * omap2_cm_wait_idlest_ready - wait for a module to leave idle or standby + * @prcm_mod: PRCM module offset + * @idlest_id: CM_IDLESTx register ID (i.e., x = 1, 2, 3) + * @idlest_shift: shift of the bit in the CM_IDLEST* register to check + * + * XXX document + */ +int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) +{ + int ena = 0, i = 0; + u8 cm_idlest_reg; + u32 mask; + + if (!idlest_id || (idlest_id > ARRAY_SIZE(cm_idlest_offs))) + return -EINVAL; + + cm_idlest_reg = cm_idlest_offs[idlest_id - 1]; + + mask = 1 << idlest_shift; + + if (cpu_is_omap24xx()) + ena = mask; + else if (cpu_is_omap34xx()) + ena = 0; + else + BUG(); + + omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), + MAX_MODULE_READY_TIME, i); + + return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; +} + diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h new file mode 100644 index 000000000000..5e572112be06 --- /dev/null +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -0,0 +1,131 @@ +/* + * OMAP2/3 Clock Management (CM) register definitions + * + * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The CM hardware modules on the OMAP2/3 are quite similar to each + * other. The CM modules/instances on OMAP4 are quite different, so + * they are handled in a separate file. + */ +#ifndef __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H +#define __ARCH_ASM_MACH_OMAP2_CM2XXX_3XXX_H + +#include "prcm-common.h" + +#define OMAP2420_CM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg)) +#define OMAP2430_CM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) +#define OMAP34XX_CM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) + + +/* + * OMAP3-specific global CM registers + * Use cm_{read,write}_reg() with these registers. + * These registers appear once per CM module. + */ + +#define OMAP3430_CM_REVISION OMAP34XX_CM_REGADDR(OCP_MOD, 0x0000) +#define OMAP3430_CM_SYSCONFIG OMAP34XX_CM_REGADDR(OCP_MOD, 0x0010) +#define OMAP3430_CM_POLCTRL OMAP34XX_CM_REGADDR(OCP_MOD, 0x009c) + +#define OMAP3_CM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP3430_CM_CLKOUT_CTRL OMAP_CM_REGADDR(OMAP3430_CCR_MOD, 0x0070) + +/* + * Module specific CM register offsets from CM_BASE + domain offset + * Use cm_{read,write}_mod_reg() with these registers. + * These register offsets generally appear in more than one PRCM submodule. + */ + +/* Common between OMAP2 and OMAP3 */ + +#define CM_FCLKEN 0x0000 +#define CM_FCLKEN1 CM_FCLKEN +#define CM_CLKEN CM_FCLKEN +#define CM_ICLKEN 0x0010 +#define CM_ICLKEN1 CM_ICLKEN +#define CM_ICLKEN2 0x0014 +#define CM_ICLKEN3 0x0018 +#define CM_IDLEST 0x0020 +#define CM_IDLEST1 CM_IDLEST +#define CM_IDLEST2 0x0024 +#define CM_AUTOIDLE 0x0030 +#define CM_AUTOIDLE1 CM_AUTOIDLE +#define CM_AUTOIDLE2 0x0034 +#define CM_AUTOIDLE3 0x0038 +#define CM_CLKSEL 0x0040 +#define CM_CLKSEL1 CM_CLKSEL +#define CM_CLKSEL2 0x0044 +#define OMAP2_CM_CLKSTCTRL 0x0048 + +/* OMAP2-specific register offsets */ + +#define OMAP24XX_CM_FCLKEN2 0x0004 +#define OMAP24XX_CM_ICLKEN4 0x001c +#define OMAP24XX_CM_AUTOIDLE4 0x003c + +#define OMAP2430_CM_IDLEST3 0x0028 + +/* OMAP3-specific register offsets */ + +#define OMAP3430_CM_CLKEN_PLL 0x0004 +#define OMAP3430ES2_CM_CLKEN2 0x0004 +#define OMAP3430ES2_CM_FCLKEN3 0x0008 +#define OMAP3430_CM_IDLEST_PLL CM_IDLEST2 +#define OMAP3430_CM_AUTOIDLE_PLL CM_AUTOIDLE2 +#define OMAP3430ES2_CM_AUTOIDLE2_PLL CM_AUTOIDLE2 +#define OMAP3430_CM_CLKSEL1 CM_CLKSEL +#define OMAP3430_CM_CLKSEL1_PLL CM_CLKSEL +#define OMAP3430_CM_CLKSEL2_PLL CM_CLKSEL2 +#define OMAP3430_CM_SLEEPDEP CM_CLKSEL2 +#define OMAP3430_CM_CLKSEL3 OMAP2_CM_CLKSTCTRL +#define OMAP3430_CM_CLKSTST 0x004c +#define OMAP3430ES2_CM_CLKSEL4 0x004c +#define OMAP3430ES2_CM_CLKSEL5 0x0050 +#define OMAP3430_CM_CLKSEL2_EMU 0x0050 +#define OMAP3430_CM_CLKSEL3_EMU 0x0054 + + +/* CM_IDLEST bit field values to indicate deasserted IdleReq */ + +#define OMAP24XX_CM_IDLEST_VAL 0 +#define OMAP34XX_CM_IDLEST_VAL 1 + + +/* Clock management domain register get/set */ + +#ifndef __ASSEMBLER__ + +extern u32 cm_read_mod_reg(s16 module, u16 idx); +extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); +extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); + +extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, + u8 idlest_shift); +extern u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); + +#endif + +/* CM register bits shared between 24XX and 3430 */ + +/* CM_CLKSEL_GFX */ +#define OMAP_CLKSEL_GFX_SHIFT 0 +#define OMAP_CLKSEL_GFX_MASK (0x7 << 0) + +/* CM_ICLKEN_GFX */ +#define OMAP_EN_GFX_SHIFT 0 +#define OMAP_EN_GFX_MASK (1 << 0) + +/* CM_IDLEST_GFX */ +#define OMAP_ST_GFX_MASK (1 << 0) + +#endif diff --git a/arch/arm/mach-omap2/cm44xx.h b/arch/arm/mach-omap2/cm44xx.h index d3905263e035..48fc3f426fbd 100644 --- a/arch/arm/mach-omap2/cm44xx.h +++ b/arch/arm/mach-omap2/cm44xx.h @@ -18,6 +18,7 @@ #include "prcm-common.h" +#include "cm.h" #define OMAP4_CM_CLKSTCTRL 0x0000 diff --git a/arch/arm/mach-omap2/cm4xxx.c b/arch/arm/mach-omap2/cm4xxx.c index f8a660a1a4a6..25d2b3e4c6f7 100644 --- a/arch/arm/mach-omap2/cm4xxx.c +++ b/arch/arm/mach-omap2/cm4xxx.c @@ -23,7 +23,7 @@ #include -#include "cm.h" +#include "cm44xx.h" #include "cm-regbits-44xx.h" /** diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index b066c6e110a6..2506edfc4acb 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -20,8 +20,8 @@ #include "cm-regbits-34xx.h" #include "prm-regbits-34xx.h" -#include "cm.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" #include "sdrc.h" #include "pm.h" #include "control.h" diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index ed8d330522f1..cb535ee4e8fe 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c @@ -32,9 +32,7 @@ #include #include "clock.h" -#include "prm.h" -#include "prm-regbits-34xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index 6feeeae6c21b..cf5f3331af27 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c @@ -11,9 +11,16 @@ * published by the Free Software Foundation. */ +/* + * XXX The function pointers to the PRM/CM functions are incorrect and + * should be removed. No device driver should be changing PRM/CM bits + * directly; that's a layering violation -- those bits are the responsibility + * of the OMAP PM core code. + */ + #include -#include "prm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #ifdef CONFIG_BRIDGE_DVFS #include #endif diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 2b660e57a302..1312ce2913a5 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -145,8 +145,9 @@ #include #include -#include "cm.h" -#include "prm.h" +#include "cm2xxx_3xxx.h" +#include "cm44xx.h" +#include "prm2xxx_3xxx.h" #include "prm44xx.h" /* Maximum microseconds to wait for OMAP module to softreset */ diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index a8afb610c7d8..1f5d68beabf3 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -33,8 +33,8 @@ #include #include -#include "prm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #include "pm.h" int omap2_pm_debug; diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index aea7ced9a2ff..8ea49dcaae4d 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -42,9 +42,9 @@ #include #include -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" #include "sdrc.h" #include "pm.h" diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index c45b4fa1deeb..7e500d892804 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -41,11 +41,11 @@ #include -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" #include "prm-regbits-34xx.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "pm.h" #include "sdrc.h" #include "control.h" diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 77f42b96df41..8a0dcd05afeb 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -19,6 +19,9 @@ #include #include #include +#include "cm2xxx_3xxx.h" +#include "cm44xx.h" +#include "prm2xxx_3xxx.h" #include "prm44xx.h" #include diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index 7efdf682d7fd..dae767bf1952 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -18,6 +18,7 @@ #include #include +#include "prm2xxx_3xxx.h" #include "prm44xx.h" #include "prm-regbits-44xx.h" #include "powerdomains.h" diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c index adc85d359289..e136895e0a37 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c @@ -19,10 +19,8 @@ #include "powerdomains.h" #include "prcm-common.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" -#include "cm.h" -#include "cm-regbits-24xx.h" /* 24XX powerdomains and dependencies */ diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 1ddc040d7bc0..1830c63ae676 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -19,9 +19,9 @@ #include "powerdomains.h" #include "prcm-common.h" -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "prm-regbits-34xx.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "cm-regbits-34xx.h" /* diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c index cf6adfcf035f..069a21d54911 100644 --- a/arch/arm/mach-omap2/powerdomains44xx_data.c +++ b/arch/arm/mach-omap2/powerdomains44xx_data.c @@ -26,7 +26,6 @@ #include "powerdomains.h" #include "prcm-common.h" -#include "prm.h" #include "prm-regbits-44xx.h" #include "prm44xx.h" #include "prcm_mpu44xx.h" diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h index 427ab612f0de..87486f559784 100644 --- a/arch/arm/mach-omap2/prcm-common.h +++ b/arch/arm/mach-omap2/prcm-common.h @@ -396,5 +396,11 @@ */ #define MAX_MODULE_HARDRESET_WAIT 10000 +# ifndef __ASSEMBLER__ +extern void __iomem *prm_base; +extern void __iomem *cm_base; +extern void __iomem *cm2_base; +# endif + #endif diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index aac8070fadcd..171c710c8221 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -29,16 +29,17 @@ #include "clock.h" #include "clock2xxx.h" -#include "cm.h" -#include "prm.h" +#include "cm2xxx_3xxx.h" +#include "cm44xx.h" +#include "prm2xxx_3xxx.h" #include "prm44xx.h" #include "prm-regbits-24xx.h" #include "prm-regbits-44xx.h" #include "control.h" -static void __iomem *prm_base; -static void __iomem *cm_base; -static void __iomem *cm2_base; +void __iomem *prm_base; +void __iomem *cm_base; +void __iomem *cm2_base; #define MAX_MODULE_ENABLE_WAIT 100000 @@ -158,56 +159,6 @@ void omap_prcm_arch_reset(char mode, const char *cmd) prcm_offs, OMAP4_RM_RSTCTRL); } -static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) -{ - BUG_ON(!base); - return __raw_readl(base + module + reg); -} - -static inline void __omap_prcm_write(u32 value, void __iomem *base, - s16 module, u16 reg) -{ - BUG_ON(!base); - __raw_writel(value, base + module + reg); -} - -/* Read a register in a PRM module */ -u32 prm_read_mod_reg(s16 module, u16 idx) -{ - return __omap_prcm_read(prm_base, module, idx); -} - -/* Write into a register in a PRM module */ -void prm_write_mod_reg(u32 val, s16 module, u16 idx) -{ - __omap_prcm_write(val, prm_base, module, idx); -} - -/* Read-modify-write a register in a PRM module. Caller must lock */ -u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) -{ - u32 v; - - v = prm_read_mod_reg(module, idx); - v &= ~mask; - v |= bits; - prm_write_mod_reg(v, module, idx); - - return v; -} - -/* Read a PRM register, AND it, and shift the result down to bit 0 */ -u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) -{ - u32 v; - - v = prm_read_mod_reg(domain, idx); - v &= mask; - v >>= __ffs(mask); - - return v; -} - /* Read a PRM register, AND it, and shift the result down to bit 0 */ u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask) { @@ -232,30 +183,6 @@ u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg) return v; } -/* Read a register in a CM module */ -u32 cm_read_mod_reg(s16 module, u16 idx) -{ - return __omap_prcm_read(cm_base, module, idx); -} - -/* Write into a register in a CM module */ -void cm_write_mod_reg(u32 val, s16 module, u16 idx) -{ - __omap_prcm_write(val, cm_base, module, idx); -} - -/* Read-modify-write a register in a CM module. Caller must lock */ -u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) -{ - u32 v; - - v = cm_read_mod_reg(module, idx); - v &= ~mask; - v |= bits; - cm_write_mod_reg(v, module, idx); - - return v; -} /** * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness @@ -266,6 +193,9 @@ u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) * * Returns 1 if the module indicated readiness in time, or 0 if it * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds. + * + * XXX This function is deprecated. It should be removed once the + * hwmod conversion is complete. */ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, const char *name) diff --git a/arch/arm/mach-omap2/prm-regbits-24xx.h b/arch/arm/mach-omap2/prm-regbits-24xx.h index 0b188ffa710e..6ac966103f34 100644 --- a/arch/arm/mach-omap2/prm-regbits-24xx.h +++ b/arch/arm/mach-omap2/prm-regbits-24xx.h @@ -14,7 +14,7 @@ * published by the Free Software Foundation. */ -#include "prm.h" +#include "prm2xxx_3xxx.h" /* Bits shared between registers */ diff --git a/arch/arm/mach-omap2/prm-regbits-34xx.h b/arch/arm/mach-omap2/prm-regbits-34xx.h index ec1a710db9ce..64c087af6a8b 100644 --- a/arch/arm/mach-omap2/prm-regbits-34xx.h +++ b/arch/arm/mach-omap2/prm-regbits-34xx.h @@ -1,6 +1,3 @@ -#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H -#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H - /* * OMAP3430 Power/Reset Management register bits * @@ -13,8 +10,11 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H +#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_34XX_H + -#include "prm.h" +#include "prm2xxx_3xxx.h" /* Shared register bits */ diff --git a/arch/arm/mach-omap2/prm-regbits-44xx.h b/arch/arm/mach-omap2/prm-regbits-44xx.h index 25b19b610177..6d2776f6fc08 100644 --- a/arch/arm/mach-omap2/prm-regbits-44xx.h +++ b/arch/arm/mach-omap2/prm-regbits-44xx.h @@ -22,8 +22,6 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H #define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_44XX_H -#include "prm.h" - /* * Used by PRM_LDO_SRAM_CORE_SETUP, PRM_LDO_SRAM_IVA_SETUP, diff --git a/arch/arm/mach-omap2/prm.h b/arch/arm/mach-omap2/prm.h index 10a24ca3f400..39d562169d18 100644 --- a/arch/arm/mach-omap2/prm.h +++ b/arch/arm/mach-omap2/prm.h @@ -1,304 +1,20 @@ -#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H -#define __ARCH_ARM_MACH_OMAP2_PRM_H - /* - * OMAP2/3 Power/Reset Management (PRM) register definitions + * OMAP2/3/4 Power/Reset Management (PRM) bitfield definitions * * Copyright (C) 2007-2009 Texas Instruments, Inc. * Copyright (C) 2010 Nokia Corporation * - * Written by Paul Walmsley + * Paul Walmsley * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ +#ifndef __ARCH_ARM_MACH_OMAP2_PRM_H +#define __ARCH_ARM_MACH_OMAP2_PRM_H #include "prcm-common.h" -#define OMAP2420_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) -#define OMAP2430_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) -#define OMAP34XX_PRM_REGADDR(module, reg) \ - OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) - -/* - * Architecture-specific global PRM registers - * Use __raw_{read,write}l() with these registers. - * - * With a few exceptions, these are the register names beginning with - * PRCM_* on 24xx, and PRM_* on 34xx. (The exceptions are the - * IRQSTATUS and IRQENABLE bits.) - * - */ - -#define OMAP2_PRCM_REVISION_OFFSET 0x0000 -#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) -#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 -#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) - -#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 -#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c -#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) - -#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 -#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) -#define OMAP2_PRCM_VOLTST_OFFSET 0x0054 -#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) -#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 -#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) -#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) -#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 -#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) -#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 -#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) -#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 -#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) -#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 -#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) -#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 -#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) -#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 -#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) - -#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) -#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) - -#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) - -#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) -#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) -#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) -#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) -#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) -#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) -#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) -#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) -#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) -#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) - -#define OMAP3_PRM_REVISION_OFFSET 0x0004 -#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) -#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 -#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) - -#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 -#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) -#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c -#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) - - -#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 -#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) -#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 -#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) -#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 -#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) -#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c -#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) -#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 -#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) -#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 -#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) -#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 -#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) -#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c -#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) -#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 -#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) -#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 -#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) -#define OMAP3_PRM_RSTST_OFFSET 0x0058 -#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) -#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 -#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) -#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 -#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) -#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 -#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) -#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 -#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) -#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 -#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) -#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 -#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) -#define OMAP3_PRM_POLCTRL_OFFSET 0x009c -#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) -#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 -#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) -#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 -#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) -#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 -#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) -#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 -#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) -#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc -#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) -#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 -#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) -#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 -#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) -#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 -#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) -#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 -#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) -#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 -#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) -#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc -#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) -#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 -#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) -#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 -#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) - -#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 -#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) -#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 -#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) - -/* - * Module specific PRM registers from PRM_BASE + domain offset - * - * Use prm_{read,write}_mod_reg() with these registers. - * - * With a few exceptions, these are the register names beginning with - * {PM,RM}_* on both architectures. (The exceptions are the IRQSTATUS - * and IRQENABLE bits.) - * - */ - -/* Registers appearing on both 24xx and 34xx */ - -#define OMAP2_RM_RSTCTRL 0x0050 -#define OMAP2_RM_RSTTIME 0x0054 -#define OMAP2_RM_RSTST 0x0058 -#define OMAP2_PM_PWSTCTRL 0x00e0 -#define OMAP2_PM_PWSTST 0x00e4 - -#define PM_WKEN 0x00a0 -#define PM_WKEN1 PM_WKEN -#define PM_WKST 0x00b0 -#define PM_WKST1 PM_WKST -#define PM_WKDEP 0x00c8 -#define PM_EVGENCTRL 0x00d4 -#define PM_EVGENONTIM 0x00d8 -#define PM_EVGENOFFTIM 0x00dc - -/* Omap2 specific registers */ -#define OMAP24XX_PM_WKEN2 0x00a4 -#define OMAP24XX_PM_WKST2 0x00b4 - -#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ -#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ -#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 -#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc - -/* Omap3 specific registers */ -#define OMAP3430ES2_PM_WKEN3 0x00f0 -#define OMAP3430ES2_PM_WKST3 0x00b8 - -#define OMAP3430_PM_MPUGRPSEL 0x00a4 -#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL -#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 - -#define OMAP3430_PM_IVAGRPSEL 0x00a8 -#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL -#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 - -#define OMAP3430_PM_PREPWSTST 0x00e8 - -#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 -#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc - - -#ifndef __ASSEMBLER__ - -/* Power/reset management domain register get/set */ -extern u32 prm_read_mod_reg(s16 module, u16 idx); -extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); -extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); - -/* Read-modify-write bits in a PRM register (by domain) */ -static inline u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return prm_rmw_mod_reg_bits(bits, bits, module, idx); -} - -static inline u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) -{ - return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); -} - -/* These omap2_ PRM functions apply to both OMAP2 and 3 */ -int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); -int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); -int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); - -#endif - -/* - * Bits common to specific registers - * - * The 3430 register and bit names are generally used, - * since they tend to make more sense - */ - -/* PM_EVGENONTIM_MPU */ -/* Named PM_EVEGENONTIM_MPU on the 24XX */ -#define OMAP_ONTIMEVAL_SHIFT 0 -#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) - -/* PM_EVGENOFFTIM_MPU */ -/* Named PM_EVEGENOFFTIM_MPU on the 24XX */ -#define OMAP_OFFTIMEVAL_SHIFT 0 -#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) - -/* PRM_CLKSETUP and PRCM_VOLTSETUP */ -/* Named PRCM_CLKSSETUP on the 24XX */ -#define OMAP_SETUP_TIME_SHIFT 0 -#define OMAP_SETUP_TIME_MASK (0xffff << 0) - -/* PRM_CLKSRC_CTRL */ -/* Named PRCM_CLKSRC_CTRL on the 24XX */ -#define OMAP_SYSCLKDIV_SHIFT 6 -#define OMAP_SYSCLKDIV_MASK (0x3 << 6) -#define OMAP_AUTOEXTCLKMODE_SHIFT 3 -#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) -#define OMAP_SYSCLKSEL_SHIFT 0 -#define OMAP_SYSCLKSEL_MASK (0x3 << 0) - -/* PM_EVGENCTRL_MPU */ -#define OMAP_OFFLOADMODE_SHIFT 3 -#define OMAP_OFFLOADMODE_MASK (0x3 << 3) -#define OMAP_ONLOADMODE_SHIFT 1 -#define OMAP_ONLOADMODE_MASK (0x3 << 1) -#define OMAP_ENABLE_MASK (1 << 0) - -/* PRM_RSTTIME */ -/* Named RM_RSTTIME_WKUP on the 24xx */ -#define OMAP_RSTTIME2_SHIFT 8 -#define OMAP_RSTTIME2_MASK (0x1f << 8) -#define OMAP_RSTTIME1_SHIFT 0 -#define OMAP_RSTTIME1_MASK (0xff << 0) - -/* PRM_RSTCTRL */ -/* Named RM_RSTCTRL_WKUP on the 24xx */ -/* 2420 calls RST_DPLL3 'RST_DPLL' */ -#define OMAP_RST_DPLL3_MASK (1 << 2) -#define OMAP_RST_GS_MASK (1 << 1) - - -/* - * Bits common to module-shared registers - * - * Not all registers of a particular type support all of these bits - - * check TRM if you are unsure - */ - /* * 24XX: PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP * @@ -323,59 +39,6 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); #define OMAP_POWERSTATEST_SHIFT 0 #define OMAP_POWERSTATEST_MASK (0x3 << 0) -/* - * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is - * called 'COREWKUP_RST' - * - * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, - * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON - */ -#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) - -/* - * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP - * - * 2430: RM_RSTST_MDM - * - * 3430: RM_RSTST_CORE, RM_RSTST_EMU - */ -#define OMAP_DOMAINWKUP_RST_MASK (1 << 2) - -/* - * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP - * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. - * - * 2430: RM_RSTST_MDM - * - * 3430: RM_RSTST_CORE, RM_RSTST_EMU - */ -#define OMAP_GLOBALWARM_RST_MASK (1 << 1) -#define OMAP_GLOBALCOLD_RST_MASK (1 << 0) - -/* - * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP - * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" - * - * 2430: PM_WKDEP_MDM - * - * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, - * PM_WKDEP_PER - */ -#define OMAP_EN_WKUP_SHIFT 4 -#define OMAP_EN_WKUP_MASK (1 << 4) - -/* - * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, - * PM_PWSTCTRL_DSP - * - * 2430: PM_PWSTCTRL_MDM - * - * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, - * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, - * PM_PWSTCTRL_NEON - */ -#define OMAP_LOGICRETSTATE_MASK (1 << 2) - /* * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, * PM_PWSTCTRL_DSP, PM_PWSTST_MPU @@ -390,11 +53,4 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); #define OMAP_POWERSTATE_MASK (0x3 << 0) -/* - * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP - * submodule to exit hardreset - */ -#define MAX_MODULE_HARDRESET_WAIT 10000 - - #endif diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 421771eee450..064b52a3e202 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -12,18 +12,65 @@ */ #include -#include #include #include +#include #include #include #include -#include "prm.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" #include "prm-regbits-24xx.h" #include "prm-regbits-34xx.h" +u32 prm_read_mod_reg(s16 module, u16 idx) +{ + return __raw_readl(prm_base + module + idx); +} + +void prm_write_mod_reg(u32 val, s16 module, u16 idx) +{ + __raw_writel(val, prm_base + module + idx); +} + +/* Read-modify-write a register in a PRM module. Caller must lock */ +u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +{ + u32 v; + + v = prm_read_mod_reg(module, idx); + v &= ~mask; + v |= bits; + prm_write_mod_reg(v, module, idx); + + return v; +} + +/* Read a PRM register, AND it, and shift the result down to bit 0 */ +u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) +{ + u32 v; + + v = prm_read_mod_reg(domain, idx); + v &= mask; + v >>= __ffs(mask); + + return v; +} + +u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return prm_rmw_mod_reg_bits(bits, bits, module, idx); +} + +u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +{ + return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); +} + + /** * omap2_prm_is_hardreset_asserted - read the HW reset line state of * submodules contained in the hwmod module diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h new file mode 100644 index 000000000000..ab28517c82ce --- /dev/null +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -0,0 +1,367 @@ +/* + * OMAP2/3 Power/Reset Management (PRM) register definitions + * + * Copyright (C) 2007-2009 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * The PRM hardware modules on the OMAP2/3 are quite similar to each + * other. The PRM on OMAP4 has a new register layout, and is handled + * in a separate file. + */ +#ifndef __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H +#define __ARCH_ARM_MACH_OMAP2_PRM2XXX_3XXX_H + +#include "prcm-common.h" +#include "prm.h" + +#define OMAP2420_PRM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg)) +#define OMAP2430_PRM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg)) +#define OMAP34XX_PRM_REGADDR(module, reg) \ + OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg)) + + +/* + * OMAP2-specific global PRM registers + * Use __raw_{read,write}l() with these registers. + * + * With a few exceptions, these are the register names beginning with + * PRCM_* on 24xx. (The exceptions are the IRQSTATUS and IRQENABLE + * bits.) + * + */ + +#define OMAP2_PRCM_REVISION_OFFSET 0x0000 +#define OMAP2420_PRCM_REVISION OMAP2420_PRM_REGADDR(OCP_MOD, 0x0000) +#define OMAP2_PRCM_SYSCONFIG_OFFSET 0x0010 +#define OMAP2420_PRCM_SYSCONFIG OMAP2420_PRM_REGADDR(OCP_MOD, 0x0010) + +#define OMAP2_PRCM_IRQSTATUS_MPU_OFFSET 0x0018 +#define OMAP2420_PRCM_IRQSTATUS_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP2_PRCM_IRQENABLE_MPU_OFFSET 0x001c +#define OMAP2420_PRCM_IRQENABLE_MPU OMAP2420_PRM_REGADDR(OCP_MOD, 0x001c) + +#define OMAP2_PRCM_VOLTCTRL_OFFSET 0x0050 +#define OMAP2420_PRCM_VOLTCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0050) +#define OMAP2_PRCM_VOLTST_OFFSET 0x0054 +#define OMAP2420_PRCM_VOLTST OMAP2420_PRM_REGADDR(OCP_MOD, 0x0054) +#define OMAP2_PRCM_CLKSRC_CTRL_OFFSET 0x0060 +#define OMAP2420_PRCM_CLKSRC_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0060) +#define OMAP2_PRCM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP2420_PRCM_CLKOUT_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0070) +#define OMAP2_PRCM_CLKEMUL_CTRL_OFFSET 0x0078 +#define OMAP2420_PRCM_CLKEMUL_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0078) +#define OMAP2_PRCM_CLKCFG_CTRL_OFFSET 0x0080 +#define OMAP2420_PRCM_CLKCFG_CTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0080) +#define OMAP2_PRCM_CLKCFG_STATUS_OFFSET 0x0084 +#define OMAP2420_PRCM_CLKCFG_STATUS OMAP2420_PRM_REGADDR(OCP_MOD, 0x0084) +#define OMAP2_PRCM_VOLTSETUP_OFFSET 0x0090 +#define OMAP2420_PRCM_VOLTSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0090) +#define OMAP2_PRCM_CLKSSETUP_OFFSET 0x0094 +#define OMAP2420_PRCM_CLKSSETUP OMAP2420_PRM_REGADDR(OCP_MOD, 0x0094) +#define OMAP2_PRCM_POLCTRL_OFFSET 0x0098 +#define OMAP2420_PRCM_POLCTRL OMAP2420_PRM_REGADDR(OCP_MOD, 0x0098) + +#define OMAP2430_PRCM_REVISION OMAP2430_PRM_REGADDR(OCP_MOD, 0x0000) +#define OMAP2430_PRCM_SYSCONFIG OMAP2430_PRM_REGADDR(OCP_MOD, 0x0010) + +#define OMAP2430_PRCM_IRQSTATUS_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP2430_PRCM_IRQENABLE_MPU OMAP2430_PRM_REGADDR(OCP_MOD, 0x001c) + +#define OMAP2430_PRCM_VOLTCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0050) +#define OMAP2430_PRCM_VOLTST OMAP2430_PRM_REGADDR(OCP_MOD, 0x0054) +#define OMAP2430_PRCM_CLKSRC_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0060) +#define OMAP2430_PRCM_CLKOUT_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0070) +#define OMAP2430_PRCM_CLKEMUL_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0078) +#define OMAP2430_PRCM_CLKCFG_CTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0080) +#define OMAP2430_PRCM_CLKCFG_STATUS OMAP2430_PRM_REGADDR(OCP_MOD, 0x0084) +#define OMAP2430_PRCM_VOLTSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0090) +#define OMAP2430_PRCM_CLKSSETUP OMAP2430_PRM_REGADDR(OCP_MOD, 0x0094) +#define OMAP2430_PRCM_POLCTRL OMAP2430_PRM_REGADDR(OCP_MOD, 0x0098) + +/* + * OMAP3-specific global PRM registers + * Use __raw_{read,write}l() with these registers. + * + * With a few exceptions, these are the register names beginning with + * PRM_* on 34xx. (The exceptions are the IRQSTATUS and IRQENABLE + * bits.) + */ + +#define OMAP3_PRM_REVISION_OFFSET 0x0004 +#define OMAP3430_PRM_REVISION OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0004) +#define OMAP3_PRM_SYSCONFIG_OFFSET 0x0014 +#define OMAP3430_PRM_SYSCONFIG OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0014) + +#define OMAP3_PRM_IRQSTATUS_MPU_OFFSET 0x0018 +#define OMAP3430_PRM_IRQSTATUS_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x0018) +#define OMAP3_PRM_IRQENABLE_MPU_OFFSET 0x001c +#define OMAP3430_PRM_IRQENABLE_MPU OMAP34XX_PRM_REGADDR(OCP_MOD, 0x001c) + + +#define OMAP3_PRM_VC_SMPS_SA_OFFSET 0x0020 +#define OMAP3430_PRM_VC_SMPS_SA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0020) +#define OMAP3_PRM_VC_SMPS_VOL_RA_OFFSET 0x0024 +#define OMAP3430_PRM_VC_SMPS_VOL_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0024) +#define OMAP3_PRM_VC_SMPS_CMD_RA_OFFSET 0x0028 +#define OMAP3430_PRM_VC_SMPS_CMD_RA OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0028) +#define OMAP3_PRM_VC_CMD_VAL_0_OFFSET 0x002c +#define OMAP3430_PRM_VC_CMD_VAL_0 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x002c) +#define OMAP3_PRM_VC_CMD_VAL_1_OFFSET 0x0030 +#define OMAP3430_PRM_VC_CMD_VAL_1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0030) +#define OMAP3_PRM_VC_CH_CONF_OFFSET 0x0034 +#define OMAP3430_PRM_VC_CH_CONF OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0034) +#define OMAP3_PRM_VC_I2C_CFG_OFFSET 0x0038 +#define OMAP3430_PRM_VC_I2C_CFG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0038) +#define OMAP3_PRM_VC_BYPASS_VAL_OFFSET 0x003c +#define OMAP3430_PRM_VC_BYPASS_VAL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x003c) +#define OMAP3_PRM_RSTCTRL_OFFSET 0x0050 +#define OMAP3430_PRM_RSTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0050) +#define OMAP3_PRM_RSTTIME_OFFSET 0x0054 +#define OMAP3430_PRM_RSTTIME OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0054) +#define OMAP3_PRM_RSTST_OFFSET 0x0058 +#define OMAP3430_PRM_RSTST OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0058) +#define OMAP3_PRM_VOLTCTRL_OFFSET 0x0060 +#define OMAP3430_PRM_VOLTCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0060) +#define OMAP3_PRM_SRAM_PCHARGE_OFFSET 0x0064 +#define OMAP3430_PRM_SRAM_PCHARGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0064) +#define OMAP3_PRM_CLKSRC_CTRL_OFFSET 0x0070 +#define OMAP3430_PRM_CLKSRC_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0070) +#define OMAP3_PRM_VOLTSETUP1_OFFSET 0x0090 +#define OMAP3430_PRM_VOLTSETUP1 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0090) +#define OMAP3_PRM_VOLTOFFSET_OFFSET 0x0094 +#define OMAP3430_PRM_VOLTOFFSET OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0094) +#define OMAP3_PRM_CLKSETUP_OFFSET 0x0098 +#define OMAP3430_PRM_CLKSETUP OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x0098) +#define OMAP3_PRM_POLCTRL_OFFSET 0x009c +#define OMAP3430_PRM_POLCTRL OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x009c) +#define OMAP3_PRM_VOLTSETUP2_OFFSET 0x00a0 +#define OMAP3430_PRM_VOLTSETUP2 OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00a0) +#define OMAP3_PRM_VP1_CONFIG_OFFSET 0x00b0 +#define OMAP3430_PRM_VP1_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b0) +#define OMAP3_PRM_VP1_VSTEPMIN_OFFSET 0x00b4 +#define OMAP3430_PRM_VP1_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b4) +#define OMAP3_PRM_VP1_VSTEPMAX_OFFSET 0x00b8 +#define OMAP3430_PRM_VP1_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00b8) +#define OMAP3_PRM_VP1_VLIMITTO_OFFSET 0x00bc +#define OMAP3430_PRM_VP1_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00bc) +#define OMAP3_PRM_VP1_VOLTAGE_OFFSET 0x00c0 +#define OMAP3430_PRM_VP1_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c0) +#define OMAP3_PRM_VP1_STATUS_OFFSET 0x00c4 +#define OMAP3430_PRM_VP1_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00c4) +#define OMAP3_PRM_VP2_CONFIG_OFFSET 0x00d0 +#define OMAP3430_PRM_VP2_CONFIG OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d0) +#define OMAP3_PRM_VP2_VSTEPMIN_OFFSET 0x00d4 +#define OMAP3430_PRM_VP2_VSTEPMIN OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d4) +#define OMAP3_PRM_VP2_VSTEPMAX_OFFSET 0x00d8 +#define OMAP3430_PRM_VP2_VSTEPMAX OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00d8) +#define OMAP3_PRM_VP2_VLIMITTO_OFFSET 0x00dc +#define OMAP3430_PRM_VP2_VLIMITTO OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00dc) +#define OMAP3_PRM_VP2_VOLTAGE_OFFSET 0x00e0 +#define OMAP3430_PRM_VP2_VOLTAGE OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e0) +#define OMAP3_PRM_VP2_STATUS_OFFSET 0x00e4 +#define OMAP3430_PRM_VP2_STATUS OMAP34XX_PRM_REGADDR(OMAP3430_GR_MOD, 0x00e4) + +#define OMAP3_PRM_CLKSEL_OFFSET 0x0040 +#define OMAP3430_PRM_CLKSEL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0040) +#define OMAP3_PRM_CLKOUT_CTRL_OFFSET 0x0070 +#define OMAP3430_PRM_CLKOUT_CTRL OMAP34XX_PRM_REGADDR(OMAP3430_CCR_MOD, 0x0070) + +/* + * Module specific PRM register offsets from PRM_BASE + domain offset + * + * Use prm_{read,write}_mod_reg() with these registers. + * + * With a few exceptions, these are the register names beginning with + * {PM,RM}_* on both OMAP2/3 SoC families.. (The exceptions are the + * IRQSTATUS and IRQENABLE bits.) + */ + +/* Register offsets appearing on both OMAP2 and OMAP3 */ + +#define OMAP2_RM_RSTCTRL 0x0050 +#define OMAP2_RM_RSTTIME 0x0054 +#define OMAP2_RM_RSTST 0x0058 +#define OMAP2_PM_PWSTCTRL 0x00e0 +#define OMAP2_PM_PWSTST 0x00e4 + +#define PM_WKEN 0x00a0 +#define PM_WKEN1 PM_WKEN +#define PM_WKST 0x00b0 +#define PM_WKST1 PM_WKST +#define PM_WKDEP 0x00c8 +#define PM_EVGENCTRL 0x00d4 +#define PM_EVGENONTIM 0x00d8 +#define PM_EVGENOFFTIM 0x00dc + +/* OMAP2xxx specific register offsets */ +#define OMAP24XX_PM_WKEN2 0x00a4 +#define OMAP24XX_PM_WKST2 0x00b4 + +#define OMAP24XX_PRCM_IRQSTATUS_DSP 0x00f0 /* IVA mod */ +#define OMAP24XX_PRCM_IRQENABLE_DSP 0x00f4 /* IVA mod */ +#define OMAP24XX_PRCM_IRQSTATUS_IVA 0x00f8 +#define OMAP24XX_PRCM_IRQENABLE_IVA 0x00fc + +/* OMAP3 specific register offsets */ +#define OMAP3430ES2_PM_WKEN3 0x00f0 +#define OMAP3430ES2_PM_WKST3 0x00b8 + +#define OMAP3430_PM_MPUGRPSEL 0x00a4 +#define OMAP3430_PM_MPUGRPSEL1 OMAP3430_PM_MPUGRPSEL +#define OMAP3430ES2_PM_MPUGRPSEL3 0x00f8 + +#define OMAP3430_PM_IVAGRPSEL 0x00a8 +#define OMAP3430_PM_IVAGRPSEL1 OMAP3430_PM_IVAGRPSEL +#define OMAP3430ES2_PM_IVAGRPSEL3 0x00f4 + +#define OMAP3430_PM_PREPWSTST 0x00e8 + +#define OMAP3430_PRM_IRQSTATUS_IVA2 0x00f8 +#define OMAP3430_PRM_IRQENABLE_IVA2 0x00fc + + +#ifndef __ASSEMBLER__ + +/* Power/reset management domain register get/set */ +extern u32 prm_read_mod_reg(s16 module, u16 idx); +extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); +extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +extern u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); + +/* These omap2_ PRM functions apply to both OMAP2 and 3 */ +extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); +extern int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift); +extern int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift); + +#endif + +/* + * Bits common to specific registers + * + * The 3430 register and bit names are generally used, + * since they tend to make more sense + */ + +/* PM_EVGENONTIM_MPU */ +/* Named PM_EVEGENONTIM_MPU on the 24XX */ +#define OMAP_ONTIMEVAL_SHIFT 0 +#define OMAP_ONTIMEVAL_MASK (0xffffffff << 0) + +/* PM_EVGENOFFTIM_MPU */ +/* Named PM_EVEGENOFFTIM_MPU on the 24XX */ +#define OMAP_OFFTIMEVAL_SHIFT 0 +#define OMAP_OFFTIMEVAL_MASK (0xffffffff << 0) + +/* PRM_CLKSETUP and PRCM_VOLTSETUP */ +/* Named PRCM_CLKSSETUP on the 24XX */ +#define OMAP_SETUP_TIME_SHIFT 0 +#define OMAP_SETUP_TIME_MASK (0xffff << 0) + +/* PRM_CLKSRC_CTRL */ +/* Named PRCM_CLKSRC_CTRL on the 24XX */ +#define OMAP_SYSCLKDIV_SHIFT 6 +#define OMAP_SYSCLKDIV_MASK (0x3 << 6) +#define OMAP_AUTOEXTCLKMODE_SHIFT 3 +#define OMAP_AUTOEXTCLKMODE_MASK (0x3 << 3) +#define OMAP_SYSCLKSEL_SHIFT 0 +#define OMAP_SYSCLKSEL_MASK (0x3 << 0) + +/* PM_EVGENCTRL_MPU */ +#define OMAP_OFFLOADMODE_SHIFT 3 +#define OMAP_OFFLOADMODE_MASK (0x3 << 3) +#define OMAP_ONLOADMODE_SHIFT 1 +#define OMAP_ONLOADMODE_MASK (0x3 << 1) +#define OMAP_ENABLE_MASK (1 << 0) + +/* PRM_RSTTIME */ +/* Named RM_RSTTIME_WKUP on the 24xx */ +#define OMAP_RSTTIME2_SHIFT 8 +#define OMAP_RSTTIME2_MASK (0x1f << 8) +#define OMAP_RSTTIME1_SHIFT 0 +#define OMAP_RSTTIME1_MASK (0xff << 0) + +/* PRM_RSTCTRL */ +/* Named RM_RSTCTRL_WKUP on the 24xx */ +/* 2420 calls RST_DPLL3 'RST_DPLL' */ +#define OMAP_RST_DPLL3_MASK (1 << 2) +#define OMAP_RST_GS_MASK (1 << 1) + + +/* + * Bits common to module-shared registers + * + * Not all registers of a particular type support all of these bits - + * check TRM if you are unsure + */ + +/* + * 24XX: RM_RSTST_MPU and RM_RSTST_DSP - on 24XX, 'COREDOMAINWKUP_RST' is + * called 'COREWKUP_RST' + * + * 3430: RM_RSTST_IVA2, RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSS, + * RM_RSTST_CAM, RM_RSTST_PER, RM_RSTST_NEON + */ +#define OMAP_COREDOMAINWKUP_RST_MASK (1 << 3) + +/* + * 24XX: RM_RSTST_MPU, RM_RSTST_GFX, RM_RSTST_DSP + * + * 2430: RM_RSTST_MDM + * + * 3430: RM_RSTST_CORE, RM_RSTST_EMU + */ +#define OMAP_DOMAINWKUP_RST_MASK (1 << 2) + +/* + * 24XX: RM_RSTST_MPU, RM_RSTST_WKUP, RM_RSTST_DSP + * On 24XX, 'GLOBALWARM_RST' is called 'GLOBALWMPU_RST'. + * + * 2430: RM_RSTST_MDM + * + * 3430: RM_RSTST_CORE, RM_RSTST_EMU + */ +#define OMAP_GLOBALWARM_RST_MASK (1 << 1) +#define OMAP_GLOBALCOLD_RST_MASK (1 << 0) + +/* + * 24XX: PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_CORE, PM_WKDEP_DSP + * 2420 TRM sometimes uses "EN_WAKEUP" instead of "EN_WKUP" + * + * 2430: PM_WKDEP_MDM + * + * 3430: PM_WKDEP_IVA2, PM_WKDEP_GFX, PM_WKDEP_DSS, PM_WKDEP_CAM, + * PM_WKDEP_PER + */ +#define OMAP_EN_WKUP_SHIFT 4 +#define OMAP_EN_WKUP_MASK (1 << 4) + +/* + * 24XX: PM_PWSTCTRL_MPU, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, + * PM_PWSTCTRL_DSP + * + * 2430: PM_PWSTCTRL_MDM + * + * 3430: PM_PWSTCTRL_IVA2, PM_PWSTCTRL_CORE, PM_PWSTCTRL_GFX, + * PM_PWSTCTRL_DSS, PM_PWSTCTRL_CAM, PM_PWSTCTRL_PER, + * PM_PWSTCTRL_NEON + */ +#define OMAP_LOGICRETSTATE_MASK (1 << 2) + + +/* + * MAX_MODULE_HARDRESET_WAIT: Maximum microseconds to wait for an OMAP + * submodule to exit hardreset + */ +#define MAX_MODULE_HARDRESET_WAIT 10000 + + +#endif diff --git a/arch/arm/mach-omap2/prm44xx.h b/arch/arm/mach-omap2/prm44xx.h index 0d444a5c939c..3d361497ca70 100644 --- a/arch/arm/mach-omap2/prm44xx.h +++ b/arch/arm/mach-omap2/prm44xx.h @@ -26,6 +26,7 @@ #define __ARCH_ARM_MACH_OMAP2_PRM44XX_H #include "prcm-common.h" +#include "prm.h" #define OMAP4430_PRM_BASE 0x4a306000 diff --git a/arch/arm/mach-omap2/sdrc.c b/arch/arm/mach-omap2/sdrc.c index 4c65f5628b39..da6f3a63b5d5 100644 --- a/arch/arm/mach-omap2/sdrc.c +++ b/arch/arm/mach-omap2/sdrc.c @@ -27,8 +27,6 @@ #include #include -#include "prm.h" - #include #include "sdrc.h" diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 0f4d27aef44d..64778b6240c1 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -28,7 +28,7 @@ #include #include -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "clock.h" #include #include "sdrc.h" diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 0548bbd43407..26770d80419e 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -40,9 +40,9 @@ #include #include -#include "prm.h" +#include "prm2xxx_3xxx.h" #include "pm.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" #include "prm-regbits-34xx.h" #include "control.h" diff --git a/arch/arm/mach-omap2/sleep34xx.S b/arch/arm/mach-omap2/sleep34xx.S index e3b5cd76c54c..98d8232808b8 100644 --- a/arch/arm/mach-omap2/sleep34xx.S +++ b/arch/arm/mach-omap2/sleep34xx.S @@ -27,8 +27,8 @@ #include #include -#include "cm.h" -#include "prm.h" +#include "cm2xxx_3xxx.h" +#include "prm2xxx_3xxx.h" #include "sdrc.h" #include "control.h" diff --git a/arch/arm/mach-omap2/sram242x.S b/arch/arm/mach-omap2/sram242x.S index 92e6e1a12af8..8e7e6fef09ef 100644 --- a/arch/arm/mach-omap2/sram242x.S +++ b/arch/arm/mach-omap2/sram242x.S @@ -27,8 +27,8 @@ #include #include -#include "prm.h" -#include "cm.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" #include "sdrc.h" .text diff --git a/arch/arm/mach-omap2/sram243x.S b/arch/arm/mach-omap2/sram243x.S index ab4973695c71..9ea87f68524f 100644 --- a/arch/arm/mach-omap2/sram243x.S +++ b/arch/arm/mach-omap2/sram243x.S @@ -27,8 +27,8 @@ #include #include -#include "prm.h" -#include "cm.h" +#include "prm2xxx_3xxx.h" +#include "cm2xxx_3xxx.h" #include "sdrc.h" .text diff --git a/arch/arm/mach-omap2/sram34xx.S b/arch/arm/mach-omap2/sram34xx.S index 3637274af5be..b7aba60f8325 100644 --- a/arch/arm/mach-omap2/sram34xx.S +++ b/arch/arm/mach-omap2/sram34xx.S @@ -32,7 +32,7 @@ #include #include "sdrc.h" -#include "cm.h" +#include "cm2xxx_3xxx.h" .text diff --git a/arch/arm/plat-omap/include/plat/common.h b/arch/arm/plat-omap/include/plat/common.h index a9d69a09920d..6b8088ec74af 100644 --- a/arch/arm/plat-omap/include/plat/common.h +++ b/arch/arm/plat-omap/include/plat/common.h @@ -27,6 +27,8 @@ #ifndef __ARCH_ARM_MACH_OMAP_COMMON_H #define __ARCH_ARM_MACH_OMAP_COMMON_H +#include + #include struct sys_timer; diff --git a/arch/arm/plat-omap/include/plat/prcm.h b/arch/arm/plat-omap/include/plat/prcm.h index ab77442e42ab..3769fc6eca29 100644 --- a/arch/arm/plat-omap/include/plat/prcm.h +++ b/arch/arm/plat-omap/include/plat/prcm.h @@ -34,15 +34,8 @@ int omap2_cm_wait_idlest(void __iomem *reg, u32 mask, u8 idlest, void omap3_prcm_save_context(void); void omap3_prcm_restore_context(void); -u32 prm_read_mod_reg(s16 module, u16 idx); -void prm_write_mod_reg(u32 val, s16 module, u16 idx); -u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); -u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); u32 omap4_prm_read_bits_shift(void __iomem *reg, u32 mask); u32 omap4_prm_rmw_reg_bits(u32 mask, u32 bits, void __iomem *reg); -u32 cm_read_mod_reg(s16 module, u16 idx); -void cm_write_mod_reg(u32 val, s16 module, u16 idx); -u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); #endif diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index fdecd339d4f8..95449b90074d 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -28,6 +28,8 @@ #include #include +/* XXX These "sideways" includes are a sign that something is wrong */ +#include "../mach-omap2/cm2xxx_3xxx.h" #include "../mach-omap2/cm-regbits-34xx.h" struct omap_mcbsp **mcbsp_ptr; diff --git a/arch/arm/plat-omap/sram.c b/arch/arm/plat-omap/sram.c index 1a686c89d8dd..e26e50487d60 100644 --- a/arch/arm/plat-omap/sram.c +++ b/arch/arm/plat-omap/sram.c @@ -33,9 +33,10 @@ #include "sram.h" #include "fb.h" + +/* XXX These "sideways" includes are a sign that something is wrong */ #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) -# include "../mach-omap2/prm.h" -# include "../mach-omap2/cm.h" +# include "../mach-omap2/prm2xxx_3xxx.h" # include "../mach-omap2/sdrc.h" #endif diff --git a/drivers/staging/tidspbridge/core/_tiomap.h b/drivers/staging/tidspbridge/core/_tiomap.h index 1c1f157e167a..7fac488f7f48 100644 --- a/drivers/staging/tidspbridge/core/_tiomap.h +++ b/drivers/staging/tidspbridge/core/_tiomap.h @@ -21,6 +21,12 @@ #include #include +/* + * XXX These mach-omap2/ includes are wrong and should be removed. No + * driver should read or write to PRM/CM registers directly; they + * should rely on OMAP core code to do this. + */ +#include #include #include #include -- cgit From c4d7e58fb52c632d8e33cd23a4917d7a7f8302ac Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 21:05:14 -0700 Subject: OMAP2/3: PRM/CM: prefix OMAP2 PRM/CM functions with "omap2_" Now that OMAP4-specific PRCM functions have been added, distinguish the existing OMAP2/3-specific PRCM functions by prefixing them with "omap2_". This patch should not result in any functional change. Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Jarkko Nikula Cc: Peter Ujfalusi Cc: Liam Girdwood Cc: Mark Brown Tested-by: Santosh Shilimkar Tested-by: Rajendra Nayak --- arch/arm/mach-omap2/clkt2xxx_apll.c | 10 +- arch/arm/mach-omap2/clkt2xxx_dpllcore.c | 8 +- arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 12 +- arch/arm/mach-omap2/clockdomain.c | 22 +- arch/arm/mach-omap2/cm2xxx_3xxx.c | 352 ++++++++++++++------------- arch/arm/mach-omap2/cm2xxx_3xxx.h | 10 +- arch/arm/mach-omap2/control.c | 40 +-- arch/arm/mach-omap2/dsp.c | 12 +- arch/arm/mach-omap2/pm-debug.c | 8 +- arch/arm/mach-omap2/pm24xx.c | 194 +++++++-------- arch/arm/mach-omap2/pm34xx.c | 143 +++++------ arch/arm/mach-omap2/powerdomain2xxx_3xxx.c | 66 ++--- arch/arm/mach-omap2/powerdomain44xx.c | 33 +-- arch/arm/mach-omap2/prcm.c | 16 +- arch/arm/mach-omap2/prm2xxx_3xxx.c | 34 +-- arch/arm/mach-omap2/prm2xxx_3xxx.h | 12 +- arch/arm/mach-omap2/sdrc2xxx.c | 4 + arch/arm/mach-omap2/serial.c | 1 + arch/arm/plat-omap/mcbsp.c | 8 +- 19 files changed, 507 insertions(+), 478 deletions(-) (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c index 954d11f37542..f51cffd1fc53 100644 --- a/arch/arm/mach-omap2/clkt2xxx_apll.c +++ b/arch/arm/mach-omap2/clkt2xxx_apll.c @@ -49,14 +49,14 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask) apll_mask = EN_APLL_LOCKED << clk->enable_bit; - cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); if ((cval & apll_mask) == apll_mask) return 0; /* apll already enabled */ cval &= ~apll_mask; cval |= apll_mask; - cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); + omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); omap2_cm_wait_idlest(cm_idlest_pll, status_mask, OMAP24XX_CM_IDLEST_VAL, clk->name); @@ -83,9 +83,9 @@ static void omap2_clk_apll_disable(struct clk *clk) { u32 cval; - cval = cm_read_mod_reg(PLL_MOD, CM_CLKEN); + cval = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); cval &= ~(EN_APLL_LOCKED << clk->enable_bit); - cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); + omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN); } /* Public data */ @@ -106,7 +106,7 @@ u32 omap2xxx_get_apll_clkin(void) { u32 aplls, srate = 0; - aplls = cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); + aplls = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL1); aplls &= OMAP24XX_APLLS_CLKIN_MASK; aplls >>= OMAP24XX_APLLS_CLKIN_SHIFT; diff --git a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c index 530a76bc4a6c..4ae439222085 100644 --- a/arch/arm/mach-omap2/clkt2xxx_dpllcore.c +++ b/arch/arm/mach-omap2/clkt2xxx_dpllcore.c @@ -54,7 +54,7 @@ unsigned long omap2xxx_clk_get_core_rate(struct clk *clk) core_clk = omap2_get_dpll_rate(clk); - v = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + v = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); v &= OMAP24XX_CORE_CLK_SRC_MASK; if (v == CORE_CLK_SRC_32K) @@ -73,7 +73,7 @@ static long omap2_dpllcore_round_rate(unsigned long target_rate) { u32 high, low, core_clk_src; - core_clk_src = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + core_clk_src = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); core_clk_src &= OMAP24XX_CORE_CLK_SRC_MASK; if (core_clk_src == CORE_CLK_SRC_DPLL) { /* DPLL clockout */ @@ -111,7 +111,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) const struct dpll_data *dd; cur_rate = omap2xxx_clk_get_core_rate(dclk); - mult = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + mult = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); mult &= OMAP24XX_CORE_CLK_SRC_MASK; if ((rate == (cur_rate / 2)) && (mult == 2)) { @@ -136,7 +136,7 @@ int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate) tmpset.cm_clksel1_pll &= ~(dd->mult_mask | dd->div1_mask); div = ((curr_prcm_set->xtal_speed / 1000000) - 1); - tmpset.cm_clksel2_pll = cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); + tmpset.cm_clksel2_pll = omap2_cm_read_mod_reg(PLL_MOD, CM_CLKSEL2); tmpset.cm_clksel2_pll &= ~OMAP24XX_CORE_CLK_SRC_MASK; if (rate > low) { tmpset.cm_clksel2_pll |= CORE_CLK_SRC_DPLL_X2; diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c index f49f47d7457d..39f9d5a58d0c 100644 --- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c +++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c @@ -133,21 +133,21 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate) done_rate = CORE_CLK_SRC_DPLL; /* MPU divider */ - cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); + omap2_cm_write_mod_reg(prcm->cm_clksel_mpu, MPU_MOD, CM_CLKSEL); /* dsp + iva1 div(2420), iva2.1(2430) */ - cm_write_mod_reg(prcm->cm_clksel_dsp, + omap2_cm_write_mod_reg(prcm->cm_clksel_dsp, OMAP24XX_DSP_MOD, CM_CLKSEL); - cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); + omap2_cm_write_mod_reg(prcm->cm_clksel_gfx, GFX_MOD, CM_CLKSEL); /* Major subsystem dividers */ - tmp = cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; - cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, + tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; + omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, CM_CLKSEL1); if (cpu_is_omap2430()) - cm_write_mod_reg(prcm->cm_clksel_mdm, + omap2_cm_write_mod_reg(prcm->cm_clksel_mdm, OMAP2430_MDM_MOD, CM_CLKSEL); /* x2 to enter omap2xxx_sdrc_init_params() */ diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index a2142e0f1ef4..da74f719d874 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -13,7 +13,6 @@ */ #undef DEBUG -#include #include #include #include @@ -30,7 +29,6 @@ #include "prm2xxx_3xxx.h" #include "prm-regbits-24xx.h" #include "cm2xxx_3xxx.h" -#include "cm2xxx_3xxx.h" #include #include @@ -410,7 +408,7 @@ int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) pr_debug("clockdomain: hardware will wake up %s when %s wakes " "up\n", clkdm1->name, clkdm2->name); - prm_set_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_prm_set_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); } @@ -445,7 +443,7 @@ int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) pr_debug("clockdomain: hardware will no longer wake up %s " "after %s wakes up\n", clkdm1->name, clkdm2->name); - prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_prm_clear_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP); } @@ -481,7 +479,7 @@ int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) } /* XXX It's faster to return the atomic wkdep_usecount */ - return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, + return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, PM_WKDEP, (1 << clkdm2->dep_bit)); } @@ -515,7 +513,7 @@ int clkdm_clear_all_wkdeps(struct clockdomain *clkdm) atomic_set(&cd->wkdep_usecount, 0); } - prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); + omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, PM_WKDEP); return 0; } @@ -554,7 +552,7 @@ int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) pr_debug("clockdomain: will prevent %s from sleeping if %s " "is active\n", clkdm1->name, clkdm2->name); - cm_set_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_cm_set_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP); } @@ -597,7 +595,7 @@ int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) "sleeping if %s is active\n", clkdm1->name, clkdm2->name); - cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), + omap2_cm_clear_mod_reg_bits((1 << clkdm2->dep_bit), clkdm1->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP); } @@ -640,7 +638,7 @@ int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2) } /* XXX It's faster to return the atomic sleepdep_usecount */ - return prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, + return omap2_prm_read_mod_bits_shift(clkdm1->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP, (1 << clkdm2->dep_bit)); } @@ -678,7 +676,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm) atomic_set(&cd->sleepdep_usecount, 0); } - prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, + omap2_prm_clear_mod_reg_bits(mask, clkdm->pwrdm.ptr->prcm_offs, OMAP3430_CM_SLEEPDEP); return 0; @@ -730,7 +728,7 @@ int omap2_clkdm_sleep(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { - cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, + omap2_cm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { @@ -774,7 +772,7 @@ int omap2_clkdm_wakeup(struct clockdomain *clkdm) if (cpu_is_omap24xx()) { - cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, + omap2_cm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, clkdm->pwrdm.ptr->prcm_offs, OMAP2_PM_PWSTCTRL); } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) { diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c index 1c98dfc93a83..e3d598a4c624 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c @@ -29,37 +29,37 @@ static const u8 cm_idlest_offs[] = { CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3 }; -u32 cm_read_mod_reg(s16 module, u16 idx) +u32 omap2_cm_read_mod_reg(s16 module, u16 idx) { return __raw_readl(cm_base + module + idx); } -void cm_write_mod_reg(u32 val, s16 module, u16 idx) +void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx) { __raw_writel(val, cm_base + module + idx); } /* Read-modify-write a register in a CM module. Caller must lock */ -u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) { u32 v; - v = cm_read_mod_reg(module, idx); + v = omap2_cm_read_mod_reg(module, idx); v &= ~mask; v |= bits; - cm_write_mod_reg(v, module, idx); + omap2_cm_write_mod_reg(v, module, idx); return v; } -u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) { - return cm_rmw_mod_reg_bits(bits, bits, module, idx); + return omap2_cm_rmw_mod_reg_bits(bits, bits, module, idx); } -u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) { - return cm_rmw_mod_reg_bits(bits, 0x0, module, idx); + return omap2_cm_rmw_mod_reg_bits(bits, 0x0, module, idx); } /** @@ -90,7 +90,7 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) else BUG(); - omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), + omap_test_timeout(((omap2_cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena), MAX_MODULE_READY_TIME, i); return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; @@ -166,228 +166,238 @@ static struct omap3_cm_regs cm_context; void omap3_cm_save_context(void) { cm_context.iva2_cm_clksel1 = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); cm_context.iva2_cm_clksel2 = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); cm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); cm_context.sgx_cm_clksel = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); cm_context.dss_cm_clksel = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); cm_context.cam_cm_clksel = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); cm_context.per_cm_clksel = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); cm_context.emu_cm_clksel = - cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); + omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); cm_context.emu_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_EMU_MOD, OMAP2_CM_CLKSTCTRL); cm_context.pll_cm_autoidle2 = - cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); + omap2_cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); cm_context.pll_cm_clksel4 = - cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); cm_context.pll_cm_clksel5 = - cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); cm_context.pll_cm_clken2 = - cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); cm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); cm_context.iva2_cm_fclken = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); - cm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD, - OMAP3430_CM_CLKEN_PLL); + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); + cm_context.iva2_cm_clken_pll = + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL); cm_context.core_cm_fclken1 = - cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); cm_context.core_cm_fclken3 = - cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); + omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); cm_context.sgx_cm_fclken = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); cm_context.wkup_cm_fclken = - cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); cm_context.dss_cm_fclken = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); cm_context.cam_cm_fclken = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); cm_context.per_cm_fclken = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); cm_context.usbhost_cm_fclken = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); cm_context.core_cm_iclken1 = - cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); + omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); cm_context.core_cm_iclken2 = - cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); + omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); cm_context.core_cm_iclken3 = - cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); + omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); cm_context.sgx_cm_iclken = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); cm_context.wkup_cm_iclken = - cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); cm_context.dss_cm_iclken = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); cm_context.cam_cm_iclken = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); cm_context.per_cm_iclken = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); cm_context.usbhost_cm_iclken = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); cm_context.iva2_cm_autoidle2 = - cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); cm_context.mpu_cm_autoidle2 = - cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); + omap2_cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); cm_context.iva2_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP2_CM_CLKSTCTRL); cm_context.mpu_cm_clkstctrl = - cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP2_CM_CLKSTCTRL); cm_context.core_cm_clkstctrl = - cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); cm_context.sgx_cm_clkstctrl = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP2_CM_CLKSTCTRL); cm_context.dss_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP2_CM_CLKSTCTRL); cm_context.cam_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP2_CM_CLKSTCTRL); cm_context.per_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP2_CM_CLKSTCTRL); cm_context.neon_cm_clkstctrl = - cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430_NEON_MOD, OMAP2_CM_CLKSTCTRL); cm_context.usbhost_cm_clkstctrl = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, + OMAP2_CM_CLKSTCTRL); cm_context.core_cm_autoidle1 = - cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); + omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); cm_context.core_cm_autoidle2 = - cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); + omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); cm_context.core_cm_autoidle3 = - cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); + omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); cm_context.wkup_cm_autoidle = - cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); + omap2_cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); cm_context.dss_cm_autoidle = - cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); cm_context.cam_cm_autoidle = - cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); cm_context.per_cm_autoidle = - cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); cm_context.usbhost_cm_autoidle = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); cm_context.sgx_cm_sleepdep = - cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_read_mod_reg(OMAP3430ES2_SGX_MOD, + OMAP3430_CM_SLEEPDEP); cm_context.dss_cm_sleepdep = - cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); cm_context.cam_cm_sleepdep = - cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); cm_context.per_cm_sleepdep = - cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); cm_context.usbhost_cm_sleepdep = - cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, + OMAP3430_CM_SLEEPDEP); cm_context.cm_clkout_ctrl = - cm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_CM_CLKOUT_CTRL_OFFSET); + omap2_cm_read_mod_reg(OMAP3430_CCR_MOD, + OMAP3_CM_CLKOUT_CTRL_OFFSET); } void omap3_cm_restore_context(void) { - cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, - CM_CLKSEL1); - cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, - CM_CLKSEL2); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel1, OMAP3430_IVA2_MOD, + CM_CLKSEL1); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clksel2, OMAP3430_IVA2_MOD, + CM_CLKSEL2); __raw_writel(cm_context.cm_sysconfig, OMAP3430_CM_SYSCONFIG); - cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, - CM_CLKSEL); - cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, - CM_CLKSEL); - cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, - CM_CLKSEL); - cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, - CM_CLKSEL); - cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, - CM_CLKSEL1); - cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, - OMAP3430ES2_CM_CLKSEL4); - cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, - OMAP3430ES2_CM_CLKSEL5); - cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, - OMAP3430ES2_CM_CLKEN2); + omap2_cm_write_mod_reg(cm_context.sgx_cm_clksel, OMAP3430ES2_SGX_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.dss_cm_clksel, OMAP3430_DSS_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.cam_cm_clksel, OMAP3430_CAM_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.per_cm_clksel, OMAP3430_PER_MOD, + CM_CLKSEL); + omap2_cm_write_mod_reg(cm_context.emu_cm_clksel, OMAP3430_EMU_MOD, + CM_CLKSEL1); + omap2_cm_write_mod_reg(cm_context.emu_cm_clkstctrl, OMAP3430_EMU_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.pll_cm_autoidle2, PLL_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.pll_cm_clksel4, PLL_MOD, + OMAP3430ES2_CM_CLKSEL4); + omap2_cm_write_mod_reg(cm_context.pll_cm_clksel5, PLL_MOD, + OMAP3430ES2_CM_CLKSEL5); + omap2_cm_write_mod_reg(cm_context.pll_cm_clken2, PLL_MOD, + OMAP3430ES2_CM_CLKEN2); __raw_writel(cm_context.cm_polctrl, OMAP3430_CM_POLCTRL); - cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, - CM_FCLKEN); - cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, - OMAP3430_CM_CLKEN_PLL); - cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, CM_FCLKEN1); - cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, - OMAP3430ES2_CM_FCLKEN3); - cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, - CM_FCLKEN); - cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); - cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, - CM_FCLKEN); - cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, - CM_FCLKEN); - cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, - CM_FCLKEN); - cm_write_mod_reg(cm_context.usbhost_cm_fclken, - OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); - cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, CM_ICLKEN1); - cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, CM_ICLKEN2); - cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, CM_ICLKEN3); - cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, - CM_ICLKEN); - cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); - cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, - CM_ICLKEN); - cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, - CM_ICLKEN); - cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, - CM_ICLKEN); - cm_write_mod_reg(cm_context.usbhost_cm_iclken, - OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); - cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, - OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, - OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); - cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, - CM_AUTOIDLE1); - cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, - CM_AUTOIDLE2); - cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, - CM_AUTOIDLE3); - cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, CM_AUTOIDLE); - cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, - CM_AUTOIDLE); - cm_write_mod_reg(cm_context.usbhost_cm_autoidle, - OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); - cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, - OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, - OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); - cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, - OMAP3_CM_CLKOUT_CTRL_OFFSET); + omap2_cm_write_mod_reg(cm_context.iva2_cm_fclken, OMAP3430_IVA2_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clken_pll, OMAP3430_IVA2_MOD, + OMAP3430_CM_CLKEN_PLL); + omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, + CM_FCLKEN1); + omap2_cm_write_mod_reg(cm_context.core_cm_fclken3, CORE_MOD, + OMAP3430ES2_CM_FCLKEN3); + omap2_cm_write_mod_reg(cm_context.sgx_cm_fclken, OMAP3430ES2_SGX_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.wkup_cm_fclken, WKUP_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.dss_cm_fclken, OMAP3430_DSS_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.cam_cm_fclken, OMAP3430_CAM_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.per_cm_fclken, OMAP3430_PER_MOD, + CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_fclken, + OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(cm_context.core_cm_iclken1, CORE_MOD, + CM_ICLKEN1); + omap2_cm_write_mod_reg(cm_context.core_cm_iclken2, CORE_MOD, + CM_ICLKEN2); + omap2_cm_write_mod_reg(cm_context.core_cm_iclken3, CORE_MOD, + CM_ICLKEN3); + omap2_cm_write_mod_reg(cm_context.sgx_cm_iclken, OMAP3430ES2_SGX_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.wkup_cm_iclken, WKUP_MOD, CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.dss_cm_iclken, OMAP3430_DSS_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.cam_cm_iclken, OMAP3430_CAM_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.per_cm_iclken, OMAP3430_PER_MOD, + CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_iclken, + OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); + omap2_cm_write_mod_reg(cm_context.iva2_cm_autoidle2, OMAP3430_IVA2_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.mpu_cm_autoidle2, MPU_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.iva2_cm_clkstctrl, OMAP3430_IVA2_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.mpu_cm_clkstctrl, MPU_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.core_cm_clkstctrl, CORE_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.sgx_cm_clkstctrl, OMAP3430ES2_SGX_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.dss_cm_clkstctrl, OMAP3430_DSS_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.cam_cm_clkstctrl, OMAP3430_CAM_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.per_cm_clkstctrl, OMAP3430_PER_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.neon_cm_clkstctrl, OMAP3430_NEON_MOD, + OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_clkstctrl, + OMAP3430ES2_USBHOST_MOD, OMAP2_CM_CLKSTCTRL); + omap2_cm_write_mod_reg(cm_context.core_cm_autoidle1, CORE_MOD, + CM_AUTOIDLE1); + omap2_cm_write_mod_reg(cm_context.core_cm_autoidle2, CORE_MOD, + CM_AUTOIDLE2); + omap2_cm_write_mod_reg(cm_context.core_cm_autoidle3, CORE_MOD, + CM_AUTOIDLE3); + omap2_cm_write_mod_reg(cm_context.wkup_cm_autoidle, WKUP_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.dss_cm_autoidle, OMAP3430_DSS_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.cam_cm_autoidle, OMAP3430_CAM_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.per_cm_autoidle, OMAP3430_PER_MOD, + CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_autoidle, + OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); + omap2_cm_write_mod_reg(cm_context.sgx_cm_sleepdep, OMAP3430ES2_SGX_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.dss_cm_sleepdep, OMAP3430_DSS_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.cam_cm_sleepdep, OMAP3430_CAM_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.per_cm_sleepdep, OMAP3430_PER_MOD, + OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.usbhost_cm_sleepdep, + OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); + omap2_cm_write_mod_reg(cm_context.cm_clkout_ctrl, OMAP3430_CCR_MOD, + OMAP3_CM_CLKOUT_CTRL_OFFSET); } #endif diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h index ce2582c1441b..ff24edf54d31 100644 --- a/arch/arm/mach-omap2/cm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h @@ -104,14 +104,14 @@ #ifndef __ASSEMBLER__ -extern u32 cm_read_mod_reg(s16 module, u16 idx); -extern void cm_write_mod_reg(u32 val, s16 module, u16 idx); -extern u32 cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +extern u32 omap2_cm_read_mod_reg(s16 module, u16 idx); +extern void omap2_cm_write_mod_reg(u32 val, s16 module, u16 idx); +extern u32 omap2_cm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); extern int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift); -extern u32 cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); -extern u32 cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_cm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_cm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); #endif diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 2506edfc4acb..61101e807df1 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c @@ -252,13 +252,13 @@ void omap3_clear_scratchpad_contents(void) void __iomem *v_addr; u32 offset = 0; v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); - if (prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & + if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & OMAP3430_GLOBAL_COLD_RST_MASK) { for ( ; offset <= max_offset; offset += 0x4) __raw_writel(0x0, (v_addr + offset)); - prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, - OMAP3430_GR_MOD, - OMAP3_PRM_RSTST_OFFSET); + omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, + OMAP3430_GR_MOD, + OMAP3_PRM_RSTST_OFFSET); } } @@ -300,32 +300,34 @@ void omap3_save_scratchpad_contents(void) scratchpad_contents.sdrc_block_offset = 0x64; /* Populate the PRCM block contents */ - prcm_block_contents.prm_clksrc_ctrl = prm_read_mod_reg(OMAP3430_GR_MOD, - OMAP3_PRM_CLKSRC_CTRL_OFFSET); - prcm_block_contents.prm_clksel = prm_read_mod_reg(OMAP3430_CCR_MOD, - OMAP3_PRM_CLKSEL_OFFSET); + prcm_block_contents.prm_clksrc_ctrl = + omap2_prm_read_mod_reg(OMAP3430_GR_MOD, + OMAP3_PRM_CLKSRC_CTRL_OFFSET); + prcm_block_contents.prm_clksel = + omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, + OMAP3_PRM_CLKSEL_OFFSET); prcm_block_contents.cm_clksel_core = - cm_read_mod_reg(CORE_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); prcm_block_contents.cm_clksel_wkup = - cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); + omap2_cm_read_mod_reg(WKUP_MOD, CM_CLKSEL); prcm_block_contents.cm_clken_pll = - cm_read_mod_reg(PLL_MOD, CM_CLKEN); + omap2_cm_read_mod_reg(PLL_MOD, CM_CLKEN); prcm_block_contents.cm_autoidle_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_AUTOIDLE_PLL); prcm_block_contents.cm_clksel1_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL1_PLL); prcm_block_contents.cm_clksel2_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL2_PLL); prcm_block_contents.cm_clksel3_pll = - cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); + omap2_cm_read_mod_reg(PLL_MOD, OMAP3430_CM_CLKSEL3); prcm_block_contents.cm_clken_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKEN_PLL); prcm_block_contents.cm_autoidle_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_AUTOIDLE_PLL); prcm_block_contents.cm_clksel1_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL1_PLL); prcm_block_contents.cm_clksel2_pll_mpu = - cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); + omap2_cm_read_mod_reg(MPU_MOD, OMAP3430_CM_CLKSEL2_PLL); prcm_block_contents.prcm_block_size = 0x0; /* Populate the SDRC block contents */ diff --git a/arch/arm/mach-omap2/dsp.c b/arch/arm/mach-omap2/dsp.c index cf5f3331af27..911cd2e68d46 100644 --- a/arch/arm/mach-omap2/dsp.c +++ b/arch/arm/mach-omap2/dsp.c @@ -38,12 +38,12 @@ static struct omap_dsp_platform_data omap_dsp_pdata __initdata = { .cpu_set_freq = omap_pm_cpu_set_freq, .cpu_get_freq = omap_pm_cpu_get_freq, #endif - .dsp_prm_read = prm_read_mod_reg, - .dsp_prm_write = prm_write_mod_reg, - .dsp_prm_rmw_bits = prm_rmw_mod_reg_bits, - .dsp_cm_read = cm_read_mod_reg, - .dsp_cm_write = cm_write_mod_reg, - .dsp_cm_rmw_bits = cm_rmw_mod_reg_bits, + .dsp_prm_read = omap2_prm_read_mod_reg, + .dsp_prm_write = omap2_prm_write_mod_reg, + .dsp_prm_rmw_bits = omap2_prm_rmw_mod_reg_bits, + .dsp_cm_read = omap2_cm_read_mod_reg, + .dsp_cm_write = omap2_cm_write_mod_reg, + .dsp_cm_rmw_bits = omap2_cm_rmw_mod_reg_bits, }; static int __init omap_dsp_init(void) diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 1f5d68beabf3..1a4efb5e435a 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -45,10 +45,10 @@ u32 wakeup_timer_milliseconds; #define DUMP_PRM_MOD_REG(mod, reg) \ regs[reg_count].name = #mod "." #reg; \ - regs[reg_count++].val = prm_read_mod_reg(mod, reg) + regs[reg_count++].val = omap2_prm_read_mod_reg(mod, reg) #define DUMP_CM_MOD_REG(mod, reg) \ regs[reg_count].name = #mod "." #reg; \ - regs[reg_count++].val = cm_read_mod_reg(mod, reg) + regs[reg_count++].val = omap2_cm_read_mod_reg(mod, reg) #define DUMP_PRM_REG(reg) \ regs[reg_count].name = #reg; \ regs[reg_count++].val = __raw_readl(reg) @@ -328,10 +328,10 @@ static void pm_dbg_regset_store(u32 *ptr) for (j = pm_dbg_reg_modules[i].low; j <= pm_dbg_reg_modules[i].high; j += 4) { if (pm_dbg_reg_modules[i].type == MOD_CM) - val = cm_read_mod_reg( + val = omap2_cm_read_mod_reg( pm_dbg_reg_modules[i].offset, j); else - val = prm_read_mod_reg( + val = omap2_prm_read_mod_reg( pm_dbg_reg_modules[i].offset, j); *(ptr++) = val; } diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index 8ea49dcaae4d..bf0c36b239f9 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -79,8 +79,8 @@ static int omap2_fclks_active(void) { u32 f1, f2; - f1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); - f2 = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); /* Ignore UART clocks. These are handled by UART core (serial.c) */ f1 &= ~(OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_UART2_MASK); @@ -105,9 +105,9 @@ static void omap2_enter_full_retention(void) /* Clear old wake-up events */ /* REVISIT: These write to reserved bits? */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); /* * Set MPU powerdomain's next power state to RETENTION; @@ -167,30 +167,30 @@ no_sleep: clk_enable(osc_ck); /* clear CORE wake-up events */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ - prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); + omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); /* MPU domain wake events */ - l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); + l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); if (l & 0x01) - prm_write_mod_reg(0x01, OCP_MOD, + omap2_prm_write_mod_reg(0x01, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); if (l & 0x20) - prm_write_mod_reg(0x20, OCP_MOD, + omap2_prm_write_mod_reg(0x20, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); /* Mask future PRCM-to-MPU interrupts */ - prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); + omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); } static int omap2_i2c_active(void) { u32 l; - l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); return l & (OMAP2420_EN_I2C2_MASK | OMAP2420_EN_I2C1_MASK); } @@ -201,13 +201,13 @@ static int omap2_allow_mpu_retention(void) u32 l; /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */ - l = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); + l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); if (l & (OMAP2420_EN_MMC_MASK | OMAP24XX_EN_UART2_MASK | OMAP24XX_EN_UART1_MASK | OMAP24XX_EN_MCSPI2_MASK | OMAP24XX_EN_MCSPI1_MASK | OMAP24XX_EN_DSS1_MASK)) return 0; /* Check for UART3. */ - l = cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); + l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); if (l & OMAP24XX_EN_UART3_MASK) return 0; if (sti_console_enabled) @@ -230,18 +230,18 @@ static void omap2_enter_mpu_retention(void) * it is in retention mode. */ if (omap2_allow_mpu_retention()) { /* REVISIT: These write to reserved bits? */ - prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); - prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); + omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); /* Try to enter MPU retention */ - prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | + omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT) | OMAP_LOGICRETSTATE_MASK, MPU_MOD, OMAP2_PM_PWSTCTRL); } else { /* Block MPU retention */ - prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, + omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK, MPU_MOD, OMAP2_PM_PWSTCTRL); only_idle = 1; } @@ -310,9 +310,9 @@ static int omap2_pm_suspend(void) { u32 wken_wkup, mir1; - wken_wkup = prm_read_mod_reg(WKUP_MOD, PM_WKEN); + wken_wkup = omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); wken_wkup &= ~OMAP24XX_EN_GPT1_MASK; - prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); + omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); /* Mask GPT1 */ mir1 = omap_readl(0x480fe0a4); @@ -322,7 +322,7 @@ static int omap2_pm_suspend(void) omap2_enter_full_retention(); omap_writel(mir1, 0x480fe0a4); - prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); + omap2_prm_write_mod_reg(wken_wkup, WKUP_MOD, PM_WKEN); return 0; } @@ -376,7 +376,7 @@ static void __init prcm_setup_regs(void) struct powerdomain *pwrdm; /* Enable autoidle */ - prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, + omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK, OCP_MOD, OMAP2_PRCM_SYSCONFIG_OFFSET); /* @@ -415,87 +415,87 @@ static void __init prcm_setup_regs(void) clkdm_add_wkdep(mpu_clkdm, wkup_clkdm); /* Enable clock autoidle for all domains */ - cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | - OMAP24XX_AUTO_MAILBOXES_MASK | - OMAP24XX_AUTO_WDT4_MASK | - OMAP2420_AUTO_WDT3_MASK | - OMAP24XX_AUTO_MSPRO_MASK | - OMAP2420_AUTO_MMC_MASK | - OMAP24XX_AUTO_FAC_MASK | - OMAP2420_AUTO_EAC_MASK | - OMAP24XX_AUTO_HDQ_MASK | - OMAP24XX_AUTO_UART2_MASK | - OMAP24XX_AUTO_UART1_MASK | - OMAP24XX_AUTO_I2C2_MASK | - OMAP24XX_AUTO_I2C1_MASK | - OMAP24XX_AUTO_MCSPI2_MASK | - OMAP24XX_AUTO_MCSPI1_MASK | - OMAP24XX_AUTO_MCBSP2_MASK | - OMAP24XX_AUTO_MCBSP1_MASK | - OMAP24XX_AUTO_GPT12_MASK | - OMAP24XX_AUTO_GPT11_MASK | - OMAP24XX_AUTO_GPT10_MASK | - OMAP24XX_AUTO_GPT9_MASK | - OMAP24XX_AUTO_GPT8_MASK | - OMAP24XX_AUTO_GPT7_MASK | - OMAP24XX_AUTO_GPT6_MASK | - OMAP24XX_AUTO_GPT5_MASK | - OMAP24XX_AUTO_GPT4_MASK | - OMAP24XX_AUTO_GPT3_MASK | - OMAP24XX_AUTO_GPT2_MASK | - OMAP2420_AUTO_VLYNQ_MASK | - OMAP24XX_AUTO_DSS_MASK, - CORE_MOD, CM_AUTOIDLE1); - cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | - OMAP24XX_AUTO_SSI_MASK | - OMAP24XX_AUTO_USB_MASK, - CORE_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | - OMAP24XX_AUTO_GPMC_MASK | - OMAP24XX_AUTO_SDMA_MASK, - CORE_MOD, CM_AUTOIDLE3); - cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | - OMAP24XX_AUTO_AES_MASK | - OMAP24XX_AUTO_RNG_MASK | - OMAP24XX_AUTO_SHA_MASK | - OMAP24XX_AUTO_DES_MASK, - CORE_MOD, OMAP24XX_CM_AUTOIDLE4); - - cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, - CM_AUTOIDLE); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_CAM_MASK | + OMAP24XX_AUTO_MAILBOXES_MASK | + OMAP24XX_AUTO_WDT4_MASK | + OMAP2420_AUTO_WDT3_MASK | + OMAP24XX_AUTO_MSPRO_MASK | + OMAP2420_AUTO_MMC_MASK | + OMAP24XX_AUTO_FAC_MASK | + OMAP2420_AUTO_EAC_MASK | + OMAP24XX_AUTO_HDQ_MASK | + OMAP24XX_AUTO_UART2_MASK | + OMAP24XX_AUTO_UART1_MASK | + OMAP24XX_AUTO_I2C2_MASK | + OMAP24XX_AUTO_I2C1_MASK | + OMAP24XX_AUTO_MCSPI2_MASK | + OMAP24XX_AUTO_MCSPI1_MASK | + OMAP24XX_AUTO_MCBSP2_MASK | + OMAP24XX_AUTO_MCBSP1_MASK | + OMAP24XX_AUTO_GPT12_MASK | + OMAP24XX_AUTO_GPT11_MASK | + OMAP24XX_AUTO_GPT10_MASK | + OMAP24XX_AUTO_GPT9_MASK | + OMAP24XX_AUTO_GPT8_MASK | + OMAP24XX_AUTO_GPT7_MASK | + OMAP24XX_AUTO_GPT6_MASK | + OMAP24XX_AUTO_GPT5_MASK | + OMAP24XX_AUTO_GPT4_MASK | + OMAP24XX_AUTO_GPT3_MASK | + OMAP24XX_AUTO_GPT2_MASK | + OMAP2420_AUTO_VLYNQ_MASK | + OMAP24XX_AUTO_DSS_MASK, + CORE_MOD, CM_AUTOIDLE1); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_UART3_MASK | + OMAP24XX_AUTO_SSI_MASK | + OMAP24XX_AUTO_USB_MASK, + CORE_MOD, CM_AUTOIDLE2); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_SDRC_MASK | + OMAP24XX_AUTO_GPMC_MASK | + OMAP24XX_AUTO_SDMA_MASK, + CORE_MOD, CM_AUTOIDLE3); + omap2_cm_write_mod_reg(OMAP24XX_AUTO_PKA_MASK | + OMAP24XX_AUTO_AES_MASK | + OMAP24XX_AUTO_RNG_MASK | + OMAP24XX_AUTO_SHA_MASK | + OMAP24XX_AUTO_DES_MASK, + CORE_MOD, OMAP24XX_CM_AUTOIDLE4); + + omap2_cm_write_mod_reg(OMAP2420_AUTO_DSP_IPI_MASK, OMAP24XX_DSP_MOD, + CM_AUTOIDLE); /* Put DPLL and both APLLs into autoidle mode */ - cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | - (0x03 << OMAP24XX_AUTO_96M_SHIFT) | - (0x03 << OMAP24XX_AUTO_54M_SHIFT), - PLL_MOD, CM_AUTOIDLE); - - cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | - OMAP24XX_AUTO_WDT1_MASK | - OMAP24XX_AUTO_MPU_WDT_MASK | - OMAP24XX_AUTO_GPIOS_MASK | - OMAP24XX_AUTO_32KSYNC_MASK | - OMAP24XX_AUTO_GPT1_MASK, - WKUP_MOD, CM_AUTOIDLE); + omap2_cm_write_mod_reg((0x03 << OMAP24XX_AUTO_DPLL_SHIFT) | + (0x03 << OMAP24XX_AUTO_96M_SHIFT) | + (0x03 << OMAP24XX_AUTO_54M_SHIFT), + PLL_MOD, CM_AUTOIDLE); + + omap2_cm_write_mod_reg(OMAP24XX_AUTO_OMAPCTRL_MASK | + OMAP24XX_AUTO_WDT1_MASK | + OMAP24XX_AUTO_MPU_WDT_MASK | + OMAP24XX_AUTO_GPIOS_MASK | + OMAP24XX_AUTO_32KSYNC_MASK | + OMAP24XX_AUTO_GPT1_MASK, + WKUP_MOD, CM_AUTOIDLE); /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk * stabilisation */ - prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, - OMAP2_PRCM_CLKSSETUP_OFFSET); + omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, + OMAP2_PRCM_CLKSSETUP_OFFSET); /* Configure automatic voltage transition */ - prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, - OMAP2_PRCM_VOLTSETUP_OFFSET); - prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | - (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | - OMAP24XX_MEMRETCTRL_MASK | - (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | - (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), - OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); + omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT, OMAP24XX_GR_MOD, + OMAP2_PRCM_VOLTSETUP_OFFSET); + omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK | + (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT) | + OMAP24XX_MEMRETCTRL_MASK | + (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT) | + (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT), + OMAP24XX_GR_MOD, OMAP2_PRCM_VOLTCTRL_OFFSET); /* Enable wake-up events */ - prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, - WKUP_MOD, PM_WKEN); + omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK | OMAP24XX_EN_GPT1_MASK, + WKUP_MOD, PM_WKEN); } static int __init omap2_pm_init(void) @@ -506,7 +506,7 @@ static int __init omap2_pm_init(void) return -ENODEV; printk(KERN_INFO "Power Management for OMAP2 initializing\n"); - l = prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); + l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_REVISION_OFFSET); printk(KERN_INFO "PRCM revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f); /* Look up important powerdomains */ diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index cfff321c747e..1ca6ef4c25b3 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -105,12 +105,12 @@ static void omap3_enable_io_chain(void) int timeout = 0; if (omap_rev() >= OMAP3430_REV_ES3_1) { - prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, + omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, PM_WKEN); /* Do a readback to assure write has been done */ - prm_read_mod_reg(WKUP_MOD, PM_WKEN); + omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN); - while (!(prm_read_mod_reg(WKUP_MOD, PM_WKEN) & + while (!(omap2_prm_read_mod_reg(WKUP_MOD, PM_WKEN) & OMAP3430_ST_IO_CHAIN_MASK)) { timeout++; if (timeout > 1000) { @@ -118,7 +118,7 @@ static void omap3_enable_io_chain(void) "activation failed.\n"); return; } - prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, + omap2_prm_set_mod_reg_bits(OMAP3430_ST_IO_CHAIN_MASK, WKUP_MOD, PM_WKEN); } } @@ -127,7 +127,7 @@ static void omap3_enable_io_chain(void) static void omap3_disable_io_chain(void) { if (omap_rev() >= OMAP3430_REV_ES3_1) - prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, + omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_CHAIN_MASK, WKUP_MOD, PM_WKEN); } @@ -221,27 +221,27 @@ static int prcm_clear_mod_irqs(s16 module, u8 regs) OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; int c = 0; - wkst = prm_read_mod_reg(module, wkst_off); - wkst &= prm_read_mod_reg(module, grpsel_off); + wkst = omap2_prm_read_mod_reg(module, wkst_off); + wkst &= omap2_prm_read_mod_reg(module, grpsel_off); if (wkst) { - iclk = cm_read_mod_reg(module, iclk_off); - fclk = cm_read_mod_reg(module, fclk_off); + iclk = omap2_cm_read_mod_reg(module, iclk_off); + fclk = omap2_cm_read_mod_reg(module, fclk_off); while (wkst) { clken = wkst; - cm_set_mod_reg_bits(clken, module, iclk_off); + omap2_cm_set_mod_reg_bits(clken, module, iclk_off); /* * For USBHOST, we don't know whether HOST1 or * HOST2 woke us up, so enable both f-clocks */ if (module == OMAP3430ES2_USBHOST_MOD) clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; - cm_set_mod_reg_bits(clken, module, fclk_off); - prm_write_mod_reg(wkst, module, wkst_off); - wkst = prm_read_mod_reg(module, wkst_off); + omap2_cm_set_mod_reg_bits(clken, module, fclk_off); + omap2_prm_write_mod_reg(wkst, module, wkst_off); + wkst = omap2_prm_read_mod_reg(module, wkst_off); c++; } - cm_write_mod_reg(iclk, module, iclk_off); - cm_write_mod_reg(fclk, module, fclk_off); + omap2_cm_write_mod_reg(iclk, module, iclk_off); + omap2_cm_write_mod_reg(fclk, module, fclk_off); } return c; @@ -284,9 +284,9 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) u32 irqenable_mpu, irqstatus_mpu; int c = 0; - irqenable_mpu = prm_read_mod_reg(OCP_MOD, + irqenable_mpu = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); - irqstatus_mpu = prm_read_mod_reg(OCP_MOD, + irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); irqstatus_mpu &= irqenable_mpu; @@ -307,10 +307,10 @@ static irqreturn_t prcm_interrupt_handler (int irq, void *dev_id) "no code to handle it (%08x)\n", irqstatus_mpu); } - prm_write_mod_reg(irqstatus_mpu, OCP_MOD, + omap2_prm_write_mod_reg(irqstatus_mpu, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); - irqstatus_mpu = prm_read_mod_reg(OCP_MOD, + irqstatus_mpu = omap2_prm_read_mod_reg(OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); irqstatus_mpu &= irqenable_mpu; @@ -398,7 +398,7 @@ void omap_sram_idle(void) if (omap3_has_io_wakeup() && (per_next_state < PWRDM_POWER_ON || core_next_state < PWRDM_POWER_ON)) { - prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); + omap2_prm_set_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); omap3_enable_io_chain(); } @@ -471,7 +471,7 @@ void omap_sram_idle(void) omap_uart_resume_idle(0); omap_uart_resume_idle(1); if (core_next_state == PWRDM_POWER_OFF) - prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, + omap2_prm_clear_mod_reg_bits(OMAP3430_AUTO_OFF_MASK, OMAP3430_GR_MOD, OMAP3_PRM_VOLTCTRL_OFFSET); } @@ -495,7 +495,8 @@ console_still_active: if (omap3_has_io_wakeup() && (per_next_state < PWRDM_POWER_ON || core_next_state < PWRDM_POWER_ON)) { - prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, PM_WKEN); + omap2_prm_clear_mod_reg_bits(OMAP3430_EN_IO_MASK, WKUP_MOD, + PM_WKEN); omap3_disable_io_chain(); } @@ -633,21 +634,21 @@ static struct platform_suspend_ops omap_pm_ops = { static void __init omap3_iva_idle(void) { /* ensure IVA2 clock is disabled */ - cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); /* if no clock activity, nothing else to do */ - if (!(cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & + if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & OMAP3430_CLKACTIVITY_IVA2_MASK)) return; /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | + omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK | OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Enable IVA2 clock */ - cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, + omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, OMAP3430_IVA2_MOD, CM_FCLKEN); /* Set IVA2 boot mode to 'idle' */ @@ -655,13 +656,13 @@ static void __init omap3_iva_idle(void) OMAP343X_CONTROL_IVA2_BOOTMOD); /* Un-reset IVA2 */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); + omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); /* Disable IVA2 clock */ - cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); + omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); /* Reset IVA2 */ - prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | + omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | OMAP3430_RST2_IVA2_MASK | OMAP3430_RST3_IVA2_MASK, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); @@ -685,10 +686,10 @@ static void __init omap3_d2d_idle(void) omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); /* reset modem */ - prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | + omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, CORE_MOD, OMAP2_RM_RSTCTRL); - prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); } static void __init prcm_setup_regs(void) @@ -703,23 +704,23 @@ static void __init prcm_setup_regs(void) /* XXX Reset all wkdeps. This should be done when initializing * powerdomains */ - prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); - prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, MPU_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_DSS_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_NEON_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_CAM_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, PM_WKDEP); if (omap_rev() > OMAP3430_REV_ES1_0) { - prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); - prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430ES2_SGX_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, OMAP3430ES2_USBHOST_MOD, PM_WKDEP); } else - prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); + omap2_prm_write_mod_reg(0, GFX_MOD, PM_WKDEP); /* * Enable interface clock autoidle for all modules. * Note that in the long run this should be done by clockfw */ - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_MODEM_MASK | OMAP3430ES2_AUTO_MMC3_MASK | OMAP3430ES2_AUTO_ICR_MASK | @@ -752,7 +753,7 @@ static void __init prcm_setup_regs(void) OMAP3430_AUTO_SSI_MASK, CORE_MOD, CM_AUTOIDLE1); - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_PKA_MASK | OMAP3430_AUTO_AES1_MASK | OMAP3430_AUTO_RNG_MASK | @@ -761,13 +762,13 @@ static void __init prcm_setup_regs(void) CORE_MOD, CM_AUTOIDLE2); if (omap_rev() > OMAP3430_REV_ES1_0) { - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_MAD2D_MASK | OMAP3430ES2_AUTO_USBTLL_MASK, CORE_MOD, CM_AUTOIDLE3); } - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_WDT2_MASK | OMAP3430_AUTO_WDT1_MASK | OMAP3430_AUTO_GPIO1_MASK | @@ -776,17 +777,17 @@ static void __init prcm_setup_regs(void) OMAP3430_AUTO_GPT1_MASK, WKUP_MOD, CM_AUTOIDLE); - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_DSS_MASK, OMAP3430_DSS_MOD, CM_AUTOIDLE); - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430_AUTO_CAM_MASK, OMAP3430_CAM_MOD, CM_AUTOIDLE); - cm_write_mod_reg( + omap2_cm_write_mod_reg( omap3630_auto_uart4_mask | OMAP3430_AUTO_GPIO6_MASK | OMAP3430_AUTO_GPIO5_MASK | @@ -810,7 +811,7 @@ static void __init prcm_setup_regs(void) CM_AUTOIDLE); if (omap_rev() > OMAP3430_REV_ES1_0) { - cm_write_mod_reg( + omap2_cm_write_mod_reg( OMAP3430ES2_AUTO_USBHOST_MASK, OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); @@ -822,16 +823,16 @@ static void __init prcm_setup_regs(void) * Set all plls to autoidle. This is needed until autoidle is * enabled by clockfw */ - cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, + omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_IVA2_DPLL_SHIFT, OMAP3430_IVA2_MOD, CM_AUTOIDLE2); - cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, + omap2_cm_write_mod_reg(1 << OMAP3430_AUTO_MPU_DPLL_SHIFT, MPU_MOD, CM_AUTOIDLE2); - cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | + omap2_cm_write_mod_reg((1 << OMAP3430_AUTO_PERIPH_DPLL_SHIFT) | (1 << OMAP3430_AUTO_CORE_DPLL_SHIFT), PLL_MOD, CM_AUTOIDLE); - cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, + omap2_cm_write_mod_reg(1 << OMAP3430ES2_AUTO_PERIPH2_DPLL_SHIFT, PLL_MOD, CM_AUTOIDLE2); @@ -840,31 +841,31 @@ static void __init prcm_setup_regs(void) * sys_clkreq. In the long run clock framework should * take care of this. */ - prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, 1 << OMAP_AUTOEXTCLKMODE_SHIFT, OMAP3430_GR_MOD, OMAP3_PRM_CLKSRC_CTRL_OFFSET); /* setup wakup source */ - prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | + omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, WKUP_MOD, PM_WKEN); /* No need to write EN_IO, that is always enabled */ - prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | + omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | OMAP3430_GRPSEL_GPT1_MASK | OMAP3430_GRPSEL_GPT12_MASK, WKUP_MOD, OMAP3430_PM_MPUGRPSEL); /* For some reason IO doesn't generate wakeup event even if * it is selected to mpu wakeup goup */ - prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, + omap2_prm_write_mod_reg(OMAP3430_IO_EN_MASK | OMAP3430_WKUP_EN_MASK, OCP_MOD, OMAP3_PRM_IRQENABLE_MPU_OFFSET); /* Enable PM_WKEN to support DSS LPR */ - prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, + omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, OMAP3430_DSS_MOD, PM_WKEN); /* Enable wakeups in PER */ - prm_write_mod_reg(omap3630_en_uart4_mask | + omap2_prm_write_mod_reg(omap3630_en_uart4_mask | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | @@ -872,7 +873,7 @@ static void __init prcm_setup_regs(void) OMAP3430_EN_MCBSP4_MASK, OMAP3430_PER_MOD, PM_WKEN); /* and allow them to wake up MPU */ - prm_write_mod_reg(omap3630_grpsel_uart4_mask | + omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | OMAP3430_GRPSEL_GPIO2_MASK | OMAP3430_GRPSEL_GPIO3_MASK | OMAP3430_GRPSEL_GPIO4_MASK | @@ -885,22 +886,22 @@ static void __init prcm_setup_regs(void) OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); /* Don't attach IVA interrupts */ - prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); - prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); - prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); - prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); + omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); + omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); + omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); /* Clear any pending 'reset' flags */ - prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); - prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); + omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); /* Clear any pending PRCM interrupts */ - prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); + omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); omap3_iva_idle(); omap3_d2d_idle(); diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c index 838ac758c513..b5e9e4d18b8c 100644 --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c @@ -28,7 +28,7 @@ /* Common functions across OMAP2 and OMAP3 */ static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { - prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, (pwrst << OMAP_POWERSTATE_SHIFT), pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; @@ -36,14 +36,16 @@ static int omap2_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) static int omap2_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL, OMAP_POWERSTATE_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, + OMAP_POWERSTATE_MASK); } static int omap2_pwrdm_read_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, - OMAP2_PM_PWSTST, OMAP_POWERSTATEST_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTST, + OMAP_POWERSTATEST_MASK); } static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, @@ -53,8 +55,8 @@ static int omap2_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); - prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL); + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); return 0; } @@ -66,8 +68,8 @@ static int omap2_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, - OMAP2_PM_PWSTCTRL); + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); return 0; } @@ -78,7 +80,8 @@ static int omap2_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) m = omap2_pwrdm_get_mem_bank_stst_mask(bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, m); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, + m); } static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) @@ -87,7 +90,8 @@ static int omap2_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, m); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, m); } static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) @@ -95,8 +99,8 @@ static int omap2_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) u32 v; v = pwrst << __ffs(OMAP3430_LOGICL1CACHERETSTATE_MASK); - prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + omap2_prm_rmw_mod_reg_bits(OMAP3430_LOGICL1CACHERETSTATE_MASK, v, + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); return 0; } @@ -112,7 +116,7 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) */ /* XXX Is this udelay() value meaningful? */ - while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & + while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP2_PM_PWSTST) & OMAP_INTRANSITION_MASK) && (c++ < PWRDM_TRANSITION_BAILOUT)) udelay(1); @@ -131,26 +135,30 @@ static int omap2_pwrdm_wait_transition(struct powerdomain *pwrdm) /* Applicable only for OMAP3. Not supported on OMAP2 */ static int omap3_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, - OMAP3430_LASTPOWERSTATEENTERED_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP3430_PM_PREPWSTST, + OMAP3430_LASTPOWERSTATEENTERED_MASK); } static int omap3_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTST, - OMAP3430_LOGICSTATEST_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTST, + OMAP3430_LOGICSTATEST_MASK); } static int omap3_pwrdm_read_logic_retst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL, - OMAP3430_LOGICSTATEST_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL, + OMAP3430_LOGICSTATEST_MASK); } static int omap3_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, - OMAP3430_LASTLOGICSTATEENTERED_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP3430_PM_PREPWSTST, + OMAP3430_LASTLOGICSTATEENTERED_MASK); } static int omap3_get_mem_bank_lastmemst_mask(u8 bank) @@ -177,26 +185,28 @@ static int omap3_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank) m = omap3_get_mem_bank_lastmemst_mask(bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST, m); } static int omap3_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) { - prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); + omap2_prm_write_mod_reg(0, pwrdm->prcm_offs, OMAP3430_PM_PREPWSTST); return 0; } static int omap3_pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm) { - return prm_rmw_mod_reg_bits(0, 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + return omap2_prm_rmw_mod_reg_bits(0, + 1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, + pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); } static int omap3_pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm) { - return prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, 0, - pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL); + return omap2_prm_rmw_mod_reg_bits(1 << OMAP3430ES2_SAVEANDRESTORE_SHIFT, + 0, pwrdm->prcm_offs, + OMAP2_PM_PWSTCTRL); } struct pwrdm_ops omap2_pwrdm_operations = { diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index dae767bf1952..4c5ab1a2d44b 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -25,7 +25,7 @@ static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { - prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK, (pwrst << OMAP_POWERSTATE_SHIFT), pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -33,25 +33,25 @@ static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) static int omap4_pwrdm_read_next_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, OMAP_POWERSTATE_MASK); } static int omap4_pwrdm_read_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, OMAP_POWERSTATEST_MASK); } static int omap4_pwrdm_read_prev_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, OMAP4430_LASTPOWERSTATEENTERED_MASK); } static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) { - prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP4430_LOWPOWERSTATECHANGE_MASK, (1 << OMAP4430_LOWPOWERSTATECHANGE_SHIFT), pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -59,7 +59,7 @@ static int omap4_pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm) static int omap4_pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm) { - prm_rmw_mod_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, + omap2_prm_rmw_mod_reg_bits(OMAP4430_LASTPOWERSTATEENTERED_MASK, OMAP4430_LASTPOWERSTATEENTERED_MASK, pwrdm->prcm_offs, OMAP4_PM_PWSTST); return 0; @@ -70,7 +70,7 @@ static int omap4_pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst) u32 v; v = pwrst << __ffs(OMAP4430_LOGICRETSTATE_MASK); - prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, + omap2_prm_rmw_mod_reg_bits(OMAP4430_LOGICRETSTATE_MASK, v, pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -83,7 +83,7 @@ static int omap4_pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, m = omap2_pwrdm_get_mem_bank_onstate_mask(bank); - prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -96,7 +96,7 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, + omap2_prm_rmw_mod_reg_bits(m, (pwrst << __ffs(m)), pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL); return 0; @@ -104,14 +104,15 @@ static int omap4_pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, static int omap4_pwrdm_read_logic_pwrst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, OMAP4430_LOGICSTATEST_MASK); } static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm) { - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, - OMAP4430_LOGICRETSTATE_MASK); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL, + OMAP4430_LOGICRETSTATE_MASK); } static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) @@ -120,7 +121,8 @@ static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank) m = omap2_pwrdm_get_mem_bank_stst_mask(bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, m); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTST, + m); } static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) @@ -129,7 +131,8 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank) m = omap2_pwrdm_get_mem_bank_retst_mask(bank); - return prm_read_mod_bits_shift(pwrdm->prcm_offs, OMAP4_PM_PWSTCTRL, m); + return omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs, + OMAP4_PM_PWSTCTRL, m); } static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) @@ -143,7 +146,7 @@ static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm) */ /* XXX Is this udelay() value meaningful? */ - while ((prm_read_mod_reg(pwrdm->prcm_offs, OMAP4_PM_PWSTST) & + while ((omap2_prm_read_mod_reg(pwrdm->prcm_offs, OMAP4_PM_PWSTST) & OMAP_INTRANSITION_MASK) && (c++ < PWRDM_TRANSITION_BAILOUT)) udelay(1); diff --git a/arch/arm/mach-omap2/prcm.c b/arch/arm/mach-omap2/prcm.c index 68c541f98ad2..c22e726de121 100644 --- a/arch/arm/mach-omap2/prcm.c +++ b/arch/arm/mach-omap2/prcm.c @@ -17,7 +17,8 @@ * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ -#include + +#include #include #include #include @@ -30,10 +31,9 @@ #include "clock.h" #include "clock2xxx.h" #include "cm2xxx_3xxx.h" -#include "cm44xx.h" #include "prm2xxx_3xxx.h" #include "prm44xx.h" -#include "prcm44xx.h" +#include "prminst44xx.h" #include "prm-regbits-24xx.h" #include "prm-regbits-44xx.h" #include "control.h" @@ -48,9 +48,9 @@ u32 omap_prcm_get_reset_sources(void) { /* XXX This presumably needs modification for 34XX */ if (cpu_is_omap24xx() || cpu_is_omap34xx()) - return prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; + return omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST) & 0x7f; if (cpu_is_omap44xx()) - return prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; + return omap2_prm_read_mod_reg(WKUP_MOD, OMAP4_RM_RSTST) & 0x7f; return 0; } @@ -75,9 +75,9 @@ void omap_prcm_arch_reset(char mode, const char *cmd) } /* XXX should be moved to some OMAP2/3 specific code */ - prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, - OMAP2_RM_RSTCTRL); - prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ + omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, prcm_offs, + OMAP2_RM_RSTCTRL); + omap2_prm_read_mod_reg(prcm_offs, OMAP2_RM_RSTCTRL); /* OCP barrier */ } /** diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.c b/arch/arm/mach-omap2/prm2xxx_3xxx.c index 3e1d36c83fc4..ec0362574b5e 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.c +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.c @@ -25,49 +25,49 @@ #include "prm-regbits-24xx.h" #include "prm-regbits-34xx.h" -u32 prm_read_mod_reg(s16 module, u16 idx) +u32 omap2_prm_read_mod_reg(s16 module, u16 idx) { return __raw_readl(prm_base + module + idx); } -void prm_write_mod_reg(u32 val, s16 module, u16 idx) +void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx) { __raw_writel(val, prm_base + module + idx); } /* Read-modify-write a register in a PRM module. Caller must lock */ -u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) +u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx) { u32 v; - v = prm_read_mod_reg(module, idx); + v = omap2_prm_read_mod_reg(module, idx); v &= ~mask; v |= bits; - prm_write_mod_reg(v, module, idx); + omap2_prm_write_mod_reg(v, module, idx); return v; } /* Read a PRM register, AND it, and shift the result down to bit 0 */ -u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) +u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask) { u32 v; - v = prm_read_mod_reg(domain, idx); + v = omap2_prm_read_mod_reg(domain, idx); v &= mask; v >>= __ffs(mask); return v; } -u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) +u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx) { - return prm_rmw_mod_reg_bits(bits, bits, module, idx); + return omap2_prm_rmw_mod_reg_bits(bits, bits, module, idx); } -u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) +u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx) { - return prm_rmw_mod_reg_bits(bits, 0x0, module, idx); + return omap2_prm_rmw_mod_reg_bits(bits, 0x0, module, idx); } @@ -86,7 +86,7 @@ int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift) if (!(cpu_is_omap24xx() || cpu_is_omap34xx())) return -EINVAL; - return prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, + return omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, (1 << shift)); } @@ -110,7 +110,7 @@ int omap2_prm_assert_hardreset(s16 prm_mod, u8 shift) return -EINVAL; mask = 1 << shift; - prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); + omap2_prm_rmw_mod_reg_bits(mask, mask, prm_mod, OMAP2_RM_RSTCTRL); return 0; } @@ -140,15 +140,15 @@ int omap2_prm_deassert_hardreset(s16 prm_mod, u8 shift) mask = 1 << shift; /* Check the current status to avoid de-asserting the line twice */ - if (prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) + if (omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTCTRL, mask) == 0) return -EEXIST; /* Clear the reset status by writing 1 to the status bit */ - prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); + omap2_prm_rmw_mod_reg_bits(0xffffffff, mask, prm_mod, OMAP2_RM_RSTST); /* de-assert the reset control line */ - prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); + omap2_prm_rmw_mod_reg_bits(mask, 0, prm_mod, OMAP2_RM_RSTCTRL); /* wait the status to be set */ - omap_test_timeout(prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, + omap_test_timeout(omap2_prm_read_mod_bits_shift(prm_mod, OMAP2_RM_RSTST, mask), MAX_MODULE_HARDRESET_WAIT, c); diff --git a/arch/arm/mach-omap2/prm2xxx_3xxx.h b/arch/arm/mach-omap2/prm2xxx_3xxx.h index ab28517c82ce..53d44f6e3736 100644 --- a/arch/arm/mach-omap2/prm2xxx_3xxx.h +++ b/arch/arm/mach-omap2/prm2xxx_3xxx.h @@ -230,12 +230,12 @@ #ifndef __ASSEMBLER__ /* Power/reset management domain register get/set */ -extern u32 prm_read_mod_reg(s16 module, u16 idx); -extern void prm_write_mod_reg(u32 val, s16 module, u16 idx); -extern u32 prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); -extern u32 prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); -extern u32 prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); -extern u32 prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); +extern u32 omap2_prm_read_mod_reg(s16 module, u16 idx); +extern void omap2_prm_write_mod_reg(u32 val, s16 module, u16 idx); +extern u32 omap2_prm_rmw_mod_reg_bits(u32 mask, u32 bits, s16 module, s16 idx); +extern u32 omap2_prm_set_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_prm_clear_mod_reg_bits(u32 bits, s16 module, s16 idx); +extern u32 omap2_prm_read_mod_bits_shift(s16 domain, s16 idx, u32 mask); /* These omap2_ PRM functions apply to both OMAP2 and 3 */ extern int omap2_prm_is_hardreset_asserted(s16 prm_mod, u8 shift); diff --git a/arch/arm/mach-omap2/sdrc2xxx.c b/arch/arm/mach-omap2/sdrc2xxx.c index 64778b6240c1..ccdb010f169d 100644 --- a/arch/arm/mach-omap2/sdrc2xxx.c +++ b/arch/arm/mach-omap2/sdrc2xxx.c @@ -99,6 +99,10 @@ u32 omap2xxx_sdrc_reprogram(u32 level, u32 force) m_type = omap2xxx_sdrc_get_type(); local_irq_save(flags); + /* + * XXX These calls should be abstracted out through a + * prm2xxx.c function + */ if (cpu_is_omap2420()) __raw_writel(0xffff, OMAP2420_PRCM_VOLTSETUP); else diff --git a/arch/arm/mach-omap2/serial.c b/arch/arm/mach-omap2/serial.c index 26770d80419e..c8740ba4fba5 100644 --- a/arch/arm/mach-omap2/serial.c +++ b/arch/arm/mach-omap2/serial.c @@ -490,6 +490,7 @@ static void omap_uart_idle_init(struct omap_uart_state *uart) u32 wk_mask = 0; u32 padconf = 0; + /* XXX These PRM accesses do not belong here */ uart->wk_en = OMAP34XX_PRM_REGADDR(mod, PM_WKEN1); uart->wk_st = OMAP34XX_PRM_REGADDR(mod, PM_WKST1); switch (uart->num) { diff --git a/arch/arm/plat-omap/mcbsp.c b/arch/arm/plat-omap/mcbsp.c index 95449b90074d..b5a6e178a7f9 100644 --- a/arch/arm/plat-omap/mcbsp.c +++ b/arch/arm/plat-omap/mcbsp.c @@ -236,9 +236,9 @@ static void omap_st_on(struct omap_mcbsp *mcbsp) * Sidetone uses McBSP ICLK - which must not idle when sidetones * are enabled or sidetones start sounding ugly. */ - w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); + w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); w &= ~(1 << (mcbsp->id - 2)); - cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); + omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); /* Enable McBSP Sidetone */ w = MCBSP_READ(mcbsp, SSELCR); @@ -265,9 +265,9 @@ static void omap_st_off(struct omap_mcbsp *mcbsp) w = MCBSP_READ(mcbsp, SSELCR); MCBSP_WRITE(mcbsp, SSELCR, w & ~(SIDETONEEN)); - w = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); + w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); w |= 1 << (mcbsp->id - 2); - cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); + omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); } static void omap_st_fir_write(struct omap_mcbsp *mcbsp, s16 *fir) -- cgit From 1540f214065982e6cbc6b8da1fe65a15e358f7c5 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 21:05:15 -0700 Subject: OMAP2+: clockdomain: move header file from plat-omap to mach-omap2 The OMAP clockdomain code and data is all OMAP2+-specific. This seems unlikely to change any time soon. Move plat-omap/include/plat/clockdomain.h to mach-omap2/clockdomain.h. The primary point of doing this is to remove the temptation for unrelated upper-layer code to access clockdomain code and data directly. DSPBridge also uses the clockdomain headers for some reason, so, modify it also. The DSPBridge code should not be including the clockdomain headers; these should be removed. Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Omar Ramirez Luna Cc: Felipe Contreras Cc: Greg Kroah-Hartman Tested-by: Rajendra Nayak Tested-by: Santosh Shilimkar --- arch/arm/mach-omap2/clock.c | 2 +- arch/arm/mach-omap2/clockdomain.c | 2 +- arch/arm/mach-omap2/clockdomain.h | 149 ++++++++++++++++++++++ arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c | 2 +- arch/arm/mach-omap2/clockdomains44xx_data.c | 2 +- arch/arm/mach-omap2/cpuidle34xx.c | 2 +- arch/arm/mach-omap2/io.c | 2 +- arch/arm/mach-omap2/omap_hwmod.c | 2 +- arch/arm/mach-omap2/pm-debug.c | 2 +- arch/arm/mach-omap2/pm.c | 2 +- arch/arm/mach-omap2/pm24xx.c | 2 +- arch/arm/mach-omap2/pm34xx.c | 2 +- arch/arm/mach-omap2/powerdomain.c | 2 +- arch/arm/plat-omap/include/plat/clockdomain.h | 151 ----------------------- drivers/staging/tidspbridge/core/_tiomap.h | 7 +- 15 files changed, 167 insertions(+), 164 deletions(-) create mode 100644 arch/arm/mach-omap2/clockdomain.h delete mode 100644 arch/arm/plat-omap/include/plat/clockdomain.h (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index cda2f1da2e1f..2a2f15213add 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c @@ -24,7 +24,7 @@ #include #include -#include +#include "clockdomain.h" #include #include diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index e5605c21ad38..650bf685dd99 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -35,7 +35,7 @@ #include #include -#include +#include "clockdomain.h" #include /* clkdm_list contains all registered struct clockdomains */ diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h new file mode 100644 index 000000000000..372c64669868 --- /dev/null +++ b/arch/arm/mach-omap2/clockdomain.h @@ -0,0 +1,149 @@ +/* + * arch/arm/plat-omap/include/mach/clockdomain.h + * + * OMAP2/3 clockdomain framework functions + * + * Copyright (C) 2008 Texas Instruments, Inc. + * Copyright (C) 2008-2010 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H +#define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAIN_H + +#include + +#include +#include +#include + +/* Clockdomain capability flags */ +#define CLKDM_CAN_FORCE_SLEEP (1 << 0) +#define CLKDM_CAN_FORCE_WAKEUP (1 << 1) +#define CLKDM_CAN_ENABLE_AUTO (1 << 2) +#define CLKDM_CAN_DISABLE_AUTO (1 << 3) + +#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) +#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) +#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP) + +/** + * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode + * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only + * @omap_chip: OMAP chip types that this autodep is valid on + * + * A clockdomain that should have wkdeps and sleepdeps added when a + * clockdomain should stay active in hwsup mode; and conversely, + * removed when the clockdomain should be allowed to go inactive in + * hwsup mode. + * + * Autodeps are deprecated and should be removed after + * omap_hwmod-based fine-grained module idle control is added. + */ +struct clkdm_autodep { + union { + const char *name; + struct clockdomain *ptr; + } clkdm; + const struct omap_chip_id omap_chip; +}; + +/** + * struct clkdm_dep - encode dependencies between clockdomains + * @clkdm_name: clockdomain name + * @clkdm: pointer to the struct clockdomain of @clkdm_name + * @omap_chip: OMAP chip types that this dependency is valid on + * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake + * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle + * + * Statically defined. @clkdm is resolved from @clkdm_name at runtime and + * should not be pre-initialized. + * + * XXX Should also include hardware (fixed) dependencies. + */ +struct clkdm_dep { + const char *clkdm_name; + struct clockdomain *clkdm; + atomic_t wkdep_usecount; + atomic_t sleepdep_usecount; + const struct omap_chip_id omap_chip; +}; + +/** + * struct clockdomain - OMAP clockdomain + * @name: clockdomain name + * @pwrdm: powerdomain containing this clockdomain + * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain + * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg + * @flags: Clockdomain capability flags + * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit + * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers + * @cm_inst: (OMAP4 only) CM instance register offset + * @clkdm_offs: (OMAP4 only) CM clockdomain register offset + * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up + * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact + * @omap_chip: OMAP chip types that this clockdomain is valid on + * @usecount: Usecount tracking + * @node: list_head to link all clockdomains together + * + * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only) + * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance + * definitions (OMAP4 only) + * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance + * definitions (OMAP4 only) + */ +struct clockdomain { + const char *name; + union { + const char *name; + struct powerdomain *ptr; + } pwrdm; +#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) + const u16 clktrctrl_mask; +#endif + const u8 flags; + const u8 dep_bit; + const u8 prcm_partition; + const s16 cm_inst; + const u16 clkdm_offs; + struct clkdm_dep *wkdep_srcs; + struct clkdm_dep *sleepdep_srcs; + const struct omap_chip_id omap_chip; + atomic_t usecount; + struct list_head node; +}; + +void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); +struct clockdomain *clkdm_lookup(const char *name); + +int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), + void *user); +struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); + +int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_clear_all_wkdeps(struct clockdomain *clkdm); +int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); +int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); + +void omap2_clkdm_allow_idle(struct clockdomain *clkdm); +void omap2_clkdm_deny_idle(struct clockdomain *clkdm); + +int omap2_clkdm_wakeup(struct clockdomain *clkdm); +int omap2_clkdm_sleep(struct clockdomain *clkdm); + +int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); +int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); + +extern void __init omap2_clockdomains_init(void); +extern void __init omap44xx_clockdomains_init(void); + +#endif diff --git a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c index 6e9ec49d637f..e4a7133ea3b3 100644 --- a/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/clockdomains2xxx_3xxx_data.c @@ -35,7 +35,7 @@ #include #include -#include +#include "clockdomain.h" #include "prm2xxx_3xxx.h" #include "cm2xxx_3xxx.h" #include "cm-regbits-24xx.h" diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c index 2d3d1ef23814..51920fc7fc52 100644 --- a/arch/arm/mach-omap2/clockdomains44xx_data.c +++ b/arch/arm/mach-omap2/clockdomains44xx_data.c @@ -26,7 +26,7 @@ #include #include -#include +#include "clockdomain.h" #include "cm1_44xx.h" #include "cm2_44xx.h" diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index 0fb619c52588..f518270b3e83 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include "clockdomain.h" #include #include "pm.h" diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index ba766576e03e..545182d9faa6 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -41,7 +41,7 @@ #include #include -#include +#include "clockdomain.h" #include #include diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index 1312ce2913a5..e1358ba51395 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -139,7 +139,7 @@ #include #include -#include +#include "clockdomain.h" #include #include #include diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 1a4efb5e435a..3f989896a36c 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -30,7 +30,7 @@ #include #include #include -#include +#include "clockdomain.h" #include #include "cm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 6ec2ee12272a..24228e9dd496 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -19,7 +19,7 @@ #include #include -#include +#include "clockdomain.h" static struct omap_device_pm_latency *pm_lats; diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index bf0c36b239f9..f6aef7687b8a 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -51,7 +51,7 @@ #include "control.h" #include -#include +#include "clockdomain.h" #ifdef CONFIG_SUSPEND static suspend_state_t suspend_state = PM_SUSPEND_ON; diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 1ca6ef4c25b3..0fae3d6b76e8 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -31,7 +31,7 @@ #include #include -#include +#include "clockdomain.h" #include #include #include diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index a76ad3f0ca65..7eb7ba49d6bf 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -27,7 +27,7 @@ #include #include -#include +#include "clockdomain.h" #include #include "pm.h" diff --git a/arch/arm/plat-omap/include/plat/clockdomain.h b/arch/arm/plat-omap/include/plat/clockdomain.h deleted file mode 100644 index e91ae92f217c..000000000000 --- a/arch/arm/plat-omap/include/plat/clockdomain.h +++ /dev/null @@ -1,151 +0,0 @@ -/* - * arch/arm/plat-omap/include/mach/clockdomain.h - * - * OMAP2/3 clockdomain framework functions - * - * Copyright (C) 2008 Texas Instruments, Inc. - * Copyright (C) 2008-2010 Nokia Corporation - * - * Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * XXX This should be moved to mach-omap2/ at the earliest opportunity. - */ - -#ifndef __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H -#define __ASM_ARM_ARCH_OMAP_CLOCKDOMAIN_H - -#include - -#include -#include -#include - -/* Clockdomain capability flags */ -#define CLKDM_CAN_FORCE_SLEEP (1 << 0) -#define CLKDM_CAN_FORCE_WAKEUP (1 << 1) -#define CLKDM_CAN_ENABLE_AUTO (1 << 2) -#define CLKDM_CAN_DISABLE_AUTO (1 << 3) - -#define CLKDM_CAN_HWSUP (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO) -#define CLKDM_CAN_SWSUP (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP) -#define CLKDM_CAN_HWSUP_SWSUP (CLKDM_CAN_SWSUP | CLKDM_CAN_HWSUP) - -/** - * struct clkdm_autodep - clkdm deps to add when entering/exiting hwsup mode - * @clkdm: clockdomain to add wkdep+sleepdep on - set name member only - * @omap_chip: OMAP chip types that this autodep is valid on - * - * A clockdomain that should have wkdeps and sleepdeps added when a - * clockdomain should stay active in hwsup mode; and conversely, - * removed when the clockdomain should be allowed to go inactive in - * hwsup mode. - * - * Autodeps are deprecated and should be removed after - * omap_hwmod-based fine-grained module idle control is added. - */ -struct clkdm_autodep { - union { - const char *name; - struct clockdomain *ptr; - } clkdm; - const struct omap_chip_id omap_chip; -}; - -/** - * struct clkdm_dep - encode dependencies between clockdomains - * @clkdm_name: clockdomain name - * @clkdm: pointer to the struct clockdomain of @clkdm_name - * @omap_chip: OMAP chip types that this dependency is valid on - * @wkdep_usecount: Number of wakeup dependencies causing this clkdm to wake - * @sleepdep_usecount: Number of sleep deps that could prevent clkdm from idle - * - * Statically defined. @clkdm is resolved from @clkdm_name at runtime and - * should not be pre-initialized. - * - * XXX Should also include hardware (fixed) dependencies. - */ -struct clkdm_dep { - const char *clkdm_name; - struct clockdomain *clkdm; - atomic_t wkdep_usecount; - atomic_t sleepdep_usecount; - const struct omap_chip_id omap_chip; -}; - -/** - * struct clockdomain - OMAP clockdomain - * @name: clockdomain name - * @pwrdm: powerdomain containing this clockdomain - * @clktrctrl_reg: CLKSTCTRL reg for the given clock domain - * @clktrctrl_mask: CLKTRCTRL/AUTOSTATE field mask in CM_CLKSTCTRL reg - * @flags: Clockdomain capability flags - * @dep_bit: Bit shift of this clockdomain's PM_WKDEP/CM_SLEEPDEP bit - * @prcm_partition: (OMAP4 only) PRCM partition ID for this clkdm's registers - * @cm_inst: (OMAP4 only) CM instance register offset - * @clkdm_offs: (OMAP4 only) CM clockdomain register offset - * @wkdep_srcs: Clockdomains that can be told to wake this powerdomain up - * @sleepdep_srcs: Clockdomains that can be told to keep this clkdm from inact - * @omap_chip: OMAP chip types that this clockdomain is valid on - * @usecount: Usecount tracking - * @node: list_head to link all clockdomains together - * - * @prcm_partition should be a macro from mach-omap2/prcm44xx.h (OMAP4 only) - * @cm_inst should be a macro ending in _INST from the OMAP4 CM instance - * definitions (OMAP4 only) - * @clkdm_offs should be a macro ending in _CDOFFS from the OMAP4 CM instance - * definitions (OMAP4 only) - */ -struct clockdomain { - const char *name; - union { - const char *name; - struct powerdomain *ptr; - } pwrdm; -#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) - const u16 clktrctrl_mask; -#endif - const u8 flags; - const u8 dep_bit; - const u8 prcm_partition; - const s16 cm_inst; - const u16 clkdm_offs; - struct clkdm_dep *wkdep_srcs; - struct clkdm_dep *sleepdep_srcs; - const struct omap_chip_id omap_chip; - atomic_t usecount; - struct list_head node; -}; - -void clkdm_init(struct clockdomain **clkdms, struct clkdm_autodep *autodeps); -struct clockdomain *clkdm_lookup(const char *name); - -int clkdm_for_each(int (*fn)(struct clockdomain *clkdm, void *user), - void *user); -struct powerdomain *clkdm_get_pwrdm(struct clockdomain *clkdm); - -int clkdm_add_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_del_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_read_wkdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_clear_all_wkdeps(struct clockdomain *clkdm); -int clkdm_add_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_del_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_read_sleepdep(struct clockdomain *clkdm1, struct clockdomain *clkdm2); -int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm); - -void omap2_clkdm_allow_idle(struct clockdomain *clkdm); -void omap2_clkdm_deny_idle(struct clockdomain *clkdm); - -int omap2_clkdm_wakeup(struct clockdomain *clkdm); -int omap2_clkdm_sleep(struct clockdomain *clkdm); - -int omap2_clkdm_clk_enable(struct clockdomain *clkdm, struct clk *clk); -int omap2_clkdm_clk_disable(struct clockdomain *clkdm, struct clk *clk); - -extern void __init omap2_clockdomains_init(void); -extern void __init omap44xx_clockdomains_init(void); - -#endif diff --git a/drivers/staging/tidspbridge/core/_tiomap.h b/drivers/staging/tidspbridge/core/_tiomap.h index 7fac488f7f48..a3190e74ff74 100644 --- a/drivers/staging/tidspbridge/core/_tiomap.h +++ b/drivers/staging/tidspbridge/core/_tiomap.h @@ -19,8 +19,13 @@ #ifndef _TIOMAP_ #define _TIOMAP_ +/* + * XXX These powerdomain.h/clockdomain.h includes are wrong and should + * be removed. No driver should call pwrdm_* or clkdm_* functions + * directly; they should rely on OMAP core code to do this. + */ #include -#include +#include /* * XXX These mach-omap2/ includes are wrong and should be removed. No * driver should read or write to PRM/CM registers directly; they -- cgit From 72e06d087204f3bc9acf281717b90ebf0b9731f7 Mon Sep 17 00:00:00 2001 From: Paul Walmsley Date: Tue, 21 Dec 2010 21:05:16 -0700 Subject: OMAP2+: powerdomain: move header file from plat-omap to mach-omap2 The OMAP powerdomain code and data is all OMAP2+-specific. This seems unlikely to change any time soon. Move plat-omap/include/plat/powerdomain.h to mach-omap2/powerdomain.h. The primary point of doing this is to remove the temptation for unrelated upper-layer code to access powerdomain code and data directly. As part of this process, remove the references to powerdomain data from the GPIO "driver" and the OMAP PM no-op layer, both in plat-omap. Change the DSPBridge code to point to the new location for the powerdomain headers. The DSPBridge code should not be including the powerdomain headers; these should be removed. Signed-off-by: Paul Walmsley Cc: Kevin Hilman Cc: Omar Ramirez Luna Cc: Felipe Contreras Cc: Greg Kroah-Hartman --- arch/arm/mach-omap2/clockdomain.c | 2 +- arch/arm/mach-omap2/clockdomain.h | 2 +- arch/arm/mach-omap2/cpuidle34xx.c | 2 +- arch/arm/mach-omap2/io.c | 2 +- arch/arm/mach-omap2/omap_hwmod.c | 2 +- arch/arm/mach-omap2/pm-debug.c | 2 +- arch/arm/mach-omap2/pm.c | 2 +- arch/arm/mach-omap2/pm.h | 2 +- arch/arm/mach-omap2/pm24xx.c | 4 +- arch/arm/mach-omap2/pm34xx.c | 6 +- arch/arm/mach-omap2/pm44xx.c | 2 +- arch/arm/mach-omap2/powerdomain-common.c | 1 - arch/arm/mach-omap2/powerdomain.c | 2 +- arch/arm/mach-omap2/powerdomain.h | 232 +++++++++++++++++++++++ arch/arm/mach-omap2/powerdomain2xxx_3xxx.c | 2 +- arch/arm/mach-omap2/powerdomain44xx.c | 3 +- arch/arm/mach-omap2/powerdomains.h | 30 --- arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c | 4 +- arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h | 2 +- arch/arm/mach-omap2/powerdomains2xxx_data.c | 3 +- arch/arm/mach-omap2/powerdomains3xxx_data.c | 3 +- arch/arm/mach-omap2/powerdomains44xx_data.c | 3 +- arch/arm/plat-omap/gpio.c | 5 +- arch/arm/plat-omap/include/plat/gpio.h | 2 +- arch/arm/plat-omap/include/plat/omap-pm.h | 2 - arch/arm/plat-omap/include/plat/powerdomain.h | 219 --------------------- arch/arm/plat-omap/omap-pm-noop.c | 2 - drivers/staging/tidspbridge/core/_tiomap.h | 2 +- 28 files changed, 259 insertions(+), 286 deletions(-) create mode 100644 arch/arm/mach-omap2/powerdomain.h delete mode 100644 arch/arm/mach-omap2/powerdomains.h delete mode 100644 arch/arm/plat-omap/include/plat/powerdomain.h (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c index 650bf685dd99..e20b98636ab4 100644 --- a/arch/arm/mach-omap2/clockdomain.c +++ b/arch/arm/mach-omap2/clockdomain.c @@ -34,7 +34,7 @@ #include "prcm44xx.h" #include -#include +#include "powerdomain.h" #include "clockdomain.h" #include diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h index 372c64669868..de3faa20b46b 100644 --- a/arch/arm/mach-omap2/clockdomain.h +++ b/arch/arm/mach-omap2/clockdomain.h @@ -18,7 +18,7 @@ #include -#include +#include "powerdomain.h" #include #include diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c index f518270b3e83..f3e043fe5eb8 100644 --- a/arch/arm/mach-omap2/cpuidle34xx.c +++ b/arch/arm/mach-omap2/cpuidle34xx.c @@ -27,7 +27,7 @@ #include #include -#include +#include "powerdomain.h" #include "clockdomain.h" #include diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 545182d9faa6..e66687b0b9de 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c @@ -39,7 +39,7 @@ #include "io.h" #include -#include +#include "powerdomain.h" #include "clockdomain.h" #include diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c index e1358ba51395..12856eb7b179 100644 --- a/arch/arm/mach-omap2/omap_hwmod.c +++ b/arch/arm/mach-omap2/omap_hwmod.c @@ -140,7 +140,7 @@ #include #include #include "clockdomain.h" -#include +#include "powerdomain.h" #include #include #include diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index 3f989896a36c..e535082b0c2e 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -29,7 +29,7 @@ #include #include -#include +#include "powerdomain.h" #include "clockdomain.h" #include diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c index 24228e9dd496..227a211921c3 100644 --- a/arch/arm/mach-omap2/pm.c +++ b/arch/arm/mach-omap2/pm.c @@ -18,7 +18,7 @@ #include #include -#include +#include "powerdomain.h" #include "clockdomain.h" static struct omap_device_pm_latency *pm_lats; diff --git a/arch/arm/mach-omap2/pm.h b/arch/arm/mach-omap2/pm.h index 8b4f45eba1b5..482df7fc1585 100644 --- a/arch/arm/mach-omap2/pm.h +++ b/arch/arm/mach-omap2/pm.h @@ -11,7 +11,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_PM_H #define __ARCH_ARM_MACH_OMAP2_PM_H -#include +#include "powerdomain.h" extern void *omap3_secure_ram_storage; extern void omap3_pm_off_mode_enable(int); diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index f6aef7687b8a..2844b84f8d46 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c @@ -50,7 +50,7 @@ #include "pm.h" #include "control.h" -#include +#include "powerdomain.h" #include "clockdomain.h" #ifdef CONFIG_SUSPEND @@ -120,7 +120,7 @@ static void omap2_enter_full_retention(void) l = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0) | OMAP24XX_USBSTANDBYCTRL; omap_ctrl_writel(l, OMAP2_CONTROL_DEVCONF0); - omap2_gpio_prepare_for_idle(PWRDM_POWER_RET); + omap2_gpio_prepare_for_idle(0); if (omap2_pm_debug) { omap2_pm_dump(0, 0, 0); diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 0fae3d6b76e8..5efd1fb8c640 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c @@ -32,7 +32,7 @@ #include #include "clockdomain.h" -#include +#include "powerdomain.h" #include #include #include @@ -360,6 +360,7 @@ void omap_sram_idle(void) int mpu_next_state = PWRDM_POWER_ON; int per_next_state = PWRDM_POWER_ON; int core_next_state = PWRDM_POWER_ON; + int per_going_off; int core_prev_state, per_prev_state; u32 sdrc_pwr = 0; @@ -411,9 +412,10 @@ void omap_sram_idle(void) /* PER */ if (per_next_state < PWRDM_POWER_ON) { + per_going_off = (per_next_state == PWRDM_POWER_OFF) ? 1 : 0; omap_uart_prepare_idle(2); omap_uart_prepare_idle(3); - omap2_gpio_prepare_for_idle(per_next_state); + omap2_gpio_prepare_for_idle(per_going_off); if (per_next_state == PWRDM_POWER_OFF) omap3_per_save_context(); } diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c index 6aff9961e35d..e9f4862c4de4 100644 --- a/arch/arm/mach-omap2/pm44xx.c +++ b/arch/arm/mach-omap2/pm44xx.c @@ -16,7 +16,7 @@ #include #include -#include +#include "powerdomain.h" #include struct power_state { diff --git a/arch/arm/mach-omap2/powerdomain-common.c b/arch/arm/mach-omap2/powerdomain-common.c index cb01c7a3689a..171fccd208c7 100644 --- a/arch/arm/mach-omap2/powerdomain-common.c +++ b/arch/arm/mach-omap2/powerdomain-common.c @@ -20,7 +20,6 @@ #include "cm-regbits-44xx.h" #include "prm-regbits-34xx.h" #include "prm-regbits-44xx.h" -#include "powerdomains.h" /* * OMAP3 and OMAP4 specific register bit initialisations diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c index 7eb7ba49d6bf..06ef60eebebd 100644 --- a/arch/arm/mach-omap2/powerdomain.c +++ b/arch/arm/mach-omap2/powerdomain.c @@ -26,7 +26,7 @@ #include "prm44xx.h" #include -#include +#include "powerdomain.h" #include "clockdomain.h" #include diff --git a/arch/arm/mach-omap2/powerdomain.h b/arch/arm/mach-omap2/powerdomain.h new file mode 100644 index 000000000000..35b5b4800a43 --- /dev/null +++ b/arch/arm/mach-omap2/powerdomain.h @@ -0,0 +1,232 @@ +/* + * OMAP2/3/4 powerdomain control + * + * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc. + * Copyright (C) 2007-2010 Nokia Corporation + * + * Paul Walmsley + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * XXX This should be moved to the mach-omap2/ directory at the earliest + * opportunity. + */ + +#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H +#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H + +#include +#include + +#include + +#include + +/* Powerdomain basic power states */ +#define PWRDM_POWER_OFF 0x0 +#define PWRDM_POWER_RET 0x1 +#define PWRDM_POWER_INACTIVE 0x2 +#define PWRDM_POWER_ON 0x3 + +#define PWRDM_MAX_PWRSTS 4 + +/* Powerdomain allowable state bitfields */ +#define PWRSTS_ON (1 << PWRDM_POWER_ON) +#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) +#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ + (1 << PWRDM_POWER_ON)) + +#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ + (1 << PWRDM_POWER_RET)) + +#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ + (1 << PWRDM_POWER_ON)) + +#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) + + +/* Powerdomain flags */ +#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ +#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits + * in MEM bank 1 position. This is + * true for OMAP3430 + */ +#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* + * support to transition from a + * sleep state to a lower sleep + * state without waking up the + * powerdomain + */ + +/* + * Number of memory banks that are power-controllable. On OMAP4430, the + * maximum is 5. + */ +#define PWRDM_MAX_MEM_BANKS 5 + +/* + * Maximum number of clockdomains that can be associated with a powerdomain. + * CORE powerdomain on OMAP4 is the worst case + */ +#define PWRDM_MAX_CLKDMS 9 + +/* XXX A completely arbitrary number. What is reasonable here? */ +#define PWRDM_TRANSITION_BAILOUT 100000 + +struct clockdomain; +struct powerdomain; + +/** + * struct powerdomain - OMAP powerdomain + * @name: Powerdomain name + * @omap_chip: represents the OMAP chip types containing this pwrdm + * @prcm_offs: the address offset from CM_BASE/PRM_BASE + * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs + * @pwrsts: Possible powerdomain power states + * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION + * @flags: Powerdomain flags + * @banks: Number of software-controllable memory banks in this powerdomain + * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION + * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON + * @pwrdm_clkdms: Clockdomains in this powerdomain + * @node: list_head linking all powerdomains + * @state: + * @state_counter: + * @timer: + * @state_timer: + * + * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. + */ +struct powerdomain { + const char *name; + const struct omap_chip_id omap_chip; + const s16 prcm_offs; + const u8 pwrsts; + const u8 pwrsts_logic_ret; + const u8 flags; + const u8 banks; + const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; + const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; + const u8 prcm_partition; + struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; + struct list_head node; + int state; + unsigned state_counter[PWRDM_MAX_PWRSTS]; + unsigned ret_logic_off_counter; + unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; + +#ifdef CONFIG_PM_DEBUG + s64 timer; + s64 state_timer[PWRDM_MAX_PWRSTS]; +#endif +}; + +/** + * struct pwrdm_ops - Arch specfic function implementations + * @pwrdm_set_next_pwrst: Set the target power state for a pd + * @pwrdm_read_next_pwrst: Read the target power state set for a pd + * @pwrdm_read_pwrst: Read the current power state of a pd + * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd + * @pwrdm_set_logic_retst: Set the logic state in RET for a pd + * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd + * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd + * @pwrdm_read_logic_pwrst: Read the current logic state of a pd + * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd + * @pwrdm_read_logic_retst: Read the logic state in RET for a pd + * @pwrdm_read_mem_pwrst: Read the current memory state of a pd + * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd + * @pwrdm_read_mem_retst: Read the memory state in RET for a pd + * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd + * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd + * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd + * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep + * @pwrdm_wait_transition: Wait for a pd state transition to complete + */ +struct pwrdm_ops { + int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); + int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); + int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); + int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); + int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); + int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); + int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); + int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); + int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); + int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); + int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); + int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); + int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); +}; + +void pwrdm_fw_init(void); +void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); + +struct powerdomain *pwrdm_lookup(const char *name); + +int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), + void *user); +int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), + void *user); + +int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); +int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); +int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, + int (*fn)(struct powerdomain *pwrdm, + struct clockdomain *clkdm)); + +int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); + +int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); +int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); +int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); + +int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); +int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); +int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); + +int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); +int pwrdm_read_logic_retst(struct powerdomain *pwrdm); +int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); +int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); +int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); + +int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); +int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); +bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); + +int pwrdm_wait_transition(struct powerdomain *pwrdm); + +int pwrdm_state_switch(struct powerdomain *pwrdm); +int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); +int pwrdm_pre_transition(void); +int pwrdm_post_transition(void); +int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); + +extern void omap2xxx_powerdomains_init(void); +extern void omap3xxx_powerdomains_init(void); +extern void omap44xx_powerdomains_init(void); + +extern struct pwrdm_ops omap2_pwrdm_operations; +extern struct pwrdm_ops omap3_pwrdm_operations; +extern struct pwrdm_ops omap4_pwrdm_operations; + +/* Common Internal functions used across OMAP rev's */ +extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); +extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); +extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); + +extern struct powerdomain wkup_omap2_pwrdm; +extern struct powerdomain gfx_omap2_pwrdm; + + +#endif diff --git a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c index b5e9e4d18b8c..d5233890370c 100644 --- a/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c +++ b/arch/arm/mach-omap2/powerdomain2xxx_3xxx.c @@ -18,8 +18,8 @@ #include +#include "powerdomain.h" #include "prm-regbits-34xx.h" -#include "powerdomains.h" #include "prm.h" #include "prm-regbits-24xx.h" #include "prm-regbits-34xx.h" diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c index 28bf5e3b000c..a7880af4b3d9 100644 --- a/arch/arm/mach-omap2/powerdomain44xx.c +++ b/arch/arm/mach-omap2/powerdomain44xx.c @@ -16,13 +16,12 @@ #include #include -#include +#include "powerdomain.h" #include #include "prm2xxx_3xxx.h" #include "prm44xx.h" #include "prminst44xx.h" #include "prm-regbits-44xx.h" -#include "powerdomains.h" static int omap4_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) { diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h deleted file mode 100644 index f83adaf889ee..000000000000 --- a/arch/arm/mach-omap2/powerdomains.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * OMAP2+ powerdomain prototypes - * - * Copyright (C) 2010 Texas Instruments, Inc. - * - * Rajendra Nayak - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#ifndef ARCH_ARM_MACH_OMAP2_POWERDOMAINS_H -#define ARCH_ARM_MACH_OMAP2_POWERDOMAINS_H - -#include - -extern struct pwrdm_ops omap2_pwrdm_operations; -extern struct pwrdm_ops omap3_pwrdm_operations; -extern struct pwrdm_ops omap4_pwrdm_operations; - -/* Common Internal functions used across OMAP rev's */ -extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank); -extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank); -extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank); - -extern struct powerdomain wkup_omap2_pwrdm; -extern struct powerdomain gfx_omap2_pwrdm; - -#endif diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c index 14c6ef7e01e3..5b4dd971320a 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.c @@ -45,13 +45,11 @@ * address offset is different between the C55 and C64 DSPs. */ -#include +#include "powerdomain.h" #include "prcm-common.h" #include "prm.h" -#include "powerdomains.h" - /* OMAP2/3-common powerdomains */ /* diff --git a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h index 45d684a3bf2b..fa311669d53d 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h +++ b/arch/arm/mach-omap2/powerdomains2xxx_3xxx_data.h @@ -14,7 +14,7 @@ #ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H #define __ARCH_ARM_MACH_OMAP2_POWERDOMAINS2XXX_3XXX_DATA_H -#include +#include "powerdomain.h" extern struct powerdomain gfx_omap2_pwrdm; extern struct powerdomain wkup_omap2_pwrdm; diff --git a/arch/arm/mach-omap2/powerdomains2xxx_data.c b/arch/arm/mach-omap2/powerdomains2xxx_data.c index e136895e0a37..9b1a33500577 100644 --- a/arch/arm/mach-omap2/powerdomains2xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains2xxx_data.c @@ -14,9 +14,8 @@ #include #include -#include +#include "powerdomain.h" #include "powerdomains2xxx_3xxx_data.h" -#include "powerdomains.h" #include "prcm-common.h" #include "prm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/powerdomains3xxx_data.c b/arch/arm/mach-omap2/powerdomains3xxx_data.c index 1830c63ae676..e1bec562625b 100644 --- a/arch/arm/mach-omap2/powerdomains3xxx_data.c +++ b/arch/arm/mach-omap2/powerdomains3xxx_data.c @@ -14,9 +14,8 @@ #include #include -#include +#include "powerdomain.h" #include "powerdomains2xxx_3xxx_data.h" -#include "powerdomains.h" #include "prcm-common.h" #include "prm2xxx_3xxx.h" diff --git a/arch/arm/mach-omap2/powerdomains44xx_data.c b/arch/arm/mach-omap2/powerdomains44xx_data.c index 823f4770f947..5fdf485a022a 100644 --- a/arch/arm/mach-omap2/powerdomains44xx_data.c +++ b/arch/arm/mach-omap2/powerdomains44xx_data.c @@ -22,8 +22,7 @@ #include #include -#include -#include "powerdomains.h" +#include "powerdomain.h" #include "prcm-common.h" #include "prcm44xx.h" diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c index 8d493b992e70..1f98e0b94847 100644 --- a/arch/arm/plat-omap/gpio.c +++ b/arch/arm/plat-omap/gpio.c @@ -29,7 +29,6 @@ #include #include #include -#include /* * OMAP1510 GPIO registers @@ -1864,7 +1863,7 @@ static struct sys_device omap_gpio_device = { static int workaround_enabled; -void omap2_gpio_prepare_for_idle(int power_state) +void omap2_gpio_prepare_for_idle(int off_mode) { int i, c = 0; int min = 0; @@ -1880,7 +1879,7 @@ void omap2_gpio_prepare_for_idle(int power_state) for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) clk_disable(bank->dbck); - if (power_state > PWRDM_POWER_OFF) + if (!off_mode) continue; /* If going to OFF, remove triggering for all diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index 41ff2f8943f0..d6f9fa0f62af 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h @@ -82,7 +82,7 @@ struct omap_gpio_platform_data { /* TODO: Analyze removing gpio_bank_count usage from driver code */ extern int gpio_bank_count; -extern void omap2_gpio_prepare_for_idle(int power_state); +extern void omap2_gpio_prepare_for_idle(int off_mode); extern void omap2_gpio_resume_after_idle(void); extern void omap_set_gpio_debounce(int gpio, int enable); extern void omap_set_gpio_debounce_time(int gpio, int enable); diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h index 62c3fe918ab2..47d61107ccda 100644 --- a/arch/arm/plat-omap/include/plat/omap-pm.h +++ b/arch/arm/plat-omap/include/plat/omap-pm.h @@ -19,8 +19,6 @@ #include #include -#include "powerdomain.h" - /* * agent_id values for use with omap_pm_set_min_bus_tput(): * diff --git a/arch/arm/plat-omap/include/plat/powerdomain.h b/arch/arm/plat-omap/include/plat/powerdomain.h deleted file mode 100644 index a0d3a30de9fd..000000000000 --- a/arch/arm/plat-omap/include/plat/powerdomain.h +++ /dev/null @@ -1,219 +0,0 @@ -/* - * OMAP2/3/4 powerdomain control - * - * Copyright (C) 2007-2008 Texas Instruments, Inc. - * Copyright (C) 2007-2010 Nokia Corporation - * - * Written by Paul Walmsley - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * XXX This should be moved to the mach-omap2/ directory at the earliest - * opportunity. - */ - -#ifndef ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN -#define ASM_ARM_PLAT_OMAP_INCLUDE_PLAT_POWERDOMAIN - -#include -#include - -#include - -#include - -/* Powerdomain basic power states */ -#define PWRDM_POWER_OFF 0x0 -#define PWRDM_POWER_RET 0x1 -#define PWRDM_POWER_INACTIVE 0x2 -#define PWRDM_POWER_ON 0x3 - -#define PWRDM_MAX_PWRSTS 4 - -/* Powerdomain allowable state bitfields */ -#define PWRSTS_ON (1 << PWRDM_POWER_ON) -#define PWRSTS_OFF (1 << PWRDM_POWER_OFF) -#define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ - (1 << PWRDM_POWER_ON)) - -#define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ - (1 << PWRDM_POWER_RET)) - -#define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ - (1 << PWRDM_POWER_ON)) - -#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) - - -/* Powerdomain flags */ -#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ -#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits - * in MEM bank 1 position. This is - * true for OMAP3430 - */ -#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* - * support to transition from a - * sleep state to a lower sleep - * state without waking up the - * powerdomain - */ - -/* - * Number of memory banks that are power-controllable. On OMAP4430, the - * maximum is 5. - */ -#define PWRDM_MAX_MEM_BANKS 5 - -/* - * Maximum number of clockdomains that can be associated with a powerdomain. - * CORE powerdomain on OMAP4 is the worst case - */ -#define PWRDM_MAX_CLKDMS 9 - -/* XXX A completely arbitrary number. What is reasonable here? */ -#define PWRDM_TRANSITION_BAILOUT 100000 - -struct clockdomain; -struct powerdomain; - -/** - * struct powerdomain - OMAP powerdomain - * @name: Powerdomain name - * @omap_chip: represents the OMAP chip types containing this pwrdm - * @prcm_offs: the address offset from CM_BASE/PRM_BASE - * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs - * @pwrsts: Possible powerdomain power states - * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION - * @flags: Powerdomain flags - * @banks: Number of software-controllable memory banks in this powerdomain - * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION - * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON - * @pwrdm_clkdms: Clockdomains in this powerdomain - * @node: list_head linking all powerdomains - * @state: - * @state_counter: - * @timer: - * @state_timer: - * - * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h. - */ -struct powerdomain { - const char *name; - const struct omap_chip_id omap_chip; - const s16 prcm_offs; - const u8 pwrsts; - const u8 pwrsts_logic_ret; - const u8 flags; - const u8 banks; - const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; - const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; - const u8 prcm_partition; - struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; - struct list_head node; - int state; - unsigned state_counter[PWRDM_MAX_PWRSTS]; - unsigned ret_logic_off_counter; - unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; - -#ifdef CONFIG_PM_DEBUG - s64 timer; - s64 state_timer[PWRDM_MAX_PWRSTS]; -#endif -}; - -/** - * struct pwrdm_ops - Arch specfic function implementations - * @pwrdm_set_next_pwrst: Set the target power state for a pd - * @pwrdm_read_next_pwrst: Read the target power state set for a pd - * @pwrdm_read_pwrst: Read the current power state of a pd - * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd - * @pwrdm_set_logic_retst: Set the logic state in RET for a pd - * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd - * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd - * @pwrdm_read_logic_pwrst: Read the current logic state of a pd - * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd - * @pwrdm_read_logic_retst: Read the logic state in RET for a pd - * @pwrdm_read_mem_pwrst: Read the current memory state of a pd - * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd - * @pwrdm_read_mem_retst: Read the memory state in RET for a pd - * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd - * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd - * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd - * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep - * @pwrdm_wait_transition: Wait for a pd state transition to complete - */ -struct pwrdm_ops { - int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst); - int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst); - int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); - int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst); - int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm); - int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); - int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank); - int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank); - int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm); - int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm); - int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm); - int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm); - int (*pwrdm_wait_transition)(struct powerdomain *pwrdm); -}; - -void pwrdm_fw_init(void); -void pwrdm_init(struct powerdomain **pwrdm_list, struct pwrdm_ops *custom_funcs); - -struct powerdomain *pwrdm_lookup(const char *name); - -int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), - void *user); -int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), - void *user); - -int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); -int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); -int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, - int (*fn)(struct powerdomain *pwrdm, - struct clockdomain *clkdm)); - -int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); - -int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); -int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); -int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); - -int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); -int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); -int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); - -int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); -int pwrdm_read_logic_retst(struct powerdomain *pwrdm); -int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); -int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); -int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); - -int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); -int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); -bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); - -int pwrdm_wait_transition(struct powerdomain *pwrdm); - -int pwrdm_state_switch(struct powerdomain *pwrdm); -int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); -int pwrdm_pre_transition(void); -int pwrdm_post_transition(void); -int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm); - -extern void omap2xxx_powerdomains_init(void); -extern void omap3xxx_powerdomains_init(void); -extern void omap44xx_powerdomains_init(void); - -#endif diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index ca75abb18068..19cb9f5a9f04 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c @@ -24,8 +24,6 @@ /* Interface documentation is in mach/omap-pm.h */ #include -#include - /* * Device-driver-originated constraints (via board-*.c files) */ diff --git a/drivers/staging/tidspbridge/core/_tiomap.h b/drivers/staging/tidspbridge/core/_tiomap.h index a3190e74ff74..1159a500f49d 100644 --- a/drivers/staging/tidspbridge/core/_tiomap.h +++ b/drivers/staging/tidspbridge/core/_tiomap.h @@ -24,7 +24,7 @@ * be removed. No driver should call pwrdm_* or clkdm_* functions * directly; they should rely on OMAP core code to do this. */ -#include +#include #include /* * XXX These mach-omap2/ includes are wrong and should be removed. No -- cgit From 6081dc348f122cdb76093b2fc6cf5742c968cb69 Mon Sep 17 00:00:00 2001 From: Kevin Hilman Date: Tue, 21 Dec 2010 21:31:55 -0700 Subject: OMAP: PM noop: implement context loss count for non-omap_devices For devices which have not (yet) been converted to use omap_device, implement the context loss counter using the "brutal method" as originally proposed by Paul Walmsley[1]. The dummy context loss counter is incremented every time it is checked, but only when off-mode is enabled. When off-mode is disabled, the dummy counter stops incrementing. Tested on 36xx/Zoom3 using MMC driver, which is currently the only in-tree user of this API. This patch should be reverted after all devices are converted to using omap_device. [1] http://marc.info/?l=linux-omap&m=129176260000626&w=2 Signed-off-by: Kevin Hilman [paul@pwsan.com: fixed compile warning; fixed to compile on OMAP1] Signed-off-by: Paul Walmsley --- arch/arm/mach-omap2/pm-debug.c | 5 ++++ arch/arm/plat-omap/include/plat/omap-pm.h | 2 ++ arch/arm/plat-omap/omap-pm-noop.c | 46 ++++++++++++++++++++++++++++++- 3 files changed, 52 insertions(+), 1 deletion(-) (limited to 'arch/arm/mach-omap2/pm-debug.c') diff --git a/arch/arm/mach-omap2/pm-debug.c b/arch/arm/mach-omap2/pm-debug.c index e535082b0c2e..125f56591fb5 100644 --- a/arch/arm/mach-omap2/pm-debug.c +++ b/arch/arm/mach-omap2/pm-debug.c @@ -32,6 +32,7 @@ #include "powerdomain.h" #include "clockdomain.h" #include +#include #include "cm2xxx_3xxx.h" #include "prm2xxx_3xxx.h" @@ -581,6 +582,10 @@ static int option_set(void *data, u64 val) *option = val; if (option == &enable_off_mode) { + if (val) + omap_pm_enable_off_mode(); + else + omap_pm_disable_off_mode(); if (cpu_is_omap34xx()) omap3_pm_off_mode_enable(val); } diff --git a/arch/arm/plat-omap/include/plat/omap-pm.h b/arch/arm/plat-omap/include/plat/omap-pm.h index c07bb44e9e5a..c0a752053039 100644 --- a/arch/arm/plat-omap/include/plat/omap-pm.h +++ b/arch/arm/plat-omap/include/plat/omap-pm.h @@ -354,5 +354,7 @@ unsigned long omap_pm_cpu_get_freq(void); */ u32 omap_pm_get_dev_context_loss_count(struct device *dev); +void omap_pm_enable_off_mode(void); +void omap_pm_disable_off_mode(void); #endif diff --git a/arch/arm/plat-omap/omap-pm-noop.c b/arch/arm/plat-omap/omap-pm-noop.c index af58daddcf50..b0471bb2d47d 100644 --- a/arch/arm/plat-omap/omap-pm-noop.c +++ b/arch/arm/plat-omap/omap-pm-noop.c @@ -26,6 +26,9 @@ #include #include +static bool off_mode_enabled; +static u32 dummy_context_loss_counter; + /* * Device-driver-originated constraints (via board-*.c files) */ @@ -280,10 +283,34 @@ unsigned long omap_pm_cpu_get_freq(void) return 0; } +/** + * omap_pm_enable_off_mode - notify OMAP PM that off-mode is enabled + * + * Intended for use only by OMAP PM core code to notify this layer + * that off mode has been enabled. + */ +void omap_pm_enable_off_mode(void) +{ + off_mode_enabled = true; +} + +/** + * omap_pm_disable_off_mode - notify OMAP PM that off-mode is disabled + * + * Intended for use only by OMAP PM core code to notify this layer + * that off mode has been disabled. + */ +void omap_pm_disable_off_mode(void) +{ + off_mode_enabled = false; +} + /* * Device context loss tracking */ +#ifdef CONFIG_ARCH_OMAP2PLUS + u32 omap_pm_get_dev_context_loss_count(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); @@ -292,13 +319,30 @@ u32 omap_pm_get_dev_context_loss_count(struct device *dev) if (WARN_ON(!dev)) return 0; - count = omap_device_get_context_loss_count(pdev); + if (dev->parent == &omap_device_parent) { + count = omap_device_get_context_loss_count(pdev); + } else { + WARN_ONCE(off_mode_enabled, "omap_pm: using dummy context loss counter; device %s should be converted to omap_device", + dev_name(dev)); + if (off_mode_enabled) + dummy_context_loss_counter++; + count = dummy_context_loss_counter; + } + pr_debug("OMAP PM: context loss count for dev %s = %d\n", dev_name(dev), count); return count; } +#else + +u32 omap_pm_get_dev_context_loss_count(struct device *dev) +{ + return dummy_context_loss_counter; +} + +#endif /* Should be called before clk framework init */ int __init omap_pm_if_early_init(void) -- cgit