From b8a033023994c4e59697bb3b16b441b38f258390 Mon Sep 17 00:00:00 2001 From: Vineet Gupta Date: Wed, 11 Mar 2015 21:42:37 +0530 Subject: ARCv2: barriers ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for kernel proper. SMP barrier is provided by DMB instruction which also guarantees local barrier hence used as backend of smp_*mb() as well as *mb() APIs Also hookup barriers into MMIO accessors to avoid ordering issues in IO Cc: Peter Zijlstra (Intel) Reviewed-by: Will Deacon Signed-off-by: Vineet Gupta --- arch/arc/include/asm/Kbuild | 1 - 1 file changed, 1 deletion(-) (limited to 'arch/arc/include/asm/Kbuild') diff --git a/arch/arc/include/asm/Kbuild b/arch/arc/include/asm/Kbuild index be0c39e76f7c..59e2dd1d434f 100644 --- a/arch/arc/include/asm/Kbuild +++ b/arch/arc/include/asm/Kbuild @@ -1,5 +1,4 @@ generic-y += auxvec.h -generic-y += barrier.h generic-y += bitsperlong.h generic-y += bugs.h generic-y += clkdev.h -- cgit