From 2f802af21f09aeb75651b582079ef9b10b507b1a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 23 Jan 2023 16:15:21 +0100 Subject: ARM: dts: socfpga: align UART node name with bindings Bindings expect UART/serial node names to be "serial". Signed-off-by: Krzysztof Kozlowski Signed-off-by: Dinh Nguyen --- arch/arm/boot/dts/socfpga.dtsi | 4 ++-- arch/arm/boot/dts/socfpga_arria10.dtsi | 4 ++-- arch/arm/boot/dts/socfpga_vt.dts | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 6eda6fdc101b..dcbd9ea9cf5e 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -905,7 +905,7 @@ reset-names = "timer"; }; - uart0: serial0@ffc02000 { + uart0: serial@ffc02000 { compatible = "snps,dw-apb-uart"; reg = <0xffc02000 0x1000>; interrupts = <0 162 4>; @@ -918,7 +918,7 @@ resets = <&rst UART0_RESET>; }; - uart1: serial1@ffc03000 { + uart1: serial@ffc03000 { compatible = "snps,dw-apb-uart"; reg = <0xffc03000 0x1000>; interrupts = <0 163 4>; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 3b2a2c9c6547..72c55e5187ca 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -845,7 +845,7 @@ reset-names = "timer"; }; - uart0: serial0@ffc02000 { + uart0: serial@ffc02000 { compatible = "snps,dw-apb-uart"; reg = <0xffc02000 0x100>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; @@ -856,7 +856,7 @@ status = "disabled"; }; - uart1: serial1@ffc02100 { + uart1: serial@ffc02100 { compatible = "snps,dw-apb-uart"; reg = <0xffc02100 0x100>; interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 3d0d806888b7..845ab2cc5ce6 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -57,11 +57,11 @@ clock-frequency = <7000000>; }; - serial0@ffc02000 { + serial@ffc02000 { clock-frequency = <7372800>; }; - serial1@ffc03000 { + serial@ffc03000 { clock-frequency = <7372800>; }; -- cgit From 21ab7031cbff8c6b6f608234e18ffe0473e98f9d Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 23 Jan 2023 12:12:38 -0600 Subject: arm64: dts: add pinctrl-single property for Stratix10/Agilex The Stratix10/Agilex has a pin control IP that can make use of the pinctrl-single driver. Add the pinctrl-single dts property for the Stratix10/Agilex platforms. Signed-off-by: Dinh Nguyen --- v2: no changes --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 15 +++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 55c5e1fdddc7..b488e8d185f3 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -353,6 +353,22 @@ reset-names = "dma", "dma-ocp"; }; + pinctrl0: pinctrl@ffd13000 { + compatible = "pinctrl-single"; + reg = <0xffd13000 0xA0>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + }; + + pinctrl1: pinctrl@ffd13100 { + compatible = "pinctrl-single"; + reg = <0xffd13100 0x20>; + #pinctrl-cells = <1>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + }; + rst: rstmgr@ffd11000 { #reset-cells = <1>; compatible = "altr,stratix10-rst-mgr"; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 849b46dd8098..f22302a19796 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -357,6 +357,21 @@ clock-names = "apb_pclk"; }; + pinctrl0: pinctrl@ffd13000 { + compatible = "pinctrl-single"; + #pinctrl-cells = <1>; + reg = <0xffd13000 0xa0>; + pinctrl-single,register-width = <32>; + pinctrl-single,function-mask = <0x0000000f>; + }; + + pinctrl1: pinconf@ffd13100 { + compatible = "pinctrl-single"; + #pinctrl-cells = <1>; + reg = <0xffd13100 0x20>; + pinctrl-single,register-width = <32>; + }; + rst: rstmgr@ffd11000 { #reset-cells = <1>; compatible = "altr,stratix10-rst-mgr"; -- cgit From d17c1a3d6a091afdc3b65116faa98d3363082f6a Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Mon, 23 Jan 2023 13:08:23 -0600 Subject: arm64: dts: stratix10: add i2c pins for pinctrl Add the I2C pins definition to the Stratix10 devkit. This allows for the I2C driver to use pinctrl on the pins to allow for GPIO recovery. Signed-off-by: Dinh Nguyen --- v2: remove underscores in node names --- .../boot/dts/altera/socfpga_stratix10_socdk.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 17752ca743e5..38ae674f2f02 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -65,6 +65,22 @@ }; }; +&pinctrl0 { + i2c1_pmx_func: i2c1-pmx-func { + pinctrl-single,pins = < + 0x78 0x4 /* I2C1_SDA (IO6-B) PIN30SEL) */ + 0x7c 0x4 /* I2C1_SCL (IO7-B) PIN31SEL */ + >; + }; + + i2c1_pmx_func_gpio: i2c1-pmx-func-gpio { + pinctrl-single,pins = < + 0x78 0x8 /* I2C1_SDA (IO6-B) PIN30SEL) */ + 0x7c 0x8 /* I2C1_SCL (IO7-B) PIN31SEL */ + >; + }; +}; + &gpio1 { status = "okay"; }; @@ -131,6 +147,13 @@ i2c-sda-falling-time-ns = <890>; /* hcnt */ i2c-sdl-falling-time-ns = <890>; /* lcnt */ + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&i2c1_pmx_func>; + pinctrl-1 = <&i2c1_pmx_func_gpio>; + + scl-gpios = <&portb 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&portb 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + adc@14 { compatible = "lltc,ltc2497"; reg = <0x14>; -- cgit From 2f8ba037c45925b372194df4bc27fca85fbeeffb Mon Sep 17 00:00:00 2001 From: Dinh Nguyen Date: Wed, 25 Jan 2023 14:07:00 -0600 Subject: arm64: dts: socfpga: change address-cells to support 64-bit addressing Update the address-cells and size-cells to 2 in order to support 64-bit addressing. Signed-off-by: Dinh Nguyen --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 5 ++--- arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index b488e8d185f3..41c9eb51d0ee 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -134,9 +134,8 @@ ranges = <0 0 0 0xffffffff>; base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; - + #address-cells = <0x2>; + #size-cells = <0x2>; compatible = "fpga-region"; fpga-mgr = <&fpga_mgr>; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index f22302a19796..f9674cc46764 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -139,8 +139,8 @@ ranges = <0 0 0 0xffffffff>; base_fpga_region { - #address-cells = <0x1>; - #size-cells = <0x1>; + #address-cells = <0x2>; + #size-cells = <0x2>; compatible = "fpga-region"; fpga-mgr = <&fpga_mgr>; }; -- cgit