From eed1d9b6e36b06faa53c6dc74134ec21b1336d94 Mon Sep 17 00:00:00 2001 From: Bhupesh Sharma Date: Wed, 19 May 2021 20:06:50 +0530 Subject: arm64: dts: qcom: sdm845: Use RPMH_CE_CLK macro directly In commit 3e482859f1ef ("dts: qcom: sdm845: Add dt entries to support crypto engine."), we decided to use the value indicated by constant RPMH_CE_CLK rather than using it directly. Now that the same RPMH clock value might be used for other SoCs (in addition to sdm845), let's use the constant RPMH_CE_CLK to make sure that this dtsi is compatible with the other qcom ones. Signed-off-by: Bhupesh Sharma Reviewed-by: Thara Gopinath Link: https://lore.kernel.org/r/20210519143700.27392-8-bhupesh.sharma@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 6d7172e6f4c3..425f169b5d1e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2311,7 +2311,7 @@ compatible = "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>; interrupts = ; - clocks = <&rpmhcc 15>; + clocks = <&rpmhcc RPMH_CE_CLK>; clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; @@ -2327,7 +2327,7 @@ reg = <0 0x01dfa000 0 0x6000>; clocks = <&gcc GCC_CE1_AHB_CLK>, <&gcc GCC_CE1_AHB_CLK>, - <&rpmhcc 15>; + <&rpmhcc RPMH_CE_CLK>; clock-names = "iface", "bus", "core"; dmas = <&cryptobam 6>, <&cryptobam 7>; dma-names = "rx", "tx"; -- cgit From 2c2f64ae36d97c1ec756ed781640f7951f7bac42 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sat, 11 Sep 2021 14:01:01 +0200 Subject: arm64: dts: qcom: msm8998: Provide missing "xo" and "sleep_clk" to GCC In a future patch the GCC driver will stop requesting this xo clock by its global "xo" name, in favour of having an explicit phandle here in the DT. Aside from that this clock in addition to the mandatory "sleep_clk" were never passed despite being required by the relevant dt-bindings. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210911120101.248476-1-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 34039b5c8017..d284ffe9bd71 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -117,7 +117,7 @@ clock-output-names = "xo_board"; }; - sleep_clk { + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32764>; @@ -855,6 +855,9 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0x00100000 0xb0000>; + + clock-names = "xo", "sleep_clk"; + clocks = <&xo>, <&sleep_clk>; }; rpm_msg_ram: memory@778000 { -- cgit From 3f917b7893f1367771736d1e40e224a6b5bda562 Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Mon, 13 Sep 2021 16:28:55 +0530 Subject: arm64: dts: qcom: sc7280-idp: Add vcc-supply for qfprom Add vcc-supply for the IDP boards that was missed when the qfprom device tree properties were added for the sc7280 SoC. Fixes: c1b2189a19cf ("arm64: dts: qcom: sc7280: Add qfprom node") Reported-by: satya priya Signed-off-by: Rajendra Nayak Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631530735-19811-1-git-send-email-rnayak@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 371a2a9dcf7a..99f9ee5d13f5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -207,6 +207,10 @@ }; }; +&qfprom { + vcc-supply = <&vreg_l1c_1p8>; +}; + &qupv3_id_0 { status = "okay"; }; -- cgit From 36c6581214c41c0311c2cc510c3e894dbd9c555d Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Mon, 9 Aug 2021 15:16:02 -0400 Subject: arm64: dts: qcom: sdm845: Add support for LMh node Add LMh nodes for CPU cluster0 and CPU cluster1. Also add interrupt support in cpufreq node to capture the LMh interrupt and let the scheduler know of the max frequency throttling. Reviewed-by: Bjorn Andersson Signed-off-by: Thara Gopinath Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210809191605.3742979-5-thara.gopinath@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 425f169b5d1e..5a1a81e15ca6 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -3641,6 +3641,30 @@ }; }; + lmh_cluster1: lmh@17d70800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d70800 0 0x400>; + interrupts = ; + cpus = <&CPU4>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + lmh_cluster0: lmh@17d78800 { + compatible = "qcom,sdm845-lmh"; + reg = <0 0x17d78800 0 0x400>; + interrupts = ; + cpus = <&CPU0>; + qcom,lmh-temp-arm-millicelsius = <65000>; + qcom,lmh-temp-low-millicelsius = <94500>; + qcom,lmh-temp-high-millicelsius = <95000>; + interrupt-controller; + #interrupt-cells = <1>; + }; + sound: sound { }; @@ -4912,6 +4936,8 @@ reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; reg-names = "freq-domain0", "freq-domain1"; + interrupts-extended = <&lmh_cluster0 0>, <&lmh_cluster1 0>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; -- cgit From 52e3b2ca6f9dcc13f57cbbc9ddda49503b376244 Mon Sep 17 00:00:00 2001 From: Thara Gopinath Date: Mon, 9 Aug 2021 15:16:03 -0400 Subject: arm64: dts: qcom: sdm845: Remove cpufreq cooling devices for CPU thermal zones Now that Limits h/w is enabled to monitor thermal events around cpus and throttle the cpu frequencies, remove cpufreq cooling device for the CPU thermal zones which does software throttling of cpu frequencies. Reviewed-by: Bjorn Andersson Signed-off-by: Thara Gopinath Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210809191605.3742979-6-thara.gopinath@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 136 ----------------------------------- 1 file changed, 136 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 5a1a81e15ca6..d18f7b419d2e 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -4995,23 +4995,6 @@ type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu0_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu0_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu1-thermal { @@ -5039,23 +5022,6 @@ type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu1_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu1_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu2-thermal { @@ -5083,23 +5049,6 @@ type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu2_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu2_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu3-thermal { @@ -5127,23 +5076,6 @@ type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu3_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu3_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu4-thermal { @@ -5171,23 +5103,6 @@ type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu4_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu4_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu5-thermal { @@ -5215,23 +5130,6 @@ type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu5_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu5_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu6-thermal { @@ -5259,23 +5157,6 @@ type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu6_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu6_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; cpu7-thermal { @@ -5303,23 +5184,6 @@ type = "critical"; }; }; - - cooling-maps { - map0 { - trip = <&cpu7_alert0>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu7_alert1>; - cooling-device = <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; }; aoss0-thermal { -- cgit From c075a2e39d2f0823c3670745e820aec0dd8dd0a7 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Sep 2021 20:31:19 +0200 Subject: arm64: dts: qcom: msm8998: Configure the MultiMedia Clock Controller (MMCC) The MSM8998 MMCC is supported and has a driver: configure it as a preparation for a later enablement of multimedia nodes (mdp, venus and others). Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210901183123.1087392-1-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index d284ffe9bd71..0d8c4437246b 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -2333,6 +2334,36 @@ #size-cells = <0>; }; + mmcc: clock-controller@c8c0000 { + compatible = "qcom,mmcc-msm8998"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + reg = <0xc8c0000 0x40000>; + status = "disabled"; + + clock-names = "xo", + "gpll0", + "dsi0dsi", + "dsi0byte", + "dsi1dsi", + "dsi1byte", + "hdmipll", + "dplink", + "dpvco", + "core_bi_pll_test_se"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, + <&gcc GCC_MMSS_GPLL0_CLK>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + }; + remoteproc_adsp: remoteproc@17300000 { compatible = "qcom,msm8998-adsp-pas"; reg = <0x17300000 0x4040>; -- cgit From 05ce21b54423e551b259298bd6e8c0f23530b5da Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Sep 2021 20:31:20 +0200 Subject: arm64: dts: qcom: msm8998: Configure the multimedia subsystem iommu In preparation for enabling various components of the multimedia subsystem, write configuration for its related IOMMU. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210901183123.1087392-2-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 37 +++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 0d8c4437246b..1412b1ea506d 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2364,6 +2364,43 @@ <0>; }; + mmss_smmu: iommu@cd00000 { + compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; + reg = <0x0cd00000 0x40000>; + #iommu-cells = <1>; + + clocks = <&mmcc MNOC_AHB_CLK>, + <&mmcc BIMC_SMMU_AHB_CLK>, + <&rpmcc RPM_SMD_MMAXI_CLK>, + <&mmcc BIMC_SMMU_AXI_CLK>; + clock-names = "iface-mm", "iface-smmu", + "bus-mm", "bus-smmu"; + status = "disabled"; + + #global-interrupts = <0>; + interrupts = + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + remoteproc_adsp: remoteproc@17300000 { compatible = "qcom,msm8998-adsp-pas"; reg = <0x17300000 0x4040>; -- cgit From 3f1dcaff642e75c1d2ad03f783fa8a3b1f56dd50 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Sep 2021 20:31:21 +0200 Subject: arm64: dts: qcom: msm8998: Fix CPU/L2 idle state latency and residency The entry/exit latency and minimum residency in state for the idle states of MSM8998 were ..bad: first of all, for all of them the timings were written for CPU sleep but the min-residency-us param was miscalculated (supposedly, while porting this from downstream); Then, the power collapse states are setting PC on both the CPU cluster *and* the L2 cache, which have different timings: in the specific case of L2 the times are higher so these ones should be taken into account instead of the CPU ones. This parameter misconfiguration was not giving particular issues because on MSM8998 there was no CPU scaling at all, so cluster/L2 power collapse was rarely (if ever) hit. When CPU scaling is enabled, though, the wrong timings will produce SoC unstability shown to the user as random, apparently error-less, sudden reboots and/or lockups. This set of parameters are stabilizing the SoC when CPU scaling is ON and when power collapse is frequently hit. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210901183123.1087392-3-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 1412b1ea506d..6f6893a8250e 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -309,38 +309,42 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { compatible = "arm,idle-state"; idle-state-name = "little-retention"; + /* CPU Retention (C2D), L2 Active */ arm,psci-suspend-param = <0x00000002>; entry-latency-us = <81>; exit-latency-us = <86>; - min-residency-us = <200>; + min-residency-us = <504>; }; LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "little-power-collapse"; + /* CPU + L2 Power Collapse (C3, D4) */ arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <273>; - exit-latency-us = <612>; - min-residency-us = <1000>; + entry-latency-us = <814>; + exit-latency-us = <4562>; + min-residency-us = <9183>; local-timer-stop; }; BIG_CPU_SLEEP_0: cpu-sleep-1-0 { compatible = "arm,idle-state"; idle-state-name = "big-retention"; + /* CPU Retention (C2D), L2 Active */ arm,psci-suspend-param = <0x00000002>; entry-latency-us = <79>; exit-latency-us = <82>; - min-residency-us = <200>; + min-residency-us = <1302>; }; BIG_CPU_SLEEP_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "big-power-collapse"; + /* CPU + L2 Power Collapse (C3, D4) */ arm,psci-suspend-param = <0x40000003>; - entry-latency-us = <336>; - exit-latency-us = <525>; - min-residency-us = <1000>; + entry-latency-us = <724>; + exit-latency-us = <2027>; + min-residency-us = <9419>; local-timer-stop; }; }; -- cgit From 94117eb172281aa57a10292b49d50c1d901f5d0c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Sep 2021 20:31:22 +0200 Subject: arm64: dts: qcom: msm8998: Move qfprom iospace to calibrated values The QFPROM iospace was (erroneously, I believe) set to the uncalibrated fuse start address, but every driver only needs - and will always only need - only calibrated values. Move the iospace forward to the calibrated values start to avoid offsetting every fuse definition. Obviously, the only defined fuse (qusb2_hstx_trim) was also fixed to remove the offset, in order to comply with this change. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210901183123.1087392-4-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 6f6893a8250e..0fafd9e0691b 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -870,14 +870,14 @@ reg = <0x00778000 0x7000>; }; - qfprom: qfprom@780000 { + qfprom: qfprom@784000 { compatible = "qcom,qfprom"; - reg = <0x00780000 0x621c>; + reg = <0x00784000 0x621c>; #address-cells = <1>; #size-cells = <1>; - qusb2_hstx_trim: hstx-trim@423a { - reg = <0x423a 0x1>; + qusb2_hstx_trim: hstx-trim@23a { + reg = <0x23a 0x1>; bits = <0 4>; }; }; -- cgit From 87cd46d68aeac88203b8aa205d0ac821f7b067c1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 1 Sep 2021 20:31:23 +0200 Subject: arm64: dts: qcom: msm8998: Configure Adreno GPU and related IOMMU The MSM8998 SoC includes an Adreno 540.1 GPU, with a maximum frequency of 710MHz. This GPU may or may not accept a ZAP shader, depending on platform configuration, so adding a zap-shader node is left to the board DT. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210901183123.1087392-5-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 97 +++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 0fafd9e0691b..460e6b37d82a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1424,6 +1424,103 @@ }; }; + adreno_gpu: gpu@5000000 { + compatible = "qcom,adreno-540.1", "qcom,adreno"; + reg = <0x05000000 0x40000>; + reg-names = "kgsl_3d0_reg_memory"; + + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gpucc RBBMTIMER_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_GPU_BIMC_GFX_CLK>, + <&gpucc RBCPR_CLK>, + <&gpucc GFX3D_CLK>; + clock-names = "iface", + "rbbmtimer", + "mem", + "mem_iface", + "rbcpr", + "core"; + + interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&adreno_smmu 0>; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&rpmpd MSM8998_VDDMX>; + #stream-id-cells = <16>; + status = "disabled"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-710000097 { + opp-hz = /bits/ 64 <710000097>; + opp-level = ; + opp-supported-hw = <0xFF>; + }; + + opp-670000048 { + opp-hz = /bits/ 64 <670000048>; + opp-level = ; + opp-supported-hw = <0xFF>; + }; + + opp-596000097 { + opp-hz = /bits/ 64 <596000097>; + opp-level = ; + opp-supported-hw = <0xFF>; + }; + + opp-515000097 { + opp-hz = /bits/ 64 <515000097>; + opp-level = ; + opp-supported-hw = <0xFF>; + }; + + opp-414000000 { + opp-hz = /bits/ 64 <414000000>; + opp-level = ; + opp-supported-hw = <0xFF>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + opp-level = ; + opp-supported-hw = <0xFF>; + }; + + opp-257000000 { + opp-hz = /bits/ 64 <257000000>; + opp-level = ; + opp-supported-hw = <0xFF>; + }; + }; + }; + + adreno_smmu: iommu@5040000 { + compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; + reg = <0x05040000 0x10000>; + clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, + <&gcc GCC_BIMC_GFX_CLK>, + <&gcc GCC_GPU_BIMC_GFX_CLK>; + clock-names = "iface", "mem", "mem_iface"; + + #global-interrupts = <0>; + #iommu-cells = <1>; + interrupts = + , + , + ; + /* + * GPU-GX GDSC's parent is GPU-CX. We need to bring up the + * GPU-CX for SMMU but we need both of them up for Adreno. + * Contemporarily, we also need to manage the VDDMX rpmpd + * domain in the Adreno driver. + * Enable GPU CX/GX GDSCs here so that we can manage the + * SoC VDDMX RPM Power Domain in the Adreno driver. + */ + power-domains = <&gpucc GPU_GX_GDSC>; + status = "disabled"; + }; + gpucc: clock-controller@5065000 { compatible = "qcom,msm8998-gpucc"; #clock-cells = <1>; -- cgit From c57b4247faaf6d17a319c91d5eb736c3bc65aca2 Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Wed, 1 Sep 2021 19:33:24 +0000 Subject: arm64: dts: qcom: db820c: Move blsp1_uart2 pin states to msm8996.dtsi Move blsp1_uart2_default and blsp1_uart2_sleep to the SoC device tree to avoid duplicating them in other device trees. Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210901193214.250375-2-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi | 29 ---------------------------- arch/arm64/boot/dts/qcom/msm8996.dtsi | 17 ++++++++++++++++ 2 files changed, 17 insertions(+), 29 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi index 51e17094d7b1..eca428ab2517 100644 --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dtsi @@ -148,9 +148,6 @@ &blsp1_uart2 { label = "BT-UART"; status = "okay"; - pinctrl-names = "default", "sleep"; - pinctrl-0 = <&blsp1_uart2_default>; - pinctrl-1 = <&blsp1_uart2_sleep>; bluetooth { compatible = "qcom,qca6174-bt"; @@ -437,32 +434,6 @@ }; }; - blsp1_uart2_default: blsp1_uart2_default { - mux { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "blsp_uart2"; - }; - - config { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - drive-strength = <16>; - bias-disable; - }; - }; - - blsp1_uart2_sleep: blsp1_uart2_sleep { - mux { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - function = "gpio"; - }; - - config { - pins = "gpio41", "gpio42", "gpio43", "gpio44"; - drive-strength = <2>; - bias-disable; - }; - }; - hdmi_hpd_active: hdmi_hpd_active { mux { pins = "gpio34"; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 52df22ab3f6a..23c3435ab888 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1211,6 +1211,20 @@ }; }; + blsp1_uart2_default: blsp1-uart2-default { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "blsp_uart2"; + drive-strength = <16>; + bias-disable; + }; + + blsp1_uart2_sleep: blsp1-uart2-sleep { + pins = "gpio41", "gpio42", "gpio43", "gpio44"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + blsp1_i2c3_default: blsp1-i2c2-default { pins = "gpio47", "gpio48"; function = "blsp_i2c3"; @@ -2704,6 +2718,9 @@ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp1_uart2_default>; + pinctrl-1 = <&blsp1_uart2_sleep>; dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; dma-names = "tx", "rx"; status = "disabled"; -- cgit From 214faf07e3914e97fd71a166a6c677ba13780a0c Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Wed, 1 Sep 2021 19:33:32 +0000 Subject: arm64: dts: qcom: msm8996: Add blsp2_i2c3 Add a node for blsp2_i2c3 which is used for type-C port control chips and speaker codecs on some devices. Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210901193214.250375-3-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 23c3435ab888..1f4eca018183 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -1253,6 +1253,20 @@ bias-disable; }; + blsp2_i2c3_default: blsp2-i2c3 { + pins = "gpio51", "gpio52"; + function = "blsp_i2c9"; + drive-strength = <16>; + bias-disable; + }; + + blsp2_i2c3_sleep: blsp2-i2c3-sleep { + pins = "gpio51", "gpio52"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + wcd_intr_default: wcd-intr-default{ pins = "gpio54"; function = "gpio"; @@ -2825,6 +2839,24 @@ status = "disabled"; }; + blsp2_i2c3: i2c@75b7000 { + compatible = "qcom,i2c-qup-v2.2.1"; + reg = <0x075b7000 0x1000>; + interrupts = ; + clocks = <&gcc GCC_BLSP2_AHB_CLK>, + <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>; + clock-names = "iface", "core"; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&blsp2_i2c3_default>; + pinctrl-1 = <&blsp2_i2c3_sleep>; + dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + blsp2_i2c5: i2c@75b9000 { compatible = "qcom,i2c-qup-v2.2.1"; reg = <0x75b9000 0x1000>; -- cgit From 46680fe9ba615223f33b7fc1f1d6262db625be9f Mon Sep 17 00:00:00 2001 From: Yassine Oudjana Date: Wed, 1 Sep 2021 19:33:42 +0000 Subject: arm64: dts: qcom: msm8996: Add support for the Xiaomi MSM8996 platform There are 5 Xiaomi devices with the MSM8996 SoC: - Mi 5 (gemini): MSM8996 + PMI8994 - Mi Note 2 (scorpio): MSM8996 Pro + PMI8996 - Mi 5s (capricorn): MSM8996 Pro + PMI8996 - Mi Mix (lithium): MSM8996 Pro + PMI8996 - Mi 5s Plus (natrium): MSM8996 Pro + PMI8996 These devices share a common board design with only a few differences. Add support for the common board, as well as support for the Mi Note 2. Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210901193214.250375-4-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi | 673 +++++++++++++++++++++ .../arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts | 431 +++++++++++++ 3 files changed, 1105 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi create mode 100644 arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 70516508be56..7e33d492bf26 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi new file mode 100644 index 000000000000..d239b01b8505 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-common.dtsi @@ -0,0 +1,673 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Yassine Oudjana + */ + +/dts-v1/; + +#include "msm8996.dtsi" +#include "pm8994.dtsi" +#include "pmi8994.dtsi" +#include +#include +#include +#include + +/ { + clocks { + compatible = "simple-bus"; + + divclk1_cdc: divclk1 { + compatible = "gpio-gate-clock"; + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; + #clock-cells = <0>; + enable-gpios = <&pm8994_gpios 15 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&divclk1_default>; + }; + + divclk4: divclk4 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "divclk4"; + + pinctrl-names = "default"; + pinctrl-0 = <&divclk4_pin_a>; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + + vol_up { + label = "Volume Up"; + gpios = <&pm8994_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + dome { + label = "Home"; + gpios = <&tlmm 34 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + reserved-memory { + memory@88800000 { + reg = <0x0 0x88800000 0x0 0x1400000>; + no-map; + }; + + /* This platform has all PIL regions offset by 0x1400000 */ + /delete-node/ mpss@88800000; + mpss_region: mpss@89c00000 { + reg = <0x0 0x89c00000 0x0 0x6200000>; + no-map; + }; + + /delete-node/ adsp@8ea00000; + adsp_region: adsp@8ea00000 { + reg = <0x0 0x8fe00000 0x0 0x1b00000>; + no-map; + }; + + /delete-node/ slpi@90b00000; + slpi_region: slpi@91900000 { + reg = <0x0 0x91900000 0x0 0xa00000>; + no-map; + }; + + /delete-node/ gpu@8f200000; + zap_shader_region: gpu@92300000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x92300000 0x0 0x2000>; + no-map; + }; + + /delete-node/ venus@91000000; + venus_region: venus@90400000 { + reg = <0x0 0x92400000 0x0 0x500000>; + no-map; + }; + + ramoops@92900000 { + compatible = "ramoops"; + reg = <0x0 0x92900000 0x0 0x100000>; + no-map; + + record-size = <0x8000>; + console-size = <0x80000>; + ftrace-size = <0x20000>; + pmsg-size = <0x40000>; + }; + + /delete-node/ rmtfs@86700000; + rmtfs@f6c00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xf6c00000 0 0x200000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; + + /delete-node/ mba@91500000; + mba_region: mba@f6f00000 { + reg = <0x0 0xf6f00000 0x0 0x100000>; + no-map; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3800000>; + regulator-max-microvolt = <3800000>; + regulator-always-on; + regulator-boot-on; + }; + + vdd_3v2_tp: vdd-3v2-tp { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v2_tp"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + startup-delay-us = <4000>; + vin-supply = <&vph_pwr>; + + gpio = <&tlmm 73 0>; + enable-active-high; + }; + + vdd_3v3: rome-vreg { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <4000>; + vin-supply = <&vph_pwr_bbyp>; + + gpio = <&pm8994_gpios 9 0>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&rome_enable_default>; + + /* Required by QCA6174a - vddpe-3v3 */ + regulator-always-on; + }; + + /* WL_EN pin defined as a fixed regulator */ + wlan_en: wlan-en-1-8v { + compatible = "regulator-fixed"; + regulator-name = "wlan-en-regulator"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&pm8994_gpios 8 0>; + /* WLAN card specific delay */ + startup-delay-us = <70000>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&wlan_en_default>; + }; +}; + +&adsp_pil { + status = "okay"; +}; + +&blsp2_i2c2 { + status = "okay"; + label = "NFC_I2C"; + + nfc: pn548@28 { + compatible = "nxp,nxp-nci-i2c"; + + reg = <0x28>; + clock-frequency = <400000>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH>; + + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + firmware-gpios = <&tlmm 21 GPIO_ACTIVE_HIGH>; + + pinctrl-names = "default"; + pinctrl-0 = <&nfc_default>; + }; +}; + +&blsp2_i2c3 { + status = "okay"; + label = "TYPEC_I2C"; + + typec: tusb320@47 { + compatible = "ti,tusb320"; + reg = <0x47>; + interrupt-parent = <&tlmm>; + interrupts = <63 IRQ_TYPE_EDGE_RISING>; + }; +}; + +&blsp2_i2c6 { + status = "okay"; + label = "MSM_TS_I2C"; +}; + +&blsp1_uart2 { + status = "okay"; + label = "QCA_UART"; + + bluetooth: qca6174a { + compatible = "qcom,qca6174-bt"; + + enable-gpios = <&pm8994_gpios 19 GPIO_ACTIVE_HIGH>; + clocks = <&divclk4>; + }; +}; + +&dsi0 { + status = "okay"; + + vdd-supply = <&vreg_l2a_1p25>; + vddio-supply = <&vreg_l14a_1p8>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mdss_dsi_default &mdss_te_default>; + pinctrl-1 = <&mdss_dsi_sleep &mdss_te_sleep>; +}; + +&dsi0_out { + status = "okay"; + + data-lanes = <0 1 2 3>; +}; + +&dsi0_phy { + status = "okay"; + + vcca-supply = <&vreg_l28a_0p925>; +}; + +&gpu { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mmcc { + vdd-gfx-supply = <&vdd_gfx>; +}; + +&pcie0 { + status = "okay"; + + /* Supplied by vdd_3v3, but choose wlan_en to drive enable pin high */ + vddpe-3v3-supply = <&wlan_en>; + vdda-supply = <&vreg_l28a_0p925>; + + perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; +}; + +&pcie_phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; +}; + +&pm8994_resin { + status = "okay"; + + linux,code = ; +}; + +&usb3 { + status = "okay"; + extcon = <&typec>; + + qcom,select-utmi-as-pipe-clk; + + dwc3@6a00000 { + extcon = <&typec>; + + /* usb3-phy is not used on this device */ + phys = <&hsusb_phy1>; + phy-names = "usb2-phy"; + + maximum-speed = "high-speed"; + snps,is-utmi-l1-suspend; + snps,usb2-gadget-lpm-disable; + snps,hird-threshold = /bits/ 8 <0>; + }; +}; + +&hsusb_phy1 { + status = "okay"; + extcon = <&typec>; + + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + +&ufshc { + status = "okay"; + + vcc-supply = <&vreg_l20a_2p95>; + vccq-supply = <&vreg_l25a_1p2>; + vccq2-supply = <&vreg_s4a_1p8>; + + vcc-max-microamp = <600000>; + vccq-max-microamp = <450000>; + vccq2-max-microamp = <450000>; +}; + +&ufsphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l28a_0p925>; + vdda-pll-supply = <&vreg_l12a_1p8>; + + vdda-phy-max-microamp = <18380>; + vdda-pll-max-microamp = <9440>; + + vddp-ref-clk-supply = <&vreg_l25a_1p2>; + vddp-ref-clk-max-microamp = <100>; + vddp-ref-clk-always-on; +}; + +&venus { + status = "okay"; +}; + +&wcd9335 { + clock-names = "mclk", "slimbus"; + clocks = <&divclk1_cdc>, + <&rpmcc RPM_SMD_BB_CLK1>; + + vdd-buck-supply = <&vreg_s4a_1p8>; + vdd-buck-sido-supply = <&vreg_s4a_1p8>; + vdd-rx-supply = <&vreg_s4a_1p8>; + vdd-tx-supply = <&vreg_s4a_1p8>; + vdd-vbat-supply = <&vph_pwr>; + vdd-micbias-supply = <&vph_pwr_bbyp>; + vdd-io-supply = <&vreg_s4a_1p8>; +}; + +&rpm_requests { + pm8994-regulators { + compatible = "qcom,rpm-pm8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_l1-supply = <&vreg_s1b_1p025>; + vdd_l2_l26_l28-supply = <&vreg_s3a_1p3>; + vdd_l3_l11-supply = <&vreg_s3a_1p3>; + vdd_l4_l27_l31-supply = <&vreg_s3a_1p3>; + vdd_l5_l7-supply = <&vreg_s5a_2p15>; + vdd_l6_l12_l32-supply = <&vreg_s5a_2p15>; + vdd_l8_l16_l30-supply = <&vph_pwr>; + vdd_l9_l10_l18_l22-supply = <&vph_pwr_bbyp>; + vdd_l13_l19_l23_l24-supply = <&vph_pwr_bbyp>; + vdd_l14_l15-supply = <&vreg_s5a_2p15>; + vdd_l17_l29-supply = <&vph_pwr_bbyp>; + vdd_l20_l21-supply = <&vph_pwr_bbyp>; + vdd_l25-supply = <&vreg_s3a_1p3>; + vdd_lvs1_2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p3: s3 { + regulator-name = "vreg_s3a_1p3"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + + /* Required by QCA6174a - vdd-core */ + regulator-always-on; + }; + vreg_s4a_1p8: s4 { + regulator-name = "vreg_s4a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + + /* Required by QCA6174a - vddio */ + regulator-always-on; + }; + vreg_s5a_2p15: s5 { + regulator-name = "vreg_s5a_2p15"; + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + vreg_s7a_0p8: s7 { + regulator-name = "vreg_s7a_0p8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + vreg_l1a_1p0: l1 { + regulator-name = "vreg_l1a_1p0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + vreg_l2a_1p25: l2 { + regulator-name = "vreg_l2a_1p25"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + }; + vreg_l4a_1p225: l4 { + regulator-name = "vreg_l4a_1p225"; + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + vreg_l6a_1p8: l6 { + regulator-name = "vreg_l6a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l8a_1p8: l8 { + regulator-name = "vreg_l8a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l9a_1p8: l9 { + regulator-name = "vreg_l9a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l10a_1p8: l10 { + regulator-name = "vreg_l10a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l12a_1p8: l12 { + regulator-name = "vreg_l12a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + }; + vreg_l13a_2p95: l13 { + regulator-name = "vreg_l13a_2p95"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + vreg_l14a_1p8: l14 { + regulator-name = "vreg_l14a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l15a_1p8: l15 { + regulator-name = "vreg_l15a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l16a_2p7: l16 { + regulator-name = "vreg_l16a_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + vreg_l19a_3p3: l19 { + regulator-name = "vreg_l19a_3p3"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + vreg_l20a_2p95: l20 { + regulator-name = "vreg_l20a_2p95"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + vreg_l21a_2p95: l21 { + regulator-name = "vreg_l21a_2p95"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + vreg_l23a_2p8: l23 { + regulator-name = "vreg_l23a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l24a_3p075: l24 { + regulator-name = "vreg_l24a_3p075"; + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + vreg_l25a_1p2: l25 { + regulator-name = "vreg_l25a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + vreg_l27a_1p2: l27 { + regulator-name = "vreg_l27a_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + vreg_l28a_0p925: l28 { + regulator-name = "vreg_l28a_0p925"; + regulator-min-microvolt = <925000>; + regulator-max-microvolt = <925000>; + regulator-allow-set-load; + }; + vreg_l30a_1p8: l30 { + regulator-name = "vreg_l30a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + /* Required by QCA6174a - vddio-xtal */ + regulator-always-on; + }; + vreg_l32a_1p8: l32 { + regulator-name = "vreg_l32a_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_lvs1a_1p8: lvs1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_lvs2a_1p8: lvs2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + + pmi8994-regulators { + compatible = "qcom,rpm-pmi8994-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_bst_byp-supply = <&vph_pwr>; + + vreg_s1b_1p025: s1 { + regulator-name = "vreg_s1b_1p025"; + regulator-min-microvolt = <1025000>; + regulator-max-microvolt = <1025000>; + }; + + vph_pwr_bbyp: boost-bypass { + regulator-name = "vph_pwr_bbyp"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3600000>; + }; + }; +}; + +&pm8994_spmi_regulators { + qcom,saw-reg = <&saw3>; + s8 { + qcom,saw-slave; + }; + s9 { + qcom,saw-slave; + }; + s10 { + qcom,saw-slave; + }; + vreg_apc_0p8: s11 { + qcom,saw-leader; + regulator-name = "vreg_apc_0p8"; + regulator-min-microvolt = <470000>; + regulator-max-microvolt = <1140000>; + regulator-max-step-microvolt = <150000>; + regulator-always-on; + }; +}; + +&pmi8994_spmi_regulators { + vdd_gfx: s2 { + regulator-name = "vdd_gfx"; + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1015000>; + regulator-enable-ramp-delay = <500>; + }; +}; + +&pm8994_gpios { + wlan_en_default: wlan-en-default { + pins = "gpio8"; + function = PMIC_GPIO_FUNC_NORMAL; + output-low; + qcom,drive-strength = ; + power-source = ; + bias-disable; + }; + + rome_enable_default: rome-enable-default { + pins = "gpio9"; + function = PMIC_GPIO_FUNC_NORMAL; + output-high; + qcom,drive-strength = ; + power-source = ; + }; + + divclk1_default: divclk1_default { + pins = "gpio15"; + function = PMIC_GPIO_FUNC_FUNC1; + bias-disable; + power-source = ; + qcom,drive-strength = ; + }; + + divclk4_pin_a: divclk4 { + pins = "gpio18"; + function = PMIC_GPIO_FUNC_FUNC2; + bias-disable; + power-source = ; + }; +}; + +&tlmm { + mdss_dsi_default: mdss_dsi_default { + pins = "gpio8"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + mdss_dsi_sleep: mdss_dsi_sleep { + pins = "gpio8"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + mdss_te_default: mdss_te_default { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + mdss_te_sleep: mdss_te_sleep { + pins = "gpio10"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + nfc_default: nfc_default { + pins = "gpio12", "gpio21"; + function = "gpio"; + drive-strength = <16>; + bias-pull-up; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts new file mode 100644 index 000000000000..ea2ca271fe7d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-scorpio.dts @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2020, Yassine Oudjana + */ + +/dts-v1/; + +#include "msm8996-xiaomi-common.dtsi" +#include "pmi8996.dtsi" +#include +#include + +/ { + model = "Xiaomi Mi Note 2"; + compatible = "xiaomi,scorpio", "qcom,msm8996"; + qcom,msm-id = <305 0x10000>; + qcom,board-id = <34 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer0: framebuffer@83401000 { + compatible = "simple-framebuffer"; + reg = <0x00 0x83401000 0x00 (1080 * 1920 * 3)>; + width = <1080>; + height = <1920>; + stride = <(1080 * 3)>; + format = "r8g8b8"; + + /* DSI0 and MDP SMMU clocks */ + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MMSS_MMAGIC_AHB_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc SMMU_MDP_AHB_CLK>, + <&mmcc SMMU_MDP_AXI_CLK>; + + /* MDSS power domain */ + power-domains = <&mmcc MDSS_GDSC>; + }; + }; + + reserved-memory { + cont_splash_mem: memory@83401000 { + reg = <0x0 0x83401000 0x0 (1080 * 1920 * 3)>; + no-map; + }; + }; +}; + +&adsp_pil { + firmware-name = "qcom/msm8996/scorpio/adsp.mbn"; +}; + +&blsp2_i2c6 { + touchscreen: atmel-mxt-ts@4a { + compatible = "atmel,maxtouch"; + reg = <0x4a>; + interrupt-parent = <&tlmm>; + interrupts = <125 IRQ_TYPE_LEVEL_LOW>; + vdda-supply = <&vreg_l6a_1p8>; + vdd-supply = <&vdd_3v2_tp>; + reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touchscreen_default>; + pinctrl-1 = <&touchscreen_sleep>; + }; +}; + +&gpu { + zap-shader { + firmware-name = "qcom/msm8996/scorpio/a530_zap.mbn"; + }; +}; + +&mdp_smmu { + /* + * Probing this SMMU causes a crash due to writing to some secure + * registers. Disable it for now. + */ + status = "disabled"; +}; + +&mdss { + /* + * MDSS depends on the MDP SMMU, and probing it alters the bootloader + * configured framebuffer used by simplefb. Disable it for now. + */ + status = "disabled"; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + +&sound { + compatible = "qcom,apq8096-sndcard"; + model = "scorpio"; + audio-routing = "RX_BIAS", "MCLK"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_6_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 6>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 1>; + }; + }; +}; + +&venus { + firmware-name = "qcom/msm8996/scorpio/venus.mbn"; +}; + +&rpm_requests { + pm8994-regulators { + vreg_l3a_0p875: l3 { + regulator-name = "vreg_l3a_0p875"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + vreg_l11a_1p1: l11 { + regulator-name = "vreg_l11a_1p1"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + vreg_l17a_2p8: l17 { + regulator-name = "vreg_l17a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l18a_2p8: l18 { + regulator-name = "vreg_l18a_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + vreg_l22a_3p0: l22 { + regulator-name = "vreg_l22a_3p0"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3500000>; + }; + vreg_l29a_2p7: l29 { + regulator-name = "vreg_l29a_2p7"; + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + }; +}; + +&vdd_gfx { + regulator-max-microvolt = <1065000>; +}; + +&pm8994_gpios { + gpio-line-names = + "NC", /* GPIO_1 */ + "VOL_UP_N", /* GPIO_2 */ + "SPKR_ID", /* GPIO_3 */ + "PWM_HAPTICS", /* GPIO_4 */ + "INFARED_DRV", /* GPIO_5 */ + "NC", /* GPIO_6 */ + "KEYPAD_LED_EN_A", /* GPIO_7 */ + "WL_EN", /* GPIO_8 */ + "3P3_ENABLE", /* GPIO_9 */ + "KEYPAD_LED_EN_B", /* GPIO_10 */ + "FP_ID", /* GPIO_11 */ + "NC", /* GPIO_12 */ + "NC", /* GPIO_13 */ + "NC", /* GPIO_14 */ + "DIVCLK1_CDC", /* GPIO_15 */ + "DIVCLK2_HAPTICS", /* GPIO_16 */ + "NC", /* GPIO_17 */ + "32KHz_CLK_IN", /* GPIO_18 */ + "BT_EN", /* GPIO_19 */ + "PMIC_SLB", /* GPIO_20 */ + "UIM_BATT_ALARM", /* GPIO_21 */ + "NC"; /* GPIO_22 */ +}; + +&pm8994_mpps { + gpio-line-names = + "VREF_SDC_UIM_APC", /* MPP_1 */ + "NC", /* MPP_2 */ + "VREF_DACX", /* MPP_3 */ + "NC", /* MPP_4 */ + "NC", /* MPP_5 */ + "STAT_SMB1351", /* MPP_6 */ + "NC", /* MPP_7 */ + "NC"; /* MPP_8 */ +}; + +&pmi8994_gpios { + gpio-line-names = + "NC", /* GPIO_1 */ + "SPKR_PA_RST", /* GPIO_2 */ + "NC", /* GPIO_3 */ + "NC", /* GPIO_4 */ + "NC", /* GPIO_5 */ + "NC", /* GPIO_6 */ + "NC", /* GPIO_7 */ + "NC", /* GPIO_8 */ + "NC", /* GPIO_9 */ + "NC"; /* GPIO_10 */ +}; + +&tlmm { + gpio-line-names = + "ESE_SPI_MOSI", /* GPIO_0 */ + "ESE_SPI_MISO", /* GPIO_1 */ + "NC", /* GPIO_2 */ + "ESE_SPI_CLK", /* GPIO_3 */ + "MSM_UART_TX", /* GPIO_4 */ + "MSM_UART_RX", /* GPIO_5 */ + "NFC_I2C_SDA", /* GPIO_6 */ + "NFC_I2C_SCL", /* GPIO_7 */ + "OLED_RESET_N", /* GPIO_8 */ + "NFC_IRQ", /* GPIO_9 */ + "OLED_TE", /* GPIO_10 */ + "OLED_ID_DET1", /* GPIO_11 */ + "NFC_DISABLE", /* GPIO_12 */ + "CAM_MCLK0", /* GPIO_13 */ + "OLED_ID_DET2", /* GPIO_14 */ + "CAM_MCLK2", /* GPIO_15 */ + "ESE_PWR_REQ", /* GPIO_16 */ + "CCI_I2C_SDA0", /* GPIO_17 */ + "CCI_I2C_SCL0", /* GPIO_18 */ + "CCI_I2C_SDA1", /* GPIO_19 */ + "CCI_I2C_SCL1", /* GPIO_20 */ + "NFC_DWL_REQ", /* GPIO_21 */ + "CCI_TIMER1", /* GPIO_22 */ + "WEBCAM1_RESET_N", /* GPIO_23 */ + "ESE_IRQ", /* GPIO_24 */ + "NC", /* GPIO_25 */ + "WEBCAM1_STANDBY", /* GPIO_26 */ + "NC", /* GPIO_27 */ + "NC", /* GPIO_28 */ + "OLED_ERR_FG", /* GPIO_29 */ + "CAM1_RST_N", /* GPIO_30 */ + "HIFI_SW_MUTE", /* GPIO_31 */ + "NC", /* GPIO_32 */ + "NC", /* GPIO_33 */ + "FP_DOME_SW", /* GPIO_34 */ + "PCI_E0_RST_N", /* GPIO_35 */ + "PCI_E0_CLKREQ_N", /* GPIO_36 */ + "PCI_E0_WAKE", /* GPIO_37 */ + "OV_PWDN", /* GPIO_38 */ + "NC", /* GPIO_39 */ + "VDDR_1P6_EN", /* GPIO_40 */ + "QCA_UART_TXD", /* GPIO_41 */ + "QCA_UART_RXD", /* GPIO_42 */ + "QCA_UART_CTS", /* GPIO_43 */ + "QCA_UART_RTS", /* GPIO_44 */ + "MAWC_UART_TX", /* GPIO_45 */ + "MAWC_UART_RX", /* GPIO_46 */ + "NC", /* GPIO_47 */ + "NC", /* GPIO_48 */ + "AUDIO_SWITCH_EN", /* GPIO_49 */ + "FP_SPI_RST", /* GPIO_50 */ + "TYPEC_I2C_SDA", /* GPIO_51 */ + "TYPEC_I2C_SCL", /* GPIO_52 */ + "CODEC_INT2_N", /* GPIO_53 */ + "CODEC_INT1_N", /* GPIO_54 */ + "APPS_I2C7_SDA", /* GPIO_55 */ + "APPS_I2C7_SCL", /* GPIO_56 */ + "FORCE_USB_BOOT", /* GPIO_57 */ + "SPKR_I2S_BCK", /* GPIO_58 */ + "SPKR_I2S_WS", /* GPIO_59 */ + "SPKR_I2S_DOUT", /* GPIO_60 */ + "SPKR_I2S_DIN", /* GPIO_61 */ + "ESE_RSTN", /* GPIO_62 */ + "TYPEC_INT", /* GPIO_63 */ + "CODEC_RESET_N", /* GPIO_64 */ + "PCM_CLK", /* GPIO_65 */ + "PCM_SYNC", /* GPIO_66 */ + "PCM_DIN", /* GPIO_67 */ + "PCM_DOUT", /* GPIO_68 */ + "CDC_44K1_CLK", /* GPIO_69 */ + "SLIMBUS_CLK", /* GPIO_70 */ + "SLIMBUS_DATA0", /* GPIO_71 */ + "SLIMBUS_DATA1", /* GPIO_72 */ + "LDO_5V_IN_EN", /* GPIO_73 */ + "NC", /* GPIO_74 */ + "TSP_RST_N", /* GPIO_75 */ + "NC", /* GPIO_76 */ + "TOUCHKEY_INT", /* GPIO_77 */ + "SPKR_I2S_MCLK", /* GPIO_78 */ + "SPKR_PA_INT", /* GPIO_79 */ + "SENSOR_RESET_N", /* GPIO_80 */ + "FP_SPI_MOSI", /* GPIO_81 */ + "FP_SPI_MISO", /* GPIO_82 */ + "FP_SPI_CS_N", /* GPIO_83 */ + "FP_SPI_CLK", /* GPIO_84 */ + "HIFI_SD", /* GPIO_85 */ + "CAM_VDD_1P05_EN", /* GPIO_86 */ + "MSM_TS_I2C_SDA", /* GPIO_87 */ + "MSM_TS_I2C_SCL", /* GPIO_88 */ + "NC", /* GPIO_89 */ + "ESE_SPI_CS_N", /* GPIO_90 */ + "NC", /* GPIO_91 */ + "NC", /* GPIO_92 */ + "NC", /* GPIO_93 */ + "NC", /* GPIO_94 */ + "NC", /* GPIO_95 */ + "NC", /* GPIO_96 */ + "GRFC_0", /* GPIO_97 */ + "GRFC_1", /* GPIO_98 */ + "NC", /* GPIO_99 */ + "GRFC_3", /* GPIO_100 */ + "GRFC_4", /* GPIO_101 */ + "NC", /* GPIO_102 */ + "NC", /* GPIO_103 */ + "GRFC_7", /* GPIO_104 */ + "UIM2_DATA", /* GPIO_105 */ + "UIM2_CLK", /* GPIO_106 */ + "UIM2_RESET", /* GPIO_107 */ + "UIM2_PRESENT", /* GPIO_108 */ + "UIM1_DATA", /* GPIO_109 */ + "UIM1_CLK", /* GPIO_110 */ + "UIM1_RESET", /* GPIO_111 */ + "UIM1_PRESENT", /* GPIO_112 */ + "UIM_BATT_ALARM", /* GPIO_113 */ + "GRFC_8", /* GPIO_114 */ + "GRFC_9", /* GPIO_115 */ + "TX_GTR_THRES", /* GPIO_116 */ + "ACC_INT", /* GPIO_117 */ + "GYRO_INT", /* GPIO_118 */ + "COMPASS_INT", /* GPIO_119 */ + "PROXIMITY_INT_N", /* GPIO_120 */ + "FP_IRQ", /* GPIO_121 */ + "TSP_TA", /* GPIO_122 */ + "HALL_INTR2", /* GPIO_123 */ + "HALL_INTR1", /* GPIO_124 */ + "TS_INT_N", /* GPIO_125 */ + "NC", /* GPIO_126 */ + "GRFC_11", /* GPIO_127 */ + "HIFI_PWR_EN", /* GPIO_128 */ + "EXT_GPS_LNA_EN", /* GPIO_129 */ + "NC", /* GPIO_130 */ + "NC", /* GPIO_131 */ + "NC", /* GPIO_132 */ + "GRFC_14", /* GPIO_133 */ + "GSM_TX2_PHASE_D", /* GPIO_134 */ + "HIFI_SW_SEL", /* GPIO_135 */ + "GRFC_15", /* GPIO_136 */ + "RFFE3_DATA", /* GPIO_137 */ + "RFFE3_CLK", /* GPIO_138 */ + "NC", /* GPIO_139 */ + "NC", /* GPIO_140 */ + "RFFE5_DATA", /* GPIO_141 */ + "RFFE5_CLK", /* GPIO_142 */ + "NC", /* GPIO_143 */ + "COEX_UART_TX", /* GPIO_144 */ + "COEX_UART_RX", /* GPIO_145 */ + "RFFE2_DATA", /* GPIO_146 */ + "RFFE2_CLK", /* GPIO_147 */ + "RFFE1_DATA", /* GPIO_148 */ + "RFFE1_CLK"; /* GPIO_149 */ + + touchscreen_default: touchscreen_default { + pins = "gpio75", "gpio125"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + + touchscreen_sleep: touchscreen_sleep { + pins = "gpio75", "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; -- cgit From 4ac46b3682c599dcb6affedf50ceb279afda9546 Mon Sep 17 00:00:00 2001 From: Raffaele Tranquillini Date: Wed, 1 Sep 2021 19:35:39 +0000 Subject: arm64: dts: qcom: msm8996: xiaomi-gemini: Add support for Xiaomi Mi 5 Add a device tree for Xiaomi Mi 5 (gemini). Signed-off-by: Raffaele Tranquillini Signed-off-by: Yassine Oudjana Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210901193214.250375-5-y.oudjana@protonmail.com --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts | 431 +++++++++++++++++++++ 2 files changed, 432 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 7e33d492bf26..2c252844356c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8996-pmi8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-dora.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-kagura.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts new file mode 100644 index 000000000000..77d508e5164a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8996-xiaomi-gemini.dts @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Raffaele Tranquillini + */ + +/dts-v1/; + +#include "msm8996-xiaomi-common.dtsi" +#include +#include +#include + +/ { + model = "Xiaomi Mi 5"; + compatible = "xiaomi,gemini", "qcom,msm8996"; + qcom,msm-id = <246 0x30001>; + qcom,pmic-id = <0x20009 0x2000a 0x00 0x00>; + qcom,board-id = <31 0>; + + clocks { + divclk2_haptics: divclk2 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + clock-output-names = "divclk2"; + + pinctrl-names = "default"; + pinctrl-0 = <&divclk2_pin_a>; + }; + }; +}; + +&adsp_pil { + firmware-name = "qcom/msm8996/gemini/adsp.mbn"; +}; + +&blsp2_i2c3 { + haptics: drv2604@5a { + compatible = "ti,drv2604"; + reg = <0x5a>; + enable-gpio = <&tlmm 93 0x00>; + mode = ; + library-sel = ; + pinctrl-names = "default","sleep"; + pinctrl-0 = <&vibrator_default>; + pinctrl-1 = <&vibrator_sleep>; + }; + + lp5562@30 { + compatible = "ti,lp5562"; + reg = <0x30>; + #address-cells = <1>; + #size-cells = <0>; + enable-gpio = <&pm8994_gpios 7 1>; + clock-mode = /bits/8 <2>; + label = "button-backlight"; + + led@0 { + reg = <0>; + chan-name = "button-backlight"; + led-cur = /bits/ 8 <0x32>; + max-cur = /bits/ 8 <0xC8>; + }; + + led@1 { + reg = <0>; + chan-name = "button-backlight1"; + led-cur = /bits/ 8 <0x32>; + max-cur = /bits/ 8 <0xC8>; + }; + }; +}; + +&blsp2_i2c6 { + synaptics@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-parent = <&tlmm>; + interrupts = <125 IRQ_TYPE_LEVEL_LOW>; + vdda-supply = <&vreg_l6a_1p8>; + vdd-supply = <&vdd_3v2_tp>; + reset-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&touchscreen_default>; + pinctrl-1 = <&touchscreen_sleep>; + }; + +}; + +&gpu { + zap-shader { + firmware-name = "qcom/msm8996/gemini/a530_zap.mbn"; + }; +}; + +&q6asmdai { + dai@0 { + reg = <0>; + }; + + dai@1 { + reg = <1>; + }; + + dai@2 { + reg = <2>; + }; +}; + +&sound { + compatible = "qcom,apq8096-sndcard"; + model = "gemini"; + audio-routing = "RX_BIAS", "MCLK", + "MM_DL1", "MultiMedia1 Playback", + "MM_DL2", "MultiMedia2 Playback", + "MultiMedia3 Capture", "MM_UL3"; + + mm1-dai-link { + link-name = "MultiMedia1"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>; + }; + }; + + mm2-dai-link { + link-name = "MultiMedia2"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>; + }; + }; + + mm3-dai-link { + link-name = "MultiMedia3"; + cpu { + sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>; + }; + }; + + slim-dai-link { + link-name = "SLIM Playback"; + cpu { + sound-dai = <&q6afedai SLIMBUS_6_RX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 6>; + }; + }; + + slimcap-dai-link { + link-name = "SLIM Capture"; + cpu { + sound-dai = <&q6afedai SLIMBUS_0_TX>; + }; + + platform { + sound-dai = <&q6routing>; + }; + + codec { + sound-dai = <&wcd9335 1>; + }; + }; +}; + +&venus { + firmware-name = "qcom/msm8996/gemini/venus.mbn"; +}; + +&rpm_requests { + pm8994-regulators { + vreg_l17a_2p8: l17 { + regulator-name = "vreg_l17a_2p8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + vreg_l29a_2p7: l29 { + regulator-name = "vreg_l29a_2p7"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + }; +}; + +&pm8994_gpios { + gpio-line-names = + "NC", /* GPIO_1 */ + "VOL_UP_N", /* GPIO_2 */ + "SPKR_ID", /* GPIO_3 */ + "PWM_HAPTICS", /* GPIO_4 */ + "INFARED_DRV", /* GPIO_5 */ + "NC", /* GPIO_6 */ + "KEYPAD_LED_EN", /* GPIO_7 */ + "WL_EN", /* GPIO_8 */ + "3P3_ENABLE", /* GPIO_9 */ + "FP_ID", /* GPIO_10 */ + "NC", /* GPIO_11 */ + "NC", /* GPIO_12 */ + "NC", /* GPIO_13 */ + "NC", /* GPIO_14 */ + "DIVCLK1_CDC", /* GPIO_15 */ + "DIVCLK2_HAPTICS", /* GPIO_16 */ + "NC", /* GPIO_17 */ + "32KHz_CLK_IN", /* GPIO_18 */ + "BT_EN", /* GPIO_19 */ + "PMIC_SLB", /* GPIO_20 */ + "UIM_BATT_ALARM", /* GPIO_21 */ + "NC"; /* GPIO_22 */ + + divclk2_pin_a: divclk2 { + pins = "gpio16"; + function = PMIC_GPIO_FUNC_FUNC2; + bias-disable; + power-source = ; + }; +}; + +&pm8994_mpps { + gpio-line-names = + "NC", /* MPP_1 */ + "CCI_TIMER1", /* MPP_2 */ + "PMIC_SLB", /* MPP_3 */ + "EXT_FET_WLED_PWR_EN_N",/* MPP_4 */ + "NC", /* MPP_5 */ + "NC", /* MPP_6 */ + "NC", /* MPP_7 */ + "NC"; /* MPP_8 */ +}; + +&pmi8994_gpios { + gpio-line-names = + "NC", /* GPIO_1 */ + "SPKR_PA_RST", /* GPIO_2 */ + "NC", /* GPIO_3 */ + "NC", /* GPIO_4 */ + "NC", /* GPIO_5 */ + "NC", /* GPIO_6 */ + "NC", /* GPIO_7 */ + "NC", /* GPIO_8 */ + "NC", /* GPIO_9 */ + "NC"; /* GPIO_10 */ +}; + +&tlmm { + gpio-line-names = + "ESE_SPI_MOSI", /* GPIO_0 */ + "ESE_SPI_MISO", /* GPIO_1 */ + "ERR_INT_N", /* GPIO_2 */ + "ESE_SPI_CLK", /* GPIO_3 */ + "MSM_UART_TX", /* GPIO_4 */ + "MSM_UART_RX", /* GPIO_5 */ + "NFC_I2C_SDA", /* GPIO_6 */ + "NFC_I2C_SCL", /* GPIO_7 */ + "LCD0_RESET_N", /* GPIO_8 */ + "NFC_IRQ", /* GPIO_9 */ + "LCD_TE", /* GPIO_10 */ + "LCD_ID_DET1", /* GPIO_11 */ + "NFC_DISABLE", /* GPIO_12 */ + "CAM_MCLK0", /* GPIO_13 */ + "NC", /* GPIO_14 */ + "CAM_MCLK2", /* GPIO_15 */ + "ESE_PWR_REQ", /* GPIO_16 */ + "CCI_I2C_SDA0", /* GPIO_17 */ + "CCI_I2C_SCL0", /* GPIO_18 */ + "CCI_I2C_SDA1", /* GPIO_19 */ + "CCI_I2C_SCL1", /* GPIO_20 */ + "NFC_DWL_REQ", /* GPIO_21 */ + "CCI_TIMER1", /* GPIO_22 */ + "WEBCAM1_RESET_N", /* GPIO_23 */ + "ESE_IRQ", /* GPIO_24 */ + "NC", /* GPIO_25 */ + "WEBCAM1_STANDBY", /* GPIO_26 */ + "NC", /* GPIO_27 */ + "NC", /* GPIO_28 */ + "NC", /* GPIO_29 */ + "CAM1_RST_N", /* GPIO_30 */ + "NC", /* GPIO_31 */ + "NC", /* GPIO_32 */ + "NC", /* GPIO_33 */ + "FP_DOME_SW", /* GPIO_34 */ + "PCI_E0_RST_N", /* GPIO_35 */ + "PCI_E0_CLKREQ_N", /* GPIO_36 */ + "PCI_E0_WAKE", /* GPIO_37 */ + "FM_INT_N", /* GPIO_38 */ + "FM_RESET_N", /* GPIO_39 */ + "NC", /* GPIO_40 */ + "QCA_UART_TXD", /* GPIO_41 */ + "QCA_UART_RXD", /* GPIO_42 */ + "QCA_UART_CTS", /* GPIO_43 */ + "QCA_UART_RTS", /* GPIO_44 */ + "MAWC_UART_TX", /* GPIO_45 */ + "MAWC_UART_RX", /* GPIO_46 */ + "NC", /* GPIO_47 */ + "NC", /* GPIO_48 */ + "AUDIO_SWITCH_EN", /* GPIO_49 */ + "FP_SPI_RST", /* GPIO_50 */ + "TYPEC_I2C_SDA", /* GPIO_51 */ + "TYPEC_I2C_SCL", /* GPIO_52 */ + "CODEC_INT2_N", /* GPIO_53 */ + "CODEC_INT1_N", /* GPIO_54 */ + "APPS_I2C7_SDA", /* GPIO_55 */ + "APPS_I2C7_SCL", /* GPIO_56 */ + "FORCE_USB_BOOT", /* GPIO_57 */ + "SPKR_I2S_BCK", /* GPIO_58 */ + "SPKR_I2S_WS", /* GPIO_59 */ + "SPKR_I2S_DOUT", /* GPIO_60 */ + "SPKR_I2S_DIN", /* GPIO_61 */ + "ESE_RSTN", /* GPIO_62 */ + "TYPEC_INT", /* GPIO_63 */ + "CODEC_RESET_N", /* GPIO_64 */ + "PCM_CLK", /* GPIO_65 */ + "PCM_SYNC", /* GPIO_66 */ + "PCM_DIN", /* GPIO_67 */ + "PCM_DOUT", /* GPIO_68 */ + "HIFI_CLK", /* GPIO_69 */ + "SLIMBUS_CLK", /* GPIO_70 */ + "SLIMBUS_DATA0", /* GPIO_71 */ + "SLIMBUS_DATA1", /* GPIO_72 */ + "LDO_5V_IN_EN", /* GPIO_73 */ + "NC", /* GPIO_74 */ + "FM_I2S_CLK", /* GPIO_75 */ + "FM_I2S_SYNC", /* GPIO_76 */ + "FM_I2S_DATA", /* GPIO_77 */ + "FM_STATUS", /* GPIO_78 */ + "NC", /* GPIO_79 */ + "SENSOR_RESET_N", /* GPIO_80 */ + "FP_SPI_MOSI", /* GPIO_81 */ + "FP_SPI_MISO", /* GPIO_82 */ + "FP_SPI_CS_N", /* GPIO_83 */ + "FP_SPI_CLK", /* GPIO_84 */ + "NC", /* GPIO_85 */ + "CAM_VDD_1P05_EN", /* GPIO_86 */ + "MSM_TS_I2C_SDA", /* GPIO_87 */ + "MSM_TS_I2C_SCL", /* GPIO_88 */ + "TS_RESOUT_N", /* GPIO_89 */ + "ESE_SPI_CS_N", /* GPIO_90 */ + "NC", /* GPIO_91 */ + "NC", /* GPIO_92 */ + "HAPTICS_EN", /* GPIO_93 */ + "NC", /* GPIO_94 */ + "NC", /* GPIO_95 */ + "NC", /* GPIO_96 */ + "NC", /* GPIO_97 */ + "GRFC_1", /* GPIO_98 */ + "NC", /* GPIO_99 */ + "GRFC_3", /* GPIO_100 */ + "GRFC_4", /* GPIO_101 */ + "NC", /* GPIO_102 */ + "NC", /* GPIO_103 */ + "GRFC_7", /* GPIO_104 */ + "UIM2_DATA", /* GPIO_105 */ + "UIM2_CLK", /* GPIO_106 */ + "UIM2_RESET", /* GPIO_107 */ + "UIM2_PRESENT", /* GPIO_108 */ + "UIM1_DATA", /* GPIO_109 */ + "UIM1_CLK", /* GPIO_110 */ + "UIM1_RESET", /* GPIO_111 */ + "UIM1_PRESENT", /* GPIO_112 */ + "UIM_BATT_ALARM", /* GPIO_113 */ + "GRFC_8", /* GPIO_114 */ + "GRFC_9", /* GPIO_115 */ + "TX_GTR_THRES", /* GPIO_116 */ + "ACCEL_INT", /* GPIO_117 */ + "GYRO_INT", /* GPIO_118 */ + "COMPASS_INT", /* GPIO_119 */ + "PROXIMITY_INT_N", /* GPIO_120 */ + "FP_IRQ", /* GPIO_121 */ + "NC", /* GPIO_122 */ + "HALL_INTR2", /* GPIO_123 */ + "HALL_INTR1", /* GPIO_124 */ + "TS_INT_N", /* GPIO_125 */ + "NC", /* GPIO_126 */ + "GRFC_11", /* GPIO_127 */ + "NC", /* GPIO_128 */ + "EXT_GPS_LNA_EN", /* GPIO_129 */ + "NC", /* GPIO_130 */ + "NC", /* GPIO_131 */ + "NC", /* GPIO_132 */ + "GRFC_14", /* GPIO_133 */ + "GSM_TX2_PHASE_D", /* GPIO_134 */ + "NC", /* GPIO_135 */ + "NC", /* GPIO_136 */ + "RFFE3_DATA", /* GPIO_137 */ + "RFFE3_CLK", /* GPIO_138 */ + "NC", /* GPIO_139 */ + "NC", /* GPIO_140 */ + "RFFE5_DATA", /* GPIO_141 */ + "RFFE5_CLK", /* GPIO_142 */ + "NC", /* GPIO_143 */ + "COEX_UART_TX", /* GPIO_144 */ + "COEX_UART_RX", /* GPIO_145 */ + "RFFE2_DATA", /* GPIO_146 */ + "RFFE2_CLK", /* GPIO_147 */ + "RFFE1_DATA", /* GPIO_148 */ + "RFFE1_CLK"; /* GPIO_149 */ + + touchscreen_default: touchscreen_default { + pins = "gpio89", "gpio125"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; + + touchscreen_sleep: touchscreen_sleep { + pins = "gpio89", "gpio125"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + vibrator_default: vibrator_default { + pins = "gpio93"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + vibrator_sleep: vibrator_sleep { + pins = "gpio93"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; -- cgit From 82ea7d411d43f60dce878252558e926f957109f0 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 2 Sep 2021 14:51:37 -0700 Subject: arm64: dts: qcom: sc7180: Base dynamic CPU power coefficients in reality The sc7180's dynamic-power-coefficient violates the device tree bindings. The bindings (arm/cpus.yaml) say that the units for the dynamic-power-coefficient are supposed to be "uW/MHz/V^2". The ones for sc7180 aren't this. Qualcomm arbitrarily picked 100 for the "little" CPUs and then picked a number for the big CPU based on this. At the time, there was a giant dicussion about this. Apparently Qualcomm Engineers were instructed not to share the actual numbers here. As part of the discussion, I pointed out [1] that these numbers shouldn't really be secret since once a device is shipping anyone can just run a script and produce them. This patch is the result of running the script I posted in that discussion on sc7180-trogdor-coachz, which is currently available for purchase by consumers. [1] https://lore.kernel.org/r/CAD=FV=U1FP0e3_AVHpauUUZtD-5X3XCwh5aT9fH_8S_FFML2Uw@mail.gmail.com/ I ran the script four times, measuring little, big, little, big. I used the 64-bit version of dhrystone 2.2 in my test. I got these results: 576 kHz, 596 mV, 20 mW, 88 Cx 768 kHz, 596 mV, 32 mW, 122 Cx 1017 kHz, 660 mV, 45 mW, 97 Cx 1248 kHz, 720 mV, 87 mW, 139 Cx 1324 kHz, 756 mV, 109 mW, 148 Cx 1516 kHz, 828 mV, 150 mW, 148 Cx 1612 kHz, 884 mV, 182 mW, 147 Cx 1708 kHz, 884 mV, 192 mW, 146 Cx 1804 kHz, 884 mV, 207 mW, 149 Cx Your dynamic-power-coefficient for cpu 0: 132 825 kHz, 596 mV, 142 mW, 401 Cx 979 kHz, 628 mV, 183 mW, 427 Cx 1113 kHz, 656 mV, 224 mW, 433 Cx 1267 kHz, 688 mV, 282 mW, 449 Cx 1555 kHz, 812 mV, 475 mW, 450 Cx 1708 kHz, 828 mV, 566 mW, 478 Cx 1843 kHz, 884 mV, 692 mW, 476 Cx 1900 kHz, 884 mV, 722 mW, 482 Cx 1996 kHz, 916 mV, 814 mW, 482 Cx 2112 kHz, 916 mV, 862 mW, 483 Cx 2208 kHz, 916 mV, 962 mW, 521 Cx 2323 kHz, 940 mV, 1060 mW, 517 Cx 2400 kHz, 956 mV, 1133 mW, 518 Cx Your dynamic-power-coefficient for cpu 6: 471 576 kHz, 596 mV, 26 mW, 103 Cx 768 kHz, 596 mV, 40 mW, 147 Cx 1017 kHz, 660 mV, 54 mW, 114 Cx 1248 kHz, 720 mV, 97 mW, 151 Cx 1324 kHz, 756 mV, 113 mW, 150 Cx 1516 kHz, 828 mV, 154 mW, 148 Cx 1612 kHz, 884 mV, 194 mW, 155 Cx 1708 kHz, 884 mV, 203 mW, 152 Cx 1804 kHz, 884 mV, 219 mW, 155 Cx Your dynamic-power-coefficient for cpu 0: 142 825 kHz, 596 mV, 148 mW, 530 Cx 979 kHz, 628 mV, 189 mW, 475 Cx 1113 kHz, 656 mV, 230 mW, 461 Cx 1267 kHz, 688 mV, 287 mW, 466 Cx 1555 kHz, 812 mV, 469 mW, 445 Cx 1708 kHz, 828 mV, 567 mW, 480 Cx 1843 kHz, 884 mV, 699 mW, 482 Cx 1900 kHz, 884 mV, 719 mW, 480 Cx 1996 kHz, 916 mV, 814 mW, 484 Cx 2112 kHz, 916 mV, 861 mW, 483 Cx 2208 kHz, 916 mV, 963 mW, 522 Cx 2323 kHz, 940 mV, 1063 mW, 520 Cx 2400 kHz, 956 mV, 1135 mW, 519 Cx Your dynamic-power-coefficient for cpu 6: 489 As you can see, the calculations aren't perfectly consistent but roughly you could say about 480 for big and 137 for little. The ratio between these numbers isn't quite the same as the ratio between the two numbers that Qualcomm used. Perhaps this is because Qualcomm measured something slightly different than the 64-bit version of dhrystone 2.2 or perhaps it's because they fudged these numbers a bit (and fudged the capacity-dmips-mhz). As per discussion [2], let's use the numbers I came up with and also un-fudge capacity-dmips-mhz. While unfudging capacity-dmips-mhz, let's scale it so that bigs are 1024 which seems to be the common practice. In general these numbers don't need to be perfectly exact. In fact, they can't be since the CPU power depends a lot on what's being run on the CPU and the big/little CPUs are each more or less efficient in different operations. Historically running the 32-bit vs. 64-bit versions of dhrystone produced notably different numbers, though I didn't test this time. We also need to scale all of the sustainable-power numbers by the same amount. I scale ones related to the big CPUs by the adjustment I made to the big dynamic-power-coefficient and the ones related to the little CPUs by the adjustment I made to the little dynamic-power-coefficient. [2] https://lore.kernel.org/r/0a865b6e-be34-6371-f9f2-9913ee1c5608@codeaurora.org/ Fixes: 71f873169a80 ("arm64: dts: qcom: sc7180: Add dynamic CPU power coefficients") Signed-off-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210902145127.v2.1.I049b30065f3c715234b6303f55d72c059c8625eb@changeid --- .../arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi | 2 +- .../arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi | 8 ++-- arch/arm64/boot/dts/qcom/sc7180.dtsi | 52 +++++++++++----------- 3 files changed, 31 insertions(+), 31 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi index a758e4d22612..81098aa9687b 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi @@ -33,7 +33,7 @@ ap_h1_spi: &spi0 {}; polling-delay = <0>; thermal-sensors = <&pm6150_adc_tm 1>; - sustainable-power = <814>; + sustainable-power = <965>; trips { skin_temp_alert0: trip-point0 { diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi index a246dbd74cc1..b7b5264888b7 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom.dtsi @@ -44,7 +44,7 @@ ap_h1_spi: &spi0 {}; }; &cpu6_thermal { - sustainable-power = <948>; + sustainable-power = <1124>; }; &cpu7_alert0 { @@ -56,7 +56,7 @@ ap_h1_spi: &spi0 {}; }; &cpu7_thermal { - sustainable-power = <948>; + sustainable-power = <1124>; }; &cpu8_alert0 { @@ -68,7 +68,7 @@ ap_h1_spi: &spi0 {}; }; &cpu8_thermal { - sustainable-power = <948>; + sustainable-power = <1124>; }; &cpu9_alert0 { @@ -80,7 +80,7 @@ ap_h1_spi: &spi0 {}; }; &cpu9_thermal { - sustainable-power = <948>; + sustainable-power = <1124>; }; &gpio_keys { diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index c8921e2d6480..495c15deacb7 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -137,8 +137,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <415>; + dynamic-power-coefficient = <137>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; @@ -162,8 +162,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <415>; + dynamic-power-coefficient = <137>; next-level-cache = <&L2_100>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, @@ -184,8 +184,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <415>; + dynamic-power-coefficient = <137>; next-level-cache = <&L2_200>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, @@ -206,8 +206,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <415>; + dynamic-power-coefficient = <137>; next-level-cache = <&L2_300>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, @@ -228,8 +228,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <415>; + dynamic-power-coefficient = <137>; next-level-cache = <&L2_400>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, @@ -250,8 +250,8 @@ cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1024>; - dynamic-power-coefficient = <100>; + capacity-dmips-mhz = <415>; + dynamic-power-coefficient = <137>; next-level-cache = <&L2_500>; operating-points-v2 = <&cpu0_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, @@ -272,8 +272,8 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1740>; - dynamic-power-coefficient = <405>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <480>; next-level-cache = <&L2_600>; operating-points-v2 = <&cpu6_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, @@ -294,8 +294,8 @@ cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1 &CLUSTER_SLEEP_0>; - capacity-dmips-mhz = <1740>; - dynamic-power-coefficient = <405>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <480>; next-level-cache = <&L2_700>; operating-points-v2 = <&cpu6_opp_table>; interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, @@ -3616,7 +3616,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 1>; - sustainable-power = <768>; + sustainable-power = <1052>; trips { cpu0_alert0: trip-point0 { @@ -3665,7 +3665,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 2>; - sustainable-power = <768>; + sustainable-power = <1052>; trips { cpu1_alert0: trip-point0 { @@ -3714,7 +3714,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 3>; - sustainable-power = <768>; + sustainable-power = <1052>; trips { cpu2_alert0: trip-point0 { @@ -3763,7 +3763,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 4>; - sustainable-power = <768>; + sustainable-power = <1052>; trips { cpu3_alert0: trip-point0 { @@ -3812,7 +3812,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 5>; - sustainable-power = <768>; + sustainable-power = <1052>; trips { cpu4_alert0: trip-point0 { @@ -3861,7 +3861,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 6>; - sustainable-power = <768>; + sustainable-power = <1052>; trips { cpu5_alert0: trip-point0 { @@ -3910,7 +3910,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 9>; - sustainable-power = <1202>; + sustainable-power = <1425>; trips { cpu6_alert0: trip-point0 { @@ -3951,7 +3951,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 10>; - sustainable-power = <1202>; + sustainable-power = <1425>; trips { cpu7_alert0: trip-point0 { @@ -3992,7 +3992,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 11>; - sustainable-power = <1202>; + sustainable-power = <1425>; trips { cpu8_alert0: trip-point0 { @@ -4033,7 +4033,7 @@ polling-delay = <0>; thermal-sensors = <&tsens0 12>; - sustainable-power = <1202>; + sustainable-power = <1425>; trips { cpu9_alert0: trip-point0 { -- cgit From d412786ab86b814d0695b9ab3c426b10572f7bb2 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Fri, 3 Sep 2021 00:03:25 +0200 Subject: arm64: dts: qcom: ipq8074: remove USB tx-fifo-resize property tx-fifo-resize is now added by default by the dwc3-qcom driver to the SNPS DWC3 child node. So, lets drop the tx-fifo-resize property from dwc3-qcom nodes as having it there will cause the dwc3-qcom driver to error and abort probe with: [ 1.362938] dwc3-qcom 8af8800.usb: unable to add property [ 1.368405] dwc3-qcom 8af8800.usb: failed to register DWC3 Core, err=-17 Fixes: cefdd52fa045 ("usb: dwc3: dwc3-qcom: Enable tx-fifo-resize property by default") Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210902220325.1783567-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index a620ac0d0b19..db333001df4d 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -487,7 +487,6 @@ interrupts = ; phys = <&qusb_phy_0>, <&usb0_ssphy>; phy-names = "usb2-phy", "usb3-phy"; - tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; @@ -528,7 +527,6 @@ interrupts = ; phys = <&qusb_phy_1>, <&usb1_ssphy>; phy-names = "usb2-phy", "usb3-phy"; - tx-fifo-resize; snps,is-utmi-l1-suspend; snps,hird-threshold = /bits/ 8 <0x0>; snps,dis_u2_susphy_quirk; -- cgit From b8d1e3d334879a3b7efddc90d51c667aa8116358 Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Fri, 3 Sep 2021 12:22:19 -0700 Subject: arm64: dts: qcom: sc7180-trogdor: Delete ADC config for unused thermistors The charger thermistor on Lazor, CoachZ rev1 and Pompom rev1+2 is either the wrong part or not stuffed at all, the same is true for the skin temperature thermistor on CoachZ rev1. The corresponding thermal zones are already disabled for these devices, in addition delete the ADC nodes of the thermistors. For Lazor and CoachZ rev1 also disable the PM6150 ADC and thermal monitor since none of the ADC channels is used. Signed-off-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210903122212.v2.1.I9777d0036ecbb749a4fb9ebb892f94c6e3a51772@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts | 14 ++++++++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts | 8 ++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts | 8 ++++++++ 4 files changed, 42 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts index 21b516e0694a..8290d036044a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dts @@ -23,6 +23,20 @@ status = "disabled"; }; +&pm6150_adc { + status = "disabled"; + + /delete-node/ skin-temp-thermistor@4e; + /delete-node/ charger-thermistor@4f; +}; + +&pm6150_adc_tm { + status = "disabled"; + + /delete-node/ charger-thermistor@0; + /delete-node/ skin-temp-thermistor@1; +}; + /* * CoachZ rev1 is stuffed with a 47k NTC as thermistor for skin temperature, * which currently is not supported by the PM6150 ADC driver. Disable the diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi index 00535aaa43c9..86c9e750995f 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi @@ -54,6 +54,18 @@ ap_ts_pen_1v8: &i2c4 { compatible = "boe,nv133fhm-n62"; }; +&pm6150_adc { + status = "disabled"; + + /delete-node/ charger-thermistor@4f; +}; + +&pm6150_adc_tm { + status = "disabled"; + + /delete-node/ charger-thermistor@0; +}; + &trackpad { interrupts = <58 IRQ_TYPE_EDGE_FALLING>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts index e122a6b481ff..76a130bad60a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dts @@ -26,6 +26,14 @@ status = "disabled"; }; +&pm6150_adc { + /delete-node/ charger-thermistor@4f; +}; + +&pm6150_adc_tm { + /delete-node/ charger-thermistor@0; +}; + &pp3300_hub { /* pp3300_l7c is used to power the USB hub */ /delete-property/regulator-always-on; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts index 4f32e6733f4c..88cf2246c18a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dts @@ -22,3 +22,11 @@ &charger_thermal { status = "disabled"; }; + +&pm6150_adc { + /delete-node/ charger-thermistor@4f; +}; + +&pm6150_adc_tm { + /delete-node/ charger-thermistor@0; +}; -- cgit From 17d32c10a2880ae7702d8e56128a542d9c6e9c75 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:36:28 +0200 Subject: arm64: dts: qcom: pmi8998: Add node for WLED The PMI8998 PMIC has a WLED backlight controller, which is used on most MSM8998 and SDM845 based devices: add a base configuration for it and keep it disabled. This contains only the PMIC specific configuration that does not change across boards; parameters like number of strings, OVP and current limits are product specific and shall be specified in the product DT in order to achieve functionality. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123628.365968-1-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/pmi8998.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pmi8998.dtsi b/arch/arm64/boot/dts/qcom/pmi8998.dtsi index d230c510d4b7..0fef5f113f05 100644 --- a/arch/arm64/boot/dts/qcom/pmi8998.dtsi +++ b/arch/arm64/boot/dts/qcom/pmi8998.dtsi @@ -41,5 +41,17 @@ interrupt-names = "sc-err", "ocp"; }; }; + + pmi8998_wled: leds@d800 { + compatible = "qcom,pmi8998-wled"; + reg = <0xd800 0xd900>; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp", "short"; + label = "backlight"; + + status = "disabled"; + }; + }; }; -- cgit From 63750607afad67e57841689b01a9425822503e0c Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Sun, 5 Sep 2021 18:58:16 +0200 Subject: arm64: dts: qcom: ipq8074: add SPMI bus IPQ8074 uses SPMI for communication with the PMIC, so since its already supported add the DT node for it. Signed-off-by: Robert Marko Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210905165816.655275-1-robimarko@gmail.com --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index db333001df4d..e5b5457b550f 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -293,6 +293,25 @@ #reset-cells = <0x1>; }; + spmi_bus: spmi@200f000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x0200f000 0x001000>, + <0x02400000 0x800000>, + <0x02c00000 0x800000>, + <0x03800000 0x200000>, + <0x0200a000 0x000700>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupts = ; + interrupt-names = "periph_irq"; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; + sdhc_1: sdhci@7824900 { compatible = "qcom,sdhci-msm-v4"; reg = <0x7824900 0x500>, <0x7824000 0x800>; -- cgit From be0416a3f9173aaa1f946ee0dbc4c146a295834d Mon Sep 17 00:00:00 2001 From: Matthias Kaehlcke Date: Thu, 9 Sep 2021 12:21:01 -0700 Subject: arm64: dts: qcom: Add sc7180-trogdor-homestar Homestar is a trogdor variant. The DT bits are essentially the same as in the downstream tree, except for: - skip -rev0 and rev1 which were early builds and have their issues, it's not very useful to support them upstream - don't include the .dtsi for the MIPI cameras, which doesn't exist upstream Signed-off-by: Matthias Kaehlcke Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909122053.1.Ieafda79b74f74a2b15ed86e181c06a3060706ec5@changeid --- arch/arm64/boot/dts/qcom/Makefile | 2 + .../boot/dts/qcom/sc7180-trogdor-homestar-r2.dts | 20 ++ .../boot/dts/qcom/sc7180-trogdor-homestar-r3.dts | 15 + .../boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 335 +++++++++++++++++++++ 4 files changed, 372 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts create mode 100644 arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 2c252844356c..1b7130de1b61 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -50,6 +50,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r1-lte.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-coachz-r3-lte.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r2.dtb +dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-homestar-r3.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r0.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1.dtb dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-lazor-r1-kb.dtb diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts new file mode 100644 index 000000000000..db6c2da67cea --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r2.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Homestar board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-homestar.dtsi" + +/ { + model = "Google Homestar (rev2)"; + compatible = "google,homestar-rev2","google,homestar-rev23", "qcom,sc7180"; +}; + +&panel { + /delete-property/hpd-gpios; + no-hpd; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts new file mode 100644 index 000000000000..3fd8aa5bb7a6 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar-r3.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Homestar board device tree source + * + * Copyright 2021 Google LLC. + */ + +/dts-v1/; + +#include "sc7180-trogdor-homestar.dtsi" + +/ { + model = "Google Homestar (rev3+)"; + compatible = "google,homestar", "qcom,sc7180"; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi new file mode 100644 index 000000000000..cd3054226865 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -0,0 +1,335 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Google Homestar board device tree source + * + * Copyright 2021 Google LLC. + */ + +#include "sc7180.dtsi" + +ap_ec_spi: &spi6 {}; +ap_h1_spi: &spi0 {}; + +#include "sc7180-trogdor.dtsi" + +/ { + /* BOARD-SPECIFIC TOP LEVEL NODES */ + + max98360a_1: max98360a_1 { + compatible = "maxim,max98360a"; + #sound-dai-cells = <0>; + }; + + max98360a_2: max98360a_2 { + compatible = "maxim,max98360a"; + #sound-dai-cells = <0>; + }; + + max98360a_3: max98360a_3 { + compatible = "maxim,max98360a"; + #sound-dai-cells = <0>; + }; + + pp3300_touch: pp3300-touch { + compatible = "regulator-fixed"; + regulator-name = "pp3300_touch"; + + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&en_pp3300_touch>; + + vin-supply = <&pp3300_a>; + }; + + thermal-zones { + skin_temp_thermal: skin-temp-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + + thermal-sensors = <&pm6150_adc_tm 1>; + sustainable-power = <814>; + + trips { + skin_temp_alert0: trip-point0 { + temperature = <55000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin_temp_alert1: trip-point1 { + temperature = <58000>; + hysteresis = <1000>; + type = "passive"; + }; + + skin-temp-crit { + temperature = <73000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&skin_temp_alert0>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + + map1 { + trip = <&skin_temp_alert1>; + cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; +}; + +&ap_tp_i2c { + status = "disabled"; +}; + +ap_ts_pen_1v8: &i2c4 { + status = "okay"; + clock-frequency = <400000>; + + ap_ts: touchscreen@14 { + compatible = "goodix,gt7375p"; + reg = <0x14>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_l>, <&ts_reset_l>; + + interrupt-parent = <&tlmm>; + interrupts = <9 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 8 GPIO_ACTIVE_LOW>; + + vdd-supply = <&pp3300_touch>; + }; +}; + +/* Panel controls backlight over aux channel */ + +&backlight { + status = "disabled"; +}; + +&camcc { + status = "okay"; +}; + +&panel { + compatible = "samsung,atna33xc20"; + enable-gpios = <&tlmm 12 GPIO_ACTIVE_HIGH>; + /delete-property/ backlight; +}; + +&pm6150_adc { + skin-temp-thermistor@4d { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; +}; + +&pm6150_adc_tm { + status = "okay"; + + skin-temp-thermistor@1 { + reg = <1>; + io-channels = <&pm6150_adc ADC5_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + +&pp3300_dx_edp { + gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>; +}; + +&secondary_mi2s { + qcom,playback-sd-lines = <0 1>; +}; + +&sound_multimedia1_codec { + sound-dai = <&max98360a>, <&max98360a_1>, <&max98360a_2>, <&max98360a_3> ; +}; + +&wifi { + qcom,ath10k-calibration-variant = "GO_HOMESTAR"; +}; + +/* PINCTRL - modifications to sc7180-trogdor.dtsi */ + +&en_pp3300_dx_edp { + pinmux { + pins = "gpio67"; + }; + + pinconf { + pins = "gpio67"; + }; +}; + +&sec_mi2s_active{ + pinmux { + pins = "gpio49", "gpio50", "gpio51", "gpio52"; + function = "mi2s_1"; + }; +}; + +&ts_reset_l { + pinconf { + /* + * We want reset state by default and it will be up to the + * driver to disable this when it's ready. + */ + output-low; + }; +}; + +/* PINCTRL - board-specific pinctrl */ + +&tlmm { + gpio-line-names = "HUB_RST_L", + "AP_RAM_ID0", + "AP_SKU_ID2", + "AP_RAM_ID1", + "", + "AP_RAM_ID2", + "UF_CAM_EN", + "WF_CAM_EN", + "TS_RESET_L", + "TS_INT_L", + "", + "EDP_BRIJ_IRQ", + "AP_EDP_BKLTEN", + "UF_CAM_MCLK", + "WF_CAM_CLK", + "EDP_BRIJ_I2C_SDA", + "EDP_BRIJ_I2C_SCL", + "UF_CAM_SDA", + "UF_CAM_SCL", + "WF_CAM_SDA", + "WF_CAM_SCL", + "AVEE_LCD_EN", + "", + "AMP_EN", + "AMP_EN2", + "AP_SAR_SENSOR_SDA", + "AP_SAR_SENSOR_SCL", + "SEL_LCM", + "HP_IRQ", + "WF_CAM_RST_L", + "UF_CAM_RST_L", + "AP_BRD_ID2", + "BRIJ_SUSPEND", + "AP_BRD_ID0", + "AP_H1_SPI_MISO", + "AP_H1_SPI_MOSI", + "AP_H1_SPI_CLK", + "AP_H1_SPI_CS_L", + "BT_UART_CTS", + "BT_UART_RTS", + "BT_UART_TXD", + "BT_UART_RXD", + "H1_AP_INT_ODL", + "", + "UART_AP_TX_DBG_RX", + "UART_DBG_TX_AP_RX", + "HP_I2C_SDA", + "HP_I2C_SCL", + "FORCED_USB_BOOT", + "AMP_BCLK", + "AMP_LRCLK", + "AMP_DIN", + "AMP_DIN_2", + "HP_BCLK", + "HP_LRCLK", + "HP_DOUT", + "HP_DIN", + "HP_MCLK", + "AP_SKU_ID0", + "AP_EC_SPI_MISO", + "AP_EC_SPI_MOSI", + "AP_EC_SPI_CLK", + "AP_EC_SPI_CS_L", + "AP_SPI_CLK", + "AP_SPI_MOSI", + "AP_SPI_MISO", + /* + * AP_FLASH_WP_L is crossystem ABI. Schematics + * call it BIOS_FLASH_WP_L. + */ + "AP_FLASH_WP_L", + "EN_PP3300_DX_EDP", + "AP_SPI_CS0_L", + "SD_CD_ODL", + "", + "", + "", + "WLAN_SW_CTRL", + "", + "REPORT_E", + "VDD_RESET_1.8V", + "ID0", + "", + "ID1", + "AVDD_LCD_EN", + "MIPI_1.8V_EN", + "", + "CODEC_PWR_EN", + "HUB_EN", + "", + "PP1800_MIPI_SW_EN", + "EN_PP3300_TOUCH", + "", + "", + "AP_SKU_ID1", + "AP_RST_REQ", + "", + "AP_BRD_ID1", + "AP_EC_INT_L", + "SDM_GRFC_3", + "", + "", + "BOOT_CONFIG_4", + "BOOT_CONFIG_2", + "", + "", + "", + "", + "EDP_BRIJ_EN", + "", + "", + "BOOT_CONFIG_3", + "WCI2_LTE_COEX_TXD", + "WCI2_LTE_COEX_RXD", + "", + "", + "", + "", + "FORCED_USB_BOOT_POL", + "AP_TS_PEN_I2C_SDA", + "AP_TS_PEN_I2C_SCL", + "DP_HOT_PLUG_DET", + "EC_IN_RW_ODL"; + + en_pp3300_touch: en-pp3300-touch { + pinmux { + pins = "gpio87"; + function = "gpio"; + }; + + pinconf { + pins = "gpio87"; + drive-strength = <2>; + bias-disable; + }; + }; +}; -- cgit From 425f30cc843c727bc7753a0d33710d1e4a999168 Mon Sep 17 00:00:00 2001 From: Kuogee Hsieh Date: Thu, 9 Sep 2021 12:49:58 -0700 Subject: arm64: dts: qcom: sc7280: fix display port phy reg property Existing display port phy reg property is derived from usb phy which map display port phy pcs to wrong address which cause aux init with wrong address and prevent both dpcd read and write from working. Fix this problem by assigning correct pcs address to display port phy reg property. Fixes: bb9efa59c665 ("arm64: dts: qcom: sc7280: Add USB related nodes") Signed-off-by: Kuogee Hsieh Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631216998-10049-1-git-send-email-khsieh@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 53a21d086178..1c5e4565e88b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1258,15 +1258,11 @@ dp_phy: dp-phy@88ea200 { reg = <0 0x088ea200 0 0x200>, <0 0x088ea400 0 0x200>, - <0 0x088eac00 0 0x400>, + <0 0x088eaa00 0 0x200>, <0 0x088ea600 0 0x200>, - <0 0x088ea800 0 0x200>, - <0 0x088eaa00 0 0x100>; + <0 0x088ea800 0 0x200>; #phy-cells = <0>; #clock-cells = <1>; - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "pipe0"; - clock-output-names = "usb3_phy_pipe_clk_src"; }; }; -- cgit From b464f08ca769947c4bb9d37548c21711efca326b Mon Sep 17 00:00:00 2001 From: Steev Klimaszewski Date: Tue, 14 Sep 2021 13:16:03 -0500 Subject: arm64: dts: qcom: c630: add second channel for wifi On the Lenovo Yoga C630, the WiFi/BT chip can use both RF channels/antennas, so add the regulator for it. Signed-off-by: Steev Klimaszewski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210914181603.32708-1-steev@kali.org --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 385e5029437d..cb11b963d68a 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -230,6 +230,9 @@ }; vreg_l23a_3p3: ldo23 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; }; vdda_qusb_hs0_3p1: @@ -615,6 +618,7 @@ vddxo-supply = <&vreg_l7a_1p8>; vddrf-supply = <&vreg_l17a_1p3>; vddch0-supply = <&vreg_l25a_3p3>; + vddch1-supply = <&vreg_l23a_3p3>; max-speed = <3200000>; }; }; @@ -729,6 +733,7 @@ vdd-1.8-xo-supply = <&vreg_l7a_1p8>; vdd-1.3-rfa-supply = <&vreg_l17a_1p3>; vdd-3.3-ch0-supply = <&vreg_l25a_3p3>; + vdd-3.3-ch1-supply = <&vreg_l23a_3p3>; qcom,snoc-host-cap-8bit-quirk; }; -- cgit From 0f6b380d580cd081d5e385d349f55dfc52e3d68c Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Mon, 31 May 2021 15:44:53 -0700 Subject: arm64: dts: qcom: apq8016-sbc: Update modem and WiFi firmware path The firmware for the modem and WiFi subsystems platform specific and is signed with a OEM specific key (or a test key). In order to support more than a single device it is therefor not possible to rely on the default path and stash these files directly in the firmware directory. This has already been addressed for other platforms, but the APQ8016 SBC (aka db410c) was never finished upstream. Signed-off-by: Bjorn Andersson Reviewed-by: Stephan Gerhold Tested-by: Stephan Gerhold Link: https://lore.kernel.org/r/20210531224453.783218-1-bjorn.andersson@linaro.org --- arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 12 ++++++++++++ arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi index f8d8f3e3664e..351c68d29afb 100644 --- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi +++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi @@ -305,6 +305,12 @@ status = "okay"; }; +&mpss { + status = "okay"; + + firmware-name = "qcom/msm8916/mba.mbn", "qcom/msm8916/modem.mbn"; +}; + &pm8916_resin { status = "okay"; linux,code = ; @@ -312,6 +318,8 @@ &pronto { status = "okay"; + + firmware-name = "qcom/msm8916/wcnss.mbn"; }; &sdhc_1 { @@ -394,6 +402,10 @@ qcom,mbhc-vthreshold-high = <75 150 237 450 500>; }; +&wcnss_ctrl { + firmware-name = "qcom/msm8916/WCNSS_qcom_wlan_nv.bin"; +}; + /* Enable CoreSight */ &cti0 { status = "okay"; }; &cti1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 3f85e34a8ce6..008b98fe8c6b 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1765,7 +1765,7 @@ label = "pronto"; - wcnss { + wcnss_ctrl: wcnss { compatible = "qcom,wcnss"; qcom,smd-channels = "WCNSS_CTRL"; -- cgit From ec04b0ebef7c5ac75048ba3a7d99878d9eb5c2ff Mon Sep 17 00:00:00 2001 From: Rajendra Nayak Date: Wed, 25 Aug 2021 16:06:58 +0530 Subject: arm64: dts: qcom: sc7280: Define CPU topology sc7280 has 8 big.LITTLE CPUs setup with DynamIQ, so all cores are within the same CPU cluster. Add cpu-map to define the CPU topology. Signed-off-by: Rajendra Nayak Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1629887818-28489-1-git-send-email-rnayak@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 1c5e4565e88b..a4b4277bca02 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -219,6 +219,42 @@ }; }; + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + idle-states { entry-method = "psci"; -- cgit From 3509de752ea14c7e5781b3a56a4a0bf832f5723a Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 29 Aug 2021 19:16:26 +0800 Subject: arm64: dts: qcom: ipq6018: Fix qcom,controlled-remotely property Property qcom,controlled-remotely should be boolean. Fix it. Signed-off-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210829111628.5543-2-shawn.guo@linaro.org --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index d2fe58e0eb7a..7b6205c180df 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -200,7 +200,7 @@ clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <1>; - qcom,controlled-remotely = <1>; + qcom,controlled-remotely; qcom,config-pipe-trust-reg = <0>; }; -- cgit From 8c97f0ac4dc8f1743eb8e8a49f66189e13ae45e9 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 29 Aug 2021 19:16:27 +0800 Subject: arm64: dts: qcom: ipq8074: Fix qcom,controlled-remotely property Property qcom,controlled-remotely should be boolean. Fix it. Signed-off-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210829111628.5543-3-shawn.guo@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index e5b5457b550f..cc3a178eec8a 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -220,7 +220,7 @@ clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <1>; - qcom,controlled-remotely = <1>; + qcom,controlled-remotely; status = "disabled"; }; -- cgit From 1c8bf398b6b51eb085a49036ad8f9c000171cce1 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 29 Aug 2021 19:16:28 +0800 Subject: arm64: dts: qcom: sdm845: Fix qcom,controlled-remotely property Property qcom,controlled-remotely should be boolean. Fix it. Signed-off-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210829111628.5543-4-shawn.guo@linaro.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index d18f7b419d2e..10d0fcea4af0 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2315,7 +2315,7 @@ clock-names = "bam_clk"; #dma-cells = <1>; qcom,ee = <0>; - qcom,controlled-remotely = <1>; + qcom,controlled-remotely; iommus = <&apps_smmu 0x704 0x1>, <&apps_smmu 0x706 0x1>, <&apps_smmu 0x714 0x1>, -- cgit From 65751ebea0a726670935990592f4ce9bfd20f13b Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Mon, 30 Aug 2021 08:06:37 -0700 Subject: arm64: dts: qcom: sc7280: Move the SD CD GPIO pin out of the dtsi file There's nothing magical about GPIO91 and boards could use different GPIOs for card detect. Move the pin out of the dtsi file and to the only existing board file. Signed-off-by: Douglas Anderson Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210830080621.1.Ia15d97bc4a81f2916290e23a8fde9cbc66186159@changeid --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 1 + arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 99f9ee5d13f5..3268f24a667b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -340,6 +340,7 @@ }; sd-cd { + pins = "gpio91"; bias-pull-up; }; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index a4b4277bca02..7a2d68aa987d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1605,10 +1605,6 @@ data { pins = "sdc2_data"; }; - - sd-cd { - pins = "gpio91"; - }; }; sdc2_off: sdc2-off { -- cgit From bbef0142f52984c3f8faaa4f70174235478b0613 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 31 Aug 2021 13:23:25 +0800 Subject: arm64: dts: qcom: Update BAM DMA node name per DT schema Follow dma-controller.yaml schema to use `dma-controller` as node name of BAM DMA devices. Signed-off-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210831052325.21229-1-shawn.guo@linaro.org --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 +- arch/arm64/boot/dts/qcom/msm8996.dtsi | 4 ++-- arch/arm64/boot/dts/qcom/msm8998.dtsi | 2 +- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index cc3a178eec8a..aebd0949ac81 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -212,7 +212,7 @@ status = "disabled"; }; - cryptobam: dma@704000 { + cryptobam: dma-controller@704000 { compatible = "qcom,bam-v1.7.0"; reg = <0x00704000 0x20000>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 1f4eca018183..eb3ec5ff46eb 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -2714,7 +2714,7 @@ status = "disabled"; }; - blsp1_dma: dma@7544000 { + blsp1_dma: dma-controller@7544000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07544000 0x2b000>; interrupts = ; @@ -2774,7 +2774,7 @@ status = "disabled"; }; - blsp2_dma: dma@7584000 { + blsp2_dma: dma-controller@7584000 { compatible = "qcom,bam-v1.7.0"; reg = <0x07584000 0x2b000>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index 460e6b37d82a..3c1f13385dd7 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -2292,7 +2292,7 @@ #size-cells = <0>; }; - blsp2_dma: dma@c184000 { + blsp2_dma: dma-controller@c184000 { compatible = "qcom,bam-v1.7.0"; reg = <0x0c184000 0x25000>; interrupts = ; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 10d0fcea4af0..033614ab92d1 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2307,7 +2307,7 @@ }; }; - cryptobam: dma@1dc4000 { + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.0"; reg = <0 0x01dc4000 0 0x24000>; interrupts = ; -- cgit From 20bb9e3dd2e4896f1bbaecd952b48bdc3200fc97 Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Tue, 31 Aug 2021 08:57:32 +0300 Subject: arm64: dts: qcom: ipq6018: add usb3 DT description Based on downstream codeaurora code. Tested (USB2 only) on IPQ6010 based hardware. Signed-off-by: Kathiravan T Signed-off-by: Baruch Siach [bjorn: Changed dwc3 node name to usb, per binding] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/ebc2d340d566fa2d43127e253d5b8b134a87a78e.1630389452.git.baruch@tkos.co.il --- arch/arm64/boot/dts/qcom/ipq6018.dtsi | 83 +++++++++++++++++++++++++++++++++++ 1 file changed, 83 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 7b6205c180df..c79ba072e88f 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -671,6 +671,89 @@ }; }; + ssphy_0: ssphy@78000 { + compatible = "qcom,ipq6018-qmp-usb3-phy"; + reg = <0x0 0x78000 0x0 0x1C4>; + #address-cells = <2>; + #size-cells = <2>; + #clock-cells = <1>; + ranges; + + clocks = <&gcc GCC_USB0_AUX_CLK>, + <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, <&xo>; + clock-names = "aux", "cfg_ahb", "ref"; + + resets = <&gcc GCC_USB0_PHY_BCR>, + <&gcc GCC_USB3PHY_0_PHY_BCR>; + reset-names = "phy","common"; + status = "disabled"; + + usb0_ssphy: lane@78200 { + reg = <0x0 0x00078200 0x0 0x130>, /* Tx */ + <0x0 0x00078400 0x0 0x200>, /* Rx */ + <0x0 0x00078800 0x0 0x1F8>, /* PCS */ + <0x0 0x00078600 0x0 0x044>; /* PCS misc */ + #phy-cells = <0>; + clocks = <&gcc GCC_USB0_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "gcc_usb0_pipe_clk_src"; + }; + }; + + qusb_phy_0: qusb@79000 { + compatible = "qcom,ipq6018-qusb2-phy"; + reg = <0x0 0x079000 0x0 0x180>; + #phy-cells = <0>; + + clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, + <&xo>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2_0_PHY_BCR>; + status = "disabled"; + }; + + usb3: usb3@8A00000 { + compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; + reg = <0x0 0x8AF8800 0x0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_SLEEP_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + clock-names = "sys_noc_axi", + "master", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, + <&gcc GCC_USB0_MASTER_CLK>, + <&gcc GCC_USB0_MOCK_UTMI_CLK>; + assigned-clock-rates = <133330000>, + <133330000>, + <20000000>; + + resets = <&gcc GCC_USB0_BCR>; + status = "disabled"; + + dwc_0: usb@8A00000 { + compatible = "snps,dwc3"; + reg = <0x0 0x8A00000 0x0 0xcd00>; + interrupts = ; + phys = <&qusb_phy_0>, <&usb0_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + tx-fifo-resize; + snps,is-utmi-l1-suspend; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + snps,ref-clock-period-ns = <0x32>; + dr_mode = "host"; + }; + }; }; wcss: wcss-smp2p { -- cgit From d68170ae44dda039785bf475f710425ce148e8fe Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Sep 2021 18:13:39 +0300 Subject: arm64: dts: qcom: pm8150: use qcom,pm8998-pon binding Change pm8150 to use the qcom,pm8998-pon compatible string for the pon in order to pass reboot mode properly. Fixes: 5101f22a5c37 ("arm64: dts: qcom: pm8150: Add base dts file") Signed-off-by: Dmitry Baryshkov Tested-by: Amit Pundir Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210916151341.1797512-1-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index c566a64b1373..00385b1fd358 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -48,7 +48,7 @@ #size-cells = <0>; pon: power-on@800 { - compatible = "qcom,pm8916-pon"; + compatible = "qcom,pm8998-pon"; reg = <0x0800>; pon_pwrkey: pwrkey { -- cgit From aea101ba752d27042f0f45b6ea6bdc022d9e334d Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Sep 2021 18:13:40 +0300 Subject: arm64: dts: qcom: pm8150: specify reboot mode magics Specify recovery and bootloader magic values to be programmed by the qcom-pon driver. This allows the bootloader to handle reboot-to-bootloader functionality. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210916151341.1797512-2-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/pm8150.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8150.dtsi b/arch/arm64/boot/dts/qcom/pm8150.dtsi index 00385b1fd358..0df76f7b1cc1 100644 --- a/arch/arm64/boot/dts/qcom/pm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8150.dtsi @@ -50,6 +50,8 @@ pon: power-on@800 { compatible = "qcom,pm8998-pon"; reg = <0x0800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; pon_pwrkey: pwrkey { compatible = "qcom,pm8941-pwrkey"; -- cgit From 7a5fca955037436108b6e175ff83bb7063a109f6 Mon Sep 17 00:00:00 2001 From: Dmitry Baryshkov Date: Thu, 16 Sep 2021 18:13:41 +0300 Subject: arm64: dts: qcom: qrb5165-rb5: enabled pwrkey and resin nodes Enable powerkey and resin nodes to let the board handle POWER and Volume- keys properly. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210916151341.1797512-3-dmitry.baryshkov@linaro.org --- arch/arm64/boot/dts/qcom/qrb5165-rb5.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts index 8ac96f8e79d4..28d5b5528516 100644 --- a/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts +++ b/arch/arm64/boot/dts/qcom/qrb5165-rb5.dts @@ -804,6 +804,16 @@ }; }; +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + status = "okay"; + + linux,code = ; +}; + &qupv3_id_0 { status = "okay"; }; -- cgit From bd7dd79ca335604cf0d674b29685280343042249 Mon Sep 17 00:00:00 2001 From: satya priya Date: Fri, 17 Sep 2021 16:40:40 +0530 Subject: arm64: dts: qcom: sc7280: Add volume up support for sc7280-idp Add pm7325 PMIC gpio support for vol+ on sc7280-idp. Signed-off-by: satya priya Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631877040-26587-1-git-send-email-skakit@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 3268f24a667b..feb50639ad76 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -7,11 +7,32 @@ #include #include +#include #include "sc7280.dtsi" #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" +/ { + gpio-keys { + compatible = "gpio-keys"; + label = "gpio-keys"; + + pinctrl-names = "default"; + pinctrl-0 = <&key_vol_up_default>; + + volume-up { + label = "volume_up"; + gpios = <&pm7325_gpios 6 GPIO_ACTIVE_LOW>; + linux,input-type = <1>; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + linux,can-disable; + }; + }; +}; + &apps_rsc { pm7325-regulators { compatible = "qcom,pm7325-rpmh-regulators"; @@ -288,6 +309,17 @@ /* PINCTRL - additions to nodes defined in sc7280.dtsi */ +&pm7325_gpios { + key_vol_up_default: key-vol-up-default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + power-source = <0>; + qcom,drive-strength = <3>; + }; +}; + &qup_uart5_default { tx { pins = "gpio46"; -- cgit From c8efde9f6b18b66da3c8b7c77bd1ac422b872aee Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Wed, 11 Aug 2021 06:12:51 +0530 Subject: arm64: dts: qcom: sc7280: Add clock controller ID headers Add the GPUCC, DISPCC and VIDEOCC clock headers which were dropped earlier. Signed-off-by: Taniya Das Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1628642571-25383-1-git-send-email-tdas@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 7a2d68aa987d..e4ba5c5dbe19 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5,8 +5,11 @@ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ +#include #include +#include #include +#include #include #include #include -- cgit From 96c471970b7bcb6a9b0dae3b691c1d52b1f04359 Mon Sep 17 00:00:00 2001 From: Akhil P Oommen Date: Wed, 11 Aug 2021 19:53:54 +0530 Subject: arm64: dts: qcom: sc7280: Add gpu support Add the necessary dt nodes for gpu support in sc7280. Signed-off-by: Akhil P Oommen Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1628691835-36958-1-git-send-email-akhilpo@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 115 +++++++++++++++++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index e4ba5c5dbe19..5e090555b85a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -686,6 +686,85 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; + gpu@3d00000 { + compatible = "qcom,adreno-635.0", "qcom,adreno"; + #stream-id-cells = <16>; + reg = <0 0x03d00000 0 0x40000>, + <0 0x03d9e000 0 0x1000>, + <0 0x03d61000 0 0x800>; + reg-names = "kgsl_3d0_reg_memory", + "cx_mem", + "cx_dbgc"; + interrupts = ; + iommus = <&adreno_smmu 0 0x401>; + operating-points-v2 = <&gpu_opp_table>; + qcom,gmu = <&gmu>; + interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "gfx-mem"; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-315000000 { + opp-hz = /bits/ 64 <315000000>; + opp-level = ; + opp-peak-kBps = <1804000>; + }; + + opp-450000000 { + opp-hz = /bits/ 64 <450000000>; + opp-level = ; + opp-peak-kBps = <4068000>; + }; + + opp-550000000 { + opp-hz = /bits/ 64 <550000000>; + opp-level = ; + opp-peak-kBps = <6832000>; + }; + }; + }; + + gmu: gmu@3d69000 { + compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; + reg = <0 0x03d6a000 0 0x34000>, + <0 0x3de0000 0 0x10000>, + <0 0x0b290000 0 0x10000>; + reg-names = "gmu", "rscc", "gmu_pdc"; + interrupts = , + ; + interrupt-names = "hfi", "gmu"; + clocks = <&gpucc 5>, + <&gpucc 8>, + <&gcc GCC_DDRSS_GPU_AXI_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gpucc 2>, + <&gpucc 15>, + <&gpucc 11>; + clock-names = "gmu", + "cxo", + "axi", + "memnoc", + "ahb", + "hub", + "smmu_vote"; + power-domains = <&gpucc 0>, + <&gpucc 1>; + power-domain-names = "cx", + "gx"; + iommus = <&adreno_smmu 5 0x400>; + operating-points-v2 = <&gmu_opp_table>; + + gmu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-level = ; + }; + }; + }; + gpucc: clock-controller@3d90000 { compatible = "qcom,sc7280-gpucc"; reg = <0 0x03d90000 0 0x9000>; @@ -700,6 +779,42 @@ #power-domain-cells = <1>; }; + adreno_smmu: iommu@3da0000 { + compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", "arm,mmu-500"; + reg = <0 0x03da0000 0 0x20000>; + #iommu-cells = <2>; + #global-interrupts = <2>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + ; + + clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc 2>, + <&gpucc 11>, + <&gpucc 5>, + <&gpucc 15>, + <&gpucc 13>; + clock-names = "gcc_gpu_memnoc_gfx_clk", + "gcc_gpu_snoc_dvm_gfx_clk", + "gpu_cc_ahb_clk", + "gpu_cc_hlos1_vote_gpu_smmu_clk", + "gpu_cc_cx_gmu_clk", + "gpu_cc_hub_cx_int_clk", + "gpu_cc_hub_aon_clk"; + + power-domains = <&gpucc 0>; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, -- cgit From b39f266c19f02c6bf4f39c9a5bf09482b64e96c1 Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 11 Aug 2021 19:53:55 +0530 Subject: arm64: dts: qcom: sc7280: Add gpu thermal zone cooling support Add cooling-cells property and the cooling maps for the gpu thermal zones to support GPU thermal cooling. Signed-off-by: Manaf Meethalavalappu Pallikunhi Signed-off-by: Akhil P Oommen Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1628691835-36958-2-git-send-email-akhilpo@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 29 ++++++++++++++++++++++------- 1 file changed, 22 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 5e090555b85a..af6b5692b165 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -686,7 +686,7 @@ qcom,bcm-voters = <&apps_bcm_voter>; }; - gpu@3d00000 { + gpu: gpu@3d00000 { compatible = "qcom,adreno-635.0", "qcom,adreno"; #stream-id-cells = <16>; reg = <0 0x03d00000 0 0x40000>, @@ -701,6 +701,7 @@ qcom,gmu = <&gmu>; interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "gfx-mem"; + #cooling-cells = <2>; gpu_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2617,16 +2618,16 @@ }; gpuss0-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens1 1>; trips { gpuss0_alert0: trip-point0 { - temperature = <90000>; + temperature = <95000>; hysteresis = <2000>; - type = "hot"; + type = "passive"; }; gpuss0_crit: gpuss0-crit { @@ -2635,19 +2636,26 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss0_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; gpuss1-thermal { - polling-delay-passive = <0>; + polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&tsens1 2>; trips { gpuss1_alert0: trip-point0 { - temperature = <90000>; + temperature = <95000>; hysteresis = <2000>; - type = "hot"; + type = "passive"; }; gpuss1_crit: gpuss1-crit { @@ -2656,6 +2664,13 @@ type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&gpuss1_alert0>; + cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; nspss0-thermal { -- cgit From 33b89923d02153721223d69cda7d95c06a359e4a Mon Sep 17 00:00:00 2001 From: Stephen Boyd Date: Wed, 11 Aug 2021 11:19:04 -0700 Subject: arm64: dts: qcom: sc7280: Use GIC_SPI for intc cells Let's use the GIC_SPI macro instead of a plain 0 here to match other uses of the primary interrupt controller on sc7280. Suggested-by: Matthias Kaehlcke Cc: Alex Elder Signed-off-by: Stephen Boyd Reviewed-by: Alex Elder Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210811181904.779316-1-swboyd@chromium.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index af6b5692b165..8051a2639268 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -637,8 +637,8 @@ "ipa-shared", "gsi"; - interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>, - <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names = "ipa", -- cgit From 7a62bfebc8c94bdb6eb8f54f49889dc6b5b79601 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 21 Sep 2021 17:21:18 +0200 Subject: arm64: dts: qcom: msm8916: Add unit name for /soc node This fixes the following warning when building with W=1: Warning (unit_address_vs_reg): /soc: node has a reg or ranges property, but no unit name Signed-off-by: Stephan Gerhold Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210921152120.6710-1-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 008b98fe8c6b..5551dba2d5fd 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -414,7 +414,7 @@ }; }; - soc: soc { + soc: soc@0 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0 0xffffffff>; -- cgit From f633d5f74e72addccc7393ff69f32e0b34e808fb Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 21 Sep 2021 17:21:20 +0200 Subject: arm64: dts: qcom: msm8916: Add "qcom,msm8916-sdhci" compatible According to Documentation/devicetree/bindings/mmc/sdhci-msm.txt a SoC specific compatible should be used in addition to the IP version compatible, but for some reason it was never added for MSM8916. Add the "qcom,msm8916-sdhci" compatible additionally to make the device tree match the documented bindings. Signed-off-by: Stephan Gerhold Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210921152120.6710-3-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 5551dba2d5fd..973a584f1e9e 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1420,7 +1420,7 @@ }; sdhc_1: sdhci@7824000 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07824900 0x11c>, <0x07824000 0x800>; reg-names = "hc_mem", "core_mem"; @@ -1438,7 +1438,7 @@ }; sdhc_2: sdhci@7864000 { - compatible = "qcom,sdhci-msm-v4"; + compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; reg = <0x07864900 0x11c>, <0x07864000 0x800>; reg-names = "hc_mem", "core_mem"; -- cgit From 0c38d6b6a6a6f15723c875bf97bed51cfda6e4ee Mon Sep 17 00:00:00 2001 From: Sujit Kautkar Date: Mon, 20 Sep 2021 11:32:50 -0700 Subject: arm64: dts: qcom: sc7180-trogdor: Enable IPA on LTE only SKUs Enable the IPA node for LTE and skip for wifi-only SKUs Signed-off-by: Sujit Kautkar Reviewed-by: Alex Elder Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210920113220.v1.1.I904da9664f294fcf222f6f378d37eaadd72ca92e@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi | 11 +++++++++++ arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 11 ----------- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi index 469aad4e5948..fd4b71203754 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-lte-sku.dtsi @@ -17,3 +17,14 @@ firmware-name = "qcom/sc7180-trogdor/modem/mba.mbn", "qcom/sc7180-trogdor/modem/qdsp6sw.mbn"; }; + +&ipa { + status = "okay"; + + /* + * Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the + * modem needs to cover certain init steps (GSI init), and + * the AP needs to wait for it. + */ + modem-init; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 0f2b3c00e434..6a216e17b96a 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -751,17 +751,6 @@ hp_i2c: &i2c9 { }; }; -&ipa { - status = "okay"; - - /* - * Trogdor doesn't have QHEE (Qualcomm's EL2 blob), so the - * modem needs to cover certain init steps (GSI init), and - * the AP needs to wait for it. - */ - modem-init; -}; - &lpass_cpu { status = "okay"; -- cgit From 752432e40e8f0d02d0af07cce2d6d4b250be11ef Mon Sep 17 00:00:00 2001 From: Shaik Sajida Bhanu Date: Mon, 16 Aug 2021 22:20:50 +0530 Subject: arm64: dts: qcom: sc7180: Use maximum drive strength values for eMMC The current drive strength values are not sufficient on non discrete boards and this leads to CRC errors during switching to HS400 enhanced strobe mode. Hardware simulation results on non discrete boards shows up that use the maximum drive strength values for data and command lines could helps in avoiding these CRC errors. So, update data and command line drive strength values to maximum. Signed-off-by: Shaik Sajida Bhanu Reviewed-by: Douglas Anderson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1629132650-26277-1-git-send-email-sbhanu@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 6a216e17b96a..8685931553b3 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1513,13 +1513,13 @@ ap_spi_fp: &spi10 { pinconf-cmd { pins = "sdc1_cmd"; bias-pull-up; - drive-strength = <10>; + drive-strength = <16>; }; pinconf-data { pins = "sdc1_data"; bias-pull-up; - drive-strength = <10>; + drive-strength = <16>; }; pinconf-rclk { -- cgit From 07b2fb60467203a6525415022a6eefdddebe6b14 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 22 Sep 2021 16:52:08 -0300 Subject: arm64: dts: qcom: sm6125: Remove leading zeroes dtc complains about the leading zeroes: arch/arm64/boot/dts/qcom/sm6125.dtsi:497.19-503.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f121000: unit name should not have leading 0s arch/arm64/boot/dts/qcom/sm6125.dtsi:505.19-510.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f123000: unit name should not have leading 0s arch/arm64/boot/dts/qcom/sm6125.dtsi:512.19-517.6: Warning (unit_address_format): /soc/timer@f120000/frame@0f124000: unit name should not have leading 0 Remove them. Signed-off-by: Fabio Estevam Reviewed-by: Martin Botka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210922195208.1734936-1-festevam@gmail.com --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 2b37ce6a9f9c..0c1057456597 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -494,7 +494,7 @@ reg = <0x0f120000 0x1000>; clock-frequency = <19200000>; - frame@0f121000 { + frame@f121000 { frame-number = <0>; interrupts = , ; @@ -502,14 +502,14 @@ <0x0f122000 0x1000>; }; - frame@0f123000 { + frame@f123000 { frame-number = <1>; interrupts = ; reg = <0x0f123000 0x1000>; status = "disabled"; }; - frame@0f124000 { + frame@f124000 { frame-number = <2>; interrupts = ; reg = <0x0f124000 0x1000>; -- cgit From 7720ea001b528d88cdb7980cb9c97327f95a815d Mon Sep 17 00:00:00 2001 From: Roja Rani Yarubandi Date: Thu, 23 Sep 2021 17:46:12 +0530 Subject: arm64: dts: qcom: sc7280: Add QSPI node Add QSPI DT node and qspi_opp_table for SC7280 SoC. Move qspi_opp_table to / because SPI nodes assume any child node is a spi device and so we can't put the table underneath the spi controller. Signed-off-by: Roja Rani Yarubandi Signed-off-by: Rajesh Patil Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1632399378-12229-3-git-send-email-rajpat@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 61 ++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 8051a2639268..bec3468760eb 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -454,6 +454,25 @@ method = "smc"; }; + qspi_opp_table: qspi-opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -1469,6 +1488,23 @@ }; }; + qspi: spi@88dc000 { + compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; + reg = <0 0x088dc000 0 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + clock-names = "iface", "core"; + interconnects = <&gem_noc MASTER_APPSS_PROC 0 + &cnoc2 SLAVE_QSPI_0 0>; + interconnect-names = "qspi-config"; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qspi_opp_table>; + status = "disabled"; + }; + dc_noc: interconnect@90e0000 { reg = <0 0x090e0000 0 0x5080>; compatible = "qcom,sc7280-dc-noc"; @@ -1664,6 +1700,31 @@ gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; + qspi_clk: qspi-clk { + pins = "gpio14"; + function = "qspi_clk"; + }; + + qspi_cs0: qspi-cs0 { + pins = "gpio15"; + function = "qspi_cs"; + }; + + qspi_cs1: qspi-cs1 { + pins = "gpio19"; + function = "qspi_cs"; + }; + + qspi_data01: qspi-data01 { + pins = "gpio12", "gpio13"; + function = "qspi_data"; + }; + + qspi_data12: qspi-data12 { + pins = "gpio16", "gpio17"; + function = "qspi_data"; + }; + qup_uart5_default: qup-uart5-default { pins = "gpio46", "gpio47"; function = "qup13"; -- cgit From df0174b13d3f6e744a5a3dfdfc1853bb60533fdb Mon Sep 17 00:00:00 2001 From: Rajesh Patil Date: Thu, 23 Sep 2021 17:46:13 +0530 Subject: arm64: dts: qcom: sc7280: Configure SPI-NOR FLASH for sc7280-idp Add spi-nor flash node and pinctrl configurations for the SC7280 IDP. Signed-off-by: Rajesh Patil Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1632399378-12229-4-git-send-email-rajpat@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index feb50639ad76..52974796d69e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -232,6 +232,20 @@ vcc-supply = <&vreg_l1c_1p8>; }; +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <37500000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + &qupv3_id_0 { status = "okay"; }; @@ -320,6 +334,19 @@ }; }; +&qspi_cs0 { + bias-disable; +}; + +&qspi_clk { + bias-disable; +}; + +&qspi_data01 { + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; +}; + &qup_uart5_default { tx { pins = "gpio46"; -- cgit From bf6f37a3086bec4c103dc4a478b25c9adf8dd671 Mon Sep 17 00:00:00 2001 From: Roja Rani Yarubandi Date: Thu, 23 Sep 2021 17:46:14 +0530 Subject: arm64: dts: qcom: sc7280: Add QUPv3 wrapper_0 nodes Add QUPv3 wrapper_0 DT nodes for SC7280 SoC. Signed-off-by: Roja Rani Yarubandi Signed-off-by: Rajesh Patil Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1632399378-12229-5-git-send-email-rajpat@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 724 ++++++++++++++++++++++++++++++++++- 1 file changed, 722 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bec3468760eb..ec6faa5bf5fc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -473,6 +473,25 @@ }; }; + qup_opp_table: qup-opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + soc: soc@0 { #address-cells = <2>; #size-cells = <2>; @@ -575,24 +594,425 @@ qupv3_id_0: geniqup@9c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x009c0000 0 0x2000>; - clock-names = "m-ahb", "s-ahb"; clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; #address-cells = <2>; #size-cells = <2>; ranges; + iommus = <&apps_smmu 0x123 0x0>; status = "disabled"; + i2c0: i2c@980000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00980000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00980000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart0: serial@980000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00980000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c1: i2c@984000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00984000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00984000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart1: serial@984000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00984000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c2: i2c@988000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00988000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00988000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart2: serial@988000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00988000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c3: i2c@98c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0098c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c3_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0098c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart3: serial@98c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0098c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c4: i2c@990000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00990000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c4_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00990000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart4: serial@990000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00990000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c5: i2c@994000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00994000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c5_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00994000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + uart5: serial@994000 { compatible = "qcom,geni-debug-uart"; reg = <0 0x00994000 0 0x4000>; - clock-names = "se"; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; pinctrl-names = "default"; pinctrl-0 = <&qup_uart5_default>; interrupts = ; status = "disabled"; }; + + i2c6: i2c@998000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00998000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c6_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi6: spi@998000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00998000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart6: serial@998000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00998000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c7: i2c@99c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0099c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c7_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, + <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi7: spi@99c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0099c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart7: serial@99c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x0099c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; }; cnoc2: interconnect@1500000 { @@ -1725,11 +2145,311 @@ function = "qspi_data"; }; + qup_i2c0_data_clk: qup-i2c0-data-clk { + pins = "gpio0", "gpio1"; + function = "qup00"; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk { + pins = "gpio4", "gpio5"; + function = "qup01"; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk { + pins = "gpio8", "gpio9"; + function = "qup02"; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk { + pins = "gpio12", "gpio13"; + function = "qup03"; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk { + pins = "gpio16", "gpio17"; + function = "qup04"; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk { + pins = "gpio20", "gpio21"; + function = "qup05"; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk { + pins = "gpio24", "gpio25"; + function = "qup06"; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk { + pins = "gpio28", "gpio29"; + function = "qup07"; + }; + + qup_spi0_data_clk: qup-spi0-data-clk { + pins = "gpio0", "gpio1", "gpio2"; + function = "qup00"; + }; + + qup_spi0_cs: qup-spi0-cs { + pins = "gpio3"; + function = "qup00"; + }; + + qup_spi0_cs_gpio: qup-spi0-cs-gpio { + pins = "gpio3"; + function = "gpio"; + }; + + qup_spi1_data_clk: qup-spi1-data-clk { + pins = "gpio4", "gpio5", "gpio6"; + function = "qup01"; + }; + + qup_spi1_cs: qup-spi1-cs { + pins = "gpio7"; + function = "qup01"; + }; + + qup_spi1_cs_gpio: qup-spi1-cs-gpio { + pins = "gpio7"; + function = "gpio"; + }; + + qup_spi2_data_clk: qup-spi2-data-clk { + pins = "gpio8", "gpio9", "gpio10"; + function = "qup02"; + }; + + qup_spi2_cs: qup-spi2-cs { + pins = "gpio11"; + function = "qup02"; + }; + + qup_spi2_cs_gpio: qup-spi2-cs-gpio { + pins = "gpio11"; + function = "gpio"; + }; + + qup_spi3_data_clk: qup-spi3-data-clk { + pins = "gpio12", "gpio13", "gpio14"; + function = "qup03"; + }; + + qup_spi3_cs: qup-spi3-cs { + pins = "gpio15"; + function = "qup03"; + }; + + qup_spi3_cs_gpio: qup-spi3-cs-gpio { + pins = "gpio15"; + function = "gpio"; + }; + + qup_spi4_data_clk: qup-spi4-data-clk { + pins = "gpio16", "gpio17", "gpio18"; + function = "qup04"; + }; + + qup_spi4_cs: qup-spi4-cs { + pins = "gpio19"; + function = "qup04"; + }; + + qup_spi4_cs_gpio: qup-spi4-cs-gpio { + pins = "gpio19"; + function = "gpio"; + }; + + qup_spi5_data_clk: qup-spi5-data-clk { + pins = "gpio20", "gpio21", "gpio22"; + function = "qup05"; + }; + + qup_spi5_cs: qup-spi5-cs { + pins = "gpio23"; + function = "qup05"; + }; + + qup_spi5_cs_gpio: qup-spi5-cs-gpio { + pins = "gpio23"; + function = "gpio"; + }; + + qup_spi6_data_clk: qup-spi6-data-clk { + pins = "gpio24", "gpio25", "gpio26"; + function = "qup06"; + }; + + qup_spi6_cs: qup-spi6-cs { + pins = "gpio27"; + function = "qup06"; + }; + + qup_spi6_cs_gpio: qup-spi6-cs-gpio { + pins = "gpio27"; + function = "gpio"; + }; + + qup_spi7_data_clk: qup-spi7-data-clk { + pins = "gpio28", "gpio29", "gpio30"; + function = "qup07"; + }; + + qup_spi7_cs: qup-spi7-cs { + pins = "gpio31"; + function = "qup07"; + }; + + qup_spi7_cs_gpio: qup-spi7-cs-gpio { + pins = "gpio31"; + function = "gpio"; + }; + + qup_uart0_cts: qup-uart0-cts { + pins = "gpio0"; + function = "qup00"; + }; + + qup_uart0_rts: qup-uart0-rts { + pins = "gpio1"; + function = "qup00"; + }; + + qup_uart0_tx: qup-uart0-tx { + pins = "gpio2"; + function = "qup00"; + }; + + qup_uart0_rx: qup-uart0-rx { + pins = "gpio3"; + function = "qup00"; + }; + + qup_uart1_cts: qup-uart1-cts { + pins = "gpio4"; + function = "qup01"; + }; + + qup_uart1_rts: qup-uart1-rts { + pins = "gpio5"; + function = "qup01"; + }; + + qup_uart1_tx: qup-uart1-tx { + pins = "gpio6"; + function = "qup01"; + }; + + qup_uart1_rx: qup-uart1-rx { + pins = "gpio7"; + function = "qup01"; + }; + + qup_uart2_cts: qup-uart2-cts { + pins = "gpio8"; + function = "qup02"; + }; + + qup_uart2_rts: qup-uart2-rts { + pins = "gpio9"; + function = "qup02"; + }; + + qup_uart2_tx: qup-uart2-tx { + pins = "gpio10"; + function = "qup02"; + }; + + qup_uart2_rx: qup-uart2-rx { + pins = "gpio11"; + function = "qup02"; + }; + + qup_uart3_cts: qup-uart3-cts { + pins = "gpio12"; + function = "qup03"; + }; + + qup_uart3_rts: qup-uart3-rts { + pins = "gpio13"; + function = "qup03"; + }; + + qup_uart3_tx: qup-uart3-tx { + pins = "gpio14"; + function = "qup03"; + }; + + qup_uart3_rx: qup-uart3-rx { + pins = "gpio15"; + function = "qup03"; + }; + + qup_uart4_cts: qup-uart4-cts { + pins = "gpio16"; + function = "qup04"; + }; + + qup_uart4_rts: qup-uart4-rts { + pins = "gpio17"; + function = "qup04"; + }; + + qup_uart4_tx: qup-uart4-tx { + pins = "gpio18"; + function = "qup04"; + }; + + qup_uart4_rx: qup-uart4-rx { + pins = "gpio19"; + function = "qup04"; + }; + qup_uart5_default: qup-uart5-default { pins = "gpio46", "gpio47"; function = "qup13"; }; + qup_uart6_cts: qup-uart6-cts { + pins = "gpio24"; + function = "qup06"; + }; + + qup_uart6_rts: qup-uart6-rts { + pins = "gpio25"; + function = "qup06"; + }; + + qup_uart6_tx: qup-uart6-tx { + pins = "gpio26"; + function = "qup06"; + }; + + qup_uart6_rx: qup-uart6-rx { + pins = "gpio27"; + function = "qup06"; + }; + + qup_uart7_cts: qup-uart7-cts { + pins = "gpio28"; + function = "qup07"; + }; + + qup_uart7_rts: qup-uart7-rts { + pins = "gpio29"; + function = "qup07"; + }; + + qup_uart7_tx: qup-uart7-tx { + pins = "gpio30"; + function = "qup07"; + }; + + qup_uart7_rx: qup-uart7-rx { + pins = "gpio31"; + function = "qup07"; + }; + sdc1_on: sdc1-on { clk { pins = "sdc1_clk"; -- cgit From 38cd93f413fd946fa39b83d3283a6a2a21ca0789 Mon Sep 17 00:00:00 2001 From: Roja Rani Yarubandi Date: Thu, 23 Sep 2021 17:46:15 +0530 Subject: arm64: dts: qcom: sc7280: Update QUPv3 UART5 DT node Uart5 is treated as dedicated debug uart.Change the compatible as "qcom,geni-uart" in SoC DT to make it generic and later update it as "qcom,geni-debug-uart" in sc7280-idp Add interconnects and power-domains. Split the pinctrl functions and correct the gpio pins. Signed-off-by: Roja Rani Yarubandi Signed-off-by: Rajesh Patil Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1632399378-12229-6-git-send-email-rajpat@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 ++++++++----------- arch/arm64/boot/dts/qcom/sc7280.dtsi | 30 +++++++++++++++++++++++++----- 2 files changed, 33 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 52974796d69e..c93e21819021 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -279,6 +279,7 @@ }; &uart5 { + compatible = "qcom,geni-debug-uart"; status = "okay"; }; @@ -347,18 +348,14 @@ bias-pull-up; }; -&qup_uart5_default { - tx { - pins = "gpio46"; - drive-strength = <2>; - bias-disable; - }; +&qup_uart5_tx { + drive-strength = <2>; + bias-disable; +}; - rx { - pins = "gpio47"; - drive-strength = <2>; - bias-pull-up; - }; +&qup_uart5_rx { + drive-strength = <2>; + bias-pull-up; }; &sdc1_on { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ec6faa5bf5fc..1cb20bd7fbe6 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -900,13 +900,18 @@ }; uart5: serial@994000 { - compatible = "qcom,geni-debug-uart"; + compatible = "qcom,geni-uart"; reg = <0 0x00994000 0 0x4000>; clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; clock-names = "se"; pinctrl-names = "default"; - pinctrl-0 = <&qup_uart5_default>; + pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>; interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; + interconnect-names = "qup-core", "qup-config"; status = "disabled"; }; @@ -2405,9 +2410,24 @@ function = "qup04"; }; - qup_uart5_default: qup-uart5-default { - pins = "gpio46", "gpio47"; - function = "qup13"; + qup_uart5_cts: qup-uart5-cts { + pins = "gpio20"; + function = "qup05"; + }; + + qup_uart5_rts: qup-uart5-rts { + pins = "gpio21"; + function = "qup05"; + }; + + qup_uart5_tx: qup-uart5-tx { + pins = "gpio22"; + function = "qup05"; + }; + + qup_uart5_rx: qup-uart5-rx { + pins = "gpio23"; + function = "qup05"; }; qup_uart6_cts: qup-uart6-cts { -- cgit From e3bc6fec5aaa67b8147a422d8d88a36d46827f0f Mon Sep 17 00:00:00 2001 From: Rajesh Patil Date: Thu, 23 Sep 2021 17:46:16 +0530 Subject: arm64: dts: qcom: sc7280: Configure uart7 to support bluetooth on sc7280-idp Add bluetooth uart pin configuration for sc7280-idp. Signed-off-by: Rajesh Patil Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1632399378-12229-7-git-send-email-rajpat@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 85 ++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index c93e21819021..c41747344c6d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -322,6 +322,16 @@ vdda18-supply = <&vreg_l1c_1p8>; }; +&uart7 { + status = "okay"; + + /delete-property/interrupts; + interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 31 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default", "sleep"; + pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>; +}; + /* PINCTRL - additions to nodes defined in sc7280.dtsi */ &pm7325_gpios { @@ -358,6 +368,81 @@ bias-pull-up; }; +&qup_uart7_cts { + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; +}; + +&qup_uart7_rts { + /* We'll drive RTS, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_tx { + /* We'll drive TX, so no pull */ + drive-strength = <2>; + bias-disable; +}; + +&qup_uart7_rx { + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + bias-pull-up; +}; + +&tlmm { + qup_uart7_sleep_cts: qup-uart7-sleep-cts { + pins = "gpio28"; + function = "gpio"; + /* + * Configure a pull-down on CTS to match the pull of + * the Bluetooth module. + */ + bias-pull-down; + }; + + qup_uart7_sleep_rts: qup-uart7-sleep-rts { + pins = "gpio29"; + function = "gpio"; + /* + * Configure pull-down on RTS. As RTS is active low + * signal, pull it low to indicate the BT SoC that it + * can wakeup the system anytime from suspend state by + * pulling RX low (by sending wakeup bytes). + */ + bias-pull-down; + }; + + qup_uart7_sleep_tx: qup-uart7-sleep-tx { + pins = "gpio30"; + function = "gpio"; + /* + * Configure pull-up on TX when it isn't actively driven + * to prevent BT SoC from receiving garbage during sleep. + */ + bias-pull-up; + }; + + qup_uart7_sleep_rx: qup-uart7-sleep-rx { + pins = "gpio31"; + function = "gpio"; + /* + * Configure a pull-up on RX. This is needed to avoid + * garbage data when the TX pin of the Bluetooth module + * is floating which may cause spurious wakeups. + */ + bias-pull-up; + }; +}; + &sdc1_on { clk { bias-disable; -- cgit From 4e8e7648ae645d1113649a7b9a781fdb4b2701f5 Mon Sep 17 00:00:00 2001 From: Roja Rani Yarubandi Date: Thu, 23 Sep 2021 17:46:17 +0530 Subject: arm64: dts: qcom: sc7280: Add QUPv3 wrapper_1 nodes Add QUPv3 wrapper_1 DT nodes for SC7280 SoC. Signed-off-by: Roja Rani Yarubandi Signed-off-by: Rajesh Patil Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1632399378-12229-8-git-send-email-rajpat@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 + arch/arm64/boot/dts/qcom/sc7280.dtsi | 749 +++++++++++++++++++++++++++++++ 2 files changed, 753 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index c41747344c6d..def22ff78906 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -250,6 +250,10 @@ status = "okay"; }; +&qupv3_id_1 { + status = "okay"; +}; + &sdhc_1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 1cb20bd7fbe6..bd0876924585 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1020,6 +1020,435 @@ }; }; + qupv3_id_1: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x2000>; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", "s-ahb"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + iommus = <&apps_smmu 0x43 0x0>; + status = "disabled"; + + i2c8: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi8: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart8: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a80000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c9: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c9_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi9: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart9: serial@a84000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a84000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c10: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi10: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart10: serial@a88000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a88000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c11: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c11_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi11: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart11: serial@a8c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a8c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c12: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c12_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi12: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart12: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a90000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c13: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c13_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi13: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart13: serial@a94000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a94000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c14: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c14_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi14: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a98000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart14: serial@a98000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a98000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + i2c15: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a9c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c15_data_clk>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, + <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "qup-core", "qup-config", + "qup-memory"; + status = "disabled"; + }; + + spi15: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a9c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + + uart15: serial@a9c000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00a9c000 0 0x4000>; + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + pinctrl-names = "default"; + pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; + interrupts = ; + power-domains = <&rpmhpd SC7280_CX>; + operating-points-v2 = <&qup_opp_table>; + interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; + interconnect-names = "qup-core", "qup-config"; + status = "disabled"; + }; + }; + cnoc2: interconnect@1500000 { reg = <0 0x01500000 0 0x1000>; compatible = "qcom,sc7280-cnoc2"; @@ -2190,6 +2619,46 @@ function = "qup07"; }; + qup_i2c8_data_clk: qup-i2c8-data-clk { + pins = "gpio32", "gpio33"; + function = "qup10"; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk { + pins = "gpio36", "gpio37"; + function = "qup11"; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk { + pins = "gpio40", "gpio41"; + function = "qup12"; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk { + pins = "gpio44", "gpio45"; + function = "qup13"; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk { + pins = "gpio48", "gpio49"; + function = "qup14"; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk { + pins = "gpio52", "gpio53"; + function = "qup15"; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk { + pins = "gpio56", "gpio57"; + function = "qup16"; + }; + + qup_i2c15_data_clk: qup-i2c15-data-clk { + pins = "gpio60", "gpio61"; + function = "qup17"; + }; + qup_spi0_data_clk: qup-spi0-data-clk { pins = "gpio0", "gpio1", "gpio2"; function = "qup00"; @@ -2310,6 +2779,126 @@ function = "gpio"; }; + qup_spi8_data_clk: qup-spi8-data-clk { + pins = "gpio32", "gpio33", "gpio34"; + function = "qup10"; + }; + + qup_spi8_cs: qup-spi8-cs { + pins = "gpio35"; + function = "qup10"; + }; + + qup_spi8_cs_gpio: qup-spi8-cs-gpio { + pins = "gpio35"; + function = "gpio"; + }; + + qup_spi9_data_clk: qup-spi9-data-clk { + pins = "gpio36", "gpio37", "gpio38"; + function = "qup11"; + }; + + qup_spi9_cs: qup-spi9-cs { + pins = "gpio39"; + function = "qup11"; + }; + + qup_spi9_cs_gpio: qup-spi9-cs-gpio { + pins = "gpio39"; + function = "gpio"; + }; + + qup_spi10_data_clk: qup-spi10-data-clk { + pins = "gpio40", "gpio41", "gpio42"; + function = "qup12"; + }; + + qup_spi10_cs: qup-spi10-cs { + pins = "gpio43"; + function = "qup12"; + }; + + qup_spi10_cs_gpio: qup-spi10-cs-gpio { + pins = "gpio43"; + function = "gpio"; + }; + + qup_spi11_data_clk: qup-spi11-data-clk { + pins = "gpio44", "gpio45", "gpio46"; + function = "qup13"; + }; + + qup_spi11_cs: qup-spi11-cs { + pins = "gpio47"; + function = "qup13"; + }; + + qup_spi11_cs_gpio: qup-spi11-cs-gpio { + pins = "gpio47"; + function = "gpio"; + }; + + qup_spi12_data_clk: qup-spi12-data-clk { + pins = "gpio48", "gpio49", "gpio50"; + function = "qup14"; + }; + + qup_spi12_cs: qup-spi12-cs { + pins = "gpio51"; + function = "qup14"; + }; + + qup_spi12_cs_gpio: qup-spi12-cs-gpio { + pins = "gpio51"; + function = "gpio"; + }; + + qup_spi13_data_clk: qup-spi13-data-clk { + pins = "gpio52", "gpio53", "gpio54"; + function = "qup15"; + }; + + qup_spi13_cs: qup-spi13-cs { + pins = "gpio55"; + function = "qup15"; + }; + + qup_spi13_cs_gpio: qup-spi13-cs-gpio { + pins = "gpio55"; + function = "gpio"; + }; + + qup_spi14_data_clk: qup-spi14-data-clk { + pins = "gpio56", "gpio57", "gpio58"; + function = "qup16"; + }; + + qup_spi14_cs: qup-spi14-cs { + pins = "gpio59"; + function = "qup16"; + }; + + qup_spi14_cs_gpio: qup-spi14-cs-gpio { + pins = "gpio59"; + function = "gpio"; + }; + + qup_spi15_data_clk: qup-spi15-data-clk { + pins = "gpio60", "gpio61", "gpio62"; + function = "qup17"; + }; + + qup_spi15_cs: qup-spi15-cs { + pins = "gpio63"; + function = "qup17"; + }; + + qup_spi15_cs_gpio: qup-spi15-cs-gpio { + pins = "gpio63"; + function = "gpio"; + }; + qup_uart0_cts: qup-uart0-cts { pins = "gpio0"; function = "qup00"; @@ -2546,6 +3135,166 @@ bias-bus-hold; }; }; + + qup_uart8_cts: qup-uart8-cts { + pins = "gpio32"; + function = "qup10"; + }; + + qup_uart8_rts: qup-uart8-rts { + pins = "gpio33"; + function = "qup10"; + }; + + qup_uart8_tx: qup-uart8-tx { + pins = "gpio34"; + function = "qup10"; + }; + + qup_uart8_rx: qup-uart8-rx { + pins = "gpio35"; + function = "qup10"; + }; + + qup_uart9_cts: qup-uart9-cts { + pins = "gpio36"; + function = "qup11"; + }; + + qup_uart9_rts: qup-uart9-rts { + pins = "gpio37"; + function = "qup11"; + }; + + qup_uart9_tx: qup-uart9-tx { + pins = "gpio38"; + function = "qup11"; + }; + + qup_uart9_rx: qup-uart9-rx { + pins = "gpio39"; + function = "qup11"; + }; + + qup_uart10_cts: qup-uart10-cts { + pins = "gpio40"; + function = "qup12"; + }; + + qup_uart10_rts: qup-uart10-rts { + pins = "gpio41"; + function = "qup12"; + }; + + qup_uart10_tx: qup-uart10-tx { + pins = "gpio42"; + function = "qup12"; + }; + + qup_uart10_rx: qup-uart10-rx { + pins = "gpio43"; + function = "qup12"; + }; + + qup_uart11_cts: qup-uart11-cts { + pins = "gpio44"; + function = "qup13"; + }; + + qup_uart11_rts: qup-uart11-rts { + pins = "gpio45"; + function = "qup13"; + }; + + qup_uart11_tx: qup-uart11-tx { + pins = "gpio46"; + function = "qup13"; + }; + + qup_uart11_rx: qup-uart11-rx { + pins = "gpio47"; + function = "qup13"; + }; + + qup_uart12_cts: qup-uart12-cts { + pins = "gpio48"; + function = "qup14"; + }; + + qup_uart12_rts: qup-uart12-rts { + pins = "gpio49"; + function = "qup14"; + }; + + qup_uart12_tx: qup-uart12-tx { + pins = "gpio50"; + function = "qup14"; + }; + + qup_uart12_rx: qup-uart12-rx { + pins = "gpio51"; + function = "qup14"; + }; + + qup_uart13_cts: qup-uart13-cts { + pins = "gpio52"; + function = "qup15"; + }; + + qup_uart13_rts: qup-uart13-rts { + pins = "gpio53"; + function = "qup15"; + }; + + qup_uart13_tx: qup-uart13-tx { + pins = "gpio54"; + function = "qup15"; + }; + + qup_uart13_rx: qup-uart13-rx { + pins = "gpio55"; + function = "qup15"; + }; + + qup_uart14_cts: qup-uart14-cts { + pins = "gpio56"; + function = "qup16"; + }; + + qup_uart14_rts: qup-uart14-rts { + pins = "gpio57"; + function = "qup16"; + }; + + qup_uart14_tx: qup-uart14-tx { + pins = "gpio58"; + function = "qup16"; + }; + + qup_uart14_rx: qup-uart14-rx { + pins = "gpio59"; + function = "qup16"; + }; + + qup_uart15_cts: qup-uart15-cts { + pins = "gpio60"; + function = "qup17"; + }; + + qup_uart15_rts: qup-uart15-rts { + pins = "gpio61"; + function = "qup17"; + }; + + qup_uart15_tx: qup-uart15-tx { + pins = "gpio62"; + function = "qup17"; + }; + + qup_uart15_rx: qup-uart15-rx { + pins = "gpio63"; + function = "qup17"; + }; }; apps_smmu: iommu@15000000 { -- cgit From 5f65408d9bfcc418353c8cd4dd17f60ba60d61a0 Mon Sep 17 00:00:00 2001 From: Rajesh Patil Date: Thu, 23 Sep 2021 17:46:18 +0530 Subject: arm64: dts: qcom: sc7280: Add aliases for I2C and SPI Add aliases for i2c and spi for sc7280 soc. Signed-off-by: Rajesh Patil Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1632399378-12229-9-git-send-email-rajpat@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bd0876924585..d89515f1f47f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -29,8 +29,40 @@ chosen { }; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + i2c9 = &i2c9; + i2c10 = &i2c10; + i2c11 = &i2c11; + i2c12 = &i2c12; + i2c13 = &i2c13; + i2c14 = &i2c14; + i2c15 = &i2c15; mmc1 = &sdhc_1; mmc2 = &sdhc_2; + spi0 = &spi0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &spi5; + spi6 = &spi6; + spi7 = &spi7; + spi8 = &spi8; + spi9 = &spi9; + spi10 = &spi10; + spi11 = &spi11; + spi12 = &spi12; + spi13 = &spi13; + spi14 = &spi14; + spi15 = &spi15; }; clocks { -- cgit From 36730a8f5f4561d4c3682dd3f310a2dbe6cf23f8 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Tue, 24 Aug 2021 10:19:18 +0800 Subject: arm64: dts: qcom: pm660: Add reboot mode support It turns out that the pm660 PON is a GEN2 device. Update the compatible to "qcom,pm8998-pon" and add reboot mode support, so that devices can be rebooted into bootloader and recovery mode. Tested on Xiaomi Redmi Note 7 phone. While at it, drop the unnecessary newline between 'compatible' and 'reg' property. Signed-off-by: Shawn Guo Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210824021918.17271-1-shawn.guo@linaro.org --- arch/arm64/boot/dts/qcom/pm660.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm660.dtsi b/arch/arm64/boot/dts/qcom/pm660.dtsi index e847d7209afc..d0ef8a1675e2 100644 --- a/arch/arm64/boot/dts/qcom/pm660.dtsi +++ b/arch/arm64/boot/dts/qcom/pm660.dtsi @@ -49,9 +49,10 @@ }; pon: pon@800 { - compatible = "qcom,pm8916-pon"; - + compatible = "qcom,pm8998-pon"; reg = <0x800>; + mode-bootloader = <0x2>; + mode-recovery = <0x1>; pwrkey { compatible = "qcom,pm8941-pwrkey"; -- cgit From 390883af89d2ed653c3f7eefc06368241d422a38 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:37:27 +0200 Subject: arm64: dts: qcom: msm8998: Introduce support for Sony Yoshino platform This commit introduces support for the Sony Yoshino platform, using the MSM8998 SoC, including: - Sony Xperia XZ1 (codename Poplar), - Sony Xperia XZ1 Compact (codename Lilac), - Sony Xperia XZ Premium (codename Maple). All of the three aforementioned smartphones are sharing a 99% equal board configuration, with very small differences between each other, which is the reason for the introduction of a common msm8998-sony-xperia-yoshino DT. This base configuration includes regulators and project-wide pin configurations and it's made to boot to a serial console. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Marijn Suijten Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123733.367248-1-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/Makefile | 3 + .../dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts | 19 + .../dts/qcom/msm8998-sony-xperia-yoshino-maple.dts | 43 ++ .../qcom/msm8998-sony-xperia-yoshino-poplar.dts | 24 ++ .../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 475 +++++++++++++++++++++ 5 files changed, 564 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts create mode 100644 arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 1b7130de1b61..2a8fd0dbf274 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -41,6 +41,9 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-cheeseburger.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-oneplus-dumpling.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-lilac.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-maple.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8998-sony-xperia-yoshino-poplar.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts new file mode 100644 index 000000000000..550de79e0151 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + */ + +/dts-v1/; + +#include "msm8998-sony-xperia-yoshino.dtsi" + +/ { + model = "Sony Xperia XZ1 Compact"; + compatible = "sony,xperia-lilac", "qcom,msm8998"; +}; + +&vreg_l22a_2p85 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts new file mode 100644 index 000000000000..35a6cdb55aec --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + */ + +/dts-v1/; + +#include "msm8998-sony-xperia-yoshino.dtsi" + +/ { + model = "Sony Xperia XZ Premium"; + compatible = "sony,xperia-maple", "qcom,msm8998"; + + disp_dvdd_vreg: disp-dvdd-vreg { + compatible = "regulator-fixed"; + regulator-name = "disp_dvdd_en"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + startup-delay-us = <0>; + enable-active-high; + gpio = <&pmi8998_gpio 10 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&disp_dvdd_en>; + }; +}; + +&pmi8998_gpio { + disp_dvdd_en: disp-dvdd-en-active { + pins = "gpio10"; + function = "normal"; + bias-disable; + drive-push-pull; + output-high; + power-source = <0>; + qcom,drive-strength = <1>; + }; +}; + +&vreg_l22a_2p85 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts new file mode 100644 index 000000000000..6255004b9a09 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + */ + +/dts-v1/; + +#include "msm8998-sony-xperia-yoshino.dtsi" + +/ { + model = "Sony Xperia XZ1"; + compatible = "sony,xperia-poplar", "qcom,msm8998"; +}; + +&vreg_l18a_2p85 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; +}; + +&vreg_l22a_2p85 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; +}; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi new file mode 100644 index 000000000000..98d23f8b93ac --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -0,0 +1,475 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + * Copyright (c) 2021, Konrad Dybcio + */ + +#include "msm8998.dtsi" +#include "pm8005.dtsi" +#include "pm8998.dtsi" +#include "pmi8998.dtsi" +#include +#include +#include +#include +#include + +/ { + /* required for bootloader to select correct board */ + qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */ + qcom,board-id = <8 0>; + + board_vbat: vbat-regulator { + compatible = "regulator-fixed"; + regulator-name = "VBAT"; + + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <4000000>; + regulator-always-on; + regulator-boot-on; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + regulator-name = "vph_pwr"; + regulator-always-on; + regulator-boot-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + label = "Side buttons"; + pinctrl-names = "default"; + pinctrl-0 = <&vol_down_pin_a>, <&cam_focus_pin_a>, + <&cam_snapshot_pin_a>; + vol-down { + label = "Volume Down"; + gpios = <&pm8998_gpio 5 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera-snapshot { + label = "Camera Snapshot"; + gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <15>; + }; + + camera-focus { + label = "Camera Focus"; + gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <15>; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + input-name = "hall-sensors"; + label = "Hall sensors"; + pinctrl-names = "default"; + pinctrl-0 = <&hall_sensor0_default>; + + hall-sensor0 { + label = "Cover Hall Sensor"; + gpios = <&tlmm 124 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <30>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@85800000 { + reg = <0x0 0x85800000 0x0 0x3700000>; + no-map; + }; + + cont_splash_mem: memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x2400000>; + no-map; + }; + + zap_shader_region: memory@f6400000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf6400000 0x0 0x2000>; + no-map; + }; + + adsp_region: memory@fe000000 { + reg = <0x0 0xfe000000 0x0 0x800000>; + no-map; + }; + + qseecom_region: memory@fe800000 { + reg = <0x0 0xfe800000 0x0 0x1400000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + record-size = <0x10000>; + console-size = <0x60000>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + ecc-size = <16>; + }; + }; +}; + +&blsp2_uart1 { + status = "okay"; +}; + +&mmcc { + status = "ok"; +}; + +&mmss_smmu { + status = "ok"; +}; + +&pm8005_lsid1 { + pm8005-regulators { + compatible = "qcom,pm8005-regulators"; + + vdd_s1-supply = <&vph_pwr>; + + /* VDD_GFX supply */ + pm8005_s1: s1 { + regulator-min-microvolt = <524000>; + regulator-max-microvolt = <1088000>; + regulator-enable-ramp-delay = <500>; + regulator-always-on; + }; + }; +}; + +&pm8998_gpio { + vol_down_pin_a: vol-down-active { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-up; + input-enable; + qcom,drive-strength = ; + }; + + cam_focus_pin_a: cam-focus-btn-active { + pins = "gpio7"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-up; + input-enable; + qcom,drive-strength = ; + }; + + cam_snapshot_pin_a: cam-snapshot-btn-active { + pins = "gpio8"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-pull-up; + input-enable; + qcom,drive-strength = ; + }; +}; + +&pm8998_pon { + resin { + compatible = "qcom,pm8941-resin"; + interrupts = ; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; +}; + +&qusb2phy { + status = "okay"; + + vdda-pll-supply = <&vreg_l12a_1p8>; + vdda-phy-dpdm-supply = <&vreg_l24a_3p075>; +}; + +&rpm_requests { + pm8998-regulators { + compatible = "qcom,rpm-pm8998-regulators"; + + vdd_s1-supply = <&vph_pwr>; + vdd_s2-supply = <&vph_pwr>; + vdd_s3-supply = <&vph_pwr>; + vdd_s4-supply = <&vph_pwr>; + vdd_s5-supply = <&vph_pwr>; + vdd_s6-supply = <&vph_pwr>; + vdd_s7-supply = <&vph_pwr>; + vdd_s8-supply = <&vph_pwr>; + vdd_s9-supply = <&vph_pwr>; + vdd_s10-supply = <&vph_pwr>; + vdd_s11-supply = <&vph_pwr>; + vdd_s12-supply = <&vph_pwr>; + vdd_s13-supply = <&vph_pwr>; + vdd_l1_l27-supply = <&vreg_s7a_1p025>; + vdd_l2_l8_l17-supply = <&vreg_s3a_1p35>; + vdd_l3_l11-supply = <&vreg_s7a_1p025>; + vdd_l4_l5-supply = <&vreg_s7a_1p025>; + vdd_l6-supply = <&vreg_s5a_2p04>; + vdd_l7_l12_l14_l15-supply = <&vreg_s5a_2p04>; + vdd_l9-supply = <&vreg_bob>; + vdd_l10_l23_l25-supply = <&vreg_bob>; + vdd_l13_l19_l21-supply = <&vreg_bob>; + vdd_l16_l28-supply = <&vreg_bob>; + vdd_l18_l22-supply = <&vreg_bob>; + vdd_l20_l24-supply = <&vreg_bob>; + vdd_l26-supply = <&vreg_s3a_1p35>; + vdd_lvs1_lvs2-supply = <&vreg_s4a_1p8>; + + vreg_s3a_1p35: s3 { + regulator-min-microvolt = <1352000>; + regulator-max-microvolt = <1352000>; + }; + vreg_s4a_1p8: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-system-load = <100000>; + regulator-allow-set-load; + }; + vreg_s5a_2p04: s5 { + regulator-min-microvolt = <1904000>; + regulator-max-microvolt = <2032000>; + }; + vreg_s7a_1p025: s7 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1028000>; + }; + vreg_l1a_0p875: l1 { + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + regulator-system-load = <73400>; + regulator-allow-set-load; + }; + vreg_l2a_1p2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-system-load = <12560>; + regulator-allow-set-load; + }; + vreg_l3a_1p0: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + vreg_l5a_0p8: l5 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + }; + vreg_l6a_1p8: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l7a_1p8: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l8a_1p2: l8 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + vreg_l9a_1p8: l9 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + vreg_l10a_1p8: l10 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + }; + vreg_l11a_1p0: l11 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + }; + vreg_l12a_1p8: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l13a_2p95: l13 { + regulator-min-microvolt = <1808000>; + regulator-max-microvolt = <2960000>; + regulator-allow-set-load; + }; + vreg_l14a_1p85: l14 { + regulator-min-microvolt = <1848000>; + regulator-max-microvolt = <1856000>; + regulator-system-load = <32000>; + regulator-allow-set-load; + }; + vreg_l15a_1p8: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + vreg_l16a_2p7: l16 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <2704000>; + }; + vreg_l17a_1p3: l17 { + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1304000>; + }; + vreg_l18a_2p85: l18 {}; + vreg_l19a_2p7: l19 { + regulator-min-microvolt = <2696000>; + regulator-max-microvolt = <2704000>; + }; + vreg_l20a_2p95: l20 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-system-load = <10000>; + regulator-allow-set-load; + }; + vreg_l21a_2p95: l21 { + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <2960000>; + regulator-system-load = <800000>; + regulator-allow-set-load; + }; + vreg_l22a_2p85: l22 { }; + vreg_l23a_3p3: l23 { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3312000>; + }; + vreg_l24a_3p075: l24 { + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + }; + vreg_l25a_3p3: l25 { + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3312000>; + }; + vreg_l26a_1p2: l26 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-allow-set-load; + }; + vreg_l28_3p0: l28 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + vreg_lvs1a_1p8: lvs1 { }; + vreg_lvs2a_1p8: lvs2 { }; + }; + + pmi8998-regulators { + compatible = "qcom,rpm-pmi8998-regulators"; + + vdd_bob-supply = <&vph_pwr>; + + vreg_bob: bob { + regulator-min-microvolt = <3312000>; + regulator-max-microvolt = <3600000>; + }; + }; +}; + +&sdhc2 { + status = "okay"; + cd-gpios = <&tlmm 95 GPIO_ACTIVE_HIGH>; + + vmmc-supply = <&vreg_l21a_2p95>; + vqmmc-supply = <&vreg_l13a_2p95>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &sdc2_cd_on>; + pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &sdc2_cd_off>; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>, <81 4>; + + mdp_vsync_n: mdp-vsync-n { + pins = "gpio10"; + function = "mdp_vsync_a"; + drive-strength = <2>; + bias-pull-down; + }; + + nfc_ven: nfc-ven { + pins = "gpio12"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-low; + }; + + msm_mclk0_default: msm-mclk0-active { + pins = "gpio13"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + msm_mclk1_default: msm-mclk1-active { + pins = "gpio14"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + + cci0_default: cci0-default { + pins = "gpio18", "gpio19"; + function = "cci_i2c"; + bias-disable; + drive-strength = <2>; + }; + + cci1_default: cci1-default { + pins = "gpio19", "gpio20"; + function = "cci_i2c"; + bias-disable; + drive-strength = <2>; + }; + + hall_sensor0_default: acc-cover-open { + pins = "gpio124"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + input-enable; + }; +}; + +/* + * WARNING: + * Disable UFS until card quirks are in to avoid unrecoverable hard-brick + * that would happen as soon as the UFS card gets probed as, without the + * required quirks, the bootloader will be erased right after card probe. + */ +&ufshc { + status = "disabled"; +}; + +&ufsphy { + status = "disabled"; +}; + +&usb3 { + status = "okay"; +}; + +&usb3_dwc3 { + /* Force to peripheral until we have Type-C hooked up */ + dr_mode = "peripheral"; +}; + +&usb3phy { + status = "okay"; + + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l2a_1p2>; +}; -- cgit From ebe0932e4fe5a5a0eb197f1de50442a2bf2d7b08 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:37:28 +0200 Subject: arm64: dts: qcom: msm8998-xperia: Add RMI4 touchscreen support All of the devices in the Sony Yoshino platform are using a Synaptics RMI4-compatible touch IC with identical pins and supplies: enable the I2C-5 bus and add the rmi4-i2c node along with the required pin configurations. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123733.367248-2-angelogioacchino.delregno@somainline.org --- .../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 98d23f8b93ac..8bbff6e80b7f 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -30,6 +30,15 @@ regulator-boot-on; }; + touch_vddio_vreg: touch-vddio-vreg { + compatible = "regulator-fixed"; + regulator-name = "touch_vddio_vreg"; + startup-delay-us = <10000>; + gpio = <&tlmm 133 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_vddio_en>; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -130,6 +139,42 @@ }; }; +&blsp1_i2c5 { + status = "okay"; + clock-frequency = <355000>; + + touchscreen@2c { + compatible = "syna,rmi4-i2c"; + reg = <0x2c>; + #address-cells = <1>; + #size-cells = <0>; + interrupts-extended = <&tlmm 125 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_n>; + + vdd-supply = <&vreg_l28_3p0>; + vio-supply = <&touch_vddio_vreg>; + + syna,reset-delay-ms = <220>; + syna,startup-delay-ms = <1000>; + + rmi4-f01@1 { + reg = <0x01>; + syna,nosleep-mode = <1>; + }; + + rmi4-f11@11 { + reg = <0x11>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp1_i2c5_sleep { + bias-disable; +}; + &blsp2_uart1 { status = "okay"; }; @@ -442,6 +487,21 @@ drive-strength = <2>; input-enable; }; + + ts_int_n: ts-int-n { + pins = "gpio125"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_vddio_en: ts-vddio-en-default { + pins = "gpio133"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + output-low; + }; }; /* -- cgit From 58ba4efabc150f85ba3c80a31c37e03adebd5135 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:37:29 +0200 Subject: arm64: dts: qcom: msm8998-xperia: Add support for wcn3990 Bluetooth This platform uses the WCN3990 Bluetooth chip, reachable on UART-3. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123733.367248-3-angelogioacchino.delregno@somainline.org --- .../arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 8bbff6e80b7f..cfd61c399b02 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -175,6 +175,22 @@ bias-disable; }; +&blsp1_uart3 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn3990-bt"; + + vddio-supply = <&vreg_s4a_1p8>; + vddxo-supply = <&vreg_l7a_1p8>; + vddrf-supply = <&vreg_l17a_1p3>; + vddch0-supply = <&vreg_l25a_3p3>; + max-speed = <3200000>; + + clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; + }; +}; + &blsp2_uart1 { status = "okay"; }; -- cgit From 4de9700d0332f21d12ffec7ba67733ea9a6581a5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:37:30 +0200 Subject: arm64: dts: qcom: msm8998-xperia: Add support for gpio vibrator All smartphones in the Sony Yoshino platforms have got a simple vibrator hooked to a GPIO: add support for that and add its own pin configuration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123733.367248-4-angelogioacchino.delregno@somainline.org --- .../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index cfd61c399b02..798f2d8a8237 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -137,6 +137,13 @@ ecc-size = <16>; }; }; + + vibrator { + compatible = "gpio-vibrator"; + enable-gpios = <&pmi8998_gpio 5 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&vib_default>; + }; }; &blsp1_i2c5 { @@ -245,6 +252,18 @@ }; }; +&pmi8998_gpio { + vib_default: vib-en { + pins = "gpio5"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-disable; + drive-push-pull; + output-low; + qcom,drive-strength = ; + power-source = <0>; + }; +}; + &pm8998_pon { resin { compatible = "qcom,pm8941-resin"; -- cgit From 67372ee2c0bca8bfb1e16e961e9f3969d434f978 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:37:31 +0200 Subject: arm64: dts: qcom: msm8998-xperia: Configure display boost regulators Add configuration for the LAB and IBB regulators (in boost mode): this platform has smartphones with three different display sizes, hence different displays requiring different voltage. The common configuration parameters have been put in the common device-tree, while specific voltage specs and soft-start-us are variant specific, so they have been put into the machine specific dts file. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123733.367248-5-angelogioacchino.delregno@somainline.org --- .../dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts | 11 ++++++++++ .../dts/qcom/msm8998-sony-xperia-yoshino-maple.dts | 11 ++++++++++ .../qcom/msm8998-sony-xperia-yoshino-poplar.dts | 11 ++++++++++ .../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 25 ++++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts index 550de79e0151..0de919357de4 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-lilac.dts @@ -13,6 +13,17 @@ compatible = "sony,xperia-lilac", "qcom,msm8998"; }; +&ibb { + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; +}; + +&lab { + regulator-min-microvolt = <5500000>; + regulator-max-microvolt = <5500000>; + qcom,soft-start-us = <800>; +}; + &vreg_l22a_2p85 { regulator-min-microvolt = <2800000>; regulator-max-microvolt = <2800000>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts index 35a6cdb55aec..87115d648cef 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-maple.dts @@ -25,6 +25,17 @@ }; }; +&ibb { + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; +}; + +&lab { + regulator-min-microvolt = <5800000>; + regulator-max-microvolt = <5800000>; + qcom,soft-start-us = <200>; +}; + &pmi8998_gpio { disp_dvdd_en: disp-dvdd-en-active { pins = "gpio10"; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts index 6255004b9a09..9fa3583c951b 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino-poplar.dts @@ -13,6 +13,17 @@ compatible = "sony,xperia-poplar", "qcom,msm8998"; }; +&ibb { + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; +}; + +&lab { + regulator-min-microvolt = <5600000>; + regulator-max-microvolt = <5600000>; + qcom,soft-start-us = <800>; +}; + &vreg_l18a_2p85 { regulator-min-microvolt = <2850000>; regulator-max-microvolt = <2850000>; diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 798f2d8a8237..e2cccc8314be 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -202,6 +202,31 @@ status = "okay"; }; +&ibb { + regulator-min-microamp = <800000>; + regulator-max-microamp = <800000>; + regulator-enable-ramp-delay = <200>; + regulator-over-current-protection; + regulator-pull-down; + regulator-ramp-delay = <1>; + regulator-settling-time-up-us = <600>; + regulator-settling-time-down-us = <1000>; + regulator-soft-start; + qcom,discharge-resistor-kohms = <300>; +}; + +&lab { + regulator-min-microamp = <200000>; + regulator-max-microamp = <200000>; + regulator-enable-ramp-delay = <500>; + regulator-over-current-protection; + regulator-pull-down; + regulator-ramp-delay = <1>; + regulator-settling-time-up-us = <50000>; + regulator-settling-time-down-us = <3000>; + regulator-soft-start; +}; + &mmcc { status = "ok"; }; -- cgit From a5fde059398b5d985a3fcfea06f75cce2a88081f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:37:32 +0200 Subject: arm64: dts: qcom: msm8998-xperia: Add camera regulators All of the machines of the Sony Yoshino platform are equipped with two cameras, sharing the same regulators configuration. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123733.367248-6-angelogioacchino.delregno@somainline.org --- .../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index e2cccc8314be..2c609e2cfc4a 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -30,6 +30,38 @@ regulator-boot-on; }; + cam0_vdig_vreg: cam0-vdig { + compatible = "regulator-fixed"; + regulator-name = "cam0_vdig"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 21 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam0_vdig_default>; + }; + + cam1_vdig_vreg: cam1-vdig { + compatible = "regulator-fixed"; + regulator-name = "cam1_vdig"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&tlmm 25 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam1_vdig_default>; + vin-supply = <&vreg_s3a_1p35>; + }; + + cam_vio_vreg: cam-vio-vreg { + compatible = "regulator-fixed"; + regulator-name = "cam_vio_vreg"; + startup-delay-us = <0>; + enable-active-high; + gpio = <&pmi8998_gpio 1 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&cam_vio_default>; + vin-supply = <&vreg_lvs1a_1p8>; + }; + touch_vddio_vreg: touch-vddio-vreg { compatible = "regulator-fixed"; regulator-name = "touch_vddio_vreg"; @@ -278,6 +310,16 @@ }; &pmi8998_gpio { + cam_vio_default: cam-vio-active { + pins = "gpio1"; + function = PMIC_GPIO_FUNC_NORMAL; + bias-disable; + drive-push-pull; + output-low; + qcom,drive-strength = ; + power-source = <1>; + }; + vib_default: vib-en { pins = "gpio5"; function = PMIC_GPIO_FUNC_NORMAL; @@ -540,6 +582,20 @@ drive-strength = <2>; }; + cam0_vdig_default: cam0-vdig-default { + pins = "gpio21"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + cam1_vdig_default: cam1-vdig-default { + pins = "gpio25"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + hall_sensor0_default: acc-cover-open { pins = "gpio124"; function = "gpio"; -- cgit From 6cadaa14f290a0b7c2f3b2b7afd3192c5b49473f Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:37:33 +0200 Subject: arm64: dts: qcom: msm8998-xperia: Add audio clock and its pin All smartphones of this platform are equipped with a WCD9335 audio codec, getting its MCLK from PM8998 gpio13: add this clock to DT. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Marijn Suijten Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123733.367248-7-angelogioacchino.delregno@somainline.org --- .../boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi index 2c609e2cfc4a..91e391282181 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998-sony-xperia-yoshino.dtsi @@ -20,6 +20,19 @@ qcom,msm-id = <0x124 0x20000>, <0x124 0x20001>; /* 8998v2, v2.1 */ qcom,board-id = <8 0>; + clocks { + compatible = "simple-bus"; + + div1_mclk: divclk1 { + compatible = "gpio-gate-clock"; + pinctrl-0 = <&audio_mclk_pin>; + pinctrl-names = "default"; + clocks = <&rpmcc RPM_SMD_DIV_CLK1>; + #clock-cells = <0>; + enable-gpios = <&pm8998_gpio 13 GPIO_ACTIVE_HIGH>; + }; + }; + board_vbat: vbat-regulator { compatible = "regulator-fixed"; regulator-name = "VBAT"; @@ -307,6 +320,12 @@ input-enable; qcom,drive-strength = ; }; + + audio_mclk_pin: audio-mclk-pin-active { + pins = "gpio13"; + function = "func2"; + power-source = <0>; + }; }; &pmi8998_gpio { -- cgit From be4c096e6ba7728f4a1ead1de820d75436aedbd9 Mon Sep 17 00:00:00 2001 From: Douglas Anderson Date: Thu, 23 Sep 2021 08:14:04 -0700 Subject: arm64: dts: qcom: sc7180: Base homestar's power coefficients in reality The commit 82ea7d411d43 ("arm64: dts: qcom: sc7180: Base dynamic CPU power coefficients in reality") and the commit be0416a3f917 ("arm64: dts: qcom: Add sc7180-trogdor-homestar") passed each other in the tubes that make up the Internet. Despite the fact the patches didn't cause a merge conflict, they need to account for each other. Do that. Fixes: 82ea7d411d43 ("arm64: dts: qcom: sc7180: Base dynamic CPU power coefficients in reality") Fixes: be0416a3f917 ("arm64: dts: qcom: Add sc7180-trogdor-homestar") Signed-off-by: Douglas Anderson Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923081352.1.I2a2ee0ac428a63927324d65022929565aa7d8361@changeid --- arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi index cd3054226865..382f8c6f1576 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi @@ -51,7 +51,7 @@ ap_h1_spi: &spi0 {}; polling-delay = <0>; thermal-sensors = <&pm6150_adc_tm 1>; - sustainable-power = <814>; + sustainable-power = <965>; trips { skin_temp_alert0: trip-point0 { -- cgit From 135780456218e98172f3bca1e1af4ae6646d4bbe Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 16 Sep 2021 19:29:22 +0530 Subject: arm64: dts: qcom: sc7180: Use QMP property to control load state Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SC7180 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Reviewed-by: Matthias Kaehlcke Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631800770-371-6-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 495c15deacb7..acd2d1f45311 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include @@ -1922,14 +1921,15 @@ clock-names = "iface", "bus", "nav", "snoc_axi", "mnoc_axi", "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, - <&rpmhpd SC7180_CX>, + power-domains = <&rpmhpd SC7180_CX>, <&rpmhpd SC7180_MX>, <&rpmhpd SC7180_MSS>; - power-domain-names = "load_state", "cx", "mx", "mss"; + power-domain-names = "cx", "mx", "mss"; memory-region = <&mpss_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; @@ -3224,7 +3224,6 @@ mboxes = <&apss_shared 0>; #clock-cells = <0>; - #power-domain-cells = <1>; }; spmi_bus: spmi@c440000 { -- cgit From 6b3207dfebdf10474f1df143892c9d78644be643 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 16 Sep 2021 19:29:23 +0530 Subject: arm64: dts: qcom: sc7280: Use QMP property to control load state Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SC7280 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631800770-371-7-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index d89515f1f47f..844762cdcc32 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -2554,7 +2553,6 @@ IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; - #power-domain-cells = <1>; }; spmi_bus: spmi@c440000 { -- cgit From db8e45a81bdc5246f55c4000033bbdc886cde70f Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 16 Sep 2021 19:29:24 +0530 Subject: arm64: dts: qcom: sdm845: Use QMP property to control load state Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SDM845 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631800770-371-8-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 033614ab92d1..35736b372e53 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -763,6 +763,8 @@ memory-region = <&adsp_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; @@ -862,6 +864,8 @@ memory-region = <&cdsp_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "stop"; @@ -2979,6 +2983,8 @@ clock-names = "iface", "bus", "mem", "gpll0_mss", "snoc_axi", "mnoc_axi", "prng", "xo"; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; @@ -2988,11 +2994,10 @@ qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>; - power-domains = <&aoss_qmp 2>, - <&rpmhpd SDM845_CX>, + power-domains = <&rpmhpd SDM845_CX>, <&rpmhpd SDM845_MX>, <&rpmhpd SDM845_MSS>; - power-domain-names = "load_state", "cx", "mx", "mss"; + power-domain-names = "cx", "mx", "mss"; mba { memory-region = <&mba_region>; @@ -4607,7 +4612,6 @@ mboxes = <&apss_shared 0>; #clock-cells = <0>; - #power-domain-cells = <1>; cx_cdev: cx { #cooling-cells = <2>; -- cgit From d9d327f6a37f85a975cf9df9ecff60337586e7b0 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 16 Sep 2021 19:29:25 +0530 Subject: arm64: dts: qcom: sm8150: Use QMP property to control load state Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8150 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631800770-371-9-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index ef0232c2cf45..8a035693b7a3 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -6,7 +6,6 @@ #include #include -#include #include #include #include @@ -1729,13 +1728,14 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, - <&rpmhpd 3>, + power-domains = <&rpmhpd 3>, <&rpmhpd 2>; - power-domain-names = "load_state", "lcx", "lmx"; + power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&slpi_smp2p_out 0>; qcom,smem-state-names = "stop"; @@ -2319,13 +2319,14 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, - <&rpmhpd 7>, + power-domains = <&rpmhpd 7>, <&rpmhpd 0>; - power-domain-names = "load_state", "cx", "mss"; + power-domain-names = "cx", "mss"; memory-region = <&mpss_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; @@ -2945,12 +2946,12 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, - <&rpmhpd 7>; - power-domain-names = "load_state", "cx"; + power-domains = <&rpmhpd 7>; memory-region = <&cdsp_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&cdsp_smp2p_out 0>; qcom,smem-state-names = "stop"; @@ -3174,7 +3175,6 @@ mboxes = <&apss_shared 0>; #clock-cells = <0>; - #power-domain-cells = <1>; }; tsens0: thermal-sensor@c263000 { @@ -3321,12 +3321,12 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, - <&rpmhpd 7>; - power-domain-names = "load_state", "cx"; + power-domains = <&rpmhpd 7>; memory-region = <&adsp_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&adsp_smp2p_out 0>; qcom,smem-state-names = "stop"; -- cgit From b74ee2d71be84837648695465ce81dfb44420b7b Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 16 Sep 2021 19:29:26 +0530 Subject: arm64: dts: qcom: sm8250: Use QMP property to control load state Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8250 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631800770-371-10-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 8c15d9fed08f..2796b27f7c04 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include @@ -2088,13 +2087,14 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, - <&rpmhpd SM8250_LCX>, + power-domains = <&rpmhpd SM8250_LCX>, <&rpmhpd SM8250_LMX>; - power-domain-names = "load_state", "lcx", "lmx"; + power-domain-names = "lcx", "lmx"; memory-region = <&slpi_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_slpi_out 0>; qcom,smem-state-names = "stop"; @@ -2154,12 +2154,12 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, - <&rpmhpd SM8250_CX>; - power-domain-names = "load_state", "cx"; + power-domains = <&rpmhpd SM8250_CX>; memory-region = <&cdsp_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_cdsp_out 0>; qcom,smem-state-names = "stop"; @@ -2907,7 +2907,6 @@ IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; - #power-domain-cells = <1>; }; spmi_bus: spmi@c440000 { @@ -3824,13 +3823,14 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, - <&rpmhpd SM8250_LCX>, + power-domains = <&rpmhpd SM8250_LCX>, <&rpmhpd SM8250_LMX>; - power-domain-names = "load_state", "lcx", "lmx"; + power-domain-names = "lcx", "lmx"; memory-region = <&adsp_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; qcom,smem-state-names = "stop"; -- cgit From 6b7cb2d23791c541dff2f152d9c5c2f9da065289 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Thu, 16 Sep 2021 19:29:27 +0530 Subject: arm64: dts: qcom: sm8350: Use QMP property to control load state Use the Qualcomm Mailbox Protocol (QMP) property to control the load state resources on SM8350 SoCs and drop deprecated power-domains exposed by AOSS QMP node. Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631800770-371-11-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index e91cd8a5e535..6c83cd52a279 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -726,15 +725,16 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>, - <&rpmhpd 0>, + power-domains = <&rpmhpd 0>, <&rpmhpd 12>; - power-domain-names = "load_state", "cx", "mss"; + power-domain-names = "cx", "mss"; interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; memory-region = <&pil_modem_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_modem_out 0>; qcom,smem-state-names = "stop"; @@ -794,7 +794,6 @@ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; #clock-cells = <0>; - #power-domain-cells = <1>; }; spmi_bus: spmi@c440000 { @@ -1107,13 +1106,14 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_SLPI>, - <&rpmhpd 4>, + power-domains = <&rpmhpd 4>, <&rpmhpd 5>; - power-domain-names = "load_state", "lcx", "lmx"; + power-domain-names = "lcx", "lmx"; memory-region = <&pil_slpi_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_slpi_out 0>; qcom,smem-state-names = "stop"; @@ -1147,15 +1147,16 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_CDSP>, - <&rpmhpd 0>, + power-domains = <&rpmhpd 0>, <&rpmhpd 10>; - power-domain-names = "load_state", "cx", "mxc"; + power-domain-names = "cx", "mxc"; interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; memory-region = <&pil_cdsp_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_cdsp_out 0>; qcom,smem-state-names = "stop"; @@ -1381,13 +1382,14 @@ clocks = <&rpmhcc RPMH_CXO_CLK>; clock-names = "xo"; - power-domains = <&aoss_qmp AOSS_QMP_LS_LPASS>, - <&rpmhpd 4>, + power-domains = <&rpmhpd 4>, <&rpmhpd 5>; - power-domain-names = "load_state", "lcx", "lmx"; + power-domain-names = "lcx", "lmx"; memory-region = <&pil_adsp_mem>; + qcom,qmp = <&aoss_qmp>; + qcom,smem-states = <&smp2p_adsp_out 0>; qcom,smem-state-names = "stop"; -- cgit From 55d0feb3ab3de31320db41c92eaac6d73c644a6d Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:47 +0200 Subject: dt-bindings: arm: cpus: Add Kryo 560 CPUs Document Kryo 560 CPUs found in Qualcomm Snapdragon 690 (SM6350). Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-1-konrad.dybcio@somainline.org --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 9a2432a88074..897eec887e5a 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -171,6 +171,7 @@ properties: - qcom,kryo385 - qcom,kryo468 - qcom,kryo485 + - qcom,kryo560 - qcom,kryo685 - qcom,scorpion -- cgit From 5f82b9cda61e60a7f381a4aa427fa9eb472e581c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:48 +0200 Subject: arm64: dts: qcom: Add SM6350 device tree Add a base DT for SM6350 SoC Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-2-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 485 +++++++++++++++++++++++++++++++++++ 1 file changed, 485 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6350.dtsi diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi new file mode 100644 index 000000000000..d718ecf7d74e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -0,0 +1,485 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ + +#include +#include +#include +#include + +/ { + interrupt-parent = <&intc>; + #address-cells = <2>; + #size-cells = <2>; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <76800000>; + clock-output-names = "xo_board"; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo560"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + #cooling-cells = <2>; + L2_0: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + L3_0: l3-cache { + compatible = "cache"; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo560"; + reg = <0x0 0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_100>; + #cooling-cells = <2>; + L2_100: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo560"; + reg = <0x0 0x200>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_200>; + #cooling-cells = <2>; + L2_200: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo560"; + reg = <0x0 0x300>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_300>; + #cooling-cells = <2>; + L2_300: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo560"; + reg = <0x0 0x400>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_400>; + #cooling-cells = <2>; + L2_400: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo560"; + reg = <0x0 0x500>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_500>; + #cooling-cells = <2>; + L2_500: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo560"; + reg = <0x0 0x600>; + enable-method = "psci"; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <703>; + next-level-cache = <&L2_600>; + #cooling-cells = <2>; + L2_600: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo560"; + reg = <0x0 0x700>; + enable-method = "psci"; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <703>; + next-level-cache = <&L2_700>; + #cooling-cells = <2>; + L2_700: l2-cache { + compatible = "cache"; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm6350", "qcom,scm"; + #reset-cells = <1>; + }; + }; + + memory@80000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0x0 0x80000000 0x0 0x0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: memory@80000000 { + reg = <0 0x80000000 0 0x600000>; + no-map; + }; + + xbl_aop_mem: memory@80700000 { + reg = <0 0x80700000 0 0x160000>; + no-map; + }; + + cmd_db: memory@80860000 { + compatible = "qcom,cmd-db"; + reg = <0 0x80860000 0 0x20000>; + no-map; + }; + + sec_apps_mem: memory@808ff000 { + reg = <0 0x808ff000 0 0x1000>; + no-map; + }; + + smem_mem: memory@80900000 { + reg = <0 0x80900000 0 0x200000>; + no-map; + }; + + cdsp_sec_mem: memory@80b00000 { + reg = <0 0x80b00000 0 0x1e00000>; + no-map; + }; + + pil_camera_mem: memory@86000000 { + reg = <0 0x86000000 0 0x500000>; + no-map; + }; + + pil_npu_mem: memory@86500000 { + reg = <0 0x86500000 0 0x500000>; + no-map; + }; + + pil_video_mem: memory@86a00000 { + reg = <0 0x86a00000 0 0x500000>; + no-map; + }; + + pil_cdsp_mem: memory@86f00000 { + reg = <0 0x86f00000 0 0x1e00000>; + no-map; + }; + + pil_adsp_mem: memory@88d00000 { + reg = <0 0x88d00000 0 0x2800000>; + no-map; + }; + + wlan_fw_mem: memory@8b500000 { + reg = <0 0x8b500000 0 0x200000>; + no-map; + }; + + pil_ipa_fw_mem: memory@8b700000 { + reg = <0 0x8b700000 0 0x10000>; + no-map; + }; + + pil_ipa_gsi_mem: memory@8b710000 { + reg = <0 0x8b710000 0 0x5400>; + no-map; + }; + + pil_gpu_mem: memory@8b715400 { + reg = <0 0x8b715400 0 0x2000>; + no-map; + }; + + pil_modem_mem: memory@8b800000 { + reg = <0 0x8b800000 0 0xf800000>; + no-map; + }; + + cont_splash_memory: memory@a0000000 { + reg = <0 0xa0000000 0 0x2300000>; + no-map; + }; + + dfps_data_memory: memory@a2300000 { + reg = <0 0xa2300000 0 0x100000>; + no-map; + }; + + removed_region: memory@c0000000 { + reg = <0 0xc0000000 0 0x3900000>; + no-map; + }; + + debug_region: memory@ffb00000 { + reg = <0 0xffb00000 0 0xc0000>; + no-map; + }; + + last_log_region: memory@ffbc0000 { + reg = <0 0xffbc0000 0 0x40000>; + no-map; + }; + + ramoops: ramoops@ffc00000 { + compatible = "removed-dma-pool", "ramoops"; + reg = <0 0xffc00000 0 0x00100000>; + record-size = <0x1000>; + console-size = <0x40000>; + ftrace-size = <0x0>; + msg-size = <0x20000 0x20000>; + cc-size = <0x0>; + no-map; + }; + + cmdline_region: memory@ffd00000 { + reg = <0 0xffd00000 0 0x1000>; + no-map; + }; + }; + + smem { + compatible = "qcom,smem"; + memory-region = <&smem_mem>; + hwlocks = <&tcsr_mutex 3>; + }; + + soc: soc@0 { + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0 0 0 0x10 0>; + dma-ranges = <0 0 0 0 0x10 0>; + compatible = "simple-bus"; + + ipcc: mailbox@408000 { + compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; + reg = <0 0x00408000 0 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0x0 0x01f40000 0x0 0x40000>; + #hwlock-cells = <1>; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm6350-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; + qcom,pdc-ranges = <0 480 94>, <94 609 31>, + <125 63 1>, <126 655 12>, <138 139 15>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + + intc: interrupt-controller@17a00000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ + <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + watchdog@17c10000 { + compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt"; + reg = <0 0x17c10000 0 0x1000>; + clocks = <&sleep_clk>; + interrupts = ; + }; + + timer@17c20000 { + compatible = "arm,armv7-timer-mem"; + reg = <0x0 0x17c20000 0x0 0x1000>; + clock-frequency = <19200000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + frame@17c21000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0 0x17c21000 0x0 0x1000>, + <0x0 0x17c22000 0x0 0x1000>; + }; + + frame@17c23000 { + frame-number = <1>; + interrupts = ; + reg = <0x0 0x17c23000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c25000 { + frame-number = <2>; + interrupts = ; + reg = <0x0 0x17c25000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c27000 { + frame-number = <3>; + interrupts = ; + reg = <0x0 0x17c27000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c29000 { + frame-number = <4>; + interrupts = ; + reg = <0x0 0x17c29000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c2b000 { + frame-number = <5>; + interrupts = ; + reg = <0x0 0x17c2b000 0x0 0x1000>; + status = "disabled"; + }; + + frame@17c2d000 { + frame-number = <6>; + interrupts = ; + reg = <0x0 0x17c2d000 0x0 0x1000>; + status = "disabled"; + }; + }; + + apps_rsc: rsc@18200000 { + compatible = "qcom,rpmh-rsc"; + label = "apps_rsc"; + reg = <0x0 0x18200000 0x0 0x10000>, + <0x0 0x18210000 0x0 0x10000>, + <0x0 0x18220000 0x0 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , , + , ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + clock-frequency = <19200000>; + interrupts = , + , + , + ; + }; +}; -- cgit From ced2f0d75e132a611f6239846b853452c23e6176 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:49 +0200 Subject: arm64: dts: qcom: sm6350: Add LLCC node Add a node for LLCC with SM6350-specific compatible. Acked-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-3-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index d718ecf7d74e..5442c088cf37 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -372,6 +372,12 @@ #hwlock-cells = <1>; }; + system-cache-controller@9200000 { + compatible = "qcom,sm6350-llcc"; + reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; + reg-names = "llcc_base", "llcc_broadcast_base"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm6350-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; -- cgit From 985e02e7c0626a1e07c532bda5b6812f4ba5072c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:50 +0200 Subject: arm64: dts: qcom: sm6350: Add RPMHCC node Add RPMHCC node to allow for referencing RPMH-controlled clocks in other nodes. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-4-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 5442c088cf37..555ae0bbba18 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -477,6 +477,13 @@ qcom,drv-id = <2>; qcom,tcs-config = , , , ; + + rpmhcc: clock-controller { + compatible = "qcom,sm6350-rpmh-clk"; + #clock-cells = <1>; + clock-names = "xo"; + clocks = <&xo_board>; + }; }; }; -- cgit From 30de1108df222e760297ed76f1ff1b4acc960dc7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:51 +0200 Subject: arm64: dts: qcom: sm6350: Add GCC node Add and configure GCC node to allow for referencing GCC-controlled clocks in other nodes. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-5-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 555ae0bbba18..9934ecec1bb2 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -3,6 +3,8 @@ * Copyright (c) 2021, Konrad Dybcio */ +#include +#include #include #include #include @@ -357,6 +359,20 @@ dma-ranges = <0 0 0 0 0x10 0>; compatible = "simple-bus"; + gcc: clock-controller@100000 { + compatible = "qcom,gcc-sm6350"; + reg = <0 0x00100000 0 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + clock-names = "bi_tcxo", + "bi_tcxo_ao", + "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; + }; + ipcc: mailbox@408000 { compatible = "qcom,sm6350-ipcc", "qcom,ipcc"; reg = <0 0x00408000 0 0x1000>; -- cgit From 538f4bcd5106aba43c5864ff86797662df8c30ec Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:52 +0200 Subject: arm64: dts: qcom: sm6350: Add TLMM block node Add TLMM pinctrl node to enable referencing the SoC pins in other nodes. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-6-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 9934ecec1bb2..68de0beb9b01 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -404,6 +404,25 @@ interrupt-controller; }; + tlmm: pinctrl@f100000 { + compatible = "qcom,sm6350-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + interrupts = , + , + , + , + , + , + , + , + ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 157>; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- cgit From 23737b9557fea0d3069b0fbbecce3b1c09737de5 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:53 +0200 Subject: arm64: dts: qcom: sm6350: Add USB1 nodes Add nodes required for USB1 to function. SM6350 (thankfully) resuses SDM845 and SC7180 IP, so no additional code porting is required. Acked-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio [bjorn: Renamed dwc3 node "usb"] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-7-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 101 +++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 68de0beb9b01..e01a2b5af4de 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -388,12 +388,113 @@ #hwlock-cells = <1>; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>; + clock-names = "cfg_ahb", "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_1_qmpphy: phy@88e9000 { + compatible = "qcom,sc7180-qmp-usb3-dp-phy"; + reg = <0 0x088e9000 0 0x200>, + <0 0x088e8000 0 0x40>, + <0 0x088ea000 0 0x200>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_QLINK_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&xo_board>; + clock-names = "aux", "ref", "com_aux", "cfg_ahb"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: usb3-phy@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x400>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #clock-cells = <0>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + + dp_phy: dp-phy@88ea200 { + reg = <0 0x088ea200 0 0x200>, + <0 0x088ea400 0 0x200>, + <0 0x088eac00 0 0x400>, + <0 0x088ea600 0 0x200>, + <0 0x088ea800 0 0x200>, + <0 0x088eaa00 0 0x100>; + #phy-cells = <0>; + #clock-cells = <1>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; }; + usb_1: usb@a6f8800 { + compatible = "qcom,sm6350-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + interrupts = ; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x10>; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm6350-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>; -- cgit From 3cc415413f540403a0cbc36a49aa40ba764f708c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:54 +0200 Subject: arm64: dts: qcom: sm6350: Add cpufreq-hw support Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable CPU clock scaling. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-8-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index e01a2b5af4de..fc4b1c3f6471 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -42,6 +42,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_0>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_0: l2-cache { compatible = "cache"; @@ -60,6 +61,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_100>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_100: l2-cache { compatible = "cache"; @@ -75,6 +77,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_200>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_200: l2-cache { compatible = "cache"; @@ -90,6 +93,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_300>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_300: l2-cache { compatible = "cache"; @@ -105,6 +109,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_400>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_400: l2-cache { compatible = "cache"; @@ -120,6 +125,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; next-level-cache = <&L2_500>; + qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; L2_500: l2-cache { compatible = "cache"; @@ -136,6 +142,7 @@ capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <703>; next-level-cache = <&L2_600>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_600: l2-cache { compatible = "cache"; @@ -151,6 +158,7 @@ capacity-dmips-mhz = <1894>; dynamic-power-coefficient = <703>; next-level-cache = <&L2_700>; + qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; L2_700: l2-cache { compatible = "cache"; @@ -621,6 +629,16 @@ clocks = <&xo_board>; }; }; + + cpufreq_hw: cpufreq@18323000 { + compatible = "qcom,cpufreq-hw"; + reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + }; }; timer { -- cgit From 25e0ae68481905f40c41d6b588d221354fb36055 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:55 +0200 Subject: arm64: dts: qcom: sm6350: Add TSENS nodes Add nodes required for TSENS block using the common qcom,tsens-v2 binding. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-9-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index fc4b1c3f6471..cdb342d9153b 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -513,6 +513,28 @@ interrupt-controller; }; + tsens0: thermal-sensor@c263000 { + compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; + reg = <0 0x0c263000 0 0x1ff>, /* TM */ + <0 0x0c222000 0 0x8>; /* SROT */ + #qcom,sensors = <16>; + interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 28 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c265000 { + compatible = "qcom,sm6350-tsens", "qcom,tsens-v2"; + reg = <0 0x0c265000 0 0x1ff>, /* TM */ + <0 0x0c223000 0 0x8>; /* SROT */ + #qcom,sensors = <16>; + interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 29 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", "critical"; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sm6350-tlmm"; reg = <0 0x0f100000 0 0x300000>; -- cgit From 8fe2e0d9dba8cafa98dbd6c8f3cfbc6a20bbc93a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:56 +0200 Subject: arm64: dts: qcom: sm6350: Add AOSS_QMP Add a node for AOSS_QMP in preparation for remote processor enablement. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-10-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index cdb342d9153b..a9ebce05168a 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -535,6 +535,17 @@ #thermal-sensor-cells = <1>; }; + aoss_qmp: power-controller@c300000 { + compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x1000>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + #power-domain-cells = <1>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sm6350-tlmm"; reg = <0 0x0f100000 0 0x300000>; -- cgit From 001eaf9514f22eb9a01725a0c29b3f46cd7cdc0c Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:57 +0200 Subject: arm64: dts: qcom: sm6350: Add SPMI bus Add a node for SPMI to allow for communication with on-board PMICs. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-11-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index a9ebce05168a..52e4abda1045 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -546,6 +546,24 @@ #power-domain-cells = <1>; }; + spmi_bus: spmi@c440000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0xc440000 0 0x1100>, + <0 0xc600000 0 0x2000000>, + <0 0xe600000 0 0x100000>, + <0 0xe700000 0 0xa0000>, + <0 0xc40a000 0 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,sm6350-tlmm"; reg = <0 0x0f100000 0 0x300000>; -- cgit From 574af54562440e7036a7b4a71d016f166ca2e830 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:58 +0200 Subject: arm64: dts: qcom: sm6350: Add PRNG node Add a node for the PRNG to enable hw-accelerated pseudo-random number generation. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-12-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 52e4abda1045..edebf283514f 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -390,6 +390,13 @@ #mbox-cells = <2>; }; + rng: rng@793000 { + compatible = "qcom,prng-ee"; + reg = <0 0x00793000 0 0x1000>; + clocks = <&gcc GCC_PRNG_AHB_CLK>; + clock-names = "core"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; -- cgit From 9264d3c8ee511b5c246f2dd96fc94230c2b588f6 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:21:59 +0200 Subject: arm64: dts: qcom: sm6350: Add RPMHPD and BCM voter Add RPMHPD node, its OPP table and BCM voter to prepare for performance level voting. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-13-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 54 ++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index edebf283514f..55a53376443e 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -686,6 +686,60 @@ clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sm6350-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = ; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = ; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = ; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = ; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = ; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = ; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = ; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = ; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = ; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = ; + }; + }; + }; + + apps_bcm_voter: bcm_voter { + compatible = "qcom,bcm-voter"; + }; }; cpufreq_hw: cpufreq@18323000 { -- cgit From 1797e1c9a95cd052ad481968e078c9f2beec0e8b Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:22:00 +0200 Subject: arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes Add SDHCI1/2 nodes for eMMC and uSD card respectively. Do note that most SM6350 devices seem to come with UFS. Signed-off-by: Konrad Dybcio [bjorn: Replaced SM6350_CX with its constant value] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-14-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 81 ++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 55a53376443e..cbe355b3f5e8 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include / { @@ -397,12 +398,92 @@ clock-names = "core"; }; + sdhc_1: sdhci@7c4000 { + compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x007c4000 0 0x1000>, + <0 0x007c5000 0 0x1000>, + <0 0x007c8000 0 0x8000>; + reg-names = "hc", "cqhci", "ice"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + qcom,dll-config = <0x000f642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd 0>; + operating-points-v2 = <&sdhc1_opp_table>; + bus-width = <8>; + non-removable; + supports-cqe; + + status = "disabled"; + + sdhc1_opp_table: sdhc1-opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x0 0x01f40000 0x0 0x40000>; #hwlock-cells = <1>; }; + sdhc_2: sdhci@8804000 { + compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd 0>; + operating-points-v2 = <&sdhc2_opp_table>; + bus-width = <4>; + + status = "disabled"; + + sdhc2_opp_table: sdhc2-opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + usb_1_hsphy: phy@88e3000 { compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy"; reg = <0 0x088e3000 0 0x400>; -- cgit From 4ef13f7fe4cd9e29118e09597b4fdd721fd24c11 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:22:01 +0200 Subject: arm64: dts: qcom: sm6350: Add apps_smmu and assign iommus prop to USB1 Add a node for the APPS SMMU to allow for managing memory access to peripherals such as the USB controller. While at it, add iommus property to the USB1 node to make sure its registers can be accessed, as they seem to be gated by default. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-15-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 89 ++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index cbe355b3f5e8..926d30c57add 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -582,6 +582,7 @@ compatible = "snps,dwc3"; reg = <0 0x0a600000 0 0xcd00>; interrupts = ; + iommus = <&apps_smmu 0x540 0x0>; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; snps,has-lpm-erratum; @@ -671,6 +672,94 @@ gpio-ranges = <&tlmm 0 0 157>; }; + apps_smmu: iommu@15000000 { + compatible = "qcom,sm6350-smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + #iommu-cells = <2>; + #global-interrupts = <1>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; -- cgit From ed1648d52a375e606a0c88f5bf65282686ae6541 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:22:02 +0200 Subject: arm64: dts: qcom: sm6350: Add device tree for Sony Xperia 10 III Add initial SM6350 SoC and Sony Xperia 10 III (PDX213, Lena platform) device trees. There is no sign of another Lena devices on the horizon, so a common DTSI is not created for now. 10 III features a Full HD OLED display and 5G support, among other nice things like USB3. The bootloader is VERY unpleasant, to get a bootable setup you have to run: mkbootimg --kernel arch/arm64/boot/Image.gz --ramdisk [some initrd] \ --dtb arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dtb \ --cmdline "[some cmdline]" --base 0 --kernel_offset 0x8000 \ --ramdisk_offset 0x1000000 --dtb_offset 0x1f00000 --os_version 11 \ --os_patch_level "2021-08" --tags_offset 0x100 --pagesize 4096 \ --header_version 2 -o mainline.img adb reboot bootloader // You have to either pull vbmeta{"","_system"} from // /dev/block/bootdevice/by-name/ or build one as a part of AOSP build process fastboot --disable-verity --disable-verification flash vbmeta vbmeta.img fastboot --disable-verity --disable-verification flash vbmeta_system \ vbmeta_system.img fastboot flash boot mainline.img fastboot erase dtbo // This will take approx 70s... fastboot reboot Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-16-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + .../dts/qcom/sm6350-sony-xperia-lena-pdx213.dts | 57 ++++++++++++++++++++++ 2 files changed, 58 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 2a8fd0dbf274..a7af01230d09 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -91,6 +91,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-oneplus-fajita.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts new file mode 100644 index 000000000000..a26c23754f5d --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, Konrad Dybcio + */ +/dts-v1/; + +#include "sm6350.dtsi" + +/ { + model = "Sony Xperia 10 III"; + compatible = "sony,pdx213", "qcom,sm6350"; + qcom,msm-id = <434 0x10000>, <459 0x10000>; + qcom,board-id = <0x1000B 0>; + + chosen { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + framebuffer: framebuffer@a0000000 { + compatible = "simple-framebuffer"; + reg = <0 0xa0000000 0 0x2300000>; + width = <1080>; + height = <2520>; + stride = <(1080 * 4)>; + format = "a8r8g8b8"; + clocks = <&gcc GCC_DISP_AXI_CLK>; + }; + }; +}; + +&sdhc_2 { + status = "okay"; + + cd-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>; +}; + +&tlmm { + gpio-reserved-ranges = <13 4>, <45 2>, <56 2>; +}; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + maximum-speed = "super-speed"; + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + status = "okay"; +}; + +&usb_1_qmpphy { + status = "okay"; +}; -- cgit From a9a5ca5c8c37793aaf8fb99f593ac9ddad0bf0bf Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 23 Sep 2021 18:22:03 +0200 Subject: arm64: dts: qcom: pm6150l: Add missing include Add missing include to make it compile. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210923162204.21752-17-konrad.dybcio@somainline.org --- arch/arm64/boot/dts/qcom/pm6150l.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/qcom/pm6150l.dtsi b/arch/arm64/boot/dts/qcom/pm6150l.dtsi index b49860cd1387..3ca2860bb0cf 100644 --- a/arch/arm64/boot/dts/qcom/pm6150l.dtsi +++ b/arch/arm64/boot/dts/qcom/pm6150l.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause // Copyright (c) 2019, The Linux Foundation. All rights reserved. +#include #include #include -- cgit From ede638c42c82b1e6648a3c6ac71aaf088ff830e2 Mon Sep 17 00:00:00 2001 From: Sai Prakash Ranjan Date: Thu, 12 Aug 2021 14:47:42 +0530 Subject: arm64: dts: qcom: sc7180: Add IMEM and pil info regions Add IMEM and pil info DT nodes for SC7180 SoC which will help in the post-mortem debug. Signed-off-by: Sai Prakash Ranjan [bjorn: Dropped dload-mode subnode, as no agreement was reached on this binding] Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/39064a2db95ccc2cb5eef003569bef2de651c8ed.1628757036.git.saiprakash.ranjan@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index acd2d1f45311..f10217c0e70c 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -3245,6 +3245,21 @@ cell-index = <0>; }; + imem@146aa000 { + compatible = "simple-mfd"; + reg = <0 0x146aa000 0 0x2000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0 0x146aa000 0x2000>; + + pil-reloc@94c { + compatible = "qcom,pil-reloc-info"; + reg = <0x94c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc7180-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; -- cgit From 51c7786f5d4201422e076b9a3650e543a61d36da Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 16 Aug 2021 14:35:44 +0200 Subject: arm64: dts: qcom: msm8916-longcheer-l8150: Add missing sensor interrupts So far there were no interrupts set up for the BMC150 accelerometer + magnetometer combo because they were broken for some reason. It turns out Longcheer L8150 actually has a BMC156 which is very similar to BMC150, but only has an INT2 pin for the accelerometer part. This requires some minor changes in the bmc150-accel driver which is now supported by using the more correct bosch,bmc156_accel compatible. Unfortunately it looks like even INT2 is not functional on most boards because the interrupt line is not actually connected to the BMC156. However, there are two pads next to the chip that can be shorted to make it work if needed. While at it, add the missing interrupts for the magnetometer part and extra BMG160 gyroscope, those seem to work without any problems. Also correct the magnetometer compatible to bosch,bmc156_magn for clarity (no functional difference for the magnetometer part). Tested-by: Nikita Travkin Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210816123544.14027-1-stephan@gerhold.net --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 43 ++++++++++++++++++++-- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 1e893c0b6fbc..30716eb8fb2d 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -121,9 +121,21 @@ status = "okay"; accelerometer@10 { - compatible = "bosch,bmc150_accel"; + compatible = "bosch,bmc156_accel"; reg = <0x10>; + /* + * For some reason the interrupt line is usually not connected + * to the BMC156. However, there are two pads next to the chip + * that can be shorted to make it work if needed. + * + * interrupt-parent = <&msmgpio>; + * interrupts = <116 IRQ_TYPE_EDGE_RISING>; + */ + + pinctrl-names = "default"; + pinctrl-0 = <&accel_int_default>; + vdd-supply = <&pm8916_l17>; vddio-supply = <&pm8916_l6>; @@ -133,9 +145,15 @@ }; magnetometer@12 { - compatible = "bosch,bmc150_magn"; + compatible = "bosch,bmc156_magn"; reg = <0x12>; + interrupt-parent = <&msmgpio>; + interrupts = <113 IRQ_TYPE_EDGE_RISING>; + + pinctrl-names = "default"; + pinctrl-0 = <&magn_int_default>; + vdd-supply = <&pm8916_l17>; vddio-supply = <&pm8916_l6>; }; @@ -145,7 +163,8 @@ reg = <0x68>; interrupt-parent = <&msmgpio>; - interrupts = <23 IRQ_TYPE_EDGE_RISING>; + interrupts = <23 IRQ_TYPE_EDGE_RISING>, + <22 IRQ_TYPE_EDGE_RISING>; pinctrl-names = "default"; pinctrl-0 = <&gyro_int_default>; @@ -336,6 +355,14 @@ }; &msmgpio { + accel_int_default: accel-int-default { + pins = "gpio116"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + camera_flash_default: camera-flash-default { pins = "gpio31", "gpio32"; function = "gpio"; @@ -361,7 +388,15 @@ }; gyro_int_default: gyro-int-default { - pins = "gpio23"; + pins = "gpio22", "gpio23"; + function = "gpio"; + + drive-strength = <2>; + bias-disable; + }; + + magn_int_default: magn-int-default { + pins = "gpio113"; function = "gpio"; drive-strength = <2>; -- cgit From 8199a0b31e76d158ac14841e7119890461f8c595 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Mon, 16 Aug 2021 20:18:10 +0200 Subject: arm64: dts: qcom: msm8916: Fix Secondary MI2S bit clock At the moment, playing audio on Secondary MI2S will just end up getting stuck, without actually playing any audio. This happens because the wrong bit clock is configured when playing audio on Secondary MI2S. The PRI_I2S_CLK (better name: SPKR_I2S_CLK) is used by the SPKR audio mux block that provides both Primary and Secondary MI2S. The SEC_I2S_CLK (better name: MIC_I2S_CLK) is used by the MIC audio mux block that provides Tertiary MI2S. Quaternary MI2S is also part of the MIC audio mux but has its own clock (AUX_I2S_CLK). This means that (quite confusingly) the SEC_I2S_CLK is not actually used for Secondary MI2S as the name would suggest. Secondary MI2S needs to have the same clock as Primary MI2S configured. Fix the clock list for the lpass node in the device tree and add a comment to clarify this confusing naming. With these changes, audio can be played correctly on Secondary MI2S. Cc: Srinivas Kandagatla Fixes: 3761a3618f55 ("arm64: dts: qcom: add lpass node") Tested-by: Vincent Knecht Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210816181810.2242-1-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 973a584f1e9e..6b06b387b021 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -1384,11 +1384,17 @@ lpass: audio-controller@7708000 { status = "disabled"; compatible = "qcom,lpass-cpu-apq8016"; + + /* + * Note: Unlike the name would suggest, the SEC_I2S_CLK + * is actually only used by Tertiary MI2S while + * Primary/Secondary MI2S both use the PRI_I2S_CLK. + */ clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>, <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, - <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, + <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>; -- cgit From 122d2c5f31b6e668a9c01bd023949b0f39954c76 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:38:20 +0200 Subject: arm64: dts: qcom: Add support for MSM8998 F(x)tec Pro1 QX1000 Add device tree support for the F(x)tec Pro 1 (QX1000) smartphone; this is a minimal configuration to boot to serial console. Signed-off-by: AngeloGioacchino Del Regno Reported-by: kernel test robot Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123823.368199-1-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 185 ++++++++++++++++++++++++ 2 files changed, 186 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index a7af01230d09..8398c0a2150f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -36,6 +36,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8996-sony-xperia-tone-keyaki.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-gemini.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8996-xiaomi-scorpio.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-asus-novago-tp370ql.dtb +dtb-$(CONFIG_ARCH_QCOM) += msm8998-fxtec-pro1.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-hp-envy-x2.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-lenovo-miix-630.dtb dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts new file mode 100644 index 000000000000..dc566567f42f --- /dev/null +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -0,0 +1,185 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2021, AngeloGioacchino Del Regno + * + */ + +/dts-v1/; + +#include "msm8998-mtp.dtsi" + +#include +#include +#include + +/ { + model = "F(x)tec Pro1 (QX1000)"; + compatible = "fxtec,pro1", "qcom,msm8998"; + qcom,board-id = <0x02000b 0x10>; + + /* + * Until we hook up type-c detection, we + * have to stick with this. But it works. + */ + extcon_usb: extcon-usb { + compatible = "linux,extcon-usb-gpio"; + id-gpio = <&tlmm 38 GPIO_ACTIVE_HIGH>; + }; + + gpio-hall-sensors { + compatible = "gpio-keys"; + input-name = "hall-sensors"; + label = "Hall sensors"; + pinctrl-names = "default"; + pinctrl-0 = <&hall_sensor1_default>; + + hall-sensor1 { + label = "Keyboard Hall Sensor"; + gpios = <&tlmm 124 GPIO_ACTIVE_HIGH>; + debounce-interval = <15>; + gpio-key,wakeup; + linux,input-type = ; + linux,code = ; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "side-buttons"; + label = "Side buttons"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&vol_up_pin_a>, <&cam_focus_pin_a>, + <&cam_snapshot_pin_a>; + vol-up { + label = "Volume Up"; + gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + gpio-key,wakeup; + debounce-interval = <15>; + }; + + camera-snapshot { + label = "Camera Snapshot"; + gpios = <&pm8998_gpio 7 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <15>; + }; + + camera-focus { + label = "Camera Focus"; + gpios = <&pm8998_gpio 8 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <15>; + }; + }; + + reserved-memory { + cont_splash_mem: memory@9d400000 { + reg = <0x0 0x9d400000 0x0 0x2000000>; + no-map; + }; + + zap_shader_region: memory@f6400000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xf6400000 0x0 0x2000>; + no-map; + }; + + ramoops@ffc00000 { + compatible = "ramoops"; + reg = <0x0 0xffc00000 0x0 0x100000>; + console-size = <0x60000>; + ecc-size = <16>; + ftrace-size = <0x10000>; + pmsg-size = <0x20000>; + record-size = <0x10000>; + }; + }; +}; + +&mmcc { + status = "ok"; +}; + +&mmss_smmu { + status = "ok"; +}; + +&pm8998_gpio { + vol_up_pin_a: vol-up-active { + pins = "gpio6"; + function = "normal"; + bias-pull-up; + input-enable; + qcom,drive-strength = ; + }; + + cam_focus_pin_a: cam-focus-btn-active { + pins = "gpio7"; + function = "normal"; + bias-pull-up; + input-enable; + qcom,drive-strength = ; + }; + + cam_snapshot_pin_a: cam-snapshot-btn-active { + pins = "gpio8"; + function = "normal"; + bias-pull-up; + input-enable; + qcom,drive-strength = ; + }; +}; + +&pm8998_pon { + resin { + compatible = "qcom,pm8941-resin"; + interrupts = ; + bias-pull-up; + debounce = <15625>; + linux,code = ; + }; +}; + +&tlmm { + gpio-reserved-ranges = <0 4>; + + mdp_vsync_n: mdp-vsync-n { + pins = "gpio10"; + function = "mdp_vsync_a"; + bias-pull-down; + drive-strength = <2>; + }; + + hall_sensor1_default: hall-sensor1-def { + pins = "gpio124"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + input-enable; + }; +}; + +&ufshc { + status = "ok"; +}; + +&ufsphy { + status = "ok"; +}; + +&usb3_dwc3 { + dr_mode = "peripheral"; + extcon = <&extcon_usb>; +}; + +/* GT9286 analog supply */ +&vreg_l28_3p0 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; +}; -- cgit From 946c9a2cf8b02a21275e83f0d75826856c223eae Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:38:21 +0200 Subject: arm64: dts: qcom: msm8998-fxtec-pro1: Add physical keyboard leds Add configuration for the physical keyboard LEDs, including the caps lock indicator and keyboard backlight. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123823.368199-2-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index dc566567f42f..d44250f09965 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -78,6 +78,28 @@ }; }; + keyboard-leds { + compatible = "gpio-leds"; + + backlight { + color = ; + default-state = "off"; + function = LED_FUNCTION_KBD_BACKLIGHT; + gpios = <&tlmm 16 GPIO_ACTIVE_HIGH>; + label = "white:kbd_backlight"; + retain-state-suspended; + }; + + caps-lock { + color = ; + default-state = "off"; + function = LED_FUNCTION_CAPSLOCK; + gpios = <&tlmm 26 GPIO_ACTIVE_HIGH>; + label = "yellow:capslock"; + linux,default-trigger = "kbd-capslock"; + }; + }; + reserved-memory { cont_splash_mem: memory@9d400000 { reg = <0x0 0x9d400000 0x0 0x2000000>; -- cgit From f66ea51f0e477b8a8ceff3a6257df163c54af478 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:38:22 +0200 Subject: arm64: dts: qcom: msm8998-fxtec-pro1: Add Goodix GT9286 touchscreen This smartphone has a Goodix GT8296 touch IC, reachable at address 0x14 on blsp2 i2c-1. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123823.368199-3-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index d44250f09965..deabb00758e3 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -122,6 +122,33 @@ record-size = <0x10000>; }; }; + + ts_vio_vreg: ts-vio-vreg { + compatible = "regulator-fixed"; + regulator-name = "ts_vio_reg"; + startup-delay-us = <2>; + enable-active-high; + gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&ts_vio_default>; + regulator-always-on; + }; +}; + +&blsp2_i2c1 { + status = "ok"; + + touchscreen@14 { + compatible = "goodix,gt9286"; + reg = <0x14>; + interrupt-parent = <&tlmm>; + interrupts = <125 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&vreg_l28_3p0>; + VDDIO-supply = <&ts_vio_vreg>; + pinctrl-names = "active"; + pinctrl-0 = <&ts_rst_n>, <&ts_int_n>; + }; }; &mmcc { @@ -178,6 +205,20 @@ drive-strength = <2>; }; + ts_vio_default: ts-vio-def { + pins = "gpio81"; + function = "gpio"; + bias-disable; + drive-strength = <2>; + }; + + ts_rst_n: ts-rst-n { + pins = "gpio89"; + function = "gpio"; + bias-pull-up; + drive-strength = <8>; + }; + hall_sensor1_default: hall-sensor1-def { pins = "gpio124"; function = "gpio"; @@ -185,6 +226,13 @@ drive-strength = <2>; input-enable; }; + + ts_int_n: ts-int-n { + pins = "gpio125"; + function = "gpio"; + bias-disable; + drive-strength = <8>; + }; }; &ufshc { -- cgit From cea83511353d896be613a69ccee1c464e68686f6 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 9 Sep 2021 14:38:23 +0200 Subject: arm64: dts: qcom: msm8998-fxtec-pro1: Add tlmm keyboard keys This device has a physical matrix keyboard, connected to a GPIO expander, for which there's still no support yet. Though, some of the keys are connected to the MSM8998 GPIOs and not as a matrix, so these can be added. Signed-off-by: AngeloGioacchino Del Regno Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210909123823.368199-4-angelogioacchino.delregno@somainline.org --- arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts | 64 +++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts index deabb00758e3..49705fe655ee 100644 --- a/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts +++ b/arch/arm64/boot/dts/qcom/msm8998-fxtec-pro1.dts @@ -43,6 +43,62 @@ }; }; + gpio-kb-extra-keys { + compatible = "gpio-keys"; + input-name = "extra-kb-keys"; + label = "Keyboard extra keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_kb_pins_extra>; + + home { + label = "Home"; + gpios = <&tlmm 21 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + }; + + super-l { + label = "Super Left"; + gpios = <&tlmm 32 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + }; + + super-r { + label = "Super Right"; + gpios = <&tlmm 33 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + }; + + shift { + label = "Shift"; + gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + }; + + ctrl { + label = "Ctrl"; + gpios = <&tlmm 128 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + }; + + alt { + label = "Alt"; + gpios = <&tlmm 129 GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <15>; + linux,can-disable; + }; + }; + gpio-keys { compatible = "gpio-keys"; input-name = "side-buttons"; @@ -205,6 +261,14 @@ drive-strength = <2>; }; + gpio_kb_pins_extra: gpio-kb-pins-extra { + pins = "gpio21", "gpio32", "gpio33", "gpio114", + "gpio128", "gpio129"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + ts_vio_default: ts-vio-def { pins = "gpio81"; function = "gpio"; -- cgit From eca7d3a366b3ab9f31e142c13a43c5b0f94a920d Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 17 Sep 2021 19:25:31 +0530 Subject: arm64: dts: qcom: sc7280: Update reserved memory map Add missing reserved regions as described in v1 of SC7280 memory map. Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631886935-14691-7-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 844762cdcc32..ee287e103bbf 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -83,6 +83,16 @@ #size-cells = <2>; ranges; + hyp_mem: memory@80000000 { + reg = <0x0 0x80000000 0x0 0x600000>; + no-map; + }; + + xbl_mem: memory@80600000 { + reg = <0x0 0x80600000 0x0 0x200000>; + no-map; + }; + aop_mem: memory@80800000 { reg = <0x0 0x80800000 0x0 0x60000>; no-map; @@ -94,6 +104,16 @@ no-map; }; + reserved_xbl_uefi_log: memory@80880000 { + reg = <0x0 0x80884000 0x0 0x10000>; + no-map; + }; + + sec_apps_mem: memory@808ff000 { + reg = <0x0 0x808ff000 0x0 0x1000>; + no-map; + }; + smem_mem: memory@80900000 { reg = <0x0 0x80900000 0x0 0x200000>; no-map; @@ -104,10 +124,24 @@ reg = <0x0 0x80b00000 0x0 0x100000>; }; + wlan_fw_mem: memory@80c00000 { + reg = <0x0 0x80c00000 0x0 0xc00000>; + no-map; + }; + ipa_fw_mem: memory@8b700000 { reg = <0 0x8b700000 0 0x10000>; no-map; }; + + rmtfs_mem: memory@9c900000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0 0x9c900000 0x0 0x280000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <15>; + }; }; cpus { -- cgit From f83146890172da67443c7b80e529fd1781046c65 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 17 Sep 2021 19:25:32 +0530 Subject: arm64: dts: qcom: sc7280: Add/Delete/Update reserved memory nodes Add, delete and update platform specific reserved memory nodes. Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631886935-14691-8-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 52 ++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index def22ff78906..e0972fa13861 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -33,6 +33,58 @@ }; }; +/* + * Reserved memory changes + * + * Delete all unused memory nodes and define the peripheral memory regions + * required by the board dts. + * + */ + +/delete-node/ &hyp_mem; +/delete-node/ &xbl_mem; +/delete-node/ &reserved_xbl_uefi_log; +/delete-node/ &sec_apps_mem; + +/* Increase the size from 2.5MB to 8MB */ +&rmtfs_mem { + reg = <0x0 0x9c900000 0x0 0x800000>; +}; + +/ { + reserved-memory { + adsp_mem: memory@86700000 { + reg = <0x0 0x86700000 0x0 0x2800000>; + no-map; + }; + + camera_mem: memory@8ad00000 { + reg = <0x0 0x8ad00000 0x0 0x500000>; + no-map; + }; + + venus_mem: memory@8b200000 { + reg = <0x0 0x8b200000 0x0 0x500000>; + no-map; + }; + + mpss_mem: memory@8b800000 { + reg = <0x0 0x8b800000 0x0 0xf600000>; + no-map; + }; + + wpss_mem: memory@9ae00000 { + reg = <0x0 0x9ae00000 0x0 0x1900000>; + no-map; + }; + + mba_mem: memory@9c700000 { + reg = <0x0 0x9c700000 0x0 0x200000>; + no-map; + }; + }; +}; + &apps_rsc { pm7325-regulators { compatible = "qcom,pm7325-rpmh-regulators"; -- cgit From dddf4b0621d61b8203d500ef85a853626ff42432 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 17 Sep 2021 19:25:33 +0530 Subject: arm64: dts: qcom: sc7280: Add nodes to boot modem Add miscellaneous nodes to boot the modem and support post-mortem debug on SC7280 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631886935-14691-9-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ee287e103bbf..f7f882e302d5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1606,6 +1606,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fc0000 { + compatible = "qcom,sc7280-tcsr", "syscon"; + reg = <0 0x01fc0000 0 0x30000>; + }; + lpasscc: lpasscc@3000000 { compatible = "qcom,sc7280-lpasscc"; reg = <0 0x03000000 0 0x40>, @@ -3361,6 +3366,21 @@ }; }; + imem@146a5000 { + compatible = "qcom,sc7280-imem", "syscon"; + reg = <0 0x146a5000 0 0x6000>; + + #address-cells = <1>; + #size-cells = <1>; + + ranges = <0 0 0x146a5000 0x6000>; + + pil-reloc@594c { + compatible = "qcom,pil-reloc-info"; + reg = <0x594c 0xc8>; + }; + }; + apps_smmu: iommu@15000000 { compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; reg = <0 0x15000000 0 0x100000>; -- cgit From 4882cafb99c2b004b9773631fb00ca6d96dc0124 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 17 Sep 2021 19:25:34 +0530 Subject: arm64: dts: qcom: sc7280: Add Q6V5 MSS node This patch adds Q6V5 MSS PAS remoteproc node for SC7280 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Matthias Kaehlcke Reviewed-by: Stephen Boyd Reviewed-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631886935-14691-10-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 40 ++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index f7f882e302d5..002bc34c44e3 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1759,6 +1759,46 @@ power-domains = <&gpucc 0>; }; + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sc7280-mpss-pas"; + reg = <0 0x04080000 0 0x10000>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", "handover", + "stop-ack", "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + power-domains = <&rpmhpd SC7280_CX>, + <&rpmhpd SC7280_MSS>; + power-domain-names = "cx", "mss"; + + memory-region = <&mpss_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + label = "modem"; + qcom,remote-pid = <1>; + }; + }; + stm@6002000 { compatible = "arm,coresight-stm", "arm,primecell"; reg = <0 0x06002000 0 0x1000>, -- cgit From 0025fac17b313cca5c640dd57cbf38d01ce10b27 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Fri, 17 Sep 2021 19:25:35 +0530 Subject: arm64: dts: qcom: sc7280: Update Q6V5 MSS node Update MSS node to support MSA based modem boot on SC7280 SoCs. Signed-off-by: Sibi Sankar Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/1631886935-14691-11-git-send-email-sibis@codeaurora.org --- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 7 +++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 19 ++++++++++++++++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index e0972fa13861..272d5ca957dc 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -306,6 +306,13 @@ status = "okay"; }; +&remoteproc_mpss { + status = "okay"; + compatible = "qcom,sc7280-mss-pil"; + iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>; + memory-region = <&mba_mem &mpss_mem>; +}; + &sdhc_1 { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 002bc34c44e3..24956570eb8e 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1761,7 +1761,8 @@ remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sc7280-mpss-pas"; - reg = <0 0x04080000 0 0x10000>; + reg = <0 0x04080000 0 0x10000>, <0 0x04180000 0 0x48>; + reg-names = "qdsp6", "rmb"; interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, @@ -1772,8 +1773,12 @@ interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack", "shutdown-ack"; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "xo"; + clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, + <&gcc GCC_MSS_OFFLINE_AXI_CLK>, + <&gcc GCC_MSS_SNOC_AXI_CLK>, + <&rpmhcc RPMH_PKA_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "offline", "snoc_axi", "pka", "xo"; power-domains = <&rpmhpd SC7280_CX>, <&rpmhpd SC7280_MSS>; @@ -1786,6 +1791,14 @@ qcom,smem-states = <&modem_smp2p_out 0>; qcom,smem-state-names = "stop"; + resets = <&aoss_reset AOSS_CC_MSS_RESTART>, + <&pdc_reset PDC_MODEM_SYNC_RESET>; + reset-names = "mss_restart", "pdc_reset"; + + qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>; + qcom,ext-regs = <&tcsr 0x10000 0x10004 &tcsr_mutex 0x26004 0x26008>; + qcom,qaccept-regs = <&tcsr_mutex 0x23030 0x23040 0x23020>; + status = "disabled"; glink-edge { -- cgit From 483de2b44cd3a168458f8f9ff237e78a434729bc Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 28 Sep 2021 13:29:43 +0200 Subject: arm64: dts: qcom: pm8916: Remove wrong reg-names for rtc@6000 While removing the size from the "reg" properties in pm8916.dtsi, commit bd6429e81010 ("ARM64: dts: qcom: Remove size elements from pmic reg properties") mistakenly also removed the second register address for the rtc@6000 device. That one did not represent the size of the register region but actually the address of the second "alarm" register region of the rtc@6000 device. Now there are "reg-names" for two "reg" elements, but there is actually only one "reg" listed. Since the DT schema for "qcom,pm8941-rtc" only expects one "reg" element anyway, just drop the "reg-names" entirely to fix this. Fixes: bd6429e81010 ("ARM64: dts: qcom: Remove size elements from pmic reg properties") Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210928112945.25310-1-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index f931cb0de231..42180f1b5dbb 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -86,7 +86,6 @@ rtc@6000 { compatible = "qcom,pm8941-rtc"; reg = <0x6000>; - reg-names = "rtc", "alarm"; interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; }; -- cgit From f5d7bca55425c8611e6cfa3f236d1f56031920e8 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 28 Sep 2021 13:29:44 +0200 Subject: arm64: dts: qcom: pm8916: Add pm8941-misc extcon for USB detection At the moment, USB gadget mode on MSM8916 works only with an extcon device that reports the correct USB mode. This might be because the USB PHY needs to be configured appropriately. Unfortunately there is currently no simple approach to get such an extcon device during early bring-up. The extcon device for USB VBUS (i.e. gadget/peripheral mode) is typically provided by the charging driver which is almost always very complex to port. On pretty much all devices with PM8916, the USB VBUS is also connected to the PM8916 "USB_IN" pad, no matter if they use the linear charger integrated into PM8916 or not. The state of this pad can be checked with the "USBIN_VALID" interrupt of PM8916. The "qcom,pm8941-misc" binding exists to expose an "usb_vbus" and/or "usb_id" interrupt from the PMIC as an extcon device. Add a &pm8916_usbin node to pm8916.dtsi which can be used as simple extcon device for devices that are currently lacking a proper charger driver. Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210928112945.25310-2-stephan@gerhold.net --- arch/arm64/boot/dts/qcom/pm8916.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/pm8916.dtsi b/arch/arm64/boot/dts/qcom/pm8916.dtsi index 42180f1b5dbb..48c6c9cca53b 100644 --- a/arch/arm64/boot/dts/qcom/pm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8916.dtsi @@ -41,6 +41,14 @@ }; }; + pm8916_usbin: extcon@1300 { + compatible = "qcom,pm8941-misc"; + reg = <0x1300>; + interrupts = <0x0 0x13 1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "usb_vbus"; + status = "disabled"; + }; + pm8916_temp: temp-alarm@2400 { compatible = "qcom,spmi-temp-alarm"; reg = <0x2400>; -- cgit From b30cad26d8030bddeb0ee2373b6d4c1440ffb1a3 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Tue, 28 Sep 2021 13:29:45 +0200 Subject: arm64: dts: qcom: msm8916-longcheer-l8150: Use &pm8916_usbin extcon At the moment, longcheer-l8150 is using a dummy extcon-usb-gpio device that permanently enables USB gadget mode. This workaround allows USB to work but is actually wrong and confusing. The "vbus-gpio" used there refers to an unused (floating) GPIO that is pulled up to make extcon-usb-gpio report USB gadget mode permanently. Replace this with the new &pm8916_usbin extcon device that actually reports if an USB cable is attached or not. This allows the USB PHY to be turned off when there is no USB cable attached and is much cleaner overall. Fixes: 16e8e8072108 ("arm64: dts: qcom: Add device tree for Longcheer L8150") Signed-off-by: Stephan Gerhold Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210928112945.25310-3-stephan@gerhold.net --- .../boot/dts/qcom/msm8916-longcheer-l8150.dts | 23 ++++++---------------- 1 file changed, 6 insertions(+), 17 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts index 30716eb8fb2d..285102f0e04f 100644 --- a/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts +++ b/arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts @@ -30,14 +30,6 @@ }; }; - // FIXME: Use extcon device provided by charger driver when available - usb_vbus: usb-vbus { - compatible = "linux,extcon-usb-gpio"; - vbus-gpio = <&msmgpio 62 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&usb_vbus_default>; - }; - gpio-keys { compatible = "gpio-keys"; @@ -215,6 +207,10 @@ linux,code = ; }; +&pm8916_usbin { + status = "okay"; +}; + &pm8916_vib { status = "okay"; }; @@ -244,11 +240,11 @@ &usb { status = "okay"; dr_mode = "peripheral"; - extcon = <&usb_vbus>; + extcon = <&pm8916_usbin>; }; &usb_hs_phy { - extcon = <&usb_vbus>; + extcon = <&pm8916_usbin>; }; &smd_rpm_regulators { @@ -410,11 +406,4 @@ drive-strength = <2>; bias-disable; }; - - usb_vbus_default: usb-vbus-default { - pins = "gpio62"; - function = "gpio"; - - bias-pull-up; - }; }; -- cgit From 4e31e85759a0622b25a63300019d04ff031c95e0 Mon Sep 17 00:00:00 2001 From: Marijn Suijten Date: Sat, 25 Sep 2021 16:18:41 +0200 Subject: arm64: dts: qcom: sm6125: Improve indentation of multiline properties Some multiline properties (spread out over multiple lines to keep length in check) were not indented properly, leading to misalignment with the items above. The DT file is still small enough to address this early in the process. Signed-off-by: Marijn Suijten Reviewed-by: Martin Botka Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210925141841.407257-1-marijn.suijten@somainline.org --- arch/arm64/boot/dts/qcom/sm6125.dtsi | 46 ++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi index 0c1057456597..c2317dd29896 100644 --- a/arch/arm64/boot/dts/qcom/sm6125.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi @@ -326,8 +326,8 @@ tlmm: pinctrl@500000 { compatible = "qcom,sm6125-tlmm"; reg = <0x00500000 0x400000>, - <0x00900000 0x400000>, - <0x00d00000 0x400000>; + <0x00900000 0x400000>, + <0x00d00000 0x400000>; reg-names = "west", "south", "east"; interrupts = ; gpio-controller; @@ -391,12 +391,12 @@ reg-names = "hc", "core"; interrupts = , - ; + ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_AHB_CLK>, - <&gcc GCC_SDCC1_APPS_CLK>, - <&xo_board>; + <&gcc GCC_SDCC1_APPS_CLK>, + <&xo_board>; clock-names = "iface", "core", "xo"; bus-width = <8>; non-removable; @@ -409,12 +409,12 @@ reg-names = "hc"; interrupts = , - ; + ; interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&xo_board>; + <&gcc GCC_SDCC2_APPS_CLK>, + <&xo_board>; clock-names = "iface", "core", "xo"; pinctrl-0 = <&sdc2_state_on>; @@ -433,11 +433,11 @@ ranges; clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB3_PRIM_CLKREF_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB3_PRIM_CLKREF_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, <&gcc GCC_USB30_PRIM_MASTER_CLK>; @@ -462,11 +462,11 @@ spmi_bus: spmi@1c40000 { compatible = "qcom,spmi-pmic-arb"; - reg = <0x01c40000 0x1100>, - <0x01e00000 0x2000000>, - <0x03e00000 0x100000>, - <0x03f00000 0xa0000>, - <0x01c0a000 0x26000>; + reg = <0x01c40000 0x1100>, + <0x01e00000 0x2000000>, + <0x03e00000 0x100000>, + <0x03f00000 0xa0000>, + <0x01c0a000 0x26000>; reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; interrupt-names = "periph_irq"; interrupts = ; @@ -497,7 +497,7 @@ frame@f121000 { frame-number = <0>; interrupts = , - ; + ; reg = <0x0f121000 0x1000>, <0x0f122000 0x1000>; }; @@ -548,7 +548,7 @@ intc: interrupt-controller@f200000 { compatible = "arm,gic-v3"; reg = <0x0f200000 0x20000>, - <0x0f300000 0x100000>; + <0x0f300000 0x100000>; #interrupt-cells = <3>; interrupt-controller; interrupts = ; @@ -558,9 +558,9 @@ timer { compatible = "arm,armv8-timer"; interrupts = ; + GIC_PPI 2 0xf08 + GIC_PPI 3 0xf08 + GIC_PPI 0 0xf08>; clock-frequency = <19200000>; }; }; -- cgit From c22441a7cbd014e2546329af89363b2a43cc8bf2 Mon Sep 17 00:00:00 2001 From: Shawn Guo Date: Sun, 26 Sep 2021 15:22:15 +0800 Subject: arm64: dts: qcom: sdm630-nile: Correct regulator label name 29.5V (29p5) is obviously wrong for regulator l4 and l5. Correct them to be 2.95V (2p95). No functional change. Signed-off-by: Shawn Guo Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210926072215.27517-1-shawn.guo@linaro.org --- arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi index 849900e8b80e..11d0a8c1cf35 100644 --- a/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile.dtsi @@ -308,7 +308,7 @@ regulator-allow-set-load; }; - vreg_l4b_29p5: l4 { + vreg_l4b_2p95: l4 { regulator-min-microvolt = <2944000>; regulator-max-microvolt = <2952000>; regulator-enable-ramp-delay = <250>; @@ -327,7 +327,7 @@ * Tighten the range to 1.8-3.328 (closest to 3.3) to * make the mmc driver happy. */ - vreg_l5b_29p5: l5 { + vreg_l5b_2p95: l5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3328000>; regulator-enable-ramp-delay = <250>; @@ -559,14 +559,14 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; - vmmc-supply = <&vreg_l4b_29p5>; + vmmc-supply = <&vreg_l4b_2p95>; vqmmc-supply = <&vreg_l8a_1p8>; }; &sdhc_2 { status = "okay"; - vmmc-supply = <&vreg_l5b_29p5>; + vmmc-supply = <&vreg_l5b_2p95>; vqmmc-supply = <&vreg_l2b_2p95>; }; -- cgit