From 666b76e9ae7ed2fd7ac5ed000807ad9bc9a344b7 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Sun, 17 Mar 2024 23:32:03 +0100 Subject: dt-bindings: vendor-prefixes: add Cudy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cudy is a Chinese company providing networking products. Signed-off-by: Rafał Miłecki Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240317223206.22033-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index fbf47f0bacf1..e474055359f1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -338,6 +338,8 @@ patternProperties: description: Czech Technical University in Prague "^cubietech,.*": description: Cubietech, Ltd. + "^cudy,.*": + description: Shenzhen Cudy Technology Co., Ltd. "^cui,.*": description: CUI Devices "^cypress,.*": -- cgit From c016058b950470bacad0d06628bf396ef4feaba0 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Sun, 17 Mar 2024 23:32:04 +0100 Subject: dt-bindings: arm64: dts: mediatek: Add Cudy WR3000 V1 router MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cudy WR3000 V1 is an MT7981B (AKA Filogic 820) based wireless router. Signed-off-by: Rafał Miłecki Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240317223206.22033-3-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 09f9ffd3ff7b..1cf47db94c57 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -85,6 +85,7 @@ properties: - const: mediatek,mt7629 - items: - enum: + - cudy,wr3000-v1 - xiaomi,ax3000t - const: mediatek,mt7981b - items: -- cgit From 62b24c7fdf0a039814e3eed33de0dced3fc10aa4 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Sun, 17 Mar 2024 23:32:05 +0100 Subject: arm64: dts: mediatek: mt7981: add pinctrl MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7981 contains on-SoC PIN controller that is also a GPIO provider. Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240317223206.22033-4-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 4feff3d1c5f4..95c6fe888083 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -86,6 +86,28 @@ #pwm-cells = <2>; }; + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", + "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + gpio-ranges = <&pio 0 0 56>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- cgit From deb26f5bce5a2aec514a99141431f6a4360a12b1 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Sun, 17 Mar 2024 23:32:06 +0100 Subject: arm64: dts: mediatek: Add Cudy WR3000 V1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cudy WR3000 V1 is an MT7981B (AKA Filogic 820) based wireless router. It has 256 MiB of RAM, some LEDs & buttons and (not described yet) 4 Ethernet ports. Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240317223206.22033-5-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts | 74 ++++++++++++++++++++++ 2 files changed, 75 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 37b4ca3a87c9..96da4ad640aa 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts b/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts new file mode 100644 index 000000000000..54101cc08a25 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; +#include +#include +#include + +#include "mt7981b.dtsi" + +/ { + compatible = "cudy,wr3000-v1", "mediatek,mt7981b"; + model = "Cudy WR3000 V1"; + + memory@40000000 { + reg = <0 0x40000000 0 0x10000000>; + device_type = "memory"; + }; + + keys { + compatible = "gpio-keys"; + + key-wps { + label = "WPS"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-reset { + label = "RESET"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_WAN; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_WLAN_2GHZ; + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + }; + + led-2 { + color = ; + function = LED_FUNCTION_WLAN_5GHZ; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + led-3 { + color = ; + function = LED_FUNCTION_LAN; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-4 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led-5 { + color = ; + function = LED_FUNCTION_WAN_ONLINE; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + }; +}; -- cgit From e4b4f4d21aa63cfe6bebc5ca734a965faef095c0 Mon Sep 17 00:00:00 2001 From: Lorenzo Bianconi Date: Sat, 9 Mar 2024 10:32:14 +0100 Subject: dt-bindings: arm64: dts: airoha: Add en7581 entry Introduce Airoha EN7581 entry in Airoha dts binding. Acked-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/r/ee9cda964dac62d38d1c239f7b189f707d3708a0.1709975956.git.lorenzo@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/airoha.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml index 3292c669ee11..7c38c08dbf3f 100644 --- a/Documentation/devicetree/bindings/arm/airoha.yaml +++ b/Documentation/devicetree/bindings/arm/airoha.yaml @@ -22,6 +22,10 @@ properties: - enum: - airoha,en7523-evb - const: airoha,en7523 + - items: + - enum: + - airoha,en7581-evb + - const: airoha,en7581 additionalProperties: true -- cgit From ab52c59103002b49f2455371e4b9c56ba3ef1781 Mon Sep 17 00:00:00 2001 From: Daniel Danzberger Date: Sat, 9 Mar 2024 10:32:15 +0100 Subject: arm64: dts: Add Airoha EN7581 SoC and EN7581 Evaluation Board Introduce the Airoha EN7581 SoC's dtsi and the Airoha EN7581 Evaluation Board's dts file, as well as the required Makefiles. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Daniel Danzberger Co-developed-by: Lorenzo Bianconi Signed-off-by: Lorenzo Bianconi Link: https://lore.kernel.org/r/f05a36dd7e8ef34ead8a63aa10fcffb542229404.1709975956.git.lorenzo@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/Makefile | 1 + arch/arm64/boot/dts/airoha/Makefile | 2 + arch/arm64/boot/dts/airoha/en7581-evb.dts | 26 +++++ arch/arm64/boot/dts/airoha/en7581.dtsi | 154 ++++++++++++++++++++++++++++++ 4 files changed, 183 insertions(+) create mode 100644 arch/arm64/boot/dts/airoha/Makefile create mode 100644 arch/arm64/boot/dts/airoha/en7581-evb.dts create mode 100644 arch/arm64/boot/dts/airoha/en7581.dtsi diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 30dd6347a929..21cd3a87f385 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += actions +subdir-y += airoha subdir-y += allwinner subdir-y += altera subdir-y += amazon diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile new file mode 100644 index 000000000000..ebea112ce1d7 --- /dev/null +++ b/arch/arm64/boot/dts/airoha/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts new file mode 100644 index 000000000000..cf58e43dd5b2 --- /dev/null +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7581.dtsi" + +/ { + model = "Airoha EN7581 Evaluation Board"; + compatible = "airoha,en7581-evb", "airoha,en7581"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; +}; diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi new file mode 100644 index 000000000000..55eb1762fb11 --- /dev/null +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include +#include + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + npu-binary@84000000 { + no-map; + reg = <0x0 0x84000000 0x0 0xa00000>; + }; + + npu-flag@84b0000 { + no-map; + reg = <0x0 0x84b00000 0x0 0x100000>; + }; + + npu-pkt@85000000 { + no-map; + reg = <0x0 0x85000000 0x0 0x1a00000>; + }; + + npu-phyaddr@86b00000 { + no-map; + reg = <0x0 0x86b00000 0x0 0x100000>; + }; + + npu-rxdesc@86d00000 { + no-map; + reg = <0x0 0x86d00000 0x0 0x100000>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@9000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x09000000 0x0 0x20000>, + <0x0 0x09080000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x2000>, + <0x0 0x09500000 0x0 0x2000>, + <0x0 0x09600000 0x0 0x20000>; + interrupts = ; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x0 0x1fbf0000 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clock-frequency = <1843200>; + }; + }; +}; -- cgit From 85f9e6c303600dc887ea05de7b54240b040c859d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 13 Mar 2024 15:15:37 +0100 Subject: arm64: dts: mediatek: Complete chassis-type for MT8183 Chromebooks Define the chassis type on the remaining MT8183 Chromebooks. Link: https://lore.kernel.org/r/20240313141538.1438167-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts | 1 + arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts | 1 + 11 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts index 072133fb0f01..f34964afe39b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts @@ -9,6 +9,7 @@ / { model = "Google cozmo board"; + chassis-type = "laptop"; compatible = "google,cozmo", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index b595622e7bee..72852b760038 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -9,6 +9,7 @@ / { model = "Google fennel sku1 board"; + chassis-type = "convertible"; compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183"; pwmleds { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts index 5a1c39318a6c..757d0afd14fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts @@ -9,6 +9,7 @@ / { model = "Google fennel sku6 board"; + chassis-type = "convertible"; compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts index 3ea4fdb40118..6641b087e7c5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts @@ -9,6 +9,7 @@ / { model = "Google fennel sku7 board"; + chassis-type = "convertible"; compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts index 3fc5a6181d7e..877256eab262 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts @@ -9,6 +9,7 @@ / { model = "Google fennel14 sku2 board"; + chassis-type = "laptop"; compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts index 23ad0b91e977..b981dd31a430 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts @@ -9,6 +9,7 @@ / { model = "Google fennel14 sku0 board"; + chassis-type = "laptop"; compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts index e5bd9191e426..f3ac9c074226 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts @@ -9,6 +9,7 @@ / { model = "Google kappa board"; + chassis-type = "laptop"; compatible = "google,kappa", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts index 8fa89db03e63..e8241587949b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts @@ -9,5 +9,6 @@ / { model = "Google kenzo sku17 board"; + chassis-type = "laptop"; compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts index 89208b843b27..928b205a616a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts @@ -9,6 +9,7 @@ / { model = "Google willow board sku0"; + chassis-type = "laptop"; compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts index c7b20441d053..71307a8052d6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts @@ -9,5 +9,6 @@ / { model = "Google willow board sku1"; + chassis-type = "laptop"; compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts index 7739358008ee..5a416143b4a0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts @@ -12,6 +12,7 @@ / { model = "MediaTek kodama sku32 board"; + chassis-type = "tablet"; compatible = "google,kodama-sku32", "google,kodama", "mediatek,mt8183"; }; -- cgit From 42aa8daecd80d18bc12c43d7be6fd82c6fd526a1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 13 Mar 2024 15:15:38 +0100 Subject: arm64: dts: mediatek: Add missing chassis-type to MT8192 Chromebooks None of the MT8192 Chromebooks had their chassis-type specified: add the right definition for each. Reviewed-by: David Heidelberg Link: https://lore.kernel.org/r/20240313141538.1438167-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts | 1 + arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts | 1 + arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts | 1 + arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts | 1 + 4 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts index fd2cb8765a15..ac2673e56fb8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -7,6 +7,7 @@ / { model = "Google Hayato rev1"; + chassis-type = "convertible"; compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts index 3127ee5f6172..cd86ad9ba28a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts @@ -7,6 +7,7 @@ / { model = "Google Hayato rev5"; + chassis-type = "convertible"; compatible = "google,hayato-rev5-sku2", "google,hayato-sku2", "google,hayato", "mediatek,mt8192"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index bc88866ab2f5..29aa87e93888 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -8,6 +8,7 @@ / { model = "Google Spherion (rev0 - 3)"; + chassis-type = "laptop"; compatible = "google,spherion-rev3", "google,spherion-rev2", "google,spherion-rev1", "google,spherion-rev0", "google,spherion", "mediatek,mt8192"; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts index 0039158c9e60..5e9e598bab90 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts @@ -8,6 +8,7 @@ / { model = "Google Spherion (rev4)"; + chassis-type = "laptop"; compatible = "google,spherion-rev4", "google,spherion", "mediatek,mt8192"; -- cgit From b376befe9c8897780dc7a92fca76f79b5053f8a1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Fri, 22 Mar 2024 10:28:42 +0100 Subject: dt-bindings: soc: mediatek: Add support for MT8188 VPPSYS Add compatible for MT8188 VPP mutex, having different bits to activate mute for various hardware IPs. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240322092845.381313-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index ba2014a8725c..a10326a9683d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt8186-disp-mutex - mediatek,mt8186-mdp3-mutex - mediatek,mt8188-disp-mutex + - mediatek,mt8188-vpp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex - mediatek,mt8195-vpp-mutex -- cgit From 09346afaba0a89652da38966293ad321e2170a90 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 13 Feb 2024 14:00:44 +0100 Subject: arm64: dts: mediatek: mt7988: add XHCI controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add bindings of two on-SoC XHCI controllers. Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240213130044.1976-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 32 ++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index bba97de4fb44..3eb5396dea22 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT +#include #include +#include / { compatible = "mediatek,mt7988a"; @@ -78,7 +80,7 @@ #interrupt-cells = <3>; }; - clock-controller@10001000 { + infracfg: clock-controller@10001000 { compatible = "mediatek,mt7988-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; @@ -103,6 +105,34 @@ #clock-cells = <1>; }; + usb@11190000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, + <0 0x11193e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_USB_SYS>, + <&infracfg CLK_INFRA_USB_REF>, + <&infracfg CLK_INFRA_66M_USB_HCK>, + <&infracfg CLK_INFRA_133M_USB_HCK>, + <&infracfg CLK_INFRA_USB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + }; + + usb@11200000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, + <&infracfg CLK_INFRA_USB_CK_P1>, + <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + }; + clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; -- cgit From 8f5a9d6b304a6599d5dfb315bb0b0de9edf5dce0 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Wed, 21 Feb 2024 09:55:47 +0100 Subject: arm64: dts: mediatek: mt7981: add watchdog & WiFi controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7981 (Filogic 820) is a low cost version of MT7986 (Filogic 830) with the same watchdog controller. It also comes with on-SoC 802.11ax wireless. Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240221085547.27840-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 95c6fe888083..5674ac81d1f8 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ #include #include +#include / { compatible = "mediatek,mt7981b"; @@ -62,12 +63,19 @@ #clock-cells = <1>; }; - clock-controller@1001b000 { + topckgen: clock-controller@1001b000 { compatible = "mediatek,mt7981-topckgen", "syscon"; reg = <0 0x1001b000 0 0x1000>; #clock-cells = <1>; }; + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + }; + clock-controller@1001e000 { compatible = "mediatek,mt7981-apmixedsys"; reg = <0 0x1001e000 0 0x1000>; @@ -114,6 +122,22 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + wifi@18000000 { + compatible = "mediatek,mt7981-wmac"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; + interrupts = , + , + , + ; + clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; + }; }; timer { -- cgit From 341e4a070dc288ca6c2f3e47db23c112b7bdd0bd Mon Sep 17 00:00:00 2001 From: Macpaul Lin Date: Fri, 15 Sep 2023 16:12:11 +0800 Subject: dt-bindings: arm64: mediatek: add mt8390-evk board 1. Add compatible for MT8390. 2. Add bindings for the MediaTek mt8390-evk board, also known as the "Genio 700-EVK". The MT8390 and MT8188 belong to the same SoC family, with only minor differences in their physical characteristics. They utilize unique efuse values for differentiation. The booting process and configurations are managed by boot loaders, firmware, and TF-A. Consequently, the part numbers and procurement channels vary. Signed-off-by: Macpaul Lin Reviewed-by: Krzysztof Kozlowski Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230915081212.13959-1-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 1cf47db94c57..d986b160fed1 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -352,6 +352,11 @@ properties: - enum: - mediatek,mt8365-evk - const: mediatek,mt8365 + - items: + - enum: + - mediatek,mt8390-evk + - const: mediatek,mt8390 + - const: mediatek,mt8188 - items: - enum: - mediatek,mt8395-evk -- cgit From 7982bf7ec2e378bd60b8d785e379de0af85fecf1 Mon Sep 17 00:00:00 2001 From: Macpaul Lin Date: Fri, 15 Sep 2023 16:12:12 +0800 Subject: arm64: dts: mediatek: add device-tree for Genio 700 EVK board Add basic device-tree for the Genio 700 EVK board. The Genio 700 EVK is based on MediaTek MT8390 SoC. MT8390 hardware register maps are identical to MT8188. The Genio 700 EVK has following features: - MT8390 SoC - MT6365 PMIC - MT6319 Buck IC - 12V DC Jack - 2x4GB LPDDR4X - 64GB eMMC 5.1 - 64Mb SPI NOR - M.2 Key A-E slot with PCIe Gen2 and USB 2.0 - 2x DSI LCM ports - 2x touch sensor ports - 2x MIPI-CSI, as camera daughter board slots - USB 2 micro USB connector - USB 3 with 1 to 2 hub: - M.2 Key B slot - Type-C connector, with DisplayPort over Type-C - HDMI 2.0 TX port with Type A HDMI connector - eDP port - Gigabit Ethernet with RJ45 connector - SD card slot - Earphone Jack - Analog Microphone - 2x Digital Microphone - 3x UART with serial-to-usb converters and micro USB connectors Signed-off-by: Chris-QJ Chen Signed-off-by: Pablo Sun Signed-off-by: Macpaul Lin Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20230915081212.13959-2-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../boot/dts/mediatek/mt8390-genio-700-evk.dts | 880 +++++++++++++++++++++ 2 files changed, 881 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 96da4ad640aa..cae5fcc7ca0c 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -77,5 +77,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts new file mode 100644 index 000000000000..6bb1d5d112ef --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -0,0 +1,880 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Chris Chen + * Pablo Sun + * Macpaul Lin + */ +/dts-v1/; + +#include "mt8188.dtsi" +#include "mt6359.dtsi" +#include +#include +#include +#include +#include +#include +#include + +/ { + model = "MediaTek Genio-700 EVK"; + compatible = "mediatek,mt8390-evk", "mediatek,mt8390", + "mediatek,mt8188"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x2 0x00000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible = "shared-dma-pool"; + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + }; + + common_fixed_5v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "5v_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + edp_panel_fixed_3v3: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "edp_panel_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_3v3_en_pins>; + }; + + gpio_fixed_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "gpio_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sdio_fixed_1v8: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "sdio_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + }; + + sdio_fixed_3v3: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "sdio_card"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + touch0_fixed_3v3: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "touch_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_hub_fixed_3v3: regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "usb_hub_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 112 GPIO_ACTIVE_HIGH>; /* HUB_3V3_EN */ + startup-delay-us = <10000>; + enable-active-high; + }; + + usb_hub_reset_1v8: regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "usb_hub_reset"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 7 GPIO_ACTIVE_HIGH>; /* HUB_RESET */ + vin-supply = <&usb_hub_fixed_3v3>; + }; + + usb_p0_vbus: regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "usb_p0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p1_vbus: regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "usb_p1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 87 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p2_vbus: regulator-10 { + compatible = "regulator-fixed"; + regulator-name = "usb_p2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt9271"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&touch0_fixed_3v3>; + VDDIO-supply = <&mt6359_vio18_ldo_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&rt1715_int_pins>; + clock-frequency = <1000000>; + status = "okay"; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x1481b>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + no-sdio; + cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mt6359_vpa_buck_reg>; + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-max-microvolt = <3100000>; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-enable-ramp-delay = <480>; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&mt6359codec { + mediatek,mic-type-0 = <1>; /* ACC */ + mediatek,mic-type-1 = <3>; /* DCC */ +}; + +&pio { + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + dptx_pins: dptx-pins { + pins-cmd-dat { + pinmux = ; + bias-pull-up; + }; + }; + + edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { + pins1 { + pinmux = ; + output-high; + }; + }; + + eth_default_pins: eth-default-pins { + pins-cc { + pinmux = , + , + , + ; + drive-strength = ; + }; + + pins-mdio { + pinmux = , + ; + drive-strength = ; + input-enable; + }; + + pins-power { + pinmux = , + ; + output-high; + }; + + pins-rxd { + pinmux = , + , + , + ; + drive-strength = ; + }; + + pins-txd { + pinmux = , + , + , + ; + drive-strength = ; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-txd { + pinmux = , + , + , + ; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c5_pins: i2c5-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + gpio_key_pins: gpio-key-pins { + pins { + pinmux = , + , + ; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc2_default_pins: mmc2-default-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-pcm { + pinmux = ; + }; + }; + + mmc2_uhs_pins: mmc2-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + mmc2_eint_pins: mmc2-eint-pins { + pins-dat1 { + pinmux = ; + input-enable; + bias-pull-up = ; + }; + }; + + mmc2_dat1_pins: mmc2-dat1-pins { + pins-dat1 { + pinmux = ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + panel_default_pins: panel-default-pins { + pins-dcdc { + pinmux = ; + output-low; + }; + + pins-en { + pinmux = ; + output-low; + }; + + pins-rst { + pinmux = ; + output-high; + }; + }; + + rt1715_int_pins: rt1715-int-pins { + pins_cmd0_dat { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + spi0_pins: spi0-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi1_pins: spi1-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + spi2_pins: spi2-pins { + pins-spi { + pinmux = , + , + , + ; + bias-disable; + }; + }; + + touch_pins: touch-pins { + pins-irq { + pinmux = ; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux = ; + output-high; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + bias-pull-up; + }; + }; + + usb_default_pins: usb-default-pins { + pins-iddig { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-valid { + pinmux = ; + input-enable; + }; + + pins-vbus { + pinmux = ; + output-high; + }; + + }; + + usb1_default_pins: usb1-default-pins { + pins-valid { + pinmux = ; + input-enable; + }; + + pins-usb-hub-3v3-en { + pinmux = ; + output-high; + }; + }; + + wifi_pwrseq_pins: wifi-pwrseq-pins { + pins-wifi-enable { + pinmux = ; + output-low; + }; + }; +}; + +&pmic { + interrupt-parent = <&pio>; + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi2 { + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&xhci0 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; +}; + +&xhci1 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_hub_reset_1v8>; +}; + +&xhci2 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; +}; -- cgit From b2b6f2edb82a08abe8942535bc77da55a0f43e14 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 10 Apr 2024 10:30:00 +0200 Subject: arm64: dts: mediatek: mt8195: Fix GPU thermal zone name for SVS This SoC has two GPU related thermal zones: the primary zone must be called "gpu-thermal" for SVS to pick it up. Fixes: 1e5b6725199f ("arm64: dts: mediatek: mt8195: Add AP domain thermal zones") Link: https://lore.kernel.org/r/20240410083002.1357857-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d8b68f86ce4..2ee45752583c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3880,7 +3880,7 @@ }; }; - gpu0-thermal { + gpu-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; -- cgit From 86beeec5dd2b8e28217f67815a3fb15752031667 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 10 Apr 2024 10:30:01 +0200 Subject: arm64: dts: mediatek: mt8192: Fix GPU thermal zone name for SVS This SoC has two GPU related thermal zones: the primary zone must be called "gpu-thermal" for SVS to pick it up. Fixes: c7a728051f4e ("arm64: dts: mediatek: mt8192: Add thermal nodes and thermal zones") Link: https://lore.kernel.org/r/20240410083002.1357857-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 84cbdf6e9eb0..47dea10dd3b8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -2234,7 +2234,7 @@ }; }; - gpu0-thermal { + gpu-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8192_AP_GPU0>; -- cgit From 4a5191c5dd28c9016600af5e4be1db3a74791ab1 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Wed, 10 Apr 2024 10:30:02 +0200 Subject: arm64: dts: mediatek: mt8183: Refactor thermal zones The thermal zones in MT8183 had cryptic names and all of them, apart from the cpu-thermal zone, had no thermal trips, hence those were not probed at all. Refactor the tzts1..5 and tztsABB thermal zones to add the correct thermal trips and give them a meaningful name, corresponding to the actually monitored thermal zone. While at it, also rename the thermal sensor node to "thermal-sensor". Now the thermal zones are probing and their temperatures can be read. Fixes: b325ce39785b ("arm64: dts: mt8183: add thermal zone node") Link: https://lore.kernel.org/r/20240410083002.1357857-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 136 +++++++++++++++++++++++-------- 1 file changed, 102 insertions(+), 34 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 774ae5d9143f..fbf145639b8c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1183,7 +1183,7 @@ status = "disabled"; }; - thermal: thermal@1100b000 { + thermal: thermal-sensor@1100b000 { #thermal-sensor-cells = <1>; compatible = "mediatek,mt8183-thermal"; reg = <0 0x1100b000 0 0xc00>; @@ -2090,61 +2090,129 @@ }; }; - /* The tzts1 ~ tzts6 don't need to polling */ - /* The tzts1 ~ tzts6 don't need to thermal throttle */ - - tzts1: tzts1 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts1: soc-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 1>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + trips { + soc_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts2: tzts2 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts2: gpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 2>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + gpu_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts3: tzts3 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts3: md1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 3>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + md1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + md1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts4: tzts4 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts4: cpu-little-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 4>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + cpul_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpul_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts5: tzts5 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts5: cpu-big-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 5>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + cpub_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpub_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tztsABB: tztsABB { - polling-delay-passive = <0>; - polling-delay = <0>; + tztsABB: tsabb-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 6>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + tsabb_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + tsabb_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; }; -- cgit From 32b33be8894f3389d15b409140d663acbdf9de1d Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 9 Apr 2024 13:42:08 +0200 Subject: arm64: dts: medaitek: mt8395-nio-12l: Set i2c6 pins to bias-disable GPIOs 25 and 26 do not support pull-up/pull-down when those are muxed as I2C6's SDA6/SCL6 lines: set those to bias-disable to avoid warning messages from the pinctrl driver. Fixes: 96564b1e2ea4 ("arm64: dts: mediatek: Introduce the MT8395 Radxa NIO 12L board") Link: https://lore.kernel.org/r/20240409114211.310462-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index e5d9b671a405..97634cc04e65 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -528,7 +528,7 @@ pins { pinmux = , ; - bias-pull-up = ; + bias-disable; }; }; -- cgit From 048a70e3141a660d116bb86fe7e158235a9c4656 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 9 Apr 2024 13:42:09 +0200 Subject: arm64: dts: mediatek: mt8395-nio-12l: Define RSEL in microamperes The paris pinctrl driver supports specifying the RSEL drive strength in microamperes as well as internal bits definitions: choose to specify those in uA to avoid using hardware specific values in device trees. Link: https://lore.kernel.org/r/20240409114211.310462-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index 97634cc04e65..abd6612b8624 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -434,6 +434,8 @@ }; &pio { + mediatek,rsel-resistance-in-si-unit; + eth_default_pins: eth-default-pins { pins-cc { pinmux = , @@ -509,7 +511,7 @@ pins-bus { pinmux = , ; - bias-pull-up = ; + bias-pull-up = <1000>; drive-strength = <6>; drive-strength-microamp = <1000>; }; @@ -519,7 +521,7 @@ pins-bus { pinmux = , ; - bias-pull-up = ; + bias-pull-up = <1000>; drive-strength-microamp = <1000>; }; }; -- cgit From 9af42385908bb4c33adf9f39af51ba269dbf9882 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 9 Apr 2024 13:42:10 +0200 Subject: arm64: dts: mediatek: mt8395-nio-12l: Enable PHYs and USB role switch Enable the PCIe0 PHY to be able to set calibrations read from eFuses, improving the stability and performance of the PCIe link. While at it, also enable the T-PHYs for both PCIe1 and for USB, allowing the USB ports to finally switch to gadget mode if needed, and configure the VBUS/ID pins of both USB ports for the same. Link: https://lore.kernel.org/r/20240409114211.310462-5-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index abd6612b8624..dfd0cbd71607 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -685,6 +685,26 @@ }; }; + usb3_port0_pins: usb3p0-default-pins { + pins-vbus { + pinmux = ; + input-enable; + }; + }; + + usb2_port0_pins: usb2p0-default-pins { + pins-iddig { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-vbus { + pinmux = ; + output-low; + }; + }; + wifi_vreg_pins: wifi-vreg-pins { pins-wifi-pmu-en { pinmux = ; @@ -709,6 +729,10 @@ status = "okay"; }; +&pciephy { + status = "okay"; +}; + &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; @@ -776,6 +800,18 @@ }; }; +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + &uart0 { /* Exposed at 40 pin connector */ pinctrl-0 = <&uart0_pins>; @@ -791,6 +827,8 @@ }; &ssusb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb3_port0_pins>; role-switch-default-mode = "host"; usb-role-switch; vusb33-supply = <&mt6359_vusb_ldo_reg>; @@ -804,6 +842,8 @@ }; &ssusb2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_port0_pins>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; -- cgit From 7ca7bbd28983e640c7b58e231d69911a84f5ec8a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 9 Apr 2024 13:42:11 +0200 Subject: arm64: dts: mediatek: mt8395-nio-12l: Add power supplies for CPU/GPU scaling Add the necessary power supplies to safely enable CPU and GPU frequency scaling. Link: https://lore.kernel.org/r/20240409114211.310462-6-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8395-radxa-nio-12l.dts | 40 ++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index dfd0cbd71607..4b5f6cf16f70 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -140,6 +140,38 @@ }; }; +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu4 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu5 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu6 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + ð { phy-mode = "rgmii-rxid"; phy-handle = <&rgmii_phy>; @@ -343,6 +375,14 @@ }; }; +&mfg0 { + domain-supply = <&mt6315_7_vbuck1>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + /* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */ &mmc0 { pinctrl-names = "default", "state_uhs"; -- cgit From e9a9055fdcdc1e5a27cef118c5b4f09cdd2fa28e Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Apr 2024 15:56:12 +0800 Subject: arm64: dts: mediatek: mt8183-kukui: Drop bogus output-enable property The "output-enable" property is set on uart1's RTS pin. This is bogus because the hardware does not actually have a controllable output buffer. Secondly, the implementation incorrectly treats this property as a request to switch the pin to GPIO output. This does not fit the intended semantic of "output-enable" and it does not have any affect either because the pin is muxed to the UART function, not the GPIO function. Drop the property. Fixes: cd894e274b74 ("arm64: dts: mt8183: Add krane-sku176 board") Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20240412075613.1200048-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 100191c6453b..feb8a5acf2cd 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -803,7 +803,6 @@ }; pins-rts { pinmux = ; - output-enable; }; pins-cts { pinmux = ; @@ -822,7 +821,6 @@ }; pins-rts { pinmux = ; - output-enable; }; pins-cts { pinmux = ; -- cgit From 27f0974a982998d59c645489da9dd99e4c6bafb2 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Fri, 12 Apr 2024 15:55:14 +0800 Subject: arm64: dts: mediatek: Drop mediatek,drive-strength-adv usage The "mediatek,drive-strength-adv" pin config property has been deprecated in favor of the generic "drive-strength-microamp" property. Drop or convert all instances. A value of 0 disables the advanced mode, which is the hardware default. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20240412075516.1199846-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-evb.dts | 6 ------ arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 6 ------ arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 6 ------ arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 4 +--- 4 files changed, 1 insertion(+), 21 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 681deddffc2a..f04baea5d6cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -160,7 +160,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -169,7 +168,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -178,7 +176,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -187,7 +184,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -196,7 +192,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -205,7 +200,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index feb8a5acf2cd..5472cd0be63a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -533,7 +533,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -542,7 +541,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -551,7 +549,6 @@ pinmux = , ; bias-disable; - mediatek,drive-strength-adv = <00>; }; }; @@ -560,7 +557,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -569,7 +565,6 @@ pinmux = , ; bias-disable; - mediatek,drive-strength-adv = <00>; }; }; @@ -578,7 +573,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 333c516af490..81f6c205fa98 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -197,7 +197,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -206,7 +205,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -215,7 +213,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -224,7 +221,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -233,7 +229,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -242,7 +237,6 @@ pinmux = , ; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index 341b6e074139..83456d649ff7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -74,7 +74,6 @@ pinmux = , ; bias-pull-up = ; - mediatek,drive-strength-adv = <0>; drive-strength = <6>; }; }; @@ -84,7 +83,6 @@ pinmux = , ; bias-pull-up = ; - mediatek,drive-strength-adv = <0>; drive-strength = <6>; }; }; @@ -94,7 +92,7 @@ pinmux = , ; bias-pull-up = ; - mediatek,drive-strength-adv = <7>; + drive-strength-microamp = <1000>; }; }; -- cgit From 87728e3ccf352dd9fd482f894e73d12102bf9014 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 16 Apr 2024 09:14:09 +0200 Subject: arm64: dts: mediatek: mt8195-cherry: Specify sound DAI links and routing The drivers and bindings acquired support for specifying audio hardware and links in device tree: describe and link the sound related HW of this machine. Link: https://lore.kernel.org/r/20240416071410.75620-18-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 45 +++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 4a11918da370..e35adff02469 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -240,6 +240,7 @@ spk_amplifier: rt1019p { compatible = "realtek,rt1019p"; label = "rt1019p"; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&rt1019p_pins_default>; sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; @@ -366,6 +367,7 @@ &dp_tx { status = "okay"; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&dptx_pin>; @@ -436,6 +438,7 @@ /* Realtek RT5682i or RT5682s, sharing the same configuration */ reg = <0x1a>; interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>; + #sound-dai-cells = <0>; realtek,jd-src = <1>; AVDD-supply = <&mt6359_vio18_ldo_reg>; @@ -1162,6 +1165,48 @@ "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5"; pinctrl-names = "default"; pinctrl-0 = <&aud_pins_default>; + + audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "IN1P", "Headset Mic", + "Ext Spk", "Speaker"; + + mm-dai-link { + link-name = "ETDM1_IN_BE"; + mediatek,clk-provider = "cpu"; + }; + + hs-playback-dai-link { + link-name = "ETDM1_OUT_BE"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&audio_codec>; + }; + }; + + hs-capture-dai-link { + link-name = "ETDM2_IN_BE"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&audio_codec>; + }; + }; + + spk-playback-dai-link { + link-name = "ETDM2_OUT_BE"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&spk_amplifier>; + }; + }; + + displayport-dai-link { + link-name = "DPTX_BE"; + codec { + sound-dai = <&dp_tx>; + }; + }; }; &spi0 { -- cgit From 458d92b55b87d2586d586f1e9ab010ce068dd14c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Tue, 16 Apr 2024 09:14:10 +0200 Subject: arm64: dts: mediatek: mt8186-corsola: Specify sound DAI links and routing The drivers and bindings acquired support for specifying audio hardware and links in device tree: describe and link the sound related HW of this machine. Link: https://lore.kernel.org/r/20240416071410.75620-19-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi | 42 +++++++++++++++++++++--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi index 1807e9d6cb0e..afdab5724eaa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi @@ -42,7 +42,7 @@ default-brightness-level = <576>; }; - bt-sco-codec { + bt-sco { compatible = "linux,bt-sco"; #sound-dai-cells = <0>; }; @@ -223,12 +223,44 @@ mediatek,adsp = <&adsp>; mediatek,platform = <&afe>; - playback-codecs { - sound-dai = <&it6505dptx>, <&rt1019p>; + audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "IN1P", "Headset Mic", + "Speakers", "Speaker", + "HDMI1", "TX"; + + hs-playback-dai-link { + link-name = "I2S0"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&rt5682s 0>; + }; + }; + + hs-capture-dai-link { + link-name = "I2S1"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&rt5682s 0>; + }; }; - headset-codec { - sound-dai = <&rt5682s 0>; + spk-share-dai-link { + link-name = "I2S2"; + mediatek,clk-provider = "cpu"; + }; + + spk-hdmi-playback-dai-link { + link-name = "I2S3"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + /* RT1019P and IT6505 connected to the same I2S line */ + codec { + sound-dai = <&it6505dptx>, <&rt1019p>; + }; }; }; -- cgit From a43bf5bebd24e7bb5fc1b47f8c95d1a52378fc8a Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 14 Mar 2024 11:34:59 +0100 Subject: dt-bindings: arm: mediatek: Add MT8195 HP Chromebook x360 13b-ca0002sa Add the MT8195 Cherry platform's Dojo machine, a convertible design commercially known as the HP Chromebook x360 (13b-ca0002sa). Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240314103500.93158-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index d986b160fed1..e93d23849353 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -343,6 +343,14 @@ properties: - const: google,tomato-rev3 - const: google,tomato - const: mediatek,mt8195 + - description: HP Dojo sku1, 3, 5, 7 (HP Chromebook x360 13b-ca0002sa) + items: + - const: google,dojo-sku7 + - const: google,dojo-sku5 + - const: google,dojo-sku3 + - const: google,dojo-sku1 + - const: google,dojo + - const: mediatek,mt8195 - items: - enum: - mediatek,mt8195-demo -- cgit From 52b7afd5b9afa96b36633256abebd995872f1c76 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 14 Mar 2024 11:35:00 +0100 Subject: arm64: mediatek: mt8195-cherry: Introduce the MT8195 Dojo Chromebook Add a devicetree for the Cherry Dojo (HP Chromebook x360 13b-ca0002sa) convertible type machine. Differences with the already supported Tomato machines include: - Different speaker amplifiers (Dual MAX98380, one per channel) - I2C Touchscreen is on a different address (though still a HID device) - Has NVMe storage on the PCIe0 controller - Slightly different keyboard top row keymap Link: https://lore.kernel.org/r/20240314103500.93158-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../boot/dts/mediatek/mt8195-cherry-dojo-r1.dts | 114 +++++++++++++++++++++ arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi | 5 + 3 files changed, 120 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index cae5fcc7ca0c..3542e42acfff 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -70,6 +70,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r5-sku2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r4.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-dojo-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts new file mode 100644 index 000000000000..88123842c818 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model = "HP Dojo (sku 1, 3, 5, 7) board"; + chassis-type = "convertible"; + compatible = "google,dojo-sku7", "google,dojo-sku5", + "google,dojo-sku3", "google,dojo-sku1", + "google,dojo", "mediatek,mt8195"; +}; + +&audio_codec { + compatible = "realtek,rt5682s"; + realtek,amic-delay-ms = <250>; +}; + +&i2c2 { + spk_r_amp: amplifier@38 { + compatible = "maxim,max98390"; + reg = <0x38>; + reset-gpios = <&pio 100 GPIO_ACTIVE_LOW>; + sound-name-prefix = "Right"; + #sound-dai-cells = <0>; + }; + + spk_l_amp: amplifier@39 { + compatible = "maxim,max98390"; + reg = <0x39>; + sound-name-prefix = "Left"; + #sound-dai-cells = <0>; + }; +}; + +&i2c4 { + touchscreen@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + hid-descr-addr = <0x0001>; + interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + post-power-on-delay-ms = <10>; + vdd-supply = <&pp3300_s3>; + }; +}; + +&keyboard_controller { + linux,keymap = < + CROS_STD_MAIN_KEYMAP + + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_KBDILLUMTOGGLE) + MATRIX_KEY(0x01, 0x09, KEY_PLAYPAUSE) + MATRIX_KEY(0x00, 0x04, KEY_MICMUTE) + MATRIX_KEY(0x00, 0x01, KEY_MUTE) + MATRIX_KEY(0x01, 0x05, KEY_VOLUMEDOWN) + MATRIX_KEY(0x03, 0x05, KEY_VOLUMEUP) + >; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins_default>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pio_default { + pins-low-power-hdmi-disable { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-down; + }; +}; + +&sound { + compatible = "mediatek,mt8195_mt6359_max98390_rt5682"; + model = "m8195_m98390_5682s"; + + audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "IN1P", "Headset Mic", + "Right Spk", "Right BE_OUT", + "Left Spk", "Left BE_OUT"; + + spk-playback-dai-link { + codec { + sound-dai = <&spk_r_amp>, <&spk_l_amp>; + }; + }; +}; + +&spk_amplifier { + /* Disable RT1019P, not present on Dojo */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index e35adff02469..fe5400e17b0f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -1434,6 +1434,11 @@ MATRIX_KEY(0x02, 0x09, 0) /* T8 */ MATRIX_KEY(0x01, 0x09, 0) /* T9 */ MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + + /* T11 to T13 are present only on Dojo */ + MATRIX_KEY(0x00, 0x01, 0) /* T11 */ + MATRIX_KEY(0x01, 0x05, 0) /* T12 */ + MATRIX_KEY(0x03, 0x05, 0) /* T13 */ >; linux,keymap = < -- cgit From 666e6f39faff05fe12bfc64c64aa9015135ce783 Mon Sep 17 00:00:00 2001 From: Macpaul Lin Date: Fri, 16 Feb 2024 17:57:51 +0800 Subject: arm64: dts: mediatek: mt8395-genio-1200-evk: add u3port1 for xhci1 This patch fixes an issue where xhci1 was not functioning properly because the state and PHY settings were incorrect. The introduction of the 'force-mode' property in the phy-mtk-tphy driver allows for the correct initialization of xhci1 by updating the Device Tree settings accordingly. The necessary fixup which added support for the 'force-mode' switch in the phy-mtk-tphy driver. commit 9b27303003f5 ("phy: mediatek: tphy: add support force phy mode switch") Link: https://lore.kernel.org/r/20231211025624.28991-2-chunfeng.yun@mediatek.com Prior to this fix, the system would exhibit the following probe failure messages for xhci1: xhci-mtk 11290000.usb: supply vbus not found, using dummy regulator xhci-mtk 11290000.usb: uwk - reg:0x400, version:104 xhci-mtk 11290000.usb: xHCI Host Controller xhci-mtk 11290000.usb: new USB bus registered, assigned bus number 5 xhci-mtk 11290000.usb: clocks are not stable (0x1003d0f) xhci-mtk 11290000.usb: can't setup: -110 xhci-mtk 11290000.usb: USB bus 5 deregistered xhci-mtk: probe of 11290000.usb failed with error -110 With the application of this dts fixup, the aforementioned initialization errors are resolved and xhci1 is working. Signed-off-by: Macpaul Lin Link: https://lore.kernel.org/r/20240216095751.4937-1-macpaul.lin@mediatek.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts index 1558649f633c..a1b613808780 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -854,6 +854,10 @@ &u3phy1 { status = "okay"; + + u3port1: usb-phy@700 { + mediatek,force-mode; + }; }; &u3phy2 { @@ -900,6 +904,8 @@ }; &xhci1 { + phys = <&u2port1 PHY_TYPE_USB2>, + <&u3port1 PHY_TYPE_USB3>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; -- cgit From 1b4472430f659369694fe7483995fd39c8d543b6 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 8 Apr 2024 10:08:15 +0200 Subject: dt-bindings: arm64: mediatek: add Kontron 3.5"-SBC-i1200 Add the compatible string for the Kontron 3.5"-SBC-i1200 single board computer. Signed-off-by: Michael Walle Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240408080816.4134370-1-mwalle@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index e93d23849353..eccc3f7cc4e6 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -367,6 +367,7 @@ properties: - const: mediatek,mt8188 - items: - enum: + - kontron,3-5-sbc-i1200 - mediatek,mt8395-evk - radxa,nio-12l - const: mediatek,mt8395 -- cgit From 94aaf79a6af5d64bad9f6de72a241722a1d8b9df Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Mon, 8 Apr 2024 10:08:16 +0200 Subject: arm64: dts: mediatek: add Kontron 3.5"-SBC-i1200 Add basic support for the Kontron 3.5" single board computer featuring a Mediatek i1200 SoC (MT8395/MT8195). Signed-off-by: Michael Walle Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240408080816.4134370-2-mwalle@kernel.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts | 1127 ++++++++++++++++++++ 2 files changed, 1128 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 3542e42acfff..12f67959f257 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -79,5 +79,6 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts new file mode 100644 index 000000000000..e4b2af9489a8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts @@ -0,0 +1,1127 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Kontron Europe GmbH + * + * Author: Michael Walle + */ +/dts-v1/; + +#include "mt8195.dtsi" +#include "mt6359.dtsi" + +#include +#include +#include +#include +#include +#include + +/ { + model = "Kontron 3.5\"-SBC-i1200"; + compatible = "kontron,3-5-sbc-i1200", "mediatek,mt8395", "mediatek,mt8195"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-0 { + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-0 { + gpios = <&pio 107 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + function = LED_FUNCTION_POWER; + color = ; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x0 0x80000000>; + }; + + vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + vpu_mem: memory@53000000 { + compatible = "shared-dma-pool"; + reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_mem: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + snd_dma_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0x1100000>; + no-map; + }; + + apu_mem: memory@62000000 { + compatible = "shared-dma-pool"; + reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ + }; + }; + + thermal_sensor0: thermal-sensor-0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = <(-25000) 1474 + (-20000) 1374 + (-15000) 1260 + (-10000) 1134 + (-5000) 1004 + 0 874 + 5000 750 + 10000 635 + 15000 532 + 20000 443 + 25000 367 + 30000 303 + 35000 250 + 40000 206 + 45000 170 + 50000 141 + 55000 117 + 60000 97 + 65000 81 + 70000 68 + 75000 57 + 80000 48 + 85000 41 + 90000 35 + 95000 30 + 100000 25 + 105000 22 + 110000 19 + 115000 16 + 120000 14 + 125000 12 + 130000 10 + 135000 9 + 140000 8 + 145000 7 + 150000 6>; + }; + + thermal_sensor1: thermal-sensor-1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 1>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = <(-25000) 1474 + (-20000) 1374 + (-15000) 1260 + (-10000) 1134 + (-5000) 1004 + 0 874 + 5000 750 + 10000 635 + 15000 532 + 20000 443 + 25000 367 + 30000 303 + 35000 250 + 40000 206 + 45000 170 + 50000 141 + 55000 117 + 60000 97 + 65000 81 + 70000 68 + 75000 57 + 80000 48 + 85000 41 + 90000 35 + 95000 30 + 100000 25 + 105000 22 + 110000 19 + 115000 16 + 120000 14 + 125000 12 + 130000 10 + 135000 9 + 140000 8 + 145000 7 + 150000 6>; + }; + + thermal_sensor2: thermal-sensor-2 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 2>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = <(-25000) 1474 + (-20000) 1374 + (-15000) 1260 + (-10000) 1134 + (-5000) 1004 + 0 874 + 5000 750 + 10000 635 + 15000 532 + 20000 443 + 25000 367 + 30000 303 + 35000 250 + 40000 206 + 45000 170 + 50000 141 + 55000 117 + 60000 97 + 65000 81 + 70000 68 + 75000 57 + 80000 48 + 85000 41 + 90000 35 + 95000 30 + 100000 25 + 105000 22 + 110000 19 + 115000 16 + 120000 14 + 125000 12 + 130000 10 + 135000 9 + 140000 8 + 145000 7 + 150000 6>; + }; +}; + +&auxadc { + status = "okay"; +}; + +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + + mdio { + ethernet_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + interrupts-extended = <&pio 94 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pio 93 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpu { + status = "okay"; + mali-supply = <&mt6315_7_vbuck1>; +}; + +/* CSI1/CSI2 connector */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +/* CSI3 connector */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; + + /* LVDS bridge @f */ +}; + +/* Touch panel connector */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +/* B2B connector */ +&i2c4 { + clock-frequency = <100000>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-controller; + interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + #interrupt-cells = <1>; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN1-supply = <&vsys>; + LDO_VIN2-supply = <&vsys>; + LDO_VIN3-supply = <&vsys>; + + mt6360_buck1: BUCK1 { + regulator-name = "emi_vdd2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_buck2: BUCK2 { + regulator-name = "emi_vddq"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + + mt6360_ldo1: LDO1 { + regulator-name = "mt6360_ldo1"; /* Test point */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo2: LDO2 { + regulator-name = "panel1_p1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo3: LDO3 { + regulator-name = "vmc_pmu"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo5: LDO5 { + regulator-name = "vmch_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo6: LDO6 { + regulator-name = "mt6360_ldo6"; /* Test point */ + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = ; + }; + + mt6360_ldo7: LDO7 { + regulator-name = "emi_vmddr_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = ; + regulator-always-on; + }; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + hs400-ds-delay = <0x14c11>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>, <&mmc1_detect_pins>; + pinctrl-1 = <&mmc1_default_pins>; + cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-always-on; +}; + +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins_default>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins_default>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-cc { + pinmux = , + , + , + ; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = , + ; + input-enable; + }; + + pins-power { + pinmux = , + ; + output-high; + }; + + pins-reset { + pinmux = ; + output-high; + }; + + pins-interrupt { + pinmux = ; + input-enable; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = , + , + , + ; + }; + + pins-cc { + pinmux = , + , + , + ; + }; + + pins-rxd { + pinmux = , + , + , + ; + }; + + pins-mdio { + pinmux = , + ; + input-disable; + bias-disable; + }; + }; + + gpio_keys_pins: gpio-keys-pins { + pins { + pinmux = ; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins { + pinmux = , + ; + bias-pull-up = ; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <1000>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = ; + drive-strength = <6>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <6>; + bias-pull-up = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <6>; + bias-pull-up = ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = ; + drive-strength = <8>; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = <8>; + bias-pull-up = ; + }; + }; + + mmc1_detect_pins: mmc1-detect-pins { + pins-insert { + pinmux = ; + bias-pull-up; + }; + }; + + nor_pins_default: nor-default-pins { + pins-ck-io { + pinmux = , + , + ; + drive-strength = <6>; + bias-pull-down; + }; + + pins-cs { + pinmux = ; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie0_pins_default: pcie0-default-pins { + pins-bus { + pinmux = , + , + ; + bias-pull-up; + }; + }; + + pcie1_pins_default: pcie1-default-pins { + pins-bus { + pinmux = , + , + ; + bias-pull-up = ; + }; + }; + + led_pins: led-pins { + pins-power-en { + pinmux = ; + output-high; + }; + }; + + spi0_pins: spi0-default-pins { + pins-cs-mosi-clk { + pinmux = , + , + ; + bias-disable; + }; + + pins-miso { + pinmux = ; + bias-pull-down; + }; + }; + + spi1_pins: spi1-default-pins { + pins-cs-mosi-clk { + pinmux = , + , + ; + bias-disable; + }; + + pins-miso { + pinmux = ; + bias-pull-down; + }; + }; + + uart0_pins: uart0-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + }; + + uart1_pins: uart1-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + + pins-rts { + pinmux = ; + }; + + pins-cts { + pinmux = ; + input-enable; + }; + }; + + uart2_pins: uart2-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + + pins-rts { + pinmux = ; + }; + + pins-cts { + pinmux = ; + input-enable; + }; + }; + + uart3_pins: uart3-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up = ; + }; + + pins-tx { + pinmux = ; + }; + }; + + uart4_pins: uart4-pins { + pins-rx { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = ; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region = <&scp_mem>; + firmware-name = "mediatek/mt8195/scp.img"; + status = "okay"; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-ramp-delay = <6250>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-name = "Vgpu"; + regulator-min-microvolt = <625000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-ramp-delay = <6250>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + +/* USB3.2 front port */ +&ssusb0 { + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +/* USB2.0 M.2 Key-E */ +&ssusb2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +/* USB2.0 to on-board usb hub */ +&ssusb3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + mediatek,pad-select = <0>; + status = "okay"; + + tpm: tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <18500000>; + }; +}; + +/* B2B connector */ +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&thermal_zones { + cpu-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&thermal_sensor0>; + + trips { + trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + pcb-top-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&thermal_sensor1>; + + trips { + trip-alert { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-crit { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + pcb-bottom-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&thermal_sensor2>; + + trips { + trip-alert { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-crit { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; +}; + +/* USB3 */ +&u3phy0 { + status = "okay"; +}; + +/* PCIe1/USB2 */ +&u3phy1 { + status = "okay"; +}; + +/* USB2 */ +&u3phy2 { + status = "okay"; +}; + +/* USB2 */ +&u3phy3 { + status = "okay"; +}; + +/* USB3.2 front port */ +&xhci0 { + status = "okay"; +}; + +/* USB2.0 M.2 Key-B */ +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + mediatek,u3p-dis-msk = <0x01>; + status = "okay"; +}; + +/* USB2.0 M.2 Key-E */ +&xhci2 { + status = "okay"; +}; + +/* USB2.0 to on-board usb hub */ +&xhci3 { + status = "okay"; +}; -- cgit From 897a7edba9330974726c564dfdbf4fb5e203b9ac Mon Sep 17 00:00:00 2001 From: Pin-yen Lin Date: Thu, 2 May 2024 23:39:51 +0800 Subject: arm64: dts: mediatek: mt8192-asurada: Add off-on-delay-us for pp3300_mipibrdg Set off-on-delay-us to 500000 us for pp3300_mipibrdg to make sure it complies with the panel's unprepare delay (the time to power down completely) of the power sequence. Explicit configuration on the regulator node is required because mt8192-asurada uses the same power supply for the panel and the anx7625 DP bridge. For example, the power sequence could be violated in this sequence: 1. Bridge on: panel goes off, but regulator doesn't turn off (refcount=1). 2. Bridge off: regulator turns off (refcount=0). 3. Bridge resume -> regulator turns on but the bridge driver doesn't check the delay. Or in this sequence: 1. Bridge on: panel goes off. The regulator doesn't turn off (refcount=1), but the .unprepared_time in panel_edp is still updated. 2. Bridge off, regulator goes off (refcount=0). 3. Panel on, but the panel driver uses the wrong .unprepared_time to check the unprepare delay. Fixes: f9f00b1f6b9b ("arm64: dts: mediatek: asurada: Add display regulators") Signed-off-by: Pin-yen Lin Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240502154455.3427793-1-treapking@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 7a704246678f..08d71ddf3668 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -147,6 +147,7 @@ regulator-boot-on; gpio = <&pio 127 GPIO_ACTIVE_HIGH>; vin-supply = <&pp3300_g>; + off-on-delay-us = <500000>; }; /* separately switched 3.3V power rail */ -- cgit From f14cdf03d1b9c1ce45b3752a54c500c36d26d3dc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 29 May 2024 14:06:14 +0200 Subject: arm64: dts: mediatek: mt7986a: bpi-r3: Convert to sugar syntax Overlay syntactic sugar for generating target-path fragments is supported by the version of dtc supplied with the kernel since commit 50aafd60898a8b3e ("scripts/dtc: Update to upstream version v1.4.6-21-g84e414b0b5bc"). Hence convert the Bananapi R3 overlay devicetree source files to sugar syntax, improving readability. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/2fd900a30b5a0f7de4ea68f60bac250794b8cdb4.1716984213.git.geert+renesas@glider.be Signed-off-by: AngeloGioacchino Del Regno --- .../dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso | 28 +++---- .../dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso | 74 +++++++++--------- .../dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso | 90 +++++++++++----------- .../dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso | 16 ++-- 4 files changed, 98 insertions(+), 110 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso index 779dc6782bb1..047a8388811e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso @@ -9,21 +9,17 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - }; - }; }; +&{/soc/mmc@11230000} { + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso index 7b97c5c91bd0..24398f8a7da4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso @@ -9,46 +9,44 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; +}; + +&{/soc/spi@1100a000} { + #address-cells = <1>; + #size-cells = <0>; + + spi_nand: flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; - fragment@0 { - target-path = "/soc/spi@1100a000"; - __overlay__ { + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; - #size-cells = <0>; - spi_nand: flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "reserved"; - reg = <0x100000 0x280000>; - }; - - partition@380000 { - label = "fip"; - reg = <0x380000 0x200000>; - read-only; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x7a80000>; - }; - }; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "reserved"; + reg = <0x100000 0x280000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso index e48881be4ed6..6a0d529b54ac 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso @@ -9,54 +9,52 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; +}; + +&{/soc/spi@1100a000} { + #address-cells = <1>; + #size-cells = <0>; - fragment@0 { - target-path = "/soc/spi@1100a000"; - __overlay__ { + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; - #size-cells = <0>; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x40000>; - }; - - partition@80000 { - label = "reserved2"; - reg = <0x80000 0x80000>; - }; - - partition@100000 { - label = "fip"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "recovery"; - reg = <0x180000 0xa80000>; - }; - - partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; - }; - }; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; + }; + + partition@80000 { + label = "reserved2"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xa80000>; + }; + + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso index f623bce075ce..d9e01967acc4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso @@ -9,15 +9,11 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - status = "okay"; - }; - }; }; +&{/soc/mmc@11230000} { + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + status = "okay"; +}; -- cgit From f80cfe9616b7448eca709a3e87ca57201cd5787c Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Fri, 5 Apr 2024 12:50:30 +0200 Subject: arm64: dts: mediatek: mt7981: fix code alignment for PWM clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Align "clocks" array entries to start at the same column. Fixes: cf29427573cc ("arm64: dts: mediatek: Add initial MT7981B and Xiaomi AX3000T") Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20240405105030.24559-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 5674ac81d1f8..8a6263cc569c 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -86,10 +86,10 @@ compatible = "mediatek,mt7981-pwm"; reg = <0 0x10048000 0 0x1000>; clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; + <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; #pwm-cells = <2>; }; -- cgit From 454880d6168cc908d5f45a81a9aa6bdddf2ebc55 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 14 May 2024 03:51:54 +0200 Subject: arm64: dts: mediatek: mt7981: add efuse block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7981 (Filogic 820) uses efuse for storing calibration data. Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240514015154.11206-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 8a6263cc569c..0fc7c6d33d72 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -116,6 +116,13 @@ #interrupt-cells = <2>; }; + efuse@11f20000 { + compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; + reg = <0 0x11f20000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; -- cgit From 4e293c219e8e6b4a0c3aeeb4388836947ca478e3 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 10 May 2024 11:57:06 +0200 Subject: dt-bindings: arm64: mediatek: add BananaPi R3 Mini Add MT7988A based BananaPi R3 Mini. Signed-off-by: Frank Wunderlich Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240510095707.6895-2-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index eccc3f7cc4e6..f73dd2edeb9e 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -92,6 +92,7 @@ properties: - enum: - acelink,ew-7886cax - bananapi,bpi-r3 + - bananapi,bpi-r3mini - mediatek,mt7986a-rfb - const: mediatek,mt7986a - items: -- cgit From a098310bee5dbdfdea1265f137afad3e96d5ae86 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Fri, 10 May 2024 11:57:07 +0200 Subject: arm64: dts: mediatek: Add mt7986 based Bananapi R3 Mini Add devicetree for Bananapi R3 Mini SBC. Key features: - MediaTek MT7986A(Filogic 830) Quad core ARM Cortex A53 - Wifi 6 2.4G/5G (MT7976C) - 2G DDR RAM - 8G eMMC flash - 128MB Nand flash - 2x 2.5GbE network port - 1x M.2 Key B USB interface - 1x M.2 KEY M PCIe interface - 1x USB2.0 interface source: https://wiki.banana-pi.org/Banana_Pi_BPI-R3_Mini Co-developed-by: Eric Woudstra Signed-off-by: Eric Woudstra Co-developed-by: Tianling Shen Signed-off-by: Tianling Shen Signed-off-by: Frank Wunderlich Reviewed-by: Daniel Golle Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240510095707.6895-3-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts | 493 +++++++++++++++++++++ 2 files changed, 494 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 12f67959f257..39226a832312 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts new file mode 100644 index 000000000000..e2a2fea7adf0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Authors: Frank Wunderlich + * Eric Woudstra + * Tianling Shen + */ + +/dts-v1/; + +#include +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "Bananapi BPI-R3 Mini"; + chassis-type = "embedded"; + compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dcin: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "12vd"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + /* + * The signal is inverted on this board and the PWM driver + * does not support polarity inversion. + */ + /* cooling level (0, 1, 2) */ + cooling-levels = <255 96 0>; + pwms = <&pwm 0 10000>; + }; + + reg_1p8v: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1.8vd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + reg_3p3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + usb_vbus: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&pio 20 GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; + + en8811_a: regulator-phy1 { + compatible = "regulator-fixed"; + regulator-name = "phy1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 16 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + en8811_b: regulator-phy2 { + compatible = "regulator-fixed"; + regulator-name = "phy2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 17 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led-0 { + color = ; + function = LED_FUNCTION_POWER; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset-key { + label = "reset"; + linux,code = ; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + }; + +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_high>; + }; + + map1 { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_med>; + }; + + map2 { + /* active: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_active_low>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + phy-handle = <&phy0>; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy-handle = <&phy1>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; +}; + + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; + + /* MAC Address EEPROM */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + address-width = <8>; + pagesize = <8>; + size = <256>; + }; +}; + +&mdio { + phy0: ethernet-phy@14 { + reg = <14>; + interrupts-extended = <&pio 48 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + phy-mode = "2500base-x"; + full-duplex; + pause; + airoha,pnswap-rx; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { /* en8811_a_gpio5 */ + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + led@1 { /* en8811_a_gpio4 */ + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + default-state = "keep"; + }; + }; + }; + + phy1: ethernet-phy@15 { + reg = <15>; + interrupts-extended = <&pio 46 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pio 47 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + phy-mode = "2500base-x"; + full-duplex; + pause; + airoha,pnswap-rx; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { /* en8811_b_gpio5 */ + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + function-enumerator = <1>; + default-state = "keep"; + }; + led@1 { /* en8811_b_gpio4 */ + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + function-enumerator = <2>; + default-state = "keep"; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + i2c_pins: i2c-pins { + mux { + function = "i2c"; + groups = "i2c"; + }; + }; + + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0"; + }; + }; + + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + usb_ngff_pins: usb-ngff-pins { + ngff-gnss-off-conf { + pins = "GPIO_6"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-pe-rst-conf { + pins = "GPIO_7"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-wwan-off-conf { + pins = "GPIO_8"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-pwr-off-conf { + pins = "GPIO_9"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-rst-conf { + pins = "GPIO_10"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-coex-conf { + pins = "SPI1_CS"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_led_pins: wf-led-pins { + mux { + function = "led"; + groups = "wifi_led"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&ssusb { + pinctrl-names = "default"; + pinctrl-0 = <&usb_ngff_pins>; + vusb33-supply = <®_3p3v>; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; + + led { + led-active-low; + }; +}; + -- cgit From 1061f1b6610a87e1064cc914cb20210a0ca7b83d Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Mon, 27 May 2024 13:59:31 +0200 Subject: dt-bindings: vendor-prefixes: add OpenWrt MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OpenWrt project (with the help of MediaTek and Banana Pi) has produced its very first own hardware. It needs its own prefix. Signed-off-by: Rafał Miłecki Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240527115933.7396-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index e474055359f1..eabc353b8512 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1084,6 +1084,8 @@ patternProperties: description: OpenPandora GmbH "^openrisc,.*": description: OpenRISC.io + "^openwrt,.*": + description: OpenWrt "^option,.*": description: Option NV "^oranth,.*": -- cgit From ff31b980c4e198e9807092c25bc96ed89231dd8a Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Mon, 27 May 2024 13:59:32 +0200 Subject: dt-bindings: arm64: dts: mediatek: Add OpenWrt One MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OpenWrt One is the first ever OpenWrt product. It's based on MT7981B and has entered an early production stage. Signed-off-by: Rafał Miłecki Acked-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240527115933.7396-3-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index f73dd2edeb9e..11331fd6a616 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -86,6 +86,7 @@ properties: - items: - enum: - cudy,wr3000-v1 + - openwrt,one - xiaomi,ax3000t - const: mediatek,mt7981b - items: -- cgit From 95c465c439541bd5f38ced2f827f0f069bcc118e Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Mon, 27 May 2024 13:59:33 +0200 Subject: arm64: dts: mediatek: Add OpenWrt One MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit OpenWrt One is the first ever OpenWrt product. It's based on MT7981B (AKA Filogic 820) and has 1 GiB or DDR4 RAM. The rest of peripherals remains to be added later. Signed-off-by: Rafał Miłecki Reviewed-by: Linus Walleij Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240527115933.7396-4-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 39226a832312..56d551da917e 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-openwrt-one.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts new file mode 100644 index 000000000000..4f6cbb491287 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; + +#include "mt7981b.dtsi" + +/ { + compatible = "openwrt,one", "mediatek,mt7981b"; + model = "OpenWrt One"; + + memory@40000000 { + reg = <0 0x40000000 0 0x40000000>; + device_type = "memory"; + }; +}; -- cgit From 09ff2216a035709967096210cea144563bbc3259 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 4 Jun 2024 08:43:01 +0200 Subject: arm64: dts: mediatek: mt7988: add PWM controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7988 has on-SoC controller that can control up to 8 PWM interfaces. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20240604064302.487-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 3eb5396dea22..27098f724b7a 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -105,6 +105,25 @@ #clock-cells = <1>; }; + pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_CK1>, + <&infracfg CLK_INFRA_66M_PWM_CK2>, + <&infracfg CLK_INFRA_66M_PWM_CK3>, + <&infracfg CLK_INFRA_66M_PWM_CK4>, + <&infracfg CLK_INFRA_66M_PWM_CK5>, + <&infracfg CLK_INFRA_66M_PWM_CK6>, + <&infracfg CLK_INFRA_66M_PWM_CK7>, + <&infracfg CLK_INFRA_66M_PWM_CK8>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4", "pwm5", "pwm6", "pwm7", "pwm8"; + #pwm-cells = <2>; + status = "disabled"; + }; + usb@11190000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11190000 0 0x2e00>, -- cgit From 660c230bf30280334931bfcb4fb815998433ff57 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 4 Jun 2024 08:43:02 +0200 Subject: arm64: dts: mediatek: mt7988: add I2C controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7988 has three on-SoC I2C controllers that are the same hardware blocks as already noticed on MT7981 chipsets. Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20240604064302.487-2-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7988a.dtsi | 39 +++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index 27098f724b7a..aa728331e876 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -124,6 +124,45 @@ status = "disabled"; }; + i2c@11003000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@11004000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11004000 0 0x1000>, + <0 0x10217100 0 0x80>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@11005000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x10217180 0 0x80>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + usb@11190000 { compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; reg = <0 0x11190000 0 0x2e00>, -- cgit From aebba1030a5766cdf894ed4ab0cac7aed5aee9c1 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 4 Jun 2024 09:49:16 +0200 Subject: arm64: dts: mediatek: mt7622: fix "emmc" pinctrl mux MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Value "emmc_rst" is a group name and should be part of the "groups" property. This fixes: arch/arm64/boot/dts/mediatek/mt7622-rfb1.dtb: pinctrl@10211000: emmc-pins-default:mux:function: ['emmc', 'emmc_rst'] is too long from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml# arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dtb: pinctrl@10211000: emmc-pins-default:mux:function: ['emmc', 'emmc_rst'] is too long from schema $id: http://devicetree.org/schemas/pinctrl/mediatek,mt7622-pinctrl.yaml# Fixes: 3725ba3f5574 ("arm64: dts: mt7622: add pinctrl related device nodes") Fixes: 0b6286dd96c0 ("arm64: dts: mt7622: add bananapi BPI-R64 board") Signed-off-by: Rafał Miłecki Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240604074916.7929-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++-- arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 224bb289660c..2791de5b28f6 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -329,8 +329,8 @@ /* eMMC is shared pin with parallel NAND */ emmc_pins_default: emmc-pins-default { mux { - function = "emmc", "emmc_rst"; - groups = "emmc"; + function = "emmc"; + groups = "emmc", "emmc_rst"; }; /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 41629769bdc8..8c3e2e2578bc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -268,8 +268,8 @@ /* eMMC is shared pin with parallel NAND */ emmc_pins_default: emmc-pins-default { mux { - function = "emmc", "emmc_rst"; - groups = "emmc"; + function = "emmc"; + groups = "emmc", "emmc_rst"; }; /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", -- cgit From c3e87229b0fd8917af8dad6af94744c94929ed95 Mon Sep 17 00:00:00 2001 From: Rafał Miłecki Date: Tue, 4 Jun 2024 08:31:59 +0200 Subject: arm64: dts: mediatek: mt7981: add I2C controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7981 has one on-SoC I2C controller that differs from recent Mediatek blocks by having a different SLAVE_ADDR register offset (thus a custom binding compatible string). Signed-off-by: Rafał Miłecki Link: https://lore.kernel.org/r/20240604063159.29216-1-zajec5@gmail.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7981b.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 0fc7c6d33d72..64aeeb24efac 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -94,6 +94,21 @@ #pwm-cells = <2>; }; + i2c@11007000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>, + <&infracfg CLK_INFRA_I2C_MCK_CK>, + <&infracfg CLK_INFRA_I2C_PCK_CK>; + clock-names = "main", "dma", "arb", "pmic"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + pio: pinctrl@11d00000 { compatible = "mediatek,mt7981-pinctrl"; reg = <0 0x11d00000 0 0x1000>, -- cgit From 1e8a1a9ea21831a32555e25174b7587668326bbc Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Jun 2024 11:24:19 +0200 Subject: arm64: dts: mediatek: mt8365: drop incorrect power-domain-cells The top SCPSYS node is not a power domain provider. It's child "power-controller" is instead. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240612092421.52917-1-krzysztof.kozlowski@linaro.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 24581f7410aa..455c2ae3b30a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -302,7 +302,6 @@ scpsys: syscon@10006000 { compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; /* System Power Manager */ spm: power-controller { -- cgit From cc827572ad153d63b5f1a3b376727681bcba567e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Jun 2024 11:24:20 +0200 Subject: arm64: dts: mediatek: mt8365: use a specific SCPSYS compatible SoCs should use dedicated compatibles for each of their syscon nodes to precisely describe the block. Using an incorrect compatible does not allow to properly match/validate children of the syscon device. Replace SYSCFG compatible, which does not have children, with a new dedicated one for SCPSYS block. Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240612092421.52917-2-krzysztof.kozlowski@linaro.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8365.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 455c2ae3b30a..eb449bfa8803 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -300,7 +300,7 @@ }; scpsys: syscon@10006000 { - compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd"; + compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; /* System Power Manager */ -- cgit From b220332f9849e82b55d566a40f9c8457b177e232 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Wed, 12 Jun 2024 11:24:21 +0200 Subject: arm64: dts: mediatek: mt8173-elm: drop PMIC's syscon node According to AngeloGioacchino Del Regno, the syscon node in PMIC is neither needed nor used. It looks like a solution to expose some of the registers of PMIC. Drop it to solve also incorrect number of entries in the "reg" property and fix dtbs_check warning: mt8173-elm.dtb: syscon@c000: reg: [[0, 49152], [0, 264]] is too long Link: https://lore.kernel.org/all/671a4b1e-3d95-438c-beae-d967e0ad1c77@collabora.com/ Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20240612092421.52917-3-krzysztof.kozlowski@linaro.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 6d962d437e02..b4d85147b77b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -1134,12 +1134,6 @@ rtc: mt6397rtc { compatible = "mediatek,mt6397-rtc"; }; - - syscfg_pctl_pmic: syscon@c000 { - compatible = "mediatek,mt6397-pctl-pmic-syscfg", - "syscon"; - reg = <0 0x0000c000 0 0x0108>; - }; }; }; -- cgit From 45682a4fffdd9abd6e2df9c5c534d22f2eda94f9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 May 2024 11:39:05 +0200 Subject: arm64: dts: mediatek: mt8188: Add Global Command Engine mailboxes In preparation for adding multimedia nodes and power domains, add support for the two Global Command Engine (GCE) mailboxes found in this SoC. Link: https://lore.kernel.org/r/20240527093908.97574-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index b4315c9214dc..06fa3b862c31 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -413,6 +414,22 @@ clock-names = "spi", "wrap"; }; + gce0: mailbox@10320000 { + compatible = "mediatek,mt8188-gce"; + reg = <0 0x10320000 0 0x4000>; + interrupts = ; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + }; + + gce1: mailbox@10330000 { + compatible = "mediatek,mt8188-gce"; + reg = <0 0x10330000 0 0x4000>; + interrupts = ; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; + }; + scp: scp@10500000 { compatible = "mediatek,mt8188-scp"; reg = <0 0x10500000 0 0x100000>, -- cgit From e15d0dd73eacf8cce08725631b99e45ff58061f9 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 May 2024 11:39:06 +0200 Subject: arm64: dts: mediatek: mt8188: Add VDOSYS0/1 support for multimedia Add support for the two VDOSYS blocks in MT8188, later on used for various Multimedia related IP, including display and video codecs. Link: https://lore.kernel.org/r/20240527093908.97574-4-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 06fa3b862c31..84f2809eae7a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -969,5 +969,22 @@ reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + + vdosys0: syscon@1c01d000 { + compatible = "mediatek,mt8188-vdosys0", "syscon"; + reg = <0 0x1c01d000 0 0x1000>; + #clock-cells = <1>; + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; + }; + + vdosys1: syscon@1c100000 { + compatible = "mediatek,mt8188-vdosys1", "syscon"; + reg = <0 0x1c100000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; + }; }; }; -- cgit From eaf73e4224a348ef228de6b0b6fa0c7da91d0e25 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 May 2024 11:39:07 +0200 Subject: arm64: dts: mediatek: mt8188: Add support for SoC power domains In preparation for adding support for hardware IP that requires power switching, add the necessary power domains nodes for the MT8188 SoC. Link: https://lore.kernel.org/r/20240527093908.97574-5-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 323 +++++++++++++++++++++++++++++++ 1 file changed, 323 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 84f2809eae7a..0bca6c9f15fe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -384,6 +384,329 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8188-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { + reg = ; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_MFG1 { + reg = ; + clocks = <&topckgen CLK_APMIXED_MFGPLL>, + <&topckgen CLK_TOP_MFG_CORE_TMP>; + clock-names = "mfg", "alt"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_MFG2 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_MFG3 { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_MFG4 { + reg = ; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { + reg = ; + clocks = <&topckgen CLK_TOP_VPP>, + <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_IMG>, + <&topckgen CLK_TOP_VENC>, + <&topckgen CLK_TOP_VDEC>, + <&topckgen CLK_TOP_WPE_VPP>, + <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, + <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, + <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>, + <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>, + <&vppsys0 CLK_VPP0_SMI_IOMMU>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, + <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, + <&vppsys0 CLK_VPP0_SMI_RSI>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "top", "cam", "ccu", "img", "venc", + "vdec", "wpe", "cfgck", "cfgxo", + "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1", + "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa", + "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6", + "ss-sram-rdr", "ss-iommu", "ss-imgcam", + "ss-emi", "ss-subcmn-rdr", "ss-rsi", + "ss-cmn-l4", "ss-vdec1", "ss-wpe", + "ss-cvdo-ve1"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { + reg = ; + clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>, + <&topckgen CLK_TOP_CFGREG_F26M_VDO0>, + <&vdosys0 CLK_VDO0_SMI_GALS>, + <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_IOMMU>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_RSI>, + <&vdosys0 CLK_VDO0_APB_BUS>; + clock-names = "cfgck", "cfgxo", "ss-gals", + "ss-cmn", "ss-emi", "ss-iommu", + "ss-larb", "ss-rsi", "ss-bus"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { + reg = ; + clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, + <&topckgen CLK_TOP_CFGREG_F26M_VPP1>, + <&vppsys1 CLK_VPP1_GALS5>, + <&vppsys1 CLK_VPP1_GALS6>, + <&vppsys1 CLK_VPP1_LARB5>, + <&vppsys1 CLK_VPP1_LARB6>; + clock-names = "cfgck", "cfgxo", + "ss-vpp1-g5", "ss-vpp1-g6", + "ss-vpp1-l5", "ss-vpp1-l6"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_VDEC1 { + reg = ; + clocks = <&vdecsys CLK_VDEC2_LARB1>; + clock-names = "ss-vdec"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_VDEC0 { + reg = ; + clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; + clock-names = "ss-vdec"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { + reg = ; + clocks = <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_CCU_AHB>, + <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; + clock-names = "cam", "ccu", "bus", "cfgck"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { + reg = ; + clocks = <&camsys CLK_CAM_MAIN_LARB13>, + <&camsys CLK_CAM_MAIN_LARB14>, + <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>; + clock-names= "ss-cam-l13", "ss-cam-l14", + "ss-cam-mm0", "ss-cam-mm1", + "ss-camsys"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_CAM_SUBB { + reg = ; + clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>, + <&camsys_yuvb CLK_CAM_YUVB_LARBX>; + clock-names = "ss-camb-sub", + "ss-camb-raw", + "ss-camb-yuv"; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_CAM_SUBA { + reg =; + clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>, + <&camsys_yuva CLK_CAM_YUVA_LARBX>; + clock-names = "ss-cama-sub", + "ss-cama-raw", + "ss-cama-yuv"; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { + reg = ; + clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>, + <&topckgen CLK_TOP_CFGREG_F26M_VDO1>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names = "cfgck", "cfgxo", "ss-larb2", + "ss-larb3", "ss-gals"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_HDMI_TX { + reg = ; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP_24M>; + clock-names = "bus", "hdcp"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_DP_TX { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_EDP_TX { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VENC { + reg = ; + clocks = <&vencsys CLK_VENC1_LARB>, + <&vencsys CLK_VENC1_VENC>, + <&vencsys CLK_VENC1_GALS>, + <&vencsys CLK_VENC1_GALS_SRAM>; + clock-names = "ss-ve1-larb", "ss-ve1-core", + "ss-ve1-gals", "ss-ve1-sram"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_WPE { + reg = ; + clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, + <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; + clock-names = "ss-wpe-l7", "ss-wpe-l7pce"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; + clock-names = "ss-pextp-fmem"; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP { + reg = ; + clocks = <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>; + clock-names = "seninf0", "seninf1"; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP { + reg = ; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_ADSP_AO { + reg = ; + clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&topckgen CLK_TOP_ADSP>; + clock-names = "bus", "main"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { + reg = ; + clocks = <&topckgen CLK_TOP_ASM_H>; + clock-names = "asm"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_AUDIO { + reg = ; + clocks = <&topckgen CLK_TOP_A1SYS_HP>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; + clock-names = "a1sys", "intbus", "adspck"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_ADSP { + reg = ; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_ETHER { + reg = ; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + clock-names = "ethermac"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8188-wdt"; reg = <0 0x10007000 0 0x100>; -- cgit From c44589a890ffd64fbb2813eaadab143c347ef909 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Mon, 27 May 2024 11:39:08 +0200 Subject: arm64: dts: mediatek: mt8188: Add support for Mali GPU on Panfrost Add the necessary OPP table for the GPU and also add a GPU node to enable support for the Valhall-JM G57 MC3 found on this SoC, using the Panfrost driver. Link: https://lore.kernel.org/r/20240527093908.97574-6-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8188.dtsi | 123 +++++++++++++++++++++++++++++++ 1 file changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index 0bca6c9f15fe..29d012d28edb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -294,6 +294,112 @@ clock-output-names = "clk32k"; }; + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-microvolt = <575000>; + opp-supported-hw = <0xff>; + }; + opp-431000000 { + opp-hz = /bits/ 64 <431000000>; + opp-microvolt = <587500>; + opp-supported-hw = <0xff>; + }; + opp-473000000 { + opp-hz = /bits/ 64 <473000000>; + opp-microvolt = <600000>; + opp-supported-hw = <0xff>; + }; + opp-515000000 { + opp-hz = /bits/ 64 <515000000>; + opp-microvolt = <612500>; + opp-supported-hw = <0xff>; + }; + opp-556000000 { + opp-hz = /bits/ 64 <556000000>; + opp-microvolt = <625000>; + opp-supported-hw = <0xff>; + }; + opp-598000000 { + opp-hz = /bits/ 64 <598000000>; + opp-microvolt = <637500>; + opp-supported-hw = <0xff>; + }; + opp-640000000 { + opp-hz = /bits/ 64 <640000000>; + opp-microvolt = <650000>; + opp-supported-hw = <0xff>; + }; + opp-670000000 { + opp-hz = /bits/ 64 <670000000>; + opp-microvolt = <662500>; + opp-supported-hw = <0xff>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <675000>; + opp-supported-hw = <0xff>; + }; + opp-730000000 { + opp-hz = /bits/ 64 <730000000>; + opp-microvolt = <687500>; + opp-supported-hw = <0xff>; + }; + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-microvolt = <700000>; + opp-supported-hw = <0xff>; + }; + opp-790000000 { + opp-hz = /bits/ 64 <790000000>; + opp-microvolt = <712500>; + opp-supported-hw = <0xff>; + }; + opp-835000000 { + opp-hz = /bits/ 64 <835000000>; + opp-microvolt = <731250>; + opp-supported-hw = <0xff>; + }; + opp-880000000 { + opp-hz = /bits/ 64 <880000000>; + opp-microvolt = <750000>; + opp-supported-hw = <0xff>; + }; + opp-915000000 { + opp-hz = /bits/ 64 <915000000>; + opp-microvolt = <775000>; + opp-supported-hw = <0x8f>; + }; + opp-915000000-5 { + opp-hz = /bits/ 64 <915000000>; + opp-microvolt = <762500>; + opp-supported-hw = <0x30>; + }; + opp-915000000-6 { + opp-hz = /bits/ 64 <915000000>; + opp-microvolt = <750000>; + opp-supported-hw = <0x70>; + }; + opp-950000000 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <800000>; + opp-supported-hw = <0x8f>; + }; + opp-950000000-5 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <775000>; + opp-supported-hw = <0x30>; + }; + opp-950000000-6 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <750000>; + opp-supported-hw = <0x70>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupt-parent = <&gic>; @@ -1167,6 +1273,23 @@ #clock-cells = <1>; }; + gpu: gpu@13000000 { + compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm"; + reg = <0 0x13000000 0 0x4000>; + + clocks = <&mfgcfg CLK_MFGCFG_BG3D>; + interrupts = , + , + ; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, + <&spm MT8188_POWER_DOMAIN_MFG3>, + <&spm MT8188_POWER_DOMAIN_MFG4>; + power-domain-names = "core0", "core1", "core2"; + status = "disabled"; + }; + mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8188-mfgcfg"; reg = <0 0x13fbf000 0 0x1000>; -- cgit From 95173af725e6f41eb470466a52ddf2054439409c Mon Sep 17 00:00:00 2001 From: Hsin-Te Yuan Date: Thu, 13 Jun 2024 11:58:54 +0000 Subject: arm64: dts: mediatek: mt8183-kukui: Fix the value of `dlg,jack-det-rate` mismatch According to Documentation/devicetree/bindings/sound/dialog,da7219.yaml, the value of `dlg,jack-det-rate` property should be "32_64" instead of "32ms_64ms". Fixes: dc0ff0fa3a9b ("ASoC: da7219: Add Jack insertion detection polarity") Signed-off-by: Hsin-Te Yuan Link: https://lore.kernel.org/r/20240613-jack-rate-v2-1-ebc5f9f37931@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi index 8b57706ac814..586eee79c73c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi @@ -27,7 +27,7 @@ dlg,btn-cfg = <50>; dlg,mic-det-thr = <500>; dlg,jack-ins-deb = <20>; - dlg,jack-det-rate = "32ms_64ms"; + dlg,jack-det-rate = "32_64"; dlg,jack-rem-deb = <1>; dlg,a-d-btn-thr = <0xa>; -- cgit From 0b2f9d0e397b6c2d510d118bac036f7f6bb3c3db Mon Sep 17 00:00:00 2001 From: Pin-yen Lin Date: Wed, 15 Nov 2023 12:35:01 +0800 Subject: arm64: dts: mt8173: Add G2Touch touchscreen node Lenovo Ideapad C330 Chromebook (MTK) uses G2Touch touchscreen as a second source component. Signed-off-by: Pin-yen Lin Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20231115043511.2670477-1-treapking@chromium.org [Angelo: Rebased and added comment] Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi index 90cbbc18a483..8d1cbc92bce3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi @@ -27,6 +27,15 @@ hid-descr-addr = <0x0020>; interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>; }; + + /* Lenovo Ideapad C330 uses G2Touch touchscreen as a 2nd source touchscreen */ + touchscreen@40 { + compatible = "hid-over-i2c"; + reg = <0x40>; + hid-descr-addr = <0x0001>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; }; &i2c4 { -- cgit From 70bf81dd2c2dedbed1f19dfc5d1d2f22474a5296 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 31 Jan 2024 16:40:41 +0800 Subject: arm64: dts: mediatek: mt8183-pico6: Fix wake-on-X event node names The wake-on-bt and wake-on-wlan nodes don't have a button- or event- prefix that the gpio-keys binding requires. Fix up the node names to satisfy the binding. While at it, also fix up the GPIO overriding structure for the wake-on-wlan node. Instead of referencing the gpio-keys node and then open coding the node, add a label for the event node, and use that to reference and override the GPIO settings. Fixes: 055ef10ccdd4 ("arm64: dts: mt8183: Add jacuzzi pico/pico6 board") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240131084043.3970576-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts | 8 +++----- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 2 +- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts index 6a7ae616512d..0d5a11c93c68 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts @@ -17,7 +17,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_pins_wakeup>; - wobt { + event-wobt { label = "Wake on BT"; gpios = <&pio 42 GPIO_ACTIVE_HIGH>; linux,code = ; @@ -47,10 +47,8 @@ }; }; -&wifi_wakeup { - wowlan { - gpios = <&pio 113 GPIO_ACTIVE_LOW>; - }; +&wifi_wakeup_event { + gpios = <&pio 113 GPIO_ACTIVE_LOW>; }; &wifi_pwrseq { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 5472cd0be63a..a9e40c291d0e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -152,7 +152,7 @@ pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_wakeup>; - button-wowlan { + wifi_wakeup_event: event-wowlan { label = "Wake on WiFi"; gpios = <&pio 113 GPIO_ACTIVE_HIGH>; linux,code = ; -- cgit From 4055416e6c51347e7dd5784065263fe0ced0bb7d Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Wed, 31 Jan 2024 16:39:29 +0800 Subject: arm64: dts: mediatek: mt8183-kukui-jacuzzi: Add ports node for anx7625 The anx7625 binding requires a "ports" node as a container for the "port" nodes. The jacuzzi dtsi file is missing it. Add a "ports" node under the anx7625 node, and move the port related nodes and properties under it. Fixes: cabc71b08eb5 ("arm64: dts: mt8183: Add kukui-jacuzzi-damu board") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240131083931.3970388-1-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- .../boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi | 25 ++++++++++++---------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 7592e3b86037..fa4ab4d2899f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -155,21 +155,24 @@ vdd18-supply = <&pp1800_mipibrdg>; vdd33-supply = <&vddio_mipibrdg>; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - anx7625_in: endpoint { - remote-endpoint = <&dsi_out>; + port@0 { + reg = <0>; + + anx7625_in: endpoint { + remote-endpoint = <&dsi_out>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - anx7625_out: endpoint { - remote-endpoint = <&panel_in>; + anx7625_out: endpoint { + remote-endpoint = <&panel_in>; + }; }; }; -- cgit From db77778a405aa0431835939f8482bea0adb26fe5 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 20 Jun 2024 12:18:30 +0200 Subject: arm64: dts: mediatek: Makefile: Generate symbols for DTBO support Add DTC_FLAGS '-@' for mt7986a-bananapi-bpi-r3 and -mini to instruct the devicetree compiler to enable generation of symbols. This allows proper support for Device Tree Overlay(s) for those boards; future boards that need DTBO support are expected to add their own DTC_FLAGS_{dtb-name}. Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20240620101830.1097548-1-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 56d551da917e..5dbb695d053f 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -84,3 +84,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb + +# Device tree overlays support +DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@ +DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@ -- cgit From 9b4e41428498651da04e0ceca879958a6703b4dd Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 20 Jun 2024 17:47:37 +0800 Subject: dt-bindings: arm: mediatek: Add MT8186 Voltorb Chromebooks Add an entry for the MT8186 based Voltorb Chromebooks, also known as the Acer Chromebook 311 (C723/C723T). The device is a clamshell style laptop with an optional touchscreen. Signed-off-by: Chen-Yu Tsai Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240620094746.2404753-3-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- Documentation/devicetree/bindings/arm/mediatek.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 11331fd6a616..1d4bb50fcd8d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -296,6 +296,13 @@ properties: - const: google,tentacruel-sku327683 - const: google,tentacruel - const: mediatek,mt8186 + - description: Google Voltorb (Acer Chromebook 311 C723/C732T) + items: + - enum: + - google,voltorb-sku589824 + - google,voltorb-sku589825 + - const: google,voltorb + - const: mediatek,mt8186 - items: - enum: - mediatek,mt8186-evb -- cgit From 321ad586e6073e33dd576ec33ae1803db3b1e717 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Thu, 20 Jun 2024 17:47:38 +0800 Subject: arm64: dts: mediatek: Add MT8186 Voltorb Chromebooks Add device trees for the MT8186 based Voltorb Chromebooks, also known as the Acer Chromebook 311 (C723/C723T). The devices are clamshell style laptops with an optional touchscreen. The devices differ from the other existing MT8186 Chromebooks in that it uses a higher speced / binned SoC which also requires a separate PMIC for the big core cluster. Also, a different codec is used for the internal speakers. Signed-off-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20240620094746.2404753-4-wenst@chromium.org Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/Makefile | 2 + .../mediatek/mt8186-corsola-voltorb-sku589824.dts | 13 +++ .../mediatek/mt8186-corsola-voltorb-sku589825.dts | 25 +++++ .../boot/dts/mediatek/mt8186-corsola-voltorb.dtsi | 103 +++++++++++++++++++++ 4 files changed, 143 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 5dbb695d053f..8fd7b2bb7a15 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -65,6 +65,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts new file mode 100644 index 000000000000..d16834eec87a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-voltorb.dtsi" + +/ { + model = "Google Voltorb sku589824 board"; + compatible = "google,voltorb-sku589824", "google,voltorb", + "mediatek,mt8186"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts new file mode 100644 index 000000000000..45e57f7706cc --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-voltorb.dtsi" + +/ { + model = "Google Voltorb sku589825 board"; + compatible = "google,voltorb-sku589825", "google,voltorb", + "mediatek,mt8186"; +}; + +&i2c1 { + touchscreen@10 { + compatible = "elan,ekth6915"; + reg = <0x10>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vcc33-supply = <&pp3300_s3>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi new file mode 100644 index 000000000000..52ec58128d56 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +#include +#include + +#include "mt8186-corsola-steelix.dtsi" + +/ { + chassis-type = "laptop"; + + max98360a: max98360a { + compatible = "maxim,max98360a"; + sdmode-gpios = <&pio 150 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&cpu6 { + proc-supply = <&mt6319_buck1>; +}; + +&cpu7 { + proc-supply = <&mt6319_buck1>; +}; + +&gpio_keys { + status = "disabled"; +}; + +&keyboard_controller { + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +&mt6366_vproc11_reg { + status = "disabled"; +}; + +&cluster1_opp_14 { + opp-hz = /bits/ 64 <2050000000>; + opp-microvolt = <1118750>; +}; + +&cluster1_opp_15 { + opp-hz = /bits/ 64 <2200000000>; +}; + +&rt1019p{ + status = "disabled"; +}; + +&sound { + compatible = "mediatek,mt8186-mt6366-rt5682s-max98360-sound"; + status = "okay"; + + spk-hdmi-playback-dai-link { + codec { + sound-dai = <&it6505dptx>, <&max98360a>; + }; + }; +}; + +&spmi { + pinctrl-names = "default"; + pinctrl-0 = <&spmi_pins>; + #address-cells = <2>; + #size-cells = <0>; + status = "okay"; + + pmic@6 { + compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6319_buck1: vbuck1 { + regulator-name = "ppvar_dvdd_proc_bc_mt6319"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + +&touchscreen { + status = "disabled"; +}; -- cgit From df768350a87031971a3c834b480aef6ad6f1f1a0 Mon Sep 17 00:00:00 2001 From: Frank Wunderlich Date: Thu, 16 May 2024 22:48:47 +0200 Subject: arm64: dts: mt7622: fix switch probe on bananapi-r64 After commit 868ff5f4944a ("net: dsa: mt7530-mdio: read PHY address of switch from device tree") the mt7531 switch on Bananapi-R64 was not detected. mt7530-mdio mdio-bus:00: reset timeout mt7530-mdio mdio-bus:00: probe with driver mt7530-mdio failed with error -110 Fix this by adding phy address in devicetree. Signed-off-by: Frank Wunderlich Link: https://lore.kernel.org/r/20240516204847.171029-1-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 2791de5b28f6..d12eac9b3eeb 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -149,9 +149,9 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7531"; - reg = <0>; + reg = <0x1f>; interrupt-controller; #interrupt-cells = <1>; interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>; -- cgit From d79603c2be61ca9d4fafa89ac7f5d8cc78568af4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 20 Jun 2024 12:16:55 +0200 Subject: arm64: dts: mediatek: Declare drive-strength numerically On some devicetrees, the drive-strength property gets assigned a MTK_DRIVE_(x)_mA definition, which matches with (x). For example, MTK_DRIVE_8mA equals to 8 and MTK_DRIVE_30mA equals to 30. Also keeping in mind that the drive-strength property is, by (binding) definition, taking a number in milliamperes unit, change all devicetrees to avoid the usage of any MTK_DRIVE_(x) definition. Reviewed-by: Chen-Yu Tsai Link: https://lore.kernel.org/r/20240620101656.1096374-2-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno --- arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 4 +-- .../boot/dts/mediatek/mt6795-sony-xperia-m5.dts | 8 ++--- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 12 +++---- .../mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts | 2 +- .../mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts | 2 +- .../dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts | 6 ++-- arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi | 8 ++--- arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts | 4 +-- arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 26 +++++++------- arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 4 +-- .../boot/dts/mediatek/mt8390-genio-700-evk.dts | 40 +++++++++++----------- .../boot/dts/mediatek/mt8395-genio-1200-evk.dts | 28 +++++++-------- 12 files changed, 72 insertions(+), 72 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 234e3b23d7a8..c84c47c1352f 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -137,7 +137,7 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; rx_pins { pinmux = , @@ -151,7 +151,7 @@ mdio_pins { pinmux = , ; - drive-strength = ; + drive-strength = <8>; input-enable; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 7364c7278276..91de920c2245 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -288,25 +288,25 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; pins-ds { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 3fab21f59d18..bb4671c18e3b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -213,14 +213,14 @@ , ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up = ; }; pins_clk { pinmux = ; bias-pull-down; - drive-strength = ; + drive-strength = <4>; }; pins_insert { @@ -241,13 +241,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <2>; bias-pull-up = ; }; pins_clk { pinmux = ; - drive-strength = ; + drive-strength = <2>; bias-pull-down = ; }; @@ -265,13 +265,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <4>; bias-pull-up = ; }; pins_clk { pinmux = ; - drive-strength = ; + drive-strength = <4>; bias-pull-down = ; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts index 4eb2a0d571af..ddb993521bbf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts @@ -19,6 +19,6 @@ &mmc1_pins_uhs { pins-clk { - drive-strength = ; + drive-strength = <6>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts index 6a733361e8ae..10c4f920a7d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts @@ -19,6 +19,6 @@ &mmc1_pins_uhs { pins-clk { - drive-strength = ; + drive-strength = <6>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts index 0d5a11c93c68..cce326aec1aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts @@ -66,16 +66,16 @@ &mmc1_pins_default { pins-cmd-dat { - drive-strength = ; + drive-strength = <6>; }; pins-clk { - drive-strength = ; + drive-strength = <6>; }; }; &mmc1_pins_uhs { pins-clk { - drive-strength = ; + drive-strength = <6>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index a9e40c291d0e..6345e969efae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -488,7 +488,7 @@ , , ; /*8ch-i2s to it6505*/ - drive-strength = ; + drive-strength = <6>; }; }; @@ -502,7 +502,7 @@ ; input-enable; bias-pull-down; - drive-strength = ; + drive-strength = <2>; }; }; @@ -673,14 +673,14 @@ , , ; - drive-strength = ; + drive-strength = <6>; input-enable; mediatek,pull-up-adv = <10>; }; pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; mediatek,pull-down-adv = <10>; input-enable; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 81f6c205fa98..1aa668c3ccf9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -350,14 +350,14 @@ , , ; - drive-strength = ; + drive-strength = <6>; input-enable; mediatek,pull-up-adv = <10>; }; pins_clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; mediatek,pull-down-adv = <10>; input-enable; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index b82f7176b4a1..31d424b8fc7c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -305,14 +305,14 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; pins-cc { pinmux = , , , ; - drive-strength = ; + drive-strength = <8>; }; pins-rxd { pinmux = , @@ -377,7 +377,7 @@ mmc0_default_pins: mmc0-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; @@ -392,13 +392,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; @@ -406,7 +406,7 @@ mmc0_uhs_pins: mmc0-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -421,19 +421,19 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; pins-ds { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; @@ -441,7 +441,7 @@ mmc1_default_pins: mmc1-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -452,7 +452,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; @@ -465,7 +465,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -476,7 +476,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 50cbaefa1a99..4211a992dd9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -308,7 +308,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { clk-pins { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -319,7 +319,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts index 6bb1d5d112ef..1474bef7e754 100644 --- a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -383,13 +383,13 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; pins-mdio { pinmux = , ; - drive-strength = ; + drive-strength = <8>; input-enable; }; @@ -404,7 +404,7 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; pins-txd { @@ -412,7 +412,7 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; }; @@ -520,7 +520,7 @@ mmc0_default_pins: mmc0-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; @@ -535,13 +535,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; @@ -549,7 +549,7 @@ mmc0_uhs_pins: mmc0-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -564,19 +564,19 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; pins-ds { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; @@ -584,7 +584,7 @@ mmc1_default_pins: mmc1-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; @@ -595,7 +595,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; @@ -608,7 +608,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; @@ -619,7 +619,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; @@ -627,7 +627,7 @@ mmc2_default_pins: mmc2-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <4>; bias-pull-down = ; }; @@ -638,7 +638,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; @@ -650,7 +650,7 @@ mmc2_uhs_pins: mmc2-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <4>; bias-pull-down = ; }; @@ -661,7 +661,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; @@ -678,7 +678,7 @@ pins-dat1 { pinmux = ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts index a1b613808780..a06610fff8ad 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -475,7 +475,7 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; pins-mdio { @@ -502,7 +502,7 @@ , , ; - drive-strength = ; + drive-strength = <8>; }; }; @@ -567,7 +567,7 @@ pinmux = , ; bias-pull-up = ; - drive-strength = ; + drive-strength = <6>; }; }; @@ -582,7 +582,7 @@ mmc0_default_pins: mmc0-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-down = ; }; @@ -597,13 +597,13 @@ , ; input-enable; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <6>; bias-pull-up = ; }; }; @@ -611,7 +611,7 @@ mmc0_uhs_pins: mmc0-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -626,19 +626,19 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; pins-ds { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; pins-rst { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; @@ -646,7 +646,7 @@ mmc1_default_pins: mmc1-default-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -657,7 +657,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; @@ -665,7 +665,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { pins-clk { pinmux = ; - drive-strength = ; + drive-strength = <8>; bias-pull-down = ; }; @@ -676,7 +676,7 @@ , ; input-enable; - drive-strength = ; + drive-strength = <8>; bias-pull-up = ; }; }; -- cgit