From 99f698e268786da84dd49bd36176c6d27fa04894 Mon Sep 17 00:00:00 2001 From: Marco Felsch Date: Mon, 4 Feb 2019 16:29:55 +0100 Subject: ARM: dts: pfla02: prepare storage devices to add paritions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Partitions in the NOR and EEPROM are application specific. Prepare the SoM device tree so platform device tree's can add partitions. Signed-off-by: Marco Felsch Acked-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 433bf09a1954..673711f445b6 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -79,7 +79,7 @@ status = "okay"; cs-gpios = <&gpio4 24 0>; - flash@0 { + som_flash: flash@0 { compatible = "m25p80", "jedec,spi-nor"; spi-max-frequency = <20000000>; reg = <0>; @@ -120,7 +120,7 @@ pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; - eeprom@50 { + som_eeprom: eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; }; -- cgit From 8da0af5d6d39fa8d9f2e230045d93f2677ce089e Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 13 Feb 2019 16:24:38 -0200 Subject: ARM: dts: vf610-zii: Disable SNVS RTC None of these vf610-zii boards have a battery or super-capacitor holding up power to the SNVS RTC embedded in the Vybrid SoC, so it is preferable to disable the snvsrtc node. Signed-off-by: Fabio Estevam Reviewed-by: Andrew Lunn Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 4 ++++ arch/arm/boot/dts/vf610-zii-scu4-aib.dts | 4 ++++ arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 4 ++++ arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 4 ++++ 4 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 445c7dc306b2..440de578d8af 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -236,6 +236,10 @@ }; }; +&snvsrtc { + status = "disabled"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts index de6dfa57bec5..e3952e9ea0db 100644 --- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts @@ -671,6 +671,10 @@ }; }; +&snvsrtc { + status = "disabled"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index 2b10672fadbd..60dad9c228a9 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -211,6 +211,10 @@ }; }; +&snvsrtc { + status = "disabled"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 0d9fe5ac83a3..6df3ef979eb0 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -219,6 +219,10 @@ }; }; +&snvsrtc { + status = "disabled"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart0>; -- cgit From 96d861c2fd40529ab122626ac27f00722760d800 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 13 Feb 2019 16:24:39 -0200 Subject: ARM: dts: vf610-zii-ssmb-spu3: Disable watchdog On vf610-zii-ssmb-spu3 board there is a supervisory microcontroller that provides the watchdog functionality, so disable the on-chip Vybrid's watchdog. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 6df3ef979eb0..2a392e2444ff 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -254,6 +254,10 @@ }; }; +&wdoga5 { + status = "disabled"; +}; + &iomuxc { pinctrl_dspi1: dspi1grp { fsl,pins = < -- cgit From 3117e851cef1b4e1b4454d3d223a43ccbf3eee20 Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 1 Mar 2019 08:28:03 -0800 Subject: ARM: dts: imx: Add TDA19971 HDMI Receiver to GW551x The GW551x has a front-panel microHDMI connector routed to a TDA19971 which is connected the the IPU CSI. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 138 ++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 8e46a80f57a4..c23ba229fd05 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -46,6 +46,8 @@ */ #include +#include +#include / { /* these are used by bootloader for disabling nodes */ @@ -99,6 +101,50 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + sound-digital { + compatible = "simple-audio-card"; + simple-audio-card,name = "tda1997x-audio"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + + cpu { + sound-dai = <&ssi2>; + }; + + codec { + bitclock-master; + frame-master; + sound-dai = <&hdmi_receiver>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ + status = "okay"; + + ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; + }; }; &can1 { @@ -264,6 +310,60 @@ #gpio-cells = <2>; }; + hdmi_receiver: hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3>; + AVDD-supply = <®_1p8b>; + DVDD-supply = <®_1p8a>; + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same cycle + * which we map to VP[15:08]<->CSI_DATA[19:12] + */ + nxp,vidout-portcfg = + /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <16>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; + bus-width = <16>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; }; &pcie { @@ -321,6 +421,14 @@ }; &iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 @@ -376,6 +484,30 @@ >; }; + pinctrl_ipu1_csi0: ipu1_csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ @@ -400,6 +532,12 @@ >; }; + pinctrl_tda1997x: tda1997xgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 -- cgit From 7d1446688d2d0c9235d0cd0890db1bb8c173568d Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Fri, 1 Mar 2019 08:32:53 -0800 Subject: ARM: dts: imx: Add TDA19971 HDMI Receiver to GW54xx The GW54xx has a front-panel microHDMI connector routed to a TDA19971 which is connected the the IPU CSI when using IMX6Q. Signed-off-by: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-gw54xx.dts | 105 ++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 29 +++++++++- 2 files changed, 131 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-gw54xx.dts b/arch/arm/boot/dts/imx6q-gw54xx.dts index 56e5b5050fcf..cb0a5f7d5a19 100644 --- a/arch/arm/boot/dts/imx6q-gw54xx.dts +++ b/arch/arm/boot/dts/imx6q-gw54xx.dts @@ -12,10 +12,30 @@ /dts-v1/; #include "imx6q.dtsi" #include "imx6qdl-gw54xx.dtsi" +#include / { model = "Gateworks Ventana i.MX6 Dual/Quad GW54XX"; compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; + + sound-digital { + compatible = "simple-audio-card"; + simple-audio-card,name = "tda1997x-audio"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + + cpu { + sound-dai = <&ssi2>; + }; + + codec { + bitclock-master; + frame-master; + sound-dai = <&hdmi_receiver>; + }; + }; + }; }; &i2c3 { @@ -35,6 +55,61 @@ }; }; }; + + hdmi_receiver: hdmi-receiver@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3v>; + AVDD-supply = <&sw4_reg>; + DVDD-supply = <&sw4_reg>; + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same cycle + * which we map to VP[15:08]<->CSI_DATA[19:12] + */ + nxp,vidout-portcfg = + /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <16>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; + bus-width = <16>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; }; &ipu2_csi1_from_ipu2_csi1_mux { @@ -63,6 +138,30 @@ >; }; + pinctrl_ipu1_csi0: ipu1_csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + pinctrl_ipu2_csi1: ipu2_csi1grp { fsl,pins = < MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b0 @@ -78,4 +177,10 @@ MX6QDL_PAD_EIM_A16__IPU2_CSI1_PIXCLK 0x1b0b0 >; }; + + pinctrl_tda1997x: tda1997xgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index 81b2fcf6eedf..e4d1c5250d1e 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -10,6 +10,7 @@ */ #include +#include / { /* these are used by bootloader for disabling nodes */ @@ -115,12 +116,12 @@ }; }; - sound { + sound-analog { compatible = "fsl,imx6q-ventana-sgtl5000", "fsl,imx-audio-sgtl5000"; model = "sgtl5000-audio"; ssi-controller = <&ssi1>; - audio-codec = <&codec>; + audio-codec = <&sgtl5000>; audio-routing = "MIC_IN", "Mic Jack", "Mic Jack", "Mic Bias", @@ -134,6 +135,25 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */ status = "okay"; + + ssi2 { + fsl,audmux-port = <1>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(1)>; + }; }; &can1 { @@ -332,7 +352,7 @@ pinctrl-0 = <&pinctrl_i2c3>; status = "okay"; - codec: sgtl5000@a { + sgtl5000: audio-codec@a { compatible = "fsl,sgtl5000"; reg = <0x0a>; clocks = <&clks IMX6QDL_CLK_CKO>; @@ -476,6 +496,9 @@ MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */ + MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0 >; }; -- cgit From 54f6deafd27db3d14ddd75771dbdc5297a24863e Mon Sep 17 00:00:00 2001 From: Yinbo Zhu Date: Tue, 26 Feb 2019 08:40:22 +0000 Subject: ARM: dts: ls1021a-qds: enable esdhc controller This patch is to enable esdhc controller in ls1021aqds Signed-off-by: Yinbo Zhu Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-qds.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/ls1021a-qds.dts b/arch/arm/boot/dts/ls1021a-qds.dts index ca60730dda40..74a67604876c 100644 --- a/arch/arm/boot/dts/ls1021a-qds.dts +++ b/arch/arm/boot/dts/ls1021a-qds.dts @@ -146,6 +146,10 @@ status = "okay"; }; +&esdhc { + status = "okay"; +}; + &i2c0 { status = "okay"; -- cgit From d058ad0e3856578a9821330edc583cc4349b179d Mon Sep 17 00:00:00 2001 From: Pierre-Jean Texier Date: Sat, 2 Mar 2019 23:32:29 +0100 Subject: ARM: dts: imx7s-warp: PMIC swbst boot-on/always-on PMIC swbst regulator is used for the MikroBUS socket (pin +5V). We have to set the regulator to "boot-on" and "always-on" to output a voltage of 5V on this socket. Signed-off-by: Pierre-Jean Texier Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 23431faecaf4..b1e956205e9a 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -121,6 +121,8 @@ swbst_reg: swbst { regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5150000>; + regulator-boot-on; + regulator-always-on; }; snvs_reg: vsnvs { -- cgit From 574e852f99c36ea867f621b748771d4d8b3c3f98 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Mar 2019 14:12:47 +0100 Subject: ARM: dts: imx6: RDU2: add switch watchdog device This adds the i2c device node for the ethernet switch watchdog. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 69942c7ff89d..7f920e0243ec 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -528,6 +528,11 @@ }; }; + watchdog@38 { + compatible = "zii,rave-wdt"; + reg = <0x38>; + }; + temp-sense@48 { compatible = "national,lm75"; reg = <0x48>; -- cgit From 5252414f7c15c2857d34c093d19ddb3171ac73d0 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 6 Mar 2019 14:12:48 +0100 Subject: ARM: dts: imx6: RDU2: manage backlight from panel Now that the backlight driver is upstream, we can properly manage the backlight from the panel. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 7f920e0243ec..9f664897bf4e 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -210,6 +210,7 @@ panel { power-supply = <®_3p3v_display>; + backlight = <&sp_backlight>; status = "disabled"; port { @@ -327,7 +328,7 @@ compatible = "zii,rave-sp-watchdog"; }; - backlight { + sp_backlight: backlight { compatible = "zii,rave-sp-backlight"; }; -- cgit From 768b525edb4a7ddd6f3f05dada9582b8281c734a Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Thu, 7 Mar 2019 19:01:48 -0600 Subject: ARM: dts: imx6qdl: Enable fsl,sec-v4.0-pwrkey The imx6q Technical reference manual shows the interrupt is available to wake from sleep using the power button. The driver has been available for quite some time, and other variants of the i.MX6 have it enabled, so this implements it much like the others. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index fe17a3405edc..6b3e48d2e5ec 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -4,6 +4,7 @@ // Copyright 2011 Linaro Ltd. #include +#include #include / { @@ -833,6 +834,14 @@ status = "disabled"; }; + snvs_pwrkey: snvs-powerkey { + compatible = "fsl,sec-v4.0-pwrkey"; + regmap = <&snvs>; + interrupts = ; + linux,keycode = ; + wakeup-source; + }; + snvs_lpgpr: snvs-lpgpr { compatible = "fsl,imx6q-snvs-lpgpr"; }; -- cgit From 10ee87d19a5d48cead4ccbe0a2a64956f766ec5c Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 12 Mar 2019 02:24:12 +0000 Subject: ARM: dts: imx7ulp: add mmdc support i.MX7ULP has a MMDC module to control DDR, it reuses i.MX6Q's MMDC module, add support for it. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index fca6e50f37c8..eb349fd7f6e4 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -286,6 +286,12 @@ status = "disabled"; }; + memory-controller@40ab0000 { + compatible = "fsl,imx7ulp-mmdc", "fsl,imx6q-mmdc"; + reg = <0x40ab0000 0x1000>; + clocks = <&pcc3 IMX7ULP_CLK_MMDC>; + }; + iomuxc1: pinctrl@40ac0000 { compatible = "fsl,imx7ulp-iomuxc1"; reg = <0x40ac0000 0x1000>; -- cgit From 476f6e53a0d0e41697ef611fd28b4a8f6b6711e5 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 12 Mar 2019 02:24:16 +0000 Subject: ARM: dts: imx: make MMDC node name generic Node name should be generic, so use "memory-controller" instead of "mmdc" for MMDC node name, also remove "mmdc" label for platforms with single MMDC node. Signed-off-by: Anson Huang Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 4 ++-- arch/arm/boot/dts/imx6sl.dtsi | 2 +- arch/arm/boot/dts/imx6sx.dtsi | 2 +- arch/arm/boot/dts/imx6ul.dtsi | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 6b3e48d2e5ec..883e2ff68106 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1138,13 +1138,13 @@ reg = <0x021ac000 0x4000>; }; - mmdc0: mmdc@21b0000 { /* MMDC0 */ + mmdc0: memory-controller@21b0000 { /* MMDC0 */ compatible = "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>; }; - mmdc1: mmdc@21b4000 { /* MMDC1 */ + mmdc1: memory-controller@21b4000 { /* MMDC1 */ reg = <0x021b4000 0x4000>; }; diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 4b4813f176cd..733ea50fc8e3 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -922,7 +922,7 @@ status = "disabled"; }; - mmdc: mmdc@21b0000 { + memory-controller@21b0000 { compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 5b16e65f7696..df0c59519886 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -1017,7 +1017,7 @@ status = "disabled"; }; - mmdc: mmdc@21b0000 { + memory-controller@21b0000 { compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 62ed30c781ed..a77bbcae4571 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -914,7 +914,7 @@ status = "disabled"; }; - mmdc: mmdc@21b0000 { + memory-controller@21b0000 { compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; reg = <0x021b0000 0x4000>; clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>; -- cgit From 3a1a67b1ca7b5402e72de48fd63a88ddd4ef2cf8 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Tue, 12 Mar 2019 02:24:20 +0000 Subject: ARM: dts: imx6qdl: Improve mmdc1 node Add MMDC1 compatible string which is missing, and also set it to be disabled by default, as most of the platforms ONLY use single channel MMDC0, if dual MMDC channels are used, it can be enabled in board dts file. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 883e2ff68106..2eb4c779298b 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -1145,7 +1145,9 @@ }; mmdc1: memory-controller@21b4000 { /* MMDC1 */ + compatible = "fsl,imx6q-mmdc"; reg = <0x021b4000 0x4000>; + status = "disabled"; }; weim: weim@21b8000 { -- cgit From f7a6f5f3bb7bd1dca1950c4910e450e9a45c9caa Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 12 Mar 2019 10:19:23 -0300 Subject: ARM: dts: vf610-zii: Remove 'max-brightness' property The 'max-brightness' property is not a valid one as per Documentation/devicetree/bindings/leds/leds-gpio.txt, so remove it. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 5 ----- arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts | 1 - arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 1 - 3 files changed, 7 deletions(-) diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 440de578d8af..6c78122401a1 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -29,35 +29,30 @@ label = "zii:green:debug1"; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; - max-brightness = <1>; }; led-fail { label = "zii:red:fail"; gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; default-state = "off"; - max-brightness = <1>; }; led-status { label = "zii:green:status"; gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; default-state = "off"; - max-brightness = <1>; }; led-debug-a { label = "zii:green:debug_a"; gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>; default-state = "off"; - max-brightness = <1>; }; led-debug-b { label = "zii:green:debug_b"; gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; default-state = "off"; - max-brightness = <1>; }; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts index 60dad9c228a9..847c5858fea1 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-dtu.dts @@ -37,7 +37,6 @@ label = "zii:green:debug1"; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; - max-brightness = <1>; }; }; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 2a392e2444ff..8366bae632d6 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -37,7 +37,6 @@ label = "zii:green:debug1"; gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; - max-brightness = <1>; }; }; -- cgit From ad8c096a84a7335ab90f708edea9892f6d88b7b2 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Fri, 15 Mar 2019 21:14:21 +0000 Subject: ARM: dts: i.MX50: Add i2c, mmc and spi aliases Using aliases, the devices will be enumerated properly. Signed-off-by: Alexander Kurz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index ee1e3e8bf4ec..9fb22b16159c 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -26,11 +26,21 @@ gpio3 = &gpio4; gpio4 = &gpio5; gpio5 = &gpio6; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + mmc2 = &esdhc3; + mmc3 = &esdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi2; + spi2 = &cspi; }; cpus { -- cgit From 5da7f749aec3ad637f33934386d0265bc3ee919f Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Fri, 15 Mar 2019 21:14:22 +0000 Subject: ARM: dts: i.MX6SL: Add i2c and mmc aliases Using aliases, the devices will be enumerated properly. Signed-off-by: Alexander Kurz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 733ea50fc8e3..0ad5d507abec 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -23,6 +23,13 @@ gpio2 = &gpio3; gpio3 = &gpio4; gpio4 = &gpio5; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &usdhc1; + mmc1 = &usdhc2; + mmc2 = &usdhc3; + mmc3 = &usdhc4; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; -- cgit From 67814a9b1b3bb312b31e7da181d488191b4115b6 Mon Sep 17 00:00:00 2001 From: Alexander Kurz Date: Fri, 15 Mar 2019 21:14:23 +0000 Subject: ARM: dts: i.MX35: Add i2c and mmc aliases Using aliases, the devices will be enumerated properly. Signed-off-by: Alexander Kurz Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx35.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi index 59cadeee23ed..9cbdc1a15cda 100644 --- a/arch/arm/boot/dts/imx35.dtsi +++ b/arch/arm/boot/dts/imx35.dtsi @@ -21,6 +21,12 @@ gpio0 = &gpio1; gpio1 = &gpio2; gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &esdhc1; + mmc1 = &esdhc2; + mmc2 = &esdhc3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; -- cgit From aed609c40c6f676354bd7cf23a51339e7adc3c4c Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Tue, 19 Mar 2019 16:24:18 +0100 Subject: ARM: dts: imx50: Add PHY node for usbotg and adjust clocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Even though the ChipIdea USB controller binding[1] doesn't specify the properties that reference a PHY as required, the Linux driver requires[2] such a reference. The clock situation is like on i.MX53: The USB controller is clocked from IMX5_CLK_USBOH3_GATE and the PHY from IMX5_CLK_USB_PHY1_GATE. [1]: Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt [2]: Search for EINVAL in drivers/usb/chipidea/ci_hdrc_imx.c Signed-off-by: Jonathan Neuschäfer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 9fb22b16159c..5dd61bff3b76 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -86,6 +86,14 @@ }; }; + usbphy0: usbphy-0 { + compatible = "usb-nop-xceiv"; + clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clock-names = "main_clk"; + #phy-cells = <0>; + status = "okay"; + }; + soc { #address-cells = <1>; #size-cells = <1>; @@ -197,7 +205,8 @@ compatible = "fsl,imx50-usb", "fsl,imx27-usb"; reg = <0x53f80000 0x0200>; interrupts = <18>; - clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; + clocks = <&clks IMX5_CLK_USBOH3_GATE>; + fsl,usbphy = <&usbphy0>; status = "disabled"; }; -- cgit From 26d459398a7ced52ff640bc1cf1cf6fc3f4b5fc8 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Wed, 20 Mar 2019 14:38:02 +0000 Subject: ARM: dts: ls1021a: Remove unused properties from QSPI node After switching to the new FSL QSPI driver the properties 'fsl,qspi-has-second-chip' and 'big-endian' are not used anymore. The driver now uses the 'reg' property to determine the bus and the chipselect. The endianness is selected by the driver depending on which SoC is used. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts | 1 - arch/arm/boot/dts/ls1021a.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts index ba1ddd93b8f8..dcb1d9bd0922 100644 --- a/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts +++ b/arch/arm/boot/dts/ls1021a-moxa-uc-8410a.dts @@ -204,7 +204,6 @@ }; &qspi { - fsl,qspi-has-second-chip; status = "okay"; flash: flash@0 { diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index b4f2723ecd86..2bcc00de88d4 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -186,7 +186,6 @@ interrupts = ; clock-names = "qspi_en", "qspi"; clocks = <&clockgen 4 1>, <&clockgen 4 1>; - big-endian; status = "disabled"; }; -- cgit From 811c94f1e866efd02060acdfa697274a9973d5c3 Mon Sep 17 00:00:00 2001 From: Uwe Kleine-König Date: Wed, 20 Mar 2019 10:12:53 +0100 Subject: ARM: dts: Add devicetree for Eckelmann ci4x10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is one of two boards that make use of the recently introduced SIOX bus. Apart from the devices described in the dts it features a display with touch that I didn't include here because it needs some non-mainline change to operate correctly. Reviewed-by: Fabio Estevam Signed-off-by: Uwe Kleine-König Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 381 ++++++++++++++++++++++++++ 2 files changed, 382 insertions(+) create mode 100644 arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index f4f5aeaf3298..3332dbf2a979 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -400,6 +400,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-cubox-i-emmc-som-v15.dtb \ imx6dl-cubox-i-som-v15.dtb \ imx6dl-dfi-fs700-m60.dtb \ + imx6dl-eckelmann-ci4x10.dtb \ imx6dl-emcon-avari.dtb \ imx6dl-gw51xx.dtb \ imx6dl-gw52xx.dtb \ diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts new file mode 100644 index 000000000000..9eb2b73951b2 --- /dev/null +++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts @@ -0,0 +1,381 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Eckelmann AG. + * Copyright (C) 2013 Freescale Semiconductor, Inc. + */ + +/dts-v1/; + +#include + +#include "imx6dl.dtsi" + +/ { + model = "Eckelmann CI 4X10 Board"; + compatible = "eckelmann,imx6dl-ci4x10", "fsl,imx6dl"; + + chosen { + stdout-path = &uart3; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + rmii_clk: clock-rmii { + /* This clock is provided by the phy (KSZ8091RNB) */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + reg_usb_h1_vbus: regulator-usb-h1-vbus { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usb_h1_vbus>; + compatible = "regulator-fixed"; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + siox { + compatible = "eckelmann,siox-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_siox>; + din-gpios = <&gpio6 11 GPIO_ACTIVE_HIGH>; + dout-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; + dclk-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; + dld-gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 12 GPIO_ACTIVE_HIGH>; + status = "okay"; + + flash@0 { + compatible = "everspin,mr25h256"; + reg = <0>; + spi-max-frequency = <15000000>; + }; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; + status = "okay"; + + tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <10000000>; + }; +}; + +&gpio2 { + gpio-line-names = "buzzer", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", "", "", "", "in2", + "prio2", "prio1", "aux", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpio6 { + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "in1", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + temperature-sensor@49 { + compatible = "ad,ad7414"; + reg = <0x49>; + }; + + rtc@51 { + compatible = "nxp,pcf2127"; + reg = <0x51>; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_hog: hog { + fsl,pins = < + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x00000018 /* buzzer */ + MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x00000018 /* OUT_1 */ + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x00000018 /* OUT_2 */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x00000018 /* OUT_3 */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x00000000 /* In1 */ + MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x00000000 /* In2 */ + MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x00000018 /* unused watchdog pin */ + MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x00000018 /* unused watchdog pin */ + + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__ECSPI1_SCLK 0x000100a0 + MX6QDL_PAD_CSI0_DAT5__ECSPI1_MOSI 0x000100a0 + MX6QDL_PAD_CSI0_DAT6__ECSPI1_MISO 0x000100a0 + MX6QDL_PAD_CSI0_DAT7__GPIO5_IO25 0x000100a0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__ECSPI2_SCLK 0x000100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x000100b1 + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x000100b1 + MX6QDL_PAD_DISP0_DAT18__GPIO5_IO12 0x000100b1 + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x0001b098 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x0001b098 + MX6QDL_PAD_ENET_TXD0__ENET_TX_DATA0 0x0001b098 + MX6QDL_PAD_ENET_TXD1__ENET_TX_DATA1 0x0001b098 + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x0001b098 + MX6QDL_PAD_ENET_RX_ER__ENET_RX_ER 0x0001b0b0 + MX6QDL_PAD_ENET_RXD0__ENET_RX_DATA0 0x0001b0b0 + MX6QDL_PAD_ENET_RXD1__ENET_RX_DATA1 0x0001b0b0 + MX6QDL_PAD_ENET_CRS_DV__ENET_RX_EN 0x0001b0b0 + MX6QDL_PAD_SD1_CMD__GPIO1_IO18 0x00000018 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x0001b020 + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x0001b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x0001b020 + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x0001b0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + /* without SION i2c doesn't detect bus busy */ + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b820 + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b820 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x00000018 + >; + }; + + pinctrl_reg_usb_h1_vbus: reg_usb_h1_vbusgrp { + fsl,pins = < + MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x0001b0b0 + >; + }; + + pinctrl_siox: sioxgrp { + fsl,pins = < + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x0001b010 /* DIN */ + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0001b010 /* DOUT */ + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0001b010 /* DCLK */ + MX6QDL_PAD_NANDF_RB0__GPIO6_IO10 0x0001b010 /* DLD */ + >; + }; + + pinctrl_uart1_dte: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT11__UART1_TX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT10__UART1_RX_DATA 0x0001b010 + MX6QDL_PAD_EIM_D19__UART1_RTS_B 0x0001b010 + MX6QDL_PAD_EIM_D20__UART1_CTS_B 0x0001b010 + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0001b010 /* DCD */ + MX6QDL_PAD_EIM_D24__GPIO3_IO24 0x0001b010 /* DTR */ + MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x0001b010 /* DSR */ + >; + }; + + pinctrl_uart2_dte: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x0001b010 + MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x0001b010 + MX6QDL_PAD_EIM_D28__UART2_RTS_B 0x0001b010 + MX6QDL_PAD_EIM_D29__UART2_CTS_B 0x0001b010 + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0001b010 /* DCD */ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x0001b010 /* DTR */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0001b010 /* DSR */ + >; + }; + + pinctrl_uart3_dce: uart3grp { + fsl,pins = < + MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x0001b010 + MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x0001b010 + >; + }; + + pinctrl_uart4_dce: uart4grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x0001b010 + >; + }; + + pinctrl_uart5_dce: uart5grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT15__UART5_RX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT14__UART5_TX_DATA 0x0001b010 + MX6QDL_PAD_CSI0_DAT19__GPIO6_IO05 0x0001b010 /* RTS */ + >; + }; + + pinctrl_usbh1: usbh1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x0001b0b0 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x00017059 + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x00010059 + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x00017059 + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x00017059 + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x00017059 + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x00017059 + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x00017059 + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x00017059 + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x00017059 + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x00017059 + >; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rmii"; + phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>; + phy-handle = <&phy>; + clocks = <&clks IMX6QDL_CLK_ENET>, <&clks IMX6QDL_CLK_ENET>, <&rmii_clk>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio1 20 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_dte>; + uart-has-rtscts; + fsl,dte-mode; + dcd-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio3 25 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_dte>; + uart-has-rtscts; + fsl,dte-mode; + dcd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; + dtr-gpios = <&gpio7 13 GPIO_ACTIVE_LOW>; + dsr-gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_dce>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4_dce>; + rts-gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5_dce>; + rts-gpios = <&gpio6 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbh1>; + vbus-supply = <®_usb_h1_vbus>; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; -- cgit From 496456058b506233a88ca60dbedbcb0e681d2423 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Fri, 22 Mar 2019 06:31:56 +0000 Subject: ARM: dts: imx7ulp: add ocotp support Add i.MX7ULP OCOTP support, its clock source is from M4 BUS clock which is NOT available in Linux clock tree, but M4 BUS clock is always ON when A7 (Linux) is alive, so just use dummy clock here. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7ulp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi index eb349fd7f6e4..d6b711011cba 100644 --- a/arch/arm/boot/dts/imx7ulp.dtsi +++ b/arch/arm/boot/dts/imx7ulp.dtsi @@ -365,5 +365,11 @@ compatible = "fsl,imx7ulp-sim", "syscon"; reg = <0x410a3000 0x1000>; }; + + ocotp: ocotp-ctrl@410a6000 { + compatible = "fsl,imx7ulp-ocotp", "syscon"; + reg = <0x410a6000 0x4000>; + clocks = <&scg1 IMX7ULP_CLK_DUMMY>; + }; }; }; -- cgit From dae9f076d1c3c5d1e4bb7363d8b1ccd6145200b1 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 25 Mar 2019 11:22:43 -0700 Subject: ARM: dts: vf610: Add ZII SPB4 board Add Device Tree for VF610 based Zodiac Seat Power Box. Signed-off-by: Andrey Smirnov Reviewed-by: Fabio Estevam Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Heiner Kallweit Cc: Fabio Estevam Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Cc: linux-imx@nxp.com Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/vf610-zii-spb4.dts | 359 +++++++++++++++++++++++++++++++++++ 2 files changed, 360 insertions(+) create mode 100644 arch/arm/boot/dts/vf610-zii-spb4.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3332dbf2a979..1234bd95d85c 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -607,6 +607,7 @@ dtb-$(CONFIG_SOC_VF610) += \ vf610-zii-dev-rev-b.dtb \ vf610-zii-dev-rev-c.dtb \ vf610-zii-scu4-aib.dtb \ + vf610-zii-spb4.dtb \ vf610-zii-ssmb-dtu.dtb \ vf610-zii-ssmb-spu3.dtb dtb-$(CONFIG_ARCH_MXS) += \ diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts new file mode 100644 index 000000000000..9dde83ccb9d1 --- /dev/null +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts @@ -0,0 +1,359 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/* + * Device tree file for ZII's SPB4 board + * + * SPB - Seat Power Box + * + * Copyright (C) 2019 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include "vf610.dtsi" + +/ { + model = "ZII VF610 SPB4 Board"; + compatible = "zii,vf610spb4", "zii,vf610dev", "fsl,vf610"; + + chosen { + stdout-path = &uart0; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + led-debug { + label = "zii:green:debug1"; + gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu { + compatible = "regulator-fixed"; + regulator-name = "vcc_3v3_mcu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&adc0 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&adc1 { + vref-supply = <®_vcc_3v3_mcu>; + status = "okay"; +}; + +&dspi1 { + bus-num = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dspi1>; + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "m25p128", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + }; +}; + +&edma0 { + status = "okay"; +}; + +&edma1 { + status = "okay"; +}; + +&esdhc0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc0>; + bus-width = <8>; + non-removable; + no-1-8-v; + keep-power-in-suspend; + no-sdio; + no-sd; + status = "okay"; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + bus-width = <4>; + no-sdio; + status = "okay"; +}; + +&fec1 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + status = "okay"; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch0: switch0@0 { + compatible = "marvell,mv88e6190"; + pinctrl-0 = <&pinctrl_gpio_switch0>; + pinctrl-names = "default"; + reg = <0>; + eeprom-length = <65536>; + reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>; + interrupt-parent = <&gpio3>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&fec1>; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_1"; + }; + + port@2 { + reg = <2>; + label = "eth_cu_1000_2"; + }; + + port@3 { + reg = <3>; + label = "eth_cu_1000_3"; + }; + + port@4 { + reg = <4>; + label = "eth_cu_1000_4"; + }; + + port@5 { + reg = <5>; + label = "eth_cu_1000_5"; + }; + + port@6 { + reg = <6>; + label = "eth_cu_1000_6"; + }; + }; + }; + }; +}; + +&i2c0 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c0>; + status = "okay"; + + io-expander@22 { + compatible = "nxp,pca9554"; + reg = <0x22>; + gpio-controller; + #gpio-cells = <2>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + label = "nameplate"; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&snvsrtc { + status = "disabled"; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart0>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&wdoga5 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_dspi1: dspi1grp { + fsl,pins = < + VF610_PAD_PTD5__DSPI1_CS0 0x1182 + VF610_PAD_PTD4__DSPI1_CS1 0x1182 + VF610_PAD_PTC6__DSPI1_SIN 0x1181 + VF610_PAD_PTC7__DSPI1_SOUT 0x1182 + VF610_PAD_PTC8__DSPI1_SCK 0x1182 + >; + }; + + pinctrl_esdhc0: esdhc0grp { + fsl,pins = < + VF610_PAD_PTC0__ESDHC0_CLK 0x31ef + VF610_PAD_PTC1__ESDHC0_CMD 0x31ef + VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef + VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef + VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef + VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef + VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef + VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef + VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef + VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + VF610_PAD_PTA24__ESDHC1_CLK 0x31ef + VF610_PAD_PTA25__ESDHC1_CMD 0x31ef + VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef + VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef + VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef + VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef + >; + }; + + pinctrl_fec1: fec1grp { + fsl,pins = < + VF610_PAD_PTA6__RMII_CLKIN 0x30d1 + VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2 + VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3 + VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1 + VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1 + VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1 + VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1 + VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2 + VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2 + VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2 + >; + }; + + pinctrl_gpio_switch0: pinctrl-gpio-switch0 { + fsl,pins = < + VF610_PAD_PTE2__GPIO_107 0x31c2 + VF610_PAD_PTB28__GPIO_98 0x219d + >; + }; + + pinctrl_i2c0: i2c0grp { + fsl,pins = < + VF610_PAD_PTB14__I2C0_SCL 0x37ff + VF610_PAD_PTB15__I2C0_SDA 0x37ff + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + VF610_PAD_PTB16__I2C1_SCL 0x37ff + VF610_PAD_PTB17__I2C1_SDA 0x37ff + >; + }; + + pinctrl_leds_debug: pinctrl-leds-debug { + fsl,pins = < + VF610_PAD_PTD3__GPIO_82 0x31c2 + >; + }; + + pinctrl_uart0: uart0grp { + fsl,pins = < + VF610_PAD_PTB10__UART0_TX 0x21a2 + VF610_PAD_PTB11__UART0_RX 0x21a1 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + VF610_PAD_PTB23__UART1_TX 0x21a2 + VF610_PAD_PTB24__UART1_RX 0x21a1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + VF610_PAD_PTD0__UART2_TX 0x21a2 + VF610_PAD_PTD1__UART2_RX 0x21a1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + VF610_PAD_PTA30__UART3_TX 0x21a2 + VF610_PAD_PTA31__UART3_RX 0x21a1 + >; + }; +}; -- cgit From 5f0a88a1aabb2b332e2fa01598cc24e708552771 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Mon, 25 Mar 2019 11:30:17 -0700 Subject: ARM: dts: vf610-zii-cfu1: Disable NOR flash/SPI controller Only a certain number of CFU1's come with NOR flash populated. Disable it by default to avoid trying to probe NOR flash on devices that don't have it. Devices that do have it can rely on the bootloader to enable this node. Signed-off-by: Andrey Smirnov Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index 6c78122401a1..afc25b33bd3b 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -87,7 +87,12 @@ bus-num = <1>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_dspi1>; - status = "okay"; + /* + * Some CFU1s come with SPI-NOR chip DNPed, so we leave this + * node disabled by default and rely on bootloader to enable + * it when appropriate. + */ + status = "disabled"; m25p128@0 { #address-cells = <1>; -- cgit From a8ab3547c7b4db9fb58fa3cbf136f3c94948effd Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 26 Mar 2019 23:38:40 -0700 Subject: ARM: dts: imx7d: Specify viewport count for PCIE block i.MX7D comes with 4 viewports, so configure PCIE node accordingly so that the driver won't assume we only have 2. Signed-off-by: Andrey Smirnov Cc: Richard Zhu Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7d.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 6eb98e7c568d..f33b560821b8 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -154,6 +154,7 @@ ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ num-lanes = <1>; + num-viewport = <4>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; -- cgit From 87fd3ce28b4694397692cecba233fe4e12298413 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Tue, 26 Mar 2019 23:38:41 -0700 Subject: ARM: dts: imx6qdl: Specify viewport count for PCIE block i.MX6 comes with 4 viewports, so configure PCIE node accordingly so that the driver won't assume we only have 2. Signed-off-by: Andrey Smirnov Cc: Richard Zhu Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 2eb4c779298b..38b18a007f48 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -280,6 +280,7 @@ ranges = <0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ num-lanes = <1>; + num-viewport = <4>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; -- cgit From a80a1af6ec8ac59fdddeb013d7c1572bcae4f6eb Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Wed, 3 Apr 2019 08:44:25 +0200 Subject: ARM: dts: tq imx7 common board support This adds TQMa7 and MBa7 board support. TQMa7 can be mounted with either i.MX7 Solo or Dual. All TQMa7 board variants can be mounted in MBa7 carrier board. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 561 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx7-tqma7.dtsi | 232 ++++++++++++++++ 2 files changed, 793 insertions(+) create mode 100644 arch/arm/boot/dts/imx7-mba7.dtsi create mode 100644 arch/arm/boot/dts/imx7-tqma7.dtsi diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi new file mode 100644 index 000000000000..578341b6848b --- /dev/null +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -0,0 +1,561 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ Systems MBa7 carrier board. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + * + * Note: This file does not include nodes for all peripheral devices. + * As device driver coverage increases additional nodes can be added. + */ + +#include +#include + +/ { + beeper { + compatible = "gpio-beeper"; + gpios = <&pca9555 0 GPIO_ACTIVE_HIGH>; + }; + + chosen { + stdout-path = &uart6; + }; + + gpio_buttons: gpio-keys { + compatible = "gpio-keys"; + + button-0 { + /* #SWITCH_A */ + label = "S11"; + linux,code = ; + gpios = <&pca9555 13 GPIO_ACTIVE_LOW>; + }; + + button-1 { + /* #SWITCH_B */ + label = "S12"; + linux,code = ; + gpios = <&pca9555 14 GPIO_ACTIVE_LOW>; + }; + + button-2 { + /* #SWITCH_C */ + label = "S13"; + linux,code = ; + gpios = <&pca9555 15 GPIO_ACTIVE_LOW>; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led1 { + label = "led1"; + gpios = <&pca9555 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led2 { + label = "led2"; + gpios = <&pca9555 9 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_SD1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_fec1_pwdn: regulator-fec1-pwdn { + compatible = "regulator-fixed"; + regulator-name = "PWDN_FEC1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_fec2_pwdn: regulator-fec2-pwdn { + compatible = "regulator-fixed"; + regulator-name = "PWDN_FEC2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + gpio = <&gpio2 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_USBOTG1"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + regulator-name = "VBUS_USBOTG2"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_1v5: regulator-mpcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V5_MPCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&pca9555 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mpcie_3v3: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_MPCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9555 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + reg_mba_12v0: regulator-mba-12v0 { + compatible = "regulator-fixed"; + regulator-name = "VCC12V0_MBA7"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&pca9555 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_lvds_transmitter: regulator-lvds-transmitter { + compatible = "regulator-fixed"; + regulator-name = "#SHTDN_LVDS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pca9555 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VCC1V8_REF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&sw2_reg>; + }; + + reg_audio_3v3: regulator-audio-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3_AUDIO"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + num-chipselects = <3>; + cs-gpios = <&gpio4 0 GPIO_ACTIVE_LOW>, <&gpio4 1 GPIO_ACTIVE_LOW>, + <&gpio4 2 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + num-chipselects = <1>; + status = "okay"; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio7 15 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-reset-delay = <1>; + phy-supply = <®_fec1_pwdn>; + phy-handle = <ðphy1_0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + /* LED1: Link/Activity, LED2: Error */ + ti,led-function = <0x0db0>; + /* Active low, LED1 and LED2 driven by phy */ + ti,led-ctrl = <0x1001>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&i2c1 { + lm75: temperature-sensor@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + tlv320aic32x4: audio-codec@18 { + compatible = "ti,tlv320aic32x4"; + reg = <0x18>; + clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; + clock-names = "mclk"; + ldoin-supply = <®_audio_3v3>; + iov-supply = <®_audio_3v3>; + }; + + pca9555: gpio-expander@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pca9555>; + gpio-controller; + #gpio-cells = <2>; + interrupt-parent = <&gpio7>; + interrupts = <12 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_mba7_1>; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x7c + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x74 + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x74 + MX7D_PAD_UART1_RX_DATA__GPIO4_IO0 0x74 + MX7D_PAD_UART1_TX_DATA__GPIO4_IO1 0x74 + MX7D_PAD_UART2_RX_DATA__GPIO4_IO2 0x74 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX7D_PAD_ECSPI2_MISO__ECSPI2_MISO 0x7c + MX7D_PAD_ECSPI2_MOSI__ECSPI2_MOSI 0x74 + MX7D_PAD_ECSPI2_SCLK__ECSPI2_SCLK 0x74 + MX7D_PAD_ECSPI2_SS0__ECSPI2_SS0 0x74 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x02 + MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x00 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x71 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x71 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x71 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x71 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x71 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x71 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x79 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x79 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x79 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x79 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x79 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x79 + /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ + MX7D_PAD_ENET1_COL__GPIO7_IO15 0x40000070 + /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x40000078 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x5a + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x52 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x5a + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x52 + >; + }; + + pinctrl_hog_mba7_1: hogmba71grp { + fsl,pins = < + /* Limitation: WDOG2_B / WDOG2_RESET not usable */ + MX7D_PAD_ENET1_RX_CLK__GPIO7_IO13 0x4000007c + MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x40000074 + /* #BOOT_EN */ + MX7D_PAD_UART2_TX_DATA__GPIO4_IO3 0x40000010 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x40000078 + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x40000078 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x40000078 + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x40000078 + >; + }; + + + pinctrl_pca9555: pca95550grp { + fsl,pins = < + MX7D_PAD_ENET1_TX_CLK__GPIO7_IO12 0x78 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x7e + MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x76 + MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x76 + MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x7e + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_SYNC__UART4_DCE_RX 0x7e + MX7D_PAD_SAI2_TX_BCLK__UART4_DCE_TX 0x76 + MX7D_PAD_SAI2_RX_DATA__UART4_DCE_CTS 0x76 + MX7D_PAD_SAI2_TX_DATA__UART4_DCE_RTS 0x7e + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX7D_PAD_I2C4_SCL__UART5_DCE_RX 0x7e + MX7D_PAD_I2C4_SDA__UART5_DCE_TX 0x76 + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__UART6_DCE_RX 0x7d + MX7D_PAD_EPDC_DATA09__UART6_DCE_TX 0x75 + MX7D_PAD_EPDC_DATA11__UART6_DCE_CTS 0x75 + MX7D_PAD_EPDC_DATA10__UART6_DCE_RTS 0x7d + >; + }; + + pinctrl_uart7: uart7grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA12__UART7_DCE_RX 0x7e + MX7D_PAD_EPDC_DATA13__UART7_DCE_TX 0x76 + MX7D_PAD_EPDC_DATA15__UART7_DCE_CTS 0x76 + /* Limitation: RTS is not connected */ + MX7D_PAD_EPDC_DATA14__UART7_DCE_RTS 0x7e + >; + }; + + pinctrl_usdhc1_gpio: usdhc1grp_gpio { + fsl,pins = < + /* WP */ + MX7D_PAD_SD1_WP__GPIO5_IO1 0x7c + /* CD */ + MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x7c + /* VSELECT */ + MX7D_PAD_GPIO1_IO08__SD1_VSELECT 0x59 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5e + MX7D_PAD_SD1_CLK__SD1_CLK 0x57 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5e + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5e + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5e + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5e + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a + MX7D_PAD_SD1_CLK__SD1_CLK 0x57 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b + MX7D_PAD_SD1_CLK__SD1_CLK 0x57 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_pwm1: pwm1grp { + fsl,pins = < + /* LCD_CONTRAST */ + MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x50 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__USB_OTG1_OC 0x5c + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 + >; + }; + + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 + >; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + assigned-clocks = <&clks IMX7D_UART3_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + assigned-clocks = <&clks IMX7D_UART5_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart7 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart7>; + assigned-clocks = <&clks IMX7D_UART7_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + vbus-supply = <®_usb_otg1_vbus>; + srp-disable; + hnp-disable; + adp-disable; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sd1_vmmc>; + bus-width = <4>; + no-1-8-v; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; +}; diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi new file mode 100644 index 000000000000..85fe461e5e67 --- /dev/null +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ Systems TQMa7x boards with full mounted PCB. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +/ { + memory@80000000 { + device_type = "memory"; + /* 512 MB - default configuration */ + reg = <0x80000000 0x20000000>; + }; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + clock-frequency = <100000>; + status = "okay"; + + pfuze3000: pmic@8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic1>; + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + /* use sw1c_reg to align with pfuze100/pfuze200 */ + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + /* NXP SE97BTP with temperature sensor + eeprom */ + se97b: temperature-sensor-eeprom@1e { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1e>; + status = "okay"; + }; + + /* ST M24C64 */ + m24c64: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + status = "okay"; + }; + + at24c02: eeprom@56 { + compatible = "atmel,24c02"; + reg = <0x56>; + pagesize = <16>; + status = "okay"; + }; + + ds1339: rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078 + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078 + >; + }; + + pinctrl_pmic1: pmic1grp { + fsl,pins = < + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x56 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5a + MX7D_PAD_SD3_CLK__SD3_CLK 0x51 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x5b + MX7D_PAD_SD3_CLK__SD3_CLK 0x51 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b + MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b + >; + }; +}; + +&sdma { + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; + assigned-clock-rates = <400000000>; + bus-width = <8>; + non-removable; + vmmc-supply = <&vgen4_reg>; + vqmmc-supply = <&sw2_reg>; + status = "okay"; +}; + +&wdog1 { + status = "okay"; +}; -- cgit From c924f0c07e482c92a74173611d7a2611f91bab22 Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Wed, 3 Apr 2019 08:44:26 +0200 Subject: ARM: dts: tq imx7s board support This adds support for the TQ TQMa7S SoM together with the MBa7 carrier board and it's based on the NXP i.MX7Solo SoC. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7s-mba7.dts | 18 ++++++++++++++++++ arch/arm/boot/dts/imx7s-tqma7.dtsi | 11 +++++++++++ 3 files changed, 30 insertions(+) create mode 100644 arch/arm/boot/dts/imx7s-mba7.dts create mode 100644 arch/arm/boot/dts/imx7s-tqma7.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 1234bd95d85c..e69e2462e2eb 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -588,6 +588,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ imx7s-colibri-eval-v3.dtb \ + imx7s-mba7.dtb \ imx7s-warp.dtb dtb-$(CONFIG_SOC_IMX7ULP) += \ imx7ulp-evk.dtb diff --git a/arch/arm/boot/dts/imx7s-mba7.dts b/arch/arm/boot/dts/imx7s-mba7.dts new file mode 100644 index 000000000000..a143d566a38b --- /dev/null +++ b/arch/arm/boot/dts/imx7s-mba7.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Source for TQ Systems TQMa7S board on MBa7 carrier board. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7s-tqma7.dtsi" +#include "imx7-mba7.dtsi" + +/ { + model = "TQ Systems TQMa7S board on MBa7 carrier board"; + compatible = "tq,imx7s-mba7", "fsl,imx7s"; +}; diff --git a/arch/arm/boot/dts/imx7s-tqma7.dtsi b/arch/arm/boot/dts/imx7s-tqma7.dtsi new file mode 100644 index 000000000000..5f5433eb7dd7 --- /dev/null +++ b/arch/arm/boot/dts/imx7s-tqma7.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ Systems TQMa7S board with NXP i.MX7Solo SoC. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +#include "imx7s.dtsi" +#include "imx7-tqma7.dtsi" -- cgit From 684a586741e2be211ca9bc800ae631b69fb3f8aa Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Wed, 3 Apr 2019 08:44:27 +0200 Subject: ARM: dts: tq imx7d board support This adds support for the TQ TQMa7D SoM together with the MBa7 carrier board and it's based on the NXP i.MX7Dual SoC. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7d-mba7.dts | 119 +++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx7d-tqma7.dtsi | 11 ++++ 3 files changed, 131 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-mba7.dts create mode 100644 arch/arm/boot/dts/imx7d-tqma7.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index e69e2462e2eb..c6eec98bc3c2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -580,6 +580,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-cl-som-imx7.dtb \ imx7d-colibri-emmc-eval-v3.dtb \ imx7d-colibri-eval-v3.dtb \ + imx7d-mba7.dtb \ imx7d-nitrogen7.dtb \ imx7d-pico-hobbit.dtb \ imx7d-pico-pi.dtb \ diff --git a/arch/arm/boot/dts/imx7d-mba7.dts b/arch/arm/boot/dts/imx7d-mba7.dts new file mode 100644 index 000000000000..221274c73dbd --- /dev/null +++ b/arch/arm/boot/dts/imx7d-mba7.dts @@ -0,0 +1,119 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Source for TQ Systems TQMa7D board on MBa7 carrier board. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +/dts-v1/; + +#include "imx7d-tqma7.dtsi" +#include "imx7-mba7.dtsi" + +/ { + model = "TQ Systems TQMa7D board on MBa7 carrier board"; + compatible = "tq,imx7d-mba7", "fsl,imx7d"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + phy-mode = "rgmii-id"; + phy-reset-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + phy-reset-duration = <1>; + phy-reset-delay = <1>; + phy-supply = <®_fec2_pwdn>; + phy-handle = <ðphy2_0>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy2_0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + ti,rx-internal-delay = ; + ti,tx-internal-delay = ; + ti,fifo-depth = ; + /* LED1: Link/Activity, LED2: error */ + ti,led-function = <0x0db0>; + /* active low, LED1/2 driven by phy */ + ti,led-ctrl = <0x1001>; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_mba7_1>; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET2_MDIO 0x02 + MX7D_PAD_SD2_WP__ENET2_MDC 0x00 + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x71 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x71 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x71 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x71 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x71 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x71 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x79 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x79 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x79 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x79 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x79 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x79 + /* Reset: SION, 100kPU, SRE_FAST, DSE_X1 */ + MX7D_PAD_EPDC_BDR0__GPIO2_IO28 0x40000070 + /* INT/PWDN: SION, 100kPU, HYS, SRE_FAST, DSE_X1 */ + MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 0x40000078 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* #pcie_wake */ + MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 0x70 + /* #pcie_rst */ + MX7D_PAD_SD2_CLK__GPIO5_IO12 0x70 + /* #pcie_dis */ + MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x70 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_usbotg2: usbotg2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__USB_OTG2_OC 0x5c + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x59 + >; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + /* 1.5V logically from 3.3V */ + /* probe deferral not supported */ + /* pcie-bus-supply = <®_mpcie_1v5>; */ + reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; + disable-gpio = <&gpio2 29 GPIO_ACTIVE_LOW>; + power-on-gpio = <&gpio2 30 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usbotg2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg2>; + vbus-supply = <®_usb_otg2_vbus>; + srp-disable; + hnp-disable; + adp-disable; + dr_mode = "host"; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx7d-tqma7.dtsi b/arch/arm/boot/dts/imx7d-tqma7.dtsi new file mode 100644 index 000000000000..8ad3048dac0d --- /dev/null +++ b/arch/arm/boot/dts/imx7d-tqma7.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 +/* + * Device Tree Include file for TQ Systems TQMa7D board with NXP i.MX7Dual SoC. + * + * Copyright (C) 2016 TQ Systems GmbH + * Author: Markus Niebel + * Copyright (C) 2019 Bruno Thomsen + */ + +#include "imx7d.dtsi" +#include "imx7-tqma7.dtsi" -- cgit From 8137474b9dd4298f7f0ed541b859f30465cbd8a8 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Thu, 28 Mar 2019 14:25:12 +0000 Subject: ARM: dts: imx7s: add mipi phy power domain Add power domain index 0 related with mipi-phy to imx7s. While at it rename pcie power-domain node to remove pgc prefix. Signed-off-by: Rui Miguel Silva Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index e88f53a4c7f4..9a680d3d6424 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -606,7 +606,13 @@ #address-cells = <1>; #size-cells = <0>; - pgc_pcie_phy: pgc-power-domain@1 { + pgc_mipi_phy: power-domain@0 { + #power-domain-cells = <0>; + reg = <0>; + power-supply = <®_1p0d>; + }; + + pgc_pcie_phy: power-domain@1 { #power-domain-cells = <0>; reg = <1>; power-supply = <®_1p0d>; -- cgit From 94a905a79f2cf337376c195acda406a2385792f4 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Thu, 28 Mar 2019 14:25:13 +0000 Subject: ARM: dts: imx7s: add multiplexer controls The IOMUXC General Purpose Register has bitfield to control video bus multiplexer to control the CSI input between the MIPI-CSI2 and parallel interface. Add that register and mask. Signed-off-by: Rui Miguel Silva Reviewed-by: Philipp Zabel Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 9a680d3d6424..792efcd2caa1 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -497,8 +497,15 @@ gpr: iomuxc-gpr@30340000 { compatible = "fsl,imx7d-iomuxc-gpr", - "fsl,imx6q-iomuxc-gpr", "syscon"; + "fsl,imx6q-iomuxc-gpr", "syscon", + "simple-mfd"; reg = <0x30340000 0x10000>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <0>; + mux-reg-masks = <0x14 0x00000010>; + }; }; ocotp: ocotp-ctrl@30350000 { -- cgit From 6a2736fccfb4491c338286bd025c04c8233c36f5 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Thu, 28 Mar 2019 14:25:14 +0000 Subject: ARM: dts: imx7s: Add video mux, csi and mipi_csi Add device tree nodes for csi, video multiplexer and mipi-csi. Signed-off-by: Rui Miguel Silva Reviewed-by: Laurent Pinchart Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 75 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 792efcd2caa1..3286838105c6 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include "imx7d-pinfunc.h" / { @@ -506,6 +507,34 @@ #mux-control-cells = <0>; mux-reg-masks = <0x14 0x00000010>; }; + + video_mux: csi-mux { + compatible = "video-mux"; + mux-controls = <&mux 0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + csi_mux_from_mipi_vc0: endpoint { + remote-endpoint = <&mipi_vc0_to_csi_mux>; + }; + }; + + port@2 { + reg = <2>; + + csi_mux_to_csi: endpoint { + remote-endpoint = <&csi_from_csi_mux>; + }; + }; + }; }; ocotp: ocotp-ctrl@30350000 { @@ -709,6 +738,23 @@ status = "disabled"; }; + csi: csi@30710000 { + compatible = "fsl,imx7-csi"; + reg = <0x30710000 0x10000>; + interrupts = ; + clocks = <&clks IMX7D_CLK_DUMMY>, + <&clks IMX7D_CSI_MCLK_ROOT_CLK>, + <&clks IMX7D_CLK_DUMMY>; + clock-names = "axi", "mclk", "dcic"; + status = "disabled"; + + port { + csi_from_csi_mux: endpoint { + remote-endpoint = <&csi_mux_to_csi>; + }; + }; + }; + lcdif: lcdif@30730000 { compatible = "fsl,imx7d-lcdif", "fsl,imx28-lcdif"; reg = <0x30730000 0x10000>; @@ -718,6 +764,35 @@ clock-names = "pix", "axi"; status = "disabled"; }; + + mipi_csi: mipi-csi@30750000 { + compatible = "fsl,imx7-mipi-csi2"; + reg = <0x30750000 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_MIPI_CSI_ROOT_CLK>, + <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; + clock-names = "pclk", "wrap", "phy"; + power-domains = <&pgc_mipi_phy>; + phy-supply = <®_1p0d>; + resets = <&src IMX7_RESET_MIPI_PHY_MRST>; + reset-names = "mrst"; + status = "disabled"; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_vc0_to_csi_mux: endpoint { + remote-endpoint = <&csi_mux_from_mipi_vc0>; + }; + }; + }; }; aips3: aips-bus@30800000 { -- cgit From 2cd37a97d1ea5861b33822c364554061244b1322 Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Thu, 28 Mar 2019 14:25:15 +0000 Subject: ARM: dts: imx7s-warp: add csi and mipi_csi node Add and enable csi and mipi_csi nodes. Signed-off-by: Rui Miguel Silva Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index b1e956205e9a..2d1a0105e6a6 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -77,6 +77,10 @@ assigned-clock-rates = <884736000>; }; +&csi { + status = "okay"; +}; + &i2c1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; @@ -213,6 +217,12 @@ }; }; +&mipi_csi { + clock-frequency = <166000000>; + fsl,csis-hs-settle = <3>; + status = "okay"; +}; + &sai1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai1>; @@ -279,6 +289,10 @@ status = "okay"; }; +&video_mux { + status = "okay"; +}; + &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; -- cgit From e345fd42493c1e3517207762f2588b9e293fa47f Mon Sep 17 00:00:00 2001 From: Rui Miguel Silva Date: Thu, 28 Mar 2019 14:25:16 +0000 Subject: ARM: dts: imx7s-warp: add ov2680 sensor node Warp7 comes with a Omnivision OV2680 sensor, add the node here to make complete the camera data path for this system. Add the needed regulator to the analog voltage supply, the port and endpoints in mipi_csi node and the pinctrl for the reset gpio. Signed-off-by: Rui Miguel Silva Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s-warp.dts | 45 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts index 2d1a0105e6a6..d6b4888fa686 100644 --- a/arch/arm/boot/dts/imx7s-warp.dts +++ b/arch/arm/boot/dts/imx7s-warp.dts @@ -55,6 +55,14 @@ regulator-always-on; }; + reg_peri_3p15v: regulator-peri-3p15v { + compatible = "regulator-fixed"; + regulator-name = "peri_3p15v_reg"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "imx7-sgtl5000"; @@ -184,6 +192,27 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; + + ov2680: camera@36 { + compatible = "ovti,ov2680"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ov2680>; + reg = <0x36>; + clocks = <&osc>; + clock-names = "xvclk"; + reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + DOVDD-supply = <&sw2_reg>; + DVDD-supply = <&sw2_reg>; + AVDD-supply = <®_peri_3p15v>; + + port { + ov2680_to_mipi: endpoint { + remote-endpoint = <&mipi_from_sensor>; + clock-lanes = <0>; + data-lanes = <1>; + }; + }; + }; }; &i2c3 { @@ -221,6 +250,16 @@ clock-frequency = <166000000>; fsl,csis-hs-settle = <3>; status = "okay"; + + port@0 { + reg = <0>; + + mipi_from_sensor: endpoint { + remote-endpoint = <&ov2680_to_mipi>; + data-lanes = <1>; + }; + + }; }; &sai1 { @@ -347,6 +386,12 @@ >; }; + pinctrl_ov2680: ov2660grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14 + >; + }; + pinctrl_sai1: sai1grp { fsl,pins = < MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f -- cgit From b14c872eebc501b9640b04f4a152df51d6eaf2fc Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:16 -0700 Subject: ARM: dts: imx6qdl: Specify IMX6QDL_CLK_IPG as "ipg" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX6QDL_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality(this at least breaks RAVE SP serdev driver on RDU2). Fix the code to specify IMX6QDL_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Reviewed-by: Lucas Stach Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Tested-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index 38b18a007f48..b3a77bcf00d5 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -928,7 +928,7 @@ compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clks IMX6QDL_CLK_SDMA>, + clocks = <&clks IMX6QDL_CLK_IPG>, <&clks IMX6QDL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; -- cgit From 8979117765c19edc3b01cc0ef853537bf93eea4b Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:17 -0700 Subject: ARM: dts: imx6sx: Specify IMX6SX_CLK_IPG as "ipg" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX6SX_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX6SX_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index df0c59519886..b16a123990a2 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -820,7 +820,7 @@ compatible = "fsl,imx6sx-sdma", "fsl,imx6q-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; - clocks = <&clks IMX6SX_CLK_SDMA>, + clocks = <&clks IMX6SX_CLK_IPG>, <&clks IMX6SX_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; -- cgit From 412b032a1dc72fc9d1c258800355efa6671b6315 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:18 -0700 Subject: ARM: dts: imx7d: Specify IMX7D_CLK_IPG as "ipg" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX7D_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX7D_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 3286838105c6..0b01109ac0a9 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -1155,8 +1155,8 @@ compatible = "fsl,imx7d-sdma", "fsl,imx35-sdma"; reg = <0x30bd0000 0x10000>; interrupts = ; - clocks = <&clks IMX7D_SDMA_CORE_CLK>, - <&clks IMX7D_AHB_CHANNEL_ROOT_CLK>; + clocks = <&clks IMX7D_IPG_ROOT_CLK>, + <&clks IMX7D_SDMA_CORE_CLK>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; -- cgit From 7b3132ecefdd1fcdf6b86e62021d0e55ea8034db Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:19 -0700 Subject: ARM: dts: imx6ul: Specify IMX6UL_CLK_IPG as "ipg" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX6UL_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX6UL_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6ul.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index a77bbcae4571..bbf010c73336 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -708,7 +708,7 @@ "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; - clocks = <&clks IMX6UL_CLK_SDMA>, + clocks = <&clks IMX6UL_CLK_IPG>, <&clks IMX6UL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; -- cgit From c5ed5daa65d5f665e666b76c3dbfa503066defde Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:20 -0700 Subject: ARM: dts: imx6sll: Specify IMX6SLL_CLK_IPG as "ipg" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX6SLL_CLK_SDMA result in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX6SLL_CLK_IPG as "ipg" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index 62847c68330b..ed598d72038c 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -621,7 +621,7 @@ compatible = "fsl,imx6sll-sdma", "fsl,imx35-sdma"; reg = <0x020ec000 0x4000>; interrupts = ; - clocks = <&clks IMX6SLL_CLK_SDMA>, + clocks = <&clks IMX6SLL_CLK_IPG>, <&clks IMX6SLL_CLK_SDMA>; clock-names = "ipg", "ahb"; #dma-cells = <3>; -- cgit From cc839d0f8c284fcb7591780b568f13415bbb737c Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:21 -0700 Subject: ARM: dts: imx6sx: Specify IMX6SX_CLK_IPG as "ahb" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX6SL_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX6SL_CLK_AHB as "ahb" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sl.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi index 0ad5d507abec..9ddbeea64b72 100644 --- a/arch/arm/boot/dts/imx6sl.dtsi +++ b/arch/arm/boot/dts/imx6sl.dtsi @@ -748,7 +748,7 @@ reg = <0x020ec000 0x4000>; interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clks IMX6SL_CLK_SDMA>, - <&clks IMX6SL_CLK_SDMA>; + <&clks IMX6SL_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; /* imx6sl reuses imx6q sdma firmware */ -- cgit From 28c168018e0902c67eb9c60d0fc4c8aa166c4efe Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:22 -0700 Subject: ARM: dts: imx53: Specify IMX5_CLK_IPG as "ahb" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX5_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX5_CLK_AHB as "ahb" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index b3300300aabe..9b672ed2486d 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -702,7 +702,7 @@ reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; -- cgit From 918bbde8085ae147a43dcb491953e0dd8f3e9d6a Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:23 -0700 Subject: ARM: dts: imx51: Specify IMX5_CLK_IPG as "ahb" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX5_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX5_CLK_AHB as "ahb" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index a5ee25cedc10..0a4b9a5d9a9c 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -489,7 +489,7 @@ reg = <0x83fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; -- cgit From b7b4fda2636296471e29b78c2aa9535d7bedb7a0 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Thu, 28 Mar 2019 23:49:24 -0700 Subject: ARM: dts: imx50: Specify IMX5_CLK_IPG as "ahb" clock to SDMA Since 25aaa75df1e6 SDMA driver uses clock rates of "ipg" and "ahb" clock to determine if it needs to configure the IP block as operating at 1:1 or 1:2 clock ratio (ACR bit in SDMAARM_CONFIG). Specifying both clocks as IMX5_CLK_SDMA results in driver incorrectly thinking that ratio is 1:1 which results in broken SDMA funtionality. Fix the code to specify IMX5_CLK_AHB as "ahb" clock for SDMA, to avoid detecting incorrect clock ratio. Signed-off-by: Andrey Smirnov Cc: Angus Ainslie (Purism) Cc: Chris Healy Cc: Lucas Stach Cc: Fabio Estevam Cc: Shawn Guo Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx50.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx50.dtsi b/arch/arm/boot/dts/imx50.dtsi index 5dd61bff3b76..0bfe7c91d0eb 100644 --- a/arch/arm/boot/dts/imx50.dtsi +++ b/arch/arm/boot/dts/imx50.dtsi @@ -430,7 +430,7 @@ reg = <0x63fb0000 0x4000>; interrupts = <6>; clocks = <&clks IMX5_CLK_SDMA_GATE>, - <&clks IMX5_CLK_SDMA_GATE>; + <&clks IMX5_CLK_AHB>; clock-names = "ipg", "ahb"; #dma-cells = <3>; fsl,sdma-ram-script-name = "imx/sdma/sdma-imx50.bin"; -- cgit From 1268d8339ca46e3a5c642b38baa1512a19378af4 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 29 Mar 2019 13:13:10 -0500 Subject: ARM: dts: mx6qdl-zii-rdu2: Use new CODEC reset pin name The correct DT property for specifying a GPIO used for reset is "reset-gpios", the driver now accepts this name, use it here. Note the GPIO polarity in the driver was ignored before and always assumed to be active low, when all the DTs are fixed we will start respecting the specified polarity. Switch polarity in DT to the currently assumed one, this way when the driver changes the behavior will not change. Signed-off-by: Andrew F. Davis Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 9f664897bf4e..7fa989ec403b 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -385,7 +385,7 @@ AVDD-supply = <®_3p3v>; IOVDD-supply = <®_3p3v>; DVDD-supply = <&vgen4_reg>; - gpio-reset = <&gpio1 2 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; }; accel@1c { @@ -578,7 +578,7 @@ AVDD-supply = <®_3p3v>; IOVDD-supply = <®_3p3v>; DVDD-supply = <&vgen4_reg>; - gpio-reset = <&gpio1 0 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; }; touchscreen@20 { -- cgit From c83bbdc227138d6fdc3ddfa8f7396d8f2b631ecf Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 29 Mar 2019 13:13:11 -0500 Subject: ARM: dts: imx6qdl-gw5903: Use new CODEC reset pin name The correct DT property for specifying a GPIO used for reset is "reset-gpios", the driver now accepts this name, use it here. Signed-off-by: Andrew F. Davis Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-gw5903.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi index 9cb9a7439121..aee9221f0f29 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi @@ -311,7 +311,7 @@ tlv320aic3105: codec@18 { compatible = "ti,tlv320aic3x"; reg = <0x18>; - gpio-reset = <&gpio5 17 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; clocks = <&clks IMX6QDL_CLK_CKO>; ai3x-micbias-vg = <2>; /* MICBIAS_2_5V */ /* Regulators */ -- cgit From cadb32a9c118a1443a95c7a0bbec086b773a0f32 Mon Sep 17 00:00:00 2001 From: "Andrew F. Davis" Date: Fri, 29 Mar 2019 13:13:12 -0500 Subject: ARM: dts: imx6qdl-var-dart: Use new CODEC reset pin name The correct DT property for specifying a GPIO used for reset is "reset-gpios", the driver now accepts this name, use it here. Signed-off-by: Andrew F. Davis Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6qdl-var-dart.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi index 8752a4961c47..c41cac502bac 100644 --- a/arch/arm/boot/dts/imx6qdl-var-dart.dtsi +++ b/arch/arm/boot/dts/imx6qdl-var-dart.dtsi @@ -183,7 +183,7 @@ IOVDD-supply = <®_3p3v>; DVDD-supply = <®_3p3v>; ai3x-ocmv = <0>; - gpio-reset = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; }; }; -- cgit From 891d940aef2f98ba043c6e63008a99dbdf68bdc6 Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Sun, 31 Mar 2019 21:16:02 +0200 Subject: ARM: dts: imx50: Add Kobo Aura DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The Kobo Aura is an e-book reader released in 2013. With the devicetree in its current state, the kernel will boot and run for about ten seconds. To solve this, the embedded controller needs to be told that the system should stay powered on. This will be done in a later patchset. - The IOMUXC mode bits for the SD interfaces were taken from the vendor's U-Boot fork. - The bus width of the eMMC is 4 bits in the vendor kernel, but I achieved better performance with 8 bits. - The SDIO clock frequency for the WiFi chip is 25MHz in the vendor kernel, but the WiFi chip (BCM43362) supports 50MHz, which works reliably on this board and gives slightly better performance. - The I2C pins' IOMUXC settings come from the vendor's U-Boot fork. Signed-off-by: Jonathan Neuschäfer Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx50-kobo-aura.dts | 258 ++++++++++++++++++++++++++++++++++ 2 files changed, 260 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx50-kobo-aura.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index c6eec98bc3c2..7776f97c4497 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -363,7 +363,8 @@ dtb-$(CONFIG_SOC_IMX35) += \ imx35-eukrea-mbimxsd35-baseboard.dtb \ imx35-pdk.dtb dtb-$(CONFIG_SOC_IMX50) += \ - imx50-evk.dtb + imx50-evk.dtb \ + imx50-kobo-aura.dtb dtb-$(CONFIG_SOC_IMX51) += \ imx51-apf51.dtb \ imx51-apf51dev.dtb \ diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts new file mode 100644 index 000000000000..a0eaf869b913 --- /dev/null +++ b/arch/arm/boot/dts/imx50-kobo-aura.dts @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright 2019 Jonathan Neuschäfer +// +// The Kobo Aura e-book reader, model N514. The mainboard is marked as E606F0B. + +/dts-v1/; +#include "imx50.dtsi" +#include + +/ { + model = "Kobo Aura (N514)"; + compatible = "kobo,aura", "fsl,imx50"; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + memory@70000000 { + device_type = "memory"; + reg = <0x70000000 0x10000000>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + on { + label = "kobo_aura:orange:on"; + gpios = <&gpio6 24 GPIO_ACTIVE_LOW>; + panic-indicator; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + power { + label = "Power Button"; + gpios = <&gpio4 10 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + hallsensor { + label = "Hallsensor"; + gpios = <&gpio5 15 GPIO_ACTIVE_LOW>; + linux,code = ; + linux,input-type = ; + }; + + frontlight { + label = "Frontlight"; + gpios = <&gpio4 1 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + }; + + sd2_pwrseq: pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_reset>; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + }; + + sd2_vmmc: gpio-regulator { + compatible = "regulator-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2_vmmc>; + regulator-name = "vmmc"; + states = <3300000 0>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-gpio = <&gpio4 12 GPIO_ACTIVE_LOW>; + startup-delay-us = <100000>; + }; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd1>; + max-frequency = <50000000>; + bus-width = <4>; + cd-gpios = <&gpio5 17 GPIO_ACTIVE_LOW>; + disable-wp; + status = "okay"; + + /* External µSD card */ +}; + +&esdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd2>; + bus-width = <4>; + max-frequency = <50000000>; + disable-wp; + mmc-pwrseq = <&sd2_pwrseq>; + vmmc-supply = <&sd2_vmmc>; + status = "okay"; + + /* CyberTan WC121 SDIO WiFi (BCM43362) */ +}; + +&esdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sd3>; + bus-width = <8>; + non-removable; + max-frequency = <50000000>; + disable-wp; + status = "okay"; + + /* Internal eMMC */ +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + /* TODO: ektf2132 touch controller at 0x15 */ +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + /* TODO: TPS65185 PMIC for E Ink at 0x68 */ +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + /* TODO: embedded controller at 0x43 */ +}; + +&iomuxc { + pinctrl_gpiokeys: gpiokeys { + fsl,pins = < + MX50_PAD_CSPI_MISO__GPIO4_10 0x0 + MX50_PAD_SD2_D7__GPIO5_15 0x0 + MX50_PAD_KEY_ROW0__GPIO4_1 0x0 + >; + }; + + pinctrl_i2c1: i2c1 { + fsl,pins = < + MX50_PAD_I2C1_SCL__I2C1_SCL 0x400001fd + MX50_PAD_I2C1_SDA__I2C1_SDA 0x400001fd + >; + }; + + pinctrl_i2c2: i2c2 { + fsl,pins = < + MX50_PAD_I2C2_SCL__I2C2_SCL 0x400001fd + MX50_PAD_I2C2_SDA__I2C2_SDA 0x400001fd + >; + }; + + pinctrl_i2c3: i2c3 { + fsl,pins = < + MX50_PAD_I2C3_SCL__I2C3_SCL 0x400001fd + MX50_PAD_I2C3_SDA__I2C3_SDA 0x400001fd + >; + }; + + pinctrl_leds: leds { + fsl,pins = < + MX50_PAD_PWM1__GPIO6_24 0x0 + >; + }; + + pinctrl_sd1: sd1 { + fsl,pins = < + MX50_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 + MX50_PAD_SD1_CLK__ESDHC1_CLK 0xd4 + MX50_PAD_SD1_D0__ESDHC1_DAT0 0x1d4 + MX50_PAD_SD1_D1__ESDHC1_DAT1 0x1d4 + MX50_PAD_SD1_D2__ESDHC1_DAT2 0x1d4 + MX50_PAD_SD1_D3__ESDHC1_DAT3 0x1d4 + + MX50_PAD_SD2_CD__GPIO5_17 0x0 + >; + }; + + pinctrl_sd2: sd2 { + fsl,pins = < + MX50_PAD_SD2_CMD__ESDHC2_CMD 0x1e4 + MX50_PAD_SD2_CLK__ESDHC2_CLK 0xd4 + MX50_PAD_SD2_D0__ESDHC2_DAT0 0x1d4 + MX50_PAD_SD2_D1__ESDHC2_DAT1 0x1d4 + MX50_PAD_SD2_D2__ESDHC2_DAT2 0x1d4 + MX50_PAD_SD2_D3__ESDHC2_DAT3 0x1d4 + >; + }; + + pinctrl_sd2_reset: sd2-reset { + fsl,pins = < + MX50_PAD_ECSPI2_MOSI__GPIO4_17 0x0 + >; + }; + + pinctrl_sd2_vmmc: sd2-vmmc { + fsl,pins = < + MX50_PAD_ECSPI1_SCLK__GPIO4_12 0x0 + >; + }; + + pinctrl_sd3: sd3 { + fsl,pins = < + MX50_PAD_SD3_CMD__ESDHC3_CMD 0x1e4 + MX50_PAD_SD3_CLK__ESDHC3_CLK 0xd4 + MX50_PAD_SD3_D0__ESDHC3_DAT0 0x1d4 + MX50_PAD_SD3_D1__ESDHC3_DAT1 0x1d4 + MX50_PAD_SD3_D2__ESDHC3_DAT2 0x1d4 + MX50_PAD_SD3_D3__ESDHC3_DAT3 0x1d4 + MX50_PAD_SD3_D4__ESDHC3_DAT4 0x1d4 + MX50_PAD_SD3_D5__ESDHC3_DAT5 0x1d4 + MX50_PAD_SD3_D6__ESDHC3_DAT6 0x1d4 + MX50_PAD_SD3_D7__ESDHC3_DAT7 0x1d4 + >; + }; + + pinctrl_uart2: uart2 { + fsl,pins = < + MX50_PAD_UART2_TXD__UART2_TXD_MUX 0x1e4 + MX50_PAD_UART2_RXD__UART2_RXD_MUX 0x1e4 + >; + }; + + pinctrl_usbphy: usbphy { + fsl,pins = < + MX50_PAD_ECSPI2_SS0__GPIO4_19 0x0 + >; + }; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbotg { + phy_type = "utmi_wide"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbphy>; + vbus-detect-gpio = <&gpio4 19 GPIO_ACTIVE_LOW>; +}; -- cgit From 4b08ecc7c68525e6e472a3e10ca1ba00e0facb26 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 1 Apr 2019 02:51:11 +0000 Subject: ARM: dts: imx6sll: add cooling-cells for cpu-freq cooling device Add #cooling-cells for i.MX6SLL cpu-freq cooling device usage. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6sll.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi index ed598d72038c..1b4899f0fcde 100644 --- a/arch/arm/boot/dts/imx6sll.dtsi +++ b/arch/arm/boot/dts/imx6sll.dtsi @@ -64,6 +64,7 @@ 198000 1175000 >; clock-latency = <61036>; /* two CLK32 periods */ + #cooling-cells = <2>; clocks = <&clks IMX6SLL_CLK_ARM>, <&clks IMX6SLL_CLK_PLL2_PFD2>, <&clks IMX6SLL_CLK_STEP>, -- cgit From 45d91250405b08a13c41d879eb70d71f22773032 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 2 Apr 2019 14:25:45 -0500 Subject: ARM: dts: imx6q-logicpd: Enable Analog audio capture The original submission had functional audio out and was based on reviewing other boards using the same wm8962 codec. However, the Logic PD board uses an analog microphone which was being disabled for a digital mic. This patch corrects that and explicitly sets the gpio-cfg pins all to 0x0000 which allows the analog microphone to capture audio. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi index fb01fa6e4224..12b18c801b98 100644 --- a/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi +++ b/arch/arm/boot/dts/imx6-logicpd-baseboard.dtsi @@ -247,9 +247,9 @@ gpio-cfg = < 0x0000 /* 0:Default */ 0x0000 /* 1:Default */ - 0x0013 /* 2:FN_DMICCLK */ + 0x0000 /* 2:FN_DMICCLK */ 0x0000 /* 3:Default */ - 0x8014 /* 4:FN_DMICCDAT */ + 0x0000 /* 4:FN_DMICCDAT */ 0x0000 /* 5:Default */ >; }; -- cgit From 6fd6d6f6a2f06cb921a0185072854c3d35d86ff1 Mon Sep 17 00:00:00 2001 From: Adam Ford Date: Tue, 2 Apr 2019 14:25:46 -0500 Subject: ARM: dts: imx6q-logicpd: Shutdown LCD regulator during suspend The LCD power sequencer is very finicky. The backlight cannot be driven until after the sequencer is done. Until now, the regulators were marked with 'regulator-always-on' to make sure it came up before the backlight. This patch allows the LCD regulators to power down and prevent the backlight from being used again until the sequencer is ready. This reduces standby power consumption by ~100mW. Signed-off-by: Adam Ford Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6q-logicpd.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6q-logicpd.dts b/arch/arm/boot/dts/imx6q-logicpd.dts index 45eb0b7f75f8..d96ae54be338 100644 --- a/arch/arm/boot/dts/imx6q-logicpd.dts +++ b/arch/arm/boot/dts/imx6q-logicpd.dts @@ -21,6 +21,8 @@ panel-lvds0 { compatible = "okaya,rs800480t-7x0gp"; + power-supply = <®_lcd_reset>; + backlight = <&backlight>; port { panel_in_lvds0: endpoint { @@ -38,7 +40,6 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio4 17 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-always-on; vin-supply = <®_3v3>; startup-delay-us = <500000>; }; @@ -52,7 +53,6 @@ regulator-max-microvolt = <3300000>; gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; enable-active-high; - regulator-always-on; vin-supply = <®_lcd>; }; }; -- cgit From 7ee137a96a880ba303684eacc9a4f7a22836b184 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 3 Apr 2019 09:53:13 -0300 Subject: ARM: dts: imx: Switch Zii dts to SPDX identifier Adopt the SPDX license identifier headers to ease license compliance management. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx51-zii-rdu1.dts | 38 +--------------------------- arch/arm/boot/dts/imx6q-zii-rdu2.dts | 38 +--------------------------- arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 38 +--------------------------- arch/arm/boot/dts/imx6qp-zii-rdu2.dts | 38 +--------------------------- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 41 +------------------------------ arch/arm/boot/dts/vf610-zii-dev-rev-c.dts | 41 +------------------------------ 6 files changed, 6 insertions(+), 228 deletions(-) diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index a8220f08dcbf..3596060f52e7 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2017 Zodiac Inflight Innovations - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6q-zii-rdu2.dts b/arch/arm/boot/dts/imx6q-zii-rdu2.dts index 0f0743db2779..a1c5e69d81ba 100644 --- a/arch/arm/boot/dts/imx6q-zii-rdu2.dts +++ b/arch/arm/boot/dts/imx6q-zii-rdu2.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2016-2017 Zodiac Inflight Innovations - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 7fa989ec403b..93be00a60c88 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2016-2017 Zodiac Inflight Innovations - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ #include diff --git a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts index 98bf7a6b2850..57de447c4609 100644 --- a/arch/arm/boot/dts/imx6qp-zii-rdu2.dts +++ b/arch/arm/boot/dts/imx6qp-zii-rdu2.dts @@ -1,42 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2016-2017 Zodiac Inflight Innovations - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index bd79e00bf615..38a394449ee5 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -1,45 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index 6f4a5602cefd..fe111f742ec2 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -1,45 +1,6 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2015, 2016 Zodiac Inflight Innovations - * - * Based on an original 'vf610-twr.dts' which is Copyright 2015, - * Freescale Semiconductor, Inc. - * - * This file is dual-licensed: you can use it either under the terms - * of the GPL or the X11 license, at your option. Note that this dual - * licensing only applies to this file, and not this project as a - * whole. - * - * a) This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * Or, alternatively, - * - * b) Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or - * sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. */ /dts-v1/; -- cgit From 00e3ff8b980b7604dcaa6ea8b2fb157ff8d16c30 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 3 Apr 2019 09:53:14 -0300 Subject: ARM: dts: imx: Use generic node names for Zii dts The devicetree specification recommends using generic node names. Some Zii dts files already follow such recommendation, but some don't, so use generic node names for consistency among the Zii dts files. Signed-off-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-cfu1.dts | 8 ++++---- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 14 +++++++------- arch/arm/boot/dts/vf610-zii-dev-rev-c.dts | 8 ++++---- arch/arm/boot/dts/vf610-zii-dev.dtsi | 4 ++-- arch/arm/boot/dts/vf610-zii-scu4-aib.dts | 10 +++++----- arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts | 8 ++++---- 6 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/arm/boot/dts/vf610-zii-cfu1.dts b/arch/arm/boot/dts/vf610-zii-cfu1.dts index afc25b33bd3b..9466913693ac 100644 --- a/arch/arm/boot/dts/vf610-zii-cfu1.dts +++ b/arch/arm/boot/dts/vf610-zii-cfu1.dts @@ -94,7 +94,7 @@ */ status = "disabled"; - m25p128@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p128", "jedec,spi-nor"; @@ -212,7 +212,7 @@ pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; - pca9554@22 { + io-expander@22 { compatible = "nxp,pca9554"; reg = <0x22>; gpio-controller; @@ -223,13 +223,13 @@ reg = <0x48>; }; - at24c04@52 { + eeprom@52 { compatible = "atmel,24c04"; reg = <0x52>; label = "nvm"; }; - at24c04@54 { + eeprom@54 { compatible = "atmel,24c04"; reg = <0x54>; label = "nameplate"; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 38a394449ee5..8b0baf6a4098 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -299,7 +299,7 @@ &gpio1 8 GPIO_ACTIVE_HIGH>; num-chipselects = <2>; - m25p128@0 { + flash@0 { compatible = "m25p128", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -328,7 +328,7 @@ pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; - gpio5: pca9554@20 { + gpio5: io-expander@20 { compatible = "nxp,pca9554"; reg = <0x20>; gpio-controller; @@ -336,7 +336,7 @@ }; - gpio6: pca9554@22 { + gpio6: io-expander@22 { compatible = "nxp,pca9554"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pca9554_22>; @@ -369,7 +369,7 @@ #size-cells = <0>; reg = <0>; - sfp1: at24c04@50 { + sfp1: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; }; @@ -380,7 +380,7 @@ #size-cells = <0>; reg = <1>; - sfp2: at24c04@50 { + sfp2: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; }; @@ -391,7 +391,7 @@ #size-cells = <0>; reg = <2>; - sfp3: at24c04@50 { + sfp3: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; }; @@ -402,7 +402,7 @@ #size-cells = <0>; reg = <3>; - sfp4: at24c04@50 { + sfp4: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; }; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index fe111f742ec2..778e02c000d1 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -238,7 +238,7 @@ status = "okay"; spi-num-chipselects = <2>; - m25p128@0 { + flash@0 { compatible = "m25p128", "jedec,spi-nor"; #address-cells = <1>; #size-cells = <1>; @@ -274,7 +274,7 @@ * P1 - WE2_CMD * P2 - WE2_CLK */ - gpio5: pca9557@18 { + gpio5: io-expander@18 { compatible = "nxp,pca9557"; reg = <0x18>; gpio-controller; @@ -322,7 +322,7 @@ * IO0 - WE1_CLK * IO1 - WE1_CMD */ - gpio7: pca9554@22 { + gpio7: io-expander@22 { compatible = "nxp,pca9554"; reg = <0x22>; gpio-controller; @@ -332,7 +332,7 @@ }; &i2c1 { - at24mac602@50 { + eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; read-only; diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index 19eb4a849efb..36bbb8a9f4d8 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -147,12 +147,12 @@ reg = <0x48>; }; - at24c04@50 { + eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; }; - at24c04@52 { + eeprom@52 { compatible = "atmel,24c04"; reg = <0x52>; }; diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts index e3952e9ea0db..d7019e89f588 100644 --- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts @@ -505,14 +505,14 @@ pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; - gpio5: pca9554@20 { + gpio5: io-expander@20 { compatible = "nxp,pca9554"; reg = <0x20>; gpio-controller; #gpio-cells = <2>; }; - gpio6: pca9554@22 { + gpio6: io-expander@22 { compatible = "nxp,pca9554"; reg = <0x22>; gpio-controller; @@ -524,12 +524,12 @@ reg = <0x48>; }; - at24c04@50 { + eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; }; - at24c04@52 { + eeprom@52 { compatible = "atmel,24c04"; reg = <0x52>; }; @@ -577,7 +577,7 @@ reg = <0x4f>; }; - gpio7: pca9555@23 { + gpio7: io-expander@23 { compatible = "nxp,pca9555"; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index 8366bae632d6..453fce80f858 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -69,7 +69,7 @@ */ status = "disabled"; - m25p128@0 { + flash@0 { #address-cells = <1>; #size-cells = <1>; compatible = "m25p128", "jedec,spi-nor"; @@ -194,7 +194,7 @@ pinctrl-0 = <&pinctrl_i2c0>; status = "okay"; - gpio6: pca9505@22 { + gpio6: io-expander@22 { compatible = "nxp,pca9554"; reg = <0x22>; gpio-controller; @@ -206,13 +206,13 @@ reg = <0x48>; }; - at24c04@50 { + eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; label = "nameplate"; }; - at24c04@52 { + eeprom@52 { compatible = "atmel,24c04"; reg = <0x52>; }; -- cgit From 35dc29ef0f5de174537ddeb0f202adb8e99e2ea6 Mon Sep 17 00:00:00 2001 From: Anson Huang Date: Mon, 8 Apr 2019 07:44:21 +0000 Subject: ARM: dts: imx6dl-sabreauto: update opp table for auto part Update i.MX6DL automotive part's opp table according to i.MX6DL automotive datasheet Rev.9, 11/2018, it adds 996MHz set-point support as below: LDO enabled(min value): 996MHz: VDDARM: 1.275V, VDDSOC: 1.175V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 1.125V, VDDSOC: 1.150V; Adding 25mV to cover board IR drop, for LDO enabled mode of 996MHz, as the max value of LDO output can NOT exceed 1.3V, so 25mV is NOT added for VDDARM. Signed-off-by: Anson Huang Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx6dl-sabreauto.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/imx6dl-sabreauto.dts b/arch/arm/boot/dts/imx6dl-sabreauto.dts index 660d52a245ba..ff3283c83a39 100644 --- a/arch/arm/boot/dts/imx6dl-sabreauto.dts +++ b/arch/arm/boot/dts/imx6dl-sabreauto.dts @@ -11,3 +11,18 @@ model = "Freescale i.MX6 DualLite/Solo SABRE Automotive Board"; compatible = "fsl,imx6dl-sabreauto", "fsl,imx6dl"; }; + +&cpu0 { + operating-points = < + /* kHz uV */ + 996000 1275000 + 792000 1175000 + 396000 1150000 + >; + fsl,soc-operating-points = < + /* ARM kHz SOC-PU uV */ + 996000 1200000 + 792000 1175000 + 396000 1175000 + >; +}; -- cgit From 6143613a84ada5de602a717f0a41b0ae6c88755f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Apr 2019 12:49:52 +0200 Subject: ARM: dts: imx53: Rename M53 SoM touchscreen node Rename the touchscreen node to match contemporary design. Signed-off-by: Marek Vasut Cc: Shawn Guo Cc: Fabio Estevam Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx53-m53.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi index db2e5bce9b6a..d1770e1d5e50 100644 --- a/arch/arm/boot/dts/imx53-m53.dtsi +++ b/arch/arm/boot/dts/imx53-m53.dtsi @@ -52,7 +52,7 @@ clock-frequency = <400000>; status = "okay"; - stmpe610@41 { + touchscreen@41 { compatible = "st,stmpe610"; reg = <0x41>; id = <0>; -- cgit From 716be61d186939eebacdbccfc14e9ea3bd70f8c6 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 12 Apr 2019 12:49:53 +0200 Subject: ARM: dts: imx53: Add Menlosystems M53 board Add device tree for the Menlosystems board based on i.MX53 M53 SoM. Signed-off-by: Marek Vasut Cc: Shawn Guo Cc: Fabio Estevam Cc: NXP Linux Team To: linux-arm-kernel@lists.infradead.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx53-m53menlo.dts | 311 +++++++++++++++++++++++++++++++++++ 2 files changed, 312 insertions(+) create mode 100644 arch/arm/boot/dts/imx53-m53menlo.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 7776f97c4497..87dc9b7fef9b 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -381,6 +381,7 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-kp-ddc.dtb \ imx53-kp-hsc.dtb \ imx53-m53evk.dtb \ + imx53-m53menlo.dtb \ imx53-mba53.dtb \ imx53-ppd.dtb \ imx53-qsb.dtb \ diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts new file mode 100644 index 000000000000..f0a3fde0739c --- /dev/null +++ b/arch/arm/boot/dts/imx53-m53menlo.dts @@ -0,0 +1,311 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2019 Marek Vasut + */ + +/dts-v1/; +#include "imx53-m53.dtsi" + +/ { + model = "MENLO M53 EMBEDDED DEVICE"; + compatible = "menlo,m53menlo", "fsl,imx53"; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_led>; + + user1 { + label = "TestLed601"; + gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "mmc0"; + }; + + user2 { + label = "TestLed602"; + gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + + eth { + label = "EthLedYe"; + gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + }; + }; + + panel { + compatible = "edt,etm070080dh6"; + enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + regulator-name = "vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2>; + status = "okay"; +}; + +&clks { + assigned-clocks = <&clks IMX5_CLK_CKO1_SEL>, + <&clks IMX5_CLK_CKO1_PODF>, + <&clks IMX5_CLK_CKO1>; + assigned-clock-parents = <&clks IMX5_CLK_AHB>; + assigned-clock-rates = <133333334>, <33333334>, <33333334>; +}; + +&esdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + cd-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_edt_ft5x06>; + interrupt-parent = <&gpio6>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + wake-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + }; + + eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + dac@60 { + compatible = "microchip,mcp4725"; + reg = <0x60>; + }; +}; + +&i2c2 { + touchscreen@41 { + status = "disabled"; + }; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + imx53-m53evk { + hoggrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1d5 + MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5 + MX53_PAD_GPIO_19__CCM_CLKO 0x1d5 + MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5 + MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5 + MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5 + MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5 + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5 + >; + }; + + pinctrl_led: ledgrp { + fsl,pins = < + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_GPIO_7__CAN1_TXCAN 0x1c4 + MX53_PAD_GPIO_8__CAN1_RXCAN 0x1c4 + >; + }; + + pinctrl_can2: can2grp { + fsl,pins = < + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4 + MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 + >; + }; + + pinctrl_display_gpio: display-gpiogrp { + fsl,pins = < + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */ + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */ + >; + }; + + pinctrl_edt_ft5x06: edt-ft5x06grp { + fsl,pins = < + MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */ + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */ + MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */ + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX53_PAD_GPIO_6__I2C3_SDA 0x400001e4 + MX53_PAD_GPIO_5__I2C3_SCL 0x400001e4 + >; + }; + + pinctrl_lvds0: lvds0grp { + /* LVDS pins only have pin mux configuration */ + fsl,pins = < + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK 0x80000000 + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0 0x80000000 + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1 0x80000000 + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2 0x80000000 + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX 0x1e4 + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX 0x1e4 + >; + }; + + pinctrl_usb: usbgrp { + fsl,pins = < + MX53_PAD_GPIO_2__GPIO1_2 0x1d5 + MX53_PAD_GPIO_3__USBOH3_USBH1_OC 0x1d5 + >; + }; + }; +}; + +&ldb { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lvds0>; + status = "okay"; + + lvds0: lvds-channel@0 { + reg = <0>; + fsl,data-mapping = "spwg"; + fsl,data-width = <18>; + status = "okay"; + + port@2 { + reg = <2>; + + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usbh1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb>; + vbus-supply = <®_usbh1_vbus>; + phy_type = "utmi"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + status = "okay"; +}; -- cgit From 5ea0c200bd30a96732fb50a5d7428d0d75b39d28 Mon Sep 17 00:00:00 2001 From: Bruno Thomsen Date: Tue, 16 Apr 2019 11:08:05 +0200 Subject: ARM: dts: bugfix tqma7 soft reset issue Running reboot command on the TQMa7 board would just hang infinite at the end of the system shutdown process. Handling of i.MX7 errata e10574: Watchdog: A watchdog timeout or software trigger will not reset the SOC. Moved pinctrl from common mba7 to common tqma7 dtsi as it improves readability of errata handling. Most integrators of this SoM will likely use the development board as inspiration for handling this SoC issue. Signed-off-by: Bruno Thomsen Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7-mba7.dtsi | 11 ----------- arch/arm/boot/dts/imx7-tqma7.dtsi | 17 +++++++++++++++++ 2 files changed, 17 insertions(+), 11 deletions(-) diff --git a/arch/arm/boot/dts/imx7-mba7.dtsi b/arch/arm/boot/dts/imx7-mba7.dtsi index 578341b6848b..50abf18ad30b 100644 --- a/arch/arm/boot/dts/imx7-mba7.dtsi +++ b/arch/arm/boot/dts/imx7-mba7.dtsi @@ -472,12 +472,6 @@ MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x59 >; }; - - pinctrl_wdog1: wdog1grp { - fsl,pins = < - MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 - >; - }; }; &pwm1 { @@ -554,8 +548,3 @@ no-1-8-v; status = "okay"; }; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog1>; -}; diff --git a/arch/arm/boot/dts/imx7-tqma7.dtsi b/arch/arm/boot/dts/imx7-tqma7.dtsi index 85fe461e5e67..9aaed85138cb 100644 --- a/arch/arm/boot/dts/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/imx7-tqma7.dtsi @@ -209,6 +209,14 @@ }; }; +&iomuxc_lpsr { + pinctrl_wdog1: wdog1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30 + >; + }; +}; + &sdma { status = "okay"; }; @@ -228,5 +236,14 @@ }; &wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog1>; + /* + * Errata e10574: + * WDOG reset needs to run with WDOG_RESET_B signal enabled. + * X1-51 (WDOG1#) signal needs carrier board handling to reset + * TQMa7 on X1-22 (RESET_IN#). + */ + fsl,ext-reset-output; status = "okay"; }; -- cgit From 69ab5392f5177aad19e006c5ba8e78bf059fee68 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sun, 14 Apr 2019 11:34:03 -0700 Subject: ARM: dts: Add support for ZII i.MX7 RPU2 board Add support for ZII's i.MX7 based Remote Peripheral Unit 2 (RPU2) board. Signed-off-by: Andrey Smirnov Reviewed-by: Fabio Estevam Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: Rob Herring Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/imx7d-zii-rpu2.dts | 941 +++++++++++++++++++++++++++++++++++ 2 files changed, 942 insertions(+) create mode 100644 arch/arm/boot/dts/imx7d-zii-rpu2.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 87dc9b7fef9b..55f3c20d103d 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -590,6 +590,7 @@ dtb-$(CONFIG_SOC_IMX7D) += \ imx7d-sdb.dtb \ imx7d-sdb-reva.dtb \ imx7d-sdb-sht11.dtb \ + imx7d-zii-rpu2.dtb \ imx7s-colibri-eval-v3.dtb \ imx7s-mba7.dtb \ imx7s-warp.dtb diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts new file mode 100644 index 000000000000..3e467a94e8a6 --- /dev/null +++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts @@ -0,0 +1,941 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Device tree file for ZII's RPU2 board + * + * RPU - Remote Peripheral Unit + * + * Copyright (C) 2019 Zodiac Inflight Innovations + */ + +/dts-v1/; +#include +#include "imx7d.dtsi" + +/ { + model = "ZII RPU2 Board"; + compatible = "zii,imx7d-rpu2", "fsl,imx7d"; + + chosen { + stdout-path = &uart1; + }; + + cs2000_ref: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24576000>; + }; + + cs2000_in_dummy: dummy-oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-0 = <&pinctrl_leds_debug>; + pinctrl-names = "default"; + + debug { + label = "zii:green:debug1"; + gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc2 1>; + }; + + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_stby>; + regulator-name = "can1-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_stby>; + regulator-name = "can2-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_vref_1v8: regulator-vref-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vref-1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "GEN_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_5p0v_main: regulator-5p0v-main { + compatible = "regulator-fixed"; + regulator-name = "5V_MAIN"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + sound1 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Audio Output 1"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound1_codec>; + simple-audio-card,frame-master = <&sound1_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "LEFTIN", "HPL", + "RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa1>; + + simple-audio-card,cpu { + sound-dai = <&sai1>; + }; + + sound1_codec: simple-audio-card,codec { + sound-dai = <&codec1>; + clocks = <&cs2000>; + }; + }; + + sound2 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Audio Output 2"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound2_codec>; + simple-audio-card,frame-master = <&sound2_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "LEFTIN", "HPL", + "RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa2>; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + sound2_codec: simple-audio-card,codec { + sound-dai = <&codec2>; + clocks = <&cs2000>; + }; + }; + + sound3 { + compatible = "simple-audio-card"; + simple-audio-card,name = "Audio Output 3"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&sound3_codec>; + simple-audio-card,frame-master = <&sound3_codec>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack"; + simple-audio-card,routing = + "Headphone Jack", "HPLEFT", + "Headphone Jack", "HPRIGHT", + "LEFTIN", "HPL", + "RIGHTIN", "HPR"; + simple-audio-card,aux-devs = <&hpa3>; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + sound3_codec: simple-audio-card,codec { + sound-dai = <&codec3>; + clocks = <&cs2000>; + }; + }; +}; + +&adc1 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&adc2 { + vref-supply = <®_vref_1v8>; + status = "okay"; +}; + +&cpu0 { + arm-supply = <&sw1a_reg>; +}; + +&clks { + assigned-clocks = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <884736000>; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, + <&clks IMX7D_ENET1_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + mdio1: mdio { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + switch: switch@0 { + compatible = "marvell,mv88e6085"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + reg = <0>; + eeprom-length = <512>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "eth_cu_1000_1"; + }; + + port@1 { + reg = <1>; + label = "eth_cu_1000_2"; + }; + + port@2 { + reg = <2>; + label = "pic"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + port@5 { + reg = <5>; + label = "cpu"; + ethernet = <&fec1>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@6 { + reg = <6>; + label = "gigabit_proc"; + ethernet = <&fec2>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>; + assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, + <&clks IMX7D_ENET2_TIME_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + assigned-clock-rates = <0>, <100000000>; + phy-mode = "rgmii"; + fsl,magic-packet; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + +&gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio1>; + + gpio-line-names = "", "", "", "", "", "", "", "", + "", "", + "usb_1_en_b", + "usb_2_en_b", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&gpio2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio2>; + + gpio-line-names = "12v_out_en_1", + "12v_out_en_2", + "12v_out_en_3", + "28v_out_en_5", + "28v_out_en_1", + "28v_out_en_2", + "28v_out_en_3", + "28v_out_en_4", + "", "", + "usb_3_en_b", + "usb_4_en_b", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", ""; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic: pmic@8 { + compatible = "fsl,pfuze3000"; + reg = <0x08>; + + regulators { + sw1a_reg: sw1a { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw1c_reg: sw1b { + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1475000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <6250>; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + + sw3a_reg: sw3 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1650000>; + regulator-boot-on; + regulator-always-on; + }; + + swbst_reg: swbst { + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5150000>; + }; + + snvs_reg: vsnvs { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <3000000>; + regulator-boot-on; + regulator-always-on; + }; + + vref_reg: vrefddr { + regulator-boot-on; + regulator-always-on; + }; + + vgen1_reg: vldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen2_reg: vldo2 { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1550000>; + regulator-always-on; + }; + + vgen3_reg: vccsd { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen4_reg: v33 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen5_reg: vldo3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vgen6_reg: vldo4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; + }; + + cs2000: clkgen@4e { + compatible = "cirrus,cs2000-cp"; + reg = <0x4e>; + #clock-cells = <0>; + clock-names = "clk_in", "ref_clk"; + clocks = <&cs2000_in_dummy>, <&cs2000_ref>; + assigned-clocks = <&cs2000>; + assigned-clock-rates = <24000000>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + }; + + eeprom@52 { + compatible = "atmel,24c04"; + reg = <0x52>; + }; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + codec2: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec2>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + gpio-reset = <&gpio1 6 GPIO_ACTIVE_LOW>; + }; + + hpa2: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa2>; + reg = <0x60>; + power-gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + codec3: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec3>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + gpio-reset = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + hpa3: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa3>; + reg = <0x60>; + power-gpio = <&gpio3 28 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + }; +}; + +&i2c4 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + codec1: codec@18 { + compatible = "ti,tlv320dac3100"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec1>; + reg = <0x18>; + #sound-dai-cells = <0>; + HPVDD-supply = <®_3p3v>; + SPRVDD-supply = <®_3p3v>; + SPLVDD-supply = <®_3p3v>; + AVDD-supply = <®_3p3v>; + IOVDD-supply = <®_3p3v>; + DVDD-supply = <&vgen4_reg>; + gpio-reset = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; + + hpa1: amp@60 { + compatible = "ti,tpa6130a2"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpa1>; + reg = <0x60>; + power-gpio = <&gpio3 26 GPIO_ACTIVE_HIGH>; + Vdd-supply = <®_5p0v_main>; + }; +}; + +&sai1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai1>; + assigned-clocks = <&clks IMX7D_SAI1_ROOT_SRC>, + <&clks IMX7D_SAI1_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX7D_SAI2_ROOT_SRC>, + <&clks IMX7D_SAI2_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&sai3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai3>; + assigned-clocks = <&clks IMX7D_SAI3_ROOT_SRC>, + <&clks IMX7D_SAI3_ROOT_CLK>; + assigned-clock-parents = <&clks IMX7D_PLL_AUDIO_POST_DIV>; + assigned-clock-rates = <0>, <36864000>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + assigned-clocks = <&clks IMX7D_UART2_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_OSC_24M_CLK>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + assigned-clocks = <&clks IMX7D_UART4_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; + status = "okay"; + + rave-sp { + compatible = "zii,rave-sp-rdu2"; + current-speed = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + + watchdog { + compatible = "zii,rave-sp-watchdog"; + }; + + eeprom@a3 { + compatible = "zii,rave-sp-eeprom"; + reg = <0xa3 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + zii,eeprom-name = "main-eeprom"; + }; + }; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + bus-width = <4>; + no-1-8-v; + no-sdio; + keep-power-in-suspend; + status = "okay"; +}; + +&usdhc3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc3>; + bus-width = <8>; + no-1-8-v; + non-removable; + no-sdio; + no-sd; + keep-power-in-suspend; + status = "okay"; +}; + +&wdog1 { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2 + MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2 + MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2 + MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59 + >; + }; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3 + MX7D_PAD_SD2_WP__ENET1_MDC 0x3 + MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 + MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 + MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 + MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 + MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 + MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 + MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 + MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 + MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 + MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 + MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 + MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 + >; + }; + + pinctrl_enet2: enet2grp { + fsl,pins = < + MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 + MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 + MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 + MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 + MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 + MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 + MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 + MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 + MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 + MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 + MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 + MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 + MX7D_PAD_UART1_TX_DATA__ENET2_1588_EVENT0_OUT 0x1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO12__FLEXCAN1_RX 0x59 + MX7D_PAD_GPIO1_IO13__FLEXCAN1_TX 0x59 + >; + }; + + pinctrl_flexcan1_stby: flexcan1stbygrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO08__GPIO1_IO8 0x59 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 + MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 + >; + }; + + pinctrl_flexcan2_stby: flexcan2stbygrp { + fsl,pins = < + MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 + >; + }; + + pinctrl_gpio1: gpio1grp { + fsl,pins = < + MX7D_PAD_GPIO1_IO10__GPIO1_IO10 0x00 + MX7D_PAD_GPIO1_IO11__GPIO1_IO11 0x00 + >; + }; + + pinctrl_gpio2: gpio2grp { + fsl,pins = < + MX7D_PAD_EPDC_DATA00__GPIO2_IO0 0x00 + MX7D_PAD_EPDC_DATA01__GPIO2_IO1 0x00 + MX7D_PAD_EPDC_DATA02__GPIO2_IO2 0x00 + MX7D_PAD_EPDC_DATA03__GPIO2_IO3 0x03 + MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x03 + MX7D_PAD_EPDC_DATA05__GPIO2_IO5 0x03 + MX7D_PAD_EPDC_DATA06__GPIO2_IO6 0x03 + MX7D_PAD_EPDC_DATA07__GPIO2_IO7 0x03 + MX7D_PAD_EPDC_DATA10__GPIO2_IO10 0x00 + MX7D_PAD_EPDC_DATA11__GPIO2_IO11 0x00 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f + MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f + >; + }; + + pinctrl_i2c1_gpio: i2c1gpiogrp { + fsl,pins = < + MX7D_PAD_I2C1_SDA__GPIO4_IO9 0x4000007f + MX7D_PAD_I2C1_SCL__GPIO4_IO8 0x4000007f + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f + MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX7D_PAD_I2C2_SDA__GPIO4_IO11 0x4000007f + MX7D_PAD_I2C2_SCL__GPIO4_IO10 0x4000007f + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f + MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX7D_PAD_I2C3_SDA__GPIO4_IO13 0x4000007f + MX7D_PAD_I2C3_SCL__GPIO4_IO12 0x4000007f + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f + MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX7D_PAD_SAI1_RX_BCLK__GPIO6_IO17 0x4000007f + MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x4000007f + >; + }; + + pinctrl_leds_debug: debuggrp { + fsl,pins = < + MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59 + >; + }; + + pinctrl_sai1: sai1grp { + fsl,pins = < + MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f + MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f + MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30 + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX7D_PAD_SAI2_TX_BCLK__SAI2_TX_BCLK 0x1f + MX7D_PAD_SAI2_TX_SYNC__SAI2_TX_SYNC 0x1f + MX7D_PAD_SAI2_TX_DATA__SAI2_TX_DATA0 0x30 + >; + }; + + pinctrl_sai3: sai3grp { + fsl,pins = < + MX7D_PAD_UART3_TX_DATA__SAI3_TX_BCLK 0x1f + MX7D_PAD_UART3_CTS_B__SAI3_TX_SYNC 0x1f + MX7D_PAD_UART3_RTS_B__SAI3_TX_DATA0 0x30 + >; + }; + + pinctrl_tpa1: tpa6130-1grp { + fsl,pins = < + MX7D_PAD_LCD_DATA21__GPIO3_IO26 0x40000038 + >; + }; + + pinctrl_tpa2: tpa6130-2grp { + fsl,pins = < + MX7D_PAD_LCD_DATA22__GPIO3_IO27 0x40000038 + >; + }; + + pinctrl_tpa3: tpa6130-3grp { + fsl,pins = < + MX7D_PAD_LCD_DATA23__GPIO3_IO28 0x40000038 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79 + MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79 + MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX7D_PAD_SD1_CMD__SD1_CMD 0x59 + MX7D_PAD_SD1_CLK__SD1_CLK 0x19 + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX7D_PAD_SD3_CMD__SD3_CMD 0x59 + MX7D_PAD_SD3_CLK__SD3_CLK 0x19 + MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 + MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 + MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 + MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 + MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 + MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 + MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 + MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 + MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59 + >; + }; +}; + +&iomuxc_lpsr { + pinctrl_codec1: dac1grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x40000038 + >; + }; + + pinctrl_codec2: dac2grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO06__GPIO1_IO6 0x40000038 + >; + }; + + pinctrl_codec3: dac3grp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO07__GPIO1_IO7 0x40000038 + >; + }; + + pinctrl_switch: switchgrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08 + >; + }; +}; -- cgit From 1437626ec447400d66738b7af5006df456142f44 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sun, 14 Apr 2019 11:35:57 -0700 Subject: ARM: dts: vf610-zii-dev: Mark i2c0 SCL as GPIO_OPEN_DRAIN Mark i2c0 SCL as GPIO_OPEN_DRAIN to fix the following warning: gpio-36 (scl): enforced open drain please flag it properly in DT/ACPI DSDT/board file Signed-off-by: Andrey Smirnov Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index 36bbb8a9f4d8..0507e6dcbb21 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -138,7 +138,7 @@ pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c0>; pinctrl-1 = <&pinctrl_i2c0_gpio>; - scl-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio1 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; status = "okay"; -- cgit From 2ea5c9b28fab2f34a0ac5d9b3d17216dd35d3162 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sun, 14 Apr 2019 11:35:58 -0700 Subject: ARM: dts: vf610-zii-dev-rev-b: Specify CS as GPIO_ACTIVE_LOW in spi0 Specify CS as GPIO_ACTIVE_LOW in spi0 to fix the following warning: m25p128@0 enforce active low on chipselect handle Signed-off-by: Andrey Smirnov Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: linux-kernel@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 8b0baf6a4098..48086c5e8549 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -295,7 +295,7 @@ gpio-sck = <&gpio1 12 GPIO_ACTIVE_HIGH>; gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>; gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>; - cs-gpios = <&gpio1 9 GPIO_ACTIVE_HIGH + cs-gpios = <&gpio1 9 GPIO_ACTIVE_LOW &gpio1 8 GPIO_ACTIVE_HIGH>; num-chipselects = <2>; -- cgit From 4171797ff78fa1f351b890e18411b7959b506149 Mon Sep 17 00:00:00 2001 From: Andrey Smirnov Date: Sun, 14 Apr 2019 11:34:01 -0700 Subject: ARM: dts: imx7s: Specify #io-channel-cells in ADC nodes Specify #io-channel-cells in ADC nodes. Needed to be able to reference them by phandle. Signed-off-by: Andrey Smirnov Cc: Shawn Guo Cc: Chris Healy Cc: Andrew Lunn Cc: Fabio Estevam Cc: Rob Herring Cc: linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org Signed-off-by: Shawn Guo --- arch/arm/boot/dts/imx7s.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 0b01109ac0a9..106711d2c01b 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -670,6 +670,7 @@ interrupts = ; clocks = <&clks IMX7D_ADC_ROOT_CLK>; clock-names = "adc"; + #io-channel-cells = <1>; status = "disabled"; }; @@ -679,6 +680,7 @@ interrupts = ; clocks = <&clks IMX7D_ADC_ROOT_CLK>; clock-names = "adc"; + #io-channel-cells = <1>; status = "disabled"; }; -- cgit