From 75a78026ea1307ef6d6924cc22be3ce9bf453c63 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 May 2021 19:55:53 +0200 Subject: dt-bindings: can: rcar_can: Convert to json-schema Convert the Renesas R-Car CAN Controller Device Tree binding documentation to json-schema. Document missing properties. Update the example to match reality. Link: https://lore.kernel.org/r/561c35648e22a3c1e3b5477ae27fd1a50da7fe98.1620323639.git.geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Reviewed-by: Ulrich Hecht Signed-off-by: Marc Kleine-Budde --- .../devicetree/bindings/net/can/rcar_can.txt | 80 ------------ .../bindings/net/can/renesas,rcar-can.yaml | 139 +++++++++++++++++++++ 2 files changed, 139 insertions(+), 80 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/can/rcar_can.txt create mode 100644 Documentation/devicetree/bindings/net/can/renesas,rcar-can.yaml diff --git a/Documentation/devicetree/bindings/net/can/rcar_can.txt b/Documentation/devicetree/bindings/net/can/rcar_can.txt deleted file mode 100644 index 90ac4fef23f5..000000000000 --- a/Documentation/devicetree/bindings/net/can/rcar_can.txt +++ /dev/null @@ -1,80 +0,0 @@ -Renesas R-Car CAN controller Device Tree Bindings -------------------------------------------------- - -Required properties: -- compatible: "renesas,can-r8a7742" if CAN controller is a part of R8A7742 SoC. - "renesas,can-r8a7743" if CAN controller is a part of R8A7743 SoC. - "renesas,can-r8a7744" if CAN controller is a part of R8A7744 SoC. - "renesas,can-r8a7745" if CAN controller is a part of R8A7745 SoC. - "renesas,can-r8a77470" if CAN controller is a part of R8A77470 SoC. - "renesas,can-r8a774a1" if CAN controller is a part of R8A774A1 SoC. - "renesas,can-r8a774b1" if CAN controller is a part of R8A774B1 SoC. - "renesas,can-r8a774c0" if CAN controller is a part of R8A774C0 SoC. - "renesas,can-r8a774e1" if CAN controller is a part of R8A774E1 SoC. - "renesas,can-r8a7778" if CAN controller is a part of R8A7778 SoC. - "renesas,can-r8a7779" if CAN controller is a part of R8A7779 SoC. - "renesas,can-r8a7790" if CAN controller is a part of R8A7790 SoC. - "renesas,can-r8a7791" if CAN controller is a part of R8A7791 SoC. - "renesas,can-r8a7792" if CAN controller is a part of R8A7792 SoC. - "renesas,can-r8a7793" if CAN controller is a part of R8A7793 SoC. - "renesas,can-r8a7794" if CAN controller is a part of R8A7794 SoC. - "renesas,can-r8a7795" if CAN controller is a part of R8A7795 SoC. - "renesas,can-r8a7796" if CAN controller is a part of R8A77960 SoC. - "renesas,can-r8a77961" if CAN controller is a part of R8A77961 SoC. - "renesas,can-r8a77965" if CAN controller is a part of R8A77965 SoC. - "renesas,can-r8a77990" if CAN controller is a part of R8A77990 SoC. - "renesas,can-r8a77995" if CAN controller is a part of R8A77995 SoC. - "renesas,rcar-gen1-can" for a generic R-Car Gen1 compatible device. - "renesas,rcar-gen2-can" for a generic R-Car Gen2 or RZ/G1 - compatible device. - "renesas,rcar-gen3-can" for a generic R-Car Gen3 or RZ/G2 - compatible device. - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first - followed by the generic version. - -- reg: physical base address and size of the R-Car CAN register map. -- interrupts: interrupt specifier for the sole interrupt. -- clocks: phandles and clock specifiers for 3 CAN clock inputs. -- clock-names: 3 clock input name strings: "clkp1", "clkp2", and "can_clk". -- pinctrl-0: pin control group to be used for this controller. -- pinctrl-names: must be "default". - -Required properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795, -R8A77960, R8A77961, R8A77965, R8A77990, and R8A77995: -For the denoted SoCs, "clkp2" can be CANFD clock. This is a div6 clock and can -be used by both CAN and CAN FD controller at the same time. It needs to be -scaled to maximum frequency if any of these controllers use it. This is done -using the below properties: - -- assigned-clocks: phandle of clkp2(CANFD) clock. -- assigned-clock-rates: maximum frequency of this clock. - -Optional properties: -- renesas,can-clock-select: R-Car CAN Clock Source Select. Valid values are: - <0x0> (default) : Peripheral clock (clkp1) - <0x1> : Peripheral clock (clkp2) - <0x3> : External input clock - -Example -------- - -SoC common .dtsi file: - - can0: can@e6e80000 { - compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; - reg = <0 0xe6e80000 0 0x1000>; - interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, - <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; - clock-names = "clkp1", "clkp2", "can_clk"; - status = "disabled"; - }; - -Board specific .dts file: - -&can0 { - pinctrl-0 = <&can0_pins>; - pinctrl-names = "default"; - status = "okay"; -}; diff --git a/Documentation/devicetree/bindings/net/can/renesas,rcar-can.yaml b/Documentation/devicetree/bindings/net/can/renesas,rcar-can.yaml new file mode 100644 index 000000000000..fadc871fd6b0 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/renesas,rcar-can.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/renesas,rcar-can.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car CAN Controller + +maintainers: + - Sergei Shtylyov + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,can-r8a7778 # R-Car M1-A + - renesas,can-r8a7779 # R-Car H1 + - const: renesas,rcar-gen1-can # R-Car Gen1 + + - items: + - enum: + - renesas,can-r8a7742 # RZ/G1H + - renesas,can-r8a7743 # RZ/G1M + - renesas,can-r8a7744 # RZ/G1N + - renesas,can-r8a7745 # RZ/G1E + - renesas,can-r8a77470 # RZ/G1C + - renesas,can-r8a7790 # R-Car H2 + - renesas,can-r8a7791 # R-Car M2-W + - renesas,can-r8a7792 # R-Car V2H + - renesas,can-r8a7793 # R-Car M2-N + - renesas,can-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-can # R-Car Gen2 and RZ/G1 + + - items: + - enum: + - renesas,can-r8a774a1 # RZ/G2M + - renesas,can-r8a774b1 # RZ/G2N + - renesas,can-r8a774c0 # RZ/G2E + - renesas,can-r8a774e1 # RZ/G2H + - renesas,can-r8a7795 # R-Car H3 + - renesas,can-r8a7796 # R-Car M3-W + - renesas,can-r8a77961 # R-Car M3-W+ + - renesas,can-r8a77965 # R-Car M3-N + - renesas,can-r8a77990 # R-Car E3 + - renesas,can-r8a77995 # R-Car D3 + - const: renesas,rcar-gen3-can # R-Car Gen3 and RZ/G2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 3 + + clock-names: + items: + - const: clkp1 + - const: clkp2 + - const: can_clk + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + renesas,can-clock-select: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 3 ] + default: 0 + description: | + R-Car CAN Clock Source Select. Valid values are: + <0x0> (default) : Peripheral clock (clkp1) + <0x1> : Peripheral clock (clkp2) + <0x3> : External input clock + + assigned-clocks: + description: + Reference to the clkp2 (CANFD) clock. + On R-Car Gen3 and RZ/G2 SoCs, "clkp2" is the CANFD clock. This is a div6 + clock and can be used by both CAN and CAN FD controllers at the same + time. It needs to be scaled to maximum frequency if any of these + controllers use it. + + assigned-clock-rates: + description: Maximum frequency of the CANFD clock. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + +allOf: + - $ref: can-controller.yaml# + + - if: + not: + properties: + compatible: + contains: + const: renesas,rcar-gen1-can + then: + required: + - resets + + - if: + properties: + compatible: + contains: + const: renesas,rcar-gen3-can + then: + required: + - assigned-clocks + - assigned-clock-rates + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + can0: can@e6e80000 { + compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; + reg = <0xe6e80000 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7791_CLK_RCAN>, <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 916>; + }; -- cgit From 8a5e7d19c8c747e3e7bfa0283a54742b103afcb5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 6 May 2021 19:55:54 +0200 Subject: dt-bindings: can: rcar_canfd: Convert to json-schema Convert the Renesas R-Car CAN FD Controller Device Tree binding documentation to json-schema. Document missing properties. The CANFD clock needs to be configured for the maximum frequency on R-Car V3M and V3H, too. Update the example to match reality. Link: https://lore.kernel.org/r/905134c87f72e2d8e37c309e0ce28ecd7d4f3992.1620323639.git.geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Reviewed-by: Ulrich Hecht Signed-off-by: Marc Kleine-Budde --- .../devicetree/bindings/net/can/rcar_canfd.txt | 107 ------------------ .../bindings/net/can/renesas,rcar-canfd.yaml | 122 +++++++++++++++++++++ 2 files changed, 122 insertions(+), 107 deletions(-) delete mode 100644 Documentation/devicetree/bindings/net/can/rcar_canfd.txt create mode 100644 Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml diff --git a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt b/Documentation/devicetree/bindings/net/can/rcar_canfd.txt deleted file mode 100644 index 248c4ed97a0a..000000000000 --- a/Documentation/devicetree/bindings/net/can/rcar_canfd.txt +++ /dev/null @@ -1,107 +0,0 @@ -Renesas R-Car CAN FD controller Device Tree Bindings ----------------------------------------------------- - -Required properties: -- compatible: Must contain one or more of the following: - - "renesas,rcar-gen3-canfd" for R-Car Gen3 and RZ/G2 compatible controllers. - - "renesas,r8a774a1-canfd" for R8A774A1 (RZ/G2M) compatible controller. - - "renesas,r8a774b1-canfd" for R8A774B1 (RZ/G2N) compatible controller. - - "renesas,r8a774c0-canfd" for R8A774C0 (RZ/G2E) compatible controller. - - "renesas,r8a774e1-canfd" for R8A774E1 (RZ/G2H) compatible controller. - - "renesas,r8a7795-canfd" for R8A7795 (R-Car H3) compatible controller. - - "renesas,r8a7796-canfd" for R8A7796 (R-Car M3-W) compatible controller. - - "renesas,r8a77965-canfd" for R8A77965 (R-Car M3-N) compatible controller. - - "renesas,r8a77970-canfd" for R8A77970 (R-Car V3M) compatible controller. - - "renesas,r8a77980-canfd" for R8A77980 (R-Car V3H) compatible controller. - - "renesas,r8a77990-canfd" for R8A77990 (R-Car E3) compatible controller. - - "renesas,r8a77995-canfd" for R8A77995 (R-Car D3) compatible controller. - - When compatible with the generic version, nodes must list the - SoC-specific version corresponding to the platform first, followed by the - family-specific and/or generic versions. - -- reg: physical base address and size of the R-Car CAN FD register map. -- interrupts: interrupt specifiers for the Channel & Global interrupts -- clocks: phandles and clock specifiers for 3 clock inputs. -- clock-names: 3 clock input name strings: "fck", "canfd", "can_clk". -- pinctrl-0: pin control group to be used for this controller. -- pinctrl-names: must be "default". - -Required child nodes: -The controller supports two channels and each is represented as a child node. -The name of the child nodes are "channel0" and "channel1" respectively. Each -child node supports the "status" property only, which is used to -enable/disable the respective channel. - -Required properties for R8A774A1, R8A774B1, R8A774C0, R8A774E1, R8A7795, -R8A7796, R8A77965, R8A77990, and R8A77995: -In the denoted SoCs, canfd clock is a div6 clock and can be used by both CAN -and CAN FD controller at the same time. It needs to be scaled to maximum -frequency if any of these controllers use it. This is done using the below -properties: - -- assigned-clocks: phandle of canfd clock. -- assigned-clock-rates: maximum frequency of this clock. - -Optional property: -The controller can operate in either CAN FD only mode (default) or -Classical CAN only mode. The mode is global to both the channels. In order to -enable the later, define the following optional property. - - renesas,no-can-fd: puts the controller in Classical CAN only mode. - -Example -------- - -SoC common .dtsi file: - - canfd: can@e66c0000 { - compatible = "renesas,r8a7795-canfd", - "renesas,rcar-gen3-canfd"; - reg = <0 0xe66c0000 0 0x8000>; - interrupts = , - ; - clocks = <&cpg CPG_MOD 914>, - <&cpg CPG_CORE R8A7795_CLK_CANFD>, - <&can_clk>; - clock-names = "fck", "canfd", "can_clk"; - assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; - assigned-clock-rates = <40000000>; - power-domains = <&cpg>; - status = "disabled"; - - channel0 { - status = "disabled"; - }; - - channel1 { - status = "disabled"; - }; - }; - -Board specific .dts file: - -E.g. below enables Channel 1 alone in the board in Classical CAN only mode. - -&canfd { - pinctrl-0 = <&canfd1_pins>; - pinctrl-names = "default"; - renesas,no-can-fd; - status = "okay"; - - channel1 { - status = "okay"; - }; -}; - -E.g. below enables Channel 0 alone in the board using External clock -as fCAN clock. - -&canfd { - pinctrl-0 = <&canfd0_pins>, <&can_clk_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; diff --git a/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml new file mode 100644 index 000000000000..0b33ba9ccb47 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/renesas,rcar-canfd.yaml @@ -0,0 +1,122 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car CAN FD Controller + +maintainers: + - Fabrizio Castro + +allOf: + - $ref: can-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - renesas,r8a774a1-canfd # RZ/G2M + - renesas,r8a774b1-canfd # RZ/G2N + - renesas,r8a774c0-canfd # RZ/G2E + - renesas,r8a774e1-canfd # RZ/G2H + - renesas,r8a7795-canfd # R-Car H3 + - renesas,r8a7796-canfd # R-Car M3-W + - renesas,r8a77965-canfd # R-Car M3-N + - renesas,r8a77970-canfd # R-Car V3M + - renesas,r8a77980-canfd # R-Car V3H + - renesas,r8a77990-canfd # R-Car E3 + - renesas,r8a77995-canfd # R-Car D3 + - const: renesas,rcar-gen3-canfd # R-Car Gen3 and RZ/G2 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Channel interrupt + - description: Global interrupt + + clocks: + maxItems: 3 + + clock-names: + items: + - const: fck + - const: canfd + - const: can_clk + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + renesas,no-can-fd: + $ref: /schemas/types.yaml#/definitions/flag + description: + The controller can operate in either CAN FD only mode (default) or + Classical CAN only mode. The mode is global to both the channels. + Specify this property to put the controller in Classical CAN only mode. + + assigned-clocks: + description: + Reference to the CANFD clock. The CANFD clock is a div6 clock and can be + used by both CAN (if present) and CAN FD controllers at the same time. + It needs to be scaled to maximum frequency if any of these controllers + use it. + + assigned-clock-rates: + description: Maximum frequency of the CANFD clock. + +patternProperties: + "^channel[01]$": + type: object + description: + The controller supports two channels and each is represented as a child + node. Each child node supports the "status" property only, which + is used to enable/disable the respective channel. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + - assigned-clocks + - assigned-clock-rates + - channel0 + - channel1 + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + canfd: can@e66c0000 { + compatible = "renesas,r8a7795-canfd", + "renesas,rcar-gen3-canfd"; + reg = <0xe66c0000 0x8000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 914>, + <&cpg CPG_CORE R8A7795_CLK_CANFD>, + <&can_clk>; + clock-names = "fck", "canfd", "can_clk"; + assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>; + assigned-clock-rates = <40000000>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + resets = <&cpg 914>; + + channel0 { + }; + + channel1 { + }; + }; -- cgit From 7e97d274db920df479e222fed10e7b242f90ffb0 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Mon, 17 May 2021 13:24:25 +0200 Subject: can: uapi: update CAN-FD frame description Since an early version of the CAN-FD specification the bit that defines a CAN-FD frame on the wire, has been renamed from Extended Data Length (EDL) to FD Frame (FDF). To avoid confusion, update the struct canfd_frame description in the UAPI headers accordingly. Link: https://lore.kernel.org/r/20210517113727.77597-1-mkl@pengutronix.de Suggested-by: Ayoub Kaanich Acked-by: Oliver Hartkopp Signed-off-by: Marc Kleine-Budde --- include/uapi/linux/can.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/uapi/linux/can.h b/include/uapi/linux/can.h index c7535352fef6..ac5d7a31671f 100644 --- a/include/uapi/linux/can.h +++ b/include/uapi/linux/can.h @@ -123,8 +123,8 @@ struct can_frame { /* * defined bits for canfd_frame.flags * - * The use of struct canfd_frame implies the Extended Data Length (EDL) bit to - * be set in the CAN frame bitstream on the wire. The EDL bit switch turns + * The use of struct canfd_frame implies the FD Frame (FDF) bit to + * be set in the CAN frame bitstream on the wire. The FDF bit switch turns * the CAN controllers bitstream processor into the CAN FD mode which creates * two new options within the CAN FD frame specification: * -- cgit From 02546884221279da2725e87e35348290470363d7 Mon Sep 17 00:00:00 2001 From: Oliver Hartkopp Date: Tue, 11 Apr 2017 15:43:43 +0200 Subject: can: uapi: introduce CANFD_FDF flag for mixed content in struct canfd_frame The struct can_frame and struct canfd_frame intentionally share the same layout to be able to write CAN frame content into a CAN FD frame structure. When this is done the former differentiation via CAN_MTU / CANFD_MTU is lost. CANFD_FDF allows programmers to mark CAN FD frames in the case of using struct canfd_frame for mixed CAN/CAN FD content (dual use). N.B. the Kernel APIs do NOT provide mixed CAN / CAN FD content inside of struct canfd_frame therefore the CANFD_FDF flag is disregarded by Linux. Link: https://lore.kernel.org/r/20170411134343.3089-1-socketcan@hartkopp.net Signed-off-by: Oliver Hartkopp Signed-off-by: Marc Kleine-Budde --- include/uapi/linux/can.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/uapi/linux/can.h b/include/uapi/linux/can.h index ac5d7a31671f..90801ada2bbe 100644 --- a/include/uapi/linux/can.h +++ b/include/uapi/linux/can.h @@ -135,9 +135,18 @@ struct can_frame { * controller only the CANFD_BRS bit is relevant for real CAN controllers when * building a CAN FD frame for transmission. Setting the CANFD_ESI bit can make * sense for virtual CAN interfaces to test applications with echoed frames. + * + * The struct can_frame and struct canfd_frame intentionally share the same + * layout to be able to write CAN frame content into a CAN FD frame structure. + * When this is done the former differentiation via CAN_MTU / CANFD_MTU gets + * lost. CANFD_FDF allows programmers to mark CAN FD frames in the case of + * using struct canfd_frame for mixed CAN / CAN FD content (dual use). + * N.B. the Kernel APIs do NOT provide mixed CAN / CAN FD content inside of + * struct canfd_frame therefore the CANFD_FDF flag is disregarded by Linux. */ #define CANFD_BRS 0x01 /* bit rate switch (second bitrate for payload data) */ #define CANFD_ESI 0x02 /* error state indicator of the transmitting node */ +#define CANFD_FDF 0x04 /* mark CAN FD for dual use of struct canfd_frame */ /** * struct canfd_frame - CAN flexible data rate frame structure -- cgit From 24a774a4f9750ecd37d7aaeacfc04a844b9cf20b Mon Sep 17 00:00:00 2001 From: zuoqilin Date: Fri, 14 May 2021 18:08:06 +0800 Subject: can: proc: remove unnecessary variables There is no need to define the variable "rate" to receive, just return directly. Link: https://lore.kernel.org/r/20210514100806.792-1-zuoqilin1@163.com Signed-off-by: zuoqilin Signed-off-by: Marc Kleine-Budde --- net/can/proc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/net/can/proc.c b/net/can/proc.c index d1fe49e6f16d..b3099f0a3cb8 100644 --- a/net/can/proc.c +++ b/net/can/proc.c @@ -99,8 +99,6 @@ static void can_init_stats(struct net *net) static unsigned long calc_rate(unsigned long oldjif, unsigned long newjif, unsigned long count) { - unsigned long rate; - if (oldjif == newjif) return 0; @@ -111,9 +109,7 @@ static unsigned long calc_rate(unsigned long oldjif, unsigned long newjif, return 99999999; } - rate = (count * HZ) / (newjif - oldjif); - - return rate; + return (count * HZ) / (newjif - oldjif); } void can_stat_update(struct timer_list *t) -- cgit From 46d8657a6b284e32b6b3bf1a6c93ee507fdd3cdb Mon Sep 17 00:00:00 2001 From: Patrick Menschel Date: Tue, 27 Apr 2021 05:21:47 +0000 Subject: can: isotp: change error format from decimal to symbolic error names This patch changes the format string for errors from decimal %d to symbolic error names %pe to achieve more comprehensive log messages. Link: https://lore.kernel.org/r/20210427052150.2308-2-menschel.p@posteo.de Signed-off-by: Patrick Menschel Signed-off-by: Marc Kleine-Budde --- net/can/isotp.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/net/can/isotp.c b/net/can/isotp.c index 9f94ad3caee9..2c4f84fac70a 100644 --- a/net/can/isotp.c +++ b/net/can/isotp.c @@ -221,8 +221,8 @@ static int isotp_send_fc(struct sock *sk, int ae, u8 flowstatus) can_send_ret = can_send(nskb, 1); if (can_send_ret) - pr_notice_once("can-isotp: %s: can_send_ret %d\n", - __func__, can_send_ret); + pr_notice_once("can-isotp: %s: can_send_ret %pe\n", + __func__, ERR_PTR(can_send_ret)); dev_put(dev); @@ -798,8 +798,8 @@ isotp_tx_burst: can_send_ret = can_send(skb, 1); if (can_send_ret) - pr_notice_once("can-isotp: %s: can_send_ret %d\n", - __func__, can_send_ret); + pr_notice_once("can-isotp: %s: can_send_ret %pe\n", + __func__, ERR_PTR(can_send_ret)); if (so->tx.idx >= so->tx.len) { /* we are done */ @@ -946,8 +946,8 @@ static int isotp_sendmsg(struct socket *sock, struct msghdr *msg, size_t size) err = can_send(skb, 1); dev_put(dev); if (err) { - pr_notice_once("can-isotp: %s: can_send_ret %d\n", - __func__, err); + pr_notice_once("can-isotp: %s: can_send_ret %pe\n", + __func__, ERR_PTR(err)); return err; } -- cgit From 6a5ddae578842652719fb926b22f1d510fe50bee Mon Sep 17 00:00:00 2001 From: Patrick Menschel Date: Tue, 27 Apr 2021 05:21:48 +0000 Subject: can: isotp: add symbolic error message to isotp_module_init() This patch adds the value of err with format %pe to the already existing error message. Link: https://lore.kernel.org/r/20210427052150.2308-3-menschel.p@posteo.de Signed-off-by: Patrick Menschel Signed-off-by: Marc Kleine-Budde --- net/can/isotp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/can/isotp.c b/net/can/isotp.c index 2c4f84fac70a..2075d8d9e6b6 100644 --- a/net/can/isotp.c +++ b/net/can/isotp.c @@ -1433,7 +1433,7 @@ static __init int isotp_module_init(void) err = can_proto_register(&isotp_can_proto); if (err < 0) - pr_err("can: registration of isotp protocol failed\n"); + pr_err("can: registration of isotp protocol failed %pe\n", ERR_PTR(err)); return err; } -- cgit From c69d190f7bb9a03cf5237d45a457993730d01605 Mon Sep 17 00:00:00 2001 From: Patrick Menschel Date: Tue, 27 Apr 2021 05:21:49 +0000 Subject: can: isotp: Add error message if txqueuelen is too small This patch adds an additional error message in case that txqueuelen is set too small and advices the user to increase txqueuelen. This is likely to happen even with small transfers if txqueuelen is at default value 10 frames. Link: https://lore.kernel.org/r/20210427052150.2308-4-menschel.p@posteo.de Signed-off-by: Patrick Menschel Signed-off-by: Marc Kleine-Budde --- net/can/isotp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/net/can/isotp.c b/net/can/isotp.c index 2075d8d9e6b6..5ff11aaf0a79 100644 --- a/net/can/isotp.c +++ b/net/can/isotp.c @@ -797,10 +797,12 @@ isotp_tx_burst: can_skb_set_owner(skb, sk); can_send_ret = can_send(skb, 1); - if (can_send_ret) + if (can_send_ret) { pr_notice_once("can-isotp: %s: can_send_ret %pe\n", __func__, ERR_PTR(can_send_ret)); - + if (can_send_ret == -ENOBUFS) + pr_notice_once("can-isotp: tx queue is full, increasing txqueuelen may prevent this error\n"); + } if (so->tx.idx >= so->tx.len) { /* we are done */ so->tx.state = ISOTP_IDLE; -- cgit From 9208f7bf053a6fb32f9276a3b78c2b7fb3c0b0cb Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Tue, 27 Apr 2021 18:52:47 +0800 Subject: can: softing: Remove redundant variable ptr The value stored to ptr in the calculations this patch removes is not used, so the calculation and the assignment can be removed. Cleans up the following clang-analyzer warning: drivers/net/can/softing/softing_main.c:279:3: warning: Value stored to 'ptr' is never read [clang-analyzer-deadcode.DeadStores]. drivers/net/can/softing/softing_main.c:242:3: warning: Value stored to 'ptr' is never read [clang-analyzer-deadcode.DeadStores]. Link: https://lore.kernel.org/r/1619520767-80948-1-git-send-email-jiapeng.chong@linux.alibaba.com Reported-by: Abaci Robot Signed-off-by: Jiapeng Chong Signed-off-by: Marc Kleine-Budde --- drivers/net/can/softing/softing_main.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/net/can/softing/softing_main.c b/drivers/net/can/softing/softing_main.c index c44f3411e561..cfc1325aad10 100644 --- a/drivers/net/can/softing/softing_main.c +++ b/drivers/net/can/softing/softing_main.c @@ -239,7 +239,6 @@ static int softing_handle_1(struct softing *card) DPRAM_INFO_BUSSTATE2 : DPRAM_INFO_BUSSTATE]); /* timestamp */ tmp_u32 = le32_to_cpup((void *)ptr); - ptr += 4; ktime = softing_raw2ktime(card, tmp_u32); ++netdev->stats.rx_errors; @@ -276,7 +275,6 @@ static int softing_handle_1(struct softing *card) ktime = softing_raw2ktime(card, tmp_u32); if (!(msg.can_id & CAN_RTR_FLAG)) memcpy(&msg.data[0], ptr, 8); - ptr += 8; /* update socket */ if (cmd & CMD_ACK) { /* acknowledge, was tx msg */ -- cgit From 83415669d8d830034c96e1de8ffb09b153a53504 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Tue, 4 May 2021 21:55:10 +0200 Subject: can: hi311x: hi3110_can_probe(): silence clang warning This patch silences the following clang warning: | drivers/net/can/spi/hi311x.c:874:17: warning: cast to smaller integer type | 'enum hi3110_model' from 'const void *' [-Wvoid-pointer-to-enum-cast] | priv->model = (enum hi3110_model)of_id->data; | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: 57e83fb9b746 ("can: hi311x: Add Holt HI-311x CAN driver") Link: https://lore.kernel.org/r/20210504200520.1179635-3-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde --- drivers/net/can/spi/hi311x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/can/spi/hi311x.c b/drivers/net/can/spi/hi311x.c index 6f5d6d04a8b9..dd17b8c53e1c 100644 --- a/drivers/net/can/spi/hi311x.c +++ b/drivers/net/can/spi/hi311x.c @@ -871,7 +871,7 @@ static int hi3110_can_probe(struct spi_device *spi) CAN_CTRLMODE_BERR_REPORTING; if (of_id) - priv->model = (enum hi3110_model)of_id->data; + priv->model = (enum hi3110_model)(uintptr_t)of_id->data; else priv->model = spi_get_device_id(spi)->driver_data; priv->net = net; -- cgit From 10462b3558d418929dad8312dd8ae5d40116c1eb Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Tue, 4 May 2021 21:55:10 +0200 Subject: can: mcp251x: mcp251x_can_probe(): silence clang warning This patch silences the following clang warning: | drivers/net/can/spi/mcp251x.c:1333:17: warning: cast to smaller integer type | 'enum mcp251x_model' from 'const void *' [-Wvoid-pointer-to-enum-cast] | priv->model = (enum mcp251x_model)match; | ^~~~~~~~~~~~~~~~~~~~~~~~~ Fixes: 8de29a5c34a5 ("can: mcp251x: Make use of device property API") Link: https://lore.kernel.org/r/20210504200520.1179635-2-mkl@pengutronix.de Reported-by: kernel test robot Cc: Andy Shevchenko Reviewed-by: Andy Shevchenko Signed-off-by: Marc Kleine-Budde --- drivers/net/can/spi/mcp251x.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/can/spi/mcp251x.c b/drivers/net/can/spi/mcp251x.c index 173c6614086f..0579ab74f728 100644 --- a/drivers/net/can/spi/mcp251x.c +++ b/drivers/net/can/spi/mcp251x.c @@ -1330,7 +1330,7 @@ static int mcp251x_can_probe(struct spi_device *spi) priv->can.ctrlmode_supported = CAN_CTRLMODE_3_SAMPLES | CAN_CTRLMODE_LOOPBACK | CAN_CTRLMODE_LISTENONLY; if (match) - priv->model = (enum mcp251x_model)match; + priv->model = (enum mcp251x_model)(uintptr_t)match; else priv->model = spi_get_device_id(spi)->driver_data; priv->net = net; -- cgit From b558e200d626b1761e4642e1acd2268fd30bddc6 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 5 May 2021 10:07:48 +0200 Subject: can: mcp251xfd: silence clang warning This patch fixes the following clang warning, by marking the functions as maybe unused. gcc doesn't complain about unused inline functions. | drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c:564:1: warning: unused function 'mcp251xfd_chip_set_mode_nowait' [-Wunused-function] | mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv, | ^ | 1 warning generated. Link: https://lore.kernel.org/r/20210514153741.1958041-3-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde --- drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c index e0ae00e34c7b..47c3f408a799 100644 --- a/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c +++ b/drivers/net/can/spi/mcp251xfd/mcp251xfd-core.c @@ -560,7 +560,7 @@ mcp251xfd_chip_set_mode(const struct mcp251xfd_priv *priv, return __mcp251xfd_chip_set_mode(priv, mode_req, false); } -static inline int +static inline int __maybe_unused mcp251xfd_chip_set_mode_nowait(const struct mcp251xfd_priv *priv, const u8 mode_req) { -- cgit From 4318b1aa22b7b44209ec5d079c83e3bae3b9c077 Mon Sep 17 00:00:00 2001 From: Marc Kleine-Budde Date: Wed, 5 May 2021 10:06:24 +0200 Subject: can: at91_can: silence clang warning This patch fixes the following clang warning, by marking the functions as maybe unused. gcc doesn't complain about unused inline functions. | drivers/net/can/at91_can.c:178:1: warning: unused function 'at91_is_sam9X5' [-Wunused-function] | AT91_IS(9X5); | ^ | drivers/net/can/at91_can.c:172:19: note: expanded from macro 'AT91_IS' | static inline int at91_is_sam##_model(const struct at91_priv *priv) \ | ^ | :66:1: note: expanded from here | at91_is_sam9X5 | ^ Link: https://lore.kernel.org/r/20210514153741.1958041-2-mkl@pengutronix.de Signed-off-by: Marc Kleine-Budde --- drivers/net/can/at91_can.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/can/at91_can.c b/drivers/net/can/at91_can.c index 9ad9b39f480e..04d0bb3ffe89 100644 --- a/drivers/net/can/at91_can.c +++ b/drivers/net/can/at91_can.c @@ -169,7 +169,7 @@ static const struct can_bittiming_const at91_bittiming_const = { }; #define AT91_IS(_model) \ -static inline int at91_is_sam##_model(const struct at91_priv *priv) \ +static inline int __maybe_unused at91_is_sam##_model(const struct at91_priv *priv) \ { \ return priv->devtype_data.type == AT91_DEVTYPE_SAM##_model; \ } -- cgit From 893974d9b5655792f3b8f490f5499d3b8886be18 Mon Sep 17 00:00:00 2001 From: Jimmy Assarsson Date: Thu, 29 Apr 2021 11:37:29 +0200 Subject: can: kvaser_usb: Rename define USB_HYBRID_{,PRO_}CANLIN_PRODUCT_ID Rename define USB_HYBRID_{,PRO_}CANLIN_PRODUCT_ID to USB_HYBRID_{,PRO_}2CANLIN_PRODUCT_ID, to reflect the channel count. Link: https://lore.kernel.org/r/20210429093730.499263-1-extja@kvaser.com Signed-off-by: Jimmy Assarsson Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c b/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c index 90ebcae13409..b2236bf63b41 100644 --- a/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c +++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c @@ -79,10 +79,10 @@ #define USB_USBCAN_PRO_2HS_V2_PRODUCT_ID 264 #define USB_MEMO_2HS_PRODUCT_ID 265 #define USB_MEMO_PRO_2HS_V2_PRODUCT_ID 266 -#define USB_HYBRID_CANLIN_PRODUCT_ID 267 +#define USB_HYBRID_2CANLIN_PRODUCT_ID 267 #define USB_ATI_USBCAN_PRO_2HS_V2_PRODUCT_ID 268 #define USB_ATI_MEMO_PRO_2HS_V2_PRODUCT_ID 269 -#define USB_HYBRID_PRO_CANLIN_PRODUCT_ID 270 +#define USB_HYBRID_PRO_2CANLIN_PRODUCT_ID 270 #define USB_U100_PRODUCT_ID 273 #define USB_U100P_PRODUCT_ID 274 #define USB_U100S_PRODUCT_ID 275 @@ -187,10 +187,10 @@ static const struct usb_device_id kvaser_usb_table[] = { { USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_PRO_2HS_V2_PRODUCT_ID) }, { USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO_2HS_PRODUCT_ID) }, { USB_DEVICE(KVASER_VENDOR_ID, USB_MEMO_PRO_2HS_V2_PRODUCT_ID) }, - { USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_CANLIN_PRODUCT_ID) }, + { USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_2CANLIN_PRODUCT_ID) }, { USB_DEVICE(KVASER_VENDOR_ID, USB_ATI_USBCAN_PRO_2HS_V2_PRODUCT_ID) }, { USB_DEVICE(KVASER_VENDOR_ID, USB_ATI_MEMO_PRO_2HS_V2_PRODUCT_ID) }, - { USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_PRO_CANLIN_PRODUCT_ID) }, + { USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_PRO_2CANLIN_PRODUCT_ID) }, { USB_DEVICE(KVASER_VENDOR_ID, USB_U100_PRODUCT_ID) }, { USB_DEVICE(KVASER_VENDOR_ID, USB_U100P_PRODUCT_ID) }, { USB_DEVICE(KVASER_VENDOR_ID, USB_U100S_PRODUCT_ID) }, -- cgit From ee6bb641bc70accfedb8d78fc957df73e6770858 Mon Sep 17 00:00:00 2001 From: Jimmy Assarsson Date: Thu, 29 Apr 2021 11:37:30 +0200 Subject: can: kvaser_usb: Add new Kvaser hydra devices Add new Kvaser hydra devices. Link: https://lore.kernel.org/r/20210429093730.499263-2-extja@kvaser.com Signed-off-by: Jimmy Assarsson Signed-off-by: Marc Kleine-Budde --- drivers/net/can/usb/Kconfig | 2 ++ drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c | 6 +++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/can/usb/Kconfig b/drivers/net/can/usb/Kconfig index 3deb9f1cd292..f959215c9d53 100644 --- a/drivers/net/can/usb/Kconfig +++ b/drivers/net/can/usb/Kconfig @@ -76,7 +76,9 @@ config CAN_KVASER_USB - Scania VCI2 (if you have the Kvaser logo on top) - Kvaser BlackBird v2 - Kvaser Leaf Pro HS v2 + - Kvaser Hybrid CAN/LIN - Kvaser Hybrid 2xCAN/LIN + - Kvaser Hybrid Pro CAN/LIN - Kvaser Hybrid Pro 2xCAN/LIN - Kvaser Memorator 2xHS v2 - Kvaser Memorator Pro 2xHS v2 diff --git a/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c b/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c index b2236bf63b41..0cc0fc866a2a 100644 --- a/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c +++ b/drivers/net/can/usb/kvaser_usb/kvaser_usb_core.c @@ -87,8 +87,10 @@ #define USB_U100P_PRODUCT_ID 274 #define USB_U100S_PRODUCT_ID 275 #define USB_USBCAN_PRO_4HS_PRODUCT_ID 276 +#define USB_HYBRID_CANLIN_PRODUCT_ID 277 +#define USB_HYBRID_PRO_CANLIN_PRODUCT_ID 278 #define USB_HYDRA_PRODUCT_ID_END \ - USB_USBCAN_PRO_4HS_PRODUCT_ID + USB_HYBRID_PRO_CANLIN_PRODUCT_ID static inline bool kvaser_is_leaf(const struct usb_device_id *id) { @@ -195,6 +197,8 @@ static const struct usb_device_id kvaser_usb_table[] = { { USB_DEVICE(KVASER_VENDOR_ID, USB_U100P_PRODUCT_ID) }, { USB_DEVICE(KVASER_VENDOR_ID, USB_U100S_PRODUCT_ID) }, { USB_DEVICE(KVASER_VENDOR_ID, USB_USBCAN_PRO_4HS_PRODUCT_ID) }, + { USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_CANLIN_PRODUCT_ID) }, + { USB_DEVICE(KVASER_VENDOR_ID, USB_HYBRID_PRO_CANLIN_PRODUCT_ID) }, { } }; MODULE_DEVICE_TABLE(usb, kvaser_usb_table); -- cgit From c7b0f6887d90665ac1aefd503c2eba1294f83473 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Sun, 9 May 2021 14:43:07 +0200 Subject: can: c_can: remove unused variable struct c_can_priv::rxmasked The member rxmasked of struct c_can_priv is initialized by c_can_chip_config(), but's it's never used, so remove it. Link: https://lore.kernel.org/r/20210509124309.30024-2-dariobin@libero.it Signed-off-by: Dario Binacchi Signed-off-by: Marc Kleine-Budde --- drivers/net/can/c_can/c_can.c | 1 - drivers/net/can/c_can/c_can.h | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/net/can/c_can/c_can.c b/drivers/net/can/c_can/c_can.c index 313793f6922d..1fa47968c2ec 100644 --- a/drivers/net/can/c_can/c_can.c +++ b/drivers/net/can/c_can/c_can.c @@ -599,7 +599,6 @@ static int c_can_chip_config(struct net_device *dev) /* Clear all internal status */ atomic_set(&priv->tx_active, 0); - priv->rxmasked = 0; priv->tx_dir = 0; /* set bittiming params */ diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h index 06045f610f0e..517845c4571e 100644 --- a/drivers/net/can/c_can/c_can.h +++ b/drivers/net/can/c_can/c_can.h @@ -205,7 +205,6 @@ struct c_can_priv { struct c_can_raminit raminit_sys; /* RAMINIT via syscon regmap */ void (*raminit)(const struct c_can_priv *priv, bool enable); u32 comm_rcv_high; - u32 rxmasked; u32 dlc[]; }; -- cgit From 2722ac986e93c4cabbefde299d01ed24db40a645 Mon Sep 17 00:00:00 2001 From: Dario Binacchi Date: Fri, 14 May 2021 18:55:47 +0200 Subject: can: c_can: add ethtool support With commit 132f2d45fb23 ("can: c_can: add support to 64 message objects") the number of message objects used for reception / transmission depends on FIFO size. The ethtools API support allows you to retrieve this info. Driver info has been added too. Link: https://lore.kernel.org/r/20210514165549.14365-2-dariobin@libero.it Signed-off-by: Dario Binacchi Reviewed-by: Andrew Lunn Signed-off-by: Marc Kleine-Budde --- drivers/net/can/c_can/Makefile | 5 + drivers/net/can/c_can/c_can.c | 1353 -------------------------------- drivers/net/can/c_can/c_can.h | 2 + drivers/net/can/c_can/c_can_ethtool.c | 43 ++ drivers/net/can/c_can/c_can_main.c | 1354 +++++++++++++++++++++++++++++++++ 5 files changed, 1404 insertions(+), 1353 deletions(-) delete mode 100644 drivers/net/can/c_can/c_can.c create mode 100644 drivers/net/can/c_can/c_can_ethtool.c create mode 100644 drivers/net/can/c_can/c_can_main.c diff --git a/drivers/net/can/c_can/Makefile b/drivers/net/can/c_can/Makefile index e6a94c948531..6fa3b2b9e4b9 100644 --- a/drivers/net/can/c_can/Makefile +++ b/drivers/net/can/c_can/Makefile @@ -4,5 +4,10 @@ # obj-$(CONFIG_CAN_C_CAN) += c_can.o + +c_can-objs := +c_can-objs += c_can_ethtool.o +c_can-objs += c_can_main.o + obj-$(CONFIG_CAN_C_CAN_PLATFORM) += c_can_platform.o obj-$(CONFIG_CAN_C_CAN_PCI) += c_can_pci.o diff --git a/drivers/net/can/c_can/c_can.c b/drivers/net/can/c_can/c_can.c deleted file mode 100644 index 1fa47968c2ec..000000000000 --- a/drivers/net/can/c_can/c_can.c +++ /dev/null @@ -1,1353 +0,0 @@ -/* - * CAN bus driver for Bosch C_CAN controller - * - * Copyright (C) 2010 ST Microelectronics - * Bhupesh Sharma - * - * Borrowed heavily from the C_CAN driver originally written by: - * Copyright (C) 2007 - * - Sascha Hauer, Marc Kleine-Budde, Pengutronix - * - Simon Kallweit, intefo AG - * - * TX and RX NAPI implementation has been borrowed from at91 CAN driver - * written by: - * Copyright - * (C) 2007 by Hans J. Koch - * (C) 2008, 2009 by Marc Kleine-Budde - * - * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. - * Bosch C_CAN user manual can be obtained from: - * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ - * users_manual_c_can.pdf - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include - -#include "c_can.h" - -/* Number of interface registers */ -#define IF_ENUM_REG_LEN 11 -#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) - -/* control extension register D_CAN specific */ -#define CONTROL_EX_PDR BIT(8) - -/* control register */ -#define CONTROL_SWR BIT(15) -#define CONTROL_TEST BIT(7) -#define CONTROL_CCE BIT(6) -#define CONTROL_DISABLE_AR BIT(5) -#define CONTROL_ENABLE_AR (0 << 5) -#define CONTROL_EIE BIT(3) -#define CONTROL_SIE BIT(2) -#define CONTROL_IE BIT(1) -#define CONTROL_INIT BIT(0) - -#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) - -/* test register */ -#define TEST_RX BIT(7) -#define TEST_TX1 BIT(6) -#define TEST_TX2 BIT(5) -#define TEST_LBACK BIT(4) -#define TEST_SILENT BIT(3) -#define TEST_BASIC BIT(2) - -/* status register */ -#define STATUS_PDA BIT(10) -#define STATUS_BOFF BIT(7) -#define STATUS_EWARN BIT(6) -#define STATUS_EPASS BIT(5) -#define STATUS_RXOK BIT(4) -#define STATUS_TXOK BIT(3) - -/* error counter register */ -#define ERR_CNT_TEC_MASK 0xff -#define ERR_CNT_TEC_SHIFT 0 -#define ERR_CNT_REC_SHIFT 8 -#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) -#define ERR_CNT_RP_SHIFT 15 -#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) - -/* bit-timing register */ -#define BTR_BRP_MASK 0x3f -#define BTR_BRP_SHIFT 0 -#define BTR_SJW_SHIFT 6 -#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) -#define BTR_TSEG1_SHIFT 8 -#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) -#define BTR_TSEG2_SHIFT 12 -#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) - -/* interrupt register */ -#define INT_STS_PENDING 0x8000 - -/* brp extension register */ -#define BRP_EXT_BRPE_MASK 0x0f -#define BRP_EXT_BRPE_SHIFT 0 - -/* IFx command request */ -#define IF_COMR_BUSY BIT(15) - -/* IFx command mask */ -#define IF_COMM_WR BIT(7) -#define IF_COMM_MASK BIT(6) -#define IF_COMM_ARB BIT(5) -#define IF_COMM_CONTROL BIT(4) -#define IF_COMM_CLR_INT_PND BIT(3) -#define IF_COMM_TXRQST BIT(2) -#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST -#define IF_COMM_DATAA BIT(1) -#define IF_COMM_DATAB BIT(0) - -/* TX buffer setup */ -#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ - IF_COMM_TXRQST | \ - IF_COMM_DATAA | IF_COMM_DATAB) - -/* For the low buffers we clear the interrupt bit, but keep newdat */ -#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ - IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ - IF_COMM_DATAA | IF_COMM_DATAB) - -/* For the high buffers we clear the interrupt bit and newdat */ -#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) - -/* Receive setup of message objects */ -#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) - -/* Invalidation of message objects */ -#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) - -/* IFx arbitration */ -#define IF_ARB_MSGVAL BIT(31) -#define IF_ARB_MSGXTD BIT(30) -#define IF_ARB_TRANSMIT BIT(29) - -/* IFx message control */ -#define IF_MCONT_NEWDAT BIT(15) -#define IF_MCONT_MSGLST BIT(14) -#define IF_MCONT_INTPND BIT(13) -#define IF_MCONT_UMASK BIT(12) -#define IF_MCONT_TXIE BIT(11) -#define IF_MCONT_RXIE BIT(10) -#define IF_MCONT_RMTEN BIT(9) -#define IF_MCONT_TXRQST BIT(8) -#define IF_MCONT_EOB BIT(7) -#define IF_MCONT_DLC_MASK 0xf - -#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) -#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) - -#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) - -/* Use IF1 for RX and IF2 for TX */ -#define IF_RX 0 -#define IF_TX 1 - -/* minimum timeout for checking BUSY status */ -#define MIN_TIMEOUT_VALUE 6 - -/* Wait for ~1 sec for INIT bit */ -#define INIT_WAIT_MS 1000 - -/* c_can lec values */ -enum c_can_lec_type { - LEC_NO_ERROR = 0, - LEC_STUFF_ERROR, - LEC_FORM_ERROR, - LEC_ACK_ERROR, - LEC_BIT1_ERROR, - LEC_BIT0_ERROR, - LEC_CRC_ERROR, - LEC_UNUSED, - LEC_MASK = LEC_UNUSED, -}; - -/* c_can error types: - * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported - */ -enum c_can_bus_error_types { - C_CAN_NO_ERROR = 0, - C_CAN_BUS_OFF, - C_CAN_ERROR_WARNING, - C_CAN_ERROR_PASSIVE, -}; - -static const struct can_bittiming_const c_can_bittiming_const = { - .name = KBUILD_MODNAME, - .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ - .tseg1_max = 16, - .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ - .tseg2_max = 8, - .sjw_max = 4, - .brp_min = 1, - .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ - .brp_inc = 1, -}; - -static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) -{ - if (priv->device) - pm_runtime_get_sync(priv->device); -} - -static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) -{ - if (priv->device) - pm_runtime_put_sync(priv->device); -} - -static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) -{ - if (priv->raminit) - priv->raminit(priv, enable); -} - -static void c_can_irq_control(struct c_can_priv *priv, bool enable) -{ - u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; - - if (enable) - ctrl |= CONTROL_IRQMSK; - - priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); -} - -static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) -{ - struct c_can_priv *priv = netdev_priv(dev); - int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); - - priv->write_reg32(priv, reg, (cmd << 16) | obj); - - for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { - if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) - return; - udelay(1); - } - netdev_err(dev, "Updating object timed out\n"); -} - -static inline void c_can_object_get(struct net_device *dev, int iface, - u32 obj, u32 cmd) -{ - c_can_obj_update(dev, iface, cmd, obj); -} - -static inline void c_can_object_put(struct net_device *dev, int iface, - u32 obj, u32 cmd) -{ - c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); -} - -/* Note: According to documentation clearing TXIE while MSGVAL is set - * is not allowed, but works nicely on C/DCAN. And that lowers the I/O - * load significantly. - */ -static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj) -{ - struct c_can_priv *priv = netdev_priv(dev); - - priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); - c_can_object_put(dev, iface, obj, IF_COMM_INVAL); -} - -static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) -{ - struct c_can_priv *priv = netdev_priv(dev); - - priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), 0); - c_can_inval_tx_object(dev, iface, obj); -} - -static void c_can_setup_tx_object(struct net_device *dev, int iface, - struct can_frame *frame, int idx) -{ - struct c_can_priv *priv = netdev_priv(dev); - u16 ctrl = IF_MCONT_TX | frame->len; - bool rtr = frame->can_id & CAN_RTR_FLAG; - u32 arb = IF_ARB_MSGVAL; - int i; - - if (frame->can_id & CAN_EFF_FLAG) { - arb |= frame->can_id & CAN_EFF_MASK; - arb |= IF_ARB_MSGXTD; - } else { - arb |= (frame->can_id & CAN_SFF_MASK) << 18; - } - - if (!rtr) - arb |= IF_ARB_TRANSMIT; - - /* If we change the DIR bit, we need to invalidate the buffer - * first, i.e. clear the MSGVAL flag in the arbiter. - */ - if (rtr != (bool)test_bit(idx, &priv->tx_dir)) { - u32 obj = idx + priv->msg_obj_tx_first; - - c_can_inval_msg_object(dev, iface, obj); - change_bit(idx, &priv->tx_dir); - } - - priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb); - - priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); - - if (priv->type == BOSCH_D_CAN) { - u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface); - - for (i = 0; i < frame->len; i += 4, dreg += 2) { - data = (u32)frame->data[i]; - data |= (u32)frame->data[i + 1] << 8; - data |= (u32)frame->data[i + 2] << 16; - data |= (u32)frame->data[i + 3] << 24; - priv->write_reg32(priv, dreg, data); - } - } else { - for (i = 0; i < frame->len; i += 2) { - priv->write_reg(priv, - C_CAN_IFACE(DATA1_REG, iface) + i / 2, - frame->data[i] | - (frame->data[i + 1] << 8)); - } - } -} - -static int c_can_handle_lost_msg_obj(struct net_device *dev, - int iface, int objno, u32 ctrl) -{ - struct net_device_stats *stats = &dev->stats; - struct c_can_priv *priv = netdev_priv(dev); - struct can_frame *frame; - struct sk_buff *skb; - - ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); - priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); - c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); - - stats->rx_errors++; - stats->rx_over_errors++; - - /* create an error msg */ - skb = alloc_can_err_skb(dev, &frame); - if (unlikely(!skb)) - return 0; - - frame->can_id |= CAN_ERR_CRTL; - frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; - - netif_receive_skb(skb); - return 1; -} - -static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) -{ - struct net_device_stats *stats = &dev->stats; - struct c_can_priv *priv = netdev_priv(dev); - struct can_frame *frame; - struct sk_buff *skb; - u32 arb, data; - - skb = alloc_can_skb(dev, &frame); - if (!skb) { - stats->rx_dropped++; - return -ENOMEM; - } - - frame->len = can_cc_dlc2len(ctrl & 0x0F); - - arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface)); - - if (arb & IF_ARB_MSGXTD) - frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; - else - frame->can_id = (arb >> 18) & CAN_SFF_MASK; - - if (arb & IF_ARB_TRANSMIT) { - frame->can_id |= CAN_RTR_FLAG; - } else { - int i, dreg = C_CAN_IFACE(DATA1_REG, iface); - - if (priv->type == BOSCH_D_CAN) { - for (i = 0; i < frame->len; i += 4, dreg += 2) { - data = priv->read_reg32(priv, dreg); - frame->data[i] = data; - frame->data[i + 1] = data >> 8; - frame->data[i + 2] = data >> 16; - frame->data[i + 3] = data >> 24; - } - } else { - for (i = 0; i < frame->len; i += 2, dreg++) { - data = priv->read_reg(priv, dreg); - frame->data[i] = data; - frame->data[i + 1] = data >> 8; - } - } - } - - stats->rx_packets++; - stats->rx_bytes += frame->len; - - netif_receive_skb(skb); - return 0; -} - -static void c_can_setup_receive_object(struct net_device *dev, int iface, - u32 obj, u32 mask, u32 id, u32 mcont) -{ - struct c_can_priv *priv = netdev_priv(dev); - - mask |= BIT(29); - priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask); - - id |= IF_ARB_MSGVAL; - priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id); - - priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); - c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); -} - -static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, - struct net_device *dev) -{ - struct can_frame *frame = (struct can_frame *)skb->data; - struct c_can_priv *priv = netdev_priv(dev); - u32 idx, obj; - - if (can_dropped_invalid_skb(dev, skb)) - return NETDEV_TX_OK; - /* This is not a FIFO. C/D_CAN sends out the buffers - * prioritized. The lowest buffer number wins. - */ - idx = fls(atomic_read(&priv->tx_active)); - obj = idx + priv->msg_obj_tx_first; - - /* If this is the last buffer, stop the xmit queue */ - if (idx == priv->msg_obj_tx_num - 1) - netif_stop_queue(dev); - /* Store the message in the interface so we can call - * can_put_echo_skb(). We must do this before we enable - * transmit as we might race against do_tx(). - */ - c_can_setup_tx_object(dev, IF_TX, frame, idx); - priv->dlc[idx] = frame->len; - can_put_echo_skb(skb, dev, idx, 0); - - /* Update the active bits */ - atomic_add(BIT(idx), &priv->tx_active); - /* Start transmission */ - c_can_object_put(dev, IF_TX, obj, IF_COMM_TX); - - return NETDEV_TX_OK; -} - -static int c_can_wait_for_ctrl_init(struct net_device *dev, - struct c_can_priv *priv, u32 init) -{ - int retry = 0; - - while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { - udelay(10); - if (retry++ > 1000) { - netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); - return -EIO; - } - } - return 0; -} - -static int c_can_set_bittiming(struct net_device *dev) -{ - unsigned int reg_btr, reg_brpe, ctrl_save; - u8 brp, brpe, sjw, tseg1, tseg2; - u32 ten_bit_brp; - struct c_can_priv *priv = netdev_priv(dev); - const struct can_bittiming *bt = &priv->can.bittiming; - int res; - - /* c_can provides a 6-bit brp and 4-bit brpe fields */ - ten_bit_brp = bt->brp - 1; - brp = ten_bit_brp & BTR_BRP_MASK; - brpe = ten_bit_brp >> 6; - - sjw = bt->sjw - 1; - tseg1 = bt->prop_seg + bt->phase_seg1 - 1; - tseg2 = bt->phase_seg2 - 1; - reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | - (tseg2 << BTR_TSEG2_SHIFT); - reg_brpe = brpe & BRP_EXT_BRPE_MASK; - - netdev_info(dev, - "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); - - ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); - ctrl_save &= ~CONTROL_INIT; - priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); - res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); - if (res) - return res; - - priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); - priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); - priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); - - return c_can_wait_for_ctrl_init(dev, priv, 0); -} - -/* Configure C_CAN message objects for Tx and Rx purposes: - * C_CAN provides a total of 32 message objects that can be configured - * either for Tx or Rx purposes. Here the first 16 message objects are used as - * a reception FIFO. The end of reception FIFO is signified by the EoB bit - * being SET. The remaining 16 message objects are kept aside for Tx purposes. - * See user guide document for further details on configuring message - * objects. - */ -static void c_can_configure_msg_objects(struct net_device *dev) -{ - struct c_can_priv *priv = netdev_priv(dev); - int i; - - /* first invalidate all message objects */ - for (i = priv->msg_obj_rx_first; i <= priv->msg_obj_num; i++) - c_can_inval_msg_object(dev, IF_RX, i); - - /* setup receive message objects */ - for (i = priv->msg_obj_rx_first; i < priv->msg_obj_rx_last; i++) - c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV); - - c_can_setup_receive_object(dev, IF_RX, priv->msg_obj_rx_last, 0, 0, - IF_MCONT_RCV_EOB); -} - -static int c_can_software_reset(struct net_device *dev) -{ - struct c_can_priv *priv = netdev_priv(dev); - int retry = 0; - - if (priv->type != BOSCH_D_CAN) - return 0; - - priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT); - while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) { - msleep(20); - if (retry++ > 100) { - netdev_err(dev, "CCTRL: software reset failed\n"); - return -EIO; - } - } - - return 0; -} - -/* Configure C_CAN chip: - * - enable/disable auto-retransmission - * - set operating mode - * - configure message objects - */ -static int c_can_chip_config(struct net_device *dev) -{ - struct c_can_priv *priv = netdev_priv(dev); - int err; - - err = c_can_software_reset(dev); - if (err) - return err; - - /* enable automatic retransmission */ - priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); - - if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && - (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { - /* loopback + silent mode : useful for hot self-test */ - priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); - priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); - } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { - /* loopback mode : useful for self-test function */ - priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); - priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); - } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { - /* silent mode : bus-monitoring mode */ - priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); - priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); - } - - /* configure message objects */ - c_can_configure_msg_objects(dev); - - /* set a `lec` value so that we can check for updates later */ - priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); - - /* Clear all internal status */ - atomic_set(&priv->tx_active, 0); - priv->tx_dir = 0; - - /* set bittiming params */ - return c_can_set_bittiming(dev); -} - -static int c_can_start(struct net_device *dev) -{ - struct c_can_priv *priv = netdev_priv(dev); - int err; - struct pinctrl *p; - - /* basic c_can configuration */ - err = c_can_chip_config(dev); - if (err) - return err; - - /* Setup the command for new messages */ - priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? - IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; - - priv->can.state = CAN_STATE_ERROR_ACTIVE; - - /* Attempt to use "active" if available else use "default" */ - p = pinctrl_get_select(priv->device, "active"); - if (!IS_ERR(p)) - pinctrl_put(p); - else - pinctrl_pm_select_default_state(priv->device); - - return 0; -} - -static void c_can_stop(struct net_device *dev) -{ - struct c_can_priv *priv = netdev_priv(dev); - - c_can_irq_control(priv, false); - - /* put ctrl to init on stop to end ongoing transmission */ - priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT); - - /* deactivate pins */ - pinctrl_pm_select_sleep_state(dev->dev.parent); - priv->can.state = CAN_STATE_STOPPED; -} - -static int c_can_set_mode(struct net_device *dev, enum can_mode mode) -{ - struct c_can_priv *priv = netdev_priv(dev); - int err; - - switch (mode) { - case CAN_MODE_START: - err = c_can_start(dev); - if (err) - return err; - netif_wake_queue(dev); - c_can_irq_control(priv, true); - break; - default: - return -EOPNOTSUPP; - } - - return 0; -} - -static int __c_can_get_berr_counter(const struct net_device *dev, - struct can_berr_counter *bec) -{ - unsigned int reg_err_counter; - struct c_can_priv *priv = netdev_priv(dev); - - reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); - bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> - ERR_CNT_REC_SHIFT; - bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; - - return 0; -} - -static int c_can_get_berr_counter(const struct net_device *dev, - struct can_berr_counter *bec) -{ - struct c_can_priv *priv = netdev_priv(dev); - int err; - - c_can_pm_runtime_get_sync(priv); - err = __c_can_get_berr_counter(dev, bec); - c_can_pm_runtime_put_sync(priv); - - return err; -} - -static void c_can_do_tx(struct net_device *dev) -{ - struct c_can_priv *priv = netdev_priv(dev); - struct net_device_stats *stats = &dev->stats; - u32 idx, obj, pkts = 0, bytes = 0, pend, clr; - - if (priv->msg_obj_tx_last > 32) - pend = priv->read_reg32(priv, C_CAN_INTPND3_REG); - else - pend = priv->read_reg(priv, C_CAN_INTPND2_REG); - clr = pend; - - while ((idx = ffs(pend))) { - idx--; - pend &= ~BIT(idx); - obj = idx + priv->msg_obj_tx_first; - - /* We use IF_RX interface instead of IF_TX because we - * are called from c_can_poll(), which runs inside - * NAPI. We are not trasmitting. - */ - c_can_inval_tx_object(dev, IF_RX, obj); - can_get_echo_skb(dev, idx, NULL); - bytes += priv->dlc[idx]; - pkts++; - } - - /* Clear the bits in the tx_active mask */ - atomic_sub(clr, &priv->tx_active); - - if (clr & BIT(priv->msg_obj_tx_num - 1)) - netif_wake_queue(dev); - - if (pkts) { - stats->tx_bytes += bytes; - stats->tx_packets += pkts; - can_led_event(dev, CAN_LED_EVENT_TX); - } -} - -/* If we have a gap in the pending bits, that means we either - * raced with the hardware or failed to readout all upper - * objects in the last run due to quota limit. - */ -static u32 c_can_adjust_pending(u32 pend, u32 rx_mask) -{ - u32 weight, lasts; - - if (pend == rx_mask) - return pend; - - /* If the last set bit is larger than the number of pending - * bits we have a gap. - */ - weight = hweight32(pend); - lasts = fls(pend); - - /* If the bits are linear, nothing to do */ - if (lasts == weight) - return pend; - - /* Find the first set bit after the gap. We walk backwards - * from the last set bit. - */ - for (lasts--; pend & BIT(lasts - 1); lasts--) - ; - - return pend & ~GENMASK(lasts - 1, 0); -} - -static inline void c_can_rx_object_get(struct net_device *dev, - struct c_can_priv *priv, u32 obj) -{ - c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high); -} - -static inline void c_can_rx_finalize(struct net_device *dev, - struct c_can_priv *priv, u32 obj) -{ - if (priv->type != BOSCH_D_CAN) - c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT); -} - -static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, - u32 pend, int quota) -{ - u32 pkts = 0, ctrl, obj; - - while ((obj = ffs(pend)) && quota > 0) { - pend &= ~BIT(obj - 1); - - c_can_rx_object_get(dev, priv, obj); - ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); - - if (ctrl & IF_MCONT_MSGLST) { - int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); - - pkts += n; - quota -= n; - continue; - } - - /* This really should not happen, but this covers some - * odd HW behaviour. Do not remove that unless you - * want to brick your machine. - */ - if (!(ctrl & IF_MCONT_NEWDAT)) - continue; - - /* read the data from the message object */ - c_can_read_msg_object(dev, IF_RX, ctrl); - - c_can_rx_finalize(dev, priv, obj); - - pkts++; - quota--; - } - - return pkts; -} - -static inline u32 c_can_get_pending(struct c_can_priv *priv) -{ - u32 pend; - - if (priv->msg_obj_rx_last > 16) - pend = priv->read_reg32(priv, C_CAN_NEWDAT1_REG); - else - pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); - - return pend; -} - -/* theory of operation: - * - * c_can core saves a received CAN message into the first free message - * object it finds free (starting with the lowest). Bits NEWDAT and - * INTPND are set for this message object indicating that a new message - * has arrived. - * - * We clear the newdat bit right away. - * - * This can result in packet reordering when the readout is slow. - */ -static int c_can_do_rx_poll(struct net_device *dev, int quota) -{ - struct c_can_priv *priv = netdev_priv(dev); - u32 pkts = 0, pend = 0, toread, n; - - while (quota > 0) { - if (!pend) { - pend = c_can_get_pending(priv); - if (!pend) - break; - /* If the pending field has a gap, handle the - * bits above the gap first. - */ - toread = c_can_adjust_pending(pend, - priv->msg_obj_rx_mask); - } else { - toread = pend; - } - /* Remove the bits from pend */ - pend &= ~toread; - /* Read the objects */ - n = c_can_read_objects(dev, priv, toread, quota); - pkts += n; - quota -= n; - } - - if (pkts) - can_led_event(dev, CAN_LED_EVENT_RX); - - return pkts; -} - -static int c_can_handle_state_change(struct net_device *dev, - enum c_can_bus_error_types error_type) -{ - unsigned int reg_err_counter; - unsigned int rx_err_passive; - struct c_can_priv *priv = netdev_priv(dev); - struct net_device_stats *stats = &dev->stats; - struct can_frame *cf; - struct sk_buff *skb; - struct can_berr_counter bec; - - switch (error_type) { - case C_CAN_NO_ERROR: - priv->can.state = CAN_STATE_ERROR_ACTIVE; - break; - case C_CAN_ERROR_WARNING: - /* error warning state */ - priv->can.can_stats.error_warning++; - priv->can.state = CAN_STATE_ERROR_WARNING; - break; - case C_CAN_ERROR_PASSIVE: - /* error passive state */ - priv->can.can_stats.error_passive++; - priv->can.state = CAN_STATE_ERROR_PASSIVE; - break; - case C_CAN_BUS_OFF: - /* bus-off state */ - priv->can.state = CAN_STATE_BUS_OFF; - priv->can.can_stats.bus_off++; - break; - default: - break; - } - - /* propagate the error condition to the CAN stack */ - skb = alloc_can_err_skb(dev, &cf); - if (unlikely(!skb)) - return 0; - - __c_can_get_berr_counter(dev, &bec); - reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); - rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> - ERR_CNT_RP_SHIFT; - - switch (error_type) { - case C_CAN_NO_ERROR: - /* error warning state */ - cf->can_id |= CAN_ERR_CRTL; - cf->data[1] = CAN_ERR_CRTL_ACTIVE; - cf->data[6] = bec.txerr; - cf->data[7] = bec.rxerr; - break; - case C_CAN_ERROR_WARNING: - /* error warning state */ - cf->can_id |= CAN_ERR_CRTL; - cf->data[1] = (bec.txerr > bec.rxerr) ? - CAN_ERR_CRTL_TX_WARNING : - CAN_ERR_CRTL_RX_WARNING; - cf->data[6] = bec.txerr; - cf->data[7] = bec.rxerr; - - break; - case C_CAN_ERROR_PASSIVE: - /* error passive state */ - cf->can_id |= CAN_ERR_CRTL; - if (rx_err_passive) - cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; - if (bec.txerr > 127) - cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; - - cf->data[6] = bec.txerr; - cf->data[7] = bec.rxerr; - break; - case C_CAN_BUS_OFF: - /* bus-off state */ - cf->can_id |= CAN_ERR_BUSOFF; - can_bus_off(dev); - break; - default: - break; - } - - stats->rx_packets++; - stats->rx_bytes += cf->len; - netif_receive_skb(skb); - - return 1; -} - -static int c_can_handle_bus_err(struct net_device *dev, - enum c_can_lec_type lec_type) -{ - struct c_can_priv *priv = netdev_priv(dev); - struct net_device_stats *stats = &dev->stats; - struct can_frame *cf; - struct sk_buff *skb; - - /* early exit if no lec update or no error. - * no lec update means that no CAN bus event has been detected - * since CPU wrote 0x7 value to status reg. - */ - if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) - return 0; - - if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) - return 0; - - /* common for all type of bus errors */ - priv->can.can_stats.bus_error++; - stats->rx_errors++; - - /* propagate the error condition to the CAN stack */ - skb = alloc_can_err_skb(dev, &cf); - if (unlikely(!skb)) - return 0; - - /* check for 'last error code' which tells us the - * type of the last error to occur on the CAN bus - */ - cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; - - switch (lec_type) { - case LEC_STUFF_ERROR: - netdev_dbg(dev, "stuff error\n"); - cf->data[2] |= CAN_ERR_PROT_STUFF; - break; - case LEC_FORM_ERROR: - netdev_dbg(dev, "form error\n"); - cf->data[2] |= CAN_ERR_PROT_FORM; - break; - case LEC_ACK_ERROR: - netdev_dbg(dev, "ack error\n"); - cf->data[3] = CAN_ERR_PROT_LOC_ACK; - break; - case LEC_BIT1_ERROR: - netdev_dbg(dev, "bit1 error\n"); - cf->data[2] |= CAN_ERR_PROT_BIT1; - break; - case LEC_BIT0_ERROR: - netdev_dbg(dev, "bit0 error\n"); - cf->data[2] |= CAN_ERR_PROT_BIT0; - break; - case LEC_CRC_ERROR: - netdev_dbg(dev, "CRC error\n"); - cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; - break; - default: - break; - } - - stats->rx_packets++; - stats->rx_bytes += cf->len; - netif_receive_skb(skb); - return 1; -} - -static int c_can_poll(struct napi_struct *napi, int quota) -{ - struct net_device *dev = napi->dev; - struct c_can_priv *priv = netdev_priv(dev); - u16 curr, last = priv->last_status; - int work_done = 0; - - /* Only read the status register if a status interrupt was pending */ - if (atomic_xchg(&priv->sie_pending, 0)) { - priv->last_status = priv->read_reg(priv, C_CAN_STS_REG); - curr = priv->last_status; - /* Ack status on C_CAN. D_CAN is self clearing */ - if (priv->type != BOSCH_D_CAN) - priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); - } else { - /* no change detected ... */ - curr = last; - } - - /* handle state changes */ - if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { - netdev_dbg(dev, "entered error warning state\n"); - work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); - } - - if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { - netdev_dbg(dev, "entered error passive state\n"); - work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); - } - - if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { - netdev_dbg(dev, "entered bus off state\n"); - work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); - goto end; - } - - /* handle bus recovery events */ - if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { - netdev_dbg(dev, "left bus off state\n"); - work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); - } - - if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { - netdev_dbg(dev, "left error passive state\n"); - work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); - } - - if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) { - netdev_dbg(dev, "left error warning state\n"); - work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR); - } - - /* handle lec errors on the bus */ - work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); - - /* Handle Tx/Rx events. We do this unconditionally */ - work_done += c_can_do_rx_poll(dev, (quota - work_done)); - c_can_do_tx(dev); - -end: - if (work_done < quota) { - napi_complete_done(napi, work_done); - /* enable all IRQs if we are not in bus off state */ - if (priv->can.state != CAN_STATE_BUS_OFF) - c_can_irq_control(priv, true); - } - - return work_done; -} - -static irqreturn_t c_can_isr(int irq, void *dev_id) -{ - struct net_device *dev = (struct net_device *)dev_id; - struct c_can_priv *priv = netdev_priv(dev); - int reg_int; - - reg_int = priv->read_reg(priv, C_CAN_INT_REG); - if (!reg_int) - return IRQ_NONE; - - /* save for later use */ - if (reg_int & INT_STS_PENDING) - atomic_set(&priv->sie_pending, 1); - - /* disable all interrupts and schedule the NAPI */ - c_can_irq_control(priv, false); - napi_schedule(&priv->napi); - - return IRQ_HANDLED; -} - -static int c_can_open(struct net_device *dev) -{ - int err; - struct c_can_priv *priv = netdev_priv(dev); - - c_can_pm_runtime_get_sync(priv); - c_can_reset_ram(priv, true); - - /* open the can device */ - err = open_candev(dev); - if (err) { - netdev_err(dev, "failed to open can device\n"); - goto exit_open_fail; - } - - /* register interrupt handler */ - err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, - dev); - if (err < 0) { - netdev_err(dev, "failed to request interrupt\n"); - goto exit_irq_fail; - } - - /* start the c_can controller */ - err = c_can_start(dev); - if (err) - goto exit_start_fail; - - can_led_event(dev, CAN_LED_EVENT_OPEN); - - napi_enable(&priv->napi); - /* enable status change, error and module interrupts */ - c_can_irq_control(priv, true); - netif_start_queue(dev); - - return 0; - -exit_start_fail: - free_irq(dev->irq, dev); -exit_irq_fail: - close_candev(dev); -exit_open_fail: - c_can_reset_ram(priv, false); - c_can_pm_runtime_put_sync(priv); - return err; -} - -static int c_can_close(struct net_device *dev) -{ - struct c_can_priv *priv = netdev_priv(dev); - - netif_stop_queue(dev); - napi_disable(&priv->napi); - c_can_stop(dev); - free_irq(dev->irq, dev); - close_candev(dev); - - c_can_reset_ram(priv, false); - c_can_pm_runtime_put_sync(priv); - - can_led_event(dev, CAN_LED_EVENT_STOP); - - return 0; -} - -struct net_device *alloc_c_can_dev(int msg_obj_num) -{ - struct net_device *dev; - struct c_can_priv *priv; - int msg_obj_tx_num = msg_obj_num / 2; - - dev = alloc_candev(struct_size(priv, dlc, msg_obj_tx_num), - msg_obj_tx_num); - if (!dev) - return NULL; - - priv = netdev_priv(dev); - priv->msg_obj_num = msg_obj_num; - priv->msg_obj_rx_num = msg_obj_num - msg_obj_tx_num; - priv->msg_obj_rx_first = 1; - priv->msg_obj_rx_last = - priv->msg_obj_rx_first + priv->msg_obj_rx_num - 1; - priv->msg_obj_rx_mask = GENMASK(priv->msg_obj_rx_num - 1, 0); - - priv->msg_obj_tx_num = msg_obj_tx_num; - priv->msg_obj_tx_first = priv->msg_obj_rx_last + 1; - priv->msg_obj_tx_last = - priv->msg_obj_tx_first + priv->msg_obj_tx_num - 1; - - netif_napi_add(dev, &priv->napi, c_can_poll, priv->msg_obj_rx_num); - - priv->dev = dev; - priv->can.bittiming_const = &c_can_bittiming_const; - priv->can.do_set_mode = c_can_set_mode; - priv->can.do_get_berr_counter = c_can_get_berr_counter; - priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | - CAN_CTRLMODE_LISTENONLY | - CAN_CTRLMODE_BERR_REPORTING; - - return dev; -} -EXPORT_SYMBOL_GPL(alloc_c_can_dev); - -#ifdef CONFIG_PM -int c_can_power_down(struct net_device *dev) -{ - u32 val; - unsigned long time_out; - struct c_can_priv *priv = netdev_priv(dev); - - if (!(dev->flags & IFF_UP)) - return 0; - - WARN_ON(priv->type != BOSCH_D_CAN); - - /* set PDR value so the device goes to power down mode */ - val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); - val |= CONTROL_EX_PDR; - priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); - - /* Wait for the PDA bit to get set */ - time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); - while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && - time_after(time_out, jiffies)) - cpu_relax(); - - if (time_after(jiffies, time_out)) - return -ETIMEDOUT; - - c_can_stop(dev); - - c_can_reset_ram(priv, false); - c_can_pm_runtime_put_sync(priv); - - return 0; -} -EXPORT_SYMBOL_GPL(c_can_power_down); - -int c_can_power_up(struct net_device *dev) -{ - u32 val; - unsigned long time_out; - struct c_can_priv *priv = netdev_priv(dev); - int ret; - - if (!(dev->flags & IFF_UP)) - return 0; - - WARN_ON(priv->type != BOSCH_D_CAN); - - c_can_pm_runtime_get_sync(priv); - c_can_reset_ram(priv, true); - - /* Clear PDR and INIT bits */ - val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); - val &= ~CONTROL_EX_PDR; - priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); - val = priv->read_reg(priv, C_CAN_CTRL_REG); - val &= ~CONTROL_INIT; - priv->write_reg(priv, C_CAN_CTRL_REG, val); - - /* Wait for the PDA bit to get clear */ - time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); - while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && - time_after(time_out, jiffies)) - cpu_relax(); - - if (time_after(jiffies, time_out)) { - ret = -ETIMEDOUT; - goto err_out; - } - - ret = c_can_start(dev); - if (ret) - goto err_out; - - c_can_irq_control(priv, true); - - return 0; - -err_out: - c_can_reset_ram(priv, false); - c_can_pm_runtime_put_sync(priv); - - return ret; -} -EXPORT_SYMBOL_GPL(c_can_power_up); -#endif - -void free_c_can_dev(struct net_device *dev) -{ - struct c_can_priv *priv = netdev_priv(dev); - - netif_napi_del(&priv->napi); - free_candev(dev); -} -EXPORT_SYMBOL_GPL(free_c_can_dev); - -static const struct net_device_ops c_can_netdev_ops = { - .ndo_open = c_can_open, - .ndo_stop = c_can_close, - .ndo_start_xmit = c_can_start_xmit, - .ndo_change_mtu = can_change_mtu, -}; - -int register_c_can_dev(struct net_device *dev) -{ - int err; - - /* Deactivate pins to prevent DRA7 DCAN IP from being - * stuck in transition when module is disabled. - * Pins are activated in c_can_start() and deactivated - * in c_can_stop() - */ - pinctrl_pm_select_sleep_state(dev->dev.parent); - - dev->flags |= IFF_ECHO; /* we support local echo */ - dev->netdev_ops = &c_can_netdev_ops; - - err = register_candev(dev); - if (!err) - devm_can_led_init(dev); - return err; -} -EXPORT_SYMBOL_GPL(register_c_can_dev); - -void unregister_c_can_dev(struct net_device *dev) -{ - unregister_candev(dev); -} -EXPORT_SYMBOL_GPL(unregister_c_can_dev); - -MODULE_AUTHOR("Bhupesh Sharma "); -MODULE_LICENSE("GPL v2"); -MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); diff --git a/drivers/net/can/c_can/c_can.h b/drivers/net/can/c_can/c_can.h index 517845c4571e..4247ff80a29c 100644 --- a/drivers/net/can/c_can/c_can.h +++ b/drivers/net/can/c_can/c_can.h @@ -218,4 +218,6 @@ int c_can_power_up(struct net_device *dev); int c_can_power_down(struct net_device *dev); #endif +void c_can_set_ethtool_ops(struct net_device *dev); + #endif /* C_CAN_H */ diff --git a/drivers/net/can/c_can/c_can_ethtool.c b/drivers/net/can/c_can/c_can_ethtool.c new file mode 100644 index 000000000000..cd5f07fca2a5 --- /dev/null +++ b/drivers/net/can/c_can/c_can_ethtool.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright 2021, Dario Binacchi + */ + +#include +#include +#include +#include +#include + +#include "c_can.h" + +static void c_can_get_drvinfo(struct net_device *netdev, + struct ethtool_drvinfo *info) +{ + struct c_can_priv *priv = netdev_priv(netdev); + struct platform_device *pdev = to_platform_device(priv->device); + + strscpy(info->driver, "c_can", sizeof(info->driver)); + strscpy(info->bus_info, pdev->name, sizeof(info->bus_info)); +} + +static void c_can_get_ringparam(struct net_device *netdev, + struct ethtool_ringparam *ring) +{ + struct c_can_priv *priv = netdev_priv(netdev); + + ring->rx_max_pending = priv->msg_obj_num; + ring->tx_max_pending = priv->msg_obj_num; + ring->rx_pending = priv->msg_obj_rx_num; + ring->tx_pending = priv->msg_obj_tx_num; +} + +static const struct ethtool_ops c_can_ethtool_ops = { + .get_drvinfo = c_can_get_drvinfo, + .get_ringparam = c_can_get_ringparam, +}; + +void c_can_set_ethtool_ops(struct net_device *netdev) +{ + netdev->ethtool_ops = &c_can_ethtool_ops; +} diff --git a/drivers/net/can/c_can/c_can_main.c b/drivers/net/can/c_can/c_can_main.c new file mode 100644 index 000000000000..7588f70ca0fe --- /dev/null +++ b/drivers/net/can/c_can/c_can_main.c @@ -0,0 +1,1354 @@ +/* + * CAN bus driver for Bosch C_CAN controller + * + * Copyright (C) 2010 ST Microelectronics + * Bhupesh Sharma + * + * Borrowed heavily from the C_CAN driver originally written by: + * Copyright (C) 2007 + * - Sascha Hauer, Marc Kleine-Budde, Pengutronix + * - Simon Kallweit, intefo AG + * + * TX and RX NAPI implementation has been borrowed from at91 CAN driver + * written by: + * Copyright + * (C) 2007 by Hans J. Koch + * (C) 2008, 2009 by Marc Kleine-Budde + * + * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B. + * Bosch C_CAN user manual can be obtained from: + * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/ + * users_manual_c_can.pdf + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "c_can.h" + +/* Number of interface registers */ +#define IF_ENUM_REG_LEN 11 +#define C_CAN_IFACE(reg, iface) (C_CAN_IF1_##reg + (iface) * IF_ENUM_REG_LEN) + +/* control extension register D_CAN specific */ +#define CONTROL_EX_PDR BIT(8) + +/* control register */ +#define CONTROL_SWR BIT(15) +#define CONTROL_TEST BIT(7) +#define CONTROL_CCE BIT(6) +#define CONTROL_DISABLE_AR BIT(5) +#define CONTROL_ENABLE_AR (0 << 5) +#define CONTROL_EIE BIT(3) +#define CONTROL_SIE BIT(2) +#define CONTROL_IE BIT(1) +#define CONTROL_INIT BIT(0) + +#define CONTROL_IRQMSK (CONTROL_EIE | CONTROL_IE | CONTROL_SIE) + +/* test register */ +#define TEST_RX BIT(7) +#define TEST_TX1 BIT(6) +#define TEST_TX2 BIT(5) +#define TEST_LBACK BIT(4) +#define TEST_SILENT BIT(3) +#define TEST_BASIC BIT(2) + +/* status register */ +#define STATUS_PDA BIT(10) +#define STATUS_BOFF BIT(7) +#define STATUS_EWARN BIT(6) +#define STATUS_EPASS BIT(5) +#define STATUS_RXOK BIT(4) +#define STATUS_TXOK BIT(3) + +/* error counter register */ +#define ERR_CNT_TEC_MASK 0xff +#define ERR_CNT_TEC_SHIFT 0 +#define ERR_CNT_REC_SHIFT 8 +#define ERR_CNT_REC_MASK (0x7f << ERR_CNT_REC_SHIFT) +#define ERR_CNT_RP_SHIFT 15 +#define ERR_CNT_RP_MASK (0x1 << ERR_CNT_RP_SHIFT) + +/* bit-timing register */ +#define BTR_BRP_MASK 0x3f +#define BTR_BRP_SHIFT 0 +#define BTR_SJW_SHIFT 6 +#define BTR_SJW_MASK (0x3 << BTR_SJW_SHIFT) +#define BTR_TSEG1_SHIFT 8 +#define BTR_TSEG1_MASK (0xf << BTR_TSEG1_SHIFT) +#define BTR_TSEG2_SHIFT 12 +#define BTR_TSEG2_MASK (0x7 << BTR_TSEG2_SHIFT) + +/* interrupt register */ +#define INT_STS_PENDING 0x8000 + +/* brp extension register */ +#define BRP_EXT_BRPE_MASK 0x0f +#define BRP_EXT_BRPE_SHIFT 0 + +/* IFx command request */ +#define IF_COMR_BUSY BIT(15) + +/* IFx command mask */ +#define IF_COMM_WR BIT(7) +#define IF_COMM_MASK BIT(6) +#define IF_COMM_ARB BIT(5) +#define IF_COMM_CONTROL BIT(4) +#define IF_COMM_CLR_INT_PND BIT(3) +#define IF_COMM_TXRQST BIT(2) +#define IF_COMM_CLR_NEWDAT IF_COMM_TXRQST +#define IF_COMM_DATAA BIT(1) +#define IF_COMM_DATAB BIT(0) + +/* TX buffer setup */ +#define IF_COMM_TX (IF_COMM_ARB | IF_COMM_CONTROL | \ + IF_COMM_TXRQST | \ + IF_COMM_DATAA | IF_COMM_DATAB) + +/* For the low buffers we clear the interrupt bit, but keep newdat */ +#define IF_COMM_RCV_LOW (IF_COMM_MASK | IF_COMM_ARB | \ + IF_COMM_CONTROL | IF_COMM_CLR_INT_PND | \ + IF_COMM_DATAA | IF_COMM_DATAB) + +/* For the high buffers we clear the interrupt bit and newdat */ +#define IF_COMM_RCV_HIGH (IF_COMM_RCV_LOW | IF_COMM_CLR_NEWDAT) + +/* Receive setup of message objects */ +#define IF_COMM_RCV_SETUP (IF_COMM_MASK | IF_COMM_ARB | IF_COMM_CONTROL) + +/* Invalidation of message objects */ +#define IF_COMM_INVAL (IF_COMM_ARB | IF_COMM_CONTROL) + +/* IFx arbitration */ +#define IF_ARB_MSGVAL BIT(31) +#define IF_ARB_MSGXTD BIT(30) +#define IF_ARB_TRANSMIT BIT(29) + +/* IFx message control */ +#define IF_MCONT_NEWDAT BIT(15) +#define IF_MCONT_MSGLST BIT(14) +#define IF_MCONT_INTPND BIT(13) +#define IF_MCONT_UMASK BIT(12) +#define IF_MCONT_TXIE BIT(11) +#define IF_MCONT_RXIE BIT(10) +#define IF_MCONT_RMTEN BIT(9) +#define IF_MCONT_TXRQST BIT(8) +#define IF_MCONT_EOB BIT(7) +#define IF_MCONT_DLC_MASK 0xf + +#define IF_MCONT_RCV (IF_MCONT_RXIE | IF_MCONT_UMASK) +#define IF_MCONT_RCV_EOB (IF_MCONT_RCV | IF_MCONT_EOB) + +#define IF_MCONT_TX (IF_MCONT_TXIE | IF_MCONT_EOB) + +/* Use IF1 for RX and IF2 for TX */ +#define IF_RX 0 +#define IF_TX 1 + +/* minimum timeout for checking BUSY status */ +#define MIN_TIMEOUT_VALUE 6 + +/* Wait for ~1 sec for INIT bit */ +#define INIT_WAIT_MS 1000 + +/* c_can lec values */ +enum c_can_lec_type { + LEC_NO_ERROR = 0, + LEC_STUFF_ERROR, + LEC_FORM_ERROR, + LEC_ACK_ERROR, + LEC_BIT1_ERROR, + LEC_BIT0_ERROR, + LEC_CRC_ERROR, + LEC_UNUSED, + LEC_MASK = LEC_UNUSED, +}; + +/* c_can error types: + * Bus errors (BUS_OFF, ERROR_WARNING, ERROR_PASSIVE) are supported + */ +enum c_can_bus_error_types { + C_CAN_NO_ERROR = 0, + C_CAN_BUS_OFF, + C_CAN_ERROR_WARNING, + C_CAN_ERROR_PASSIVE, +}; + +static const struct can_bittiming_const c_can_bittiming_const = { + .name = KBUILD_MODNAME, + .tseg1_min = 2, /* Time segment 1 = prop_seg + phase_seg1 */ + .tseg1_max = 16, + .tseg2_min = 1, /* Time segment 2 = phase_seg2 */ + .tseg2_max = 8, + .sjw_max = 4, + .brp_min = 1, + .brp_max = 1024, /* 6-bit BRP field + 4-bit BRPE field*/ + .brp_inc = 1, +}; + +static inline void c_can_pm_runtime_get_sync(const struct c_can_priv *priv) +{ + if (priv->device) + pm_runtime_get_sync(priv->device); +} + +static inline void c_can_pm_runtime_put_sync(const struct c_can_priv *priv) +{ + if (priv->device) + pm_runtime_put_sync(priv->device); +} + +static inline void c_can_reset_ram(const struct c_can_priv *priv, bool enable) +{ + if (priv->raminit) + priv->raminit(priv, enable); +} + +static void c_can_irq_control(struct c_can_priv *priv, bool enable) +{ + u32 ctrl = priv->read_reg(priv, C_CAN_CTRL_REG) & ~CONTROL_IRQMSK; + + if (enable) + ctrl |= CONTROL_IRQMSK; + + priv->write_reg(priv, C_CAN_CTRL_REG, ctrl); +} + +static void c_can_obj_update(struct net_device *dev, int iface, u32 cmd, u32 obj) +{ + struct c_can_priv *priv = netdev_priv(dev); + int cnt, reg = C_CAN_IFACE(COMREQ_REG, iface); + + priv->write_reg32(priv, reg, (cmd << 16) | obj); + + for (cnt = MIN_TIMEOUT_VALUE; cnt; cnt--) { + if (!(priv->read_reg(priv, reg) & IF_COMR_BUSY)) + return; + udelay(1); + } + netdev_err(dev, "Updating object timed out\n"); +} + +static inline void c_can_object_get(struct net_device *dev, int iface, + u32 obj, u32 cmd) +{ + c_can_obj_update(dev, iface, cmd, obj); +} + +static inline void c_can_object_put(struct net_device *dev, int iface, + u32 obj, u32 cmd) +{ + c_can_obj_update(dev, iface, cmd | IF_COMM_WR, obj); +} + +/* Note: According to documentation clearing TXIE while MSGVAL is set + * is not allowed, but works nicely on C/DCAN. And that lowers the I/O + * load significantly. + */ +static void c_can_inval_tx_object(struct net_device *dev, int iface, int obj) +{ + struct c_can_priv *priv = netdev_priv(dev); + + priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), 0); + c_can_object_put(dev, iface, obj, IF_COMM_INVAL); +} + +static void c_can_inval_msg_object(struct net_device *dev, int iface, int obj) +{ + struct c_can_priv *priv = netdev_priv(dev); + + priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), 0); + c_can_inval_tx_object(dev, iface, obj); +} + +static void c_can_setup_tx_object(struct net_device *dev, int iface, + struct can_frame *frame, int idx) +{ + struct c_can_priv *priv = netdev_priv(dev); + u16 ctrl = IF_MCONT_TX | frame->len; + bool rtr = frame->can_id & CAN_RTR_FLAG; + u32 arb = IF_ARB_MSGVAL; + int i; + + if (frame->can_id & CAN_EFF_FLAG) { + arb |= frame->can_id & CAN_EFF_MASK; + arb |= IF_ARB_MSGXTD; + } else { + arb |= (frame->can_id & CAN_SFF_MASK) << 18; + } + + if (!rtr) + arb |= IF_ARB_TRANSMIT; + + /* If we change the DIR bit, we need to invalidate the buffer + * first, i.e. clear the MSGVAL flag in the arbiter. + */ + if (rtr != (bool)test_bit(idx, &priv->tx_dir)) { + u32 obj = idx + priv->msg_obj_tx_first; + + c_can_inval_msg_object(dev, iface, obj); + change_bit(idx, &priv->tx_dir); + } + + priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), arb); + + priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); + + if (priv->type == BOSCH_D_CAN) { + u32 data = 0, dreg = C_CAN_IFACE(DATA1_REG, iface); + + for (i = 0; i < frame->len; i += 4, dreg += 2) { + data = (u32)frame->data[i]; + data |= (u32)frame->data[i + 1] << 8; + data |= (u32)frame->data[i + 2] << 16; + data |= (u32)frame->data[i + 3] << 24; + priv->write_reg32(priv, dreg, data); + } + } else { + for (i = 0; i < frame->len; i += 2) { + priv->write_reg(priv, + C_CAN_IFACE(DATA1_REG, iface) + i / 2, + frame->data[i] | + (frame->data[i + 1] << 8)); + } + } +} + +static int c_can_handle_lost_msg_obj(struct net_device *dev, + int iface, int objno, u32 ctrl) +{ + struct net_device_stats *stats = &dev->stats; + struct c_can_priv *priv = netdev_priv(dev); + struct can_frame *frame; + struct sk_buff *skb; + + ctrl &= ~(IF_MCONT_MSGLST | IF_MCONT_INTPND | IF_MCONT_NEWDAT); + priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), ctrl); + c_can_object_put(dev, iface, objno, IF_COMM_CONTROL); + + stats->rx_errors++; + stats->rx_over_errors++; + + /* create an error msg */ + skb = alloc_can_err_skb(dev, &frame); + if (unlikely(!skb)) + return 0; + + frame->can_id |= CAN_ERR_CRTL; + frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW; + + netif_receive_skb(skb); + return 1; +} + +static int c_can_read_msg_object(struct net_device *dev, int iface, u32 ctrl) +{ + struct net_device_stats *stats = &dev->stats; + struct c_can_priv *priv = netdev_priv(dev); + struct can_frame *frame; + struct sk_buff *skb; + u32 arb, data; + + skb = alloc_can_skb(dev, &frame); + if (!skb) { + stats->rx_dropped++; + return -ENOMEM; + } + + frame->len = can_cc_dlc2len(ctrl & 0x0F); + + arb = priv->read_reg32(priv, C_CAN_IFACE(ARB1_REG, iface)); + + if (arb & IF_ARB_MSGXTD) + frame->can_id = (arb & CAN_EFF_MASK) | CAN_EFF_FLAG; + else + frame->can_id = (arb >> 18) & CAN_SFF_MASK; + + if (arb & IF_ARB_TRANSMIT) { + frame->can_id |= CAN_RTR_FLAG; + } else { + int i, dreg = C_CAN_IFACE(DATA1_REG, iface); + + if (priv->type == BOSCH_D_CAN) { + for (i = 0; i < frame->len; i += 4, dreg += 2) { + data = priv->read_reg32(priv, dreg); + frame->data[i] = data; + frame->data[i + 1] = data >> 8; + frame->data[i + 2] = data >> 16; + frame->data[i + 3] = data >> 24; + } + } else { + for (i = 0; i < frame->len; i += 2, dreg++) { + data = priv->read_reg(priv, dreg); + frame->data[i] = data; + frame->data[i + 1] = data >> 8; + } + } + } + + stats->rx_packets++; + stats->rx_bytes += frame->len; + + netif_receive_skb(skb); + return 0; +} + +static void c_can_setup_receive_object(struct net_device *dev, int iface, + u32 obj, u32 mask, u32 id, u32 mcont) +{ + struct c_can_priv *priv = netdev_priv(dev); + + mask |= BIT(29); + priv->write_reg32(priv, C_CAN_IFACE(MASK1_REG, iface), mask); + + id |= IF_ARB_MSGVAL; + priv->write_reg32(priv, C_CAN_IFACE(ARB1_REG, iface), id); + + priv->write_reg(priv, C_CAN_IFACE(MSGCTRL_REG, iface), mcont); + c_can_object_put(dev, iface, obj, IF_COMM_RCV_SETUP); +} + +static netdev_tx_t c_can_start_xmit(struct sk_buff *skb, + struct net_device *dev) +{ + struct can_frame *frame = (struct can_frame *)skb->data; + struct c_can_priv *priv = netdev_priv(dev); + u32 idx, obj; + + if (can_dropped_invalid_skb(dev, skb)) + return NETDEV_TX_OK; + /* This is not a FIFO. C/D_CAN sends out the buffers + * prioritized. The lowest buffer number wins. + */ + idx = fls(atomic_read(&priv->tx_active)); + obj = idx + priv->msg_obj_tx_first; + + /* If this is the last buffer, stop the xmit queue */ + if (idx == priv->msg_obj_tx_num - 1) + netif_stop_queue(dev); + /* Store the message in the interface so we can call + * can_put_echo_skb(). We must do this before we enable + * transmit as we might race against do_tx(). + */ + c_can_setup_tx_object(dev, IF_TX, frame, idx); + priv->dlc[idx] = frame->len; + can_put_echo_skb(skb, dev, idx, 0); + + /* Update the active bits */ + atomic_add(BIT(idx), &priv->tx_active); + /* Start transmission */ + c_can_object_put(dev, IF_TX, obj, IF_COMM_TX); + + return NETDEV_TX_OK; +} + +static int c_can_wait_for_ctrl_init(struct net_device *dev, + struct c_can_priv *priv, u32 init) +{ + int retry = 0; + + while (init != (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_INIT)) { + udelay(10); + if (retry++ > 1000) { + netdev_err(dev, "CCTRL: set CONTROL_INIT failed\n"); + return -EIO; + } + } + return 0; +} + +static int c_can_set_bittiming(struct net_device *dev) +{ + unsigned int reg_btr, reg_brpe, ctrl_save; + u8 brp, brpe, sjw, tseg1, tseg2; + u32 ten_bit_brp; + struct c_can_priv *priv = netdev_priv(dev); + const struct can_bittiming *bt = &priv->can.bittiming; + int res; + + /* c_can provides a 6-bit brp and 4-bit brpe fields */ + ten_bit_brp = bt->brp - 1; + brp = ten_bit_brp & BTR_BRP_MASK; + brpe = ten_bit_brp >> 6; + + sjw = bt->sjw - 1; + tseg1 = bt->prop_seg + bt->phase_seg1 - 1; + tseg2 = bt->phase_seg2 - 1; + reg_btr = brp | (sjw << BTR_SJW_SHIFT) | (tseg1 << BTR_TSEG1_SHIFT) | + (tseg2 << BTR_TSEG2_SHIFT); + reg_brpe = brpe & BRP_EXT_BRPE_MASK; + + netdev_info(dev, + "setting BTR=%04x BRPE=%04x\n", reg_btr, reg_brpe); + + ctrl_save = priv->read_reg(priv, C_CAN_CTRL_REG); + ctrl_save &= ~CONTROL_INIT; + priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_CCE | CONTROL_INIT); + res = c_can_wait_for_ctrl_init(dev, priv, CONTROL_INIT); + if (res) + return res; + + priv->write_reg(priv, C_CAN_BTR_REG, reg_btr); + priv->write_reg(priv, C_CAN_BRPEXT_REG, reg_brpe); + priv->write_reg(priv, C_CAN_CTRL_REG, ctrl_save); + + return c_can_wait_for_ctrl_init(dev, priv, 0); +} + +/* Configure C_CAN message objects for Tx and Rx purposes: + * C_CAN provides a total of 32 message objects that can be configured + * either for Tx or Rx purposes. Here the first 16 message objects are used as + * a reception FIFO. The end of reception FIFO is signified by the EoB bit + * being SET. The remaining 16 message objects are kept aside for Tx purposes. + * See user guide document for further details on configuring message + * objects. + */ +static void c_can_configure_msg_objects(struct net_device *dev) +{ + struct c_can_priv *priv = netdev_priv(dev); + int i; + + /* first invalidate all message objects */ + for (i = priv->msg_obj_rx_first; i <= priv->msg_obj_num; i++) + c_can_inval_msg_object(dev, IF_RX, i); + + /* setup receive message objects */ + for (i = priv->msg_obj_rx_first; i < priv->msg_obj_rx_last; i++) + c_can_setup_receive_object(dev, IF_RX, i, 0, 0, IF_MCONT_RCV); + + c_can_setup_receive_object(dev, IF_RX, priv->msg_obj_rx_last, 0, 0, + IF_MCONT_RCV_EOB); +} + +static int c_can_software_reset(struct net_device *dev) +{ + struct c_can_priv *priv = netdev_priv(dev); + int retry = 0; + + if (priv->type != BOSCH_D_CAN) + return 0; + + priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_SWR | CONTROL_INIT); + while (priv->read_reg(priv, C_CAN_CTRL_REG) & CONTROL_SWR) { + msleep(20); + if (retry++ > 100) { + netdev_err(dev, "CCTRL: software reset failed\n"); + return -EIO; + } + } + + return 0; +} + +/* Configure C_CAN chip: + * - enable/disable auto-retransmission + * - set operating mode + * - configure message objects + */ +static int c_can_chip_config(struct net_device *dev) +{ + struct c_can_priv *priv = netdev_priv(dev); + int err; + + err = c_can_software_reset(dev); + if (err) + return err; + + /* enable automatic retransmission */ + priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_ENABLE_AR); + + if ((priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) && + (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK)) { + /* loopback + silent mode : useful for hot self-test */ + priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); + priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK | TEST_SILENT); + } else if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) { + /* loopback mode : useful for self-test function */ + priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); + priv->write_reg(priv, C_CAN_TEST_REG, TEST_LBACK); + } else if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY) { + /* silent mode : bus-monitoring mode */ + priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_TEST); + priv->write_reg(priv, C_CAN_TEST_REG, TEST_SILENT); + } + + /* configure message objects */ + c_can_configure_msg_objects(dev); + + /* set a `lec` value so that we can check for updates later */ + priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); + + /* Clear all internal status */ + atomic_set(&priv->tx_active, 0); + priv->tx_dir = 0; + + /* set bittiming params */ + return c_can_set_bittiming(dev); +} + +static int c_can_start(struct net_device *dev) +{ + struct c_can_priv *priv = netdev_priv(dev); + int err; + struct pinctrl *p; + + /* basic c_can configuration */ + err = c_can_chip_config(dev); + if (err) + return err; + + /* Setup the command for new messages */ + priv->comm_rcv_high = priv->type != BOSCH_D_CAN ? + IF_COMM_RCV_LOW : IF_COMM_RCV_HIGH; + + priv->can.state = CAN_STATE_ERROR_ACTIVE; + + /* Attempt to use "active" if available else use "default" */ + p = pinctrl_get_select(priv->device, "active"); + if (!IS_ERR(p)) + pinctrl_put(p); + else + pinctrl_pm_select_default_state(priv->device); + + return 0; +} + +static void c_can_stop(struct net_device *dev) +{ + struct c_can_priv *priv = netdev_priv(dev); + + c_can_irq_control(priv, false); + + /* put ctrl to init on stop to end ongoing transmission */ + priv->write_reg(priv, C_CAN_CTRL_REG, CONTROL_INIT); + + /* deactivate pins */ + pinctrl_pm_select_sleep_state(dev->dev.parent); + priv->can.state = CAN_STATE_STOPPED; +} + +static int c_can_set_mode(struct net_device *dev, enum can_mode mode) +{ + struct c_can_priv *priv = netdev_priv(dev); + int err; + + switch (mode) { + case CAN_MODE_START: + err = c_can_start(dev); + if (err) + return err; + netif_wake_queue(dev); + c_can_irq_control(priv, true); + break; + default: + return -EOPNOTSUPP; + } + + return 0; +} + +static int __c_can_get_berr_counter(const struct net_device *dev, + struct can_berr_counter *bec) +{ + unsigned int reg_err_counter; + struct c_can_priv *priv = netdev_priv(dev); + + reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); + bec->rxerr = (reg_err_counter & ERR_CNT_REC_MASK) >> + ERR_CNT_REC_SHIFT; + bec->txerr = reg_err_counter & ERR_CNT_TEC_MASK; + + return 0; +} + +static int c_can_get_berr_counter(const struct net_device *dev, + struct can_berr_counter *bec) +{ + struct c_can_priv *priv = netdev_priv(dev); + int err; + + c_can_pm_runtime_get_sync(priv); + err = __c_can_get_berr_counter(dev, bec); + c_can_pm_runtime_put_sync(priv); + + return err; +} + +static void c_can_do_tx(struct net_device *dev) +{ + struct c_can_priv *priv = netdev_priv(dev); + struct net_device_stats *stats = &dev->stats; + u32 idx, obj, pkts = 0, bytes = 0, pend, clr; + + if (priv->msg_obj_tx_last > 32) + pend = priv->read_reg32(priv, C_CAN_INTPND3_REG); + else + pend = priv->read_reg(priv, C_CAN_INTPND2_REG); + clr = pend; + + while ((idx = ffs(pend))) { + idx--; + pend &= ~BIT(idx); + obj = idx + priv->msg_obj_tx_first; + + /* We use IF_RX interface instead of IF_TX because we + * are called from c_can_poll(), which runs inside + * NAPI. We are not trasmitting. + */ + c_can_inval_tx_object(dev, IF_RX, obj); + can_get_echo_skb(dev, idx, NULL); + bytes += priv->dlc[idx]; + pkts++; + } + + /* Clear the bits in the tx_active mask */ + atomic_sub(clr, &priv->tx_active); + + if (clr & BIT(priv->msg_obj_tx_num - 1)) + netif_wake_queue(dev); + + if (pkts) { + stats->tx_bytes += bytes; + stats->tx_packets += pkts; + can_led_event(dev, CAN_LED_EVENT_TX); + } +} + +/* If we have a gap in the pending bits, that means we either + * raced with the hardware or failed to readout all upper + * objects in the last run due to quota limit. + */ +static u32 c_can_adjust_pending(u32 pend, u32 rx_mask) +{ + u32 weight, lasts; + + if (pend == rx_mask) + return pend; + + /* If the last set bit is larger than the number of pending + * bits we have a gap. + */ + weight = hweight32(pend); + lasts = fls(pend); + + /* If the bits are linear, nothing to do */ + if (lasts == weight) + return pend; + + /* Find the first set bit after the gap. We walk backwards + * from the last set bit. + */ + for (lasts--; pend & BIT(lasts - 1); lasts--) + ; + + return pend & ~GENMASK(lasts - 1, 0); +} + +static inline void c_can_rx_object_get(struct net_device *dev, + struct c_can_priv *priv, u32 obj) +{ + c_can_object_get(dev, IF_RX, obj, priv->comm_rcv_high); +} + +static inline void c_can_rx_finalize(struct net_device *dev, + struct c_can_priv *priv, u32 obj) +{ + if (priv->type != BOSCH_D_CAN) + c_can_object_get(dev, IF_RX, obj, IF_COMM_CLR_NEWDAT); +} + +static int c_can_read_objects(struct net_device *dev, struct c_can_priv *priv, + u32 pend, int quota) +{ + u32 pkts = 0, ctrl, obj; + + while ((obj = ffs(pend)) && quota > 0) { + pend &= ~BIT(obj - 1); + + c_can_rx_object_get(dev, priv, obj); + ctrl = priv->read_reg(priv, C_CAN_IFACE(MSGCTRL_REG, IF_RX)); + + if (ctrl & IF_MCONT_MSGLST) { + int n = c_can_handle_lost_msg_obj(dev, IF_RX, obj, ctrl); + + pkts += n; + quota -= n; + continue; + } + + /* This really should not happen, but this covers some + * odd HW behaviour. Do not remove that unless you + * want to brick your machine. + */ + if (!(ctrl & IF_MCONT_NEWDAT)) + continue; + + /* read the data from the message object */ + c_can_read_msg_object(dev, IF_RX, ctrl); + + c_can_rx_finalize(dev, priv, obj); + + pkts++; + quota--; + } + + return pkts; +} + +static inline u32 c_can_get_pending(struct c_can_priv *priv) +{ + u32 pend; + + if (priv->msg_obj_rx_last > 16) + pend = priv->read_reg32(priv, C_CAN_NEWDAT1_REG); + else + pend = priv->read_reg(priv, C_CAN_NEWDAT1_REG); + + return pend; +} + +/* theory of operation: + * + * c_can core saves a received CAN message into the first free message + * object it finds free (starting with the lowest). Bits NEWDAT and + * INTPND are set for this message object indicating that a new message + * has arrived. + * + * We clear the newdat bit right away. + * + * This can result in packet reordering when the readout is slow. + */ +static int c_can_do_rx_poll(struct net_device *dev, int quota) +{ + struct c_can_priv *priv = netdev_priv(dev); + u32 pkts = 0, pend = 0, toread, n; + + while (quota > 0) { + if (!pend) { + pend = c_can_get_pending(priv); + if (!pend) + break; + /* If the pending field has a gap, handle the + * bits above the gap first. + */ + toread = c_can_adjust_pending(pend, + priv->msg_obj_rx_mask); + } else { + toread = pend; + } + /* Remove the bits from pend */ + pend &= ~toread; + /* Read the objects */ + n = c_can_read_objects(dev, priv, toread, quota); + pkts += n; + quota -= n; + } + + if (pkts) + can_led_event(dev, CAN_LED_EVENT_RX); + + return pkts; +} + +static int c_can_handle_state_change(struct net_device *dev, + enum c_can_bus_error_types error_type) +{ + unsigned int reg_err_counter; + unsigned int rx_err_passive; + struct c_can_priv *priv = netdev_priv(dev); + struct net_device_stats *stats = &dev->stats; + struct can_frame *cf; + struct sk_buff *skb; + struct can_berr_counter bec; + + switch (error_type) { + case C_CAN_NO_ERROR: + priv->can.state = CAN_STATE_ERROR_ACTIVE; + break; + case C_CAN_ERROR_WARNING: + /* error warning state */ + priv->can.can_stats.error_warning++; + priv->can.state = CAN_STATE_ERROR_WARNING; + break; + case C_CAN_ERROR_PASSIVE: + /* error passive state */ + priv->can.can_stats.error_passive++; + priv->can.state = CAN_STATE_ERROR_PASSIVE; + break; + case C_CAN_BUS_OFF: + /* bus-off state */ + priv->can.state = CAN_STATE_BUS_OFF; + priv->can.can_stats.bus_off++; + break; + default: + break; + } + + /* propagate the error condition to the CAN stack */ + skb = alloc_can_err_skb(dev, &cf); + if (unlikely(!skb)) + return 0; + + __c_can_get_berr_counter(dev, &bec); + reg_err_counter = priv->read_reg(priv, C_CAN_ERR_CNT_REG); + rx_err_passive = (reg_err_counter & ERR_CNT_RP_MASK) >> + ERR_CNT_RP_SHIFT; + + switch (error_type) { + case C_CAN_NO_ERROR: + /* error warning state */ + cf->can_id |= CAN_ERR_CRTL; + cf->data[1] = CAN_ERR_CRTL_ACTIVE; + cf->data[6] = bec.txerr; + cf->data[7] = bec.rxerr; + break; + case C_CAN_ERROR_WARNING: + /* error warning state */ + cf->can_id |= CAN_ERR_CRTL; + cf->data[1] = (bec.txerr > bec.rxerr) ? + CAN_ERR_CRTL_TX_WARNING : + CAN_ERR_CRTL_RX_WARNING; + cf->data[6] = bec.txerr; + cf->data[7] = bec.rxerr; + + break; + case C_CAN_ERROR_PASSIVE: + /* error passive state */ + cf->can_id |= CAN_ERR_CRTL; + if (rx_err_passive) + cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE; + if (bec.txerr > 127) + cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE; + + cf->data[6] = bec.txerr; + cf->data[7] = bec.rxerr; + break; + case C_CAN_BUS_OFF: + /* bus-off state */ + cf->can_id |= CAN_ERR_BUSOFF; + can_bus_off(dev); + break; + default: + break; + } + + stats->rx_packets++; + stats->rx_bytes += cf->len; + netif_receive_skb(skb); + + return 1; +} + +static int c_can_handle_bus_err(struct net_device *dev, + enum c_can_lec_type lec_type) +{ + struct c_can_priv *priv = netdev_priv(dev); + struct net_device_stats *stats = &dev->stats; + struct can_frame *cf; + struct sk_buff *skb; + + /* early exit if no lec update or no error. + * no lec update means that no CAN bus event has been detected + * since CPU wrote 0x7 value to status reg. + */ + if (lec_type == LEC_UNUSED || lec_type == LEC_NO_ERROR) + return 0; + + if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING)) + return 0; + + /* common for all type of bus errors */ + priv->can.can_stats.bus_error++; + stats->rx_errors++; + + /* propagate the error condition to the CAN stack */ + skb = alloc_can_err_skb(dev, &cf); + if (unlikely(!skb)) + return 0; + + /* check for 'last error code' which tells us the + * type of the last error to occur on the CAN bus + */ + cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR; + + switch (lec_type) { + case LEC_STUFF_ERROR: + netdev_dbg(dev, "stuff error\n"); + cf->data[2] |= CAN_ERR_PROT_STUFF; + break; + case LEC_FORM_ERROR: + netdev_dbg(dev, "form error\n"); + cf->data[2] |= CAN_ERR_PROT_FORM; + break; + case LEC_ACK_ERROR: + netdev_dbg(dev, "ack error\n"); + cf->data[3] = CAN_ERR_PROT_LOC_ACK; + break; + case LEC_BIT1_ERROR: + netdev_dbg(dev, "bit1 error\n"); + cf->data[2] |= CAN_ERR_PROT_BIT1; + break; + case LEC_BIT0_ERROR: + netdev_dbg(dev, "bit0 error\n"); + cf->data[2] |= CAN_ERR_PROT_BIT0; + break; + case LEC_CRC_ERROR: + netdev_dbg(dev, "CRC error\n"); + cf->data[3] = CAN_ERR_PROT_LOC_CRC_SEQ; + break; + default: + break; + } + + stats->rx_packets++; + stats->rx_bytes += cf->len; + netif_receive_skb(skb); + return 1; +} + +static int c_can_poll(struct napi_struct *napi, int quota) +{ + struct net_device *dev = napi->dev; + struct c_can_priv *priv = netdev_priv(dev); + u16 curr, last = priv->last_status; + int work_done = 0; + + /* Only read the status register if a status interrupt was pending */ + if (atomic_xchg(&priv->sie_pending, 0)) { + priv->last_status = priv->read_reg(priv, C_CAN_STS_REG); + curr = priv->last_status; + /* Ack status on C_CAN. D_CAN is self clearing */ + if (priv->type != BOSCH_D_CAN) + priv->write_reg(priv, C_CAN_STS_REG, LEC_UNUSED); + } else { + /* no change detected ... */ + curr = last; + } + + /* handle state changes */ + if ((curr & STATUS_EWARN) && (!(last & STATUS_EWARN))) { + netdev_dbg(dev, "entered error warning state\n"); + work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); + } + + if ((curr & STATUS_EPASS) && (!(last & STATUS_EPASS))) { + netdev_dbg(dev, "entered error passive state\n"); + work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); + } + + if ((curr & STATUS_BOFF) && (!(last & STATUS_BOFF))) { + netdev_dbg(dev, "entered bus off state\n"); + work_done += c_can_handle_state_change(dev, C_CAN_BUS_OFF); + goto end; + } + + /* handle bus recovery events */ + if ((!(curr & STATUS_BOFF)) && (last & STATUS_BOFF)) { + netdev_dbg(dev, "left bus off state\n"); + work_done += c_can_handle_state_change(dev, C_CAN_ERROR_PASSIVE); + } + + if ((!(curr & STATUS_EPASS)) && (last & STATUS_EPASS)) { + netdev_dbg(dev, "left error passive state\n"); + work_done += c_can_handle_state_change(dev, C_CAN_ERROR_WARNING); + } + + if ((!(curr & STATUS_EWARN)) && (last & STATUS_EWARN)) { + netdev_dbg(dev, "left error warning state\n"); + work_done += c_can_handle_state_change(dev, C_CAN_NO_ERROR); + } + + /* handle lec errors on the bus */ + work_done += c_can_handle_bus_err(dev, curr & LEC_MASK); + + /* Handle Tx/Rx events. We do this unconditionally */ + work_done += c_can_do_rx_poll(dev, (quota - work_done)); + c_can_do_tx(dev); + +end: + if (work_done < quota) { + napi_complete_done(napi, work_done); + /* enable all IRQs if we are not in bus off state */ + if (priv->can.state != CAN_STATE_BUS_OFF) + c_can_irq_control(priv, true); + } + + return work_done; +} + +static irqreturn_t c_can_isr(int irq, void *dev_id) +{ + struct net_device *dev = (struct net_device *)dev_id; + struct c_can_priv *priv = netdev_priv(dev); + int reg_int; + + reg_int = priv->read_reg(priv, C_CAN_INT_REG); + if (!reg_int) + return IRQ_NONE; + + /* save for later use */ + if (reg_int & INT_STS_PENDING) + atomic_set(&priv->sie_pending, 1); + + /* disable all interrupts and schedule the NAPI */ + c_can_irq_control(priv, false); + napi_schedule(&priv->napi); + + return IRQ_HANDLED; +} + +static int c_can_open(struct net_device *dev) +{ + int err; + struct c_can_priv *priv = netdev_priv(dev); + + c_can_pm_runtime_get_sync(priv); + c_can_reset_ram(priv, true); + + /* open the can device */ + err = open_candev(dev); + if (err) { + netdev_err(dev, "failed to open can device\n"); + goto exit_open_fail; + } + + /* register interrupt handler */ + err = request_irq(dev->irq, &c_can_isr, IRQF_SHARED, dev->name, + dev); + if (err < 0) { + netdev_err(dev, "failed to request interrupt\n"); + goto exit_irq_fail; + } + + /* start the c_can controller */ + err = c_can_start(dev); + if (err) + goto exit_start_fail; + + can_led_event(dev, CAN_LED_EVENT_OPEN); + + napi_enable(&priv->napi); + /* enable status change, error and module interrupts */ + c_can_irq_control(priv, true); + netif_start_queue(dev); + + return 0; + +exit_start_fail: + free_irq(dev->irq, dev); +exit_irq_fail: + close_candev(dev); +exit_open_fail: + c_can_reset_ram(priv, false); + c_can_pm_runtime_put_sync(priv); + return err; +} + +static int c_can_close(struct net_device *dev) +{ + struct c_can_priv *priv = netdev_priv(dev); + + netif_stop_queue(dev); + napi_disable(&priv->napi); + c_can_stop(dev); + free_irq(dev->irq, dev); + close_candev(dev); + + c_can_reset_ram(priv, false); + c_can_pm_runtime_put_sync(priv); + + can_led_event(dev, CAN_LED_EVENT_STOP); + + return 0; +} + +struct net_device *alloc_c_can_dev(int msg_obj_num) +{ + struct net_device *dev; + struct c_can_priv *priv; + int msg_obj_tx_num = msg_obj_num / 2; + + dev = alloc_candev(struct_size(priv, dlc, msg_obj_tx_num), + msg_obj_tx_num); + if (!dev) + return NULL; + + priv = netdev_priv(dev); + priv->msg_obj_num = msg_obj_num; + priv->msg_obj_rx_num = msg_obj_num - msg_obj_tx_num; + priv->msg_obj_rx_first = 1; + priv->msg_obj_rx_last = + priv->msg_obj_rx_first + priv->msg_obj_rx_num - 1; + priv->msg_obj_rx_mask = GENMASK(priv->msg_obj_rx_num - 1, 0); + + priv->msg_obj_tx_num = msg_obj_tx_num; + priv->msg_obj_tx_first = priv->msg_obj_rx_last + 1; + priv->msg_obj_tx_last = + priv->msg_obj_tx_first + priv->msg_obj_tx_num - 1; + + netif_napi_add(dev, &priv->napi, c_can_poll, priv->msg_obj_rx_num); + + priv->dev = dev; + priv->can.bittiming_const = &c_can_bittiming_const; + priv->can.do_set_mode = c_can_set_mode; + priv->can.do_get_berr_counter = c_can_get_berr_counter; + priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK | + CAN_CTRLMODE_LISTENONLY | + CAN_CTRLMODE_BERR_REPORTING; + + return dev; +} +EXPORT_SYMBOL_GPL(alloc_c_can_dev); + +#ifdef CONFIG_PM +int c_can_power_down(struct net_device *dev) +{ + u32 val; + unsigned long time_out; + struct c_can_priv *priv = netdev_priv(dev); + + if (!(dev->flags & IFF_UP)) + return 0; + + WARN_ON(priv->type != BOSCH_D_CAN); + + /* set PDR value so the device goes to power down mode */ + val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); + val |= CONTROL_EX_PDR; + priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); + + /* Wait for the PDA bit to get set */ + time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); + while (!(priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && + time_after(time_out, jiffies)) + cpu_relax(); + + if (time_after(jiffies, time_out)) + return -ETIMEDOUT; + + c_can_stop(dev); + + c_can_reset_ram(priv, false); + c_can_pm_runtime_put_sync(priv); + + return 0; +} +EXPORT_SYMBOL_GPL(c_can_power_down); + +int c_can_power_up(struct net_device *dev) +{ + u32 val; + unsigned long time_out; + struct c_can_priv *priv = netdev_priv(dev); + int ret; + + if (!(dev->flags & IFF_UP)) + return 0; + + WARN_ON(priv->type != BOSCH_D_CAN); + + c_can_pm_runtime_get_sync(priv); + c_can_reset_ram(priv, true); + + /* Clear PDR and INIT bits */ + val = priv->read_reg(priv, C_CAN_CTRL_EX_REG); + val &= ~CONTROL_EX_PDR; + priv->write_reg(priv, C_CAN_CTRL_EX_REG, val); + val = priv->read_reg(priv, C_CAN_CTRL_REG); + val &= ~CONTROL_INIT; + priv->write_reg(priv, C_CAN_CTRL_REG, val); + + /* Wait for the PDA bit to get clear */ + time_out = jiffies + msecs_to_jiffies(INIT_WAIT_MS); + while ((priv->read_reg(priv, C_CAN_STS_REG) & STATUS_PDA) && + time_after(time_out, jiffies)) + cpu_relax(); + + if (time_after(jiffies, time_out)) { + ret = -ETIMEDOUT; + goto err_out; + } + + ret = c_can_start(dev); + if (ret) + goto err_out; + + c_can_irq_control(priv, true); + + return 0; + +err_out: + c_can_reset_ram(priv, false); + c_can_pm_runtime_put_sync(priv); + + return ret; +} +EXPORT_SYMBOL_GPL(c_can_power_up); +#endif + +void free_c_can_dev(struct net_device *dev) +{ + struct c_can_priv *priv = netdev_priv(dev); + + netif_napi_del(&priv->napi); + free_candev(dev); +} +EXPORT_SYMBOL_GPL(free_c_can_dev); + +static const struct net_device_ops c_can_netdev_ops = { + .ndo_open = c_can_open, + .ndo_stop = c_can_close, + .ndo_start_xmit = c_can_start_xmit, + .ndo_change_mtu = can_change_mtu, +}; + +int register_c_can_dev(struct net_device *dev) +{ + int err; + + /* Deactivate pins to prevent DRA7 DCAN IP from being + * stuck in transition when module is disabled. + * Pins are activated in c_can_start() and deactivated + * in c_can_stop() + */ + pinctrl_pm_select_sleep_state(dev->dev.parent); + + dev->flags |= IFF_ECHO; /* we support local echo */ + dev->netdev_ops = &c_can_netdev_ops; + c_can_set_ethtool_ops(dev); + + err = register_candev(dev); + if (!err) + devm_can_led_init(dev); + return err; +} +EXPORT_SYMBOL_GPL(register_c_can_dev); + +void unregister_c_can_dev(struct net_device *dev) +{ + unregister_candev(dev); +} +EXPORT_SYMBOL_GPL(unregister_c_can_dev); + +MODULE_AUTHOR("Bhupesh Sharma "); +MODULE_LICENSE("GPL v2"); +MODULE_DESCRIPTION("CAN bus driver for Bosch C_CAN controller"); -- cgit From 20779943a080c5ac9b9e291b76afbac12fdec023 Mon Sep 17 00:00:00 2001 From: Torin Cooper-Bennun Date: Tue, 4 May 2021 13:51:20 +0100 Subject: can: m_can: use bits.h macros for all regmasks This updates m_can.c to exclusively use GENMASK, FIELD_GET, FIELD_PREP and FIELD_MAX for regmask ops, as is convention in the current kernel (far less error-prone, far more concise). Link: https://lore.kernel.org/r/20210504125123.500553-2-torin@maxiluxsystems.com Signed-off-by: Torin Cooper-Bennun Signed-off-by: Marc Kleine-Budde --- drivers/net/can/m_can/m_can.c | 199 ++++++++++++++++++------------------------ 1 file changed, 86 insertions(+), 113 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 3cf6de21d19c..5bed59b1083f 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -83,41 +83,30 @@ enum m_can_reg { #define MRAM_CFG_LEN 8 /* Core Release Register (CREL) */ -#define CREL_REL_SHIFT 28 -#define CREL_REL_MASK (0xF << CREL_REL_SHIFT) -#define CREL_STEP_SHIFT 24 -#define CREL_STEP_MASK (0xF << CREL_STEP_SHIFT) -#define CREL_SUBSTEP_SHIFT 20 -#define CREL_SUBSTEP_MASK (0xF << CREL_SUBSTEP_SHIFT) +#define CREL_REL_MASK GENMASK(31, 28) +#define CREL_STEP_MASK GENMASK(27, 24) +#define CREL_SUBSTEP_MASK GENMASK(23, 20) /* Data Bit Timing & Prescaler Register (DBTP) */ #define DBTP_TDC BIT(23) -#define DBTP_DBRP_SHIFT 16 -#define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT) -#define DBTP_DTSEG1_SHIFT 8 -#define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT) -#define DBTP_DTSEG2_SHIFT 4 -#define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT) -#define DBTP_DSJW_SHIFT 0 -#define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT) +#define DBTP_DBRP_MASK GENMASK(20, 16) +#define DBTP_DTSEG1_MASK GENMASK(12, 8) +#define DBTP_DTSEG2_MASK GENMASK(7, 4) +#define DBTP_DSJW_MASK GENMASK(3, 0) /* Transmitter Delay Compensation Register (TDCR) */ -#define TDCR_TDCO_SHIFT 8 -#define TDCR_TDCO_MASK (0x7F << TDCR_TDCO_SHIFT) -#define TDCR_TDCF_SHIFT 0 -#define TDCR_TDCF_MASK (0x7F << TDCR_TDCF_SHIFT) +#define TDCR_TDCO_MASK GENMASK(14, 8) +#define TDCR_TDCF_MASK GENMASK(6, 0) /* Test Register (TEST) */ #define TEST_LBCK BIT(4) /* CC Control Register(CCCR) */ -#define CCCR_CMR_MASK 0x3 -#define CCCR_CMR_SHIFT 10 +#define CCCR_CMR_MASK GENMASK(11, 10) #define CCCR_CMR_CANFD 0x1 #define CCCR_CMR_CANFD_BRS 0x2 #define CCCR_CMR_CAN 0x3 -#define CCCR_CME_MASK 0x3 -#define CCCR_CME_SHIFT 8 +#define CCCR_CME_MASK GENMASK(9, 8) #define CCCR_CME_CAN 0 #define CCCR_CME_CANFD 0x1 #define CCCR_CME_CANFD_BRS 0x2 @@ -130,7 +119,7 @@ enum m_can_reg { #define CCCR_ASM BIT(2) #define CCCR_CCE BIT(1) #define CCCR_INIT BIT(0) -#define CCCR_CANFD 0x10 +#define CCCR_CANFD BIT(4) /* for version >=3.1.x */ #define CCCR_EFBI BIT(13) #define CCCR_PXHD BIT(12) @@ -140,14 +129,10 @@ enum m_can_reg { #define CCCR_NISO BIT(15) /* Nominal Bit Timing & Prescaler Register (NBTP) */ -#define NBTP_NSJW_SHIFT 25 -#define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT) -#define NBTP_NBRP_SHIFT 16 -#define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT) -#define NBTP_NTSEG1_SHIFT 8 -#define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT) -#define NBTP_NTSEG2_SHIFT 0 -#define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT) +#define NBTP_NSJW_MASK GENMASK(31, 25) +#define NBTP_NBRP_MASK GENMASK(24, 16) +#define NBTP_NTSEG1_MASK GENMASK(15, 8) +#define NBTP_NTSEG2_MASK GENMASK(6, 0) /* Timestamp Counter Configuration Register (TSCC) */ #define TSCC_TCP_MASK GENMASK(19, 16) @@ -161,16 +146,14 @@ enum m_can_reg { /* Error Counter Register(ECR) */ #define ECR_RP BIT(15) -#define ECR_REC_SHIFT 8 -#define ECR_REC_MASK (0x7f << ECR_REC_SHIFT) -#define ECR_TEC_SHIFT 0 -#define ECR_TEC_MASK 0xff +#define ECR_REC_MASK GENMASK(14, 8) +#define ECR_TEC_MASK GENMASK(7, 0) /* Protocol Status Register(PSR) */ #define PSR_BO BIT(7) #define PSR_EW BIT(6) #define PSR_EP BIT(5) -#define PSR_LEC_MASK 0x7 +#define PSR_LEC_MASK GENMASK(2, 0) /* Interrupt Register(IR) */ #define IR_ALL_INT 0xffffffff @@ -221,6 +204,7 @@ enum m_can_reg { IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \ IR_RF1L | IR_RF0L) #define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X) + /* Interrupts for version >= 3.1.x */ #define IR_ERR_LEC_31X (IR_PED | IR_PEA) #define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \ @@ -237,58 +221,45 @@ enum m_can_reg { #define ILE_EINT0 BIT(0) /* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */ -#define RXFC_FWM_SHIFT 24 -#define RXFC_FWM_MASK (0x7f << RXFC_FWM_SHIFT) -#define RXFC_FS_SHIFT 16 -#define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT) +#define RXFC_FWM_MASK GENMASK(30, 24) +#define RXFC_FS_MASK GENMASK(22, 16) /* Rx FIFO 0/1 Status (RXF0S/RXF1S) */ #define RXFS_RFL BIT(25) #define RXFS_FF BIT(24) -#define RXFS_FPI_SHIFT 16 -#define RXFS_FPI_MASK 0x3f0000 -#define RXFS_FGI_SHIFT 8 -#define RXFS_FGI_MASK 0x3f00 -#define RXFS_FFL_MASK 0x7f +#define RXFS_FPI_MASK GENMASK(21, 16) +#define RXFS_FGI_MASK GENMASK(13, 8) +#define RXFS_FFL_MASK GENMASK(6, 0) /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ #define M_CAN_RXESC_8BYTES 0x0 #define M_CAN_RXESC_64BYTES 0x777 -/* Tx Buffer Configuration(TXBC) */ -#define TXBC_NDTB_SHIFT 16 -#define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT) -#define TXBC_TFQS_SHIFT 24 -#define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT) +/* Tx Buffer Configuration (TXBC) */ +#define TXBC_TFQS_MASK GENMASK(29, 24) +#define TXBC_NDTB_MASK GENMASK(21, 16) /* Tx FIFO/Queue Status (TXFQS) */ #define TXFQS_TFQF BIT(21) -#define TXFQS_TFQPI_SHIFT 16 -#define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT) -#define TXFQS_TFGI_SHIFT 8 -#define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT) -#define TXFQS_TFFL_SHIFT 0 -#define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT) +#define TXFQS_TFQPI_MASK GENMASK(20, 16) +#define TXFQS_TFGI_MASK GENMASK(12, 8) +#define TXFQS_TFFL_MASK GENMASK(5, 0) /* Tx Buffer Element Size Configuration(TXESC) */ #define TXESC_TBDS_8BYTES 0x0 #define TXESC_TBDS_64BYTES 0x7 /* Tx Event FIFO Configuration (TXEFC) */ -#define TXEFC_EFS_SHIFT 16 -#define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT) +#define TXEFC_EFS_MASK GENMASK(21, 16) /* Tx Event FIFO Status (TXEFS) */ #define TXEFS_TEFL BIT(25) #define TXEFS_EFF BIT(24) -#define TXEFS_EFGI_SHIFT 8 -#define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT) -#define TXEFS_EFFL_SHIFT 0 -#define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT) +#define TXEFS_EFGI_MASK GENMASK(12, 8) +#define TXEFS_EFFL_MASK GENMASK(5, 0) /* Tx Event FIFO Acknowledge (TXEFA) */ -#define TXEFA_EFAI_SHIFT 0 -#define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT) +#define TXEFA_EFAI_MASK GENMASK(4, 0) /* Message RAM Configuration (in bytes) */ #define SIDF_ELEMENT_SIZE 4 @@ -324,13 +295,12 @@ enum m_can_reg { #define TX_BUF_EFC BIT(23) #define TX_BUF_FDF BIT(21) #define TX_BUF_BRS BIT(20) -#define TX_BUF_MM_SHIFT 24 -#define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT) +#define TX_BUF_MM_MASK GENMASK(31, 24) +#define TX_BUF_DLC_MASK GENMASK(19, 16) /* Tx event FIFO Element */ /* E1 */ -#define TX_EVENT_MM_SHIFT TX_BUF_MM_SHIFT -#define TX_EVENT_MM_MASK (0xff << TX_EVENT_MM_SHIFT) +#define TX_EVENT_MM_MASK GENMASK(31, 24) #define TX_EVENT_TXTS_MASK GENMASK(15, 0) static inline u32 m_can_read(struct m_can_classdev *cdev, enum m_can_reg reg) @@ -449,8 +419,8 @@ static void m_can_clean(struct net_device *net) net->stats.tx_errors++; if (cdev->version > 30) - putidx = ((m_can_read(cdev, M_CAN_TXFQS) & - TXFQS_TFQPI_MASK) >> TXFQS_TFQPI_SHIFT); + putidx = FIELD_GET(TXFQS_TFQPI_MASK, + m_can_read(cdev, M_CAN_TXFQS)); can_free_echo_skb(cdev->net, putidx, NULL); cdev->tx_skb = NULL; @@ -490,7 +460,7 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs) int i; /* calculate the fifo get index for where to read data */ - fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT; + fgi = FIELD_GET(RXFS_FGI_MASK, rxfs); dlc = m_can_fifo_read(cdev, fgi, M_CAN_FIFO_DLC); if (dlc & RX_BUF_FDF) skb = alloc_canfd_skb(dev, &cf); @@ -663,8 +633,8 @@ static int __m_can_get_berr_counter(const struct net_device *dev, unsigned int ecr; ecr = m_can_read(cdev, M_CAN_ECR); - bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT; - bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT; + bec->rxerr = FIELD_GET(ECR_REC_MASK, ecr); + bec->txerr = FIELD_GET(ECR_TEC_MASK, ecr); return 0; } @@ -1004,24 +974,23 @@ static void m_can_echo_tx_event(struct net_device *dev) m_can_txefs = m_can_read(cdev, M_CAN_TXEFS); /* Get Tx Event fifo element count */ - txe_count = (m_can_txefs & TXEFS_EFFL_MASK) >> TXEFS_EFFL_SHIFT; + txe_count = FIELD_GET(TXEFS_EFFL_MASK, m_can_txefs); /* Get and process all sent elements */ for (i = 0; i < txe_count; i++) { u32 txe, timestamp = 0; /* retrieve get index */ - fgi = (m_can_read(cdev, M_CAN_TXEFS) & TXEFS_EFGI_MASK) >> - TXEFS_EFGI_SHIFT; + fgi = FIELD_GET(TXEFS_EFGI_MASK, m_can_read(cdev, M_CAN_TXEFS)); /* get message marker, timestamp */ txe = m_can_txe_fifo_read(cdev, fgi, 4); - msg_mark = (txe & TX_EVENT_MM_MASK) >> TX_EVENT_MM_SHIFT; + msg_mark = FIELD_GET(TX_EVENT_MM_MASK, txe); timestamp = FIELD_GET(TX_EVENT_TXTS_MASK, txe); /* ack txe element */ - m_can_write(cdev, M_CAN_TXEFA, (TXEFA_EFAI_MASK & - (fgi << TXEFA_EFAI_SHIFT))); + m_can_write(cdev, M_CAN_TXEFA, FIELD_PREP(TXEFA_EFAI_MASK, + fgi)); /* update stats */ m_can_tx_update_stats(cdev, msg_mark, timestamp); @@ -1147,8 +1116,10 @@ static int m_can_set_bittiming(struct net_device *dev) sjw = bt->sjw - 1; tseg1 = bt->prop_seg + bt->phase_seg1 - 1; tseg2 = bt->phase_seg2 - 1; - reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) | - (tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT); + reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) | + FIELD_PREP(NBTP_NSJW_MASK, sjw) | + FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) | + FIELD_PREP(NBTP_NTSEG2_MASK, tseg2); m_can_write(cdev, M_CAN_NBTP, reg_btp); if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { @@ -1185,13 +1156,13 @@ static int m_can_set_bittiming(struct net_device *dev) reg_btp |= DBTP_TDC; m_can_write(cdev, M_CAN_TDCR, - tdco << TDCR_TDCO_SHIFT); + FIELD_PREP(TDCR_TDCO_MASK, tdco)); } - reg_btp |= (brp << DBTP_DBRP_SHIFT) | - (sjw << DBTP_DSJW_SHIFT) | - (tseg1 << DBTP_DTSEG1_SHIFT) | - (tseg2 << DBTP_DTSEG2_SHIFT); + reg_btp = FIELD_PREP(NBTP_NBRP_MASK, brp) | + FIELD_PREP(NBTP_NSJW_MASK, sjw) | + FIELD_PREP(NBTP_NTSEG1_MASK, tseg1) | + FIELD_PREP(NBTP_NTSEG2_MASK, tseg2); m_can_write(cdev, M_CAN_DBTP, reg_btp); } @@ -1224,13 +1195,14 @@ static void m_can_chip_config(struct net_device *dev) if (cdev->version == 30) { /* only support one Tx Buffer currently */ - m_can_write(cdev, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) | + m_can_write(cdev, M_CAN_TXBC, FIELD_PREP(TXBC_NDTB_MASK, 1) | cdev->mcfg[MRAM_TXB].off); } else { /* TX FIFO is used for newer IP Core versions */ m_can_write(cdev, M_CAN_TXBC, - (cdev->mcfg[MRAM_TXB].num << TXBC_TFQS_SHIFT) | - (cdev->mcfg[MRAM_TXB].off)); + FIELD_PREP(TXBC_TFQS_MASK, + cdev->mcfg[MRAM_TXB].num) | + cdev->mcfg[MRAM_TXB].off); } /* support 64 bytes payload */ @@ -1238,23 +1210,24 @@ static void m_can_chip_config(struct net_device *dev) /* TX Event FIFO */ if (cdev->version == 30) { - m_can_write(cdev, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) | + m_can_write(cdev, M_CAN_TXEFC, + FIELD_PREP(TXEFC_EFS_MASK, 1) | cdev->mcfg[MRAM_TXE].off); } else { /* Full TX Event FIFO is used */ m_can_write(cdev, M_CAN_TXEFC, - ((cdev->mcfg[MRAM_TXE].num << TXEFC_EFS_SHIFT) - & TXEFC_EFS_MASK) | + FIELD_PREP(TXEFC_EFS_MASK, + cdev->mcfg[MRAM_TXE].num) | cdev->mcfg[MRAM_TXE].off); } /* rx fifo configuration, blocking mode, fifo size 1 */ m_can_write(cdev, M_CAN_RXF0C, - (cdev->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) | + FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF0].num) | cdev->mcfg[MRAM_RXF0].off); m_can_write(cdev, M_CAN_RXF1C, - (cdev->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) | + FIELD_PREP(RXFC_FS_MASK, cdev->mcfg[MRAM_RXF1].num) | cdev->mcfg[MRAM_RXF1].off); cccr = m_can_read(cdev, M_CAN_CCCR); @@ -1264,11 +1237,11 @@ static void m_can_chip_config(struct net_device *dev) /* Version 3.0.x */ cccr &= ~(CCCR_TEST | CCCR_MON | CCCR_DAR | - (CCCR_CMR_MASK << CCCR_CMR_SHIFT) | - (CCCR_CME_MASK << CCCR_CME_SHIFT)); + FIELD_PREP(CCCR_CMR_MASK, FIELD_MAX(CCCR_CMR_MASK)) | + FIELD_PREP(CCCR_CME_MASK, FIELD_MAX(CCCR_CME_MASK))); if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) - cccr |= CCCR_CME_CANFD_BRS << CCCR_CME_SHIFT; + cccr |= FIELD_PREP(CCCR_CME_MASK, CCCR_CME_CANFD_BRS); } else { /* Version 3.1.x or 3.2.x */ @@ -1372,8 +1345,8 @@ static int m_can_check_core_release(struct m_can_classdev *cdev) * Example: Version 3.2.1 => rel = 3; step = 2; substep = 1; */ crel_reg = m_can_read(cdev, M_CAN_CREL); - rel = (u8)((crel_reg & CREL_REL_MASK) >> CREL_REL_SHIFT); - step = (u8)((crel_reg & CREL_STEP_MASK) >> CREL_STEP_SHIFT); + rel = (u8)FIELD_GET(CREL_REL_MASK, crel_reg); + step = (u8)FIELD_GET(CREL_STEP_MASK, crel_reg); if (rel == 3) { /* M_CAN v3.x.y: create return value */ @@ -1593,16 +1566,16 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) if (cdev->can.ctrlmode & CAN_CTRLMODE_FD) { cccr = m_can_read(cdev, M_CAN_CCCR); - cccr &= ~(CCCR_CMR_MASK << CCCR_CMR_SHIFT); + cccr &= ~CCCR_CMR_MASK; if (can_is_canfd_skb(skb)) { if (cf->flags & CANFD_BRS) - cccr |= CCCR_CMR_CANFD_BRS << - CCCR_CMR_SHIFT; + cccr |= FIELD_PREP(CCCR_CMR_MASK, + CCCR_CMR_CANFD_BRS); else - cccr |= CCCR_CMR_CANFD << - CCCR_CMR_SHIFT; + cccr |= FIELD_PREP(CCCR_CMR_MASK, + CCCR_CMR_CANFD); } else { - cccr |= CCCR_CMR_CAN << CCCR_CMR_SHIFT; + cccr |= FIELD_PREP(CCCR_CMR_MASK, CCCR_CMR_CAN); } m_can_write(cdev, M_CAN_CCCR, cccr); } @@ -1629,8 +1602,8 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) } /* get put index for frame */ - putidx = ((m_can_read(cdev, M_CAN_TXFQS) & TXFQS_TFQPI_MASK) - >> TXFQS_TFQPI_SHIFT); + putidx = FIELD_GET(TXFQS_TFQPI_MASK, + m_can_read(cdev, M_CAN_TXFQS)); /* Write ID Field to FIFO Element */ m_can_fifo_write(cdev, putidx, M_CAN_FIFO_ID, id); @@ -1648,9 +1621,9 @@ static netdev_tx_t m_can_tx_handler(struct m_can_classdev *cdev) * sending the correct echo frame */ m_can_fifo_write(cdev, putidx, M_CAN_FIFO_DLC, - ((putidx << TX_BUF_MM_SHIFT) & - TX_BUF_MM_MASK) | - (can_fd_len2dlc(cf->len) << 16) | + FIELD_PREP(TX_BUF_MM_MASK, putidx) | + FIELD_PREP(TX_BUF_DLC_MASK, + can_fd_len2dlc(cf->len)) | fdflags | TX_BUF_EFC); for (i = 0; i < cf->len; i += 4) @@ -1810,11 +1783,11 @@ static void m_can_of_parse_mram(struct m_can_classdev *cdev, cdev->mcfg[MRAM_RXF0].off = cdev->mcfg[MRAM_XIDF].off + cdev->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE; cdev->mcfg[MRAM_RXF0].num = mram_config_vals[3] & - (RXFC_FS_MASK >> RXFC_FS_SHIFT); + FIELD_MAX(RXFC_FS_MASK); cdev->mcfg[MRAM_RXF1].off = cdev->mcfg[MRAM_RXF0].off + cdev->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE; cdev->mcfg[MRAM_RXF1].num = mram_config_vals[4] & - (RXFC_FS_MASK >> RXFC_FS_SHIFT); + FIELD_MAX(RXFC_FS_MASK); cdev->mcfg[MRAM_RXB].off = cdev->mcfg[MRAM_RXF1].off + cdev->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE; cdev->mcfg[MRAM_RXB].num = mram_config_vals[5]; @@ -1824,7 +1797,7 @@ static void m_can_of_parse_mram(struct m_can_classdev *cdev, cdev->mcfg[MRAM_TXB].off = cdev->mcfg[MRAM_TXE].off + cdev->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE; cdev->mcfg[MRAM_TXB].num = mram_config_vals[7] & - (TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT); + FIELD_MAX(TXBC_NDTB_MASK); dev_dbg(cdev->dev, "sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n", -- cgit From 38395f302f4d63b8373d2340fddd225f7b644882 Mon Sep 17 00:00:00 2001 From: Torin Cooper-Bennun Date: Tue, 4 May 2021 13:51:21 +0100 Subject: can: m_can: clean up CCCR reg defs, order by revs Ensures that the different CCCR regmasks for m_can revs 3.0.x, 3.1.x, 3.2.x and 3.3.x are clearly distinguishable. Removes incorrect CCCR_CANFD define. Adds bit fields UTSU and WMM for rev 3.3.x, for completeness. Link: https://lore.kernel.org/r/20210504125123.500553-3-torin@maxiluxsystems.com Signed-off-by: Torin Cooper-Bennun Signed-off-by: Marc Kleine-Budde --- drivers/net/can/m_can/m_can.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index 5bed59b1083f..cee542c0fdd5 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -102,14 +102,6 @@ enum m_can_reg { #define TEST_LBCK BIT(4) /* CC Control Register(CCCR) */ -#define CCCR_CMR_MASK GENMASK(11, 10) -#define CCCR_CMR_CANFD 0x1 -#define CCCR_CMR_CANFD_BRS 0x2 -#define CCCR_CMR_CAN 0x3 -#define CCCR_CME_MASK GENMASK(9, 8) -#define CCCR_CME_CAN 0 -#define CCCR_CME_CANFD 0x1 -#define CCCR_CME_CANFD_BRS 0x2 #define CCCR_TXP BIT(14) #define CCCR_TEST BIT(7) #define CCCR_DAR BIT(6) @@ -119,14 +111,25 @@ enum m_can_reg { #define CCCR_ASM BIT(2) #define CCCR_CCE BIT(1) #define CCCR_INIT BIT(0) -#define CCCR_CANFD BIT(4) +/* for version 3.0.x */ +#define CCCR_CMR_MASK GENMASK(11, 10) +#define CCCR_CMR_CANFD 0x1 +#define CCCR_CMR_CANFD_BRS 0x2 +#define CCCR_CMR_CAN 0x3 +#define CCCR_CME_MASK GENMASK(9, 8) +#define CCCR_CME_CAN 0 +#define CCCR_CME_CANFD 0x1 +#define CCCR_CME_CANFD_BRS 0x2 /* for version >=3.1.x */ #define CCCR_EFBI BIT(13) #define CCCR_PXHD BIT(12) #define CCCR_BRSE BIT(9) #define CCCR_FDOE BIT(8) -/* only for version >=3.2.x */ +/* for version >=3.2.x */ #define CCCR_NISO BIT(15) +/* for version >=3.3.x */ +#define CCCR_WMM BIT(11) +#define CCCR_UTSU BIT(10) /* Nominal Bit Timing & Prescaler Register (NBTP) */ #define NBTP_NSJW_MASK GENMASK(31, 25) -- cgit From 0f31571668914f421dab628c45eeb391aaa127ef Mon Sep 17 00:00:00 2001 From: Torin Cooper-Bennun Date: Tue, 4 May 2021 13:51:22 +0100 Subject: can: m_can: make TXESC, RXESC config more explicit Introduce masks for the three RXESC fields (RBDS, F1DS, F0DS) and the one TXESC field (TBDS). Update m_can_chip_config() to explicitly set all four fields to the 64-byte option (0x7) (and these defs are renamed to be more concise). This is an improvement in maintainability, and also makes it easier to implement more flexible configuration of the M_CAN buffers in the future. Link: https://lore.kernel.org/r/20210504125123.500553-4-torin@maxiluxsystems.com Signed-off-by: Torin Cooper-Bennun Signed-off-by: Marc Kleine-Budde --- drivers/net/can/m_can/m_can.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index cee542c0fdd5..ce7722229964 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -235,8 +235,10 @@ enum m_can_reg { #define RXFS_FFL_MASK GENMASK(6, 0) /* Rx Buffer / FIFO Element Size Configuration (RXESC) */ -#define M_CAN_RXESC_8BYTES 0x0 -#define M_CAN_RXESC_64BYTES 0x777 +#define RXESC_RBDS_MASK GENMASK(10, 8) +#define RXESC_F1DS_MASK GENMASK(6, 4) +#define RXESC_F0DS_MASK GENMASK(2, 0) +#define RXESC_64B 0x7 /* Tx Buffer Configuration (TXBC) */ #define TXBC_TFQS_MASK GENMASK(29, 24) @@ -249,8 +251,8 @@ enum m_can_reg { #define TXFQS_TFFL_MASK GENMASK(5, 0) /* Tx Buffer Element Size Configuration(TXESC) */ -#define TXESC_TBDS_8BYTES 0x0 -#define TXESC_TBDS_64BYTES 0x7 +#define TXESC_TBDS_MASK GENMASK(2, 0) +#define TXESC_TBDS_64B 0x7 /* Tx Event FIFO Configuration (TXEFC) */ #define TXEFC_EFS_MASK GENMASK(21, 16) @@ -1191,7 +1193,10 @@ static void m_can_chip_config(struct net_device *dev) m_can_config_endisable(cdev, true); /* RX Buffer/FIFO Element Size 64 bytes data field */ - m_can_write(cdev, M_CAN_RXESC, M_CAN_RXESC_64BYTES); + m_can_write(cdev, M_CAN_RXESC, + FIELD_PREP(RXESC_RBDS_MASK, RXESC_64B) | + FIELD_PREP(RXESC_F1DS_MASK, RXESC_64B) | + FIELD_PREP(RXESC_F0DS_MASK, RXESC_64B)); /* Accept Non-matching Frames Into FIFO 0 */ m_can_write(cdev, M_CAN_GFC, 0x0); @@ -1209,7 +1214,8 @@ static void m_can_chip_config(struct net_device *dev) } /* support 64 bytes payload */ - m_can_write(cdev, M_CAN_TXESC, TXESC_TBDS_64BYTES); + m_can_write(cdev, M_CAN_TXESC, + FIELD_PREP(TXESC_TBDS_MASK, TXESC_TBDS_64B)); /* TX Event FIFO */ if (cdev->version == 30) { -- cgit From 50fe7547b637b3cf51876ce9ec829e79d76e5de0 Mon Sep 17 00:00:00 2001 From: Torin Cooper-Bennun Date: Tue, 4 May 2021 13:51:23 +0100 Subject: can: m_can: fix whitespace in a few comments Fixes whitespace in comments titling sections of register masks. Link: https://lore.kernel.org/r/20210504125123.500553-5-torin@maxiluxsystems.com Signed-off-by: Torin Cooper-Bennun Signed-off-by: Marc Kleine-Budde --- drivers/net/can/m_can/m_can.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c index ce7722229964..bba2a449ac70 100644 --- a/drivers/net/can/m_can/m_can.c +++ b/drivers/net/can/m_can/m_can.c @@ -101,7 +101,7 @@ enum m_can_reg { /* Test Register (TEST) */ #define TEST_LBCK BIT(4) -/* CC Control Register(CCCR) */ +/* CC Control Register (CCCR) */ #define CCCR_TXP BIT(14) #define CCCR_TEST BIT(7) #define CCCR_DAR BIT(6) @@ -147,18 +147,18 @@ enum m_can_reg { /* Timestamp Counter Value Register (TSCV) */ #define TSCV_TSC_MASK GENMASK(15, 0) -/* Error Counter Register(ECR) */ +/* Error Counter Register (ECR) */ #define ECR_RP BIT(15) #define ECR_REC_MASK GENMASK(14, 8) #define ECR_TEC_MASK GENMASK(7, 0) -/* Protocol Status Register(PSR) */ +/* Protocol Status Register (PSR) */ #define PSR_BO BIT(7) #define PSR_EW BIT(6) #define PSR_EP BIT(5) #define PSR_LEC_MASK GENMASK(2, 0) -/* Interrupt Register(IR) */ +/* Interrupt Register (IR) */ #define IR_ALL_INT 0xffffffff /* Renamed bits for versions > 3.1.x */ @@ -250,7 +250,7 @@ enum m_can_reg { #define TXFQS_TFGI_MASK GENMASK(12, 8) #define TXFQS_TFFL_MASK GENMASK(5, 0) -/* Tx Buffer Element Size Configuration(TXESC) */ +/* Tx Buffer Element Size Configuration (TXESC) */ #define TXESC_TBDS_MASK GENMASK(2, 0) #define TXESC_TBDS_64B 0x7 -- cgit