From 200a575b68d25c5ad4d3379e6d43e9b3f6083e1b Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 17 Apr 2017 23:39:37 +0200 Subject: ARM: dts: meson: organize devices in their corresponding busses The Amlogic Meson SoCs have most of the internal peripherals organized in busses. Use them to make the dts easier to read and to avoid duplicated register (bus) offset definitions. The bus information is taken from the vendor kernel: #define IO_CBUS_PHY_BASE 0xc1100000 ///2M #define IO_AOBUS_PHY_BASE 0xc8100000 ///1M There are more internal busses (such as the abp bus which seems to contain audio, HDMI and Mali registers), but since we don't have drivers for them yet these are not added (yet). Signed-off-by: Martin Blumenstingl [khilman: minor whitespace fix] Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson.dtsi | 178 ++++++++++++++++++++++-------------------- arch/arm/boot/dts/meson6.dtsi | 2 - arch/arm/boot/dts/meson8.dtsi | 116 ++++++++++++++++++--------- 3 files changed, 170 insertions(+), 126 deletions(-) diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 8c77c87660cd..8d9c36970dfd 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -65,100 +65,108 @@ #interrupt-cells = <3>; }; - timer@c1109940 { - compatible = "amlogic,meson6-timer"; - reg = <0xc1109940 0x18>; - interrupts = <0 10 1>; - }; - soc { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges; - wdt: watchdog@c1109900 { - compatible = "amlogic,meson6-wdt"; - reg = <0xc1109900 0x8>; - interrupts = <0 0 1>; - }; - - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x18>; - interrupts = <0 90 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - uart_A: serial@c11084c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc11084c0 0x18>; - interrupts = <0 26 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - uart_B: serial@c11084dc { - compatible = "amlogic,meson-uart"; - reg = <0xc11084dc 0x18>; - interrupts = <0 75 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - uart_C: serial@c1108700 { - compatible = "amlogic,meson-uart"; - reg = <0xc1108700 0x18>; - interrupts = <0 93 1>; - clocks = <&clk81>; - status = "disabled"; - }; - - i2c_AO: i2c@c8100500 { - compatible = "amlogic,meson6-i2c"; - reg = <0xc8100500 0x20>; - interrupts = <0 92 1>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_A: i2c@c1108500 { - compatible = "amlogic,meson6-i2c"; - reg = <0xc1108500 0x20>; - interrupts = <0 21 1>; - clocks = <&clk81>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - - i2c_B: i2c@c11087c0 { - compatible = "amlogic,meson6-i2c"; - reg = <0xc11087c0 0x20>; - interrupts = <0 128 1>; - clocks = <&clk81>; + cbus: cbus@c1100000 { + compatible = "simple-bus"; + reg = <0xc1100000 0x200000>; #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; + #size-cells = <1>; + ranges = <0x0 0xc1100000 0x200000>; + + uart_A: serial@84c0 { + compatible = "amlogic,meson-uart"; + reg = <0x84c0 0x18>; + interrupts = <0 26 1>; + status = "disabled"; + }; + + uart_B: serial@84dc { + compatible = "amlogic,meson-uart"; + reg = <0x84dc 0x18>; + interrupts = <0 75 1>; + status = "disabled"; + }; + + i2c_A: i2c@8500 { + compatible = "amlogic,meson6-i2c"; + reg = <0x8500 0x20>; + interrupts = <0 21 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart_C: serial@8700 { + compatible = "amlogic,meson-uart"; + reg = <0x8700 0x18>; + interrupts = <0 93 1>; + status = "disabled"; + }; + + i2c_B: i2c@87c0 { + compatible = "amlogic,meson6-i2c"; + reg = <0x87c0 0x20>; + interrupts = <0 128 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spifc: spi@8c80 { + compatible = "amlogic,meson6-spifc"; + reg = <0x8c80 0x80>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + wdt: watchdog@9900 { + compatible = "amlogic,meson6-wdt"; + reg = <0x9900 0x8>; + interrupts = <0 0 1>; + }; + + timer@9940 { + compatible = "amlogic,meson6-timer"; + reg = <0x9940 0x18>; + interrupts = <0 10 1>; + }; }; - ir_receiver: ir-receiver@c8100480 { - compatible= "amlogic,meson6-ir"; - reg = <0xc8100480 0x20>; - interrupts = <0 15 1>; - status = "disabled"; - }; - - spifc: spi@c1108c80 { - compatible = "amlogic,meson6-spifc"; - reg = <0xc1108c80 0x80>; + aobus: aobus@c8100000 { + compatible = "simple-bus"; + reg = <0xc8100000 0x100000>; #address-cells = <1>; - #size-cells = <0>; - clocks = <&clk81>; - status = "disabled"; + #size-cells = <1>; + ranges = <0x0 0xc8100000 0x100000>; + + ir_receiver: ir-receiver@480 { + compatible= "amlogic,meson6-ir"; + reg = <0x480 0x20>; + interrupts = <0 15 1>; + status = "disabled"; + }; + + uart_AO: serial@4c0 { + compatible = "amlogic,meson-uart"; + reg = <0x4c0 0x18>; + interrupts = <0 90 1>; + status = "disabled"; + }; + + i2c_AO: i2c@500 { + compatible = "amlogic,meson6-i2c"; + reg = <0x500 0x20>; + interrupts = <0 92 1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; ethmac: ethernet@c9410000 { @@ -167,8 +175,6 @@ 0xc1108108 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - clocks = <&clk81>; - clock-names = "stmmaceth"; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/meson6.dtsi b/arch/arm/boot/dts/meson6.dtsi index 8b33be15af94..b0fc91ffd6a1 100644 --- a/arch/arm/boot/dts/meson6.dtsi +++ b/arch/arm/boot/dts/meson6.dtsi @@ -51,8 +51,6 @@ model = "Amlogic Meson6 SoC"; compatible = "amlogic,meson6"; - interrupt-parent = <&gic>; - cpus { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index ebc763eab195..5eaaf067c76a 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -50,8 +50,6 @@ model = "Amlogic Meson8 SoC"; compatible = "amlogic,meson8"; - interrupt-parent = <&gic>; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -91,18 +89,55 @@ clock-frequency = <141666666>; }; - pinctrl_cbus: pinctrl@c1109880 { +}; /* end of / */ + +&aobus { + pinctrl_aobus: pinctrl@84 { + compatible = "amlogic,meson8-aobus-pinctrl"; + reg = <0x84 0xc>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio_ao: ao-bank@14 { + reg = <0x14 0x4>, + <0x2c 0x4>, + <0x24 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 120 16>; + }; + + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; + }; + + i2c_ao_pins: i2c_mst_ao { + mux { + groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; + function = "i2c_mst_ao"; + }; + }; + }; +}; + +&cbus { + pinctrl_cbus: pinctrl@9880 { compatible = "amlogic,meson8-cbus-pinctrl"; - reg = <0xc1109880 0x10>; + reg = <0x9880 0x10>; #address-cells = <1>; #size-cells = <1>; ranges; - gpio: banks@c11080b0 { - reg = <0xc11080b0 0x28>, - <0xc11080e8 0x18>, - <0xc1108120 0x18>, - <0xc1108030 0x30>; + gpio: banks@80b0 { + reg = <0x80b0 0x28>, + <0x80e8 0x18>, + <0x8120 0x18>, + <0x8030 0x30>; reg-names = "mux", "pull", "pull-enable", "gpio"; gpio-controller; #gpio-cells = <2>; @@ -134,36 +169,41 @@ }; }; }; +}; - pinctrl_aobus: pinctrl@c8100084 { - compatible = "amlogic,meson8-aobus-pinctrl"; - reg = <0xc8100084 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; +ðmac { + clocks = <&clk81>; + clock-names = "stmmaceth"; +}; - gpio_ao: ao-bank@c1108030 { - reg = <0xc8100014 0x4>, - <0xc810002c 0x4>, - <0xc8100024 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 120 16>; - }; +&i2c_AO { + clocks = <&clk81>; +}; - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - }; - }; +&i2c_A { + clocks = <&clk81>; +}; - i2c_ao_pins: i2c_mst_ao { - mux { - groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao"; - function = "i2c_mst_ao"; - }; - }; - }; -}; /* end of / */ +&i2c_B { + clocks = <&clk81>; +}; + +&spifc { + clocks = <&clk81>; +}; + +&uart_AO { + clocks = <&clk81>; +}; + +&uart_A { + clocks = <&clk81>; +}; + +&uart_B { + clocks = <&clk81>; +}; + +&uart_C { + clocks = <&clk81>; +}; -- cgit From f44135e1f961d5bed1e737ff8e67564cdfa5eb85 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Mon, 17 Apr 2017 23:39:38 +0200 Subject: ARM: dts: meson8b: inherit meson.dtsi from meson8b.dtsi Currently only meson6.dtsi and meson8.dtsi inherit the generic meson.dtsi. However, since the Meson8b platform is basically a slightly updated version of Meson8 we can safely inherit meson.dtsi. An indicator for this are the nodes which are identical in meson.dtsi and meson8b.dtsi (L2, gic, timer, uart_AO, uart_A, uart_B, uart_C). Additionally this makes the following devices available on Meson8b which were not avaialble before (however, since all affected drivers support Meson6, Meson8 and the whole GX series there's no reason to assume that they are not working): - i2c_a and i2c_B - the IR receiver - SPFIC (SPI flash controller) - the dwmac ethernet controller Differences between Meson8 and Meson8b seem to be: - ARM Cortex-A5 core instead of Cortex-A9 on Meson8 - dwmac on Meson8b supports RGMII - small pinctrl updates Inheriting meson.dtsi makes it easier to maintain by removing duplicate definitions. Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8b.dtsi | 210 +++++++++++++++++------------------------ 1 file changed, 84 insertions(+), 126 deletions(-) diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 828aa49c678c..ef9ac974111c 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -47,11 +47,9 @@ #include #include #include -#include "skeleton.dtsi" +#include "meson.dtsi" / { - interrupt-parent = <&gic>; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -84,147 +82,107 @@ reg = <0x203>; }; }; +}; /* end of / */ - soc { - compatible = "simple-bus"; +&aobus { + pinctrl_aobus: pinctrl@84 { + compatible = "amlogic,meson8b-aobus-pinctrl"; + reg = <0x84 0xc>; #address-cells = <1>; #size-cells = <1>; ranges; - L2: l2-cache-controller@c4200000 { - compatible = "arm,pl310-cache"; - reg = <0xc4200000 0x1000>; - cache-unified; - cache-level = <2>; + gpio_ao: ao-bank@14 { + reg = <0x14 0x4>, + <0x2c 0x4>, + <0x24 0x8>; + reg-names = "mux", "pull", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_aobus 0 130 16>; }; - gic: interrupt-controller@c4301000 { - compatible = "arm,cortex-a9-gic"; - reg = <0xc4301000 0x1000>, - <0xc4300100 0x0100>; - interrupt-controller; - #interrupt-cells = <3>; - }; - - reset: reset-controller@c1104404 { - compatible = "amlogic,meson8b-reset"; - reg = <0xc1104404 0x20>; - #reset-cells = <1>; - }; - - wdt: watchdog@c1109900 { - compatible = "amlogic,meson8b-wdt"; - reg = <0xc1109900 0x8>; - interrupts = <0 0 1>; + uart_ao_a_pins: uart_ao_a { + mux { + groups = "uart_tx_ao_a", "uart_rx_ao_a"; + function = "uart_ao"; + }; }; + }; +}; - timer@c1109940 { - compatible = "amlogic,meson6-timer"; - reg = <0xc1109940 0x18>; - interrupts = <0 10 1>; - }; +&cbus { + clkc: clock-controller@4000 { + #clock-cells = <1>; + compatible = "amlogic,meson8b-clkc"; + reg = <0x8000 0x4>, <0x4000 0x460>; + }; - uart_AO: serial@c81004c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc81004c0 0x18>; - interrupts = <0 90 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; + reset: reset-controller@4404 { + compatible = "amlogic,meson8b-reset"; + reg = <0x4404 0x20>; + #reset-cells = <1>; + }; - uart_A: serial@c11084c0 { - compatible = "amlogic,meson-uart"; - reg = <0xc11084c0 0x18>; - interrupts = <0 26 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; + pwm_ab: pwm@8550 { + compatible = "amlogic,meson8b-pwm"; + reg = <0x8550 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; - uart_B: serial@c11084dc { - compatible = "amlogic,meson-uart"; - reg = <0xc11084dc 0x18>; - interrupts = <0 75 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; + pwm_cd: pwm@8650 { + compatible = "amlogic,meson8b-pwm"; + reg = <0x8650 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; - uart_C: serial@c1108700 { - compatible = "amlogic,meson-uart"; - reg = <0xc1108700 0x18>; - interrupts = <0 93 1>; - clocks = <&clkc CLKID_CLK81>; - status = "disabled"; - }; + pwm_ef: pwm@86c0 { + compatible = "amlogic,meson8b-pwm"; + reg = <0x86c0 0x10>; + #pwm-cells = <3>; + status = "disabled"; + }; - clkc: clock-controller@c1104000 { - #clock-cells = <1>; - compatible = "amlogic,meson8b-clkc"; - reg = <0xc1108000 0x4>, <0xc1104000 0x460>; - }; + wdt: watchdog@9900 { + compatible = "amlogic,meson8b-wdt"; + reg = <0x9900 0x8>; + interrupts = <0 0 1>; + }; - pwm_ab: pwm@8550 { - compatible = "amlogic,meson8b-pwm"; - reg = <0xc1108550 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; + pinctrl_cbus: pinctrl@9880 { + compatible = "amlogic,meson8b-cbus-pinctrl"; + reg = <0x9880 0x10>; + #address-cells = <1>; + #size-cells = <1>; + ranges; - pwm_cd: pwm@8650 { - compatible = "amlogic,meson8b-pwm"; - reg = <0xc1108650 0x10>; - #pwm-cells = <3>; - status = "disabled"; + gpio: banks@80b0 { + reg = <0x80b0 0x28>, + <0x80e8 0x18>, + <0x8120 0x18>, + <0x8030 0x38>; + reg-names = "mux", "pull", "pull-enable", "gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl_cbus 0 0 130>; }; + }; +}; - pwm_ef: pwm@86c0 { - compatible = "amlogic,meson8b-pwm"; - reg = <0xc11086c0 0x10>; - #pwm-cells = <3>; - status = "disabled"; - }; +&uart_AO { + clocks = <&clkc CLKID_CLK81>; +}; - pinctrl_cbus: pinctrl@c1109880 { - compatible = "amlogic,meson8b-cbus-pinctrl"; - reg = <0xc1109880 0x10>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio: banks@c11080b0 { - reg = <0xc11080b0 0x28>, - <0xc11080e8 0x18>, - <0xc1108120 0x18>, - <0xc1108030 0x38>; - reg-names = "mux", "pull", "pull-enable", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_cbus 0 0 130>; - }; - }; +&uart_A { + clocks = <&clkc CLKID_CLK81>; +}; - pinctrl_aobus: pinctrl@c8100084 { - compatible = "amlogic,meson8b-aobus-pinctrl"; - reg = <0xc8100084 0xc>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - gpio_ao: ao-bank@c1108030 { - reg = <0xc8100014 0x4>, - <0xc810002c 0x4>, - <0xc8100024 0x8>; - reg-names = "mux", "pull", "gpio"; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl_aobus 0 130 16>; - }; +&uart_B { + clocks = <&clkc CLKID_CLK81>; +}; - uart_ao_a_pins: uart_ao_a { - mux { - groups = "uart_tx_ao_a", "uart_rx_ao_a"; - function = "uart_ao"; - }; - }; - }; - }; -}; /* end of / */ +&uart_C { + clocks = <&clkc CLKID_CLK81>; +}; -- cgit From bbe5b23dfdd346e782f8c56ab01bb3f5eaddd438 Mon Sep 17 00:00:00 2001 From: Carlo Caione Date: Mon, 17 Apr 2017 23:42:44 +0200 Subject: ARM: dts: meson: Extend L2 cache controller node for Meson8 and Meson8b This patch extends the L2 cache controller node for the Amlogic Meson8 and Meson8b SoCs with some missing parameters. These are taken from the Amlogic GPL kernel source. Signed-off-by: Carlo Caione [apply the change to Meson8 and Meson8b and updated description] Signed-off-by: Martin Blumenstingl Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 6 ++++++ arch/arm/boot/dts/meson8b.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 5eaaf067c76a..6993077331c7 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -188,6 +188,12 @@ clocks = <&clk81>; }; +&L2 { + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,filter-ranges = <0x100000 0xc0000000>; +}; + &spifc { clocks = <&clk81>; }; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index ef9ac974111c..d9f116a418b2 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -171,6 +171,12 @@ }; }; +&L2 { + arm,data-latency = <3 3 3>; + arm,tag-latency = <2 2 2>; + arm,filter-ranges = <0x100000 0xc0000000>; +}; + &uart_AO { clocks = <&clkc CLKID_CLK81>; }; -- cgit From 2c323c43a3d619d67bffa57dc7480cfae4c53300 Mon Sep 17 00:00:00 2001 From: Martin Blumenstingl Date: Sun, 4 Jun 2017 20:33:41 +0200 Subject: ARM: dts: meson8: add and use the real clock controller This removes the dummy clk81 gate and replaces it with the actual clock controller's CLKID_CLK81. This will also allow us to pass the real clock IDs to all devices where the clock is controlled by clkc in the future. Signed-off-by: Martin Blumenstingl Acked-by: Jerome Brunet Signed-off-by: Kevin Hilman --- arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 6993077331c7..9b0b3ddbb17e 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -43,6 +43,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include #include /include/ "meson.dtsi" @@ -82,13 +83,6 @@ reg = <0x203>; }; }; - - clk81: clk@0 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <141666666>; - }; - }; /* end of / */ &aobus { @@ -126,6 +120,12 @@ }; &cbus { + clkc: clock-controller@4000 { + #clock-cells = <1>; + compatible = "amlogic,meson8-clkc"; + reg = <0x8000 0x4>, <0x4000 0x460>; + }; + pinctrl_cbus: pinctrl@9880 { compatible = "amlogic,meson8-cbus-pinctrl"; reg = <0x9880 0x10>; @@ -172,20 +172,20 @@ }; ðmac { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; clock-names = "stmmaceth"; }; &i2c_AO { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &i2c_A { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &i2c_B { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &L2 { @@ -195,21 +195,21 @@ }; &spifc { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &uart_AO { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &uart_A { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &uart_B { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; &uart_C { - clocks = <&clk81>; + clocks = <&clkc CLKID_CLK81>; }; -- cgit