From b230e1b21c6217647d8452eab4c43420ef02b58d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 5 Jul 2024 09:59:10 +0200 Subject: ARM: dts: stm32: Keep MDIO bus in AF across suspend DH STM32MP13xx DHCOR DHSBC board The RTL8211F PHY gets confused when the MDIO bus lines get switched to ANALOG during suspend/resume cycle. Keep the MDIO and MDC lines in AF during suspend/resume to avoid confusing the PHY. The PHY can be brought out of the confused state by restarting auto-negotiation too, but that seems like an odd workaround and shouldn't be in the PHY driver. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index c9f588a65094..8db1ec4a3b26 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -94,14 +94,20 @@ /omit-if-no-ref/ eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { pins1 { + pinmux = , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { pinmux = , /* ETH_RGMII_TXD0 */ , /* ETH_RGMII_TXD1 */ , /* ETH_RGMII_TXD2 */ , /* ETH_RGMII_TXD3 */ , /* ETH_RGMII_TX_CTL */ , /* ETH_RGMII_GTX_CLK */ - , /* ETH_MDIO */ - , /* ETH_MDC */ , /* ETH_RGMII_RXD0 */ , /* ETH_RGMII_RXD1 */ , /* ETH_RGMII_RXD1 */ @@ -178,14 +184,20 @@ /omit-if-no-ref/ eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { pins1 { + pinmux = , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { pinmux = , /* ETH_RGMII_TXD0 */ , /* ETH_RGMII_TXD1 */ , /* ETH_RGMII_TXD2 */ , /* ETH_RGMII_TXD3 */ , /* ETH_RGMII_TX_CTL */ , /* ETH_RGMII_GTX_CLK */ - , /* ETH_MDIO */ - , /* ETH_MDC */ , /* ETH_RGMII_RXD0 */ , /* ETH_RGMII_RXD1 */ , /* ETH_RGMII_RXD2 */ -- cgit From 44791c0fe327d3e43447094b0abca3bd768b16e4 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 5 Jul 2024 10:01:02 +0200 Subject: ARM: dts: stm32: Disable PHY clock output on DH STM32MP13xx DHCOR DHSBC board The RTL8211F PHY clock output is not used on DH STM32MP13xx DHCOR DHSBC board, disable it to improve EMI characteristics. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index bacb70b4256b..201fb6a291cc 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -94,6 +94,7 @@ interrupt-parent = <&gpiog>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; reg = <1>; + realtek,clkout-disable; reset-assert-us = <15000>; reset-deassert-us = <55000>; reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; @@ -121,6 +122,7 @@ interrupt-parent = <&gpiog>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; reg = <1>; + realtek,clkout-disable; reset-assert-us = <15000>; reset-deassert-us = <55000>; reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; -- cgit From 5d1ff2dde48fd983b4f4511e7fe72e2a1045717d Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 29 Jun 2024 19:10:30 +0200 Subject: ARM: dts: stm32: Add ethernet MAC nvmem cells to DH STM32MP13xx DHCOR DHSBC board Describe ethernet MAC address nvmem cells in DH STM32MP13xx DHCOR DHSBC board DT. The MAC address can be fused in BSEC OTP fuses and used to set up MAC address for both ethernet MACs on this board. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 201fb6a291cc..425deb5641c1 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -75,6 +75,8 @@ }; ðernet1 { + nvmem-cell-names = "mac-address"; + nvmem-cells = <ðernet_mac1_address>; phy-handle = <ðphy1>; phy-mode = "rgmii-id"; pinctrl-0 = <ð1_rgmii_pins_a>; @@ -103,6 +105,8 @@ }; ðernet2 { + nvmem-cell-names = "mac-address"; + nvmem-cells = <ðernet_mac2_address>; phy-handle = <ðphy2>; phy-mode = "rgmii-id"; pinctrl-0 = <ð2_rgmii_pins_a>; -- cgit From 4a12b200a66c0fce782bc8cf46d0f33fc1245f03 Mon Sep 17 00:00:00 2001 From: Sean Nyekjaer Date: Tue, 9 Jul 2024 14:16:18 +0200 Subject: ARM: dts: stm32: Add missing gpio options for sdmmc2_d47_pins_d This enables DDR50 mode for the eMMC on Octavo OSD32MP1-RED board. Fixes: be78ab4f632c ("ARM: dts: stm32: add initial support for stm32mp157-odyssey board") Signed-off-by: Sean Nyekjaer Reviewed-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi index ae83e7b10232..70e132dc6147 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -2229,6 +2229,9 @@ , /* SDMMC2_D5 */ , /* SDMMC2_D6 */ ; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; }; }; -- cgit From 9d4de04f615b5eac544584039548f292c3e19833 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 5 Jul 2024 23:53:50 +0200 Subject: ARM: dts: stm32: Describe PHY LEDs in DH STM32MP13xx DHCOR DHSBC board DT The RTL8211 PHY on DH STM32MP13xx DHCOR DHSBC carrier board supports HW LED offload, the LEDs can be configured on link at 10/100/1000 line rate and on RXTX activity. There are two PHYs on this board, each only has two out of three LEDs connected to the PHY LED outputs. Describe this hardware configuration in DT. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts index 425deb5641c1..853dc21449d9 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -100,6 +100,25 @@ reset-assert-us = <15000>; reset-deassert-us = <55000>; reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_WAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_WAN; + linux,default-trigger = "netdev"; + }; + }; }; }; }; @@ -130,6 +149,25 @@ reset-assert-us = <15000>; reset-deassert-us = <55000>; reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + linux,default-trigger = "netdev"; + }; + }; }; }; }; -- cgit From 7de129f5389be1038b7748bf6b326ee37f3df933 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Mon, 12 Aug 2024 12:41:42 +0200 Subject: ARM: dts: stm32: stm32mp151a-prtt1l: Fix QSPI configuration Rename 'pins1' to 'pins' in the qspi_bk1_pins_a node to correct the subnode name. The incorrect name caused the configuration to be applied to the wrong subnode, resulting in QSPI not working properly. Some additional changes was made: - To avoid this kind of regression, all references to pin configuration nodes are now referenced directly using the format &{label/subnode}. - /delete-property/ bias-disable; was added everywhere where bias-pull-up is used - redundant properties like driver-push-pull are removed Signed-off-by: Oleksij Rempel Reviewed-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts | 12 +-- arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts | 108 ++++++++++------------- arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi | 126 +++++++++++++-------------- arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts | 16 ++-- 4 files changed, 116 insertions(+), 146 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts index 75874eafde11..8e1dd84e0c0a 100644 --- a/arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts +++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1a.dts @@ -28,16 +28,12 @@ }; }; -&pwm5_pins_a { - pins { - pinmux = ; /* TIM5_CH1 */ - }; +&{pwm5_pins_a/pins} { + pinmux = ; /* TIM5_CH1 */ }; -&pwm5_sleep_pins_a { - pins { - pinmux = ; /* TIM5_CH1 */ - }; +&{pwm5_sleep_pins_a/pins} { + pinmux = ; /* TIM5_CH1 */ }; &timers5 { diff --git a/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts index c90d815f906b..3b33b7093b68 100644 --- a/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts +++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1c.dts @@ -168,52 +168,42 @@ status = "okay"; }; -&sdmmc2_b4_od_pins_a { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - ; /* SDMMC2_D3 */ - }; +&{sdmmc2_b4_od_pins_a/pins1} { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ }; -&sdmmc2_b4_pins_a { - pins1 { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - ; /* SDMMC2_CMD */ - }; +&{sdmmc2_b4_pins_a/pins1} { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ }; -&sdmmc2_b4_sleep_pins_a { - pins { - pinmux = , /* SDMMC2_D0 */ - , /* SDMMC2_D1 */ - , /* SDMMC2_D2 */ - , /* SDMMC2_D3 */ - , /* SDMMC2_CK */ - ; /* SDMMC2_CMD */ - }; +&{sdmmc2_b4_sleep_pins_a/pins} { + pinmux = , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ }; -&sdmmc2_d47_pins_a { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; +&{sdmmc2_d47_pins_a/pins} { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ }; -&sdmmc2_d47_sleep_pins_a { - pins { - pinmux = , /* SDMMC2_D4 */ - , /* SDMMC2_D5 */ - , /* SDMMC2_D6 */ - ; /* SDMMC2_D7 */ - }; +&{sdmmc2_d47_sleep_pins_a/pins} { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ }; &sdmmc3 { @@ -238,34 +228,28 @@ }; }; -&sdmmc3_b4_od_pins_b { - pins1 { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - ; /* SDMMC3_D3 */ - }; +&{sdmmc3_b4_od_pins_b/pins1} { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ }; -&sdmmc3_b4_pins_b { - pins1 { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - , /* SDMMC3_D3 */ - ; /* SDMMC3_CMD */ - }; +&{sdmmc3_b4_pins_b/pins1} { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ }; -&sdmmc3_b4_sleep_pins_b { - pins { - pinmux = , /* SDMMC3_D0 */ - , /* SDMMC3_D1 */ - , /* SDMMC3_D2 */ - , /* SDMMC3_D3 */ - , /* SDMMC3_CK */ - ; /* SDMMC3_CMD */ - }; +&{sdmmc3_b4_sleep_pins_b/pins} { + pinmux = , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ }; &spi1 { diff --git a/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi index 3938d357e198..98a31c2b5d45 100644 --- a/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi +++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1l.dtsi @@ -69,30 +69,27 @@ status = "okay"; }; -ðernet0_rmii_pins_a { - pins1 { - pinmux = , /* ETH1_RMII_TXD0 */ - , /* ETH1_RMII_TXD1 */ - ; /* ETH1_RMII_TX_EN */ - }; - pins2 { - pinmux = , /* ETH1_RMII_RXD0 */ - , /* ETH1_RMII_RXD1 */ - , /* ETH1_RMII_REF_CLK input */ - ; /* ETH1_RMII_CRS_DV */ - }; +&{ethernet0_rmii_pins_a/pins1} { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + ; /* ETH1_RMII_TX_EN */ }; -ðernet0_rmii_sleep_pins_a { - pins1 { - pinmux = , /* ETH1_RMII_TXD0 */ - , /* ETH1_RMII_TXD1 */ - , /* ETH1_RMII_TX_EN */ - , /* ETH1_RMII_RXD0 */ - , /* ETH1_RMII_RXD1 */ - , /* ETH1_RMII_REF_CLK */ - ; /* ETH1_RMII_CRS_DV */ - }; +&{ethernet0_rmii_pins_a/pins2} { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK input */ + ; /* ETH1_RMII_CRS_DV */ +}; + +&{ethernet0_rmii_sleep_pins_a/pins1} { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ }; &iwdg2 { @@ -122,12 +119,11 @@ }; }; -&qspi_bk1_pins_a { - pins1 { - bias-pull-up; - drive-push-pull; - slew-rate = <1>; - }; +&{qspi_bk1_pins_a/pins} { + /delete-property/ bias-disable; + bias-pull-up; + drive-push-pull; + slew-rate = <1>; }; &rng1 { @@ -147,22 +143,24 @@ status = "okay"; }; -&sdmmc1_b4_od_pins_a { - pins1 { - bias-pull-up; - }; - pins2 { - bias-pull-up; - }; +&{sdmmc1_b4_od_pins_a/pins1} { + /delete-property/ bias-disable; + bias-pull-up; }; -&sdmmc1_b4_pins_a { - pins1 { - bias-pull-up; - }; - pins2 { - bias-pull-up; - }; +&{sdmmc1_b4_od_pins_a/pins2} { + /delete-property/ bias-disable; + bias-pull-up; +}; + +&{sdmmc1_b4_pins_a/pins1} { + /delete-property/ bias-disable; + bias-pull-up; +}; + +&{sdmmc1_b4_pins_a/pins2} { + /delete-property/ bias-disable; + bias-pull-up; }; &uart4 { @@ -175,34 +173,30 @@ status = "okay"; }; -&uart4_idle_pins_a { - pins1 { - pinmux = ; /* UART4_TX */ - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-pull-up; - }; +&{uart4_idle_pins_a/pins1} { + pinmux = ; /* UART4_TX */ }; -&uart4_pins_a { - pins1 { - pinmux = ; /* UART4_TX */ - bias-disable; - drive-push-pull; - slew-rate = <0>; - }; - pins2 { - pinmux = ; /* UART4_RX */ - bias-pull-up; - }; +&{uart4_idle_pins_a/pins2} { + pinmux = ; /* UART4_RX */ + /delete-property/ bias-disable; + bias-pull-up; }; -&uart4_sleep_pins_a { - pins { - pinmux = , /* UART4_TX */ - ; /* UART4_RX */ - }; +&{uart4_pins_a/pins1} { + pinmux = ; /* UART4_TX */ + slew-rate = <0>; +}; + +&{uart4_pins_a/pins2} { + pinmux = ; /* UART4_RX */ + /delete-property/ bias-disable; + bias-pull-up; +}; + +&{uart4_sleep_pins_a/pins} { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ }; &usbh_ehci { diff --git a/arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts b/arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts index ad25929e64e6..b6be61b159e7 100644 --- a/arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts +++ b/arch/arm/boot/dts/st/stm32mp151a-prtt1s.dts @@ -36,18 +36,14 @@ }; }; -&i2c1_pins_a { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - }; +&{i2c1_pins_a/pins} { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ }; -&i2c1_sleep_pins_a { - pins { - pinmux = , /* I2C1_SCL */ - ; /* I2C1_SDA */ - }; +&{i2c1_sleep_pins_a/pins} { + pinmux = , /* I2C1_SCL */ + ; /* I2C1_SDA */ }; &mdio0 { -- cgit From eb2247f1420a13976ea819ad701d9e7829ba6b78 Mon Sep 17 00:00:00 2001 From: Oleksij Rempel Date: Fri, 9 Aug 2024 11:16:14 +0200 Subject: dt-bindings: arm: stm32: Add compatible strings for Protonic boards Add compatible strings for Protonic MECIO1r0 and MECT1S boards to the STM32MP151-based boards section and Protonic MECIO1r1 board to the STM32MP153-based boards section. MECIO1 is an I/O and motor control board used in blood sample analysis machines. MECT1S is a 1000Base-T1 switch for internal machine networks of blood sample analysis machines. Signed-off-by: Oleksij Rempel Reviewed-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 58099949e8f3..703d4b574398 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -54,6 +54,8 @@ properties: - description: ST STM32MP151 based Boards items: - enum: + - prt,mecio1r0 # Protonic MECIO1r0 + - prt,mect1s # Protonic MECT1S - prt,prtt1a # Protonic PRTT1A - prt,prtt1c # Protonic PRTT1C - prt,prtt1s # Protonic PRTT1S @@ -71,6 +73,12 @@ properties: - const: dh,stm32mp151a-dhcor-som - const: st,stm32mp151 + - description: ST STM32MP153 based Boards + items: + - enum: + - prt,mecio1r1 # Protonic MECIO1r1 + - const: st,stm32mp153 + - description: DH STM32MP153 DHCOM SoM based Boards items: - const: dh,stm32mp153c-dhcom-drc02 -- cgit From 8267753c891cfde08d4c6d6fa0ae2771cdb25b7d Mon Sep 17 00:00:00 2001 From: David Jander Date: Fri, 9 Aug 2024 11:16:15 +0200 Subject: ARM: dts: stm32: Add MECIO1 and MECT1S board variants Introduce device tree support for the MECIO1 and MECT1S board variants. MECIO1 is an I/O and motor control board used in blood sample analysis machines. MECT1S is a 1000Base-T1 switch for internal machine networks of blood sample analysis machines. Signed-off-by: David Jander Signed-off-by: Oleksij Rempel Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/Makefile | 3 + arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts | 48 +++ arch/arm/boot/dts/st/stm32mp151c-mect1s.dts | 290 ++++++++++++++ arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts | 48 +++ arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi | 527 +++++++++++++++++++++++++ 5 files changed, 916 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts create mode 100644 arch/arm/boot/dts/st/stm32mp151c-mect1s.dts create mode 100644 arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts create mode 100644 arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 015903d09323..eab3a9bd435f 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -35,8 +35,11 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151a-prtt1c.dtb \ stm32mp151a-prtt1s.dtb \ stm32mp151a-dhcor-testbench.dtb \ + stm32mp151c-mecio1r0.dtb \ + stm32mp151c-mect1s.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp153c-dhcor-drc-compact.dtb \ + stm32mp153c-mecio1r1.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ diff --git a/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts new file mode 100644 index 000000000000..a5ea1431c399 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include "stm32mp15x-mecio1-io.dtsi" +#include +#include +#include + +/ { + model = "Protonic MECIO1r0"; + compatible = "prt,mecio1r0", "st,stm32mp151"; + + led { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + gpios = <&gpioa 14 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&clk_hse { + clock-frequency = <25000000>; +}; + +ðernet0 { + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL3_Q>; + assigned-clock-parents = <&rcc PLL3_Q>; + assigned-clock-rates = <125000000>; /* Clock PLL3 to 625Mhz in tf-a. */ + st,eth-clk-sel; +}; diff --git a/arch/arm/boot/dts/st/stm32mp151c-mect1s.dts b/arch/arm/boot/dts/st/stm32mp151c-mect1s.dts new file mode 100644 index 000000000000..a1b8c3646e98 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151c-mect1s.dts @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp151.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Protonic MECT1S"; + compatible = "prt,mect1s", "st,stm32mp151"; + + chosen { + stdout-path = "serial0:1500000n8"; + }; + + aliases { + serial0 = &uart4; + ethernet0 = ðernet0; + ethernet1 = ðernet1; + ethernet2 = ðernet2; + ethernet3 = ðernet3; + ethernet4 = ðernet4; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + v5v: regulator-v5v { + compatible = "regulator-fixed"; + regulator-name = "v5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + led { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&clk_hse { + clock-frequency = <24000000>; +}; + +&clk_lse { + status = "disabled"; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + st,eth-clk-sel; + + fixed-link { + speed = <100>; + full-duplex; + }; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; +}; + +&{ethernet0_rmii_pins_a/pins1} { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ +}; + +&{ethernet0_rmii_pins_a/pins2} { + pinmux = , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK input */ + ; /* ETH1_RMII_CRS_DV */ +}; + +&{ethernet0_rmii_sleep_pins_a/pins1} { + pinmux = , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ +}; + +&mdio0 { + /* All this DP83TG720R PHYs can't be probed before switch@0 is + * probed so we need to use compatible with PHYid + */ + /* TI DP83TG720R */ + t1_phy0: ethernet-phy@8 { + compatible = "ethernet-phy-id2000.a284"; + reg = <8>; + interrupts-extended = <&gpioi 5 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioh 13 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TG720R */ + t1_phy1: ethernet-phy@c { + compatible = "ethernet-phy-id2000.a284"; + reg = <12>; + interrupts-extended = <&gpioj 0 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioh 14 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TG720R */ + t1_phy2: ethernet-phy@4 { + compatible = "ethernet-phy-id2000.a284"; + reg = <4>; + interrupts-extended = <&gpioi 7 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + + /* TI DP83TG720R */ + t1_phy3: ethernet-phy@d { + compatible = "ethernet-phy-id2000.a284"; + reg = <13>; + interrupts-extended = <&gpioi 15 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpioi 13 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <1000>; + }; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&{qspi_bk1_pins_a/pins} { + /delete-property/ bias-disable; + bias-pull-up; + drive-push-pull; + slew-rate = <1>; +}; + +&spi2 { + pinctrl-0 = <&spi2_pins_b>; + pinctrl-names = "default"; + cs-gpios = <&gpioj 3 GPIO_ACTIVE_LOW>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + switch@0 { + compatible = "nxp,sja1105q"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-rx-delay-us = <1>; + spi-tx-delay-us = <1>; + spi-cpha; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet1: port@0 { + reg = <0>; + label = "t10"; + phy-mode = "rgmii-id"; + phy-handle = <&t1_phy0>; + }; + + ethernet2: port@1 { + reg = <1>; + label = "t11"; + phy-mode = "rgmii-id"; + phy-handle = <&t1_phy1>; + }; + + ethernet3: port@2 { + reg = <2>; + label = "t12"; + phy-mode = "rgmii-id"; + phy-handle = <&t1_phy2>; + }; + + ethernet4: port@3 { + reg = <3>; + label = "t13"; + phy-mode = "rgmii-id"; + phy-handle = <&t1_phy3>; + }; + + port@4 { + reg = <4>; + label = "cpu"; + ethernet = <ðernet0>; + phy-mode = "rmii"; + + /* RGMII mode is not working properly, using RMII instead. */ + fixed-link { + speed = <100>; + full-duplex; + }; + }; + }; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + vbus-supply = <&v5v>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&v3v3>; +}; + +&usbphyc_port1 { + phy-supply = <&v3v3>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts new file mode 100644 index 000000000000..16b814c19350 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ +/dts-v1/; + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include "stm32mp15x-mecio1-io.dtsi" +#include +#include +#include + +/ { + model = "Protonic MECIO1r1"; + compatible = "prt,mecio1r1", "st,stm32mp153"; + + led { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_DEBUG; + gpios = <&gpioa 13 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = ; + function = LED_FUNCTION_DEBUG; + gpios = <&gpioa 14 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&clk_hse { + clock-frequency = <24000000>; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_b>; + pinctrl-1 = <&m_can1_sleep_pins_b>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi new file mode 100644 index 000000000000..915ba2526f45 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) Protonic Holland + * Author: David Jander + */ + +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxaa-pinctrl.dtsi" +#include +#include + +/ { + chosen { + stdout-path = "serial0:1500000n8"; + }; + + aliases { + serial0 = &uart4; + ethernet0 = ðernet0; + spi1 = &spi1; + spi2 = &spi2; + spi3 = &spi3; + spi4 = &spi4; + spi5 = &spi5; + spi6 = &spi6; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xC0000000 0x10000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + }; + + v3v3: regulator-v3v3 { + compatible = "regulator-fixed"; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + v5v: regulator-v5v { + compatible = "regulator-fixed"; + regulator-name = "v5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&adc { + /* ANA0, ANA1 are dedicated pins and don't need pinctrl: only in6. */ + pinctrl-0 = <&adc12_pins_mecsbc>; + pinctrl-names = "default"; + vdd-supply = <&v3v3>; + vdda-supply = <&v3v3>; + vref-supply = <&v3v3>; + status = "okay"; +}; + +&adc1 { + status = "okay"; + + channel@0 { + reg = <0>; + /* 16.5 ck_cycles sampling time */ + st,min-sample-time-ns = <5000>; + label = "p24v_stp"; + }; + + channel@1 { + reg = <1>; + st,min-sample-time-ns = <5000>; + label = "p24v_hpdcm"; + }; + + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + label = "ain0"; + }; + + channel@3 { + reg = <3>; + st,min-sample-time-ns = <5000>; + label = "hpdcm1_i2"; + }; + + channel@5 { + reg = <5>; + st,min-sample-time-ns = <5000>; + label = "hpout1_i"; + }; + + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + label = "ain1"; + }; + + channel@9 { + reg = <9>; + st,min-sample-time-ns = <5000>; + label = "hpout0_i"; + }; + + channel@10 { + reg = <10>; + st,min-sample-time-ns = <5000>; + label = "phint0_ain"; + }; + + channel@13 { + reg = <13>; + st,min-sample-time-ns = <5000>; + label = "phint1_ain"; + }; + + channel@15 { + reg = <15>; + st,min-sample-time-ns = <5000>; + label = "hpdcm0_i1"; + }; + + channel@16 { + reg = <16>; + st,min-sample-time-ns = <5000>; + label = "lsin"; + }; + + channel@18 { + reg = <18>; + st,min-sample-time-ns = <5000>; + label = "hpdcm0_i2"; + }; + + channel@19 { + reg = <19>; + st,min-sample-time-ns = <5000>; + label = "hpdcm1_i1"; + }; +}; + +&adc2 { + status = "okay"; + + channel@2 { + reg = <2>; + /* 16.5 ck_cycles sampling time */ + st,min-sample-time-ns = <5000>; + label = "ain2"; + }; + + channel@6 { + reg = <6>; + st,min-sample-time-ns = <5000>; + label = "ain3"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_x>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_x>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + st,eth-clk-sel; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@8 { + reg = <8>; + interrupts-extended = <&gpiog 7 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpiog 10 GPIO_ACTIVE_LOW>; + reset-assert-us = <10>; + reset-deassert-us = <35>; + }; + }; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "STP_RESETN", "STP_ENABLEN", "HPOUT0", "HPOUT0_ALERTN"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog_d_mecsbc>; +}; + +&gpioe { + gpio-line-names = "HPOUT0_RESETN", "HPOUT1", "HPOUT1_ALERTN", "", + "", "", "HPOUT1_RESETN", + "LPOUT0", "LPOUT0_ALERTN", "GPOUT0_RESETN", + "LPOUT1", "LPOUT1_ALERTN", "GPOUT1_RESETN", + "LPOUT2", "LPOUT2_ALERTN", "GPOUT2_RESETN"; +}; + +&gpiof { + gpio-line-names = "LPOUT3", "LPOUT3_ALERTN", "GPOUT3_RESETN", + "LPOUT4", "LPOUT4_ALERTN", "GPOUT4_RESETN", + "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names = "LPOUT5", "LPOUT5_ALERTN", "", "LPOUT5_RESETN", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpioh { + gpio-line-names = "", "", "", "", + "", "", "", "", + "GPIO0_RESETN", "", "", "", + "", "", "", ""; +}; + +&gpioi { + gpio-line-names = "", "", "", "", + "", "", "", "", + "HPDCM0_SLEEPN", "HPDCM1_SLEEPN", "GPIO1_RESETN", "", + "", "", "", ""; +}; + +&gpioj { + gpio-line-names = "HSIN10", "HSIN11", "HSIN12", "HSIN13", + "HSIN14", "HSIN15", "", "", + "", "", "", "", + "", "RTD_RESETN", "", ""; +}; + +&gpiok { + gpio-line-names = "", "", "HSIN0", "HSIN1", + "HSIN2", "HSIN3", "HSIN4", "HSIN5"; +}; + +&gpioz { + gpio-line-names = "", "", "", "HSIN6", + "HSIN7", "HSIN8", "HSIN9", ""; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + pinctrl-1 = <&i2c2_sleep_pins_a>; + status = "okay"; + + gpio0: gpio@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS", + "", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL", + "HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN9_BIAS", + "", "", "", ""; + }; + + gpio1: gpio@21 { + compatible = "ti,tca6416"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "HSIN8_BIAS", "HSIN9_BIAS", "HSIN10_BIAS", "HSIN11_BIAS", + "", "", "HSIN_VREF2_LVL", "HSIN_VREF3_LVL", + "HSIN12_BIAS", "HSIN13_BIAS", "HSIN14_BIAS", "HSIN15_BIAS", + "", "", "LSIN8_BIAS", "LSIN9_BIAS"; + }; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <104000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +&{qspi_bk1_pins_a/pins} { + pinmux = , /* QSPI_BK1_IO0 */ + , /* QSPI_BK1_IO1 */ + , /* QSPI_BK1_IO2 */ + ; /* QSPI_BK1_IO3 */ + /delete-property/ bias-disable; + bias-pull-up; +}; + +&timers1 { + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + hpdcm0_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm1_pins_mecio1>; + pinctrl-1 = <&pwm1_sleep_pins_mecio1>; + status = "okay"; + }; +}; + +&timers8 { + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + hpdcm1_pwm: pwm { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pwm8_pins_mecio1>; + pinctrl-1 = <&pwm8_sleep_pins_mecio1>; + status = "okay"; + }; +}; + +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_a>; + pinctrl-1 = <&uart4_sleep_pins_a>; + pinctrl-2 = <&uart4_idle_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&{uart4_pins_a/pins1} { + pinmux = ; /* UART4_TX */ +}; + +&{uart4_pins_a/pins2} { + pinmux = ; /* UART4_RX */ + /delete-property/ bias-disable; + bias-pull-up; +}; + +&usbotg_hs { + dr_mode = "host"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + vbus-supply = <&v5v>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&v3v3>; +}; + +&usbphyc_port1 { + phy-supply = <&v3v3>; +}; + +&pinctrl { + adc12_pins_mecsbc: adc12-ain-mecsbc-0 { + pins { + pinmux = , /* ADC1_INP2 */ + , /* ADC1_INP6 */ + , /* ADC2_INP2 */ + , /* ADC2_INP6 */ + , /* ADC1_INP16 */ + , /* ADC1_INP15 */ + , /* ADC1_INP18 */ + , /* ADC1_INP19 */ + , /* ADC1_INP3 */ + , /* ADC1_INP9 */ + , /* ADC1_INP5 */ + , /* ADC1_INP10 */ + ; /* ADC1_INP13 */ + }; + }; + + pinctrl_hog_d_mecsbc: hog-d-0 { + pins { + pinmux = ; /* STP_RESETn */ + bias-pull-up; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_pins_mecio1: pwm1-mecio1-0 { + pins { + pinmux = , /* TIM1_CH1 */ + ; /* TIM1_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm1_sleep_pins_mecio1: pwm1-sleep-mecio1-0 { + pins { + pinmux = , /* TIM1_CH1 */ + ; /* TIM1_CH2 */ + }; + }; + + pwm8_pins_mecio1: pwm8-mecio1-0 { + pins { + pinmux = , /* TIM8_CH1 */ + ; /* TIM8_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_mecio1: pwm8-sleep-mecio1-0 { + pins { + pinmux = , /* TIM8_CH1 */ + ; /* TIM8_CH2 */ + }; + }; + + ethernet0_rgmii_pins_x: rgmii-0 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = ; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + }; + + ethernet0_rgmii_sleep_pins_x: rgmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RGMII_CLK125 */ + , /* ETH_RGMII_GTX_CLK */ + , /* ETH_RGMII_TXD0 */ + , /* ETH_RGMII_TXD1 */ + , /* ETH_RGMII_TXD2 */ + , /* ETH_RGMII_TXD3 */ + , /* ETH_RGMII_TX_CTL */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RGMII_RXD0 */ + , /* ETH_RGMII_RXD1 */ + , /* ETH_RGMII_RXD2 */ + , /* ETH_RGMII_RXD3 */ + , /* ETH_RGMII_RX_CLK */ + ; /* ETH_RGMII_RX_CTL */ + }; + }; +}; -- cgit From 2ac59e0957f8ab61eed226196f9532cc5e1b8fac Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 30 Aug 2024 23:56:36 +0200 Subject: ARM: dts: stm32: Sort properties in audio endpoints on STM32MP15xx DHCOM PDK2 Sort properties alphabetically in audio endpoints of STM32MP15xx DHCOM PDK2 DT. No functional change. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index 466d9701add0..22a2a204433b 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -191,16 +191,16 @@ sgtl5000_tx_endpoint: endpoint@0 { reg = <0>; - remote-endpoint = <&sai2a_endpoint>; - frame-master = <&sgtl5000_tx_endpoint>; bitclock-master = <&sgtl5000_tx_endpoint>; + frame-master = <&sgtl5000_tx_endpoint>; + remote-endpoint = <&sai2a_endpoint>; }; sgtl5000_rx_endpoint: endpoint@1 { reg = <1>; - remote-endpoint = <&sai2b_endpoint>; - frame-master = <&sgtl5000_rx_endpoint>; bitclock-master = <&sgtl5000_rx_endpoint>; + frame-master = <&sgtl5000_rx_endpoint>; + remote-endpoint = <&sai2b_endpoint>; }; }; @@ -246,9 +246,9 @@ sai2a_endpoint: endpoint { remote-endpoint = <&sgtl5000_tx_endpoint>; dai-format = "i2s"; - mclk-fs = <512>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; + mclk-fs = <512>; }; }; }; @@ -264,9 +264,9 @@ sai2b_endpoint: endpoint { remote-endpoint = <&sgtl5000_rx_endpoint>; dai-format = "i2s"; - mclk-fs = <512>; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; + mclk-fs = <512>; }; }; }; -- cgit From 5afb9b98a748ab9c6d5800aa62d90aaa5a28daa2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 30 Aug 2024 23:56:37 +0200 Subject: ARM: dts: stm32: Switch bitclock/frame-master to flag on STM32MP15xx DHCOM PDK2 Switch the bitclock-master and frame-master properties from phandle to flag on STM32MP15xx DHCOM PDK2. There is no real reason to use phandle in this system DT, since the phandle points to the endpoint node which contains the property itself. Simplify the DT. No functional change. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index 22a2a204433b..ea933da64903 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -191,15 +191,15 @@ sgtl5000_tx_endpoint: endpoint@0 { reg = <0>; - bitclock-master = <&sgtl5000_tx_endpoint>; - frame-master = <&sgtl5000_tx_endpoint>; + bitclock-master; + frame-master; remote-endpoint = <&sai2a_endpoint>; }; sgtl5000_rx_endpoint: endpoint@1 { reg = <1>; - bitclock-master = <&sgtl5000_rx_endpoint>; - frame-master = <&sgtl5000_rx_endpoint>; + bitclock-master; + frame-master; remote-endpoint = <&sai2b_endpoint>; }; }; -- cgit From 7d6b8316ba139c5a7cbbaa888089d9f4eb527dc9 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 30 Aug 2024 23:56:38 +0200 Subject: ARM: dts: stm32: Use SAI to generate bit and frame clock on STM32MP15xx DHCOM PDK2 By default the SGTL5000 derives bit and frame clock from MCLK, which does not produce particularly accurate results. The SGTL5000 PLL does improve the accuracy, but also increases power consumption. Using the SoC SAI interface as bit and frame clock source results in the best accuracy without the power consumption increase downside. Switch the bit and frame clock direction from SAI to SGTL5000, reduce mclk-fs to match. Signed-off-by: Marek Vasut Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi index ea933da64903..171d7c7658fa 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dhcom-pdk2.dtsi @@ -191,15 +191,11 @@ sgtl5000_tx_endpoint: endpoint@0 { reg = <0>; - bitclock-master; - frame-master; remote-endpoint = <&sai2a_endpoint>; }; sgtl5000_rx_endpoint: endpoint@1 { reg = <1>; - bitclock-master; - frame-master; remote-endpoint = <&sai2b_endpoint>; }; }; @@ -245,10 +241,12 @@ sai2a_port: port { sai2a_endpoint: endpoint { remote-endpoint = <&sgtl5000_tx_endpoint>; + bitclock-master; dai-format = "i2s"; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; - mclk-fs = <512>; + frame-master; + mclk-fs = <256>; }; }; }; @@ -263,10 +261,12 @@ sai2b_port: port { sai2b_endpoint: endpoint { remote-endpoint = <&sgtl5000_rx_endpoint>; + bitclock-master; dai-format = "i2s"; dai-tdm-slot-num = <2>; dai-tdm-slot-width = <16>; - mclk-fs = <512>; + frame-master; + mclk-fs = <256>; }; }; }; -- cgit