From 13ad4b7ce612f215437a479e6efc74aac2d20c25 Mon Sep 17 00:00:00 2001 From: Manikanta Mylavarapu Date: Mon, 22 May 2023 03:58:41 +0530 Subject: dt-bindings: mailbox: qcom: Add IPQ5018 APCS compatible Add compatible for the Qualcomm IPQ5018 APCS block. Signed-off-by: Manikanta Mylavarapu Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jassi Brar --- Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index 32d7bbc98cac..d2e25ff6db7f 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -18,6 +18,7 @@ properties: oneOf: - items: - enum: + - qcom,ipq5018-apcs-apps-global - qcom,ipq5332-apcs-apps-global - qcom,ipq8074-apcs-apps-global - qcom,ipq9574-apcs-apps-global -- cgit From ebb0130dad751e88c28ab94c71e46e8ee65427c9 Mon Sep 17 00:00:00 2001 From: Stefan Wahren Date: Sat, 17 Jun 2023 15:36:19 +0200 Subject: dt-bindings: mailbox: convert bcm2835-mbox bindings to YAML Convert the DT binding document for bcm2835-mbox from .txt to YAML. Signed-off-by: Stefan Wahren Reviewed-by: Rob Herring Signed-off-by: Jassi Brar --- .../bindings/mailbox/brcm,bcm2835-mbox.txt | 26 -------------- .../bindings/mailbox/brcm,bcm2835-mbox.yaml | 40 ++++++++++++++++++++++ 2 files changed, 40 insertions(+), 26 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt create mode 100644 Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.yaml diff --git a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt deleted file mode 100644 index b48d7d30012c..000000000000 --- a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt +++ /dev/null @@ -1,26 +0,0 @@ -Broadcom BCM2835 VideoCore mailbox IPC - -Required properties: - -- compatible: Should be "brcm,bcm2835-mbox" -- reg: Specifies base physical address and size of the registers -- interrupts: The interrupt number - See bindings/interrupt-controller/brcm,bcm2835-armctrl-ic.txt -- #mbox-cells: Specifies the number of cells needed to encode a mailbox - channel. The value shall be 0, since there is only one - mailbox channel implemented by the device. - -Example: - -mailbox: mailbox@7e00b880 { - compatible = "brcm,bcm2835-mbox"; - reg = <0x7e00b880 0x40>; - interrupts = <0 1>; - #mbox-cells = <0>; -}; - -firmware: firmware { - compatible = "raspberrypi,firmware"; - mboxes = <&mailbox>; - #power-domain-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.yaml b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.yaml new file mode 100644 index 000000000000..9588817f4511 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/brcm,bcm2835-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 VideoCore mailbox IPC + +maintainers: + - Stefan Wahren + +properties: + compatible: + const: brcm,bcm2835-mbox + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + "#mbox-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + mailbox@7e00b880 { + compatible = "brcm,bcm2835-mbox"; + reg = <0x7e00b880 0x40>; + interrupts = <0 1>; + #mbox-cells = <0>; + }; -- cgit From af9dbbbb4d30c4601a14c920c6ec9ae5cf0fdd22 Mon Sep 17 00:00:00 2001 From: Peter De Schrijver Date: Mon, 29 May 2023 16:50:43 +0300 Subject: dt-bindings: mailbox: tegra: Document Tegra264 HSP Add the compatible string for the HSP block found on the Tegra264 SoC. The HSP block in Tegra264 is not register compatible with the one in Tegra194 or Tegra234 hence there is no fallback compatibility string. Acked-by: Krzysztof Kozlowski Acked-by: Thierry Reding Signed-off-by: Peter De Schrijver Signed-off-by: Jassi Brar --- Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index a3e87516d637..2d14fc948999 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -66,6 +66,7 @@ properties: oneOf: - const: nvidia,tegra186-hsp - const: nvidia,tegra194-hsp + - const: nvidia,tegra264-hsp - items: - const: nvidia,tegra234-hsp - const: nvidia,tegra194-hsp -- cgit From 602dbbacc3ef9b0a8102202bbde9a5f253677cf0 Mon Sep 17 00:00:00 2001 From: Stefan Kristiansson Date: Mon, 29 May 2023 16:50:45 +0300 Subject: mailbox: tegra: add support for Tegra264 Tegra264 has a slightly different doorbell register layout than previous chips. Acked-by: Thierry Reding Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver Signed-off-by: Jassi Brar --- drivers/mailbox/tegra-hsp.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c index 573481e436f5..7f98e7436d94 100644 --- a/drivers/mailbox/tegra-hsp.c +++ b/drivers/mailbox/tegra-hsp.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. + * Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved. */ #include @@ -97,6 +97,7 @@ struct tegra_hsp_soc { const struct tegra_hsp_db_map *map; bool has_per_mb_ie; bool has_128_bit_mb; + unsigned int reg_stride; }; struct tegra_hsp { @@ -279,7 +280,7 @@ tegra_hsp_doorbell_create(struct tegra_hsp *hsp, const char *name, return ERR_PTR(-ENOMEM); offset = (1 + (hsp->num_sm / 2) + hsp->num_ss + hsp->num_as) * SZ_64K; - offset += index * 0x100; + offset += index * hsp->soc->reg_stride; db->channel.regs = hsp->regs + offset; db->channel.hsp = hsp; @@ -916,24 +917,35 @@ static const struct tegra_hsp_soc tegra186_hsp_soc = { .map = tegra186_hsp_db_map, .has_per_mb_ie = false, .has_128_bit_mb = false, + .reg_stride = 0x100, }; static const struct tegra_hsp_soc tegra194_hsp_soc = { .map = tegra186_hsp_db_map, .has_per_mb_ie = true, .has_128_bit_mb = false, + .reg_stride = 0x100, }; static const struct tegra_hsp_soc tegra234_hsp_soc = { .map = tegra186_hsp_db_map, .has_per_mb_ie = false, .has_128_bit_mb = true, + .reg_stride = 0x100, +}; + +static const struct tegra_hsp_soc tegra264_hsp_soc = { + .map = tegra186_hsp_db_map, + .has_per_mb_ie = false, + .has_128_bit_mb = true, + .reg_stride = 0x1000, }; static const struct of_device_id tegra_hsp_match[] = { { .compatible = "nvidia,tegra186-hsp", .data = &tegra186_hsp_soc }, { .compatible = "nvidia,tegra194-hsp", .data = &tegra194_hsp_soc }, { .compatible = "nvidia,tegra234-hsp", .data = &tegra234_hsp_soc }, + { .compatible = "nvidia,tegra264-hsp", .data = &tegra264_hsp_soc }, { } }; -- cgit From 1b712f18c461bd75f018033a15cf381e712806b5 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 20 Jun 2023 20:00:22 -0500 Subject: mailbox: ti-msgmgr: Fill non-message tx data fields with 0x0 Sec proxy/message manager data buffer is 60 bytes with the last of the registers indicating transmission completion. This however poses a bit of a challenge. The backing memory for sec_proxy / message manager is regular memory, and all sec proxy does is to trigger a burst of all 60 bytes of data over to the target thread backing ring accelerator. It doesn't do a memory scrub when it moves data out in the burst. When we transmit multiple messages, remnants of previous message is also transmitted which results in some random data being set in TISCI fields of messages that have been expanded forward. The entire concept of backward compatibility hinges on the fact that the unused message fields remain 0x0 allowing for 0x0 value to be specially considered when backward compatibility of message extension is done. So, instead of just writing the completion register, we continue to fill the message buffer up with 0x0 (note: for partial message involving completion, we already do this). This allows us to scale and introduce ABI changes back also work with other boot stages that may have left data in the internal memory. While at this, be consistent and explicit with the data_reg pointer increment. Fixes: aace66b170ce ("mailbox: Introduce TI message manager driver") Signed-off-by: Nishanth Menon Signed-off-by: Jassi Brar --- drivers/mailbox/ti-msgmgr.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/mailbox/ti-msgmgr.c b/drivers/mailbox/ti-msgmgr.c index ddac423ac1a9..03048cbda525 100644 --- a/drivers/mailbox/ti-msgmgr.c +++ b/drivers/mailbox/ti-msgmgr.c @@ -430,14 +430,20 @@ static int ti_msgmgr_send_data(struct mbox_chan *chan, void *data) /* Ensure all unused data is 0 */ data_trail &= 0xFFFFFFFF >> (8 * (sizeof(u32) - trail_bytes)); writel(data_trail, data_reg); - data_reg++; + data_reg += sizeof(u32); } + /* * 'data_reg' indicates next register to write. If we did not already * write on tx complete reg(last reg), we must do so for transmit + * In addition, we also need to make sure all intermediate data + * registers(if any required), are reset to 0 for TISCI backward + * compatibility to be maintained. */ - if (data_reg <= qinst->queue_buff_end) - writel(0, qinst->queue_buff_end); + while (data_reg <= qinst->queue_buff_end) { + writel(0, data_reg); + data_reg += sizeof(u32); + } /* If we are in polled mode, wait for a response before proceeding */ if (ti_msgmgr_chan_has_polled_queue_rx(message->chan_rx)) -- cgit