From 9ebdff9aac5ded7bb515e80478afacaaa3abd799 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sat, 31 Dec 2022 16:01:45 -0600 Subject: riscv: dts: allwinner: d1: Add crypto engine node D1 contains a crypto engine which is supported by the sun8i-ce driver. Signed-off-by: Samuel Holland Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20221231220146.646-4-samuel@sholland.org Signed-off-by: Jernej Skrabec --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 6fadcee7800f..951810d46307 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -367,6 +367,18 @@ #size-cells = <1>; }; + crypto: crypto@3040000 { + compatible = "allwinner,sun20i-d1-crypto"; + reg = <0x3040000 0x800>; + interrupts = ; + clocks = <&ccu CLK_BUS_CE>, + <&ccu CLK_CE>, + <&ccu CLK_MBUS_CE>, + <&rtc CLK_IOSC>; + clock-names = "bus", "mod", "ram", "trng"; + resets = <&ccu RST_BUS_CE>; + }; + mbus: dram-controller@3102000 { compatible = "allwinner,sun20i-d1-mbus"; reg = <0x3102000 0x1000>, -- cgit From 23ca1dd442249727abed6ac523b37d737ea5bdc0 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Tue, 28 Feb 2023 11:41:12 +0000 Subject: arm64: dts: allwinner: h5: OrangePi PC2: add OPP table to enable DVFS So far the OrangePi PC2 board was running at a fixed frequency, set by U-Boot to 816 MHz, which is the best achievable frequency at the 1.1V CPU voltage provided by the PMIC at reset. We already describe the CPU voltage regulator in the DT, but were missing the OPP table. Just include the default H5 OPP table, as used by other boards. My OrangePi PC2 runs just fine with those values, and now goes up to 1.15 GHz. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230228114112.3340715-1-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts index b5c1ff19b4c4..ce3ae19e72db 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts @@ -3,6 +3,7 @@ /dts-v1/; #include "sun50i-h5.dtsi" +#include "sun50i-h5-cpu-opp.dtsi" #include #include -- cgit From fce449f5ba9735a80a83fe636e0d6507902084a0 Mon Sep 17 00:00:00 2001 From: Trevor Woerner Date: Thu, 9 Feb 2023 21:51:32 -0500 Subject: riscv: dts: nezha-d1: add gpio-line-names Add descriptive names so users can associate specific lines with their respective pins on the 40-pin header according to the schematics. Signed-off-by: Trevor Woerner Link: http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230210025132.36605-2-twoerner@gmail.com Signed-off-by: Jernej Skrabec --- arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts | 72 +++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts index a0769185be97..4ed33c1e7c9c 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts @@ -1,6 +1,25 @@ // SPDX-License-Identifier: (GPL-2.0+ or MIT) // Copyright (C) 2021-2022 Samuel Holland +/* + * gpio line names + * + * The Nezha-D1 has a 40-pin IO header. Some of these pins are routed + * directly to pads on the SoC, others come from an 8-bit pcf857x IO + * expander. Therefore, these line names are specified in two places: + * one set for the pcf857x, and one set for the pio controller. + * + * Lines which are routed to the 40-pin header are named as follows: + * [] + * where: + * is the actual pin number of the 40-pin header + * is the name of the pin by function/gpio# + * + * For details regarding pin numbers and names see the schematics (under + * "IO EXPAND"): + * http://dl.linux-sunxi.org/D1/D1_Nezha_development_board_schematic_diagram_20210224.pdf + */ + #include #include @@ -90,6 +109,15 @@ gpio-controller; #gpio-cells = <2>; #interrupt-cells = <2>; + gpio-line-names = + "pin13 [gpio8]", + "pin16 [gpio10]", + "pin18 [gpio11]", + "pin26 [gpio17]", + "pin22 [gpio14]", + "pin28 [gpio19]", + "pin37 [gpio23]", + "pin11 [gpio6]"; }; }; @@ -164,3 +192,47 @@ usb1_vbus-supply = <®_vcc>; status = "okay"; }; + +&pio { + gpio-line-names = + /* Port A */ + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* Port B */ + "pin5 [gpio2/twi2-sck]", + "pin3 [gpio1/twi2-sda]", + "", + "pin38 [gpio24/i2s2-din]", + "pin40 [gpio25/i2s2-dout]", + "pin12 [gpio7/i2s-clk]", + "pin35 [gpio22/i2s2-lrck]", + "", + "pin8 [gpio4/uart0-txd]", + "pin10 [gpio5/uart0-rxd]", + "", + "", + "pin15 [gpio9]", + "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* Port C */ + "", + "pin31 [gpio21]", + "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + /* Port D */ + "", "", "", "", "", "", "", "", + "", "", + "pin24 [gpio16/spi1-ce0]", + "pin23 [gpio15/spi1-clk]", + "pin19 [gpio12/spi1-mosi]", + "pin21 [gpio13/spi1-miso]", + "pin27 [gpio18/spi1-hold]", + "pin29 [gpio20/spi1-wp]", + "", "", "", "", "", "", + "pin7 [gpio3/pwm]"; +}; -- cgit From f23ba46e0799fc701bcd429d22767932401e9ae8 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 19 Mar 2023 21:29:31 +0000 Subject: ARM: dts: suniv: add USB-related device nodes The suniv SoC has a USB OTG controller and a USB PHY like other Allwinner SoCs. Add their device tree node. Signed-off-by: Icenowy Zheng Reviewed-by: Andre Przywara Acked-by: Jernej Skrabec Signed-off-by: Andre Przywara Link: https://lore.kernel.org/r/20230319212936.26649-2-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 9455d27e516e..111f8bbc2a80 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -133,6 +133,32 @@ #size-cells = <0>; }; + usb_otg: usb@1c13000 { + compatible = "allwinner,suniv-f1c100s-musb"; + reg = <0x01c13000 0x0400>; + clocks = <&ccu CLK_BUS_OTG>; + resets = <&ccu RST_BUS_OTG>; + interrupts = <26>; + interrupt-names = "mc"; + phys = <&usbphy 0>; + phy-names = "usb"; + extcon = <&usbphy 0>; + allwinner,sram = <&otg_sram 1>; + status = "disabled"; + }; + + usbphy: phy@1c13400 { + compatible = "allwinner,suniv-f1c100s-usb-phy"; + reg = <0x01c13400 0x10>; + reg-names = "phy_ctrl"; + clocks = <&ccu CLK_USB_PHY0>; + clock-names = "usb0_phy"; + resets = <&ccu RST_USB_PHY0>; + reset-names = "usb0_reset"; + #phy-cells = <1>; + status = "disabled"; + }; + ccu: clock@1c20000 { compatible = "allwinner,suniv-f1c100s-ccu"; reg = <0x01c20000 0x400>; -- cgit From bedc7c5490fce4e57b55e025b4adfbd31f25623d Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 19 Mar 2023 21:29:32 +0000 Subject: ARM: dts: suniv: licheepi-nano: enable USB Lichee Pi Nano has a Micro-USB connector, with its D+, D- pins connected to the USB pins of the SoC and ID pin connected to PE2 GPIO. Enable the USB functionality. Signed-off-by: Icenowy Zheng Acked-by: Jernej Skrabec Signed-off-by: Andre Przywara Link: https://lore.kernel.org/r/20230319212936.26649-3-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts index 04e59b8381cb..43896723a994 100644 --- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts @@ -6,6 +6,8 @@ /dts-v1/; #include "suniv-f1c100s.dtsi" +#include + / { model = "Lichee Pi Nano"; compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s"; @@ -50,8 +52,22 @@ }; }; +&otg_sram { + status = "okay"; +}; + &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pe_pins>; status = "okay"; }; + +&usb_otg { + dr_mode = "otg"; + status = "okay"; +}; + +&usbphy { + usb0_id_det-gpios = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */ + status = "okay"; +}; -- cgit From eef696356f58a4f5c17ec5d7cb1d495f75edf62e Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 19 Mar 2023 21:29:33 +0000 Subject: dt-bindings: vendor-prefixes: add Source Parts and Lctech names Source Parts Inc. [1] is a company that makes a series of SBCs, SoMs, etc under a brand called Popcorn Computer [2]. Shenzen LC Technology [3] makes various boards and related products around IoT and AI technology. They used the "Cherry Pi" brand name before. Add both companies' names to the vendor prefixes list. [1] https://source.parts/ [2] https://popcorncomputer.com/ [3] http://www.chinalctech.com Signed-off-by: Icenowy Zheng Acked-by: Krzysztof Kozlowski Acked-by: Jernej Skrabec Signed-off-by: Andre Przywara Link: https://lore.kernel.org/r/20230319212936.26649-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index ed64e06ecca4..fbe837c6798a 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -721,6 +721,8 @@ patternProperties: description: Lantiq Semiconductor "^lattice,.*": description: Lattice Semiconductor + "^lctech,.*": + description: Shenzen LC Technology Co., Ltd. "^leadtek,.*": description: Shenzhen Leadtek Technology Co., Ltd. "^leez,.*": @@ -1243,6 +1245,8 @@ patternProperties: description: Solomon Systech Limited "^sony,.*": description: Sony Corporation + "^sourceparts,.*": + description: Source Parts Inc. "^spansion,.*": description: Spansion Inc. "^sparkfun,.*": -- cgit From e89556d6350430f4d9d38e555a298281e68e130e Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 19 Mar 2023 21:29:34 +0000 Subject: dt-binding: arm: sunxi: add two board compatible strings The SourceParts PopStick is a F1C200s-based stick-shaped SBC. The publicly released version is actually v1.1. The Lctech Pi F1C200s is a small development board using the Allwinner F1C200s SoC. Add the compatible string lists to the bindings documentation. Signed-off-by: Icenowy Zheng Acked-by: Krzysztof Kozlowski Signed-off-by: Andre Przywara Link: https://lore.kernel.org/r/20230319212936.26649-5-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/arm/sunxi.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index 3ad1cd50e3fe..cbdfc1c247a2 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -366,6 +366,12 @@ properties: - const: lamobo,lamobo-r1 - const: allwinner,sun7i-a20 + - description: Lctech Pi F1C200s + items: + - const: lctech,pi-f1c200s + - const: allwinner,suniv-f1c200s + - const: allwinner,suniv-f1c100s + - description: Libre Computer Board ALL-H3-CC H2+ items: - const: libretech,all-h3-cc-h2-plus @@ -807,6 +813,13 @@ properties: - const: sinlinx,sina33 - const: allwinner,sun8i-a33 + - description: SourceParts PopStick v1.1 + items: + - const: sourceparts,popstick-v1.1 + - const: sourceparts,popstick + - const: allwinner,suniv-f1c200s + - const: allwinner,suniv-f1c100s + - description: SL631 Action Camera with IMX179 items: - const: allwinner,sl631-imx179 -- cgit From 7452d4799c5b352d6987cff3db8b1e415466586e Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Sun, 19 Mar 2023 21:29:35 +0000 Subject: ARM: dts: suniv: add device tree for PopStick v1.1 PopStick is a minimal Allwinner F1C200s dongle, with its USB controller wired to a USB Type-A plug, a SD slot and a SPI NAND flash on board, and an on-board CH340 USB-UART converted connected to F1C200s's UART0. Add a device tree for it. As F1C200s is just F1C100s with a different DRAM chip co-packaged, directly use F1C100s DTSI here. This commit covers the v1.1 version of this board, which is now shipped. v1.0 is some internal sample that have not been shipped at all. Signed-off-by: Icenowy Zheng Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230319212936.26649-6-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts | 81 +++++++++++++++++++++++ 2 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index efe4152e5846..3b97d7c1e3c2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1406,7 +1406,8 @@ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-optimus.dtb \ sun9i-a80-cubieboard4.dtb dtb-$(CONFIG_MACH_SUNIV) += \ - suniv-f1c100s-licheepi-nano.dtb + suniv-f1c100s-licheepi-nano.dtb \ + suniv-f1c200s-popstick-v1.1.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-acer-a500-picasso.dtb \ tegra20-asus-tf101.dtb \ diff --git a/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts new file mode 100644 index 000000000000..184c245041a6 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c200s-popstick-v1.1.dts @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +#include +#include + +/ { + model = "Popcorn Computer PopStick v1.1"; + compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick", + "allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + function = LED_FUNCTION_STATUS; + color = ; + gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */ + linux,default-trigger = "heartbeat"; + }; + }; + + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + cd-gpios = <&pio 4 3 GPIO_ACTIVE_LOW>; /* PE3 */ + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pe_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; -- cgit From cc1858614f5d99d87d4467079c25f6bdf434add9 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Sun, 19 Mar 2023 21:29:36 +0000 Subject: ARM: dts: suniv: Add Lctech Pi F1C200s devicetree The Lctech Pi F1C200s (also previously known under the Cherry Pi brand) is a small development board with the Allwinner F1C200s SoC. This is the same as the F1C100s, but with 64MB instead of 32MB co-packaged DRAM. Alongside the obligatory micro-SD card slot, the board features a SPI-NAND flash chip, LCD and touch connectors, and unpopulated expansion header pins. There are two USB Type-C ports on the board: One supplies the power, also connects to the USB MUSB OTG controller port. The other one is connected to an CH340 USB serial chip, which in turn is connected to UART1. Add a devicetree file, so that the board can be used easily. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230319212936.26649-7-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/suniv-f1c100s.dtsi | 6 +++ arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts | 76 +++++++++++++++++++++++++++ 3 files changed, 83 insertions(+) create mode 100644 arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 3b97d7c1e3c2..a627d5593e51 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1407,6 +1407,7 @@ dtb-$(CONFIG_MACH_SUN9I) += \ sun9i-a80-cubieboard4.dtb dtb-$(CONFIG_MACH_SUNIV) += \ suniv-f1c100s-licheepi-nano.dtb \ + suniv-f1c200s-lctech-pi.dtb \ suniv-f1c200s-popstick-v1.1.dtb dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \ tegra20-acer-a500-picasso.dtb \ diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index 111f8bbc2a80..3c61d59ab5f8 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -207,6 +207,12 @@ pins = "PE0", "PE1"; function = "uart0"; }; + + /omit-if-no-ref/ + uart1_pa_pins: uart1-pa-pins { + pins = "PA2", "PA3"; + function = "uart1"; + }; }; i2c0: i2c@1c27000 { diff --git a/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts new file mode 100644 index 000000000000..2d2a3f026df3 --- /dev/null +++ b/arch/arm/boot/dts/suniv-f1c200s-lctech-pi.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 Arm Ltd, + * based on work: + * Copyright 2022 Icenowy Zheng + */ + +/dts-v1/; +#include "suniv-f1c100s.dtsi" + +#include + +/ { + model = "Lctech Pi F1C200s"; + compatible = "lctech,pi-f1c200s", "allwinner,suniv-f1c200s", + "allwinner,suniv-f1c100s"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_vcc3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&mmc0 { + broken-cd; + bus-width = <4>; + disable-wp; + vmmc-supply = <®_vcc3v3>; + status = "okay"; +}; + +&otg_sram { + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pc_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <40000000>; + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pa_pins>; + status = "okay"; +}; + +/* + * This is a Type-C socket, but CC1/2 are not connected, and VBUS is connected + * to Vin, which supplies the board. Host mode works (if the board is powered + * otherwise), but peripheral is probably the intention. + */ +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; -- cgit From a3eebcb61ffb9a26ca77a00ce80050cff0f0ecf3 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 20 Mar 2023 00:52:46 +0000 Subject: dts: add riscv include prefix link The Allwinner D1/D1s SoCs (with a RISC-V core) use an (almost?) identical die as their R528/T113-s siblings with ARM Cortex-A7 cores. To allow sharing the basic SoC .dtsi files across those two architectures as well, introduce a symlink to the RISC-V DT directory. Signed-off-by: Andre Przywara Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt Link: https://lore.kernel.org/r/20230320005249.13403-2-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- scripts/dtc/include-prefixes/riscv | 1 + 1 file changed, 1 insertion(+) create mode 120000 scripts/dtc/include-prefixes/riscv diff --git a/scripts/dtc/include-prefixes/riscv b/scripts/dtc/include-prefixes/riscv new file mode 120000 index 000000000000..202509418938 --- /dev/null +++ b/scripts/dtc/include-prefixes/riscv @@ -0,0 +1 @@ +../../../arch/riscv/boot/dts \ No newline at end of file -- cgit From 927e310e8e9d891b7621f77c369d234624d3a4fe Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 20 Mar 2023 00:52:47 +0000 Subject: ARM: dts: sunxi: add Allwinner T113-s SoC .dtsi The Allwinner T113-s SoC is apparently using the same (or at least a very similar) die as the D1/D1s, but replaces the single RISC-V core with two Arm Cortex-A7 cores. Since the D1 core .dtsi already describes all common peripherals, we just need a DT describing the ARM specific peripherals: the CPU cores, the Generic Timer, the GIC and the PMU. We include the core .dtsi directly from the riscv DT directory. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230320005249.13403-3-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun8i-t113s.dtsi | 59 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-t113s.dtsi diff --git a/arch/arm/boot/dts/sun8i-t113s.dtsi b/arch/arm/boot/dts/sun8i-t113s.dtsi new file mode 100644 index 000000000000..804aa197a24f --- /dev/null +++ b/arch/arm/boot/dts/sun8i-t113s.dtsi @@ -0,0 +1,59 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr + +#include +#include +#include + +/ { + interrupt-parent = <&gic>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <0>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a7"; + device_type = "cpu"; + reg = <1>; + clocks = <&ccu CLK_CPUX>; + clock-names = "cpu"; + }; + }; + + gic: interrupt-controller@1c81000 { + compatible = "arm,gic-400"; + reg = <0x03021000 0x1000>, + <0x03022000 0x2000>, + <0x03024000 0x2000>, + <0x03026000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + }; + + pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; -- cgit From c908060de362b2977db1b0ddba925353bc50aa29 Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 20 Mar 2023 00:52:48 +0000 Subject: dt-bindings: arm: sunxi: document MangoPi MQ-R board names The MangoPi MQ-R board is a small development board, using Allwinner SoCs with co-packaged DRAM. There are versions with a RISC-V core and ones with two Arm Cortex-A7 cores. Add the board/SoC compatible string pair to the list of known boards. Signed-off-by: Andre Przywara Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230320005249.13403-4-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ Documentation/devicetree/bindings/riscv/sunxi.yaml | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index cbdfc1c247a2..013821f4a7b8 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -856,6 +856,11 @@ properties: - const: wexler,tab7200 - const: allwinner,sun7i-a20 + - description: MangoPi MQ-R board + items: + - const: widora,mangopi-mq-r-t113 + - const: allwinner,sun8i-t113s + - description: WITS A31 Colombus Evaluation Board items: - const: wits,colombus diff --git a/Documentation/devicetree/bindings/riscv/sunxi.yaml b/Documentation/devicetree/bindings/riscv/sunxi.yaml index 9edb5e5992b1..b36e313e13a6 100644 --- a/Documentation/devicetree/bindings/riscv/sunxi.yaml +++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml @@ -64,6 +64,11 @@ properties: - const: widora,mangopi-mq-pro - const: allwinner,sun20i-d1 + - description: MangoPi MQ-R board + items: + - const: widora,mangopi-mq-r-f133 + - const: allwinner,sun20i-d1s + additionalProperties: true ... -- cgit From 20c5db6c3d79d357c9d787edad3bbf03d98a08bf Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 20 Mar 2023 00:52:49 +0000 Subject: ARM: dts: sunxi: add MangoPi MQ-R-T113 board The MangoPi MQ-R-T113 is a small SBC with the Allwinner T113-s3 SoC. The SoC features two Arm Cortex-A7 cores and 128 MB of co-packaged DDR3 DRAM. The board adds mostly connectors and the required regulators, plus a Realtek RTL8189FTV WiFi chip. Power comes in via a USB-C connector wired as a peripheral, and there is a second USB-C connector usable as a host port. Add a .dtsi file describing most of the board's peripherals, and include that from the actual board .dts file. This allows to re-use the .dtsi for the MQ-R-F113 RISC-V variant of that board. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230320005249.13403-5-andre.przywara@arm.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts | 35 ++++++ arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi | 126 +++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts create mode 100644 arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index a627d5593e51..3cc32722c394 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1397,6 +1397,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \ sun8i-s3-elimo-initium.dtb \ sun8i-s3-lichee-zero-plus.dtb \ sun8i-s3-pinecube.dtb \ + sun8i-t113s-mangopi-mq-r-t113.dtb \ sun8i-t3-cqa3t-bv3.dtb \ sun8i-v3-sl631-imx179.dtb \ sun8i-v3s-licheepi-zero.dtb \ diff --git a/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts b/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts new file mode 100644 index 000000000000..94e24b5926dd --- /dev/null +++ b/arch/arm/boot/dts/sun8i-t113s-mangopi-mq-r-t113.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. + +#include + +/dts-v1/; + +#include "sun8i-t113s.dtsi" +#include "sunxi-d1s-t113-mangopi-mq-r.dtsi" + +/ { + model = "MangoPi MQ-R-T113"; + compatible = "widora,mangopi-mq-r-t113", "allwinner,sun8i-t113s"; + + aliases { + ethernet0 = &rtl8189ftv; + }; +}; + +&cpu0 { + cpu-supply = <®_vcc_core>; +}; + +&cpu1 { + cpu-supply = <®_vcc_core>; +}; + +&mmc1 { + rtl8189ftv: wifi@1 { + reg = <1>; + interrupt-parent = <&pio>; + interrupts = <6 10 IRQ_TYPE_LEVEL_LOW>; /* PG10 = WL_WAKE_AP */ + interrupt-names = "host-wake"; + }; +}; diff --git a/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi b/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi new file mode 100644 index 000000000000..e9bc749488bb --- /dev/null +++ b/arch/arm/boot/dts/sunxi-d1s-t113-mangopi-mq-r.dtsi @@ -0,0 +1,126 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +// Copyright (C) 2022 Arm Ltd. +/* + * Common peripherals and configurations for MangoPi MQ-R boards. + */ + +#include +#include + +/ { + aliases { + serial3 = &uart3; + }; + + chosen { + stdout-path = "serial3:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = ; + function = LED_FUNCTION_STATUS; + gpios = <&pio 3 22 GPIO_ACTIVE_LOW>; /* PD22 */ + }; + }; + + /* board wide 5V supply directly from the USB-C socket */ + reg_vcc5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + /* SY8008 DC/DC regulator on the board */ + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vcc-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_vcc5v>; + }; + + /* SY8008 DC/DC regulator on the board, also supplying VDD-SYS */ + reg_vcc_core: regulator-core { + compatible = "regulator-fixed"; + regulator-name = "vcc-core"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <880000>; + vin-supply = <®_vcc5v>; + }; + + /* XC6206 LDO on the board */ + reg_avdd2v8: regulator-avdd { + compatible = "regulator-fixed"; + regulator-name = "avdd2v8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + vin-supply = <®_3v3>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&pio 6 12 GPIO_ACTIVE_LOW>; /* PG12 */ + }; +}; + +&dcxo { + clock-frequency = <24000000>; +}; + +&ehci1 { + status = "okay"; +}; + +&mmc0 { + pinctrl-0 = <&mmc0_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3v3>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + disable-wp; + bus-width = <4>; + status = "okay"; +}; + +&mmc1 { + pinctrl-0 = <&mmc1_pins>; + pinctrl-names = "default"; + vmmc-supply = <®_3v3>; + non-removable; + bus-width = <4>; + mmc-pwrseq = <&wifi_pwrseq>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_3v3>; + vcc-pd-supply = <®_3v3>; + vcc-pe-supply = <®_avdd2v8>; + vcc-pf-supply = <®_3v3>; + vcc-pg-supply = <®_3v3>; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pb_pins>; + status = "okay"; +}; + +/* The USB-C socket has its CC pins pulled to GND, so is hardwired as a UFP. */ +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + usb1_vbus-supply = <®_vcc5v>; + status = "okay"; +}; -- cgit From a9efe94fbd0bb1c9c32393b1dd7cddd75c07db42 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 21 Mar 2023 23:56:16 +0200 Subject: ARM: dts: sun6i: a31: Switch dma-names order for snps,dw-apb-uart nodes Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230321215624.78383-3-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun6i-a31.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi index 6cdadba6a3ac..5cce4918f84c 100644 --- a/arch/arm/boot/dts/sun6i-a31.dtsi +++ b/arch/arm/boot/dts/sun6i-a31.dtsi @@ -822,7 +822,7 @@ clocks = <&ccu CLK_APB2_UART0>; resets = <&ccu RST_APB2_UART0>; dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -835,7 +835,7 @@ clocks = <&ccu CLK_APB2_UART1>; resets = <&ccu RST_APB2_UART1>; dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -848,7 +848,7 @@ clocks = <&ccu CLK_APB2_UART2>; resets = <&ccu RST_APB2_UART2>; dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -861,7 +861,7 @@ clocks = <&ccu CLK_APB2_UART3>; resets = <&ccu RST_APB2_UART3>; dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -874,7 +874,7 @@ clocks = <&ccu CLK_APB2_UART4>; resets = <&ccu RST_APB2_UART4>; dmas = <&dma 10>, <&dma 10>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -887,7 +887,7 @@ clocks = <&ccu CLK_APB2_UART5>; resets = <&ccu RST_APB2_UART5>; dmas = <&dma 22>, <&dma 22>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; -- cgit From d4880d2b81d8167b2cb7e27026c42dd1df9dbf8d Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 21 Mar 2023 23:56:17 +0200 Subject: ARM: dts: sun8i: a23/a33: Switch dma-names order for snps,dw-apb-uart nodes Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230321215624.78383-4-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index f630ab55bb6a..4aa9d88c9ea3 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -490,7 +490,7 @@ clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -503,7 +503,7 @@ clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -516,7 +516,7 @@ clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -529,7 +529,7 @@ clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -542,7 +542,7 @@ clocks = <&ccu CLK_BUS_UART4>; resets = <&ccu RST_BUS_UART4>; dmas = <&dma 10>, <&dma 10>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; -- cgit From 1532d4f4d7803e8a5c4c70c280427b2d25b7abc2 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 21 Mar 2023 23:56:18 +0200 Subject: ARM: dts: sun8i: v3s: Switch dma-names order for snps,dw-apb-uart nodes Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230321215624.78383-5-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sun8i-v3s.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi index db194c606fdc..b001251644f7 100644 --- a/arch/arm/boot/dts/sun8i-v3s.dtsi +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi @@ -479,7 +479,7 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART0>; status = "disabled"; }; @@ -492,7 +492,7 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART1>; status = "disabled"; }; @@ -505,7 +505,7 @@ reg-io-width = <4>; clocks = <&ccu CLK_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; resets = <&ccu RST_BUS_UART2>; pinctrl-0 = <&uart2_pins>; pinctrl-names = "default"; -- cgit From bb9ecbee05f5fd0042caf264835fad55a132d8c7 Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 21 Mar 2023 23:56:19 +0200 Subject: ARM: dts: sunxi: h3/h5: Switch dma-names order for snps,dw-apb-uart nodes Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230321215624.78383-6-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 686193bd6bd9..ade1cd50e445 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -710,7 +710,7 @@ clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; dmas = <&dma 6>, <&dma 6>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -723,7 +723,7 @@ clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; dmas = <&dma 7>, <&dma 7>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -736,7 +736,7 @@ clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; dmas = <&dma 8>, <&dma 8>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -749,7 +749,7 @@ clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; dmas = <&dma 9>, <&dma 9>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; -- cgit From a140b18f0cc79f5c302ecedbde8364d49effa67f Mon Sep 17 00:00:00 2001 From: Cristian Ciocaltea Date: Tue, 21 Mar 2023 23:56:20 +0200 Subject: riscv: dts: allwinner: d1: Switch dma-names order for snps,dw-apb-uart nodes Commit 370f696e4474 ("dt-bindings: serial: snps-dw-apb-uart: add dma & dma-names properties") documented dma-names property to handle Allwinner D1 dtbs_check warnings, but relies on the rx->tx ordering, which is the reverse of what a bunch of different boards expect. The initial proposed solution was to allow a flexible dma-names order in the binding, due to potential ABI breakage concerns after fixing the DTS files. But luckily the Allwinner boards are not affected, since they are using a shared DMA channel for rx and tx. Hence, the first step in fixing the inconsistency was to change dma-names order in the binding to tx->rx. Do the same for the snps,dw-apb-uart nodes in the DTS file. Signed-off-by: Cristian Ciocaltea Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20230321215624.78383-7-cristian.ciocaltea@collabora.com Signed-off-by: Jernej Skrabec --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 951810d46307..922e8e0e2c09 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -211,7 +211,7 @@ clocks = <&ccu CLK_BUS_UART0>; resets = <&ccu RST_BUS_UART0>; dmas = <&dma 14>, <&dma 14>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -224,7 +224,7 @@ clocks = <&ccu CLK_BUS_UART1>; resets = <&ccu RST_BUS_UART1>; dmas = <&dma 15>, <&dma 15>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -237,7 +237,7 @@ clocks = <&ccu CLK_BUS_UART2>; resets = <&ccu RST_BUS_UART2>; dmas = <&dma 16>, <&dma 16>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -250,7 +250,7 @@ clocks = <&ccu CLK_BUS_UART3>; resets = <&ccu RST_BUS_UART3>; dmas = <&dma 17>, <&dma 17>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -263,7 +263,7 @@ clocks = <&ccu CLK_BUS_UART4>; resets = <&ccu RST_BUS_UART4>; dmas = <&dma 18>, <&dma 18>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; @@ -276,7 +276,7 @@ clocks = <&ccu CLK_BUS_UART5>; resets = <&ccu RST_BUS_UART5>; dmas = <&dma 19>, <&dma 19>; - dma-names = "rx", "tx"; + dma-names = "tx", "rx"; status = "disabled"; }; -- cgit