From bdd166bee8270534e42dc41793a43f3ec3b20dc9 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Jul 2021 10:28:44 -0300 Subject: arm64: dts: imx8mm-kontron-n801x-som: Fix the SPI chipselect polarity The conversion of the spi-imx driver to use GPIO descriptors in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors") helped to detect the following SPI chipselect polarity mismatch on an imx6q-sabresd for example: [ 4.854337] m25p80@0 enforce active low on chipselect handle Prior to the above commit, the chipselect polarity passed via cs-gpios property was ignored and considered active-low. The reason for such mismatch is clearly explained in the comments inside drivers/gpio/gpiolib-of.c: * SPI children have active low chip selects * by default. This can be specified negatively * by just omitting "spi-cs-high" in the * device node, or actively by tagging on * GPIO_ACTIVE_LOW as flag in the device * tree. If the line is simultaneously * tagged as active low in the device tree * and has the "spi-cs-high" set, we get a * conflict and the "spi-cs-high" flag will * take precedence. To properly represent the SPI chipselect polarity, change it to active-low when the "spi-cs-high" property is absent. Signed-off-by: Fabio Estevam Reviewed-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index d0456daefda8..5a2805c51361 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -63,7 +63,7 @@ &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; - cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; status = "okay"; spi-flash@0 { -- cgit From c6fe862aa35c741b5b82cc5bda5f0c3cebf11bde Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Fri, 16 Jul 2021 10:28:45 -0300 Subject: arm64: dts: imx8mm-venice: Fix the SPI chipselect polarity The conversion of the spi-imx driver to use GPIO descriptors in commit 8cdcd8aeee28 ("spi: imx/fsl-lpspi: Convert to GPIO descriptors") helped to detect the following SPI chipselect polarity mismatch on an imx6q-sabresd for example: [ 4.854337] m25p80@0 enforce active low on chipselect handle Prior to the above commit, the chipselect polarity passed via cs-gpios property was ignored and considered active-low. The reason for such mismatch is clearly explained in the comments inside drivers/gpio/gpiolib-of.c: * SPI children have active low chip selects * by default. This can be specified negatively * by just omitting "spi-cs-high" in the * device node, or actively by tagging on * GPIO_ACTIVE_LOW as flag in the device * tree. If the line is simultaneously * tagged as active low in the device tree * and has the "spi-cs-high" set, we get a * conflict and the "spi-cs-high" flag will * take precedence. To properly represent the SPI chipselect polarity, change it to active-low when the "spi-cs-high" property is absent. Signed-off-by: Fabio Estevam Reviewed-By: Tim Harvey Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 2 +- arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 8e4a0ce99790..28012279f6f6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -57,7 +57,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index b7c91bdc21dd..27afa46a253a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -76,7 +76,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index d2ffd62a3bd4..a59e849c7be2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -96,7 +96,7 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; status = "okay"; }; -- cgit From 91db167009366caad1eaaaf3786dae4d4fde63a5 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 20 Aug 2021 10:15:57 +0200 Subject: arm64: dts: freescale: imx8mq-librem5: align operating-points table name with dtschema Align the name of operating-points node to dtschema to fix warnings like: ddrc-opp-table: $nodename:0: 'ddrc-opp-table' does not match '^opp-table(-[a-z0-9]+)?$' Signed-off-by: Krzysztof Kozlowski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 460ef0d86540..3f7524400a63 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -225,7 +225,7 @@ &ddrc { operating-points-v2 = <&ddrc_opp_table>; - ddrc_opp_table: ddrc-opp-table { + ddrc_opp_table: opp-table { compatible = "operating-points-v2"; opp-25M { -- cgit From c4ce6e6c1d784fd7acc8b6c5166750a6034937de Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 20 Aug 2021 23:25:37 +0200 Subject: arm64: dts: imx8mq-reform2: add uSDHC2 CD pinctrl The SD card slot on the Reform 2 uses the card detect pad routed to the uSDHC2 module as intended. This is currently working as it is the default mux setting for this pad, but better be explicit and add it to the pinctrl node. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts index 2535268f0984..4f2db6197b39 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-mnt-reform2.dts @@ -202,6 +202,7 @@ pinctrl_usdhc2: usdhc2grp { fsl,pins = < + MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x0 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 -- cgit From 628550e2b4a9499ae92222a2e2c5902c456a56ef Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 21 Aug 2021 00:44:02 +0200 Subject: arm64: dts: zii-ultra: add PCIe PHY supply The ZII Ultra board uses the same design as the EVK board supplying PCIE_VPH with 3.3V. Add this connection to the DT to allow the PCIe driver to enable the internal PHY regulator, as required by the reference manual. Signed-off-by: Lucas Stach Reviewed-by: Fabio Estevam Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index a08a568c31d9..2222ef7b3eab 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -555,6 +555,7 @@ <&clk IMX8MQ_CLK_PCIE1_PHY>, <&pcie0_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + vph-supply = <&vgen5_reg>; status = "okay"; }; @@ -567,6 +568,7 @@ <&clk IMX8MQ_CLK_PCIE2_PHY>, <&pcie1_refclk>; clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + vph-supply = <&vgen5_reg>; status = "okay"; }; -- cgit From 99a7cacc66cae92db40139b57689be2af75fc6b8 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Thu, 26 Aug 2021 14:35:28 +0200 Subject: arm64: dts: freescale: fix arm,sp805 compatible string According to Documentation/devicetree/bindings/watchdog/arm,sp805.yaml the compatible is: compatible = "arm,sp805", "arm,primecell"; The current compatible string doesn't exist at all. Fix it. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 ++++++++-------- arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 ++++++++-------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index f85e437f80b7..605072317243 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -847,7 +847,7 @@ }; cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, @@ -857,7 +857,7 @@ }; cluster1_core1_watchdog: wdt@c010000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, @@ -867,7 +867,7 @@ }; cluster1_core2_watchdog: wdt@c020000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc020000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, @@ -877,7 +877,7 @@ }; cluster1_core3_watchdog: wdt@c030000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc030000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, @@ -887,7 +887,7 @@ }; cluster2_core0_watchdog: wdt@c100000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, @@ -897,7 +897,7 @@ }; cluster2_core1_watchdog: wdt@c110000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, @@ -907,7 +907,7 @@ }; cluster2_core2_watchdog: wdt@c120000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc120000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, @@ -917,7 +917,7 @@ }; cluster2_core3_watchdog: wdt@c130000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc130000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(16)>, diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 801ba9612d36..1282b61da8a5 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -387,7 +387,7 @@ }; cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, @@ -397,7 +397,7 @@ }; cluster1_core1_watchdog: wdt@c010000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, @@ -407,7 +407,7 @@ }; cluster2_core0_watchdog: wdt@c100000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, @@ -417,7 +417,7 @@ }; cluster2_core1_watchdog: wdt@c110000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, @@ -427,7 +427,7 @@ }; cluster3_core0_watchdog: wdt@c200000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc200000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, @@ -437,7 +437,7 @@ }; cluster3_core1_watchdog: wdt@c210000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc210000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, @@ -447,7 +447,7 @@ }; cluster4_core0_watchdog: wdt@c300000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc300000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, @@ -457,7 +457,7 @@ }; cluster4_core1_watchdog: wdt@c310000 { - compatible = "arm,sp805-wdt", "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc310000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL QORIQ_CLK_PLL_DIV(4)>, -- cgit From c179ee1e2c2ee49f1d3bc968000aaaac8e6d57d1 Mon Sep 17 00:00:00 2001 From: Richard Zhu Date: Fri, 27 Aug 2021 14:43:00 +0800 Subject: arm64: dts: imx8mq: fix the schema check errors No functional changes, but the ranges should be grouped by region. Otherwise, schema dtbs_check would report the following errors. "/linux-imx/arch/arm64/boot/dts/freescale/imx8mq-evk.dt.yaml: pcie@33800000: ranges: 'oneOf' conditional failed, one must be fixed: /linux-imx/arch/arm64/boot/dts/freescale/imx8mq-evk.dt.yaml: pcie@33800000: ranges: 'oneOf' conditional failed, one must be fixed: [[2164260864, 0, 0, 536346624, 0, 65536, 2181038080, 0, 402653184, 402653184, 0, 133169152]] is not of type 'boolean' True was expected [[2164260864, 0, 0, 536346624, 0, 65536, 2181038080, 0, 402653184, 402653184, 0, 133169152]] is not of type 'null' [2164260864, 0, 0, 536346624, 0, 65536, 2181038080, 0, 402653184, 402653184, 0, 133169152] is too long From schema: //linux-imx/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml" Refer to commit 281f1f99cf3a ("PCI: dwc: Detect number of iATU windows"). The num-viewport is not required anymore, remove them totally. Signed-off-by: Richard Zhu Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 4066b1612655..972766b67a15 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -1467,10 +1467,9 @@ #size-cells = <2>; device_type = "pci"; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; - num-viewport = <4>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; @@ -1505,10 +1504,9 @@ #address-cells = <3>; #size-cells = <2>; device_type = "pci"; - ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000 /* downstream I/O 64KB */ - 0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ + ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ + <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ num-lanes = <1>; - num-viewport = <4>; interrupts = ; interrupt-names = "msi"; #interrupt-cells = <1>; -- cgit From d7cd74466651e166c0f6272190966496453faa0c Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Wed, 8 Sep 2021 12:21:26 +0530 Subject: arm64: dts: imx8mp: Reorder flexspi clock-names entry Reorder flexspi clock-names entry to make it compliant with bindings. Signed-off-by: Kuldeep Singh Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 9b07b26230a1..04d259de5667 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -785,7 +785,7 @@ interrupts = ; clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, <&clk IMX8MP_CLK_QSPI_ROOT>; - clock-names = "fspi", "fspi_en"; + clock-names = "fspi_en", "fspi"; assigned-clock-rates = <80000000>; assigned-clocks = <&clk IMX8MP_CLK_QSPI>; #address-cells = <1>; -- cgit From 7f31ae6e01da140e34d6513815253e811019f016 Mon Sep 17 00:00:00 2001 From: Kuldeep Singh Date: Thu, 9 Sep 2021 16:42:29 +0530 Subject: arm64: dts: ls1012a: Add serial alias for ls1012a-rdb U-boot atempts to read serial alias value for ls1012a-rdb but couldn't do so as it is not initialised and thus, FDT_ERR_NOTFOUND error is reported while booting linux. Loading fdt from FIT Image at a0000000 ... Description: ls1012ardb-dtb Type: Flat Device Tree Data Start: 0xab111474 Data Size: 11285 Bytes = 11 KiB Architecture: AArch64 Load Address: 0x90000000 Loading fdt from 0xab111474 to 0x90000000 Booting using the fdt blob at 0x90000000 Uncompressing Kernel Image Loading Device Tree to 000000008fffa000, end 000000008ffffc14 ... OK WARNING: fdt_fixup_stdout: could not read serial0 alias: FDT_ERR_NOTFOUND NOTICE: RNG: INSTANTIATED Starting kernel ... Fix the above error by specifying serial value to duart. Signed-off-by: Kuldeep Singh Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts index 79f155dedb2d..e662677a6e28 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts @@ -15,6 +15,7 @@ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; aliases { + serial0 = &duart0; mmc0 = &esdhc0; mmc1 = &esdhc1; }; -- cgit From aa3457d4c137da1f7545eba40fbb8a282c8d1c09 Mon Sep 17 00:00:00 2001 From: Wasim Khan Date: Fri, 27 Aug 2021 23:27:22 +0300 Subject: arm64: dts: add device tree for the LX2160A on the NXP BlueBox3 board The NXP BlueBox3 is a prototyping board for high-performance autonomous driving systems. It contains two Linux systems, running on the LX2160A and the other on the S32G2 SoC. This patch adds the device tree support for the LX2160A SoC. In terms of networking from the LX2160A's perspective, there are: - 4 RJ45 10G ports using Aquantia copper PHYs which are attached directly to DPAA2 ports on the LX2160A - 3 NXP SJA1110 automotive Ethernet switches. First two are managed by the LX2160A (each switch has a host port towards a dpmac), the third switch is managed by the S32G2. All 3 switches are interconnected through on-board SERDES lanes. The cascade ports between the 2 switches managed by LX2160A form a DSA link, the cascade ports between the LX2160A and the S32G2 domain form user ports (the "to_sw3" net device). - 2 RJ45 1G ports using Atheros copper PHYs which are attached directly to NXP SJA1110 switches - 12 automotive 100base-T1 single-pair Ethernet ports routed from the SJA1110 internal PHY ports (TJA1103) - One SGMII SERDES lane towards an internal connector, attached to one of the SJA1110 switch ports On board rev A, the AR8035 RGMII PHY addresses were different than on rev B and later. This patch introduces a separate device tree for rev A. The main device tree is supposed to cover rev B and later. Signed-off-by: Wasim Khan Co-developed-by: Vabhav Sharma Signed-off-by: Vabhav Sharma Co-developed-by: Kuldeep Singh Signed-off-by: Kuldeep Singh Co-developed-by: Florin Chiculita Signed-off-by: Florin Chiculita Co-developed-by: Biwen Li Signed-off-by: Biwen Li Co-developed-by: Heinz Wrobel Signed-off-by: Heinz Wrobel Co-developed-by: Yangbo Lu Signed-off-by: Yangbo Lu Co-developed-by: Vladimir Oltean Signed-off-by: Vladimir Oltean Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 + .../dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts | 34 ++ .../boot/dts/freescale/fsl-lx2160a-bluebox3.dts | 658 +++++++++++++++++++++ 3 files changed, 694 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index db9e36ebe932..ecf74464705f 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -25,6 +25,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-bluebox3-rev-a.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts new file mode 100644 index 000000000000..15d273c93154 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3-rev-a.dts @@ -0,0 +1,34 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2160A BLUEBOX3 +// +// Copyright 2020-2021 NXP + +/dts-v1/; + +#include "fsl-lx2160a-bluebox3.dts" + +/ { + compatible = "fsl,lx2160a-bluebox3-rev-a", "fsl,lx2160a"; +}; + +/* The RGMII PHYs have a different MDIO address */ +&emdio1 { + /delete-node/ ethernet-phy@5; + + sw1_mii3_phy: ethernet-phy@1 { + /* AR8035 */ + compatible = "ethernet-phy-id004d.d072"; + reg = <0x1>; + interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>; + }; + + /delete-node/ ethernet-phy@6; + + sw2_mii3_phy: ethernet-phy@2 { + /* AR8035 */ + compatible = "ethernet-phy-id004d.d072"; + reg = <0x2>; + interrupts-extended = <&extirq 7 IRQ_TYPE_LEVEL_LOW>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts new file mode 100644 index 000000000000..b21be03da0af --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-bluebox3.dts @@ -0,0 +1,658 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2160A BLUEBOX3 +// +// Copyright 2020-2021 NXP + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" + +/ { + model = "NXP Layerscape LX2160ABLUEBOX3"; + compatible = "fsl,lx2160a-bluebox3", "fsl,lx2160a"; + + aliases { + crypto = &crypto; + mmc0 = &esdhc0; + mmc1 = &esdhc1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + sb_3v3: regulator-sb3v3 { + compatible = "regulator-fixed"; + regulator-name = "MC34717-3.3VSB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&can0 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&can1 { + status = "okay"; + + can-transceiver { + max-bitrate = <5000000>; + }; +}; + +&crypto { + status = "okay"; +}; + +&dpmac5 { + phy-handle = <&aqr113c_phy1>; + phy-mode = "usxgmii"; + managed = "in-band-status"; +}; + +&dpmac6 { + phy-handle = <&aqr113c_phy2>; + phy-mode = "usxgmii"; + managed = "in-band-status"; +}; + +&dpmac9 { + phy-handle = <&aqr113c_phy3>; + phy-mode = "usxgmii"; + managed = "in-band-status"; +}; + +&dpmac10 { + phy-handle = <&aqr113c_phy4>; + phy-mode = "usxgmii"; + managed = "in-band-status"; +}; + +&dpmac17 { + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&dpmac18 { + phy-mode = "rgmii"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&emdio1 { + status = "okay"; + + aqr113c_phy2: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + /* IRQ_10G_PHY2 */ + interrupts-extended = <&extirq 3 IRQ_TYPE_LEVEL_LOW>; + }; + + aqr113c_phy1: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x8>; + /* IRQ_10G_PHY1 */ + interrupts-extended = <&extirq 2 IRQ_TYPE_LEVEL_LOW>; + }; + + sw1_mii3_phy: ethernet-phy@5 { + /* AR8035 */ + compatible = "ethernet-phy-id004d.d072"; + reg = <0x5>; + interrupts-extended = <&extirq 6 IRQ_TYPE_LEVEL_LOW>; + }; + + sw2_mii3_phy: ethernet-phy@6 { + /* AR8035 */ + compatible = "ethernet-phy-id004d.d072"; + reg = <0x6>; + interrupts-extended = <&extirq 7 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&emdio2 { + status = "okay"; + + aqr113c_phy4: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + /* IRQ_10G_PHY4 */ + interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>; + }; + + aqr113c_phy3: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x8>; + /* IRQ_10G_PHY3 */ + interrupts-extended = <&extirq 4 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; + status = "okay"; +}; + +&esdhc1 { + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + status = "okay"; +}; + +&fspi { + status = "okay"; + + mt35xu512aba0: flash@0 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; + }; + + mt35xu512aba1: flash@1 { + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + reg = <1>; + m25p,fast-read; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <8>; + spi-tx-bus-width = <8>; + }; +}; + +&i2c0 { + status = "okay"; + + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x2>; + + power-monitor@40 { + compatible = "ti,ina220"; + reg = <0x40>; + shunt-resistor = <500>; + }; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3>; + + temp2: temperature-sensor@48 { + compatible = "nxp,sa56004"; + reg = <0x48>; + vcc-supply = <&sb_3v3>; + #thermal-sensor-cells = <1>; + }; + + temp1: temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <&sb_3v3>; + #thermal-sensor-cells = <1>; + }; + }; + + i2c@4 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x4>; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + interrupts-extended = <&extirq 11 IRQ_TYPE_LEVEL_LOW>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + + i2c-mux@75 { + compatible = "nxp,pca9547"; + reg = <0x75>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0>; + + spi_bridge: spi@28 { + compatible = "nxp,sc18is602b"; + reg = <0x28>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + }; + }; +}; + +&i2c5 { + status = "okay"; + + i2c-mux@77 { + compatible = "nxp,pca9846"; + reg = <0x77>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1>; + + /* The I2C multiplexer and temperature sensors are on + * the T6 riser card. + */ + i2c-mux@70 { + compatible = "nxp,pca9548"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@6 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x6>; + + q12: temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <&sb_3v3>; + #thermal-sensor-cells = <1>; + }; + }; + + i2c@7 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7>; + + q11: temperature-sensor@4c { + compatible = "nxp,sa56004"; + reg = <0x4c>; + vcc-supply = <&sb_3v3>; + #thermal-sensor-cells = <1>; + }; + + q13: temperature-sensor@48 { + compatible = "nxp,sa56004"; + reg = <0x48>; + vcc-supply = <&sb_3v3>; + #thermal-sensor-cells = <1>; + }; + + q14: temperature-sensor@4a { + compatible = "nxp,sa56004"; + reg = <0x4a>; + vcc-supply = <&sb_3v3>; + #thermal-sensor-cells = <1>; + }; + }; + }; + }; + }; +}; + +&pcs_mdio5 { + status = "okay"; +}; + +&pcs_mdio6 { + status = "okay"; +}; + +&pcs_mdio9 { + status = "okay"; +}; + +&pcs_mdio10 { + status = "okay"; +}; + +&spi_bridge { + sw1: ethernet-switch@0 { + compatible = "nxp,sja1110a"; + reg = <0>; + spi-max-frequency = <4000000>; + spi-cpol; + dsa,member = <0 0>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* Microcontroller port */ + port@0 { + reg = <0>; + status = "disabled"; + }; + + /* SW1_P1 */ + port@1 { + reg = <1>; + label = "con_2x20"; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@2 { + reg = <2>; + ethernet = <&dpmac17>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@3 { + reg = <3>; + label = "1ge_p1"; + phy-mode = "rgmii-id"; + phy-handle = <&sw1_mii3_phy>; + }; + + sw1p4: port@4 { + reg = <4>; + link = <&sw2p1>; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@5 { + reg = <5>; + label = "trx1"; + phy-mode = "internal"; + phy-handle = <&sw1_port5_base_t1_phy>; + }; + + port@6 { + reg = <6>; + label = "trx2"; + phy-mode = "internal"; + phy-handle = <&sw1_port6_base_t1_phy>; + }; + + port@7 { + reg = <7>; + label = "trx3"; + phy-mode = "internal"; + phy-handle = <&sw1_port7_base_t1_phy>; + }; + + port@8 { + reg = <8>; + label = "trx4"; + phy-mode = "internal"; + phy-handle = <&sw1_port8_base_t1_phy>; + }; + + port@9 { + reg = <9>; + label = "trx5"; + phy-mode = "internal"; + phy-handle = <&sw1_port9_base_t1_phy>; + }; + + port@a { + reg = <10>; + label = "trx6"; + phy-mode = "internal"; + phy-handle = <&sw1_port10_base_t1_phy>; + }; + }; + + mdios { + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + compatible = "nxp,sja1110-base-t1-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + sw1_port5_base_t1_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + sw1_port6_base_t1_phy: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + + sw1_port7_base_t1_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; + + sw1_port8_base_t1_phy: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x4>; + }; + + sw1_port9_base_t1_phy: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x5>; + }; + + sw1_port10_base_t1_phy: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x6>; + }; + }; + }; + }; + + sw2: ethernet-switch@2 { + compatible = "nxp,sja1110a"; + reg = <2>; + spi-max-frequency = <4000000>; + spi-cpol; + dsa,member = <0 1>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + /* Microcontroller port */ + port@0 { + reg = <0>; + status = "disabled"; + }; + + sw2p1: port@1 { + reg = <1>; + link = <&sw1p4>; + phy-mode = "sgmii"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@2 { + reg = <2>; + ethernet = <&dpmac18>; + phy-mode = "rgmii-id"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + port@3 { + reg = <3>; + label = "1ge_p2"; + phy-mode = "rgmii-id"; + phy-handle = <&sw2_mii3_phy>; + }; + + port@4 { + reg = <4>; + label = "to_sw3"; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + port@5 { + reg = <5>; + label = "trx7"; + phy-mode = "internal"; + phy-handle = <&sw2_port5_base_t1_phy>; + }; + + port@6 { + reg = <6>; + label = "trx8"; + phy-mode = "internal"; + phy-handle = <&sw2_port6_base_t1_phy>; + }; + + port@7 { + reg = <7>; + label = "trx9"; + phy-mode = "internal"; + phy-handle = <&sw2_port7_base_t1_phy>; + }; + + port@8 { + reg = <8>; + label = "trx10"; + phy-mode = "internal"; + phy-handle = <&sw2_port8_base_t1_phy>; + }; + + port@9 { + reg = <9>; + label = "trx11"; + phy-mode = "internal"; + phy-handle = <&sw2_port9_base_t1_phy>; + }; + + port@a { + reg = <10>; + label = "trx12"; + phy-mode = "internal"; + phy-handle = <&sw2_port10_base_t1_phy>; + }; + }; + + mdios { + #address-cells = <1>; + #size-cells = <0>; + + mdio@0 { + compatible = "nxp,sja1110-base-t1-mdio"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + sw2_port5_base_t1_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + + sw2_port6_base_t1_phy: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x2>; + }; + + sw2_port7_base_t1_phy: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x3>; + }; + + sw2_port8_base_t1_phy: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x4>; + }; + + sw2_port9_base_t1_phy: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x5>; + }; + + sw2_port10_base_t1_phy: ethernet-phy@6 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x6>; + }; + }; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; -- cgit From aeb78b1c05d60c1639e9ade9ff285ffc31bb3e8e Mon Sep 17 00:00:00 2001 From: Chester Lin Date: Wed, 8 Sep 2021 14:45:24 +0800 Subject: arm64: dts: add NXP S32G2 support Add an initial dtsi file for generic SoC features of NXP S32G2. Signed-off-by: Chester Lin Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 99 ++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi new file mode 100644 index 000000000000..53b18671deec --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * NXP S32G2 SoC family + * + * Copyright (c) 2021 SUSE LLC + */ + +#include + +/ { + compatible = "nxp,s32g2"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + next-level-cache = <&cluster0_l2>; + }; + + cpu2: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x100>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cpu3: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x101>; + enable-method = "psci"; + next-level-cache = <&cluster1_l2>; + }; + + cluster0_l2: l2-cache0 { + compatible = "cache"; + }; + + cluster1_l2: l2-cache1 { + compatible = "cache"; + }; + }; + + pmu { + compatible = "arm,cortex-a53-pmu"; + interrupts = ; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + }; + + firmware { + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0x80000000>; + + gic: interrupt-controller@50800000 { + compatible = "arm,gic-v3"; + reg = <0x50800000 0x10000>, + <0x50880000 0x80000>, + <0x50400000 0x2000>, + <0x50410000 0x2000>, + <0x50420000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + }; +}; -- cgit From 994f4e42ecc0a22ebcb9bf0dfde5ea8f4312c651 Mon Sep 17 00:00:00 2001 From: Chester Lin Date: Wed, 8 Sep 2021 14:45:25 +0800 Subject: arm64: dts: s32g2: add serial/uart support Add serial/uart support for NXP S32G2 based on the information provided by NXP's CodeAurora BSP. Signed-off-by: Larisa Grigore Signed-off-by: Chester Lin Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 53b18671deec..59ea8a25aa4c 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -3,6 +3,7 @@ * NXP S32G2 SoC family * * Copyright (c) 2021 SUSE LLC + * Copyright (c) 2017-2021 NXP */ #include @@ -84,6 +85,30 @@ #size-cells = <1>; ranges = <0 0 0 0x80000000>; + uart0: serial@401c8000 { + compatible = "nxp,s32g2-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x401c8000 0x3000>; + interrupts = ; + status = "disabled"; + }; + + uart1: serial@401cc000 { + compatible = "nxp,s32g2-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x401cc000 0x3000>; + interrupts = ; + status = "disabled"; + }; + + uart2: serial@402bc000 { + compatible = "nxp,s32g2-linflexuart", + "fsl,s32v234-linflexuart"; + reg = <0x402bc000 0x3000>; + interrupts = ; + status = "disabled"; + }; + gic: interrupt-controller@50800000 { compatible = "arm,gic-v3"; reg = <0x50800000 0x10000>, -- cgit From 3686673dc30d6d53b65568e43d21fb249820e1e6 Mon Sep 17 00:00:00 2001 From: Chester Lin Date: Wed, 8 Sep 2021 14:45:26 +0800 Subject: arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support Add initial device-trees of NXP S32G2's Evaluation Board (S32G-VNP-EVB) and Reference Design 2 Board (S32G-VNP-RDB2). Signed-off-by: Chester Lin Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/Makefile | 2 ++ arch/arm64/boot/dts/freescale/s32g274a-evb.dts | 26 ++++++++++++++++++++ arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 32 +++++++++++++++++++++++++ 3 files changed, 60 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-evb.dts create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index ecf74464705f..a14a6173b765 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -72,4 +72,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb +dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb +dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts new file mode 100644 index 000000000000..3aec05de0842 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 SUSE LLC + */ + +/dts-v1/; + +#include "s32g2.dtsi" + +/ { + model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)"; + compatible = "nxp,s32g274a-evb", "nxp,s32g2"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* UART (J58) to Micro USB port */ +&uart0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts new file mode 100644 index 000000000000..ed3f23babdca --- /dev/null +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2021 SUSE LLC + */ + +/dts-v1/; + +#include "s32g2.dtsi" + +/ { + model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)"; + compatible = "nxp,s32g274a-rdb2", "nxp,s32g2"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +/* UART (J2) to Micro USB port */ +&uart0 { + status = "okay"; +}; + +/* UART (J1) to Micro USB port */ +&uart1 { + status = "okay"; +}; -- cgit From 0c8bedf26f11c0780a19b506ef8f9e9cde0f0524 Mon Sep 17 00:00:00 2001 From: Chester Lin Date: Wed, 8 Sep 2021 14:45:27 +0800 Subject: arm64: dts: s32g2: add memory nodes for evb and rdb2 Add memory nodes for S32G-VNP-EVB and S32G-VNP-RDB2. Signed-off-by: Chester Lin Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/s32g274a-evb.dts | 8 ++++++++ arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts index 3aec05de0842..9118d8d2ee01 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (c) 2021 SUSE LLC + * Copyright (c) 2019-2021 NXP */ /dts-v1/; @@ -18,6 +19,13 @@ chosen { stdout-path = "serial0:115200n8"; }; + + /* 4GiB RAM */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>, + <0x8 0x80000000 0 0x80000000>; + }; }; /* UART (J58) to Micro USB port */ diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts index ed3f23babdca..e05ee854cdf5 100644 --- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts +++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-or-later OR MIT /* * Copyright (c) 2021 SUSE LLC + * Copyright (c) 2019-2021 NXP */ /dts-v1/; @@ -19,6 +20,13 @@ chosen { stdout-path = "serial0:115200n8"; }; + + /* 4GiB RAM */ + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0 0x80000000>, + <0x8 0x80000000 0 0x80000000>; + }; }; /* UART (J2) to Micro USB port */ -- cgit From b4751afb72299df0bc34588a61adeb717a6e1c58 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 31 Aug 2021 15:40:07 +0200 Subject: arm64: dts: ls1028a: move pixel clock pll into /soc Move it inside the /soc subnode because it is part of the CCSR space. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 343ecf0e8973..9a65a7118faa 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -80,13 +80,6 @@ clock-output-names = "phy_27m"; }; - dpclk: clock-controller@f1f0000 { - compatible = "fsl,ls1028a-plldig"; - reg = <0x0 0xf1f0000 0x0 0xffff>; - #clock-cells = <0>; - clocks = <&osc_27m>; - }; - firmware { optee: optee { compatible = "linaro,optee-tz"; @@ -926,6 +919,13 @@ status = "disabled"; }; + dpclk: clock-controller@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0x10000>; + #clock-cells = <0>; + clocks = <&osc_27m>; + }; + tmu: tmu@1f80000 { compatible = "fsl,qoriq-tmu"; reg = <0x0 0x1f80000 0x0 0x10000>; -- cgit From 7de87eae2d33983f12ef00879133c303424ab6b6 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 31 Aug 2021 15:40:08 +0200 Subject: arm64: dts: ls1028a: move Mali DP500 node into /soc Move it inside the /soc subnode because it is part of the CCSR space. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 41 +++++++++++++------------- 1 file changed, 21 insertions(+), 20 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 9a65a7118faa..92e4f004c1c2 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -793,6 +793,27 @@ clock-names = "wdog_clk", "apb_pclk"; }; + malidp0: display@f080000 { + compatible = "arm,mali-dp500"; + reg = <0x0 0xf080000 0x0 0x10000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "DE", "SE"; + clocks = <&dpclk>, + <&clockgen QORIQ_CLK_HWACCEL 2>, + <&clockgen QORIQ_CLK_HWACCEL 2>, + <&clockgen QORIQ_CLK_HWACCEL 2>; + clock-names = "pxlclk", "mclk", "aclk", "pclk"; + arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; + arm,malidp-arqos-value = <0xd000d000>; + + port { + dpi0_out: endpoint { + + }; + }; + }; + sai1: audio-controller@f100000 { #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; @@ -1139,24 +1160,4 @@ }; }; - malidp0: display@f080000 { - compatible = "arm,mali-dp500"; - reg = <0x0 0xf080000 0x0 0x10000>; - interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, - <0 223 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "DE", "SE"; - clocks = <&dpclk>, - <&clockgen QORIQ_CLK_HWACCEL 2>, - <&clockgen QORIQ_CLK_HWACCEL 2>, - <&clockgen QORIQ_CLK_HWACCEL 2>; - clock-names = "pxlclk", "mclk", "aclk", "pclk"; - arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; - arm,malidp-arqos-value = <0xd000d000>; - - port { - dp0_out: endpoint { - - }; - }; - }; }; -- cgit From 55ca18c0d906a88e874fdc70dd6ff4ed009c88a2 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 31 Aug 2021 15:40:09 +0200 Subject: arm64: dts: ls1028a: add Vivante GPU node Recently, support for this particular Vivante GC7000 GPU was added to the linux kernel. Add the corresponding device tree node. Signed-off-by: Michael Walle Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 92e4f004c1c2..876dea668a90 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -814,6 +814,17 @@ }; }; + gpu: gpu@f0c0000 { + compatible = "vivante,gc"; + reg = <0x0 0xf0c0000 0x0 0x10000>; + interrupts = ; + clocks = <&clockgen QORIQ_CLK_HWACCEL 2>, + <&clockgen QORIQ_CLK_HWACCEL 2>, + <&clockgen QORIQ_CLK_HWACCEL 2>; + clock-names = "core", "shader", "bus"; + #cooling-cells = <2>; + }; + sai1: audio-controller@f100000 { #sound-dai-cells = <0>; compatible = "fsl,vf610-sai"; -- cgit From 70293bea9290678d4b225215d669f189a33e7bcb Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 31 Aug 2021 15:40:11 +0200 Subject: arm64: dts: ls1028a: disable usb controller by default One of the last devices which are enabled by default are the USB controllers. Although the pins are not multi-function pins, some boards might not use USB at all. Apply the "disabled-by-default" style also for the USB controllers and enable the controllers in the actual device tree of the boards. Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 8 ++++++++ arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 8 ++++++++ arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 5 +++++ arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 ++ 4 files changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index a92ecb331cdc..2c6266991c38 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -309,3 +309,11 @@ &lpuart1 { status = "okay"; }; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index bfd14b64567e..f36f87858aef 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -335,3 +335,11 @@ &sata { status = "okay"; }; + +&usb0 { + status = "okay"; +}; + +&usb1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index d7b527272500..b0967b987f8a 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -287,6 +287,11 @@ status = "okay"; }; +&usb0 { + status = "okay"; +}; + &usb1 { dr_mode = "otg"; + status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index 876dea668a90..c10c84d9495d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -585,6 +585,7 @@ snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + status = "disabled"; }; usb1: usb@3110000 { @@ -595,6 +596,7 @@ snps,dis_rxdet_inp3_quirk; snps,quirk-frame-length-adjustment = <0x20>; snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + status = "disabled"; }; sata: sata@3200000 { -- cgit From 678338050635ee14542339344e887f41335287b9 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 31 Aug 2021 15:40:12 +0200 Subject: arm64: dts: ls1028a: move PHY nodes to MDIO controller Move the PHY nodes from the network controller to the dedicated MDIO controller. According to Vladimir Oltean direct MDIO access via the PF, that is when the PHY is put under the "mdio" subnode, is defeatured and in fact the latest reference manual isn't mentioning it anymore. Suggested-by: Vladimir Oltean Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Signed-off-by: Shawn Guo --- .../freescale/fsl-ls1028a-kontron-sl28-var1.dts | 58 ++++++++++------------ .../freescale/fsl-ls1028a-kontron-sl28-var2.dts | 17 ++----- .../freescale/fsl-ls1028a-kontron-sl28-var4.dts | 49 +++++++++--------- .../dts/freescale/fsl-ls1028a-kontron-sl28.dts | 21 ++++---- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 12 ++--- 5 files changed, 67 insertions(+), 90 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts index e8d31279b7a3..836a9b7d8263 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts @@ -8,7 +8,7 @@ * None of the four SerDes lanes are used by the module, instead they are * all led out to the carrier for customer use. * - * Copyright (C) 2020 Michael Walle + * Copyright (C) 2021 Michael Walle * */ @@ -21,43 +21,39 @@ compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a"; }; +&enetc_mdio_pf3 { + /* Delete unused phy node */ + /delete-node/ ethernet-phy@5; + + phy0: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = ; + qca,keep-pll-enabled; + vddio-supply = <&vddio>; + + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + vddh: vddh-regulator { + regulator-name = "VDDH"; + }; + }; +}; + &enetc_port0 { status = "disabled"; - /* - * Delete both the phy-handle to the old phy0 label as well as - * the mdio node with the old phy node with the old phy0 label. - */ + /* Delete the phy-handle to the old phy0 label */ /delete-property/ phy-handle; - /delete-node/ mdio; }; &enetc_port1 { phy-handle = <&phy0>; phy-connection-type = "rgmii-id"; status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - qca,clk-out-frequency = <125000000>; - qca,clk-out-strength = ; - qca,keep-pll-enabled; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-name = "VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - - vddh: vddh-regulator { - regulator-name = "VDDH"; - }; - }; - }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts index f6a79c8080d1..330e34f933a3 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dts @@ -5,7 +5,7 @@ * This is for the network variant 2 which has two ethernet ports. These * ports are connected to the internal switch. * - * Copyright (C) 2020 Michael Walle + * Copyright (C) 2021 Michael Walle * */ @@ -18,12 +18,6 @@ }; &enetc_mdio_pf3 { - phy0: ethernet-phy@5 { - reg = <0x5>; - eee-broken-1000t; - eee-broken-100tx; - }; - phy1: ethernet-phy@4 { reg = <0x4>; eee-broken-1000t; @@ -34,14 +28,11 @@ &enetc_port0 { status = "disabled"; /* - * In the base device tree the PHY was registered in the mdio - * subnode as it is PHY for this port. On this module this PHY - * is connected to a switch port instead and registered above. - * Therefore, delete the mdio subnode as well as the phy-handle - * property here. + * In the base device tree the PHY at address 5 was assigned for + * this port. On this module this PHY is connected to a switch + * port instead. Therefore, delete the phy-handle property here. */ /delete-property/ phy-handle; - /delete-node/ mdio; }; &enetc_port2 { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts index e65d1c477e2c..77ed0ebd2c75 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts @@ -5,7 +5,7 @@ * This is for the network variant 4 which has two ethernet ports. It * extends the base and provides one more port connected via RGMII. * - * Copyright (C) 2019 Michael Walle + * Copyright (C) 2021 Michael Walle * */ @@ -18,33 +18,30 @@ compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; }; -&enetc_port1 { - phy-handle = <&phy1>; - phy-connection-type = "rgmii-id"; - status = "okay"; +&enetc_mdio_pf3 { + phy1: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + qca,clk-out-frequency = <125000000>; + qca,clk-out-strength = ; + qca,keep-pll-enabled; + vddio-supply = <&vddio>; - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy1: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - qca,clk-out-frequency = <125000000>; - qca,clk-out-strength = ; - qca,keep-pll-enabled; - vddio-supply = <&vddio>; - - vddio: vddio-regulator { - regulator-name = "VDDIO"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; + vddio: vddio-regulator { + regulator-name = "VDDIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; - vddh: vddh-regulator { - regulator-name = "VDDH"; - }; + vddh: vddh-regulator { + regulator-name = "VDDH"; }; }; }; + +&enetc_port1 { + phy-handle = <&phy1>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index 2c6266991c38..b3e9c499e8b0 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -2,7 +2,7 @@ /* * Device Tree file for the Kontron SMARC-sAL28 board. * - * Copyright (C) 2019 Michael Walle + * Copyright (C) 2021 Michael Walle * */ @@ -80,22 +80,19 @@ status = "okay"; }; +&enetc_mdio_pf3 { + phy0: ethernet-phy@5 { + reg = <0x5>; + eee-broken-1000t; + eee-broken-100tx; + }; +}; + &enetc_port0 { phy-handle = <&phy0>; phy-connection-type = "sgmii"; managed = "in-band-status"; status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - phy0: ethernet-phy@5 { - reg = <0x5>; - eee-broken-1000t; - eee-broken-100tx; - }; - }; }; &esdhc { diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index b0967b987f8a..ea11b1eb01f8 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -197,6 +197,10 @@ }; &enetc_mdio_pf3 { + sgmii_phy0: ethernet-phy@2 { + reg = <0x2>; + }; + /* VSC8514 QSGMII quad PHY */ qsgmii_phy0: ethernet-phy@10 { reg = <0x10>; @@ -220,14 +224,6 @@ phy-connection-type = "sgmii"; managed = "in-band-status"; status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - sgmii_phy0: ethernet-phy@2 { - reg = <0x2>; - }; - }; }; &enetc_port2 { -- cgit From caa355c53ba4c3c643aca917b707fb6a3ff5e6fa Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Tue, 31 Aug 2021 15:40:13 +0200 Subject: arm64: dts: ls1028a: use phy-mode instead of phy-connection-type In linux both are identical, phy-mode is used more often, though. Also for the ls1028a both phy-connection-type and phy-mode was used, one for the enetc nodes and the other for the switch nodes. Unify them. But the main reason for this is that the device tree files can be shared with the u-boot ones; there the enetc driver only supports the "phy-mode" property. Suggested-by: Vladimir Oltean Signed-off-by: Michael Walle Reviewed-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 2 +- arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts index 836a9b7d8263..7cd29ab970d9 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dts @@ -54,6 +54,6 @@ &enetc_port1 { phy-handle = <&phy0>; - phy-connection-type = "rgmii-id"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts index 77ed0ebd2c75..9b5e92fb753e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dts @@ -42,6 +42,6 @@ &enetc_port1 { phy-handle = <&phy1>; - phy-connection-type = "rgmii-id"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts index b3e9c499e8b0..d74e738e4070 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dts @@ -90,7 +90,7 @@ &enetc_port0 { phy-handle = <&phy0>; - phy-connection-type = "sgmii"; + phy-mode = "sgmii"; managed = "in-band-status"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts index f36f87858aef..6e2a1da662fb 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts @@ -320,7 +320,7 @@ &enetc_port1 { phy-handle = <&qds_phy1>; - phy-connection-type = "rgmii-id"; + phy-mode = "rgmii-id"; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts index ea11b1eb01f8..7719f44bcaed 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts @@ -221,7 +221,7 @@ &enetc_port0 { phy-handle = <&sgmii_phy0>; - phy-connection-type = "sgmii"; + phy-mode = "sgmii"; managed = "in-band-status"; status = "okay"; }; -- cgit From 869f0ec048dc8fd88c0b2003373bd985795179fb Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Tue, 28 Sep 2021 14:21:54 -0500 Subject: arm64: dts: freescale: Fix 'interrupt-map' parent address cells The 'interrupt-map' in several Layerscape SoCs is malformed. The '#address-cells' size of the parent interrupt controller (the GIC) is not accounted for. Cc: Shawn Guo Cc: Li Yang Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring Acked-by: Li Yang Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 24 ++++++++++++------------ arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 24 ++++++++++++------------ arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++++++++++++------------ 3 files changed, 36 insertions(+), 36 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 605072317243..f891ef6a3754 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -241,18 +241,18 @@ interrupt-controller; reg = <0x14 4>; interrupt-map = - <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + <0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0xffffffff 0x0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 1282b61da8a5..3cb9c21d2775 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -293,18 +293,18 @@ interrupt-controller; reg = <0x14 4>; interrupt-map = - <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + <0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0xffffffff 0x0>; }; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index c4b1a59ba424..dc8661ebd1f6 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -680,18 +680,18 @@ interrupt-controller; reg = <0x14 4>; interrupt-map = - <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, - <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, - <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, - <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, - <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, - <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, - <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, - <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, - <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, - <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + <0 0 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <1 0 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <2 0 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <3 0 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <4 0 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <5 0 &gic 0 0 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, + <6 0 &gic 0 0 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, + <7 0 &gic 0 0 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <8 0 &gic 0 0 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <9 0 &gic 0 0 GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, + <10 0 &gic 0 0 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <11 0 &gic 0 0 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-map-mask = <0xffffffff 0x0>; }; }; -- cgit From 8fcea7be57365d32f98cefa9366cf4e37e597973 Mon Sep 17 00:00:00 2001 From: Vladimir Oltean Date: Wed, 29 Sep 2021 14:52:26 +0300 Subject: arm64: dts: ls1028a: mark internal links between Felix and ENETC as capable of flow control The internal Ethernet switch suffers from erratum A-050484 ("Ethernet flow control not functional on L2 switch NPI port when XFH is used"). XFH stands for "Extraction Frame Header" - which basically means the default "ocelot" DSA tagging protocol. However, the switch supports one other tagging protocol - "ocelot-8021q", and this is not subject to the erratum above. So describe the hardware ability to pass PAUSE frames in the device tree, and let the driver figure out whether it should use flow control on the CPU port or not, depending on whether the "ocelot" or "ocelot-8021q" tagging protocol is being used. Signed-off-by: Vladimir Oltean Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index c10c84d9495d..a13b998b2fbe 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1059,6 +1059,7 @@ fixed-link { speed = <2500>; full-duplex; + pause; }; }; @@ -1117,6 +1118,7 @@ fixed-link { speed = <2500>; full-duplex; + pause; }; }; @@ -1128,6 +1130,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; }; }; @@ -1142,6 +1145,7 @@ fixed-link { speed = <1000>; full-duplex; + pause; }; }; -- cgit From d39d4bb1531029e1b7373fabe790321d5cfcc58b Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:50 +0200 Subject: arm64: dts: imx8mm: add GPC node Add the DT node for the GPC, including all the PGC power domains, some of them are not fully functional yet, as they require interaction with the blk-ctrls to properly power up/down the peripherals. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 107 ++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 2f632e8ca388..83185b70dd46 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -7,6 +7,8 @@ #include #include #include +#include +#include #include #include "imx8mm-pinfunc.h" @@ -610,6 +612,111 @@ interrupts = ; #reset-cells = <1>; }; + + gpc: gpc@303a0000 { + compatible = "fsl,imx8mm-gpc"; + reg = <0x303a0000 0x10000>; + interrupts = ; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <3>; + + pgc { + #address-cells = <1>; + #size-cells = <0>; + + pgc_hsiomix: power-domain@0 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MM_CLK_USB_BUS>; + assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; + }; + + pgc_pcie: power-domain@1 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_hsiomix>; + clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>; + }; + + pgc_otg1: power-domain@2 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_hsiomix>; + }; + + pgc_otg2: power-domain@3 { + #power-domain-cells = <0>; + reg = ; + power-domains = <&pgc_hsiomix>; + }; + + pgc_gpumix: power-domain@4 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU_AHB>; + assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>, + <&clk IMX8MM_CLK_GPU_AHB>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, <400000000>; + }; + + pgc_gpu: power-domain@5 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU2D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + resets = <&src IMX8MQ_RESET_GPU_RESET>; + power-domains = <&pgc_gpumix>; + }; + + pgc_vpumix: power-domain@6 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>; + assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>; + resets = <&src IMX8MQ_RESET_VPU_RESET>; + }; + + pgc_vpu_g1: power-domain@7 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_vpu_g2: power-domain@8 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_vpu_h1: power-domain@9 { + #power-domain-cells = <0>; + reg = ; + }; + + pgc_dispmix: power-domain@10 { + #power-domain-cells = <0>; + reg = ; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>; + assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>, + <&clk IMX8MM_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>, + <&clk IMX8MM_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; + }; + + pgc_mipi: power-domain@11 { + #power-domain-cells = <0>; + reg = ; + }; + }; + }; }; aips2: bus@30400000 { -- cgit From 01df28d8085923fb1dc3c9fcb2a7676c523c66c5 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:51 +0200 Subject: arm64: dts: imx8mm: put USB controllers into power-domains Now that we have support for the power domain controller on the i.MX8MM we can put the USB controllers in their respective power domains to allow them to power down the PHY when possible. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 83185b70dd46..d8c53ffb5fff 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1078,6 +1078,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop1>; fsl,usbmisc = <&usbmisc1 0>; + power-domains = <&pgc_otg1>; status = "disabled"; }; @@ -1097,6 +1098,7 @@ assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>; phys = <&usbphynop2>; fsl,usbmisc = <&usbmisc2 0>; + power-domains = <&pgc_otg2>; status = "disabled"; }; -- cgit From 4523be8e46beb8a0992f31f53218d3f9ec267816 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Sat, 2 Oct 2021 02:59:52 +0200 Subject: arm64: dts: imx8mm: Add GPU nodes for 2D and 3D core According to the documents, the i.MX8M-Mini features a GC320 and a GCNanoUltra GPU core. Etnaviv detects them as: etnaviv-gpu 38000000.gpu: model: GC600, revision: 4653 etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341 This seems to work fine more or less without any changes to the HWDB, which still might be needed in the future to correct some features, etc. [lst]: Added power domains and switched clock assignments to the new clock defines used for the composite clocks, instead of relying on the backwards compat defines. Signed-off-by: Frieder Schrempf Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index d8c53ffb5fff..6009e54266f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1139,6 +1139,37 @@ status = "disabled"; }; + gpu_3d: gpu@38000000 { + compatible = "vivante,gc"; + reg = <0x38000000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>, + <&clk IMX8MM_CLK_GPU3D_ROOT>; + clock-names = "reg", "bus", "core", "shader"; + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-rates = <0>, <1000000000>; + power-domains = <&pgc_gpu>; + }; + + gpu_2d: gpu@38008000 { + compatible = "vivante,gc"; + reg = <0x38008000 0x8000>; + interrupts = ; + clocks = <&clk IMX8MM_CLK_GPU_AHB>, + <&clk IMX8MM_CLK_GPU_BUS_ROOT>, + <&clk IMX8MM_CLK_GPU2D_ROOT>; + clock-names = "reg", "bus", "core"; + assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-rates = <0>, <1000000000>; + power-domains = <&pgc_gpu>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ -- cgit From 2604c5cafb9613921adf4817156728e51b5b6b77 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:53 +0200 Subject: arm64: dts: imx8mm: add VPU blk-ctrl Add the DT node for the VPU blk-ctrl. With this in place the VPU power domains are fully functional. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 6009e54266f0..f4a97bd8b7ad 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1170,6 +1170,19 @@ power-domains = <&pgc_gpu>; }; + vpu_blk_ctrl: blk-ctrl@38330000 { + compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; + reg = <0x38330000 0x100>; + power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, + <&pgc_vpu_g2>, <&pgc_vpu_h1>; + power-domain-names = "bus", "g1", "g2", "h1"; + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>, + <&clk IMX8MM_CLK_VPU_G2_ROOT>, + <&clk IMX8MM_CLK_VPU_H1_ROOT>; + clock-names = "g1", "g2", "h1"; + #power-domain-cells = <1>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, /* GIC Dist */ -- cgit From d2fefef92e2dcb5e1c18844ea51a14cbc1d5c6e9 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Sat, 2 Oct 2021 02:59:54 +0200 Subject: arm64: dts: imx8mm: add DISP blk-ctrl Add the DT node for the DISP blk-ctrl. With this in place the display/mipi power domains are fully functional. Signed-off-by: Lucas Stach Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index f4a97bd8b7ad..c2f3f118f82e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -1068,6 +1068,33 @@ #size-cells = <1>; ranges = <0x32c00000 0x32c00000 0x400000>; + disp_blk_ctrl: blk-ctrl@32e28000 { + compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon"; + reg = <0x32e28000 0x100>; + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, + <&pgc_dispmix>, <&pgc_mipi>, + <&pgc_mipi>; + power-domain-names = "bus", "csi-bridge", + "lcdif", "mipi-dsi", + "mipi-csi"; + clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_CSI1_ROOT>, + <&clk IMX8MM_CLK_DISP_AXI_ROOT>, + <&clk IMX8MM_CLK_DISP_APB_ROOT>, + <&clk IMX8MM_CLK_DISP_ROOT>, + <&clk IMX8MM_CLK_DSI_CORE>, + <&clk IMX8MM_CLK_DSI_PHY_REF>, + <&clk IMX8MM_CLK_CSI1_CORE>, + <&clk IMX8MM_CLK_CSI1_PHY_REF>; + clock-names = "csi-bridge-axi","csi-bridge-apb", + "csi-bridge-core", "lcdif-axi", + "lcdif-apb", "lcdif-pix", + "dsi-pclk", "dsi-ref", + "csi-aclk", "csi-pclk"; + #power-domain-cells = <1>; + }; + usbotg1: usb@32e40000 { compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb"; reg = <0x32e40000 0x200>; -- cgit From 315e7b884190a6c9c28e95ad3b724dde9e922b99 Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Thu, 30 Sep 2021 17:56:30 +0200 Subject: arm64: dts: imx8mm-kontron: Fix reset delays for ethernet PHY According to the datasheet the VSC8531 PHY expects a reset pulse of 100 ns and a delay of 15 ms after the reset has been deasserted. Set the matching values in the devicetree. Reported-by: Heiko Thiery Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts index d17abb515835..2f24f80afb2a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -121,8 +121,8 @@ ethphy: ethernet-phy@0 { reg = <0>; - reset-assert-us = <100>; - reset-deassert-us = <100>; + reset-assert-us = <1>; + reset-deassert-us = <15000>; reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; }; }; -- cgit From ca4fd34e8603c08ac96d24c42fd8657f1ff9ad86 Mon Sep 17 00:00:00 2001 From: Martin Kepplinger Date: Tue, 5 Oct 2021 15:48:56 +0200 Subject: arm64: dts: imx8mq-librem5: add reset gpio to mantix panel description Add the missing description for the reset gpio to the panels DT description. Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 3f7524400a63..0609b591ec5a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1010,6 +1010,7 @@ vddi-supply = <®_lcd_1v8>; backlight = <&backlight_dsi>; reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>; + mantix,tp-rstn-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; port { panel_in: endpoint { -- cgit From 1f8359d4a242c2f678541f847525b721514c530b Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Tue, 5 Oct 2021 15:48:57 +0200 Subject: arm64: dts: imx8mq-librem5: Fix led_r and led_g pinctrl assignments Fix wrong pinctrl assignments. Signed-off-by: Sebastian Krzyszkowiak Suggested-by: Eric Kuzmenko Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 0609b591ec5a..95bbaa108805 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1056,13 +1056,13 @@ &pwm3 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_g>; + pinctrl-0 = <&pinctrl_led_r>; status = "okay"; }; &pwm4 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_led_r>; + pinctrl-0 = <&pinctrl_led_g>; status = "okay"; }; -- cgit From 924025e5eeb961cd1621f648a7ee8e2cd74f429f Mon Sep 17 00:00:00 2001 From: Guido Günther Date: Tue, 5 Oct 2021 15:48:58 +0200 Subject: arm64: dts: imx8mq-librem5: wire up the wifi regulator MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Connect the wifi power regulator to the corresponding GPIO. Signed-off-by: Guido Günther Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 95bbaa108805..9a309b1d0a90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -138,9 +138,14 @@ reg_wifi_3v3: regulator-wifi-3v3 { compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wifi_pwr>; regulator-name = "3V3_WIFI"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; + gpio = <&gpio3 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vdd_3v3>; }; sound { @@ -638,6 +643,13 @@ >; }; + pinctrl_wifi_pwr: wifipwrgrp { + fsl,pins = < + /* WIFI3V3_EN */ + MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x83 + >; + }; + pinctrl_wdog: wdoggrp { fsl,pins = < /* nWDOG */ -- cgit From c3817595d6d026711dcda64908b1b9830e55633b Mon Sep 17 00:00:00 2001 From: Angus Ainslie Date: Tue, 5 Oct 2021 15:48:59 +0200 Subject: arm64: dts: imx8mq-librem5: delay the startup of the SDIO The redpine wifi card takes some time to wake up. Wait for it. Signed-off-by: Angus Ainslie Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 9a309b1d0a90..7a09312f31c4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1212,6 +1212,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <4>; vmmc-supply = <®_wifi_3v3>; + post-power-on-delay-ms = <1000>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; disable-wp; cap-sdio-irq; -- cgit From 2344af0d5b58972c8ee3323923ed4167a9922b04 Mon Sep 17 00:00:00 2001 From: Angus Ainslie Date: Tue, 5 Oct 2021 15:49:00 +0200 Subject: arm64: dts: imx8mq-librem5: add power sequencing for M.2 cards Some wifi cards need reset asserted until after the power supplies have been enabled. So wire up the W_DISABLE signal for the SDIO port (WIFI_REG_ON net) and the BT_REG_ON net to use it for power sequencing. Signed-off-by: Angus Ainslie Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 7a09312f31c4..396eb4434229 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -198,6 +198,14 @@ }; }; + usdhc2_pwrseq: pwrseq { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bt>, <&pinctrl_wifi_disable>; + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>, + <&gpio4 29 GPIO_ACTIVE_HIGH>; + }; + bm818_codec: sound-wwan-codec { compatible = "broadmobi,bm818", "option,gtm601"; #sound-dai-cells = <0>; @@ -312,6 +320,13 @@ >; }; + pinctrl_bt: btgrp { + fsl,pins = < + /* BT_REG_ON */ + MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x83 + >; + }; + pinctrl_charger_in: chargeringrp { fsl,pins = < /* CHRG_INT */ @@ -643,6 +658,13 @@ >; }; + pinctrl_wifi_disable: wifidisablegrp { + fsl,pins = < + /* WIFI_REG_ON */ + MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x83 + >; + }; + pinctrl_wifi_pwr: wifipwrgrp { fsl,pins = < /* WIFI3V3_EN */ @@ -1212,6 +1234,7 @@ pinctrl-2 = <&pinctrl_usdhc2_200mhz>; bus-width = <4>; vmmc-supply = <®_wifi_3v3>; + mmc-pwrseq = <&usdhc2_pwrseq>; post-power-on-delay-ms = <1000>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; disable-wp; -- cgit From 09d255f0beb5370440e75a6bf7872f56b26ab4c9 Mon Sep 17 00:00:00 2001 From: Angus Ainslie Date: Tue, 5 Oct 2021 15:49:01 +0200 Subject: arm64: dts: imx8mq-librem5: Limit the max sdio frequency This is needed for the 1LV Cyress WiFi module to probe correctly. It also helps improve GNSS sensitivity. Signed-off-by: Angus Ainslie Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 396eb4434229..d86486fd659d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -1237,6 +1237,7 @@ mmc-pwrseq = <&usdhc2_pwrseq>; post-power-on-delay-ms = <1000>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + max-frequency = <50000000>; disable-wp; cap-sdio-irq; keep-power-in-suspend; -- cgit From fea0fd097c4f3b7436bb3ef7f397d0f0fee86c2f Mon Sep 17 00:00:00 2001 From: Sebastian Krzyszkowiak Date: Tue, 5 Oct 2021 15:49:02 +0200 Subject: arm64: dts: imx8mq-librem5: set debounce interval of volume buttons to 50ms The default of 5ms is too low. Signed-off-by: Sebastian Krzyszkowiak Signed-off-by: Martin Kepplinger Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index d86486fd659d..60d47c71499b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -40,12 +40,14 @@ label = "VOL_DOWN"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; linux,code = ; + debounce-interval = <50>; }; vol-up { label = "VOL_UP"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; linux,code = ; + debounce-interval = <50>; }; }; -- cgit From 7973009235e2d2b47ed0c6232d4eb202a682d2ad Mon Sep 17 00:00:00 2001 From: Tim Harvey Date: Wed, 6 Oct 2021 08:38:36 -0700 Subject: arm64: dts: imx8mm-venice-gw7901.dts: disable pgc_gpumix Since commit b21269b12e48 ("arm64: dts: imx8mm: add GPC node") the GW7901 will hang during kernel init because it does not power the unused GPU voltage rails on the IMX8MM. Disable pgc_gpumix to work around this. We also disable the GPU devices that depend on the gpumix power domain and pgc_gpu to avoid them staying in a probe deferred state forever. Additionally as the MIPI voltage rail is also not connected on this board we disable pgc_mipi and disp_blk_ctrl. Signed-off-by: Tim Harvey Reviewed-by: Lucas Stach Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-venice-gw7901.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index bafd5c8ea4e2..21c546c4628d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -255,6 +255,10 @@ }; }; +&disp_blk_ctrl { + status = "disabled"; +}; + &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi1>; @@ -282,6 +286,14 @@ }; }; +&gpu_2d { + status = "disabled"; +}; + +&gpu_3d { + status = "disabled"; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -632,6 +644,18 @@ status = "okay"; }; +&pgc_gpu { + status = "disabled"; +}; + +&pgc_gpumix { + status = "disabled"; +}; + +&pgc_mipi { + status = "disabled"; +}; + &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>; -- cgit From ec1e91d400bf21def54c441552bdf2976ce36e3b Mon Sep 17 00:00:00 2001 From: Frieder Schrempf Date: Fri, 15 Oct 2021 14:48:35 +0200 Subject: arm64: dts: imx8mm-kontron: Add support for ultra high speed modes on SD card In order to use ultra high speed modes (UHS) on the SD card slot, we add matching pinctrls and fix the voltage switching for LDO5 of the PMIC, by providing the SD_VSEL pin as GPIO to the PMIC driver. Signed-off-by: Frieder Schrempf Signed-off-by: Shawn Guo --- .../boot/dts/freescale/imx8mm-kontron-n801x-s.dts | 28 +++++++++++++++++++++- .../dts/freescale/imx8mm-kontron-n801x-som.dtsi | 2 ++ 2 files changed, 29 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts index 2f24f80afb2a..fa43e0989b90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-s.dts @@ -189,8 +189,10 @@ }; &usdhc2 { - pinctrl-names = "default"; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; vmmc-supply = <®_vdd_3v3>; vqmmc-supply = <®_nvcc_sd>; cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; @@ -319,4 +321,28 @@ MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 >; }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x019 + >; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi index 5a2805c51361..823814e991a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-kontron-n801x-som.dtsi @@ -86,6 +86,7 @@ pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; regulators { reg_vdd_soc: BUCK1 { @@ -225,6 +226,7 @@ pinctrl_pmic: pmicgrp { fsl,pins = < MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x141 + MX8MM_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x141 >; }; -- cgit