From a34b42f8690ce2b8360971ca5b886786ee1781af Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Fri, 24 Jun 2022 11:00:55 +0200 Subject: ARM: dts: stm32: fix pwr regulators references to use scmi Fixes stm32mp15*-scmi DTS files introduced in [1] to also access PWR regulators through SCMI service. This is needed since enabling secure only access to RCC clock and reset controllers also enables secure access only on PWR voltage regulators reg11, reg18 and usb33 hence these must also be accessed through SCMI Voltage Domain protocol. This change applies on commit [2] that already corrects issues from commit [1]. Cc: Alexandre Torgue Link: [1] https://lore.kernel.org/linux-arm-kernel/20220422150952.20587-7-alexandre.torgue@foss.st.com Link: [2] https://lore.kernel.org/linux-arm-kernel/20220613071920.5463-1-alexandre.torgue@foss.st.com Signed-off-by: Etienne Carriere Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-scmi.dtsi | 52 ++++++++++++++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts | 1 + arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts | 1 + 3 files changed, 54 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi index e90cf3acd0b3..d2afb6667479 100644 --- a/arch/arm/boot/dts/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/stm32mp15-scmi.dtsi @@ -27,6 +27,37 @@ reg = <0x16>; #reset-cells = <1>; }; + + scmi_voltd: protocol@17 { + reg = <0x17>; + + scmi_reguls: regulators { + #address-cells = <1>; + #size-cells = <0>; + + scmi_reg11: reg11@0 { + reg = <0>; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + scmi_reg18: reg18@1 { + voltd-name = "reg18"; + reg = <1>; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + scmi_usb33: usb33@2 { + reg = <2>; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; }; }; @@ -45,3 +76,24 @@ }; }; }; + +®11 { + status = "disabled"; +}; + +®18 { + status = "disabled"; +}; + +&usb33 { + status = "disabled"; +}; + +&usbotg_hs { + usb33d-supply = <&scmi_usb33>; +}; + +&usbphyc { + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts index 03226a596904..97e4f94b0a24 100644 --- a/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts @@ -35,6 +35,7 @@ }; &dsi { + phy-dsi-supply = <&scmi_reg18>; clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts index 7842384ddbe4..3b9dd6f4ccc9 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts @@ -36,6 +36,7 @@ }; &dsi { + phy-dsi-supply = <&scmi_reg18>; clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; }; -- cgit From 78ece8cce1ba0c3f3e5a7c6c1b914b3794f04c44 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Fri, 24 Jun 2022 11:27:13 +0200 Subject: ARM: dts: stm32: use the correct clock source for CEC on stm32mp151 The peripheral clock of CEC is not LSE but CEC. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 7fdc324b3cf9..c50f38f539f2 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -565,7 +565,7 @@ compatible = "st,stm32-cec"; reg = <0x40016000 0x400>; interrupts = ; - clocks = <&rcc CEC_K>, <&clk_lse>; + clocks = <&rcc CEC_K>, <&rcc CEC>; clock-names = "cec", "hdmi-cec"; status = "disabled"; }; -- cgit From cfd7ea394cd3b70ba4d9d87ee7b88e37459036b0 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Fri, 24 Jun 2022 11:27:14 +0200 Subject: ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board LSE clock is provided by SCMI. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts | 4 ++++ arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts index 36371d6ed660..e539cc80bef8 100644 --- a/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts @@ -29,6 +29,10 @@ clocks = <&scmi_clk CK_SCMI_MPU>; }; +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + &gpioz { clocks = <&scmi_clk CK_SCMI_GPIOZ>; }; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts index c1a79272c068..9cf0a44d2f47 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts @@ -34,6 +34,10 @@ resets = <&scmi_reset RST_SCMI_CRYP1>; }; +&dsi { + clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + &gpioz { clocks = <&scmi_clk CK_SCMI_GPIOZ>; }; -- cgit From bf74181e75c93a1b2b000ebf3c8b4c8c17cd59da Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Fri, 24 Jun 2022 11:27:15 +0200 Subject: ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI Delete the node fixed clock managed by secure world with SCMI. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-scmi.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/stm32mp15-scmi.dtsi index d2afb6667479..543f24c2f4f6 100644 --- a/arch/arm/boot/dts/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/stm32mp15-scmi.dtsi @@ -97,3 +97,9 @@ vdda1v1-supply = <&scmi_reg11>; vdda1v8-supply = <&scmi_reg18>; }; + +/delete-node/ &clk_hse; +/delete-node/ &clk_hsi; +/delete-node/ &clk_lse; +/delete-node/ &clk_lsi; +/delete-node/ &clk_csi; -- cgit From 1d0c1aadf1fd9f3de95d1532b3651e8634546e71 Mon Sep 17 00:00:00 2001 From: Fabrice Gasnier Date: Tue, 21 Jun 2022 10:45:09 +0200 Subject: ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15 The USBH composed of EHCI and OHCI controllers needs the PHY clock to be initialized first, before enabling (gating) them. The reverse is also required when going to suspend. So, add USBPHY clock as 1st entry in both controllers, so the USBPHY PLL gets enabled 1st upon controller init. Upon suspend/resume, this also makes the clock to be disabled/re-enabled in the correct order. This fixes some IRQ storm conditions seen when going to low-power, due to PHY PLL being disabled before all clocks are cleanly gated. Fixes: 949a0c0dec85 ("ARM: dts: stm32: add USB Host (USBH) support to stm32mp157c") Fixes: db7be2cb87ae ("ARM: dts: stm32: use usbphyc ck_usbo_48m as USBH OHCI clock on stm32mp151") Signed-off-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index c50f38f539f2..e04dda5ddd95 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1474,7 +1474,7 @@ usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; - clocks = <&rcc USBH>, <&usbphyc>; + clocks = <&usbphyc>, <&rcc USBH>; resets = <&rcc USBH_R>; interrupts = ; status = "disabled"; @@ -1483,7 +1483,7 @@ usbh_ehci: usb@5800d000 { compatible = "generic-ehci"; reg = <0x5800d000 0x1000>; - clocks = <&rcc USBH>; + clocks = <&usbphyc>, <&rcc USBH>; resets = <&rcc USBH_R>; interrupts = ; companion = <&usbh_ohci>; -- cgit From 7d9802bb0e34f118375937c6caa94818416c865a Mon Sep 17 00:00:00 2001 From: Fabien Dessenne Date: Tue, 3 May 2022 16:56:06 +0200 Subject: ARM: dts: stm32: remove the IPCC "wakeup" IRQ on stm32mp151 The stm32 ipcc mailbox driver supports only two interrupts (rx and tx), so remove the unsupported "wakeup" one. Note that the EXTI interrupt 61 has two roles : it is hierarchically linked to the GIC IPCC "rx" interrupt, and it acts as a wakeup source. Signed-off-by: Fabien Dessenne Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index e04dda5ddd95..742fdeeff4b6 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1117,10 +1117,9 @@ reg = <0x4c001000 0x400>; st,proc-id = <0>; interrupts-extended = - <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, - <&exti 61 1>; - interrupt-names = "rx", "tx", "wakeup"; + <&exti 61 1>, + <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "rx", "tx"; clocks = <&rcc IPCC>; wakeup-source; status = "disabled"; -- cgit From 1748c5c13e1586d3a359334f959626ba0f760fa5 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 4 May 2022 14:49:45 +0200 Subject: ARM: dts: stm32: Move DHCOR BUCK3 VDD 2V9 adjustment to 1V8 DTSI The Buck3 on DHCOR is used to supply IO voltage. It can output either 3V3 in the default DHCOR configuration, or 2V9 in case of AV96 DHCOR variant which has extra Empirion DCDC converter in front of the 1V8 IO supply, or outright 1V8 in case of 1V8 IO DHCOR without the Empirion DCDC converter. The 2V9 mode in case of AV96 DHCOR variant is used to reduce unnecessarily high input voltage to the Empirion DCDC converter, so move it into matching DTSI to stop confusing users. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi | 5 +++++ arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi index 75172314d7af..9937b28548c2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-io1v8.dtsi @@ -18,6 +18,11 @@ }; }; +&vdd { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; +}; + &pwr_regulators { vdd-supply = <&vdd_io>; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index 6336c3ca0f0e..134a798ad3f2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -119,8 +119,8 @@ vdd: buck3 { regulator-name = "vdd"; - regulator-min-microvolt = <2900000>; - regulator-max-microvolt = <2900000>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; regulator-always-on; regulator-initial-mode = <0>; regulator-over-current-protection; -- cgit From 95a73a50da9b0590c20010b64479d1736c95532b Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 26 May 2022 22:36:32 +0200 Subject: ARM: dts: stm32: adjust whitespace around '=' on MCU boards Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32429i-eval.dts | 8 ++++---- arch/arm/boot/dts/stm32h743.dtsi | 4 ++-- arch/arm/boot/dts/stm32h743i-disco.dts | 8 ++++---- arch/arm/boot/dts/stm32h743i-eval.dts | 8 ++++---- arch/arm/boot/dts/stm32h750i-art-pi.dts | 8 ++++---- 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 0d98aca01736..3de0e9dbe030 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -251,10 +251,10 @@ &mac { status = "okay"; - pinctrl-0 = <ðernet_mii>; - pinctrl-names = "default"; - phy-mode = "mii"; - phy-handle = <&phy1>; + pinctrl-0 = <ðernet_mii>; + pinctrl-names = "default"; + phy-mode = "mii"; + phy-handle = <&phy1>; mdio0 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 91dde07a38ba..2059593da21d 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -375,7 +375,7 @@ arm,primecell-periphid = <0x10153180>; reg = <0x52007000 0x1000>; interrupts = <49>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC1_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>; @@ -389,7 +389,7 @@ arm,primecell-periphid = <0x10153180>; reg = <0x48022400 0x400>; interrupts = <124>; - interrupt-names = "cmd_irq"; + interrupt-names = "cmd_irq"; clocks = <&rcc SDMMC2_CK>; clock-names = "apb_pclk"; resets = <&rcc STM32H7_AHB2_RESET(SDMMC2)>; diff --git a/arch/arm/boot/dts/stm32h743i-disco.dts b/arch/arm/boot/dts/stm32h743i-disco.dts index 59e01ce10318..2b452883a708 100644 --- a/arch/arm/boot/dts/stm32h743i-disco.dts +++ b/arch/arm/boot/dts/stm32h743i-disco.dts @@ -77,10 +77,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/stm32h743i-eval.dts b/arch/arm/boot/dts/stm32h743i-eval.dts index 38cc7faf6884..5c5d8059bdc7 100644 --- a/arch/arm/boot/dts/stm32h743i-eval.dts +++ b/arch/arm/boot/dts/stm32h743i-eval.dts @@ -115,10 +115,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; diff --git a/arch/arm/boot/dts/stm32h750i-art-pi.dts b/arch/arm/boot/dts/stm32h750i-art-pi.dts index 9bb73bb61901..f3e70d3b65ac 100644 --- a/arch/arm/boot/dts/stm32h750i-art-pi.dts +++ b/arch/arm/boot/dts/stm32h750i-art-pi.dts @@ -126,10 +126,10 @@ &mac { status = "disabled"; - pinctrl-0 = <ðernet_rmii>; - pinctrl-names = "default"; - phy-mode = "rmii"; - phy-handle = <&phy0>; + pinctrl-0 = <ðernet_rmii>; + pinctrl-names = "default"; + phy-mode = "rmii"; + phy-handle = <&phy0>; mdio0 { #address-cells = <1>; -- cgit From b2082d28d8c63678b80bf08e79b484c8982793f8 Mon Sep 17 00:00:00 2001 From: Leonard Göhrs Date: Fri, 3 Jun 2022 11:44:20 +0200 Subject: ARM: dts: stm32: fix missing internally connected voltage regulator for OSD32MP1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the OSD32MP1 Power System overview[1] ldo3's input is always internally connected to vdd_ddr. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Leonard Göhrs Reviewed-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-osd32.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi index 6706d8311a66..e997c4953fd1 100644 --- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -78,6 +78,7 @@ compatible = "st,stpmic1-regulators"; ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; ldo6-supply = <&v3v3>; pwr_sw1-supply = <&bst_out>; -- cgit From ef4ea690c5d75685592d687e1bfe0466808de246 Mon Sep 17 00:00:00 2001 From: Leonard Göhrs Date: Fri, 3 Jun 2022 11:44:21 +0200 Subject: ARM: dts: stm32: correct vcc-supply for eeprom on stm32mp15xx-osd32 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to the OSD32MP1 Power System overview[1] the EEPROM is connected to the VDD line and not to some single-purpose fixed regulator. Set the EEPROM supply according to the diagram to eliminate this parent-less regulator. [1]: https://octavosystems.com/app_notes/osd32mp1-power-system-overview/#connections Signed-off-by: Leonard Göhrs Acked-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-osd32.dtsi | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi index e997c4953fd1..935b7084b5a2 100644 --- a/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-osd32.dtsi @@ -50,12 +50,6 @@ no-map; }; }; - - reg_sip_eeprom: regulator_eeprom { - compatible = "regulator-fixed"; - regulator-name = "sip_eeprom"; - regulator-always-on; - }; }; &i2c4 { @@ -204,7 +198,7 @@ sip_eeprom: eeprom@50 { compatible = "atmel,24c32"; - vcc-supply = <®_sip_eeprom>; + vcc-supply = <&vdd>; reg = <0x50>; }; }; -- cgit From f3af33a8ee11a8067f8ef757f4d66451552ab16a Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Mon, 13 Jun 2022 11:34:19 +0200 Subject: dt-bindings: rcc: stm32: select the "secure" path for stm32mp13 Like for stm32mp15, when stm32 RCC node is used to interact with a secure context (using clock SCMI protocol), a different path has to be used for yaml verification. Signed-off-by: Alexandre Torgue Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml index f8c474227807..242fe922b035 100644 --- a/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml +++ b/Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml @@ -78,6 +78,7 @@ if: contains: enum: - st,stm32mp1-rcc-secure + - st,stm32mp13-rcc then: properties: clocks: -- cgit From 63058bfbdaf4c59cd5883d982a5a620471b7af52 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Wed, 23 Feb 2022 10:16:06 +0100 Subject: ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP13 Enable optee and SCMI clocks support. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index f9ebc47e6421..edbc602d2057 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -27,6 +27,31 @@ interrupt-parent = <&intc>; }; + firmware { + optee { + method = "smc"; + compatible = "linaro,optee-tz"; + }; + + scmi: scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + shmem = <&scmi_shm>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + clocks { clk_axi: clk-axi { #clock-cells = <0>; @@ -113,6 +138,19 @@ interrupt-parent = <&intc>; ranges; + scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi_shm: scmi-sram@0 { + compatible = "arm,scmi-shmem"; + reg = <0 0x80>; + }; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; -- cgit From f95634becdad3fecc01310a45bd54497c64a13c9 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Wed, 23 Feb 2022 10:18:19 +0100 Subject: ARM: dts: stm32: add RCC on STM32MP13x SoC family Enables Reset and Clocks Controller on STM32MP13 Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp131.dtsi | 116 +++++++++++++------------------------ arch/arm/boot/dts/stm32mp133.dtsi | 4 +- arch/arm/boot/dts/stm32mp13xc.dtsi | 3 +- arch/arm/boot/dts/stm32mp13xf.dtsi | 3 +- 4 files changed, 47 insertions(+), 79 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index edbc602d2057..3a921db23e9f 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -4,6 +4,8 @@ * Author: Alexandre Torgue for STMicroelectronics. */ #include +#include +#include / { #address-cells = <1>; @@ -52,62 +54,6 @@ }; }; - clocks { - clk_axi: clk-axi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <266500000>; - }; - - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_pclk3: clk-pclk3 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <104438965>; - }; - - clk_pclk4: clk-pclk4 { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <133250000>; - }; - - clk_pll4_p: clk-pll4_p { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <50000000>; - }; - - clk_pll4_r: clk-pll4_r { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <99000000>; - }; - - clk_rtc_k: clk-rtc-k { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - }; - intc: interrupt-controller@a0021000 { compatible = "arm,cortex-a7-gic"; #interrupt-cells = <3>; @@ -155,7 +101,8 @@ compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; interrupts = ; - clocks = <&clk_hsi>; + clocks = <&rcc UART4_K>; + resets = <&rcc UART4_R>; status = "disabled"; }; @@ -170,7 +117,8 @@ , , ; - clocks = <&clk_pclk4>; + clocks = <&rcc DMA1>; + resets = <&rcc DMA1_R>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; @@ -187,7 +135,8 @@ , , ; - clocks = <&clk_pclk4>; + clocks = <&rcc DMA2>; + resets = <&rcc DMA2_R>; #dma-cells = <4>; st,mem2mem; dma-requests = <8>; @@ -196,13 +145,27 @@ dmamux1: dma-router@48002000 { compatible = "st,stm32h7-dmamux"; reg = <0x48002000 0x40>; - clocks = <&clk_pclk4>; + clocks = <&rcc DMAMUX1>; + resets = <&rcc DMAMUX1_R>; #dma-cells = <3>; dma-masters = <&dma1 &dma2>; dma-requests = <128>; dma-channels = <16>; }; + rcc: rcc@50000000 { + compatible = "st,stm32mp13-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + clock-names = "hse", "hsi", "csi", "lse", "lsi"; + clocks = <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; + }; + exti: interrupt-controller@5000d000 { compatible = "st,stm32mp13-exti", "syscon"; interrupt-controller; @@ -213,14 +176,14 @@ syscfg: syscon@50020000 { compatible = "st,stm32mp157-syscfg", "syscon"; reg = <0x50020000 0x400>; - clocks = <&clk_pclk3>; + clocks = <&rcc SYSCFG>; }; mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; interrupts = ; - clocks = <&clk_pclk4>; + clocks = <&rcc MDMA>; #dma-cells = <5>; dma-channels = <32>; dma-requests = <48>; @@ -232,8 +195,9 @@ reg = <0x58005000 0x1000>, <0x58006000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; - clocks = <&clk_pll4_p>; + clocks = <&rcc SDMMC1_K>; clock-names = "apb_pclk"; + resets = <&rcc SDMMC1_R>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; @@ -246,8 +210,9 @@ reg = <0x58007000 0x1000>, <0x58008000 0x1000>; interrupts = ; interrupt-names = "cmd_irq"; - clocks = <&clk_pll4_p>; + clocks = <&rcc SDMMC2_K>; clock-names = "apb_pclk"; + resets = <&rcc SDMMC2_R>; cap-sd-highspeed; cap-mmc-highspeed; max-frequency = <130000000>; @@ -257,7 +222,7 @@ iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; - clocks = <&clk_pclk4>, <&clk_lsi>; + clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; }; @@ -266,7 +231,8 @@ compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&clk_pclk4>, <&clk_rtc_k>; + clocks = <&scmi_clk CK_SCMI_RTCAPB>, + <&scmi_clk CK_SCMI_RTC>; clock-names = "pclk", "rtc_ck"; status = "disabled"; }; @@ -307,7 +273,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOA>; st,bank-name = "GPIOA"; ngpios = <16>; gpio-ranges = <&pinctrl 0 0 16>; @@ -319,7 +285,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x1000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOB>; st,bank-name = "GPIOB"; ngpios = <16>; gpio-ranges = <&pinctrl 0 16 16>; @@ -331,7 +297,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x2000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOC>; st,bank-name = "GPIOC"; ngpios = <16>; gpio-ranges = <&pinctrl 0 32 16>; @@ -343,7 +309,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x3000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOD>; st,bank-name = "GPIOD"; ngpios = <16>; gpio-ranges = <&pinctrl 0 48 16>; @@ -355,7 +321,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x4000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOE>; st,bank-name = "GPIOE"; ngpios = <16>; gpio-ranges = <&pinctrl 0 64 16>; @@ -367,7 +333,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x5000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOF>; st,bank-name = "GPIOF"; ngpios = <16>; gpio-ranges = <&pinctrl 0 80 16>; @@ -379,7 +345,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x6000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOG>; st,bank-name = "GPIOG"; ngpios = <16>; gpio-ranges = <&pinctrl 0 96 16>; @@ -391,7 +357,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x7000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOH>; st,bank-name = "GPIOH"; ngpios = <15>; gpio-ranges = <&pinctrl 0 112 15>; @@ -403,7 +369,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0x8000 0x400>; - clocks = <&clk_pclk4>; + clocks = <&rcc GPIOI>; st,bank-name = "GPIOI"; ngpios = <8>; gpio-ranges = <&pinctrl 0 128 8>; diff --git a/arch/arm/boot/dts/stm32mp133.dtsi b/arch/arm/boot/dts/stm32mp133.dtsi index 0fb1386257cf..531c263c9f46 100644 --- a/arch/arm/boot/dts/stm32mp133.dtsi +++ b/arch/arm/boot/dts/stm32mp133.dtsi @@ -15,7 +15,7 @@ interrupts = , ; interrupt-names = "int0", "int1"; - clocks = <&clk_hse>, <&clk_pll4_r>; + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; status = "disabled"; @@ -28,7 +28,7 @@ interrupts = , ; interrupt-names = "int0", "int1"; - clocks = <&clk_hse>, <&clk_pll4_r>; + clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; diff --git a/arch/arm/boot/dts/stm32mp13xc.dtsi b/arch/arm/boot/dts/stm32mp13xc.dtsi index fa6889e30591..4d00e7592882 100644 --- a/arch/arm/boot/dts/stm32mp13xc.dtsi +++ b/arch/arm/boot/dts/stm32mp13xc.dtsi @@ -10,7 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54002000 0x400>; interrupts = ; - clocks = <&clk_axi>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; status = "disabled"; }; }; diff --git a/arch/arm/boot/dts/stm32mp13xf.dtsi b/arch/arm/boot/dts/stm32mp13xf.dtsi index fa6889e30591..4d00e7592882 100644 --- a/arch/arm/boot/dts/stm32mp13xf.dtsi +++ b/arch/arm/boot/dts/stm32mp13xf.dtsi @@ -10,7 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54002000 0x400>; interrupts = ; - clocks = <&clk_axi>; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; status = "disabled"; }; }; -- cgit From e007ec8422d3a4286f9ecdab35e92b710843b7e1 Mon Sep 17 00:00:00 2001 From: Gabriel Fernandez Date: Fri, 13 May 2022 16:51:48 +0200 Subject: ARM: dts: stm32: add optee reserved memory on stm32mp135f-dk Add the static OP-TEE reserved memory regions. Signed-off-by: Gabriel Fernandez Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp135f-dk.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 09d6226d598f..e6b8ffd332c7 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -26,6 +26,17 @@ reg = <0xc0000000 0x20000000>; }; + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@dd000000 { + reg = <0xdd000000 0x3000000>; + no-map; + }; + }; + gpio-keys { compatible = "gpio-keys"; -- cgit From fe7758e0e70b4199ff239720b53cff5248c8497c Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Jun 2022 02:15:59 +0200 Subject: ARM: dts: stm32: Fix SPI2 pinmux pin comments on stm32mp15 Those pin comments refer to SPI2 pins, not SPI1 pins, update the comments. No functional change. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 6052243ad81c..658162e2f420 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1794,15 +1794,15 @@ spi2_pins_a: spi2-0 { pins1 { - pinmux = , /* SPI1_SCK */ - ; /* SPI1_MOSI */ + pinmux = , /* SPI2_SCK */ + ; /* SPI2_MOSI */ bias-disable; drive-push-pull; slew-rate = <1>; }; pins2 { - pinmux = ; /* SPI1_MISO */ + pinmux = ; /* SPI2_MISO */ bias-disable; }; }; -- cgit From d9865c34b85af05ba0e07bf6f903eb6a56b06f25 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Jun 2022 02:20:59 +0200 Subject: dt-bindings: arm: stm32: Add compatible string for DH electronics DHCOR DRC Compact Add DT compatible string for DH electronics STM32MP15xx DHCOR on DRC Compact carrier board into YAML DT binding document. This system is a general purpose DIN Rail Controller design. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: Rob Herring Cc: devicetree@vger.kernel.org Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 8b31565fee59..4c605bccc474 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -59,12 +59,18 @@ properties: - prt,prtt1s # Protonic PRTT1S - const: st,stm32mp151 - - description: DH STM32MP153 SoM based Boards + - description: DH STM32MP153 DHCOM SoM based Boards items: - const: dh,stm32mp153c-dhcom-drc02 - const: dh,stm32mp153c-dhcom-som - const: st,stm32mp153 + - description: DH STM32MP153 DHCOR SoM based Boards + items: + - const: dh,stm32mp153c-dhcor-drc-compact + - const: dh,stm32mp153c-dhcor-som + - const: st,stm32mp153 + - items: - enum: - shiratech,stm32mp157a-iot-box # IoT Box -- cgit From bdb1f18fa959aa305c97708345fa9d9f90a59ef3 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Jun 2022 02:21:00 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for CAN1 pins Add another mux option for CAN1 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 658162e2f420..667d8b74a8a4 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -978,6 +978,26 @@ }; }; + m_can1_pins_c: m-can1-2 { + pins1 { + pinmux = ; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-disable; + }; + }; + + m_can1_sleep_pins_c: m_can1-sleep-2 { + pins { + pinmux = , /* CAN1_TX */ + ; /* CAN1_RX */ + }; + }; + m_can2_pins_a: m-can2-0 { pins1 { pinmux = ; /* CAN2_TX */ -- cgit From 5eabbd30fe60e03367b0d06461d1f94ea46a1b8a Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Jun 2022 02:21:01 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for SPI2 pins Add another mux option for SPI2 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 667d8b74a8a4..01242cb005b6 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1827,6 +1827,21 @@ }; }; + spi2_pins_b: spi2-1 { + pins1 { + pinmux = , /* SPI2_SCK */ + ; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = ; /* SPI2_MISO */ + bias-disable; + }; + }; + spi4_pins_a: spi4-0 { pins { pinmux = , /* SPI4_SCK */ -- cgit From 2ff9ec3a77f2d06165761e9606c4a5fccbe0feb2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Jun 2022 02:21:02 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for UART3 pins Add another mux option for UART3 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 41 ++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 01242cb005b6..95781bd8c309 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -2218,6 +2218,47 @@ }; }; + usart3_pins_e: usart3-4 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART3_RX */ + ; /* USART3_CTS_NSS */ + bias-pull-up; + }; + }; + + usart3_idle_pins_e: usart3-idle-4 { + pins1 { + pinmux = , /* USART3_TX */ + ; /* USART3_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART3_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART3_RX */ + bias-pull-up; + }; + }; + + usart3_sleep_pins_e: usart3-sleep-4 { + pins { + pinmux = , /* USART3_TX */ + , /* USART3_RTS */ + , /* USART3_CTS_NSS */ + ; /* USART3_RX */ + }; + }; + usbotg_hs_pins_a: usbotg-hs-0 { pins { pinmux = ; /* OTG_ID */ -- cgit From ced0cb456b429a126b8992035b3069db5f77f09e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Jun 2022 02:21:03 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for UART4 pins Add another mux option for UART4 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 95781bd8c309..adcb86831849 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1919,6 +1919,36 @@ }; }; + uart4_pins_d: uart4-3 { + pins1 { + pinmux = ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_idle_pins_d: uart4-idle-3 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_d: uart4-sleep-3 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + uart7_pins_a: uart7-0 { pins1 { pinmux = ; /* UART7_TX */ -- cgit From 35b2cb537c2147b61139e8ca226eb7c13fbe60b2 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Jun 2022 02:21:04 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for UART5 pins Add another mux option for UART5 pins, this is used on DRC Compact board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index adcb86831849..214563a4e56b 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1949,6 +1949,19 @@ }; }; + uart5_pins_a: uart5-0 { + pins1 { + pinmux = ; /* UART5_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART5_RX */ + bias-disable; + }; + }; + uart7_pins_a: uart7-0 { pins1 { pinmux = ; /* UART7_TX */ -- cgit From 49c66eb382da2ecac40f0b7d0e529ec9d24ce84e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 26 Jun 2022 02:21:05 +0200 Subject: ARM: dts: stm32: Add DHCOR based DRC Compact board Add DT for DH DRC Compact unit, which is a universal controller device. The system has two ethernet ports, one CAN, RS485 and RS232, USB, uSD card slot, eMMC and SDIO Wi-Fi. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + .../arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts | 30 ++ .../boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi | 322 +++++++++++++++++++++ 3 files changed, 353 insertions(+) create mode 100644 arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 5112f493f494..e3e9af031bf5 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1192,6 +1192,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp151a-prtt1c.dtb \ stm32mp151a-prtt1s.dtb \ stm32mp153c-dhcom-drc02.dtb \ + stm32mp153c-dhcor-drc-compact.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ diff --git a/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts b/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts new file mode 100644 index 000000000000..c8b9818499ea --- /dev/null +++ b/arch/arm/boot/dts/stm32mp153c-dhcor-drc-compact.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut + * + * DHCOR STM32MP1 variant: + * DHCR-STM32MP153C-C065-R051-V33-SPI-I-01LG + * DHCOR PCB number: 586-100 or newer + * DRC Compact PCB number: 627-100 or newer + */ + +/dts-v1/; + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcor-som.dtsi" +#include "stm32mp15xx-dhcor-drc-compact.dtsi" + +/ { + model = "DH electronics STM32MP153C DHCOR DRC Compact"; + compatible = "dh,stm32mp153c-dhcor-drc-compact", + "dh,stm32mp153c-dhcor-som", + "st,stm32mp153"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_c>; + pinctrl-1 = <&m_can1_sleep_pins_c>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi new file mode 100644 index 000000000000..27477bb219de --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-drc-compact.dtsi @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (C) 2022 Marek Vasut + */ + +/ { + aliases { + ethernet0 = ðernet0; + ethernet1 = &ksz8851; + mmc0 = &sdmmc1; + rtc0 = &hwrtc; + rtc1 = &rtc; + serial0 = &uart4; + serial1 = &uart8; + serial2 = &usart3; + serial3 = &uart5; + spi0 = &qspi; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + led { + compatible = "gpio-leds"; + led1 { + label = "yellow:user0"; + gpios = <&gpioz 6 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + led2 { + label = "red:user1"; + gpios = <&gpioz 3 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpioh 2 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vdd>; + }; +}; + +&adc { /* X11 ADC inputs */ + pinctrl-names = "default"; + pinctrl-0 = <&adc12_ain_pins_b>; + vdd-supply = <&vdd>; + vdda-supply = <&vdda>; + vref-supply = <&vdda>; + status = "okay"; + + adc1: adc@0 { + st,adc-channels = <0 1 6>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; + + adc2: adc@100 { + st,adc-channels = <0 1 2>; + st,min-sample-time-nsecs = <5000>; + status = "okay"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_c>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_c>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii"; + max-speed = <1000>; + phy-handle = <&phy0>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + reset-gpios = <&gpioz 2 GPIO_ACTIVE_LOW>; + reset-delay-us = <1000>; + reset-post-delay-us = <1000>; + + phy0: ethernet-phy@7 { + reg = <7>; + + rxc-skew-ps = <1500>; + rxdv-skew-ps = <540>; + rxd0-skew-ps = <420>; + rxd1-skew-ps = <420>; + rxd2-skew-ps = <420>; + rxd3-skew-ps = <420>; + + txc-skew-ps = <1440>; + txen-skew-ps = <540>; + txd0-skew-ps = <420>; + txd1-skew-ps = <420>; + txd2-skew-ps = <420>; + txd3-skew-ps = <420>; + }; + }; +}; + +&fmc { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&fmc_pins_b>; + pinctrl-1 = <&fmc_sleep_pins_b>; + status = "okay"; + + ksz8851: ethernet@1,0 { + compatible = "micrel,ks8851-mll"; + reg = <1 0x0 0x2>, <1 0x2 0x20000>; + interrupt-parent = <&gpioc>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + bank-width = <2>; + + /* Timing values are in nS */ + st,fmc2-ebi-cs-mux-enable; + st,fmc2-ebi-cs-transaction-type = <4>; + st,fmc2-ebi-cs-buswidth = <16>; + st,fmc2-ebi-cs-address-setup-ns = <5>; + st,fmc2-ebi-cs-address-hold-ns = <5>; + st,fmc2-ebi-cs-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-data-setup-ns = <45>; + st,fmc2-ebi-cs-data-hold-ns = <1>; + st,fmc2-ebi-cs-write-address-setup-ns = <5>; + st,fmc2-ebi-cs-write-address-hold-ns = <5>; + st,fmc2-ebi-cs-write-bus-turnaround-ns = <5>; + st,fmc2-ebi-cs-write-data-setup-ns = <45>; + st,fmc2-ebi-cs-write-data-hold-ns = <1>; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "DRCC-VAR2", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpioe { + gpio-line-names = "", "", "", "", + "", "DRCC-GPIO0", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiog { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "", + "DRCC-GPIO5", "", "", ""; +}; + +&gpioh { + gpio-line-names = "", "", "", "DRCC-HW2", + "DRCC-GPIO4", "", "", "", + "DRCC-HW1", "DRCC-HW0", "", "DRCC-VAR1", + "DRCC-VAR0", "", "", "DRCC-GPIO6"; +}; + +&gpioi { + gpio-line-names = "", "", "", "", + "", "", "", "DRCC-GPIO2", + "", "DRCC-GPIO1", "", "", + "", "", "", ""; +}; + +&i2c1 { /* X11 I2C1 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins_b>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c4 { + hwrtc: rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&sdmmc1 { /* MicroSD */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpioi 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&vdd>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; + +&sdmmc2 { /* eMMC */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; + +&sdmmc3 { /* SDIO Wi-Fi */ + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc3_b4_pins_a>; + pinctrl-1 = <&sdmmc3_b4_od_pins_a>; + pinctrl-2 = <&sdmmc3_b4_sleep_pins_a>; + broken-cd; + bus-width = <4>; + mmc-ddr-3_3v; + st,neg-edge; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + status = "okay"; +}; + +&spi2 { /* X11 SPI */ + pinctrl-names = "default"; + pinctrl-0 = <&spi2_pins_b>; + cs-gpios = <&gpioi 0 0>; + status = "disabled"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&uart4 { + label = "UART0"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_d>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart5 { /* X11 UART */ + label = "X11-UART5"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&uart8 { + label = "RS485-1"; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usart3 { /* RS485 or RS232 */ + label = "RS485-2"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&usart3_pins_e>; + pinctrl-1 = <&usart3_sleep_pins_e>; + uart-has-rtscts; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; + phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; -- cgit From bcdf998ea3eae91921eb1327664db227fd6b773e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 22 May 2022 22:24:02 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for DCMI pins Add another mux option for DCMI pins, this is used on AV96 board. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 37 ++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 214563a4e56b..94db065eada5 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -151,6 +151,43 @@ }; }; + dcmi_pins_c: dcmi-2 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + bias-pull-up; + }; + }; + + dcmi_sleep_pins_c: dcmi-sleep-2 { + pins { + pinmux = ,/* DCMI_HSYNC */ + ,/* DCMI_VSYNC */ + ,/* DCMI_PIXCLK */ + ,/* DCMI_D0 */ + ,/* DCMI_D1 */ + ,/* DCMI_D2 */ + ,/* DCMI_D3 */ + ,/* DCMI_D4 */ + ,/* DCMI_D5 */ + ,/* DCMI_D6 */ + ,/* DCMI_D7 */ + ,/* DCMI_D8 */ + ;/* DCMI_D9 */ + }; + }; + ethernet0_rgmii_pins_a: rgmii-0 { pins1 { pinmux = , /* ETH_RGMII_CLK125 */ -- cgit From f95a5242c54d528eab5c7c4f3f5910d72f585bbe Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 22 May 2022 22:24:03 +0200 Subject: ARM: dts: stm32: Add alternate pinmux for RCC pin Add another mux option for RCC pin, this is used on AV96 board for e.g. sensor clock supply. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index 94db065eada5..2cc9341d43d2 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -960,6 +960,21 @@ }; }; + mco1_pins_a: mco1-0 { + pins { + pinmux = ; /* MCO1 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + mco1_sleep_pins_a: mco1-sleep-0 { + pins { + pinmux = ; /* MCO1 */ + }; + }; + mco2_pins_a: mco2-0 { pins { pinmux = ; /* MCO2 */ -- cgit From cc6280cf885ce9ab923b9f9779aa8fbe10983d20 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sun, 22 May 2022 22:24:04 +0200 Subject: ARM: dts: stm32: Add ST MIPID02 bindings to AV96 Add DT bindings for ST MIPID02 and DCMI to Avenger96 base DT. Both the ST MIPID02 and DCMI are disabled by default, as the AV96 camera module is optional. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Manivannan Sadhasivam Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 76c54b006d87..90933077d66d 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -126,6 +126,22 @@ }; }; +&dcmi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmi_pins_c>; + pinctrl-1 = <&dcmi_sleep_pins_c>; + status = "disabled"; + + port { + dcmi_0: endpoint { + remote-endpoint = <&stmipi_2>; + bus-type = <5>; + bus-width = <8>; + pclk-sample = <0>; + }; + }; +}; + ðernet0 { status = "okay"; pinctrl-0 = <ðernet0_rgmii_pins_c>; @@ -219,6 +235,45 @@ }; &i2c4 { + stmipi: stmipi@14 { + compatible = "st,st-mipid02"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&mco1_pins_a>; + pinctrl-1 = <&mco1_sleep_pins_a>; + reg = <0x14>; + clocks = <&rcc CK_MCO1>; + clock-names = "xclk"; + assigned-clocks = <&rcc CK_MCO1>; + assigned-clock-parents = <&rcc CK_HSE>; + assigned-clock-rates = <24000000>; + VDDE-supply = <&v1v8>; + VDDIN-supply = <&v1v8>; + reset-gpios = <&gpioz 0 GPIO_ACTIVE_LOW>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + stmipi_0: endpoint { + }; + }; + + port@2 { + reg = <2>; + stmipi_2: endpoint { + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + remote-endpoint = <&dcmi_0>; + }; + }; + }; + }; + hdmi-transmitter@3d { compatible = "adi,adv7513"; reg = <0x3d>, <0x4d>, <0x2d>, <0x5d>; -- cgit