From 0bab86abe5b8c0c9491d44074d8abb012aa256e3 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Sun, 22 Dec 2019 12:39:19 +0100 Subject: arm64: tegra: Let the EMC hardware use the EMC clock The EMC hardware block needs access to the EMC clock in order to scale the external memory frequency. Add the clocks property so that drivers for the EMC can acquire a reference to the EMC clock. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index 631a7f77c386..a2c25176710a 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -607,6 +607,8 @@ emc: emc@7001b000 { compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; reg = <0x0 0x7001b000 0x0 0x1000>; + clocks = <&tegra_car TEGRA124_CLK_EMC>; + clock-names = "emc"; nvidia,memory-controller = <&mc>; }; -- cgit From 47cd385e08eac6f48b5e1cbac6939c100fd0f3fb Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Sun, 22 Dec 2019 12:39:21 +0100 Subject: arm64: tegra: Rename EMC on Tegra132 Rename the EMC node to external-memory-controller according to device tree best practices. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra132.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra132.dtsi b/arch/arm64/boot/dts/nvidia/tegra132.dtsi index a2c25176710a..6238e6e274b4 100644 --- a/arch/arm64/boot/dts/nvidia/tegra132.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra132.dtsi @@ -604,7 +604,7 @@ #iommu-cells = <1>; }; - emc: emc@7001b000 { + emc: external-memory-controller@7001b000 { compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; reg = <0x0 0x7001b000 0x0 0x1000>; clocks = <&tegra_car TEGRA124_CLK_EMC>; -- cgit From b72d52a1b60bf8e4973523582fbb5be7775ab4c2 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Sun, 22 Dec 2019 15:10:33 +0100 Subject: arm64: tegra: Add interrupt for memory controller on Tegra186 The memory controller can be interrupted by certain conditions. Add the interrupt to the device tree node to allow drivers to trap these conditions. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 7893d78a0fb6..365f7ce9f715 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -142,6 +142,7 @@ memory-controller@2c00000 { compatible = "nvidia,tegra186-mc"; reg = <0x0 0x02c00000 0x0 0xb0000>; + interrupts = ; status = "disabled"; }; -- cgit From 3f6eaef9ab37d1fc42a17ba2fcbc95b3de9ed52f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Sun, 22 Dec 2019 15:10:34 +0100 Subject: arm64: tegra: Add external memory controller on Tegra186 Add the external memory controller as a child device of the memory controller on Tegra186. The memory controller really represents the memory subsystem that encompasses both the memory and external memory controllers. The external memory controller uses the BPMP to obtain the list of supported EMC frequencies and set the EMC frequency. Also set up the dma-ranges property to describe that all memory clients can address up to 40 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 365f7ce9f715..19aba5f88e8f 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -144,6 +144,27 @@ reg = <0x0 0x02c00000 0x0 0xb0000>; interrupts = ; status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x0 0x02c00000 0x0 0x02c00000 0x0 0xb0000>; + + /* + * Memory clients have access to all 40 bits that the memory + * controller can address. + */ + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>; + + emc: external-memory-controller@2c60000 { + compatible = "nvidia,tegra186-emc"; + reg = <0x0 0x02c60000 0x0 0x50000>; + interrupts = ; + clocks = <&bpmp TEGRA186_CLK_EMC>; + clock-names = "emc"; + + nvidia,bpmp = <&bpmp>; + }; }; uarta: serial@3100000 { -- cgit From be9b887f3bbafcdbbfd6eb77c89c04776c63718e Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Sun, 22 Dec 2019 15:10:35 +0100 Subject: arm64: tegra: Add the memory subsystem on Tegra194 The memory subsystem on Tegra194 encompasses both the memory and external memory controllers. The EMC is represented as a subnode of the MC and a ranges property is used to describe the register ranges. A dma-ranges property is also added to describe that all memory clients can address up to 39 bits using the memory controller client interface (MCCIF), unless otherwise limited by the DMA engines of the hardware. A memory client can technically use 40 bits of addresses, but the memory controller on Tegra194 uses bit 39 to determine the XBAR format used to access memory. Use of this bit needs to be explicitly controlled by the operating system drivers for devices that can use this on-the-fly format conversion. Using the dma-ranges property prevents the operating system from using the bit implicitly, for example in I/O virtual address mappings. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 +++ arch/arm64/boot/dts/nvidia/tegra194.dtsi | 43 ++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi index c7f2a20e6b02..bdd33ff4e324 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi @@ -48,6 +48,10 @@ }; }; + memory-controller@2c00000 { + status = "okay"; + }; + serial@3110000 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 11220d97adb8..96dd0d7a9dde 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -7,6 +7,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra194"; @@ -164,6 +165,48 @@ }; }; + mc: memory-controller@2c00000 { + compatible = "nvidia,tegra194-mc"; + reg = <0x02c00000 0x100000>, + <0x02b80000 0x040000>, + <0x01700000 0x100000>; + status = "disabled"; + + #address-cells = <2>; + #size-cells = <2>; + + ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>, + <0x02b80000 0x0 0x02b80000 0x0 0x040000>, + <0x02c00000 0x0 0x02c00000 0x0 0x100000>; + + /* + * Bit 39 of addresses passing through the memory + * controller selects the XBAR format used when memory + * is accessed. This is used to transparently access + * memory in the XBAR format used by the discrete GPU + * (bit 39 set) or Tegra (bit 39 clear). + * + * As a consequence, the operating system must ensure + * that bit 39 is never used implicitly, for example + * via an I/O virtual address mapping of an IOMMU. If + * devices require access to the XBAR switch, their + * drivers must set this bit explicitly. + * + * Limit the DMA range for memory clients to [38:0]. + */ + dma-ranges = <0x0 0x0 0x0 0x80 0x0>; + + emc: external-memory-controller@2c60000 { + compatible = "nvidia,tegra194-emc"; + reg = <0x0 0x02c60000 0x0 0x90000>, + <0x0 0x01780000 0x0 0x80000>; + clocks = <&bpmp TEGRA194_CLK_EMC>; + clock-names = "emc"; + + nvidia,bpmp = <&bpmp>; + }; + }; + uarta: serial@3100000 { compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart"; reg = <0x03100000 0x40>; -- cgit From 06c6b06f890879fa12ed5e517f70eafb54587cc7 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Wed, 18 Dec 2019 10:25:01 +0100 Subject: arm64: tegra: Make XUSB node consistent with the rest The ordering of properties in the XUSB node is inconsistent with the ordering of the properties in other nodes. Resort them to make the node more consistent. Also get rid of some unnecessary whitespace. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186.dtsi | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi index 19aba5f88e8f..c905527c26ef 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi @@ -546,12 +546,9 @@ reg = <0x0 0x03530000 0x0 0x8000>, <0x0 0x03538000 0x0 0x1000>; reg-names = "hcd", "fpci"; - - iommus = <&smmu TEGRA186_SID_XUSB_HOST>; interrupts = , , ; - clocks = <&bpmp TEGRA186_CLK_XUSB_HOST>, <&bpmp TEGRA186_CLK_XUSB_FALCON>, <&bpmp TEGRA186_CLK_XUSB_SS>, @@ -564,16 +561,15 @@ clock-names = "xusb_host", "xusb_falcon_src", "xusb_ss", "xusb_ss_src", "xusb_hs_src", "xusb_fs_src", "pll_u_480m", "clk_m", "pll_e"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_XUSBC>, <&bpmp TEGRA186_POWER_DOMAIN_XUSBA>; power-domain-names = "xusb_host", "xusb_ss"; - nvidia,xusb-padctl = <&padctl>; - - status = "disabled"; - + iommus = <&smmu TEGRA186_SID_XUSB_HOST>; #address-cells = <1>; #size-cells = <0>; + status = "disabled"; + + nvidia,xusb-padctl = <&padctl>; }; fuse@3820000 { -- cgit From 09903c5e07ac1f84cd416ee458d16106bec3f540 Mon Sep 17 00:00:00 2001 From: JC Kuo Date: Fri, 3 Jan 2020 16:30:18 +0800 Subject: arm64: tegra: Add fuse/apbmisc node on Tegra194 This commit adds Tegra194 fuse and apbmisc device nodes. Signed-off-by: JC Kuo Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi index 96dd0d7a9dde..ccac43be12ac 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi @@ -22,6 +22,12 @@ #size-cells = <1>; ranges = <0x0 0x0 0x0 0x40000000>; + misc@100000 { + compatible = "nvidia,tegra194-misc"; + reg = <0x00100000 0xf000>, + <0x0010f000 0x1000>; + }; + gpio: gpio@2200000 { compatible = "nvidia,tegra194-gpio"; reg-names = "security", "gpio"; @@ -531,6 +537,13 @@ status = "disabled"; }; + fuse@3820000 { + compatible = "nvidia,tegra194-efuse"; + reg = <0x03820000 0x10000>; + clocks = <&bpmp TEGRA194_CLK_FUSE>; + clock-names = "fuse"; + }; + gic: interrupt-controller@3881000 { compatible = "arm,gic-400"; #interrupt-cells = <3>; -- cgit From 6f78a9460f275651418728e3cb3bfc42683b881c Mon Sep 17 00:00:00 2001 From: Tamás Szűcs Date: Sun, 8 Dec 2019 20:55:31 +0100 Subject: arm64: tegra: Enable PWM fan on Jetson Nano MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable PWM fan and extend CPU thermal zones for monitoring and fan control. This will trigger the PWM fan on J15 and cool down the system if necessary. Signed-off-by: Tamás Szűcs Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index 90381d52ac54..f2a138b14e36 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -573,6 +573,66 @@ }; }; + fan: fan { + compatible = "pwm-fan"; + pwms = <&pwm 3 45334>; + + cooling-levels = <0 64 128 255>; + #cooling-cells = <2>; + }; + + thermal-zones { + cpu { + trips { + cpu_trip_critical: critical { + temperature = <96500>; + hysteresis = <0>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <70000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active: active { + temperature = <50000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_passive: passive { + temperature = <30000>; + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu-critical { + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_critical>; + }; + + cpu-hot { + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_hot>; + }; + + cpu-active { + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active>; + }; + + cpu-passive { + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; -- cgit From 1f32a31fe27e0d86945d9f0933d343885802bfa7 Mon Sep 17 00:00:00 2001 From: Tamás Szűcs Date: Mon, 2 Dec 2019 22:52:00 +0100 Subject: arm64: tegra: Enable SDIO on Jetson Nano M.2 Key E MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enable SDMMC3 and set it up for SDIO devices. Signed-off-by: Tamás Szűcs Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts index f2a138b14e36..9101d3a39cd2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts @@ -536,6 +536,19 @@ vmmc-supply = <&vdd_3v3_sd>; }; + sdhci@700b0400 { + status = "okay"; + bus-width = <4>; + + vqmmc-supply = <&vdd_1v8>; + vmmc-supply = <&vdd_3v3_sys>; + + non-removable; + cap-sdio-irq; + keep-power-in-suspend; + wakeup-source; + }; + clocks { compatible = "simple-bus"; #address-cells = <1>; -- cgit From cd8f843c6c9bc7b8ce36c06333e10d2abc89a1fd Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 8 Nov 2019 16:36:40 +0100 Subject: arm64: tegra: Redefine force recovery key on Jetson AGX Xavier The current BTN_1 code associated with the force-recovery key is not a valid code for EV_KEY type input devices. This causes errors in the libinput debug-events command. There is no system level action that maps to the force-recovery key on Jetson AGX Xavier, so assign it the KEY_SLEEP action, which at least makes it do something marginally useful. Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts index 353a6a22196d..985e7d84f161 100644 --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts @@ -152,7 +152,7 @@ gpios = <&gpio TEGRA194_MAIN_GPIO(G, 0) GPIO_ACTIVE_LOW>; linux,input-type = ; - linux,code = ; + linux,code = ; debounce-interval = <10>; }; -- cgit From f41f34ddcee679641ff7d177b37597844d82d634 Mon Sep 17 00:00:00 2001 From: Peter Robinson Date: Sat, 2 Nov 2019 17:29:17 +0000 Subject: arm64: tegra: Allow bootloader to configure Ethernet MAC on Jetson TX2 Add an ethernet alias so that a stable MAC address is added to the device tree for the wired ethernet interface. Signed-off-by: Peter Robinson Signed-off-by: Thierry Reding --- arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi index 5e18acf5cfad..947744d0f04c 100644 --- a/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi @@ -8,6 +8,7 @@ compatible = "nvidia,p3310", "nvidia,tegra186"; aliases { + ethernet0 = "/ethernet@2490000"; sdhci0 = "/sdhci@3460000"; sdhci1 = "/sdhci@3400000"; serial0 = &uarta; -- cgit