From 3b287269ab602d794470b482960c27c873e5af47 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Fri, 7 Jun 2024 13:14:21 +0200 Subject: dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific reg-name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the reg-name "apb" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use a different reg-name when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "apb" is already defined in snps,dw-pcie.yaml, add it also for snps,dw-pcie-ep.yaml. Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-1-0a042d6b0049@kernel.org Signed-off-by: Niklas Cassel Signed-off-by: Krzysztof Wilczyński Reviewed-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index bbdb01d22848..00dec01f1f73 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -100,7 +100,7 @@ properties: for new bindings. oneOf: - description: See native 'elbi/app' CSR region for details. - enum: [ link, appl ] + enum: [ apb, link, appl ] - description: See native 'atu' CSR region for details. enum: [ atu_dma ] allOf: -- cgit From b96353773d24359c1830a90e79b8240a2720b605 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Fri, 7 Jun 2024 13:14:22 +0200 Subject: dt-bindings: PCI: snps,dw-pcie-ep: Add vendor specific interrupt-names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Considering that some drivers (e.g. pcie-dw-rockchip.c) already use the interrupt-names "sys", "pmc", "msg", "err" for the device tree binding in Root Complex mode (snps,dw-pcie.yaml), it doesn't make sense that those drivers should use different interrupt-names when running in Endpoint mode (snps,dw-pcie-ep.yaml). Therefore, since "sys", "pmc", "msg", "err" are already defined in snps,dw-pcie.yaml, add them also for snps,dw-pcie-ep.yaml. Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-2-0a042d6b0049@kernel.org Signed-off-by: Niklas Cassel Signed-off-by: Krzysztof Wilczyński Reviewed-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index 00dec01f1f73..f5f12cbc2cb3 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -156,7 +156,7 @@ properties: for new bindings. oneOf: - description: See native "app" IRQ for details - enum: [ intr ] + enum: [ intr, sys, pmc, msg, err ] max-functions: maximum: 32 -- cgit From 6f308c017c2729a5e70cf6282a74ff0f43b8e90c Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Fri, 7 Jun 2024 13:14:23 +0200 Subject: dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy IRQs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd that are triggered when the PCIe controller (when running in Endpoint mode) has sent an Assert_INTA Message to the upstream device. Some DWC controllers have these interrupt in a combined interrupt signal. Add the description of these interrupts to the device tree binding. Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-3-0a042d6b0049@kernel.org Signed-off-by: Niklas Cassel Signed-off-by: Krzysztof Wilczyński Reviewed-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml index f5f12cbc2cb3..f474b9e3fc7e 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml @@ -151,6 +151,15 @@ properties: Application-specific IRQ raised depending on the vendor-specific events basis. const: app + - description: + Interrupts triggered when the controller itself (in Endpoint mode) + has sent an Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message to + the upstream device. + pattern: "^tx_int(a|b|c|d)$" + - description: + Combined interrupt signal raised when the controller has sent an + Assert_INT{A,B,C,D} message. See "^tx_int(a|b|c|d)$" for details. + const: legacy - description: Vendor-specific IRQ names. Consider using the generic names above for new bindings. -- cgit From 9b0b9b588c00a801230727e5046a2323bf4e4d34 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Fri, 7 Jun 2024 13:14:24 +0200 Subject: dt-bindings: PCI: rockchip-dw-pcie: Prepare for Endpoint mode support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Refactor the rockchip-dw-pcie binding to move generic properties to a new rockchip-dw-pcie-common binding that can be shared by both RC and EP mode. No functional change intended. Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-4-0a042d6b0049@kernel.org Signed-off-by: Niklas Cassel Signed-off-by: Krzysztof Wilczyński Reviewed-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/rockchip-dw-pcie-common.yaml | 111 +++++++++++++++++++++ .../devicetree/bindings/pci/rockchip-dw-pcie.yaml | 93 +---------------- 2 files changed, 114 insertions(+), 90 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml new file mode 100644 index 000000000000..60d190a77580 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe RC/EP controller on Rockchip SoCs + +maintainers: + - Shawn Lin + - Simon Xue + - Heiko Stuebner + +description: |+ + Generic properties for the DesignWare based PCIe RC/EP controller on Rockchip + SoCs. + +properties: + clocks: + minItems: 5 + items: + - description: AHB clock for PCIe master + - description: AHB clock for PCIe slave + - description: AHB clock for PCIe dbi + - description: APB clock for PCIe + - description: Auxiliary clock for PCIe + - description: PIPE clock + - description: Reference clock for PCIe + + clock-names: + minItems: 5 + items: + - const: aclk_mst + - const: aclk_slv + - const: aclk_dbi + - const: pclk + - const: aux + - const: pipe + - const: ref + + interrupts: + items: + - description: + Combined system interrupt, which is used to signal the following + interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, + hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, + edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app + - description: + Combined PM interrupt, which is used to signal the following + interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, + linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, + linkst_out_l0s, pm_dstate_update + - description: + Combined message interrupt, which is used to signal the following + interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, + pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active + - description: + Combined legacy interrupt, which is used to signal the following + interrupts - inta, intb, intc, intd + - description: + Combined error interrupt, which is used to signal the following + interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, + tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, + nf_err_rx, f_err_rx, radm_qoverflow + + interrupt-names: + items: + - const: sys + - const: pmc + - const: msg + - const: legacy + - const: err + + num-lanes: true + + phys: + maxItems: 1 + + phy-names: + const: pcie-phy + + power-domains: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 2 + + reset-names: + oneOf: + - const: pipe + - items: + - const: pwr + - const: pipe + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - num-lanes + - phys + - phy-names + - power-domains + - resets + - reset-names + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml index 5f719218c472..550d8a684af3 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/pci/rockchip-dw-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: DesignWare based PCIe controller on Rockchip SoCs +title: DesignWare based PCIe Root Complex controller on Rockchip SoCs maintainers: - Shawn Lin @@ -12,12 +12,13 @@ maintainers: - Heiko Stuebner description: |+ - RK3568 SoC PCIe host controller is based on the Synopsys DesignWare + RK3568 SoC PCIe Root Complex controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in snps,dw-pcie.yaml. allOf: - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# properties: compatible: @@ -40,61 +41,6 @@ properties: - const: apb - const: config - clocks: - minItems: 5 - items: - - description: AHB clock for PCIe master - - description: AHB clock for PCIe slave - - description: AHB clock for PCIe dbi - - description: APB clock for PCIe - - description: Auxiliary clock for PCIe - - description: PIPE clock - - description: Reference clock for PCIe - - clock-names: - minItems: 5 - items: - - const: aclk_mst - - const: aclk_slv - - const: aclk_dbi - - const: pclk - - const: aux - - const: pipe - - const: ref - - interrupts: - items: - - description: - Combined system interrupt, which is used to signal the following - interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme, - hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi, - edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app - - description: - Combined PM interrupt, which is used to signal the following - interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2, - linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2, - linkst_out_l0s, pm_dstate_update - - description: - Combined message interrupt, which is used to signal the following - interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi, - pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active - - description: - Combined legacy interrupt, which is used to signal the following - interrupts - inta, intb, intc, intd - - description: - Combined error interrupt, which is used to signal the following - interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, - tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, - nf_err_rx, f_err_rx, radm_qoverflow - - interrupt-names: - items: - - const: sys - - const: pmc - - const: msg - - const: legacy - - const: err - legacy-interrupt-controller: description: Interrupt controller node for handling legacy PCI interrupts. type: object @@ -119,47 +65,14 @@ properties: msi-map: true - num-lanes: true - - phys: - maxItems: 1 - - phy-names: - const: pcie-phy - - power-domains: - maxItems: 1 - ranges: minItems: 2 maxItems: 3 - resets: - minItems: 1 - maxItems: 2 - - reset-names: - oneOf: - - const: pipe - - items: - - const: pwr - - const: pipe - vpcie3v3-supply: true required: - - compatible - - reg - - reg-names - - clocks - - clock-names - msi-map - - num-lanes - - phys - - phy-names - - power-domains - - resets - - reset-names unevaluatedProperties: false -- cgit From 5f262f67cbc5f96c857602443f1fdf66900249f3 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Fri, 7 Jun 2024 13:14:25 +0200 Subject: dt-bindings: PCI: rockchip-dw-pcie: Fix description of legacy IRQ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The descriptions of the combined interrupt signals (level1) mention all the lower interrupt signals (level2) for each combined interrupt, regardless if the lower (level2) signal is RC or EP specific. E.g. the description of "Combined system interrupt" includes rbar_update, which is EP specific, and the description of "Combined message interrupt" includes obff_idle, obff_obff, obff_cpu_active, which are all EP specific. The only exception is the "Combined legacy interrupt", which for some reason does not provide an exhaustive list of the lower (level2) signals. Add the missing lower interrupt signals: tx_inta, tx_intb, tx_intc, and tx_intd for the "Combined legacy interrupt", as per the rk3568 and rk3588 Technical Reference Manuals, such that the descriptions of the combined interrupt signals are consistent. Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-5-0a042d6b0049@kernel.org Signed-off-by: Niklas Cassel Signed-off-by: Krzysztof Wilczyński Reviewed-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index 60d190a77580..ec5e6a3d048e 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -56,7 +56,8 @@ properties: pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active - description: Combined legacy interrupt, which is used to signal the following - interrupts - inta, intb, intc, intd + interrupts - inta, intb, intc, intd, tx_inta, tx_intb, tx_intc, + tx_intd - description: Combined error interrupt, which is used to signal the following interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, -- cgit From 743025b0e072dafa6e176409eaac6e0ee203b6b3 Mon Sep 17 00:00:00 2001 From: Niklas Cassel Date: Fri, 7 Jun 2024 13:14:26 +0200 Subject: dt-bindings: PCI: rockchip: Add DesignWare based PCIe Endpoint controller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document DT bindings for PCIe Endpoint controller found in Rockchip SoCs. Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-6-0a042d6b0049@kernel.org Signed-off-by: Niklas Cassel Signed-off-by: Krzysztof Wilczyński Reviewed-by: Manivannan Sadhasivam Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/rockchip-dw-pcie-common.yaml | 14 ++++ .../bindings/pci/rockchip-dw-pcie-ep.yaml | 95 ++++++++++++++++++++++ 2 files changed, 109 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml index ec5e6a3d048e..cc9adfc7611c 100644 --- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-common.yaml @@ -39,6 +39,7 @@ properties: - const: ref interrupts: + minItems: 5 items: - description: Combined system interrupt, which is used to signal the following @@ -63,14 +64,27 @@ properties: interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout, tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx, nf_err_rx, f_err_rx, radm_qoverflow + - description: + eDMA write channel 0 interrupt + - description: + eDMA write channel 1 interrupt + - description: + eDMA read channel 0 interrupt + - description: + eDMA read channel 1 interrupt interrupt-names: + minItems: 5 items: - const: sys - const: pmc - const: msg - const: legacy - const: err + - const: dma0 + - const: dma1 + - const: dma2 + - const: dma3 num-lanes: true diff --git a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml new file mode 100644 index 000000000000..f2d1137aff50 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie-ep.yaml @@ -0,0 +1,95 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rockchip-dw-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: DesignWare based PCIe Endpoint controller on Rockchip SoCs + +maintainers: + - Niklas Cassel + +description: |+ + RK3588 SoC PCIe Endpoint controller is based on the Synopsys DesignWare + PCIe IP and thus inherits all the common properties defined in + snps,dw-pcie-ep.yaml. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/rockchip-dw-pcie-common.yaml# + +properties: + compatible: + enum: + - rockchip,rk3568-pcie-ep + - rockchip,rk3588-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers + - description: Data Bus Interface (DBI) shadow registers + - description: Rockchip designed configuration registers + - description: Memory region used to map remote RC address space + - description: Internal Address Translation Unit (iATU) registers + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: apb + - const: addr_space + - const: atu + +required: + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie3x4_ep: pcie-ep@fe150000 { + compatible = "rockchip,rk3588-pcie-ep"; + reg = <0xa 0x40000000 0x0 0x00100000>, + <0xa 0x40100000 0x0 0x00100000>, + <0x0 0xfe150000 0x0 0x00010000>, + <0x9 0x00000000 0x0 0x40000000>, + <0xa 0x40300000 0x0 0x00100000>; + reg-names = "dbi", "dbi2", "apb", "addr_space", "atu"; + clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, + <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, + <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; + clock-names = "aclk_mst", "aclk_slv", + "aclk_dbi", "pclk", + "aux", "pipe"; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "sys", "pmc", "msg", "legacy", "err", + "dma0", "dma1", "dma2", "dma3"; + max-link-speed = <3>; + num-lanes = <4>; + phys = <&pcie30phy>; + phy-names = "pcie-phy"; + power-domains = <&power RK3588_PD_PCIE>; + resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; + reset-names = "pwr", "pipe"; + }; + }; +... -- cgit From a3ec59e982e08366fa755730bbe803f7ed042391 Mon Sep 17 00:00:00 2001 From: Thippeswamy Havalige Date: Mon, 24 Jun 2024 16:40:22 +0530 Subject: dt-bindings: PCI: xilinx-cpm: Fix overlapping of bridge register and 32-bit BAR addresses MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The current configuration had non-prefetchable memory overlapping with bridge registers by 64KB from base address. This patch fixes the 'ranges' property in the device tree by adjusting the non-prefetchable memory addresses beyond the 64KB mark to prevent conflicts. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/20240624111022.133780-1-thippesw@amd.com Signed-off-by: Thippeswamy Havalige Signed-off-by: Krzysztof Wilczyński Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 4770ce02fcc3..989fb0fa2577 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -92,7 +92,7 @@ examples: <0 0 0 3 &pcie_intc_0 2>, <0 0 0 4 &pcie_intc_0 3>; bus-range = <0x00 0xff>; - ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, + ranges = <0x02000000 0x0 0xe0010000 0x0 0xe0010000 0x0 0x10000000>, <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>; msi-map = <0x0 &its_gic 0x0 0x10000>; reg = <0x0 0xfca10000 0x0 0x1000>, -- cgit From bdf8e4d5d68ff78ea5c0f3f61c4f93c2305d69cf Mon Sep 17 00:00:00 2001 From: Krishna chaitanya chundru Date: Wed, 19 Jun 2024 20:41:11 +0530 Subject: dt-bindings: PCI: qcom: Add OPP table MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PCIe needs to choose the appropriate performance state of RPMh power domain based on the PCIe gen speed. Adding the Operating Performance Points table allows to adjust power domain performance state and ICC peak bw, depending on the PCIe data rate and link width. Link: https://lore.kernel.org/linux-pci/20240619-opp_support-v15-2-aa769a2173a3@quicinc.com Signed-off-by: Krishna chaitanya chundru Signed-off-by: Krzysztof Wilczyński Reviewed-by: Krzysztof Kozlowski Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml index 1496d6993ab4..d8c0afaa4b19 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8450.yaml @@ -69,6 +69,10 @@ properties: - const: msi6 - const: msi7 + operating-points-v2: true + opp-table: + type: object + resets: maxItems: 1 -- cgit From bc9792f32cbd1a3bf8afef78efa5a9116323ca83 Mon Sep 17 00:00:00 2001 From: Sergio Paracuellos Date: Wed, 22 May 2024 06:43:21 +0200 Subject: dt-bindings: PCI: mediatek,mt7621-pcie: Add PCIe host topology ASCII graph MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MediaTek MT7621 PCIe sub-system supports a single Root Complex (RC) with 3 Root Ports. Add PCIe host topology ASCII graph to the binding for completeness. Suggested-by: Krzysztof Kozlowski Link: https://lore.kernel.org/linux-pci/20240522044321.3205160-1-sergio.paracuellos@gmail.com Signed-off-by: Sergio Paracuellos Signed-off-by: Krzysztof Wilczyński Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../bindings/pci/mediatek,mt7621-pcie.yaml | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml index 6fba42156db6..c41608863d6c 100644 --- a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml @@ -13,6 +13,35 @@ description: |+ MediaTek MT7621 PCIe subsys supports a single Root Complex (RC) with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link + MT7621 PCIe HOST Topology + + .-------. + | | + | CPU | + | | + '-------' + | + | + | + v + .------------------. + .-----------| HOST/PCI Bridge |------------. + | '------------------' | Type1 + BUS0 | | | Access + v v v On Bus0 + .-------------. .-------------. .-------------. + | VIRTUAL P2P | | VIRTUAL P2P | | VIRTUAL P2P | + | BUS0 | | BUS0 | | BUS0 | + | DEV0 | | DEV1 | | DEV2 | + '-------------' '-------------' '-------------' + Type0 | Type0 | Type0 | + Access BUS1 | Access BUS2| Access BUS3| + On Bus1 v On Bus2 v On Bus3 v + .----------. .----------. .----------. + | Device 0 | | Device 0 | | Device 0 | + | Func 0 | | Func 0 | | Func 0 | + '----------' '----------' '----------' + allOf: - $ref: /schemas/pci/pci-host-bridge.yaml# -- cgit From 631b2e7318d45bb0f1a5490c9a9e0509b67629ee Mon Sep 17 00:00:00 2001 From: Jean-Philippe Brucker Date: Fri, 7 Jun 2024 11:54:14 +0100 Subject: dt-bindings: PCI: generic: Add ats-supported property MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a way for firmware to tell the OS that ATS is supported by the PCI root complex. An endpoint with ATS enabled may send Translation Requests and Translated Memory Requests, which look just like Normal Memory Requests with a non-zero AT field. So a root controller that ignores the AT field may simply forward the request to the IOMMU as a Normal Memory Request, which could end badly. In any case, the endpoint will be unusable. The ats-supported property allows the OS to only enable ATS in endpoints if the root controller can handle ATS requests. Only add the property to pcie-host-ecam-generic for the moment. For non-generic root controllers, availability of ATS can be inferred from the compatible string. Link: https://lore.kernel.org/linux-pci/20240607105415.2501934-3-jean-philippe@linaro.org Signed-off-by: Jean-Philippe Brucker Signed-off-by: Krzysztof Wilczyński Reviewed-by: Jason Gunthorpe Reviewed-by: Liviu Dudau Reviewed-by: Nicolin Chen Reviewed-by: Rob Herring Reviewed-by: Robin Murphy --- Documentation/devicetree/bindings/pci/host-generic-pci.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml index 3484e0b4b412..bcfbaf5582cc 100644 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml @@ -110,6 +110,12 @@ properties: iommu-map-mask: true msi-parent: true + ats-supported: + description: + Indicates that a PCIe host controller supports ATS, and can handle Memory + Requests with Address Type (AT). + type: boolean + required: - compatible - reg -- cgit From 30e7c6cc88b044a7f89636dd55e9eb6b5a666b14 Mon Sep 17 00:00:00 2001 From: Abel Vesa Date: Wed, 5 Jun 2024 11:19:01 +0300 Subject: dt-bindings: PCI: qcom: x1e80100: Make the MHI reg region mandatory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All PCIe controllers found on X1E80100 have MHI register region. So change the schema to reflect that. Fixes: 692eadd51698 ("dt-bindings: PCI: qcom: Document the X1E80100 PCIe Controller") Link: https://lore.kernel.org/linux-pci/20240605-x1e80100-pci-bindings-fix-v2-1-c465e87966fc@linaro.org Signed-off-by: Abel Vesa Signed-off-by: Krzysztof Wilczyński Reviewed-by: Rob Herring (Arm) Reviewed-by: Manivannan Sadhasivam Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml index 1074310a8e7a..a9db0a231563 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml @@ -19,11 +19,10 @@ properties: const: qcom,pcie-x1e80100 reg: - minItems: 5 + minItems: 6 maxItems: 6 reg-names: - minItems: 5 items: - const: parf # Qualcomm specific registers - const: dbi # DesignWare PCIe registers -- cgit