From fda1a71a490bdc39b3a2ff75cf52fcd83ac122c2 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 30 Mar 2024 21:52:41 +0100 Subject: drm/etnaviv: drop driver owner assignment Core in platform_driver_register() already sets the .owner, so driver does not need to. Whatever is set here will be anyway overwritten by main driver calling platform_driver_register(). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Christian Gmeiner Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index a9bf426f69b3..502e200900f9 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1975,7 +1975,6 @@ static const struct dev_pm_ops etnaviv_gpu_pm_ops = { struct platform_driver etnaviv_gpu_driver = { .driver = { .name = "etnaviv-gpu", - .owner = THIS_MODULE, .pm = pm_ptr(&etnaviv_gpu_pm_ops), .of_match_table = etnaviv_gpu_match, }, -- cgit From 608ff8e90b6ee4a9f2ef1c157ecf0e72d0a6e7fd Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 25 Jan 2024 12:07:06 +0100 Subject: drm/etnaviv: Update hardware headers from rnndb Update the state HI header from the rnndb commit 8d7ee714cfe2 ("Merge pull request #24 from pH5/unknown-3950"). Signed-off-by: Philipp Zabel Reviewed-by: Christian Gmeiner Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/cmdstream.xml.h | 52 ++++++++++++++-- drivers/gpu/drm/etnaviv/common.xml.h | 12 ++-- drivers/gpu/drm/etnaviv/state.xml.h | 103 +++++++++++++++++++++++++++----- drivers/gpu/drm/etnaviv/state_blt.xml.h | 22 +++---- drivers/gpu/drm/etnaviv/state_hi.xml.h | 30 ++++++---- 5 files changed, 173 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/cmdstream.xml.h b/drivers/gpu/drm/etnaviv/cmdstream.xml.h index 65f1ba1099bd..a96597a27ae2 100644 --- a/drivers/gpu/drm/etnaviv/cmdstream.xml.h +++ b/drivers/gpu/drm/etnaviv/cmdstream.xml.h @@ -8,11 +8,11 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- cmdstream.xml ( 14094 bytes, from 2016-11-11 06:55:14) -- copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22) -- common.xml ( 23344 bytes, from 2016-11-10 15:14:07) +- cmdstream.xml ( 16933 bytes, from 2023-12-11 15:50:17) +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32) +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32) -Copyright (C) 2012-2016 by the following authors: +Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach @@ -52,6 +52,9 @@ DEALINGS IN THE SOFTWARE. #define FE_OPCODE_RETURN 0x0000000b #define FE_OPCODE_DRAW_INSTANCED 0x0000000c #define FE_OPCODE_CHIP_SELECT 0x0000000d +#define FE_OPCODE_WAIT_FENCE 0x0000000f +#define FE_OPCODE_DRAW_INDIRECT 0x00000010 +#define FE_OPCODE_SNAP_PAGES 0x00000013 #define PRIMITIVE_TYPE_POINTS 0x00000001 #define PRIMITIVE_TYPE_LINES 0x00000002 #define PRIMITIVE_TYPE_LINE_STRIP 0x00000003 @@ -192,6 +195,9 @@ DEALINGS IN THE SOFTWARE. #define VIV_FE_STALL_TOKEN_TO__MASK 0x00001f00 #define VIV_FE_STALL_TOKEN_TO__SHIFT 8 #define VIV_FE_STALL_TOKEN_TO(x) (((x) << VIV_FE_STALL_TOKEN_TO__SHIFT) & VIV_FE_STALL_TOKEN_TO__MASK) +#define VIV_FE_STALL_TOKEN_UNK28__MASK 0x30000000 +#define VIV_FE_STALL_TOKEN_UNK28__SHIFT 28 +#define VIV_FE_STALL_TOKEN_UNK28(x) (((x) << VIV_FE_STALL_TOKEN_UNK28__SHIFT) & VIV_FE_STALL_TOKEN_UNK28__MASK) #define VIV_FE_CALL 0x00000000 @@ -266,5 +272,43 @@ DEALINGS IN THE SOFTWARE. #define VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT 0 #define VIV_FE_DRAW_INSTANCED_START_INDEX(x) (((x) << VIV_FE_DRAW_INSTANCED_START_INDEX__SHIFT) & VIV_FE_DRAW_INSTANCED_START_INDEX__MASK) +#define VIV_FE_WAIT_FENCE 0x00000000 + +#define VIV_FE_WAIT_FENCE_HEADER 0x00000000 +#define VIV_FE_WAIT_FENCE_HEADER_OP__MASK 0xf8000000 +#define VIV_FE_WAIT_FENCE_HEADER_OP__SHIFT 27 +#define VIV_FE_WAIT_FENCE_HEADER_OP_WAIT_FENCE 0x78000000 +#define VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK 0x00030000 +#define VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT 16 +#define VIV_FE_WAIT_FENCE_HEADER_UNK16(x) (((x) << VIV_FE_WAIT_FENCE_HEADER_UNK16__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_UNK16__MASK) +#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK 0x0000ffff +#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT 0 +#define VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT(x) (((x) << VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__SHIFT) & VIV_FE_WAIT_FENCE_HEADER_WAITCOUNT__MASK) + +#define VIV_FE_WAIT_FENCE_ADDRESS 0x00000004 + +#define VIV_FE_DRAW_INDIRECT 0x00000000 + +#define VIV_FE_DRAW_INDIRECT_HEADER 0x00000000 +#define VIV_FE_DRAW_INDIRECT_HEADER_OP__MASK 0xf8000000 +#define VIV_FE_DRAW_INDIRECT_HEADER_OP__SHIFT 27 +#define VIV_FE_DRAW_INDIRECT_HEADER_OP_DRAW_INDIRECT 0x80000000 +#define VIV_FE_DRAW_INDIRECT_HEADER_INDEXED 0x00000100 +#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK 0x0000000f +#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT 0 +#define VIV_FE_DRAW_INDIRECT_HEADER_TYPE(x) (((x) << VIV_FE_DRAW_INDIRECT_HEADER_TYPE__SHIFT) & VIV_FE_DRAW_INDIRECT_HEADER_TYPE__MASK) + +#define VIV_FE_DRAW_INDIRECT_ADDRESS 0x00000004 + +#define VIV_FE_SNAP_PAGES 0x00000000 + +#define VIV_FE_SNAP_PAGES_HEADER 0x00000000 +#define VIV_FE_SNAP_PAGES_HEADER_OP__MASK 0xf8000000 +#define VIV_FE_SNAP_PAGES_HEADER_OP__SHIFT 27 +#define VIV_FE_SNAP_PAGES_HEADER_OP_SNAP_PAGES 0x98000000 +#define VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK 0x0000001f +#define VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT 0 +#define VIV_FE_SNAP_PAGES_HEADER_UNK0(x) (((x) << VIV_FE_SNAP_PAGES_HEADER_UNK0__SHIFT) & VIV_FE_SNAP_PAGES_HEADER_UNK0__MASK) + #endif /* CMDSTREAM_XML */ diff --git a/drivers/gpu/drm/etnaviv/common.xml.h b/drivers/gpu/drm/etnaviv/common.xml.h index 001faea80fef..07c0bf47d89f 100644 --- a/drivers/gpu/drm/etnaviv/common.xml.h +++ b/drivers/gpu/drm/etnaviv/common.xml.h @@ -8,12 +8,12 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- texdesc_3d.xml ( 3183 bytes, from 2017-12-18 16:51:59) -- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) -- common.xml ( 35468 bytes, from 2018-01-22 13:48:54) -- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) +- texdesc_3d.xml ( 3183 bytes, from 2022-11-18 09:38:25) +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32) +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32) +- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24) -Copyright (C) 2012-2018 by the following authors: +Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach @@ -65,6 +65,7 @@ DEALINGS IN THE SOFTWARE. #define chipModel_GC520 0x00000520 #define chipModel_GC530 0x00000530 #define chipModel_GC600 0x00000600 +#define chipModel_GC620 0x00000620 #define chipModel_GC700 0x00000700 #define chipModel_GC800 0x00000800 #define chipModel_GC860 0x00000860 @@ -481,5 +482,6 @@ DEALINGS IN THE SOFTWARE. #define chipMinorFeatures11_NN_INTERLEVE8 0x00000008 #define chipMinorFeatures11_TP_REORDER 0x00000010 #define chipMinorFeatures11_PE_DEPTH_ONLY_OQFIX 0x00000020 +#define chipMinorFeatures12_G2D_DEC400EX 0x00000020 #endif /* COMMON_XML */ diff --git a/drivers/gpu/drm/etnaviv/state.xml.h b/drivers/gpu/drm/etnaviv/state.xml.h index 421cb7cc0053..573e39489a27 100644 --- a/drivers/gpu/drm/etnaviv/state.xml.h +++ b/drivers/gpu/drm/etnaviv/state.xml.h @@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 26087 bytes, from 2017-12-18 16:51:59) -- common.xml ( 35468 bytes, from 2018-01-22 13:48:54) -- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) -- state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) -- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) -- state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) -- state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) -- state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) -- state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) - -Copyright (C) 2012-2017 by the following authors: +- state.xml ( 29355 bytes, from 2024-01-19 10:18:54) +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32) +- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24) +- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17) +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32) +- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03) +- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54) +- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09) +- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32) + +Copyright (C) 2012-2024 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach @@ -55,6 +55,8 @@ DEALINGS IN THE SOFTWARE. #define FE_DATA_TYPE_UNSIGNED_SHORT 0x00000003 #define FE_DATA_TYPE_INT 0x00000004 #define FE_DATA_TYPE_UNSIGNED_INT 0x00000005 +#define FE_DATA_TYPE_INT_2_10_10_10_REV 0x00000006 +#define FE_DATA_TYPE_UNSIGNED_INT_2_10_10_10_REV 0x00000007 #define FE_DATA_TYPE_FLOAT 0x00000008 #define FE_DATA_TYPE_HALF_FLOAT 0x00000009 #define FE_DATA_TYPE_FIXED 0x0000000b @@ -89,6 +91,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK 0x0000c000 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT 14 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF 0x00000000 +#define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_SIGN_EXTEND 0x00004000 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON 0x00008000 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK 0x00ff0000 #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT 16 @@ -209,7 +212,15 @@ DEALINGS IN THE SOFTWARE. #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0) (0x00000780 + 0x4*(i0)) -#define VIVS_FE_HALTI5_UNK007C4 0x000007c4 +#define VIVS_FE_HALTI5_ID_CONFIG 0x000007c4 +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_ENABLE 0x00000001 +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_ENABLE 0x00000002 +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK 0x0000ff00 +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT 8 +#define VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_VERTEX_ID_REG__MASK) +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK 0x00ff0000 +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT 16 +#define VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG(x) (((x) << VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__SHIFT) & VIVS_FE_HALTI5_ID_CONFIG_INSTANCE_ID_REG__MASK) #define VIVS_FE_HALTI5_UNK007D0(i0) (0x000007d0 + 0x4*(i0)) #define VIVS_FE_HALTI5_UNK007D0__ESIZE 0x00000004 @@ -232,6 +243,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_FE_ROBUSTNESS_UNK007F8 0x000007f8 +#define VIVS_FE_MULTI_CLUSTER_UNK007FC 0x000007fc + #define VIVS_GL 0x00000000 #define VIVS_GL_PIPE_SELECT 0x00003800 @@ -273,6 +286,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_FLUSH_CACHE_UNK11 0x00000800 #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12 0x00001000 #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13 0x00002000 +#define VIVS_GL_FLUSH_CACHE_UNK14 0x00004000 #define VIVS_GL_FLUSH_MMU 0x00003810 #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU 0x00000001 @@ -282,6 +296,8 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_FLUSH_MMU_FLUSH_UNK4 0x00000010 #define VIVS_GL_VERTEX_ELEMENT_CONFIG 0x00003814 +#define VIVS_GL_VERTEX_ELEMENT_CONFIG_UNK0 0x00000001 +#define VIVS_GL_VERTEX_ELEMENT_CONFIG_REUSE 0x00000010 #define VIVS_GL_MULTI_SAMPLE_CONFIG 0x00003818 #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK 0x00000003 @@ -368,7 +384,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_OCCLUSION_QUERY_CONTROL 0x00003830 -#define VIVS_GL_UNK03834 0x00003834 +#define VIVS_GL_VARYING_NUM_COMPONENTS2 0x00003834 #define VIVS_GL_UNK03838 0x00003838 @@ -387,7 +403,16 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_FENCE_OUT_DATA_LOW 0x0000386c -#define VIVS_GL_HALTI5_UNK03884 0x00003884 +#define VIVS_GL_USC_CONTROL 0x00003884 +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK 0x00000007 +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT 0 +#define VIVS_GL_USC_CONTROL_L1_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_L1_CACHE_RATIO__MASK) +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK 0x00000f00 +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT 8 +#define VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO(x) (((x) << VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__SHIFT) & VIVS_GL_USC_CONTROL_ATTRIB_CACHE_RATIO__MASK) +#define VIVS_GL_USC_CONTROL_UNK16__MASK 0x001f0000 +#define VIVS_GL_USC_CONTROL_UNK16__SHIFT 16 +#define VIVS_GL_USC_CONTROL_UNK16(x) (((x) << VIVS_GL_USC_CONTROL_UNK16__SHIFT) & VIVS_GL_USC_CONTROL_UNK16__MASK) #define VIVS_GL_HALTI5_SH_SPECIALS 0x00003888 #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK 0x0000007f @@ -421,7 +446,48 @@ DEALINGS IN THE SOFTWARE. #define VIVS_GL_SECURITY_UNK3904 0x00003904 +#define VIVS_GL_MULTI_CLUSTER_UNK3908 0x00003908 +#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK 0x00000007 +#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT 0 +#define VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3908_UNK0__MASK) + +#define VIVS_GL_MULTI_CLUSTER_UNK3910(i0) (0x00003910 + 0x4*(i0)) +#define VIVS_GL_MULTI_CLUSTER_UNK3910__ESIZE 0x00000004 +#define VIVS_GL_MULTI_CLUSTER_UNK3910__LEN 0x00000004 +#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK 0x000000ff +#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT 0 +#define VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK(x) (((x) << VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__SHIFT) & VIVS_GL_MULTI_CLUSTER_UNK3910_CLUSTER_ALIVE_MASK__MASK) + +#define VIVS_GL_NN_CONFIG 0x00003930 +#define VIVS_GL_NN_CONFIG_UNK0__MASK 0x00000003 +#define VIVS_GL_NN_CONFIG_UNK0__SHIFT 0 +#define VIVS_GL_NN_CONFIG_UNK0(x) (((x) << VIVS_GL_NN_CONFIG_UNK0__SHIFT) & VIVS_GL_NN_CONFIG_UNK0__MASK) +#define VIVS_GL_NN_CONFIG_DISABLE_ZDPN 0x00000004 +#define VIVS_GL_NN_CONFIG_DISABLE_SWTILING 0x00000008 +#define VIVS_GL_NN_CONFIG_SMALL_BATCH 0x00000010 +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK 0x00000060 +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT 5 +#define VIVS_GL_NN_CONFIG_DDR_BURST_SIZE(x) (((x) << VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__SHIFT) & VIVS_GL_NN_CONFIG_DDR_BURST_SIZE__MASK) +#define VIVS_GL_NN_CONFIG_UNK7 0x00000080 +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK 0x00000f00 +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT 8 +#define VIVS_GL_NN_CONFIG_NN_CORE_COUNT(x) (((x) << VIVS_GL_NN_CONFIG_NN_CORE_COUNT__SHIFT) & VIVS_GL_NN_CONFIG_NN_CORE_COUNT__MASK) +#define VIVS_GL_NN_CONFIG_UNK12 0x00001000 + +#define VIVS_GL_SRAM_REMAP_ADDRESS 0x00003938 + +#define VIVS_GL_OCB_REMAP_START 0x0000393c + +#define VIVS_GL_OCB_REMAP_END 0x00003940 + +#define VIVS_GL_TP_CONFIG 0x0000394c + +#define VIVS_GL_UNK03950 0x00003950 + #define VIVS_GL_UNK03A00 0x00003a00 +#define VIVS_GL_UNK03A00_UNK0__MASK 0x00000007 +#define VIVS_GL_UNK03A00_UNK0__SHIFT 0 +#define VIVS_GL_UNK03A00_UNK0(x) (((x) << VIVS_GL_UNK03A00_UNK0__SHIFT) & VIVS_GL_UNK03A00_UNK0__MASK) #define VIVS_GL_UNK03A04 0x00003a04 @@ -451,7 +517,7 @@ DEALINGS IN THE SOFTWARE. #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0) (0x00014640 + 0x4*(i0)) -#define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0) (0x00014680 + 0x4*(i0)) +#define VIVS_NFE_VERTEX_STREAMS_VERTEX_DIVISOR(i0) (0x00014680 + 0x4*(i0)) #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0) (0x000146c0 + 0x4*(i0)) @@ -498,5 +564,12 @@ DEALINGS IN THE SOFTWARE. #define VIVS_DUMMY_DUMMY 0x0003fffc +#define VIVS_WD 0x00000000 + +#define VIVS_WD_UNK18404 0x00018404 +#define VIVS_WD_UNK18404_UNK0__MASK 0x00000003 +#define VIVS_WD_UNK18404_UNK0__SHIFT 0 +#define VIVS_WD_UNK18404_UNK0(x) (((x) << VIVS_WD_UNK18404_UNK0__SHIFT) & VIVS_WD_UNK18404_UNK0__MASK) + #endif /* STATE_XML */ diff --git a/drivers/gpu/drm/etnaviv/state_blt.xml.h b/drivers/gpu/drm/etnaviv/state_blt.xml.h index 0e8bcf9dcc93..380d3533d645 100644 --- a/drivers/gpu/drm/etnaviv/state_blt.xml.h +++ b/drivers/gpu/drm/etnaviv/state_blt.xml.h @@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 26087 bytes, from 2017-12-18 16:51:59) -- common.xml ( 35468 bytes, from 2018-01-22 13:48:54) -- common_3d.xml ( 14615 bytes, from 2017-12-18 16:51:59) -- state_hi.xml ( 30232 bytes, from 2018-02-15 15:48:01) -- copyright.xml ( 1597 bytes, from 2016-12-08 16:37:56) -- state_2d.xml ( 51552 bytes, from 2016-12-08 16:37:56) -- state_3d.xml ( 79992 bytes, from 2017-12-18 16:51:59) -- state_blt.xml ( 13405 bytes, from 2017-12-18 16:51:59) -- state_vg.xml ( 5975 bytes, from 2016-12-08 16:37:56) - -Copyright (C) 2012-2017 by the following authors: +- state.xml ( 29355 bytes, from 2024-01-19 10:18:54) +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32) +- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24) +- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17) +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32) +- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03) +- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54) +- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09) +- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32) + +Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach diff --git a/drivers/gpu/drm/etnaviv/state_hi.xml.h b/drivers/gpu/drm/etnaviv/state_hi.xml.h index 94d5f33b1fd6..829bc528e618 100644 --- a/drivers/gpu/drm/etnaviv/state_hi.xml.h +++ b/drivers/gpu/drm/etnaviv/state_hi.xml.h @@ -8,17 +8,17 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 27198 bytes, from 2022-04-22 10:35:24) -- common.xml ( 35468 bytes, from 2020-10-28 12:56:03) -- common_3d.xml ( 15058 bytes, from 2020-10-28 12:56:03) -- state_hi.xml ( 34804 bytes, from 2022-12-02 09:06:28) -- copyright.xml ( 1597 bytes, from 2020-10-28 12:56:03) -- state_2d.xml ( 51552 bytes, from 2020-10-28 12:56:03) -- state_3d.xml ( 84445 bytes, from 2022-11-15 15:59:38) -- state_blt.xml ( 14424 bytes, from 2022-11-07 11:18:41) -- state_vg.xml ( 5975 bytes, from 2020-10-28 12:56:03) - -Copyright (C) 2012-2022 by the following authors: +- state.xml ( 29355 bytes, from 2024-01-19 10:18:54) +- common.xml ( 35664 bytes, from 2023-12-06 10:55:32) +- common_3d.xml ( 15069 bytes, from 2023-11-22 10:05:24) +- state_hi.xml ( 35854 bytes, from 2023-12-11 15:50:17) +- copyright.xml ( 1597 bytes, from 2016-11-10 13:58:32) +- state_2d.xml ( 52271 bytes, from 2023-06-02 12:35:03) +- state_3d.xml ( 89522 bytes, from 2024-01-19 10:18:54) +- state_blt.xml ( 14592 bytes, from 2023-11-22 10:05:09) +- state_vg.xml ( 5975 bytes, from 2016-11-10 13:58:32) + +Copyright (C) 2012-2023 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach @@ -275,8 +275,10 @@ DEALINGS IN THE SOFTWARE. #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE 0x00000020 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA 0x00000040 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX 0x00000080 +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU 0x00000400 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ 0x00010000 #define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ 0x00020000 +#define VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_NN 0x00400000 #define VIVS_PM_MODULE_STATUS 0x00000108 #define VIVS_PM_MODULE_STATUS_MODULE_CLOCK_GATED_FE 0x00000001 @@ -620,5 +622,11 @@ DEALINGS IN THE SOFTWARE. #define VIVS_MC_MC_AXI_SAMPLE_COUNT 0x00000574 +#define VIVS_DEC400EX 0x00000000 + +#define VIVS_DEC400EX_UNK00800 0x00000800 + +#define VIVS_DEC400EX_UNK00808 0x00000808 + #endif /* STATE_HI_XML */ -- cgit From 37d5927a856602c50fbbc3211e44dae2496fc816 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 25 Jan 2024 12:07:07 +0100 Subject: drm/etnaviv: Turn etnaviv_is_model_rev() into a function Turn the etnaviv_is_model_rev() macro into a static inline function. Use the raw model number as a parameter instead of the chipModel_GCxxxx defines. This reduces synchronization requirements for the generated headers. For newer hardware, the GCxxxx names are not the correct model names anyway. For example, model 0x8000 NPUs are called VIPNano-QI/SI(+) by VeriSilicon. Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 66 ++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 502e200900f9..5329ef2be590 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -172,10 +172,12 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value) return 0; } +static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision) +{ + return gpu->identity.model == model && + gpu->identity.revision == revision; +} -#define etnaviv_is_model_rev(gpu, mod, rev) \ - ((gpu)->identity.model == chipModel_##mod && \ - (gpu)->identity.revision == rev) #define etnaviv_field(val, field) \ (((val) & field##__MASK) >> field##__SHIFT) @@ -281,7 +283,7 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) switch (gpu->identity.instruction_count) { case 0: - if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) || + if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || gpu->identity.model == chipModel_GC880) gpu->identity.instruction_count = 512; else @@ -315,17 +317,17 @@ static void etnaviv_hw_specs(struct etnaviv_gpu *gpu) * For some cores, two varyings are consumed for position, so the * maximum varying count needs to be reduced by one. */ - if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) || - etnaviv_is_model_rev(gpu, GC4000, 0x5222) || - etnaviv_is_model_rev(gpu, GC4000, 0x5245) || - etnaviv_is_model_rev(gpu, GC4000, 0x5208) || - etnaviv_is_model_rev(gpu, GC3000, 0x5435) || - etnaviv_is_model_rev(gpu, GC2200, 0x5244) || - etnaviv_is_model_rev(gpu, GC2100, 0x5108) || - etnaviv_is_model_rev(gpu, GC2000, 0x5108) || - etnaviv_is_model_rev(gpu, GC1500, 0x5246) || - etnaviv_is_model_rev(gpu, GC880, 0x5107) || - etnaviv_is_model_rev(gpu, GC880, 0x5106)) + if (etnaviv_is_model_rev(gpu, 0x5000, 0x5434) || + etnaviv_is_model_rev(gpu, 0x4000, 0x5222) || + etnaviv_is_model_rev(gpu, 0x4000, 0x5245) || + etnaviv_is_model_rev(gpu, 0x4000, 0x5208) || + etnaviv_is_model_rev(gpu, 0x3000, 0x5435) || + etnaviv_is_model_rev(gpu, 0x2200, 0x5244) || + etnaviv_is_model_rev(gpu, 0x2100, 0x5108) || + etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || + etnaviv_is_model_rev(gpu, 0x1500, 0x5246) || + etnaviv_is_model_rev(gpu, 0x880, 0x5107) || + etnaviv_is_model_rev(gpu, 0x880, 0x5106)) gpu->identity.varyings_count -= 1; } @@ -351,7 +353,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) * Reading these two registers on GC600 rev 0x19 result in a * unhandled fault: external abort on non-linefetch */ - if (!etnaviv_is_model_rev(gpu, GC600, 0x19)) { + if (!etnaviv_is_model_rev(gpu, 0x600, 0x19)) { gpu->identity.product_id = gpu_read(gpu, VIVS_HI_CHIP_PRODUCT_ID); gpu->identity.eco_id = gpu_read(gpu, VIVS_HI_CHIP_ECO_ID); } @@ -368,7 +370,7 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) } /* Another special case */ - if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) { + if (etnaviv_is_model_rev(gpu, 0x300, 0x2201)) { u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME); if (chipDate == 0x20080814 && chipTime == 0x12051100) { @@ -387,15 +389,15 @@ static void etnaviv_hw_identify(struct etnaviv_gpu *gpu) * Fix model/rev here, so all other places can refer to this * core by its real identity. */ - if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) { + if (etnaviv_is_model_rev(gpu, 0x2000, 0xffff5450)) { gpu->identity.model = chipModel_GC3000; gpu->identity.revision &= 0xffff; } - if (etnaviv_is_model_rev(gpu, GC1000, 0x5037) && (chipDate == 0x20120617)) + if (etnaviv_is_model_rev(gpu, 0x1000, 0x5037) && (chipDate == 0x20120617)) gpu->identity.eco_id = 1; - if (etnaviv_is_model_rev(gpu, GC320, 0x5303) && (chipDate == 0x20140511)) + if (etnaviv_is_model_rev(gpu, 0x320, 0x5303) && (chipDate == 0x20140511)) gpu->identity.eco_id = 1; } @@ -641,14 +643,14 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) pmc |= BIT(15); /* Unknown bit */ /* Disable TX clock gating on affected core revisions. */ - if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) || - etnaviv_is_model_rev(gpu, GC2000, 0x5108) || - etnaviv_is_model_rev(gpu, GC7000, 0x6202) || - etnaviv_is_model_rev(gpu, GC7000, 0x6203)) + if (etnaviv_is_model_rev(gpu, 0x4000, 0x5222) || + etnaviv_is_model_rev(gpu, 0x2000, 0x5108) || + etnaviv_is_model_rev(gpu, 0x7000, 0x6202) || + etnaviv_is_model_rev(gpu, 0x7000, 0x6203)) pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX; /* Disable SE and RA clock gating on affected core revisions. */ - if (etnaviv_is_model_rev(gpu, GC7000, 0x6202)) + if (etnaviv_is_model_rev(gpu, 0x7000, 0x6202)) pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE | VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA; @@ -701,14 +703,14 @@ static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu) */ u32 pulse_eater = 0x01590880; - if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) || - etnaviv_is_model_rev(gpu, GC4000, 0x5222)) { + if (etnaviv_is_model_rev(gpu, 0x4000, 0x5208) || + etnaviv_is_model_rev(gpu, 0x4000, 0x5222)) { pulse_eater |= BIT(23); } - if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) || - etnaviv_is_model_rev(gpu, GC1000, 0x5040)) { + if (etnaviv_is_model_rev(gpu, 0x1000, 0x5039) || + etnaviv_is_model_rev(gpu, 0x1000, 0x5040)) { pulse_eater &= ~BIT(16); pulse_eater |= BIT(17); } @@ -729,8 +731,8 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) WARN_ON(!(gpu->state == ETNA_GPU_STATE_IDENTIFIED || gpu->state == ETNA_GPU_STATE_RESET)); - if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) || - etnaviv_is_model_rev(gpu, GC320, 0x5220)) && + if ((etnaviv_is_model_rev(gpu, 0x320, 0x5007) || + etnaviv_is_model_rev(gpu, 0x320, 0x5220)) && gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) { u32 mc_memory_debug; @@ -756,7 +758,7 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu) VIVS_HI_AXI_CONFIG_ARCACHE(2)); /* GC2000 rev 5108 needs a special bus config */ - if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) { + if (etnaviv_is_model_rev(gpu, 0x2000, 0x5108)) { u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG); bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK | VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK); -- cgit From e843e87abb909a042813497ab32f85a8eb03bcc8 Mon Sep 17 00:00:00 2001 From: Philipp Zabel Date: Thu, 25 Jan 2024 12:07:08 +0100 Subject: drm/etnaviv: Disable SH_EU clock gating on VIPNano-Si+ Disable SH_EU clock gating for the VIPNano-Si+ NPU on i.MX8MP and for other affected core revisions. Taken from linux-imx lf-6.1.36-2.1.0, specifically [1]. [1] https://github.com/nxp-imx/linux-imx/blob/lf-6.1.36-2.1.0/drivers/mxc/gpu-viv/hal/kernel/arch/gc_hal_kernel_hardware.c#L2747-L2761 Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 5329ef2be590..d84d73c197fc 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -654,6 +654,12 @@ static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu) pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SE | VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA; + /* Disable SH_EU clock gating on affected core revisions. */ + if (etnaviv_is_model_rev(gpu, 0x8000, 0x7200) || + etnaviv_is_model_rev(gpu, 0x8000, 0x8002) || + etnaviv_is_model_rev(gpu, 0x9200, 0x6304)) + pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_SH_EU; + pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ; pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ; -- cgit From 95e3ca33f59882f33bc73ba7748f664b042a85c1 Mon Sep 17 00:00:00 2001 From: Derek Foreman Date: Fri, 3 May 2024 14:11:58 -0500 Subject: drm/etnaviv: Read some FE registers twice On some hardware (such at the GC7000 rev 6009), these registers need to be read twice to return the correct value. Hide that in gpu_read(). Signed-off-by: Derek Foreman Signed-off-by: Lucas Stach --- drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h index 197e0037732e..31322195b9e4 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h @@ -11,6 +11,7 @@ #include "etnaviv_mmu.h" #include "etnaviv_drv.h" #include "common.xml.h" +#include "state.xml.h" struct etnaviv_gem_submit; struct etnaviv_vram_mapping; @@ -170,6 +171,13 @@ static inline void gpu_write(struct etnaviv_gpu *gpu, u32 reg, u32 data) static inline u32 gpu_read(struct etnaviv_gpu *gpu, u32 reg) { + /* On some variants, such as the GC7000r6009, some FE registers + * need two reads to be consistent. Do that extra read here and + * throw away the result. + */ + if (reg >= VIVS_FE_DMA_STATUS && reg <= VIVS_FE_AUTO_FLUSH) + readl(gpu->mmio + reg); + return readl(gpu->mmio + reg); } -- cgit From a233df7f6c8abd532748312631b0a0530d3079a7 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Wed, 15 May 2024 14:13:58 +0200 Subject: drm/etnaviv: don't disable TS on MMUv2 core when moving the linear window On MMUv2 cores the linear window is only relevant when starting the FE, before the MMU has been activated. Once the MMU is active, all accesses are translated with no way to bypass the MMU via the linear window. Thus TS ignoring the linear window offset is not an issue on cores with MMUv2 present and there is no need to disable TS when we need to move the linear window. Signed-off-by: Lucas Stach Tested-by: Joao Paulo Goncalves --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index d84d73c197fc..7502c55199b8 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -863,12 +863,15 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu) * * On MC1.0 cores the linear window offset is ignored by the TS engine, * leading to inconsistent memory views. Avoid using the offset on those - * cores if possible, otherwise disable the TS feature. + * cores if possible, otherwise disable the TS feature. MMUv2 doesn't + * expose this issue, as all TS accesses are MMU translated, so the + * linear window offset won't be used. */ cmdbuf_paddr = ALIGN_DOWN(etnaviv_cmdbuf_get_pa(&gpu->buffer), SZ_128M); if (!(gpu->identity.features & chipFeatures_PIPE_3D) || - (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) { + (gpu->identity.minor_features0 & chipMinorFeatures0_MC20) || + (gpu->identity.minor_features1 & chipMinorFeatures1_MMU_VERSION)) { if (cmdbuf_paddr >= SZ_2G) priv->mmu_global->memory_base = SZ_2G; else -- cgit From a3ecd97aa6aa444cc6c1b4c5b45d8d25068f19f6 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 21 Jun 2024 19:13:07 +0200 Subject: drm/etnaviv: switch devcoredump allocations to GFP_NOWAIT The etnaviv devcoredump is created in the GPU reset path, which must make forward progress to avoid stalling memory reclaim on unsignalled dma fences. The currently used __GFP_NORETRY does not prohibit sleeping on direct reclaim, breaking the forward progress guarantee. Switch to GFP_NOWAIT, which allows background reclaim to be triggered, but avoids any stalls waiting for direct reclaim. Signed-off-by: Lucas Stach Reviewed-by: Daniel Vetter --- drivers/gpu/drm/etnaviv/etnaviv_dump.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_dump.c b/drivers/gpu/drm/etnaviv/etnaviv_dump.c index 898f84a0fc30..2cd223461eba 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_dump.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_dump.c @@ -159,8 +159,7 @@ void etnaviv_core_dump(struct etnaviv_gem_submit *submit) file_size += sizeof(*iter.hdr) * n_obj; /* Allocate the file in vmalloc memory, it's likely to be big */ - iter.start = __vmalloc(file_size, GFP_KERNEL | __GFP_NOWARN | - __GFP_NORETRY); + iter.start = __vmalloc(file_size, GFP_NOWAIT); if (!iter.start) { mutex_unlock(&submit->mmu_context->lock); dev_warn(gpu->dev, "failed to allocate devcoredump file\n"); @@ -230,5 +229,5 @@ void etnaviv_core_dump(struct etnaviv_gem_submit *submit) etnaviv_core_dump_header(&iter, ETDUMP_BUF_END, iter.data); - dev_coredumpv(gpu->dev, iter.start, iter.data - iter.start, GFP_KERNEL); + dev_coredumpv(gpu->dev, iter.start, iter.data - iter.start, GFP_NOWAIT); } -- cgit From 58979ad6330a70450ed78837be3095107d022ea9 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 21 Jun 2024 19:11:06 +0200 Subject: drm/etnaviv: fix DMA direction handling for cached RW buffers The dma sync operation needs to be done with DMA_BIDIRECTIONAL when the BO is prepared for both read and write operations. Fixes: a8c21a5451d8 ("drm/etnaviv: add initial etnaviv DRM driver") Signed-off-by: Lucas Stach Reviewed-by: Philipp Zabel Reviewed-by: Christian Gmeiner --- drivers/gpu/drm/etnaviv/etnaviv_gem.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem.c b/drivers/gpu/drm/etnaviv/etnaviv_gem.c index 71a6d2b1c80f..5c0c9d4e3be1 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem.c @@ -355,9 +355,11 @@ static void *etnaviv_gem_vmap_impl(struct etnaviv_gem_object *obj) static inline enum dma_data_direction etnaviv_op_to_dma_dir(u32 op) { - if (op & ETNA_PREP_READ) + op &= ETNA_PREP_READ | ETNA_PREP_WRITE; + + if (op == ETNA_PREP_READ) return DMA_FROM_DEVICE; - else if (op & ETNA_PREP_WRITE) + else if (op == ETNA_PREP_WRITE) return DMA_TO_DEVICE; else return DMA_BIDIRECTIONAL; -- cgit From beb311ff0f2e1fcd0f033fcd1be45de083efc421 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 21 Jun 2024 22:00:20 +0200 Subject: drm/etnaviv: reduce number of ktime_get calls in IRQ handler A single IRQ might signal the completion of multiple jobs/fences at once. There is no point in attaching a new timestamp to each fence that only differs in when exactly the IRQ handler was able to process this fence. Get a single timestamp when the IRQ handler has determined that there are completed jobs and reuse this for all fences that get signalled by the handler. Signed-off-by: Lucas Stach Reviewed-by: Philipp Zabel Reviewed-by: Christian Gmeiner --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 7502c55199b8..7c7f97793ddd 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1548,6 +1548,7 @@ static irqreturn_t irq_handler(int irq, void *data) u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE); if (intr != 0) { + ktime_t now = ktime_get(); int event; pm_runtime_mark_last_busy(gpu->dev); @@ -1597,7 +1598,7 @@ static irqreturn_t irq_handler(int irq, void *data) */ if (fence_after(fence->seqno, gpu->completed_fence)) gpu->completed_fence = fence->seqno; - dma_fence_signal(fence); + dma_fence_signal_timestamp(fence, now); event_free(gpu, event); } -- cgit From 704d3d60fec451f37706368d9d3e320322978986 Mon Sep 17 00:00:00 2001 From: Lucas Stach Date: Fri, 21 Jun 2024 21:59:19 +0200 Subject: drm/etnaviv: don't block scheduler when GPU is still active Since 45ecaea73883 ("drm/sched: Partial revert of 'drm/sched: Keep s_fence->parent pointer'") still active jobs aren't put back in the pending list on drm_sched_start(), as they don't have a active parent fence anymore, so if the GPU is still working and the timeout is extended, all currently active jobs will be freed. To avoid prematurely freeing jobs that are still active on the GPU, don't block the scheduler until we are fully committed to actually reset the GPU. As the current job is already removed from the pending list and will not be put back when drm_sched_start() isn't called, we must make sure to put the job back on the pending list when extending the timeout. Cc: stable@vger.kernel.org #6.0 Signed-off-by: Lucas Stach Reviewed-by: Philipp Zabel Reviewed-by: Christian Gmeiner --- drivers/gpu/drm/etnaviv/etnaviv_sched.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_sched.c b/drivers/gpu/drm/etnaviv/etnaviv_sched.c index c4b04b0dee16..62dcfdc7894d 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_sched.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_sched.c @@ -38,9 +38,6 @@ static enum drm_gpu_sched_stat etnaviv_sched_timedout_job(struct drm_sched_job u32 dma_addr; int change; - /* block scheduler */ - drm_sched_stop(&gpu->sched, sched_job); - /* * If the GPU managed to complete this jobs fence, the timout is * spurious. Bail out. @@ -63,6 +60,9 @@ static enum drm_gpu_sched_stat etnaviv_sched_timedout_job(struct drm_sched_job goto out_no_timeout; } + /* block scheduler */ + drm_sched_stop(&gpu->sched, sched_job); + if(sched_job) drm_sched_increase_karma(sched_job); @@ -76,8 +76,7 @@ static enum drm_gpu_sched_stat etnaviv_sched_timedout_job(struct drm_sched_job return DRM_GPU_SCHED_STAT_NOMINAL; out_no_timeout: - /* restart scheduler after GPU is usable again */ - drm_sched_start(&gpu->sched, true); + list_add(&sched_job->list, &sched_job->sched->pending_list); return DRM_GPU_SCHED_STAT_NOMINAL; } -- cgit