From 7c4f1f1830648bbdce02b13ff5f215c7400e7ea0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 4 Mar 2023 13:33:41 +0100 Subject: arm64: dts: mba6ulx: correct GPIO keys wakeup gpio-keys,wakeup is a deprecated property. Link: https://lore.kernel.org/r/20230304123341.34223-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/mba6ulx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi index 5bf831b072d6..e25f8f209760 100644 --- a/arch/arm/boot/dts/mba6ulx.dtsi +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -57,7 +57,7 @@ label = "POWER"; linux,code = ; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - gpio-key,wakeup; + wakeup-source; }; }; -- cgit From 0022cec7edecd5ea6796dfe0d75330c55dd07a67 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:39 +0200 Subject: arm64: dts: apm: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: apm-mustang.dtb: l2-cache-0: 'cache-level' is a required property apm-mustang.dtb: l2-cache-0: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223139.115044-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/apm/apm-shadowcat.dtsi | 8 ++++++++ arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi index 70a10bcafcff..377660d705d1 100644 --- a/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi +++ b/arch/arm64/boot/dts/apm/apm-shadowcat.dtsi @@ -97,15 +97,23 @@ }; xgene_L2_0: l2-cache-0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_1: l2-cache-1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_2: l2-cache-2 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_3: l2-cache-3 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/apm/apm-storm.dtsi b/arch/arm64/boot/dts/apm/apm-storm.dtsi index d73e809fe41a..efa79209f4b2 100644 --- a/arch/arm64/boot/dts/apm/apm-storm.dtsi +++ b/arch/arm64/boot/dts/apm/apm-storm.dtsi @@ -81,15 +81,23 @@ }; xgene_L2_0: l2-cache-0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_1: l2-cache-1 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_2: l2-cache-2 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; xgene_L2_3: l2-cache-3 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; -- cgit From 9f921604a91c637eb57e57668045ca5c21f49f05 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:40 +0200 Subject: arm64: dts: amazon: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: alpine-v3-evp.dtb: cache@0: 'cache-unified' is a dependency of 'cache-size' Link: https://lore.kernel.org/r/20230421223141.115072-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/amazon/alpine-v3.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi index 73a352ea8fd5..39481d7fd7d4 100644 --- a/arch/arm64/boot/dts/amazon/alpine-v3.dtsi +++ b/arch/arm64/boot/dts/amazon/alpine-v3.dtsi @@ -250,6 +250,7 @@ cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; cluster1_l2: cache@100 { @@ -258,6 +259,7 @@ cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; cluster2_l2: cache@200 { @@ -266,6 +268,7 @@ cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; cluster3_l2: cache@300 { @@ -274,6 +277,7 @@ cache-line-size = <64>; cache-sets = <2048>; cache-level = <2>; + cache-unified; }; }; -- cgit From a0936e9edf16750867b65c8f2017352f1ea3dea8 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:32:14 +0200 Subject: arm64: dts: hisilicon: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified properties to fix warnings like: hi3660-hikey960.dtb: l2-cache0: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223215.115666-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 2 ++ arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 2 ++ arch/arm64/boot/dts/hisilicon/hip05.dtsi | 4 ++++ arch/arm64/boot/dts/hisilicon/hip06.dtsi | 4 ++++ arch/arm64/boot/dts/hisilicon/hip07.dtsi | 16 ++++++++++++++++ 5 files changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi index a57f35eb5ef6..7e137a884ae5 100644 --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi @@ -204,11 +204,13 @@ A53_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; A73_L2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index f6d3202b0d1a..872e9c73c422 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -187,11 +187,13 @@ CLUSTER0_L2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; CLUSTER1_L2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip05.dtsi b/arch/arm64/boot/dts/hisilicon/hip05.dtsi index 5b2b1bfd0d2a..65ddc0698f82 100644 --- a/arch/arm64/boot/dts/hisilicon/hip05.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip05.dtsi @@ -212,21 +212,25 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip06.dtsi b/arch/arm64/boot/dts/hisilicon/hip06.dtsi index 291c2ee38288..c588848bfdeb 100644 --- a/arch/arm64/boot/dts/hisilicon/hip06.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip06.dtsi @@ -212,21 +212,25 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/hisilicon/hip07.dtsi b/arch/arm64/boot/dts/hisilicon/hip07.dtsi index 8a9436ca2531..595abe339c5d 100644 --- a/arch/arm64/boot/dts/hisilicon/hip07.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hip07.dtsi @@ -843,81 +843,97 @@ cluster0_l2: l2-cache0 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster1_l2: l2-cache1 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster2_l2: l2-cache2 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster3_l2: l2-cache3 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster4_l2: l2-cache4 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster5_l2: l2-cache5 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster6_l2: l2-cache6 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster7_l2: l2-cache7 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster8_l2: l2-cache8 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster9_l2: l2-cache9 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster10_l2: l2-cache10 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster11_l2: l2-cache11 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster12_l2: l2-cache12 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster13_l2: l2-cache13 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster14_l2: l2-cache14 { compatible = "cache"; cache-level = <2>; + cache-unified; }; cluster15_l2: l2-cache15 { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- cgit From 7a242135a44d32a6a8563fc74f11d5a100b7cf0a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:50 +0200 Subject: arm64: dts: realtek: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: rtd1293-ds418j.dtb: l2-cache: 'cache-level' is a required property rtd1293-ds418j.dtb: l2-cache: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223151.115243-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/realtek/rtd1293.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd1295.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd1296.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd1395.dtsi | 2 ++ arch/arm64/boot/dts/realtek/rtd16xx.dtsi | 4 ++++ 5 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/realtek/rtd1293.dtsi b/arch/arm64/boot/dts/realtek/rtd1293.dtsi index 2d92b56ac94d..d0c9387ac17a 100644 --- a/arch/arm64/boot/dts/realtek/rtd1293.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1293.dtsi @@ -30,6 +30,8 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1295.dtsi b/arch/arm64/boot/dts/realtek/rtd1295.dtsi index 1402abe80ea1..b7f63102f2dd 100644 --- a/arch/arm64/boot/dts/realtek/rtd1295.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1295.dtsi @@ -44,6 +44,8 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1296.dtsi b/arch/arm64/boot/dts/realtek/rtd1296.dtsi index fb864a139c97..4f805f576cef 100644 --- a/arch/arm64/boot/dts/realtek/rtd1296.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1296.dtsi @@ -44,6 +44,8 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd1395.dtsi b/arch/arm64/boot/dts/realtek/rtd1395.dtsi index 05c9216a87ee..2efe5b25c83c 100644 --- a/arch/arm64/boot/dts/realtek/rtd1395.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd1395.dtsi @@ -44,6 +44,8 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; diff --git a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi index bf4d9e917925..34802cc62983 100644 --- a/arch/arm64/boot/dts/realtek/rtd16xx.dtsi +++ b/arch/arm64/boot/dts/realtek/rtd16xx.dtsi @@ -88,11 +88,15 @@ l2: l2-cache { compatible = "cache"; next-level-cache = <&l3>; + cache-level = <2>; + cache-unified; }; l3: l3-cache { compatible = "cache"; + cache-level = <3>; + cache-unified; }; }; -- cgit From 3740a577eaaa224db6e4bd3b6fdaea2fb3729814 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:45 +0200 Subject: arm64: dts: synaptics: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: berlin4ct-stb.dtb: cache: 'cache-level' is a required property berlin4ct-stb.dtb: cache: 'cache-unified' is a required property Link: https://lore.kernel.org/r/20230421223145.115129-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/synaptics/berlin4ct.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi index dc12350b9fc8..53d616c3cfed 100644 --- a/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi +++ b/arch/arm64/boot/dts/synaptics/berlin4ct.dtsi @@ -64,6 +64,8 @@ l2: cache { compatible = "cache"; + cache-level = <2>; + cache-unified; }; idle-states { -- cgit From 4c84cced9304303ed1c73e35277891249e3cc2cd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:37 +0200 Subject: arm64: dts: allwinner: a64: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified property to fix warnings like: sun50i-a64-pine64-lts.dtb: l2-cache: 'cache-unified' is a required property Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230421223137.115015-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 62f45f71ec65..a9c7f82c2c66 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -93,6 +93,7 @@ L2: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; -- cgit From f217d94fc632fece2a41030c2eebc4ed34a48b2a Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 22 Apr 2023 00:31:55 +0200 Subject: arm64: dts: microchip: add missing cache properties As all level 2 and level 3 caches are unified, add required cache-unified and cache-level properties to fix warnings like: sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property Link: https://lore.kernel.org/r/20230421223155.115339-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 0367a00a269b..6f7651b06478 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -52,6 +52,8 @@ }; L2_0: l2-cache0 { compatible = "cache"; + cache-level = <2>; + cache-unified; }; }; -- cgit From 70be83708c925b3f72c508e4756e48ad2330c830 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 21 Feb 2023 11:50:37 +0100 Subject: arm64: dts: microchip: sparx5: do not use PSCI on reference boards PSCI is not implemented on SparX-5 at all, there is no ATF and U-boot that is shipped does not implement it as well. I have tried flashing the latest BSP 2022.12 U-boot which did not work. After contacting Microchip, they confirmed that there is no ATF for the SoC nor PSCI implementation which is unfortunate in 2023. So, disable PSCI as otherwise kernel crashes as soon as it tries probing PSCI with, and the crash is only visible if earlycon is used. Since PSCI is not implemented, switch core bringup to use spin-tables which are implemented in the vendor U-boot and actually work. Tested on PCB134 with eMMC (VSC5640EV). Fixes: 6694aee00a4b ("arm64: dts: sparx5: Add basic cpu support") Signed-off-by: Robert Marko Acked-by: Steen Hegelund Link: https://lore.kernel.org/r/20230221105039.316819-1-robert.marko@sartura.hr Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 +- arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi | 12 ++++++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 6f7651b06478..ed6f57ce38f7 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -63,7 +63,7 @@ interrupt-affinity = <&cpu0>, <&cpu1>; }; - psci { + psci: psci { compatible = "arm,psci-0.2"; method = "smc"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi index 9d1a082de3e2..32bb76b3202a 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb_common.dtsi @@ -6,6 +6,18 @@ /dts-v1/; #include "sparx5.dtsi" +&psci { + status = "disabled"; +}; + +&cpu0 { + enable-method = "spin-table"; +}; + +&cpu1 { + enable-method = "spin-table"; +}; + &uart0 { status = "okay"; }; -- cgit From a34ebb17546d209cbb0b9b2c94303f25749557d7 Mon Sep 17 00:00:00 2001 From: Robert Marko Date: Tue, 21 Feb 2023 11:50:38 +0100 Subject: arm64: dts: microchip: sparx5: correct CPU address-cells There is no reason for CPU node #address-cells to be set at 2, so lets change them to 1 and update the reg property accordingly. Signed-off-by: Robert Marko Link: https://lore.kernel.org/r/20230221105039.316819-2-robert.marko@sartura.hr Signed-off-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index ed6f57ce38f7..4996499cc738 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -24,7 +24,7 @@ }; cpus { - #address-cells = <2>; + #address-cells = <1>; #size-cells = <0>; cpu-map { cluster0 { @@ -39,14 +39,14 @@ cpu0: cpu@0 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x0>; + reg = <0x0>; enable-method = "psci"; next-level-cache = <&L2_0>; }; cpu1: cpu@1 { compatible = "arm,cortex-a53"; device_type = "cpu"; - reg = <0x0 0x1>; + reg = <0x1>; enable-method = "psci"; next-level-cache = <&L2_0>; }; -- cgit From d5e64404e77c19ec5bd687b34a11eec0263f1aa8 Mon Sep 17 00:00:00 2001 From: Michael Walle Date: Wed, 20 Apr 2022 21:46:00 +0200 Subject: arm64: dts: sparx5: rename pinctrl nodes The pinctrl device tree binding will be converted to YAML format. Rename the pin nodes so they end with "-pins" to match the schema. Signed-off-by: Michael Walle Link: https://lore.kernel.org/r/20220420194600.3416282-1-michael@walle.cc Link: https://lore.kernel.org/r/20220319204628.1759635-5-michael@walle.cc Signed-off-by: Krzysztof Kozlowski --- .../boot/dts/microchip/sparx5_pcb134_board.dtsi | 26 +++++++++++----------- .../boot/dts/microchip/sparx5_pcb135_board.dtsi | 10 ++++----- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index ed94a80bf05f..f3e226de5e5e 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -325,69 +325,69 @@ }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", "GPIO_20", "GPIO_22", "GPIO_36", "GPIO_35", "GPIO_50", "GPIO_51", "GPIO_56", "GPIO_57"; function = "twi_scl_m"; output-low; }; - i2cmux_0: i2cmux-0 { + i2cmux_0: i2cmux-0-pins { pins = "GPIO_16"; function = "twi_scl_m"; output-high; }; - i2cmux_1: i2cmux-1 { + i2cmux_1: i2cmux-1-pins { pins = "GPIO_17"; function = "twi_scl_m"; output-high; }; - i2cmux_2: i2cmux-2 { + i2cmux_2: i2cmux-2-pins { pins = "GPIO_18"; function = "twi_scl_m"; output-high; }; - i2cmux_3: i2cmux-3 { + i2cmux_3: i2cmux-3-pins { pins = "GPIO_19"; function = "twi_scl_m"; output-high; }; - i2cmux_4: i2cmux-4 { + i2cmux_4: i2cmux-4-pins { pins = "GPIO_20"; function = "twi_scl_m"; output-high; }; - i2cmux_5: i2cmux-5 { + i2cmux_5: i2cmux-5-pins { pins = "GPIO_22"; function = "twi_scl_m"; output-high; }; - i2cmux_6: i2cmux-6 { + i2cmux_6: i2cmux-6-pins { pins = "GPIO_36"; function = "twi_scl_m"; output-high; }; - i2cmux_7: i2cmux-7 { + i2cmux_7: i2cmux-7-pins { pins = "GPIO_35"; function = "twi_scl_m"; output-high; }; - i2cmux_8: i2cmux-8 { + i2cmux_8: i2cmux-8-pins { pins = "GPIO_50"; function = "twi_scl_m"; output-high; }; - i2cmux_9: i2cmux-9 { + i2cmux_9: i2cmux-9-pins { pins = "GPIO_51"; function = "twi_scl_m"; output-high; }; - i2cmux_10: i2cmux-10 { + i2cmux_10: i2cmux-10-pins { pins = "GPIO_56"; function = "twi_scl_m"; output-high; }; - i2cmux_11: i2cmux-11 { + i2cmux_11: i2cmux-11-pins { pins = "GPIO_57"; function = "twi_scl_m"; output-high; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi index 0760cf2e48bc..82ce007d9959 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_board.dtsi @@ -59,28 +59,28 @@ }; &gpio { - i2cmux_pins_i: i2cmux-pins-i { + i2cmux_pins_i: i2cmux-pins { pins = "GPIO_35", "GPIO_36", "GPIO_50", "GPIO_51"; function = "twi_scl_m"; output-low; }; - i2cmux_s29: i2cmux-0 { + i2cmux_s29: i2cmux-0-pins { pins = "GPIO_35"; function = "twi_scl_m"; output-high; }; - i2cmux_s30: i2cmux-1 { + i2cmux_s30: i2cmux-1-pins { pins = "GPIO_36"; function = "twi_scl_m"; output-high; }; - i2cmux_s31: i2cmux-2 { + i2cmux_s31: i2cmux-2-pins { pins = "GPIO_50"; function = "twi_scl_m"; output-high; }; - i2cmux_s32: i2cmux-3 { + i2cmux_s32: i2cmux-3-pins { pins = "GPIO_51"; function = "twi_scl_m"; output-high; -- cgit