From e82b84538ad8dddce4058a89aa3383d54f7935f8 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 16 Mar 2023 11:20:30 +0100 Subject: dt-bindings: gpu: mali-bifrost: Split out MediaTek power-domains variation In preparation for adding new bindings for new MediaTek SoCs, split out the power-domains variation from the `else` in the current mediatek,mt8183-mali conditional. The sram-supply part is left in place to be disallowed for anything that is not compatible with "mediatek,mt8183-mali" as this regulator is MediaTek-specific and it is, and will ever be, used only for this specific string due to the addition of the mediatek-regulator-coupler driver. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Reviewed-by: Rob Herring Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-2-angelogioacchino.delregno@collabora.com --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 78964c140b46..7e110751353e 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -109,6 +109,9 @@ allOf: contains: const: amlogic,meson-g12a-mali then: + properties: + power-domains: + maxItems: 1 required: - resets - if: @@ -131,6 +134,8 @@ allOf: - const: gpu - const: bus - const: bus_ace + power-domains: + maxItems: 1 resets: minItems: 3 reset-names: @@ -164,8 +169,6 @@ allOf: - power-domain-names else: properties: - power-domains: - maxItems: 1 sram-supply: false - if: properties: @@ -180,6 +183,8 @@ allOf: items: - const: gpu - const: bus + power-domains: + maxItems: 1 required: - clock-names -- cgit From eccda2744f0ffb0d5050c83c5ee415fadcd3670c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 16 Mar 2023 11:20:31 +0100 Subject: dt-bindings: gpu: mali-bifrost: Set power-domains maxItems to 5 In preparation for adding (and fixing) power-domain-names and MediaTek MT8192 bindings, allow up to five items for power-domains. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Reviewed-by: Rob Herring Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-3-angelogioacchino.delregno@collabora.com --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 7e110751353e..5b7f1c9d2b30 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -63,7 +63,7 @@ properties: power-domains: minItems: 1 - maxItems: 3 + maxItems: 5 resets: minItems: 1 @@ -157,6 +157,7 @@ allOf: properties: power-domains: minItems: 3 + maxItems: 3 power-domain-names: items: - const: core0 -- cgit From aeb737902d863834ca3f7adb928520a8c70add84 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 16 Mar 2023 11:20:32 +0100 Subject: dt-bindings: gpu: mali-bifrost: Fix power-domain-names validation Commit ("dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183") incorrectly introduced power domain names for MT8183, causing validation issues. Add power-domain-names to the base schema, allowing a maximum of five elements; since platforms having a single power domain don't need any actual domain name, disallow that for each sub-schema. Fixes: a7a596cd3115 ("dt-bindings: gpu: mali-bifrost: Add Mediatek MT8183") Signed-off-by: AngeloGioacchino Del Regno Tested-by: Chen-Yu Tsai Reviewed-by: Rob Herring Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-4-angelogioacchino.delregno@collabora.com --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 5b7f1c9d2b30..7c61524aae26 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -65,6 +65,10 @@ properties: minItems: 1 maxItems: 5 + power-domain-names: + minItems: 2 + maxItems: 5 + resets: minItems: 1 maxItems: 3 @@ -112,6 +116,7 @@ allOf: properties: power-domains: maxItems: 1 + power-domain-names: false required: - resets - if: @@ -136,6 +141,7 @@ allOf: - const: bus_ace power-domains: maxItems: 1 + power-domain-names: false resets: minItems: 3 reset-names: @@ -186,6 +192,7 @@ allOf: - const: bus power-domains: maxItems: 1 + power-domain-names: false required: - clock-names -- cgit From 13a8fc8ae951ab746d5fd36254f9b1d6e938b15e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 16 Mar 2023 11:20:33 +0100 Subject: dt-bindings: gpu: mali-bifrost: Add sub-schema for MT8192's power domains MediaTek MT8192 (and similar) needs five power domains for the Mali GPU and no sram-supply: change the binding to allow so by also introducing power-domain-names in the generic binding; while at it, also disallow the newly introduced power-domain-names for all non-MediaTek bindings. Fixes: 5d82e74a97c2 ("dt-bindings: Add compatible for Mali Valhall (JM)") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-5-angelogioacchino.delregno@collabora.com --- .../devicetree/bindings/gpu/arm,mali-bifrost.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 7c61524aae26..9ede51427012 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -177,6 +177,25 @@ allOf: else: properties: sram-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8192-mali + then: + properties: + power-domains: + minItems: 5 + power-domain-names: + items: + - const: core0 + - const: core1 + - const: core2 + - const: core3 + - const: core4 + required: + - power-domains + - power-domain-names - if: properties: compatible: -- cgit From 1f03cb1b0c5558f3523b4003550fc89fe4dc5c6e Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 16 Mar 2023 11:20:34 +0100 Subject: dt-bindings: gpu: mali-bifrost: Add new MT8183 compatible Since new platform data was required in Panfrost for getting GPU DVFS finally working on MediaTek SoCs, add a new "mediatek,mt8183b-mali" compatible. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-6-angelogioacchino.delregno@collabora.com --- .../devicetree/bindings/gpu/arm,mali-bifrost.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 9ede51427012..63b993d5fd87 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -19,6 +19,7 @@ properties: - enum: - amlogic,meson-g12a-mali - mediatek,mt8183-mali + - mediatek,mt8183b-mali - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali @@ -177,6 +178,24 @@ allOf: else: properties: sram-supply: false + - if: + properties: + compatible: + contains: + const: mediatek,mt8183b-mali + then: + properties: + power-domains: + minItems: 3 + maxItems: 3 + power-domain-names: + items: + - const: core0 + - const: core1 + - const: core2 + required: + - power-domains + - power-domain-names - if: properties: compatible: -- cgit From 0b2cf514029986f741c4c4b80b28e402361dac70 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 16 Mar 2023 11:20:35 +0100 Subject: dt-bindings: gpu: mali-bifrost: Add support for MediaTek MT8186 MT8186 has a Mali-G52 MC2 2EE GPU (two cores): add a binding with two power domains (one per core) for it. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Reviewed-by: Rob Herring Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-7-angelogioacchino.delregno@collabora.com --- .../devicetree/bindings/gpu/arm,mali-bifrost.yaml | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 63b993d5fd87..3d0d96913b1b 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -20,6 +20,7 @@ properties: - amlogic,meson-g12a-mali - mediatek,mt8183-mali - mediatek,mt8183b-mali + - mediatek,mt8186-mali - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali @@ -196,6 +197,23 @@ allOf: required: - power-domains - power-domain-names + - if: + properties: + compatible: + contains: + const: mediatek,mt8186-mali + then: + properties: + power-domains: + minItems: 2 + maxItems: 2 + power-domain-names: + items: + - const: core0 + - const: core1 + required: + - power-domains + - power-domain-names - if: properties: compatible: -- cgit From 2ade28304d91963862c434cd954d5da84534d851 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 16 Mar 2023 11:20:36 +0100 Subject: dt-bindings: gpu: mali-bifrost: Add compatible for MT8195 SoC The MediaTek MT8195 SoC has a Mali G57 MC5 (Valhall-JM) and has the same number of power domains and requirements as MT8192 in terms of bindings. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-8-angelogioacchino.delregno@collabora.com --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 3d0d96913b1b..3eb9a4e95e92 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -27,6 +27,11 @@ properties: - rockchip,px30-mali - rockchip,rk3568-mali - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable + - items: + - enum: + - mediatek,mt8195-mali + - const: mediatek,mt8192-mali + - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable - items: - enum: - mediatek,mt8192-mali -- cgit From a769a7af9d0df53d638fedc87332ca0aec80267b Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 16 Mar 2023 11:20:37 +0100 Subject: drm/panfrost: Increase MAX_PM_DOMAINS to 5 Increase the MAX_PM_DOMAINS constant from 3 to 5, to support the extra power domains required by the Mali-G57 on the MT8192. Signed-off-by: Alyssa Rosenzweig Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-9-angelogioacchino.delregno@collabora.com --- drivers/gpu/drm/panfrost/panfrost_device.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h index d9ba68cffb77..b0126b9fbadc 100644 --- a/drivers/gpu/drm/panfrost/panfrost_device.h +++ b/drivers/gpu/drm/panfrost/panfrost_device.h @@ -23,7 +23,7 @@ struct panfrost_job; struct panfrost_perfcnt; #define NUM_JOB_SLOTS 3 -#define MAX_PM_DOMAINS 3 +#define MAX_PM_DOMAINS 5 struct panfrost_features { u16 id; -- cgit From 6ba1fd698620dcc328f897aa4d3c3bb8f7543e00 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 16 Mar 2023 11:20:38 +0100 Subject: drm/panfrost: Add the MT8192 GPU ID MediaTek MT8192 has a Mali-G57 with a special GPU ID. Add its GPU ID, but treat it as otherwise identical to a standard Mali-G57. We do _not_ fix up the GPU ID here -- userspace needs to be aware of the special GPU ID, in case we find functional differences between MediaTek's implementation and the standard Mali-G57 down the line. Signed-off-by: Alyssa Rosenzweig Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-10-angelogioacchino.delregno@collabora.com --- drivers/gpu/drm/panfrost/panfrost_gpu.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c index 6452e4e900dd..d28b99732dde 100644 --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c @@ -204,6 +204,14 @@ static const struct panfrost_model gpu_models[] = { GPU_MODEL(g57, 0x9001, GPU_REV(g57, 0, 0)), + + /* MediaTek MT8192 has a Mali-G57 with a different GPU ID from the + * standard. Arm's driver does not appear to handle this model. + * ChromeOS has a hack downstream for it. Treat it as equivalent to + * standard Mali-G57 for now. + */ + GPU_MODEL(g57, 0x9003, + GPU_REV(g57, 0, 0)), }; static void panfrost_gpu_init_features(struct panfrost_device *pfdev) -- cgit From 4c6811800cb48b5a0329f6e4de11d26000671553 Mon Sep 17 00:00:00 2001 From: Alyssa Rosenzweig Date: Thu, 16 Mar 2023 11:20:39 +0100 Subject: drm/panfrost: Add mediatek,mt8192-mali compatible Required for Mali-G57 on the Mediatek MT8192 and MT8195, which uses even more power domains than the MT8183 before it. Signed-off-by: Alyssa Rosenzweig [Angelo: Removed unneeded "sram" supply, added mt8195 to commit description] Co-developed-by: AngeloGioacchino Del Regno Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-11-angelogioacchino.delregno@collabora.com --- drivers/gpu/drm/panfrost/panfrost_drv.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c index f49096f53141..45c4accb6a1e 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -656,6 +656,16 @@ static const struct panfrost_compatible mediatek_mt8183_data = { .pm_domain_names = mediatek_mt8183_pm_domains, }; +static const char * const mediatek_mt8192_supplies[] = { "mali", NULL }; +static const char * const mediatek_mt8192_pm_domains[] = { "core0", "core1", "core2", + "core3", "core4" }; +static const struct panfrost_compatible mediatek_mt8192_data = { + .num_supplies = ARRAY_SIZE(mediatek_mt8192_supplies) - 1, + .supply_names = mediatek_mt8192_supplies, + .num_pm_domains = ARRAY_SIZE(mediatek_mt8192_pm_domains), + .pm_domain_names = mediatek_mt8192_pm_domains, +}; + static const struct of_device_id dt_match[] = { /* Set first to probe before the generic compatibles */ { .compatible = "amlogic,meson-gxm-mali", @@ -674,6 +684,7 @@ static const struct of_device_id dt_match[] = { { .compatible = "arm,mali-bifrost", .data = &default_data, }, { .compatible = "arm,mali-valhall-jm", .data = &default_data, }, { .compatible = "mediatek,mt8183-mali", .data = &mediatek_mt8183_data }, + { .compatible = "mediatek,mt8192-mali", .data = &mediatek_mt8192_data }, {} }; MODULE_DEVICE_TABLE(of, dt_match); -- cgit From ab1a072c05a8f4f2ce3292140b30ea0b64ad260c Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 16 Mar 2023 11:20:40 +0100 Subject: drm/panfrost: Add new compatible for Mali on the MT8183 SoC The "mediatek,mt8183-mali" compatible uses platform data that calls for getting (and managing) two regulators ("mali" and "sram") but devfreq does not support this usecase, resulting in DVFS not working. Since a lot of MediaTek SoCs need to set the voltages for the GPU SRAM regulator in a specific relation to the GPU VCORE regulator, a MediaTek SoC specific driver was introduced to automatically satisfy, through coupling, these constraints: this means that there is at all no need to manage both regulators in panfrost but to otherwise just manage the main "mali" (-> gpu vcore) regulator instead. Keeping in mind that we cannot break the ABI, the most sensible route (avoiding hacks and uselessly overcomplicated code) to get a MT8183 node with one power supply was to add a new "mediatek,mt8183b-mali" compatible, which effectively deprecates the former. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-12-angelogioacchino.delregno@collabora.com --- drivers/gpu/drm/panfrost/panfrost_drv.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c index 45c4accb6a1e..4f39b410302c 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -647,6 +647,14 @@ static const struct panfrost_compatible amlogic_data = { .vendor_quirk = panfrost_gpu_amlogic_quirk, }; +/* + * The old data with two power supplies for MT8183 is here only to + * keep retro-compatibility with older devicetrees, as DVFS will + * not work with this one. + * + * On new devicetrees please use the _b variant with a single and + * coupled regulators instead. + */ static const char * const mediatek_mt8183_supplies[] = { "mali", "sram", NULL }; static const char * const mediatek_mt8183_pm_domains[] = { "core0", "core1", "core2" }; static const struct panfrost_compatible mediatek_mt8183_data = { @@ -656,6 +664,14 @@ static const struct panfrost_compatible mediatek_mt8183_data = { .pm_domain_names = mediatek_mt8183_pm_domains, }; +static const char * const mediatek_mt8183_b_supplies[] = { "mali", NULL }; +static const struct panfrost_compatible mediatek_mt8183_b_data = { + .num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1, + .supply_names = mediatek_mt8183_b_supplies, + .num_pm_domains = ARRAY_SIZE(mediatek_mt8183_pm_domains), + .pm_domain_names = mediatek_mt8183_pm_domains, +}; + static const char * const mediatek_mt8192_supplies[] = { "mali", NULL }; static const char * const mediatek_mt8192_pm_domains[] = { "core0", "core1", "core2", "core3", "core4" }; @@ -684,6 +700,7 @@ static const struct of_device_id dt_match[] = { { .compatible = "arm,mali-bifrost", .data = &default_data, }, { .compatible = "arm,mali-valhall-jm", .data = &default_data, }, { .compatible = "mediatek,mt8183-mali", .data = &mediatek_mt8183_data }, + { .compatible = "mediatek,mt8183b-mali", .data = &mediatek_mt8183_b_data }, { .compatible = "mediatek,mt8192-mali", .data = &mediatek_mt8192_data }, {} }; -- cgit From 901cdf66e86a9db8443abe3d5c6028975be175df Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 16 Mar 2023 11:20:41 +0100 Subject: drm/panfrost: Add support for Mali on the MT8186 SoC MediaTek MT8186 has a Mali-G52 MC2 2EE (Bifrost): add a new compatible and platform data using the same supplies list as "mt8183_b" (only one regulator), and a new pm_domains list with only two power domains. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Steven Price Reviewed-by: Chen-Yu Tsai Tested-by: Chen-Yu Tsai Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230316102041.210269-13-angelogioacchino.delregno@collabora.com --- drivers/gpu/drm/panfrost/panfrost_drv.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c index 4f39b410302c..bbada731bbbd 100644 --- a/drivers/gpu/drm/panfrost/panfrost_drv.c +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c @@ -672,6 +672,14 @@ static const struct panfrost_compatible mediatek_mt8183_b_data = { .pm_domain_names = mediatek_mt8183_pm_domains, }; +static const char * const mediatek_mt8186_pm_domains[] = { "core0", "core1" }; +static const struct panfrost_compatible mediatek_mt8186_data = { + .num_supplies = ARRAY_SIZE(mediatek_mt8183_b_supplies) - 1, + .supply_names = mediatek_mt8183_b_supplies, + .num_pm_domains = ARRAY_SIZE(mediatek_mt8186_pm_domains), + .pm_domain_names = mediatek_mt8186_pm_domains, +}; + static const char * const mediatek_mt8192_supplies[] = { "mali", NULL }; static const char * const mediatek_mt8192_pm_domains[] = { "core0", "core1", "core2", "core3", "core4" }; @@ -701,6 +709,7 @@ static const struct of_device_id dt_match[] = { { .compatible = "arm,mali-valhall-jm", .data = &default_data, }, { .compatible = "mediatek,mt8183-mali", .data = &mediatek_mt8183_data }, { .compatible = "mediatek,mt8183b-mali", .data = &mediatek_mt8183_b_data }, + { .compatible = "mediatek,mt8186-mali", .data = &mediatek_mt8186_data }, { .compatible = "mediatek,mt8192-mali", .data = &mediatek_mt8192_data }, {} }; -- cgit From 845e730eaf36d2199e25860259611ffda8e07f6c Mon Sep 17 00:00:00 2001 From: Pin-yen Lin Date: Wed, 15 Mar 2023 11:55:07 +0800 Subject: drm/bridge: ps8640: Skip redundant bridge enable Skip the drm_bridge_chain_pre_enable call when the bridge is already pre_enabled. This make pre_enable and post_disable (thus pm_runtime_get/put) symmetric. Fixes: 46f206304db0 ("drm/bridge: ps8640: Rework power state handling") Signed-off-by: Pin-yen Lin Reviewed-by: Robert Foss Reviewed-by: Douglas Anderson Signed-off-by: Douglas Anderson Link: https://patchwork.freedesktop.org/patch/msgid/20230315035508.2874915-1-treapking@chromium.org --- drivers/gpu/drm/bridge/parade-ps8640.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index 4b361d7d5e44..08de501c436e 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -557,7 +557,8 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, * EDID, for this chip, we need to do a full poweron, otherwise it will * fail. */ - drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state); + if (poweroff) + drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state); edid = drm_get_edid(connector, ps_bridge->page[PAGE0_DP_CNTL]->adapter); -- cgit From 6a17b4d1b52f10a44c45eea2a9222088e7c9e573 Mon Sep 17 00:00:00 2001 From: Pin-yen Lin Date: Wed, 15 Mar 2023 11:55:08 +0800 Subject: drm/bridge: ps8640: Add a cache for EDID When there are multiple EDID reads, the bridge will be repeatedly enabled and disabled. Add a cache for EDID to speed this up. Signed-off-by: Pin-yen Lin Reviewed-by: Robert Foss Reviewed-by: Douglas Anderson Signed-off-by: Douglas Anderson Link: https://patchwork.freedesktop.org/patch/msgid/20230315035508.2874915-2-treapking@chromium.org --- drivers/gpu/drm/bridge/parade-ps8640.c | 60 ++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index 08de501c436e..cddbfe91f75e 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -105,6 +105,7 @@ struct ps8640 { struct gpio_desc *gpio_reset; struct gpio_desc *gpio_powerdown; struct device_link *link; + struct edid *edid; bool pre_enabled; bool need_post_hpd_delay; }; @@ -543,34 +544,37 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); bool poweroff = !ps_bridge->pre_enabled; - struct edid *edid; - /* - * When we end calling get_edid() triggered by an ioctl, i.e - * - * drm_mode_getconnector (ioctl) - * -> drm_helper_probe_single_connector_modes - * -> drm_bridge_connector_get_modes - * -> ps8640_bridge_get_edid - * - * We need to make sure that what we need is enabled before reading - * EDID, for this chip, we need to do a full poweron, otherwise it will - * fail. - */ - if (poweroff) - drm_atomic_bridge_chain_pre_enable(bridge, connector->state->state); + if (!ps_bridge->edid) { + /* + * When we end calling get_edid() triggered by an ioctl, i.e + * + * drm_mode_getconnector (ioctl) + * -> drm_helper_probe_single_connector_modes + * -> drm_bridge_connector_get_modes + * -> ps8640_bridge_get_edid + * + * We need to make sure that what we need is enabled before + * reading EDID, for this chip, we need to do a full poweron, + * otherwise it will fail. + */ + if (poweroff) + drm_atomic_bridge_chain_pre_enable(bridge, + connector->state->state); - edid = drm_get_edid(connector, - ps_bridge->page[PAGE0_DP_CNTL]->adapter); + ps_bridge->edid = drm_get_edid(connector, + ps_bridge->page[PAGE0_DP_CNTL]->adapter); - /* - * If we call the get_edid() function without having enabled the chip - * before, return the chip to its original power state. - */ - if (poweroff) - drm_atomic_bridge_chain_post_disable(bridge, connector->state->state); + /* + * If we call the get_edid() function without having enabled the + * chip before, return the chip to its original power state. + */ + if (poweroff) + drm_atomic_bridge_chain_post_disable(bridge, + connector->state->state); + } - return edid; + return drm_edid_duplicate(ps_bridge->edid); } static void ps8640_runtime_disable(void *data) @@ -767,6 +771,13 @@ static int ps8640_probe(struct i2c_client *client) return ret; } +static void ps8640_remove(struct i2c_client *client) +{ + struct ps8640 *ps_bridge = i2c_get_clientdata(client); + + kfree(ps_bridge->edid); +} + static const struct of_device_id ps8640_match[] = { { .compatible = "parade,ps8640" }, { } @@ -775,6 +786,7 @@ MODULE_DEVICE_TABLE(of, ps8640_match); static struct i2c_driver ps8640_driver = { .probe_new = ps8640_probe, + .remove = ps8640_remove, .driver = { .name = "ps8640", .of_match_table = ps8640_match, -- cgit From 14aed8ea48e2f5c710ab678e1ba32b9f398d40b2 Mon Sep 17 00:00:00 2001 From: Pin-yen Lin Date: Fri, 24 Mar 2023 11:59:09 +0800 Subject: drm/bridge: ps8640: Return NULL immediately when EDID read fail drm_edid_read returns NULL on error, so feeding it directly into drm_edid_duplicate may lead to NULL pointer dereference. Add a check to guard this. Fixes: 6a17b4d1b52f ("drm/bridge: ps8640: Add a cache for EDID") Signed-off-by: Pin-yen Lin Signed-off-by: Douglas Anderson Link: https://patchwork.freedesktop.org/patch/msgid/20230324035909.1727356-1-treapking@chromium.org --- drivers/gpu/drm/bridge/parade-ps8640.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c index cddbfe91f75e..b823e55650b1 100644 --- a/drivers/gpu/drm/bridge/parade-ps8640.c +++ b/drivers/gpu/drm/bridge/parade-ps8640.c @@ -543,6 +543,7 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, struct drm_connector *connector) { struct ps8640 *ps_bridge = bridge_to_ps8640(bridge); + struct device *dev = &ps_bridge->page[PAGE0_DP_CNTL]->dev; bool poweroff = !ps_bridge->pre_enabled; if (!ps_bridge->edid) { @@ -574,6 +575,11 @@ static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge, connector->state->state); } + if (!ps_bridge->edid) { + dev_err(dev, "Failed to get EDID\n"); + return NULL; + } + return drm_edid_duplicate(ps_bridge->edid); } -- cgit From 4334aec07a62e3b1afdf54f63dca757e4ce9518c Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Mon, 20 Mar 2023 18:38:21 -0500 Subject: dt-bindings: display: Drop unneeded quotes Cleanup bindings dropping unneeded quotes. Once all these are fixed, checking for this can be enabled in yamllint. Reviewed-by: Chun-Kuang Hu Reviewed-by: Krzysztof Kozlowski Reviewed-by: Laurent Pinchart Acked-by: Miguel Ojeda Reviewed-by: Dmitry Baryshkov #display/msm Link: https://lore.kernel.org/r/20230320233823.2919475-1-robh@kernel.org Signed-off-by: Rob Herring --- .../bindings/auxdisplay/holtek,ht16k33.yaml | 2 +- .../bindings/display/amlogic,meson-dw-hdmi.yaml | 4 ++-- .../bindings/display/amlogic,meson-vpu.yaml | 4 ++-- .../bindings/display/bridge/analogix,anx7625.yaml | 4 ++-- .../bindings/display/bridge/cdns,mhdp8546.yaml | 4 ++-- .../bindings/display/bridge/nxp,ptn3460.yaml | 2 +- .../bindings/display/bridge/toshiba,tc358767.yaml | 2 +- .../devicetree/bindings/display/dp-aux-bus.yaml | 2 +- .../bindings/display/imx/nxp,imx8mq-dcss.yaml | 4 ++-- .../bindings/display/mediatek/mediatek,hdmi.yaml | 2 +- .../bindings/display/msm/dsi-controller-main.yaml | 8 ++++---- .../bindings/display/msm/dsi-phy-10nm.yaml | 2 +- .../devicetree/bindings/display/msm/gmu.yaml | 4 ++-- .../devicetree/bindings/display/msm/gpu.yaml | 4 ++-- .../devicetree/bindings/display/msm/mdp4.yaml | 4 ++-- .../bindings/display/panel/ronbo,rb070d30.yaml | 2 +- .../devicetree/bindings/display/renesas,du.yaml | 4 ++-- .../display/tegra/nvidia,tegra114-mipi.yaml | 2 +- .../display/tegra/nvidia,tegra124-sor.yaml | 12 ++++++------ .../bindings/display/tegra/nvidia,tegra186-dc.yaml | 4 ++-- .../display/tegra/nvidia,tegra186-dsi-padctl.yaml | 2 +- .../bindings/display/tegra/nvidia,tegra20-dsi.yaml | 12 ++++++------ .../display/tegra/nvidia,tegra20-hdmi.yaml | 6 +++--- .../bindings/display/ti/ti,am65x-dss.yaml | 6 +++--- .../bindings/display/ti/ti,j721e-dss.yaml | 4 ++-- .../devicetree/bindings/display/ti/ti,k2g-dss.yaml | 4 ++-- .../bindings/display/xylon,logicvc-display.yaml | 22 +++++++++++----------- 27 files changed, 66 insertions(+), 66 deletions(-) diff --git a/Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml b/Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml index fc4873deb76f..4f6ffb8182a9 100644 --- a/Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml +++ b/Documentation/devicetree/bindings/auxdisplay/holtek,ht16k33.yaml @@ -10,7 +10,7 @@ maintainers: - Robin van der Gracht allOf: - - $ref: "/schemas/input/matrix-keymap.yaml#" + - $ref: /schemas/input/matrix-keymap.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml index 74cefdf1b843..0c85894648d8 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-hdmi.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic specific extensions to the Synopsys Designware HDMI Controller diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml index 6655a93b1874..0c72120acc4f 100644 --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml @@ -2,8 +2,8 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Amlogic Meson Display Controller diff --git a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml index 4590186c4a0b..b42553ac505c 100644 --- a/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml +++ b/Documentation/devicetree/bindings/display/bridge/analogix,anx7625.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Analogix Semiconductor, Inc. %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Analogix ANX7625 SlimPort (4K Mobile HD Transmitter) diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml index b2e8bc6da9d0..c2b369456e4e 100644 --- a/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml +++ b/Documentation/devicetree/bindings/display/bridge/cdns,mhdp8546.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Cadence MHDP8546 bridge diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,ptn3460.yaml b/Documentation/devicetree/bindings/display/bridge/nxp,ptn3460.yaml index 107dd138e6c6..cdeb67bc05f0 100644 --- a/Documentation/devicetree/bindings/display/bridge/nxp,ptn3460.yaml +++ b/Documentation/devicetree/bindings/display/bridge/nxp,ptn3460.yaml @@ -18,7 +18,7 @@ properties: maxItems: 1 edid-emulation: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: The EDID emulation entry to use Value Resolution Description diff --git a/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml b/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml index 140927884418..e1494b5007cb 100644 --- a/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml +++ b/Documentation/devicetree/bindings/display/bridge/toshiba,tc358767.yaml @@ -23,7 +23,7 @@ properties: i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins clock-names: - const: "ref" + const: ref clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/dp-aux-bus.yaml b/Documentation/devicetree/bindings/display/dp-aux-bus.yaml index 5e4afe9f98fb..0ece7b01790b 100644 --- a/Documentation/devicetree/bindings/display/dp-aux-bus.yaml +++ b/Documentation/devicetree/bindings/display/dp-aux-bus.yaml @@ -26,7 +26,7 @@ description: properties: $nodename: - const: "aux-bus" + const: aux-bus panel: $ref: panel/panel-common.yaml# diff --git a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml index 989ab312c1f4..4ae6328cde64 100644 --- a/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml +++ b/Documentation/devicetree/bindings/display/imx/nxp,imx8mq-dcss.yaml @@ -2,8 +2,8 @@ # Copyright 2019 NXP %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: iMX8MQ Display Controller Subsystem (DCSS) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml index 8afdd67d6780..b90b6d18a828 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi.yaml @@ -50,7 +50,7 @@ properties: - const: hdmi mediatek,syscon-hdmi: - $ref: '/schemas/types.yaml#/definitions/phandle-array' + $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: phandle to system configuration registers diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index e75a3efe4dac..2188d7c9b0bb 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -74,7 +74,7 @@ properties: syscon-sfpb: description: A phandle to mmss_sfpb syscon node (only for DSIv2). - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle qcom,dual-dsi-mode: type: boolean @@ -105,14 +105,14 @@ properties: type: object ports: - $ref: "/schemas/graph.yaml#/properties/ports" + $ref: /schemas/graph.yaml#/properties/ports description: | Contains DSI controller input and output ports as children, each containing one endpoint subnode. properties: port@0: - $ref: "/schemas/graph.yaml#/$defs/port-base" + $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: | Input endpoints of the controller. @@ -128,7 +128,7 @@ properties: enum: [ 0, 1, 2, 3 ] port@1: - $ref: "/schemas/graph.yaml#/$defs/port-base" + $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false description: | Output endpoints of the controller. diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml index 3ec466c3ab38..e6b00d7387ce 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml @@ -58,7 +58,7 @@ properties: maximum: 31 qcom,phy-drive-ldo-level: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: The PHY LDO has an amplitude tuning feature to adjust the LDO output for the HSTX drive. Use supported levels (mV) to offset the drive level diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index ab14e81cb050..029d72822d8b 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -3,8 +3,8 @@ %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/msm/gmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: GMU attached to certain Adreno GPUs diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index d4191cca71fb..5dabe7b6794b 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -2,8 +2,8 @@ %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/msm/gpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Adreno or Snapdragon GPUs diff --git a/Documentation/devicetree/bindings/display/msm/mdp4.yaml b/Documentation/devicetree/bindings/display/msm/mdp4.yaml index 58c13f5277b6..35204a287579 100644 --- a/Documentation/devicetree/bindings/display/msm/mdp4.yaml +++ b/Documentation/devicetree/bindings/display/msm/mdp4.yaml @@ -1,8 +1,8 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/msm/mdp4.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm Adreno/Snapdragon MDP4 display controller diff --git a/Documentation/devicetree/bindings/display/panel/ronbo,rb070d30.yaml b/Documentation/devicetree/bindings/display/panel/ronbo,rb070d30.yaml index d67617f6f74a..95ce22c6787a 100644 --- a/Documentation/devicetree/bindings/display/panel/ronbo,rb070d30.yaml +++ b/Documentation/devicetree/bindings/display/panel/ronbo,rb070d30.yaml @@ -37,7 +37,7 @@ properties: backlight: description: Backlight used by the panel - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle required: - compatible diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml index d4830f52c512..c5b9e6812bce 100644 --- a/Documentation/devicetree/bindings/display/renesas,du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml @@ -76,7 +76,7 @@ properties: unevaluatedProperties: false renesas,cmms: - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: /schemas/types.yaml#/definitions/phandle-array items: maxItems: 1 description: @@ -84,7 +84,7 @@ properties: available DU channel. renesas,vsps: - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: /schemas/types.yaml#/definitions/phandle-array items: items: - description: phandle to VSP instance that serves the DU channel diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml index d5ca8cf86e8e..f448624dd779 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml @@ -38,7 +38,7 @@ properties: description: The number of cells in a MIPI calibration specifier. Should be 1. The single cell specifies a bitmask of the pads that need to be calibrated for a given device. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 const: 1 additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml index 907fb0baccae..70f0e45c71d6 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml @@ -69,12 +69,12 @@ properties: # Tegra186 and later nvidia,interface: description: index of the SOR interface - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 nvidia,ddc-i2c-bus: description: phandle of an I2C controller used for DDC EDID probing - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle nvidia,hpd-gpio: description: specifies a GPIO used for hotplug detection @@ -82,23 +82,23 @@ properties: nvidia,edid: description: supplies a binary EDID blob - $ref: "/schemas/types.yaml#/definitions/uint8-array" + $ref: /schemas/types.yaml#/definitions/uint8-array nvidia,panel: description: phandle of a display panel, required for eDP - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle nvidia,xbar-cfg: description: 5 cells containing the crossbar configuration. Each lane of the SOR, identified by the cell's index, is mapped via the crossbar to the pad specified by the cell's value. - $ref: "/schemas/types.yaml#/definitions/uint32-array" + $ref: /schemas/types.yaml#/definitions/uint32-array # optional when driving an eDP output nvidia,dpaux: description: phandle to a DispayPort AUX interface - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle allOf: - if: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml index 265a60d79d89..ce4589466a18 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml @@ -60,13 +60,13 @@ properties: nvidia,outputs: description: A list of phandles of outputs that this display controller can drive. - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: /schemas/types.yaml#/definitions/phandle-array nvidia,head: description: The number of the display controller head. This is used to setup the various types of output to receive video data from the given head. - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml index e5a6145c8c53..da75b71e8ece 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml @@ -29,7 +29,7 @@ properties: - const: dsi allOf: - - $ref: "/schemas/reset/reset.yaml" + - $ref: /schemas/reset/reset.yaml additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml index 511cbe74e729..59e1dc0813e7 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml @@ -59,12 +59,12 @@ properties: description: Should contain a phandle and a specifier specifying which pads are used by this DSI output and need to be calibrated. See nvidia,tegra114-mipi.yaml for details. - $ref: "/schemas/types.yaml#/definitions/phandle-array" + $ref: /schemas/types.yaml#/definitions/phandle-array nvidia,ddc-i2c-bus: description: phandle of an I2C controller used for DDC EDID probing - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle nvidia,hpd-gpio: description: specifies a GPIO used for hotplug detection @@ -72,19 +72,19 @@ properties: nvidia,edid: description: supplies a binary EDID blob - $ref: "/schemas/types.yaml#/definitions/uint8-array" + $ref: /schemas/types.yaml#/definitions/uint8-array nvidia,panel: description: phandle of a display panel - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle nvidia,ganged-mode: description: contains a phandle to a second DSI controller to gang up with in order to support up to 8 data lanes - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle allOf: - - $ref: "../dsi-controller.yaml#" + - $ref: ../dsi-controller.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml index f65e59cfffa7..f77197e4869f 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml @@ -68,7 +68,7 @@ properties: nvidia,ddc-i2c-bus: description: phandle of an I2C controller used for DDC EDID probing - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle nvidia,hpd-gpio: description: specifies a GPIO used for hotplug detection @@ -76,11 +76,11 @@ properties: nvidia,edid: description: supplies a binary EDID blob - $ref: "/schemas/types.yaml#/definitions/uint8-array" + $ref: /schemas/types.yaml#/definitions/uint8-array nvidia,panel: description: phandle of a display panel - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle "#sound-dai-cells": const: 0 diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml index 5c7d2cbc4aac..b6b402f16161 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Texas Instruments Incorporated %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments AM65x Display Subsystem @@ -88,7 +88,7 @@ properties: The DSS DPI output port node from video port 2 ti,am65x-oldi-io-ctrl: - $ref: "/schemas/types.yaml#/definitions/phandle" + $ref: /schemas/types.yaml#/definitions/phandle description: phandle to syscon device node mapping OLDI IO_CTRL registers. The mapped range should point to OLDI_DAT0_IO_CTRL, map it and diff --git a/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml index 2986f9acc9f0..fad7cba58d39 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Texas Instruments Incorporated %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments J721E Display Subsystem diff --git a/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml index 7ce7bbad5780..96b1439f88e3 100644 --- a/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml +++ b/Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Texas Instruments Incorporated %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Texas Instruments K2G Display Subsystem diff --git a/Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml b/Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml index fc02c5d50ce4..76b804b7c880 100644 --- a/Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml +++ b/Documentation/devicetree/bindings/display/xylon,logicvc-display.yaml @@ -2,8 +2,8 @@ # Copyright 2019 Bootlin %YAML 1.2 --- -$id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" +$id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# title: Xylon LogiCVC display controller @@ -89,25 +89,25 @@ properties: description: Display output colorspace (C_DISPLAY_COLOR_SPACE). xylon,display-depth: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: Display output depth (C_PIXEL_DATA_WIDTH). xylon,row-stride: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: Fixed number of pixels in a framebuffer row (C_ROW_STRIDE). xylon,dithering: - $ref: "/schemas/types.yaml#/definitions/flag" + $ref: /schemas/types.yaml#/definitions/flag description: Dithering module is enabled (C_XCOLOR) xylon,background-layer: - $ref: "/schemas/types.yaml#/definitions/flag" + $ref: /schemas/types.yaml#/definitions/flag description: | The last layer is used to display a black background (C_USE_BACKGROUND). The layer must still be registered. xylon,layers-configurable: - $ref: "/schemas/types.yaml#/definitions/flag" + $ref: /schemas/types.yaml#/definitions/flag description: | Configuration of layers' size, position and offset is enabled (C_USE_SIZE_POSITION). @@ -131,7 +131,7 @@ properties: maxItems: 1 xylon,layer-depth: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: Layer depth (C_LAYER_X_DATA_WIDTH). xylon,layer-colorspace: @@ -151,19 +151,19 @@ properties: description: Alpha mode for the layer (C_LAYER_X_ALPHA_MODE). xylon,layer-base-offset: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: | Offset in number of lines (C_LAYER_X_OFFSET) starting from the video RAM base (C_VMEM_BASEADDR), only for version 3. xylon,layer-buffer-offset: - $ref: "/schemas/types.yaml#/definitions/uint32" + $ref: /schemas/types.yaml#/definitions/uint32 description: | Offset in number of lines (C_BUFFER_*_OFFSET) starting from the layer base offset for the second buffer used in double-buffering. xylon,layer-primary: - $ref: "/schemas/types.yaml#/definitions/flag" + $ref: /schemas/types.yaml#/definitions/flag description: | Layer should be registered as a primary plane (exactly one is required). -- cgit From 1a2dbf0303e8793444a57a2eec0c6b29523657d9 Mon Sep 17 00:00:00 2001 From: Hsin-Yi Wang Date: Mon, 27 Mar 2023 12:48:05 +0800 Subject: drm/bridge: it6505: Add range and selector_reg There are 2 banks on it6505, and when writing to different bank, REG_BANK_SEL needs to be set to the targeted bank. The current code set this additionally, which causes a race condition when a process is writing bank 0 registers while another process set the bank to 1. Set ranges in regmap config so the regmap API would handle the bank changes. Signed-off-by: Hsin-Yi Wang Reviewed-by: Neil Armstrong Reviewed-by: Andrzej Hajda Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20230327044804.3657551-1-hsinyi@chromium.org --- drivers/gpu/drm/bridge/ite-it6505.c | 34 +++++++++++++++++++++++----------- 1 file changed, 23 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/bridge/ite-it6505.c b/drivers/gpu/drm/bridge/ite-it6505.c index bc451b2a77c2..abaf6e23775e 100644 --- a/drivers/gpu/drm/bridge/ite-it6505.c +++ b/drivers/gpu/drm/bridge/ite-it6505.c @@ -258,12 +258,12 @@ #define REG_AUD_INFOFRAM_SUM 0xFB /* the following six registers are in bank1 */ -#define REG_DRV_0_DB_800_MV 0x7E -#define REG_PRE_0_DB_800_MV 0x7F -#define REG_PRE_3P5_DB_800_MV 0x81 -#define REG_SSC_CTRL0 0x88 -#define REG_SSC_CTRL1 0x89 -#define REG_SSC_CTRL2 0x8A +#define REG_DRV_0_DB_800_MV 0x17E +#define REG_PRE_0_DB_800_MV 0x17F +#define REG_PRE_3P5_DB_800_MV 0x181 +#define REG_SSC_CTRL0 0x188 +#define REG_SSC_CTRL1 0x189 +#define REG_SSC_CTRL2 0x18A #define RBR DP_LINK_BW_1_62 #define HBR DP_LINK_BW_2_7 @@ -489,7 +489,7 @@ static const struct it6505_audio_sample_rate_map audio_sample_rate_map[] = { }; static const struct regmap_range it6505_bridge_volatile_ranges[] = { - { .range_min = 0, .range_max = 0xFF }, + { .range_min = 0, .range_max = 0x1FF }, }; static const struct regmap_access_table it6505_bridge_volatile_table = { @@ -497,11 +497,27 @@ static const struct regmap_access_table it6505_bridge_volatile_table = { .n_yes_ranges = ARRAY_SIZE(it6505_bridge_volatile_ranges), }; +static const struct regmap_range_cfg it6505_regmap_banks[] = { + { + .name = "it6505", + .range_min = 0x00, + .range_max = 0x1FF, + .selector_reg = REG_BANK_SEL, + .selector_mask = 0x1, + .selector_shift = 0, + .window_start = 0x00, + .window_len = 0x100, + }, +}; + static const struct regmap_config it6505_regmap_config = { .reg_bits = 8, .val_bits = 8, .volatile_table = &it6505_bridge_volatile_table, .cache_type = REGCACHE_NONE, + .ranges = it6505_regmap_banks, + .num_ranges = ARRAY_SIZE(it6505_regmap_banks), + .max_register = 0x1FF, }; static int it6505_read(struct it6505 *it6505, unsigned int reg_addr) @@ -1267,7 +1283,6 @@ static void it6505_init(struct it6505 *it6505) it6505_write(it6505, REG_TIME_STMP_CTRL, EN_SSC_GAT | EN_ENHANCE_VID_STMP | EN_ENHANCE_AUD_STMP); it6505_write(it6505, REG_INFOFRAME_CTRL, 0x00); - it6505_write(it6505, REG_BANK_SEL, 0x01); it6505_write(it6505, REG_DRV_0_DB_800_MV, afe_setting_table[it6505->afe_setting][0]); it6505_write(it6505, REG_PRE_0_DB_800_MV, @@ -1277,7 +1292,6 @@ static void it6505_init(struct it6505 *it6505) it6505_write(it6505, REG_SSC_CTRL0, 0x9E); it6505_write(it6505, REG_SSC_CTRL1, 0x1C); it6505_write(it6505, REG_SSC_CTRL2, 0x42); - it6505_write(it6505, REG_BANK_SEL, 0x00); } static void it6505_video_disable(struct it6505 *it6505) @@ -1506,11 +1520,9 @@ static void it6505_setup_ssc(struct it6505 *it6505) it6505_set_bits(it6505, REG_TRAIN_CTRL0, SPREAD_AMP_5, it6505->enable_ssc ? SPREAD_AMP_5 : 0x00); if (it6505->enable_ssc) { - it6505_write(it6505, REG_BANK_SEL, 0x01); it6505_write(it6505, REG_SSC_CTRL0, 0x9E); it6505_write(it6505, REG_SSC_CTRL1, 0x1C); it6505_write(it6505, REG_SSC_CTRL2, 0x42); - it6505_write(it6505, REG_BANK_SEL, 0x00); it6505_write(it6505, REG_SP_CTRL0, 0x07); it6505_write(it6505, REG_IP_CTRL1, 0x29); it6505_write(it6505, REG_IP_CTRL2, 0x03); -- cgit From bd2eefd018e5a8066b7bc66d8e200fbe3095ea5e Mon Sep 17 00:00:00 2001 From: Caio Novais Date: Sat, 25 Mar 2023 10:15:32 -0300 Subject: drm/scheduler: Fix variable name in function description Compiling AMD GPU drivers displays two warnings: drivers/gpu/drm/scheduler/sched_main.c:738: warning: Function parameter or member 'file' not described in 'drm_sched_job_add_syncobj_dependency' drivers/gpu/drm/scheduler/sched_main.c:738: warning: Excess function parameter 'file_private' description in 'drm_sched_job_add_syncobj_dependency' Get rid of them by renaming the variable name on the function description Signed-off-by: Caio Novais Link: https://lore.kernel.org/r/20230325131532.6356-1-caionovais@usp.br Reviewed-by: Luben Tuikov Signed-off-by: Luben Tuikov --- drivers/gpu/drm/scheduler/sched_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index 214364fccb71..7db586e6fce6 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -722,7 +722,7 @@ EXPORT_SYMBOL(drm_sched_job_add_dependency); /** * drm_sched_job_add_syncobj_dependency - adds a syncobj's fence as a job dependency * @job: scheduler job to add the dependencies to - * @file_private: drm file private pointer + * @file: drm file private pointer * @handle: syncobj handle to lookup * @point: timeline point * -- cgit From 14302ab0d6550ef0ea48f213b0ab13c9249de185 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 22 Mar 2023 12:07:10 +0300 Subject: drm/panel: magnachip: Prevent error pointer dereference in probe Don't dereference "db->dsi_dev" when it is an error pointer. Fixes: 249a4f5e663c ("drm/panel: Add Magnachip D53E6EA8966 Panel Driver") Signed-off-by: Dan Carpenter Signed-off-by: Linus Walleij Link: https://patchwork.freedesktop.org/patch/msgid/de0273a8-8910-4ac4-b4ed-f7691c4d2ca6@kili.mountain --- drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c b/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c index 8c362c40227f..26d358b9b85a 100644 --- a/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c +++ b/drivers/gpu/drm/panel/panel-magnachip-d53e6ea8966.c @@ -418,7 +418,7 @@ static int d53e6ea8966_probe(struct spi_device *spi) if (IS_ERR(db->dsi_dev)) { dev_err(dev, "failed to register dsi device: %ld\n", PTR_ERR(db->dsi_dev)); - ret = PTR_ERR(db->dsi_dev); + return PTR_ERR(db->dsi_dev); } db->dsi_dev->lanes = 2; -- cgit From 981f8866754dc5aec6864b877acb248dc33a7bc8 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 24 Mar 2023 22:29:09 +0530 Subject: drm/panel-edp: Add B133UAN01.0 edp panel entry This panel is found in Lenovo Flex 5G laptop, so add the entry for it Signed-off-by: Bjorn Andersson Signed-off-by: Vinod Koul Acked-by: Neil Armstrong Reviewed-by: Douglas Anderson Signed-off-by: Douglas Anderson Link: https://patchwork.freedesktop.org/patch/msgid/20230324165909.131831-1-vkoul@kernel.org --- drivers/gpu/drm/panel/panel-edp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/panel/panel-edp.c b/drivers/gpu/drm/panel/panel-edp.c index 01bfe0783304..926906ca2304 100644 --- a/drivers/gpu/drm/panel/panel-edp.c +++ b/drivers/gpu/drm/panel/panel-edp.c @@ -1871,6 +1871,7 @@ static const struct edp_panel_entry edp_panels[] = { EDP_PANEL_ENTRY('A', 'U', 'O', 0x1e9b, &delay_200_500_e50, "B133UAN02.1"), EDP_PANEL_ENTRY('A', 'U', 'O', 0x1ea5, &delay_200_500_e50, "B116XAK01.6"), EDP_PANEL_ENTRY('A', 'U', 'O', 0x405c, &auo_b116xak01.delay, "B116XAK01"), + EDP_PANEL_ENTRY('A', 'U', 'O', 0x582d, &delay_200_500_e50, "B133UAN01.0"), EDP_PANEL_ENTRY('A', 'U', 'O', 0x615c, &delay_200_500_e50, "B116XAN06.1"), EDP_PANEL_ENTRY('A', 'U', 'O', 0x8594, &delay_200_500_e50, "B133UAN01.0"), -- cgit From 7fa5047a436ba27696e344d974811d9ea07ba249 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:05 -0600 Subject: drm: Use of_property_present() for testing DT property presence It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. As part of this, convert of_get_property/of_find_property calls to the recently added of_property_present() helper when we just want to test for presence of a property and nothing more. Reviewed-by: Jernej Skrabec Reviewed-by: Liu Ying # i.MX bridge Reviewed-by: Dmitry Baryshkov Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20230310144705.1542207-1-robh@kernel.org Signed-off-by: Rob Herring --- drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c | 2 +- drivers/gpu/drm/drm_mipi_dsi.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +- drivers/gpu/drm/sun4i/sun4i_backend.c | 2 +- drivers/gpu/drm/sun4i/sun8i_mixer.c | 2 +- drivers/gpu/drm/tiny/simpledrm.c | 2 +- drivers/gpu/drm/vc4/vc4_hdmi.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c index 25dc82a44ef4..ed8b7a4e0e11 100644 --- a/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c +++ b/drivers/gpu/drm/bridge/imx/imx8qxp-pixel-link.c @@ -313,7 +313,7 @@ imx8qxp_pixel_link_find_next_bridge(struct imx8qxp_pixel_link *pl) } /* specially select the next bridge with companion PXL2DPI */ - if (of_find_property(remote, "fsl,companion-pxl2dpi", NULL)) + if (of_property_present(remote, "fsl,companion-pxl2dpi")) bridge_sel = ep_cnt; ep_cnt++; diff --git a/drivers/gpu/drm/drm_mipi_dsi.c b/drivers/gpu/drm/drm_mipi_dsi.c index b41aaf2bb9f1..7900a4707d7c 100644 --- a/drivers/gpu/drm/drm_mipi_dsi.c +++ b/drivers/gpu/drm/drm_mipi_dsi.c @@ -329,7 +329,7 @@ int mipi_dsi_host_register(struct mipi_dsi_host *host) for_each_available_child_of_node(host->dev->of_node, node) { /* skip nodes without reg property */ - if (!of_find_property(node, "reg", NULL)) + if (!of_property_present(node, "reg")) continue; of_mipi_dsi_device_add(host, node); } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index ce6b76c45b6f..2359dca80492 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -964,7 +964,7 @@ static void adreno_get_pwrlevels(struct device *dev, gpu->fast_rate = 0; /* You down with OPP? */ - if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) + if (!of_property_present(dev->of_node, "operating-points-v2")) ret = adreno_get_legacy_pwrlevels(dev); else { ret = devm_pm_opp_of_add_table(dev); diff --git a/drivers/gpu/drm/sun4i/sun4i_backend.c b/drivers/gpu/drm/sun4i/sun4i_backend.c index 38070fc261f3..b11dbd50d73e 100644 --- a/drivers/gpu/drm/sun4i/sun4i_backend.c +++ b/drivers/gpu/drm/sun4i/sun4i_backend.c @@ -792,7 +792,7 @@ static int sun4i_backend_bind(struct device *dev, struct device *master, dev_set_drvdata(dev, backend); spin_lock_init(&backend->frontend_lock); - if (of_find_property(dev->of_node, "interconnects", NULL)) { + if (of_property_present(dev->of_node, "interconnects")) { /* * This assume we have the same DMA constraints for all our the * devices in our pipeline (all the backends, but also the diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c index bafee05f6b24..11d5244a5aa5 100644 --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c @@ -391,7 +391,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master, mixer->engine.ops = &sun8i_engine_ops; mixer->engine.node = dev->of_node; - if (of_find_property(dev->of_node, "iommus", NULL)) { + if (of_property_present(dev->of_node, "iommus")) { /* * This assume we have the same DMA constraints for * all our the mixers in our pipeline. This sounds diff --git a/drivers/gpu/drm/tiny/simpledrm.c b/drivers/gpu/drm/tiny/simpledrm.c index c38d85848af8..25e11ef11c4c 100644 --- a/drivers/gpu/drm/tiny/simpledrm.c +++ b/drivers/gpu/drm/tiny/simpledrm.c @@ -204,7 +204,7 @@ simplefb_get_memory_of(struct drm_device *dev, struct device_node *of_node) if (err) return ERR_PTR(err); - if (of_get_property(of_node, "reg", NULL)) + if (of_property_present(of_node, "reg")) drm_warn(dev, "preferring \"memory-region\" over \"reg\" property\n"); return res; diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c index d30e4547b4c5..464c3cc8e6fb 100644 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c @@ -3020,7 +3020,7 @@ static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) struct device *dev = &pdev->dev; int ret; - if (!of_find_property(dev->of_node, "interrupts", NULL)) { + if (!of_property_present(dev->of_node, "interrupts")) { dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); return 0; } -- cgit From 5e78066767c9f2c108b949336faa5773cd266908 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:54:20 +0200 Subject: dt-bindings: display: panel-simple: merge Innolux p120zdg-bf1 There is nothing special in Innolux p120zdg-bf1 panel, so just like other Innolux panels it can be made part of panel-simple. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230326155425.91181-1-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring --- .../display/panel/innolux,p120zdg-bf1.yaml | 43 ---------------------- .../bindings/display/panel/panel-simple.yaml | 2 + 2 files changed, 2 insertions(+), 43 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/panel/innolux,p120zdg-bf1.yaml diff --git a/Documentation/devicetree/bindings/display/panel/innolux,p120zdg-bf1.yaml b/Documentation/devicetree/bindings/display/panel/innolux,p120zdg-bf1.yaml deleted file mode 100644 index 243dac2416f3..000000000000 --- a/Documentation/devicetree/bindings/display/panel/innolux,p120zdg-bf1.yaml +++ /dev/null @@ -1,43 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/panel/innolux,p120zdg-bf1.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel - -maintainers: - - Sandeep Panda - - Douglas Anderson - -allOf: - - $ref: panel-common.yaml# - -properties: - compatible: - const: innolux,p120zdg-bf1 - - enable-gpios: true - power-supply: true - backlight: true - no-hpd: true - -required: - - compatible - - power-supply - -additionalProperties: false - -examples: - - | - #include - - panel_edp: panel-edp { - compatible = "innolux,p120zdg-bf1"; - enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>; - power-supply = <&pm8916_l2>; - backlight = <&backlight>; - no-hpd; - }; - -... diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 18241f4051d2..01560fe226dd 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -192,6 +192,8 @@ properties: - innolux,n125hce-gn1 # InnoLux 15.6" WXGA TFT LCD panel - innolux,n156bge-l21 + # Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel + - innolux,p120zdg-bf1 # Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel - innolux,zj070na-01p # King & Display KD116N21-30NV-A010 eDP TFT LCD panel -- cgit From 331b569fd21755bb9acd2ee021addf689b5a07f4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:54:21 +0200 Subject: dt-bindings: display: novatek,nt36672a: correct VDDIO supply The nt36672a bindings were added with a mistake on VDDIO supply calling it in one place vddio and in other vddi0. Typical name is rather vddio which is also now used by DTS (sdm845-xiaomi-beryllium-common.dtsi) and Linux driver. Fixes: c2abcf30efb8 ("dt-bindings: display: novatek,nt36672a: Fix unevaluated properties warning") Fixes: 9528a02430df ("dt-bindings: display: panel: Add bindings for Novatek nt36672a") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230326155425.91181-2-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring --- .../devicetree/bindings/display/panel/novatek,nt36672a.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml index 41ee3157a1cd..ae821f465e1c 100644 --- a/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt36672a.yaml @@ -34,7 +34,7 @@ properties: description: phandle of gpio for reset line - This should be 8mA, gpio can be configured using mux, pinctrl, pinctrl-names (active high) - vddi0-supply: + vddio-supply: description: phandle of the regulator that provides the supply voltage Power IC supply @@ -51,7 +51,7 @@ properties: required: - compatible - reg - - vddi0-supply + - vddio-supply - vddpos-supply - vddneg-supply - reset-gpios @@ -70,7 +70,7 @@ examples: panel@0 { compatible = "tianma,fhd-video", "novatek,nt36672a"; reg = <0>; - vddi0-supply = <&vreg_l14a_1p88>; + vddio-supply = <&vreg_l14a_1p88>; vddpos-supply = <&lab>; vddneg-supply = <&ibb>; -- cgit From dd049e8f7616e74cb9c3c2f8e88aac0ac20dd8af Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:54:22 +0200 Subject: dt-bindings: display: panel-simple-dsi: allow vddio variant Few panels like Samsung s6e3fc2x01 and sofef00 use vddio-supply instead of power-supply (in DTS and Linux driver), so allow it to fix: sdm845-oneplus-enchilada.dtb: panel@0: 'power-supply' is a required property Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230326155425.91181-3-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring --- .../bindings/display/panel/panel-simple-dsi.yaml | 24 ++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml index 2c00813f5d20..90c04cff8281 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml @@ -19,9 +19,6 @@ description: | If the panel is more advanced a dedicated binding file is required. -allOf: - - $ref: panel-common.yaml# - properties: compatible: @@ -67,12 +64,31 @@ properties: reset-gpios: true port: true power-supply: true + vddio-supply: true + +allOf: + - $ref: panel-common.yaml# + - if: + properties: + compatible: + enum: + - samsung,s6e3fc2x01 + - samsung,sofef00 + then: + properties: + power-supply: false + required: + - vddio-supply + else: + properties: + vddio-supply: false + required: + - power-supply additionalProperties: false required: - compatible - - power-supply - reg examples: -- cgit From 2727dbacb016d5a0124c54a39822f169d807b6a1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:54:23 +0200 Subject: dt-bindings: display: panel-simple-dsi: document port Panels are supposed to have one port (coming from panel-common.yaml binding): msm8916-samsung-a3u-eur.dtb: panel@0: 'port' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230326155425.91181-4-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring --- .../bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml b/Documentation/devicetree/bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml index 44ce98f68705..b749e9e906b7 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml @@ -16,6 +16,7 @@ properties: compatible: const: samsung,s6e88a0-ams452ef01 reg: true + port: true reset-gpios: true vdd3-supply: description: core voltage supply @@ -25,6 +26,7 @@ properties: required: - compatible - reg + - port - vdd3-supply - vci-supply - reset-gpios @@ -46,5 +48,11 @@ examples: vdd3-supply = <&pm8916_l17>; vci-supply = <®_vlcd_vci>; reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; }; }; -- cgit From 5ffd1f3f9a8e44ed816817bb5b0193cc64c9dba1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:54:24 +0200 Subject: dt-bindings: display: visionox,rm69299: document reg Panels are supposed to have one reg. This fixes dtbs_check warnings like: sc7180-idp.dtb: panel@0: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230326155425.91181-5-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring --- .../bindings/display/panel/visionox,rm69299.yaml | 25 +++++++++++++++------- 1 file changed, 17 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/display/panel/visionox,rm69299.yaml b/Documentation/devicetree/bindings/display/panel/visionox,rm69299.yaml index 481ef051df1e..444ac2a4772d 100644 --- a/Documentation/devicetree/bindings/display/panel/visionox,rm69299.yaml +++ b/Documentation/devicetree/bindings/display/panel/visionox,rm69299.yaml @@ -19,6 +19,8 @@ properties: compatible: const: visionox,rm69299-1080p-display + reg: true + vdda-supply: description: | Phandle of the regulator that provides the vdda supply voltage. @@ -34,6 +36,7 @@ additionalProperties: false required: - compatible + - reg - vdda-supply - vdd3p3-supply - reset-gpios @@ -41,16 +44,22 @@ required: examples: - | - panel { - compatible = "visionox,rm69299-1080p-display"; + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "visionox,rm69299-1080p-display"; + reg = <0>; - vdda-supply = <&src_pp1800_l8c>; - vdd3p3-supply = <&src_pp2800_l18a>; + vdda-supply = <&src_pp1800_l8c>; + vdd3p3-supply = <&src_pp2800_l18a>; - reset-gpios = <&pm6150l_gpio 3 0>; - port { - panel0_in: endpoint { - remote-endpoint = <&dsi0_out>; + reset-gpios = <&pm6150l_gpio 3 0>; + port { + panel0_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; }; }; }; -- cgit From fbb3b3500f76ec8b741bd2d0e761ca3e856ad924 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sun, 26 Mar 2023 17:54:25 +0200 Subject: dt-bindings: display: boe,tv101wum-nl6: document rotation Allow 'rotation' property (coming from panel-common.yaml) already used in DTS: sc7180-trogdor-quackingstick-r0.dtb: panel@0: 'rotation' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230326155425.91181-6-krzysztof.kozlowski@linaro.org Signed-off-by: Rob Herring --- Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml index f98ed588c750..aed55608ebf6 100644 --- a/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml +++ b/Documentation/devicetree/bindings/display/panel/boe,tv101wum-nl6.yaml @@ -55,6 +55,7 @@ properties: description: phandle of the backlight device attached to the panel port: true + rotation: true required: - compatible -- cgit From b2d2d8decc8d239875420af6e412158ac5a2cb1f Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Wed, 29 Mar 2023 17:11:50 -0300 Subject: dt-bindings: display: seiko,43wvf1g: Change the maintainer's contact Marco's NXP email is no longer valid. Marco told me offline that he has no interest to be listed as the maintainer contact for this binding, so add my contact. Signed-off-by: Fabio Estevam Acked-by: Krzysztof Kozlowski Signed-off-by: Neil Armstrong Link: https://patchwork.freedesktop.org/patch/msgid/20230329201150.741106-1-festevam@gmail.com --- Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml index a5426586b473..1df3cbb51ff9 100644 --- a/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml +++ b/Documentation/devicetree/bindings/display/panel/seiko,43wvf1g.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel maintainers: - - Marco Franchi + - Fabio Estevam allOf: - $ref: panel-common.yaml# -- cgit From e27a85c1757655e2e7bd09164b87bf75627e5604 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 10 Mar 2023 08:47:05 -0600 Subject: drm: Use of_property_read_bool() for boolean properties It is preferred to use typed property access functions (i.e. of_property_read_ functions) rather than low-level of_get_property/of_find_property functions for reading properties. Convert reading boolean properties to of_property_read_bool(). Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/r/20230310144706.1542295-1-robh@kernel.org Signed-off-by: Rob Herring --- drivers/gpu/drm/bridge/parade-ps8622.c | 2 +- drivers/gpu/drm/tiny/ofdrm.c | 8 ++------ 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/bridge/parade-ps8622.c b/drivers/gpu/drm/bridge/parade-ps8622.c index 530ee6a19e7e..efa80e309b98 100644 --- a/drivers/gpu/drm/bridge/parade-ps8622.c +++ b/drivers/gpu/drm/bridge/parade-ps8622.c @@ -496,7 +496,7 @@ static int ps8622_probe(struct i2c_client *client) ps8622->lane_count = ps8622->max_lane_count; } - if (!of_find_property(dev->of_node, "use-external-pwm", NULL)) { + if (!of_property_read_bool(dev->of_node, "use-external-pwm")) { ps8622->bl = backlight_device_register("ps8622-backlight", dev, ps8622, &ps8622_backlight_ops, NULL); diff --git a/drivers/gpu/drm/tiny/ofdrm.c b/drivers/gpu/drm/tiny/ofdrm.c index 6e349ca42485..76cd7f515bab 100644 --- a/drivers/gpu/drm/tiny/ofdrm.c +++ b/drivers/gpu/drm/tiny/ofdrm.c @@ -162,13 +162,9 @@ static bool display_get_big_endian_of(struct drm_device *dev, struct device_node bool big_endian; #ifdef __BIG_ENDIAN - big_endian = true; - if (of_get_property(of_node, "little-endian", NULL)) - big_endian = false; + big_endian = !of_property_read_bool(of_node, "little-endian"); #else - big_endian = false; - if (of_get_property(of_node, "big-endian", NULL)) - big_endian = true; + big_endian = of_property_read_bool(of_node, "big-endian"); #endif return big_endian; -- cgit From 191308bae4ef67df627158c7effb4f397fa992d4 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 23 Mar 2023 10:08:21 +0100 Subject: dt-bindings: gpu: mali-bifrost: Document nvmem for speedbin support Some SoCs implementing ARM Mali GPUs may be subject to speed binning and the usable bin is read from nvmem: document the addition of nvmem and nvmem-cells for 'speed-bin'. Signed-off-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230323090822.61766-2-angelogioacchino.delregno@collabora.com --- Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index 3eb9a4e95e92..0400a361875d 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -104,6 +104,13 @@ properties: dma-coherent: true + nvmem-cell-names: + items: + - const: speed-bin + + nvmem-cells: + maxItems: 1 + required: - compatible - reg -- cgit From 7d690f936e9bc9fbd6394fb3d4ad181af03ee393 Mon Sep 17 00:00:00 2001 From: AngeloGioacchino Del Regno Date: Thu, 23 Mar 2023 10:08:22 +0100 Subject: drm/panfrost: Add basic support for speed binning Some SoCs implementing ARM Mali GPUs are subject to speed binning: this means that some versions of the same SoC model may need to be limited to a slower frequency compared to the other: this is being addressed by reading nvmem (usually, an eFuse array) containing a number that identifies the speed binning of the chip, which is usually related to silicon quality. To address such situation, add basic support for reading the speed-bin through nvmem, as to make it possible to specify the supported hardware in the OPP table for GPUs. This commit also keeps compatibility with any platform that does not specify (and does not even support) speed-binning. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Boris Brezillon Signed-off-by: Boris Brezillon Link: https://patchwork.freedesktop.org/patch/msgid/20230323090822.61766-3-angelogioacchino.delregno@collabora.com --- drivers/gpu/drm/panfrost/panfrost_devfreq.c | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/panfrost/panfrost_devfreq.c b/drivers/gpu/drm/panfrost/panfrost_devfreq.c index fe5f12f16a63..58dfb15a8757 100644 --- a/drivers/gpu/drm/panfrost/panfrost_devfreq.c +++ b/drivers/gpu/drm/panfrost/panfrost_devfreq.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -82,6 +83,31 @@ static struct devfreq_dev_profile panfrost_devfreq_profile = { .get_dev_status = panfrost_devfreq_get_dev_status, }; +static int panfrost_read_speedbin(struct device *dev) +{ + u32 val; + int ret; + + ret = nvmem_cell_read_variable_le_u32(dev, "speed-bin", &val); + if (ret) { + /* + * -ENOENT means that this platform doesn't support speedbins + * as it didn't declare any speed-bin nvmem: in this case, we + * keep going without it; any other error means that we are + * supposed to read the bin value, but we failed doing so. + */ + if (ret != -ENOENT) { + DRM_DEV_ERROR(dev, "Cannot read speed-bin (%d).", ret); + return ret; + } + + return 0; + } + DRM_DEV_DEBUG(dev, "Using speed-bin = 0x%x\n", val); + + return devm_pm_opp_set_supported_hw(dev, &val, 1); +} + int panfrost_devfreq_init(struct panfrost_device *pfdev) { int ret; @@ -101,6 +127,10 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev) return 0; } + ret = panfrost_read_speedbin(dev); + if (ret) + return ret; + ret = devm_pm_opp_set_regulators(dev, pfdev->comp->supply_names); if (ret) { /* Continue if the optional regulator is missing */ -- cgit