From 62421b45d431dc6f023334800eae1bffb1e77eb2 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Fri, 20 Jan 2023 16:59:09 -0800 Subject: drm/xe: Fix typo in MCR documentation Add missing "multicast" word and adapt/wrap the rest of the sentence. Signed-off-by: Lucas De Marchi Reviewed-by: Rodrigo Vivi Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_gt_mcr.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c index ddce2c41c7f5..7c97031cd716 100644 --- a/drivers/gpu/drm/xe/xe_gt_mcr.c +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c @@ -23,12 +23,12 @@ * * MMIO accesses to MCR registers are controlled according to the settings * programmed in the platform's MCR_SELECTOR register(s). MMIO writes to MCR - * registers can be done in either a (i.e., a single write updates all + * registers can be done in either multicast (a single write updates all * instances of the register to the same value) or unicast (a write updates only - * one specific instance). Reads of MCR registers always operate in a unicast - * manner regardless of how the multicast/unicast bit is set in MCR_SELECTOR. - * Selection of a specific MCR instance for unicast operations is referred to - * as "steering." + * one specific instance) form. Reads of MCR registers always operate in a + * unicast manner regardless of how the multicast/unicast bit is set in + * MCR_SELECTOR. Selection of a specific MCR instance for unicast operations is + * referred to as "steering." * * If MCR register operations are steered toward a hardware unit that is * fused off or currently powered down due to power gating, the MMIO operation -- cgit