From c7b4d6e7fa837e70f463c6e83a0d0e5e201f85db Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Mon, 1 Jul 2024 16:50:11 +0200 Subject: arm64: dts: renesas: r8a779g0: R-Car Ethernet TSN support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add Ethernet TSN support for R-Car V4H. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240701145012.2342868-2-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index d6770d3d488b..c66a920060ff 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -553,6 +553,20 @@ status = "disabled"; }; + tsn0: ethernet@e6460000 { + compatible = "renesas,r8a779g0-ethertsn", "renesas,rcar-gen4-ethertsn"; + reg = <0 0xe6460000 0 0x7000>, + <0 0xe6449000 0 0x500>; + reg-names = "tsnes", "gptp"; + interrupts = , + ; + interrupt-names = "tx", "rx"; + clocks = <&cpg CPG_MOD 2723>; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 2723>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779g0", "renesas,rcar-gen4-i2c"; -- cgit From 3d8e475bd7a724a97cffebcaae7230abae2ca170 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Mon, 1 Jul 2024 16:50:12 +0200 Subject: arm64: dts: renesas: white-hawk-single: Wire-up Ethernet TSN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On the V4H White Hawk Single board as opposed to the Quad board the Ethernet TSN is wired up to a PHY (Marvel 88Q2110/QFN40). Wire up the connection and enable the TSN0. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240701145012.2342868-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- .../dts/renesas/r8a779g2-white-hawk-single.dts | 51 ++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts index 2f79e5a61248..50a428572d9b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779g2-white-hawk-single.dts @@ -24,3 +24,54 @@ groups = "hscif0_data", "hscif0_ctrl"; function = "hscif0"; }; + +&pfc { + tsn0_pins: tsn0 { + mux { + groups = "tsn0_link", "tsn0_mdio", "tsn0_rgmii", + "tsn0_txcrefclk"; + function = "tsn0"; + }; + + link { + groups = "tsn0_link"; + bias-disable; + }; + + mdio { + groups = "tsn0_mdio"; + drive-strength = <24>; + bias-disable; + }; + + rgmii { + groups = "tsn0_rgmii"; + drive-strength = <24>; + bias-disable; + }; + }; +}; + +&tsn0 { + pinctrl-0 = <&tsn0_pins>; + pinctrl-names = "default"; + phy-mode = "rgmii"; + phy-handle = <&phy3>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&gpio1 23 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <4000>; + + phy3: ethernet-phy@0 { + compatible = "ethernet-phy-id002b.0980", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; -- cgit From bdfa062d14b22e36207c219206b2bf770d5363b3 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 15 Jul 2024 15:07:03 +0100 Subject: arm64: dts: renesas: r9a07g0{43,44,54}: Move regulator-vbus device node Move regulator-vbus device node from common to the usbphy-ctrl device node of the individual SoC dtsi's as it embeds the vbus regulator. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240715140705.334183-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 4 ++++ arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 4 ++++ arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 4 ++++ arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi | 3 --- 4 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 2eccab9c8962..593c66b27ad1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -725,6 +725,10 @@ power-domains = <&cpg>; #reset-cells = <1>; status = "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name = "vbus"; + }; }; ohci0: usb@11c50000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index d3838e5820fc..47a671661142 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1129,6 +1129,10 @@ power-domains = <&cpg>; #reset-cells = <1>; status = "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name = "vbus"; + }; }; ohci0: usb@11c50000 { diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 1de2e5f0917d..0aace8427be3 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1137,6 +1137,10 @@ power-domains = <&cpg>; #reset-cells = <1>; status = "disabled"; + + usb0_vbus_otg: regulator-vbus { + regulator-name = "vbus"; + }; }; ohci0: usb@11c50000 { diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi index b34855956ae0..63fa5cf1061b 100644 --- a/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi +++ b/arch/arm64/boot/dts/renesas/rz-smarc-common.dtsi @@ -131,9 +131,6 @@ &phyrst { status = "okay"; - usb0_vbus_otg: regulator-vbus { - regulator-name = "vbus"; - }; }; &scif0 { -- cgit From ec9532628eb9d82282b8e52fd9c4a3800d87feec Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 30 Jul 2024 13:24:33 +0100 Subject: arm64: dts: renesas: r9a08g045: Correct GICD and GICR sizes The RZ/G3S SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU. Despite the RZ/G3S SoC being single-core, it has two instances of GICR. Fixes: e20396d65b959 ("arm64: dts: renesas: Add initial DTSI for RZ/G3S SoC") Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/20240730122436.350013-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index 37885cd24f16..e062f5eed638 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -307,8 +307,8 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x0 0x12400000 0 0x40000>, - <0x0 0x12440000 0 0x60000>; + reg = <0x0 0x12400000 0 0x20000>, + <0x0 0x12440000 0 0x40000>; interrupts = ; }; -- cgit From ab39547f739236e7f16b8b0a51fdca95cc9cadd3 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 30 Jul 2024 13:24:34 +0100 Subject: arm64: dts: renesas: r9a07g043u: Correct GICD and GICR sizes The RZ/G2UL SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU. Despite the RZ/G2UL SoC being single-core, it has two instances of GICR. Fixes: cf40c9689e510 ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC") Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/20240730122436.350013-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 18ef297db933..20fb5e41c598 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -210,8 +210,8 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; + reg = <0x0 0x11900000 0 0x20000>, + <0x0 0x11940000 0 0x40000>; interrupts = ; }; }; -- cgit From 45afa9eacb59b258d2e53c7f63430ea1e8344803 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 30 Jul 2024 13:24:35 +0100 Subject: arm64: dts: renesas: r9a07g054: Correct GICD and GICR sizes The RZ/V2L SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU. Fixes: 7c2b8198f4f32 ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC") Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/20240730122436.350013-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 0aace8427be3..01f59914dd09 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -1051,8 +1051,8 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; + reg = <0x0 0x11900000 0 0x20000>, + <0x0 0x11940000 0 0x40000>; interrupts = ; }; -- cgit From 833948fb2b63155847ab691a54800f801555429b Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 30 Jul 2024 13:24:36 +0100 Subject: arm64: dts: renesas: r9a07g044: Correct GICD and GICR sizes The RZ/G2L(C) SoC is equipped with the GIC-600. The GICD is 64KiB + 64KiB for the MBI alias (in total 128KiB), and the GICR is 128KiB per CPU. Fixes: 68a45525297b2 ("arm64: dts: renesas: Add initial DTSI for RZ/G2{L,LC} SoC's") Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/20240730122436.350013-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 47a671661142..6b1c77cd8261 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -1043,8 +1043,8 @@ #interrupt-cells = <3>; #address-cells = <0>; interrupt-controller; - reg = <0x0 0x11900000 0 0x40000>, - <0x0 0x11940000 0 0x60000>; + reg = <0x0 0x11900000 0 0x20000>, + <0x0 0x11940000 0 0x40000>; interrupts = ; }; -- cgit From a94a244a5b1a2040611aaaa17fd23dd908bc01ac Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 5 Aug 2024 14:17:05 +0100 Subject: arm64: dts: renesas: r9a07g043u: Add FCPVD node Add FCPVD node to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240805131709.101679-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 20fb5e41c598..4cfcef60680c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -129,6 +129,17 @@ }; }; + fcpvd: fcp@10880000 { + compatible = "renesas,r9a07g043u-fcpvd", "renesas,fcpv"; + reg = <0 0x10880000 0 0x10000>; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + }; + irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043u-irqc", "renesas,rzg2l-irqc"; -- cgit From 6bfd974d03a433e7fa9d5444f89851e4e4eb9779 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 5 Aug 2024 14:17:06 +0100 Subject: arm64: dts: renesas: r9a07g043u: Add VSPD node Add VSPD node to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240805131709.101679-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 4cfcef60680c..1b3db8df4bbc 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -129,6 +129,19 @@ }; }; + vspd: vsp@10870000 { + compatible = "renesas,r9a07g043u-vsp2", "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + fcpvd: fcp@10880000 { compatible = "renesas,r9a07g043u-fcpvd", "renesas,fcpv"; reg = <0 0x10880000 0 0x10000>; -- cgit From a502d6e7840367929e9a4cecc83448f0b52d3276 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 20 Aug 2024 13:19:16 +0300 Subject: arm64: dts: renesas: r9a08g045: Add I2C nodes The Renesas RZ/G3S SoC has 4 I2C channels. Add DT nodes for them. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240820101918.2384635-10-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a08g045.dtsi | 88 ++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi index e062f5eed638..067a26a66c24 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045.dtsi @@ -72,6 +72,94 @@ status = "disabled"; }; + i2c0: i2c@10090000 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G045_I2C0_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G045_I2C0_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@10090400 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090400 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G045_I2C1_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G045_I2C1_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@10090800 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G045_I2C2_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G045_I2C2_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@10090c00 { + compatible = "renesas,riic-r9a08g045", "renesas,riic-r9a09g057"; + reg = <0 0x10090c00 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD R9A08G045_I2C3_PCLK>; + clock-frequency = <100000>; + resets = <&cpg R9A08G045_I2C3_MRST>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a08g045-cpg"; reg = <0 0x11010000 0 0x10000>; -- cgit From 268a99583372a0a2ae93d0969db0bf3f95d74049 Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 20 Aug 2024 13:19:17 +0300 Subject: arm64: dts: renesas: rzg3s-smarc: Enable I2C0 node Enable I2C0 node. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240820101918.2384635-11-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi index deb2ad37bb2e..7945d44e6ee1 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -11,6 +11,7 @@ / { aliases { + i2c0 = &i2c0; serial0 = &scif0; mmc1 = &sdhi1; }; @@ -66,6 +67,12 @@ }; }; +&i2c0 { + status = "okay"; + + clock-frequency = <1000000>; +}; + &pinctrl { key-1-gpio-hog { gpio-hog; -- cgit From 1670b7cc71dafd8736f47925a93dbae71093059b Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Tue, 20 Aug 2024 13:19:18 +0300 Subject: arm64: dts: renesas: rzg3s-smarc-som: Enable I2C1 node Enable I2C1 node. Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240820101918.2384635-12-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi index 8a3d302f1535..21bfa4e03972 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -32,6 +32,7 @@ compatible = "renesas,rzg3s-smarcm", "renesas,r9a08g045s33", "renesas,r9a08g045"; aliases { + i2c1 = &i2c1; mmc0 = &sdhi0; #if SW_CONFIG3 == SW_OFF mmc2 = &sdhi2; @@ -150,6 +151,10 @@ clock-frequency = <24000000>; }; +&i2c1 { + status = "okay"; +}; + #if SW_CONFIG2 == SW_ON /* SD0 slot */ &sdhi0 { -- cgit From 9b3e59b707f25bb959c83313d4ec53c16cf64e54 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 22 Aug 2024 09:44:53 +0900 Subject: arm64: dts: renesas: r8a779g0: Add PCIe Host and Endpoint nodes Add PCIe Host and Endpoint nodes for R-Car V4H (R8A779G0). Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240822004454.1087582-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 134 ++++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index c66a920060ff..5498d3a8173d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -175,6 +175,20 @@ clock-frequency = <0>; }; + pcie0_clkref: pcie0-clkref { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + pcie1_clkref: pcie1-clkref { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + pmu_a76 { compatible = "arm,cortex-a76-pmu"; interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; @@ -737,6 +751,126 @@ status = "disabled"; }; + pciec0: pcie@e65d0000 { + compatible = "renesas,r8a779g0-pcie", + "renesas,rcar-gen4-pcie"; + reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>, + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, + <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, + <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; + interrupts = , + , + , + ; + interrupt-names = "msi", "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; + snps,enable-cdm-check; + status = "disabled"; + }; + + pciec1: pcie@e65d8000 { + compatible = "renesas,r8a779g0-pcie", + "renesas,rcar-gen4-pcie"; + reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>, + <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, + <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, + <0 0xee900000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; + interrupts = , + , + , + ; + interrupt-names = "msi", "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 625>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; + snps,enable-cdm-check; + status = "disabled"; + }; + + pciec0_ep: pcie-ep@e65d0000 { + compatible = "renesas,r8a779g0-pcie-ep", + "renesas,rcar-gen4-pcie-ep"; + reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>, + <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, + <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, + <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; + interrupts = , + , + ; + interrupt-names = "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + max-functions = /bits/ 8 <2>; + status = "disabled"; + }; + + pciec1_ep: pcie-ep@e65d8000 { + compatible = "renesas,r8a779g0-pcie-ep", + "renesas,rcar-gen4-pcie-ep"; + reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>, + <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, + <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, + <0 0xee900000 0 0x400000>; + reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; + interrupts = , + , + ; + interrupt-names = "dma", "sft_ce", "app"; + clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; + clock-names = "core", "ref"; + power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>; + resets = <&cpg 625>; + reset-names = "pwr"; + max-link-speed = <4>; + num-lanes = <2>; + max-functions = /bits/ 8 <2>; + status = "disabled"; + }; + canfd: can@e6660000 { compatible = "renesas,r8a779g0-canfd", "renesas,rcar-gen4-canfd"; -- cgit From 6ca537aa160ffd2f41cca4af72aeed18c9d41b82 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 22 Aug 2024 09:44:54 +0900 Subject: arm64: dts: renesas: white-hawk-cpu-common: Enable PCIe Host ch0 Enable PCIe Host controller channel 0 on R-Car V4H White Hawk boards. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240822004454.1087582-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi index 80496fb3d476..3845b413bd24 100644 --- a/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi +++ b/arch/arm64/boot/dts/renesas/white-hawk-cpu-common.dtsi @@ -117,6 +117,12 @@ }; }; + pcie_clk: clk-9fgv0841-pci { + compatible = "fixed-clock"; + clock-frequency = <100000000>; + #clock-cells = <0>; + }; + reg_1p2v: regulator-1p2v { compatible = "regulator-fixed"; regulator-name = "fixed-1.2V"; @@ -288,6 +294,18 @@ status = "okay"; }; +&pcie0_clkref { + compatible = "gpio-gate-clock"; + clocks = <&pcie_clk>; + enable-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>; + /delete-property/ clock-frequency; +}; + +&pciec0 { + reset-gpio = <&io_expander_a 0 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; -- cgit From e895a806608a1f95067d27ae3870c9b4c5a236ee Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 22 Aug 2024 17:23:16 +0100 Subject: arm64: dts: renesas: r9a07g043u: Add DU node Add DU node to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240822162320.5084-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 1b3db8df4bbc..a3998e5928f7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -153,6 +153,31 @@ resets = <&cpg R9A07G043_LCDC_RESET_N>; }; + du: display@10890000 { + compatible = "renesas,r9a07g043u-du"; + reg = <0 0x10890000 0 0x10000>; + interrupts = ; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + renesas,vsps = <&vspd 0>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + du_out_rgb: endpoint { + }; + }; + }; + }; + irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043u-irqc", "renesas,rzg2l-irqc"; -- cgit From 73573fde91ebbf536ad1368150a1ef875ca0786f Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 26 Aug 2024 10:07:59 +0100 Subject: arm64: dts: renesas: rzg2l-smarc: Enable HDMI audio Enable HDMI audio on the RZ/{G2L,V2L} SMARC EVK. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240826090803.56176-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi | 6 +++++ arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi | 30 ++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi index 18c526c7a4cf..e9f244c33d55 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-pinfunction.dtsi @@ -143,6 +143,12 @@ ; /* RXD */ }; + ssi1_pins: ssi1 { + pinmux = , /* BCK */ + , /* RCK */ + ; /* TXD */ + }; + usb0_pins: usb0 { pinmux = , /* VBUS */ , /* OVC */ diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi index 887dffe14910..ee3d96fdb616 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc.dtsi @@ -30,6 +30,12 @@ }; }; }; + + sound_card { + compatible = "audio-graph-card"; + label = "HDMI-Audio"; + dais = <&i2s2_port>; + }; }; &cpu_dai { @@ -88,6 +94,13 @@ remote-endpoint = <&hdmi_con_out>; }; }; + + port@2 { + reg = <2>; + codec_endpoint: endpoint { + remote-endpoint = <&i2s2_cpu_endpoint>; + }; + }; }; }; }; @@ -170,6 +183,23 @@ status = "okay"; }; +&ssi1 { + pinctrl-0 = <&ssi1_pins>; + pinctrl-names = "default"; + + status = "okay"; + + i2s2_port: port { + i2s2_cpu_endpoint: endpoint { + remote-endpoint = <&codec_endpoint>; + dai-format = "i2s"; + + bitclock-master = <&i2s2_cpu_endpoint>; + frame-master = <&i2s2_cpu_endpoint>; + }; + }; +}; + &vccq_sdhi1 { gpios = <&pinctrl RZG2L_GPIO(39, 1) GPIO_ACTIVE_HIGH>; }; -- cgit From 7fe722ee4c5a2f6d718db18e5f654dd28394f097 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 26 Aug 2024 10:08:00 +0100 Subject: arm64: dts: renesas: rzg2lc-smarc: Enable HDMI audio Enable HDMI audio on the RZ/G2LC SMARC EVK. Set SW 1.5 on the SoM module to the OFF position to turn on HDMI audio. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240826090803.56176-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts | 3 +++ arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi | 33 +++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts index 0b90367b6d1e..ee5bf2c58051 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts +++ b/arch/arm64/boot/dts/renesas/r9a07g044c2-smarc.dts @@ -47,6 +47,9 @@ #error "Cannot set as both PMOD_MTU3 and SW_RSPI_CAN are mutually exclusive" #endif +/* Please set SW_I2S0_I2S1. Default value is 0 */ +#define SW_I2S0_I2S1 0 + #include "r9a07g044c2.dtsi" #include "rzg2lc-smarc-som.dtsi" #include "rzg2lc-smarc.dtsi" diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi index f21508640b6e..377849cbb462 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc.dtsi @@ -33,6 +33,16 @@ }; }; }; + +#if (SW_I2S0_I2S1) + /delete-node/ sound; + + sound_card { + compatible = "audio-graph-card"; + label = "HDMI-Audio"; + dais = <&i2s2_port>; + }; +#endif }; #if (SW_SCIF_CAN || SW_RSPI_CAN) @@ -48,9 +58,11 @@ }; #endif +#if (!SW_I2S0_I2S1) &cpu_dai { sound-dai = <&ssi0>; }; +#endif &dsi { status = "okay"; @@ -104,6 +116,15 @@ remote-endpoint = <&hdmi_con_out>; }; }; + +#if (SW_I2S0_I2S1) + port@2 { + reg = <2>; + codec_endpoint: endpoint { + remote-endpoint = <&i2s2_cpu_endpoint>; + }; + }; +#endif }; }; }; @@ -177,6 +198,18 @@ pinctrl-names = "default"; status = "okay"; + +#if (SW_I2S0_I2S1) + i2s2_port: port { + i2s2_cpu_endpoint: endpoint { + remote-endpoint = <&codec_endpoint>; + dai-format = "i2s"; + + bitclock-master = <&i2s2_cpu_endpoint>; + frame-master = <&i2s2_cpu_endpoint>; + }; + }; +#endif }; #if (SW_RSPI_CAN) -- cgit From cc49fcd0bc2db23489a87f6fa17119a76b70ec6b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 26 Aug 2024 11:16:46 +0100 Subject: arm64: dts: renesas: r9a07g043u11-smarc: Enable DU Enable the Display Unit and link with the HDMI add-on board connected to the parallel connector on the RZ/G2UL SMARC EVK by using a Device Tree overlay. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240826101648.176647-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 3 + .../dts/renesas/r9a07g043u11-smarc-du-adv7513.dtso | 62 ++++++++++++++++++ .../boot/dts/renesas/rz-smarc-du-adv7513.dtsi | 76 ++++++++++++++++++++++ 3 files changed, 141 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-du-adv7513.dtso create mode 100644 arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index fbd214a1a638..fdf597e019d7 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -112,9 +112,12 @@ dtb-$(CONFIG_ARCH_R8A77965) += r8a779m5-salvator-xs-panel-aa104xd12.dtb dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc.dtb dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtbo +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtbo dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043-smarc-pmod.dtbo r9a07g043u11-smarc-cru-csi-ov5645-dtbs := r9a07g043u11-smarc.dtb r9a07g043u11-smarc-cru-csi-ov5645.dtbo dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-cru-csi-ov5645.dtb +r9a07g043u11-smarc-du-adv7513-dtbs := r9a07g043u11-smarc.dtb r9a07g043u11-smarc-du-adv7513.dtbo +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-du-adv7513.dtb r9a07g043u11-smarc-pmod-dtbs := r9a07g043u11-smarc.dtb r9a07g043-smarc-pmod.dtbo dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043u11-smarc-pmod.dtb diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-du-adv7513.dtso b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-du-adv7513.dtso new file mode 100644 index 000000000000..ecd43a671000 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a07g043u11-smarc-du-adv7513.dtso @@ -0,0 +1,62 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree overlay for the RZ/G2UL SMARC EVK with ADV7513 transmitter + * connected to DU enabled. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; +/plugin/; + +#include + +#define ADV7513_PARENT_I2C i2c1 +#include "rz-smarc-du-adv7513.dtsi" + +&pinctrl { + du_pins: du { + data { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = <2>; + }; + + sync { + pinmux = , /* HSYNC */ + ; /* VSYNC */ + drive-strength = <2>; + }; + + de { + pinmux = ; /* DE */ + drive-strength = <2>; + }; + + clk { + pinmux = ; /* CLK */ + }; + }; +}; diff --git a/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi b/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi new file mode 100644 index 000000000000..36707576030d --- /dev/null +++ b/arch/arm64/boot/dts/renesas/rz-smarc-du-adv7513.dtsi @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common Device Tree for the RZ/G2UL SMARC EVK (and alike EVKs) with + * ADV7513 transmitter connected to DU enabled. + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +&{/} { + hdmi-out { + compatible = "hdmi-connector"; + type = "d"; + + port { + hdmi_con_out: endpoint { + remote-endpoint = <&adv7513_out>; + }; + }; + }; +}; + +&du { + pinctrl-0 = <&du_pins>; + pinctrl-names = "default"; + + status = "okay"; + + ports { + port@0 { + du_out_rgb: endpoint { + remote-endpoint = <&adv7513_in>; + }; + }; + }; +}; + +&ADV7513_PARENT_I2C { + #address-cells = <1>; + #size-cells = <0>; + + adv7513: adv7513@39 { + compatible = "adi,adv7513"; + reg = <0x39>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + avdd-supply = <®_1p8v>; + dvdd-supply = <®_1p8v>; + pvdd-supply = <®_1p8v>; + dvdd-3v-supply = <®_3p3v>; + bgvdd-supply = <®_1p8v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7513_in: endpoint { + remote-endpoint = <&du_out_rgb>; + }; + }; + + port@1 { + reg = <1>; + + adv7513_out: endpoint { + remote-endpoint = <&hdmi_con_out>; + }; + }; + }; + }; +}; -- cgit From afec1aba08607b18cfd00fdcd6525aeca0e187bf Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 29 Jul 2024 21:26:43 +0100 Subject: dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG Document the device tree bindings for the Renesas RZ/V2H(P) SoC Clock Pulse Generator (CPG). CPG block handles the below operations: - Generation and control of clock signals for the IP modules - Generation and control of resets - Control over booting - Low power consumption and power supply domains Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the core clocks are a subset of the ones which are listed as part of section 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240729202645.263525-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../bindings/clock/renesas,rzv2h-cpg.yaml | 80 ++++++++++++++++++++++ include/dt-bindings/clock/renesas,r9a09g057-cpg.h | 21 ++++++ 2 files changed, 101 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml create mode 100644 include/dt-bindings/clock/renesas,r9a09g057-cpg.h diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml new file mode 100644 index 000000000000..926c503bed1f --- /dev/null +++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/renesas,rzv2h-cpg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2H(P) Clock Pulse Generator (CPG) + +maintainers: + - Lad Prabhakar + +description: + On Renesas RZ/V2H(P) SoCs, the CPG (Clock Pulse Generator) handles generation + and control of clock signals for the IP modules, generation and control of resets, + and control over booting, low power consumption and power supply domains. + +properties: + compatible: + const: renesas,r9a09g057-cpg + + reg: + maxItems: 1 + + clocks: + items: + - description: AUDIO_EXTAL clock input + - description: RTXIN clock input + - description: QEXTAL clock input + + clock-names: + items: + - const: audio_extal + - const: rtxin + - const: qextal + + '#clock-cells': + description: | + - For CPG core clocks, the two clock specifier cells must be "CPG_CORE" + and a core clock reference, as defined in + , + - For module clocks, the two clock specifier cells must be "CPG_MOD" and + a module number. The module number is calculated as the CLKON register + offset index multiplied by 16, plus the actual bit in the register + used to turn the CLK ON. For example, for CGC_GIC_0_GICCLK, the + calculation is (1 * 16 + 3) = 0x13. + const: 2 + + '#power-domain-cells': + const: 0 + + '#reset-cells': + description: + The single reset specifier cell must be the reset number. The reset number + is calculated as the reset register offset index multiplied by 16, plus the + actual bit in the register used to reset the specific IP block. For example, + for SYS_0_PRESETN, the calculation is (3 * 16 + 0) = 0x30. + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#power-domain-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + clock-controller@10420000 { + compatible = "renesas,r9a09g057-cpg"; + reg = <0x10420000 0x10000>; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; + clock-names = "audio_extal", "rtxin", "qextal"; + #clock-cells = <2>; + #power-domain-cells = <0>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/renesas,r9a09g057-cpg.h b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h new file mode 100644 index 000000000000..541e6d719bd6 --- /dev/null +++ b/include/dt-bindings/clock/renesas,r9a09g057-cpg.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ +#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ +#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ + +#include + +/* Core Clock list */ +#define R9A09G057_SYS_0_PCLK 0 +#define R9A09G057_CA55_0_CORE_CLK0 1 +#define R9A09G057_CA55_0_CORE_CLK1 2 +#define R9A09G057_CA55_0_CORE_CLK2 3 +#define R9A09G057_CA55_0_CORE_CLK3 4 +#define R9A09G057_CA55_0_PERIPHCLK 5 +#define R9A09G057_CM33_CLK0 6 +#define R9A09G057_CST_0_SWCLKTCK 7 +#define R9A09G057_IOTOP_0_SHCLK 8 + +#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ */ -- cgit From 15bba65c1927ec8fde95611f316146d0743f16d5 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 28 Aug 2024 13:41:26 +0100 Subject: dt-bindings: soc: renesas: Document RZ/V2H EVK board Add "renesas,rzv2h-evk" which targets the Renesas RZ/V2H ("R9A09G057") EVK board. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring (Arm) Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240828124134.188864-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 09d3ce97efa2..42a94a88f3ae 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -515,6 +515,8 @@ properties: - description: RZ/V2H(P) (R9A09G057) items: + - enum: + - renesas,rzv2h-evk # RZ/V2H EVK - enum: - renesas,r9a09g057h41 # RZ/V2H - renesas,r9a09g057h42 # RZ/V2H with Mali-G31 support -- cgit From 740cf2a2d6868a63a12e89c8dd92333b39fd1c7d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 28 Aug 2024 13:41:27 +0100 Subject: arm64: dts: renesas: Add initial SoC DTSI for RZ/V2H(P) SoC Add initial SoC DTSI for Renesas RZ/V2H(P) ("R9A09G057") SoC, below are the list of blocks added: - EXT CLKs - 4X CA55 - SCIF - PFC - CPG - SYS - GIC - ARMv8 Timer Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240828124134.188864-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 165 +++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g057.dtsi diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi new file mode 100644 index 000000000000..35b34c40cdc8 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2H(P) SoC + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a09g057"; + #address-cells = <2>; + #size-cells = <2>; + + audio_extal_clk: audio-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a55"; + reg = <0>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu1: cpu@100 { + compatible = "arm,cortex-a55"; + reg = <0x100>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu2: cpu@200 { + compatible = "arm,cortex-a55"; + reg = <0x200>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + cpu3: cpu@300 { + compatible = "arm,cortex-a55"; + reg = <0x300>; + device_type = "cpu"; + next-level-cache = <&L3_CA55>; + enable-method = "psci"; + }; + + L3_CA55: cache-controller-0 { + compatible = "cache"; + cache-unified; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + + psci { + compatible = "arm,psci-1.0", "arm,psci-0.2"; + method = "smc"; + }; + + qextal_clk: qextal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + rtxin_clk: rtxin-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + pinctrl: pinctrl@10410000 { + compatible = "renesas,r9a09g057-pinctrl"; + reg = <0 0x10410000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 96>; + #interrupt-cells = <2>; + interrupt-controller; + power-domains = <&cpg>; + resets = <&cpg 0xa5>, <&cpg 0xa6>; + }; + + cpg: clock-controller@10420000 { + compatible = "renesas,r9a09g057-cpg"; + reg = <0 0x10420000 0 0x10000>; + clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; + clock-names = "audio_extal", "rtxin", "qextal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sys: system-controller@10430000 { + compatible = "renesas,r9a09g057-sys"; + reg = <0 0x10430000 0 0x10000>; + clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; + resets = <&cpg 0x30>; + status = "disabled"; + }; + + scif: serial@11c01400 { + compatible = "renesas,scif-r9a09g057"; + reg = <0 0x11c01400 0 0x400>; + interrupts = , + , + , + , + , + , + , + , + ; + interrupt-names = "eri", "rxi", "txi", "bri", "dri", + "tei", "tei-dri", "rxi-edge", "txi-edge"; + clocks = <&cpg CPG_MOD 0x8f>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg 0x95>; + status = "disabled"; + }; + + gic: interrupt-controller@14900000 { + compatible = "arm,gic-v3"; + reg = <0x0 0x14900000 0 0x20000>, + <0x0 0x14940000 0 0x80000>; + #interrupt-cells = <3>; + #address-cells = <0>; + interrupt-controller; + interrupts = ; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; + }; +}; -- cgit From 2fddca72dc9591ea037fe86ad90a30708f4cb496 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 28 Aug 2024 13:41:28 +0100 Subject: arm64: dts: renesas: Add initial DTS for RZ/V2H EVK board Add initial DTS for RZ/V2H EVK board (based on R9A09G057H44), adding the below support: - Memory - Clock inputs - PINCTRL - SCIF Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240828124134.188864-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 2 + .../boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 61 ++++++++++++++++++++++ 2 files changed, 63 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index fdf597e019d7..97228a3cb99c 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -140,5 +140,7 @@ dtb-$(CONFIG_ARCH_R9A08G045) += r9a08g045s33-smarc.dtb dtb-$(CONFIG_ARCH_R9A09G011) += r9a09g011-v2mevk2.dtb +dtb-$(CONFIG_ARCH_R9A09G057) += r9a09g057h44-rzv2h-evk.dtb + dtb-$(CONFIG_ARCH_RCAR_GEN3) += draak-ebisu-panel-aa104xd12.dtbo dtb-$(CONFIG_ARCH_RCAR_GEN3) += salvator-panel-aa104xd12.dtbo diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts new file mode 100644 index 000000000000..47f6f2bf6925 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/V2H EVK board + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +/dts-v1/; + +#include "r9a09g057.dtsi" + +/ { + model = "Renesas RZ/V2H EVK Board based on r9a09g057h44"; + compatible = "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; + + aliases { + serial0 = &scif; + }; + + chosen { + bootargs = "ignore_loglevel"; + stdout-path = "serial0:115200n8"; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0x0 0x48000000 0x1 0xF8000000>; + }; + + memory@240000000 { + device_type = "memory"; + reg = <0x2 0x40000000 0x2 0x00000000>; + }; +}; + +&audio_extal_clk { + clock-frequency = <22579200>; +}; + +&pinctrl { + scif_pins: scif { + pins = "SCIF_TXD", "SCIF_RXD"; + renesas,output-impedance = <1>; + }; +}; + +&qextal_clk { + clock-frequency = <24000000>; +}; + +&rtxin_clk { + clock-frequency = <32768>; +}; + +&scif { + pinctrl-0 = <&scif_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; -- cgit From e3dc593ef3a854c8a0817b456269a806a9688277 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 28 Aug 2024 13:41:29 +0100 Subject: arm64: dts: renesas: r9a09g057: Add OSTM0-OSTM7 nodes Add OSTM0-OSTM7 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240828124134.188864-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 80 ++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 35b34c40cdc8..335a6dd17fce 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -121,6 +121,86 @@ status = "disabled"; }; + ostm0: timer@11800000 { + compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; + reg = <0x0 0x11800000 0x0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0x43>; + resets = <&cpg 0x6d>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm1: timer@11801000 { + compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; + reg = <0x0 0x11801000 0x0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0x44>; + resets = <&cpg 0x6e>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm2: timer@14000000 { + compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; + reg = <0x0 0x14000000 0x0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0x45>; + resets = <&cpg 0x6f>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm3: timer@14001000 { + compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; + reg = <0x0 0x14001000 0x0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0x46>; + resets = <&cpg 0x70>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm4: timer@12c00000 { + compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; + reg = <0x0 0x12c00000 0x0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0x47>; + resets = <&cpg 0x71>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm5: timer@12c01000 { + compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; + reg = <0x0 0x12c01000 0x0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0x48>; + resets = <&cpg 0x72>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm6: timer@12c02000 { + compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; + reg = <0x0 0x12c02000 0x0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0x49>; + resets = <&cpg 0x73>; + power-domains = <&cpg>; + status = "disabled"; + }; + + ostm7: timer@12c03000 { + compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; + reg = <0x0 0x12c03000 0x0 0x1000>; + interrupts = ; + clocks = <&cpg CPG_MOD 0x4a>; + resets = <&cpg 0x74>; + power-domains = <&cpg>; + status = "disabled"; + }; + scif: serial@11c01400 { compatible = "renesas,scif-r9a09g057"; reg = <0 0x11c01400 0 0x400>; -- cgit From 04c80e7bed79024b7753dd071ecf90147e9dd10d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 28 Aug 2024 13:41:30 +0100 Subject: arm64: dts: renesas: r9a09g057: Add RIIC0-RIIC8 nodes Add RIIC0-RIIC8 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240828124134.188864-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 189 +++++++++++++++++++++++++++++ 1 file changed, 189 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 335a6dd17fce..b1017efdc242 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -222,6 +222,195 @@ status = "disabled"; }; + i2c0: i2c@14400400 { + compatible = "renesas,riic-r9a09g057"; + reg = <0 0x14400400 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x94>; + resets = <&cpg 0x98>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@14400800 { + compatible = "renesas,riic-r9a09g057"; + reg = <0 0x14400800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x95>; + resets = <&cpg 0x99>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@14400c00 { + compatible = "renesas,riic-r9a09g057"; + reg = <0 0x14400c00 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x96>; + resets = <&cpg 0x9a>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@14401000 { + compatible = "renesas,riic-r9a09g057"; + reg = <0 0x14401000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x97>; + resets = <&cpg 0x9b>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c4: i2c@14401400 { + compatible = "renesas,riic-r9a09g057"; + reg = <0 0x14401400 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x98>; + resets = <&cpg 0x9c>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c5: i2c@14401800 { + compatible = "renesas,riic-r9a09g057"; + reg = <0 0x14401800 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x99>; + resets = <&cpg 0x9d>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c6: i2c@14401c00 { + compatible = "renesas,riic-r9a09g057"; + reg = <0 0x14401c00 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x9a>; + resets = <&cpg 0x9e>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@14402000 { + compatible = "renesas,riic-r9a09g057"; + reg = <0 0x14402000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x9b>; + resets = <&cpg 0x9f>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@11c01000 { + compatible = "renesas,riic-r9a09g057"; + reg = <0 0x11c01000 0 0x400>; + interrupts = , + , + , + , + , + , + , + ; + interrupt-names = "tei", "ri", "ti", "spi", "sti", + "naki", "ali", "tmoi"; + clocks = <&cpg CPG_MOD 0x93>; + resets = <&cpg 0xa0>; + power-domains = <&cpg>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gic: interrupt-controller@14900000 { compatible = "arm,gic-v3"; reg = <0x0 0x14900000 0 0x20000>, -- cgit From 2cc5322acdb4b170cfc8ba8775198e1b8915dc82 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 28 Aug 2024 13:41:31 +0100 Subject: arm64: dts: renesas: r9a09g057: Add SDHI0-SDHI2 nodes Add SDHI0-SDHI2 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240828124134.188864-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 39 ++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index b1017efdc242..9f6939a4e40f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -420,6 +420,45 @@ interrupt-controller; interrupts = ; }; + + sdhi0: mmc@15c00000 { + compatible = "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c00000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, + <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 0xa7>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi1: mmc@15c10000 { + compatible = "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c10000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, + <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 0xa8>; + power-domains = <&cpg>; + status = "disabled"; + }; + + sdhi2: mmc@15c20000 { + compatible = "renesas,sdhi-r9a09g057"; + reg = <0x0 0x15c20000 0 0x10000>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, + <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; + clock-names = "core", "clkh", "cd", "aclk"; + resets = <&cpg 0xa9>; + power-domains = <&cpg>; + status = "disabled"; + }; }; timer { -- cgit From 095105496e7dde554aa3dc01189779759d976c2d Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 28 Aug 2024 13:41:32 +0100 Subject: arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240828124134.188864-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 40 ++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi index 9f6939a4e40f..1ad5a1b6917f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi @@ -201,6 +201,46 @@ status = "disabled"; }; + wdt0: watchdog@11c00400 { + compatible = "renesas,r9a09g057-wdt"; + reg = <0 0x11c00400 0 0x400>; + clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x75>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt1: watchdog@14400000 { + compatible = "renesas,r9a09g057-wdt"; + reg = <0 0x14400000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x76>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt2: watchdog@13000000 { + compatible = "renesas,r9a09g057-wdt"; + reg = <0 0x13000000 0 0x400>; + clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x77>; + power-domains = <&cpg>; + status = "disabled"; + }; + + wdt3: watchdog@13000400 { + compatible = "renesas,r9a09g057-wdt"; + reg = <0 0x13000400 0 0x400>; + clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; + clock-names = "pclk", "oscclk"; + resets = <&cpg 0x78>; + power-domains = <&cpg>; + status = "disabled"; + }; + scif: serial@11c01400 { compatible = "renesas,scif-r9a09g057"; reg = <0 0x11c01400 0 0x400>; -- cgit From 5f0dad980205e497434671a24255a29609646b85 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 28 Aug 2024 13:41:33 +0100 Subject: arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable OSTM, I2C, and SDHI Enable OSTM0-OSTM7, RIIC{0,1,2,3,6,7,8}, and SDHI1 (available on the SD2 connector) on the RZ/V2H EVK platform. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240828124134.188864-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 191 +++++++++++++++++++++ 1 file changed, 191 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 47f6f2bf6925..18f3fb33439a 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -7,6 +7,8 @@ /dts-v1/; +#include +#include #include "r9a09g057.dtsi" / { @@ -14,6 +16,14 @@ compatible = "renesas,rzv2h-evk", "renesas,r9a09g057h44", "renesas,r9a09g057"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c6 = &i2c6; + i2c7 = &i2c7; + i2c8 = &i2c8; + mmc1 = &sdhi1; serial0 = &scif; }; @@ -32,17 +42,186 @@ device_type = "memory"; reg = <0x2 0x40000000 0x2 0x00000000>; }; + + reg_3p3v: regulator1 { + compatible = "regulator-fixed"; + + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + vqmmc_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + regulator-name = "SDHI1 VccQ"; + gpios = <&pinctrl RZG2L_GPIO(10, 2) GPIO_ACTIVE_HIGH>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + gpios-states = <0>; + states = <3300000 0>, <1800000 1>; + }; }; &audio_extal_clk { clock-frequency = <22579200>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c6 { + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c7 { + pinctrl-0 = <&i2c7_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; +}; + +&i2c8 { + pinctrl-0 = <&i2c8_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + + status = "okay"; +}; + +&ostm0 { + status = "okay"; +}; + +&ostm1 { + status = "okay"; +}; + +&ostm2 { + status = "okay"; +}; + +&ostm3 { + status = "okay"; +}; + +&ostm4 { + status = "okay"; +}; + +&ostm5 { + status = "okay"; +}; + +&ostm6 { + status = "okay"; +}; + +&ostm7 { + status = "okay"; +}; + &pinctrl { + i2c0_pins: i2c0 { + pinmux = , /* I2C0_SDA */ + ; /* I2C0_SCL */ + }; + + i2c1_pins: i2c1 { + pinmux = , /* I2C1_SDA */ + ; /* I2C1_SCL */ + }; + + i2c2_pins: i2c2 { + pinmux = , /* I2C2_SDA */ + ; /* I2C2_SCL */ + }; + + i2c3_pins: i2c3 { + pinmux = , /* I2C3_SDA */ + ; /* I2C3_SCL */ + }; + + i2c6_pins: i2c6 { + pinmux = , /* I2C6_SDA */ + ; /* I2C6_SCL */ + }; + + i2c7_pins: i2c7 { + pinmux = , /* I2C7_SDA */ + ; /* I2C7_SCL */ + }; + + i2c8_pins: i2c8 { + pinmux = , /* I2C8_SDA */ + ; /* I2C8_SCL */ + }; + scif_pins: scif { pins = "SCIF_TXD", "SCIF_RXD"; renesas,output-impedance = <1>; }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "sd1_pwr_en"; + }; + + sdhi1_pins: sd1 { + sd1_dat_cmd { + pins = "SD1DAT0", "SD1DAT1", "SD1DAT2", "SD1DAT3", "SD1CMD"; + input-enable; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd1_clk { + pins = "SD1CLK"; + renesas,output-impedance = <3>; + slew-rate = <0>; + }; + + sd1_cd { + pinmux = ; /* SD1_CD */ + }; + }; }; &qextal_clk { @@ -59,3 +238,15 @@ status = "okay"; }; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins>; + pinctrl-names = "default", "state_uhs"; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vqmmc_sdhi1>; + bus-width = <4>; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; -- cgit From 686bba2a17f43ddc68596a88850e6407c4829d67 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Wed, 28 Aug 2024 13:41:34 +0100 Subject: arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable watchdog Enable WDT1 watchdog on RZ/V2H EVK platform. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240828124134.188864-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts index 18f3fb33439a..4703da8e9cff 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts @@ -250,3 +250,7 @@ sd-uhs-sdr104; status = "okay"; }; + +&wdt1 { + status = "okay"; +}; -- cgit From 8c07e11916ffcfa29c300cf45ebd868ee15f18fc Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Thu, 4 Jul 2024 18:16:16 +0200 Subject: arm64: dts: renesas: r8a779g0: Add family fallback for VIN IP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To make it easier to support new R-Car Gen4 SoCs a family fallback compatible similar to what is used for R-Car Gen2 has been added to the VIN bindings. Add this fallback to the R-Car V4H DTSI. There is no functional change, but the addition of the family fallback in the bindings produces warnings for R-Car V4H for DTS checks if they are not added. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/20240704161620.1425409-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 48 ++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 5498d3a8173d..5a518db0b07c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -1335,7 +1335,8 @@ }; vin00: video@e6ef0000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 730>; @@ -1363,7 +1364,8 @@ }; vin01: video@e6ef1000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 731>; @@ -1391,7 +1393,8 @@ }; vin02: video@e6ef2000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 800>; @@ -1419,7 +1422,8 @@ }; vin03: video@e6ef3000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 801>; @@ -1447,7 +1451,8 @@ }; vin04: video@e6ef4000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef4000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 802>; @@ -1475,7 +1480,8 @@ }; vin05: video@e6ef5000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef5000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 803>; @@ -1503,7 +1509,8 @@ }; vin06: video@e6ef6000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef6000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 804>; @@ -1531,7 +1538,8 @@ }; vin07: video@e6ef7000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef7000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 805>; @@ -1559,7 +1567,8 @@ }; vin08: video@e6ef8000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef8000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 806>; @@ -1587,7 +1596,8 @@ }; vin09: video@e6ef9000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef9000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 807>; @@ -1615,7 +1625,8 @@ }; vin10: video@e6efa000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efa000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 808>; @@ -1643,7 +1654,8 @@ }; vin11: video@e6efb000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efb000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 809>; @@ -1671,7 +1683,8 @@ }; vin12: video@e6efc000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efc000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 810>; @@ -1699,7 +1712,8 @@ }; vin13: video@e6efd000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efd000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 811>; @@ -1727,7 +1741,8 @@ }; vin14: video@e6efe000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efe000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; @@ -1755,7 +1770,8 @@ }; vin15: video@e6eff000 { - compatible = "renesas,vin-r8a779g0"; + compatible = "renesas,vin-r8a779g0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6eff000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 813>; -- cgit From e9f351d67d59cc4d7797c802afb92a7a2071abde Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Thu, 4 Jul 2024 18:16:17 +0200 Subject: arm64: dts: renesas: r8a779a0: Add family fallback for VIN IP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To make it easier to support new R-Car Gen4 SoCs a family fallback compatible similar to what is used for R-Car Gen2 has been added to the VIN bindings. Add this fallback to the R-Car V3U DTSI. There is no functional change, but the addition of the family fallback in the bindings produces warnings for R-Car V3U for DTS checks if they are not added. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/20240704161620.1425409-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 96 ++++++++++++++++++++----------- 1 file changed, 64 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 69652d309fe6..bf23cc1dc7be 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -1174,7 +1174,8 @@ }; vin00: video@e6ef0000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 730>; @@ -1202,7 +1203,8 @@ }; vin01: video@e6ef1000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 731>; @@ -1230,7 +1232,8 @@ }; vin02: video@e6ef2000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 800>; @@ -1258,7 +1261,8 @@ }; vin03: video@e6ef3000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 801>; @@ -1286,7 +1290,8 @@ }; vin04: video@e6ef4000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef4000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 802>; @@ -1314,7 +1319,8 @@ }; vin05: video@e6ef5000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef5000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 803>; @@ -1342,7 +1348,8 @@ }; vin06: video@e6ef6000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef6000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 804>; @@ -1370,7 +1377,8 @@ }; vin07: video@e6ef7000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef7000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 805>; @@ -1398,7 +1406,8 @@ }; vin08: video@e6ef8000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef8000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 806>; @@ -1426,7 +1435,8 @@ }; vin09: video@e6ef9000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef9000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 807>; @@ -1454,7 +1464,8 @@ }; vin10: video@e6efa000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efa000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 808>; @@ -1482,7 +1493,8 @@ }; vin11: video@e6efb000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efb000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 809>; @@ -1510,7 +1522,8 @@ }; vin12: video@e6efc000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efc000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 810>; @@ -1538,7 +1551,8 @@ }; vin13: video@e6efd000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efd000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 811>; @@ -1566,7 +1580,8 @@ }; vin14: video@e6efe000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efe000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; @@ -1594,7 +1609,8 @@ }; vin15: video@e6eff000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6eff000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 813>; @@ -1622,7 +1638,8 @@ }; vin16: video@e6ed0000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ed0000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 814>; @@ -1650,7 +1667,8 @@ }; vin17: video@e6ed1000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ed1000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 815>; @@ -1678,7 +1696,8 @@ }; vin18: video@e6ed2000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ed2000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 816>; @@ -1706,7 +1725,8 @@ }; vin19: video@e6ed3000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ed3000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 817>; @@ -1734,7 +1754,8 @@ }; vin20: video@e6ed4000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ed4000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 818>; @@ -1762,7 +1783,8 @@ }; vin21: video@e6ed5000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ed5000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 819>; @@ -1790,7 +1812,8 @@ }; vin22: video@e6ed6000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ed6000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 820>; @@ -1818,7 +1841,8 @@ }; vin23: video@e6ed7000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ed7000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 821>; @@ -1846,7 +1870,8 @@ }; vin24: video@e6ed8000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ed8000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 822>; @@ -1874,7 +1899,8 @@ }; vin25: video@e6ed9000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ed9000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 823>; @@ -1902,7 +1928,8 @@ }; vin26: video@e6eda000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6eda000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 824>; @@ -1930,7 +1957,8 @@ }; vin27: video@e6edb000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6edb000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 825>; @@ -1958,7 +1986,8 @@ }; vin28: video@e6edc000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6edc000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 826>; @@ -1986,7 +2015,8 @@ }; vin29: video@e6edd000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6edd000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 827>; @@ -2014,7 +2044,8 @@ }; vin30: video@e6ede000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ede000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 828>; @@ -2042,7 +2073,8 @@ }; vin31: video@e6edf000 { - compatible = "renesas,vin-r8a779a0"; + compatible = "renesas,vin-r8a779a0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6edf000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 829>; -- cgit From c92be7b6b3559d58b6631c15c6d3889d8eb486a5 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Thu, 4 Jul 2024 18:16:20 +0200 Subject: arm64: dts: renesas: r8a779h0: Add family fallback for VIN IP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The usage of the R-Car V4M VIN bindings where merged before the bindings where approved. At that time the family fallback compatible was not part of the bindings, add it. Fixes: 2bb78d9fb7c9 ("arm64: dts: renesas: r8a779h0: Add video capture nodes") Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/20240704161620.1425409-7-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 48 ++++++++++++++++++++----------- 1 file changed, 32 insertions(+), 16 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index f34b71539e52..28ca59e735e5 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -1039,7 +1039,8 @@ }; vin00: video@e6ef0000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 730>; @@ -1067,7 +1068,8 @@ }; vin01: video@e6ef1000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 731>; @@ -1095,7 +1097,8 @@ }; vin02: video@e6ef2000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 800>; @@ -1123,7 +1126,8 @@ }; vin03: video@e6ef3000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 801>; @@ -1151,7 +1155,8 @@ }; vin04: video@e6ef4000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef4000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 802>; @@ -1179,7 +1184,8 @@ }; vin05: video@e6ef5000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef5000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 803>; @@ -1207,7 +1213,8 @@ }; vin06: video@e6ef6000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef6000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 804>; @@ -1235,7 +1242,8 @@ }; vin07: video@e6ef7000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef7000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 805>; @@ -1263,7 +1271,8 @@ }; vin08: video@e6ef8000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef8000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 806>; @@ -1291,7 +1300,8 @@ }; vin09: video@e6ef9000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6ef9000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 807>; @@ -1319,7 +1329,8 @@ }; vin10: video@e6efa000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efa000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 808>; @@ -1347,7 +1358,8 @@ }; vin11: video@e6efb000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efb000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 809>; @@ -1375,7 +1387,8 @@ }; vin12: video@e6efc000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efc000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 810>; @@ -1403,7 +1416,8 @@ }; vin13: video@e6efd000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efd000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 811>; @@ -1431,7 +1445,8 @@ }; vin14: video@e6efe000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6efe000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 812>; @@ -1459,7 +1474,8 @@ }; vin15: video@e6eff000 { - compatible = "renesas,vin-r8a779h0"; + compatible = "renesas,vin-r8a779h0", + "renesas,rcar-gen4-vin"; reg = <0 0xe6eff000 0 0x1000>; interrupts = ; clocks = <&cpg CPG_MOD 813>; -- cgit From 2c5c9e37c10e5c84035d7b202050c0879f135ef9 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Mon, 26 Aug 2024 16:43:48 +0200 Subject: arm64: dts: renesas: r8a779g0: Add family fallback for CSISP IP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To make it easier to support new R-Car Gen4 SoCs add a family fallback compatible similar to what was done for VIN on R-Car Gen4. There is no functional change, but the addition of the family fallback in the bindings produces warnings for R-Car V4H for DTS checks if they are not added. Signed-off-by: Niklas Söderlund Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240826144352.3026980-3-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index 5a518db0b07c..12900ebd098b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -2223,7 +2223,8 @@ }; isp0: isp@fed00000 { - compatible = "renesas,r8a779g0-isp"; + compatible = "renesas,r8a779g0-isp", + "renesas,rcar-gen4-isp"; reg = <0 0xfed00000 0 0x10000>; interrupts = ; clocks = <&cpg CPG_MOD 612>; @@ -2306,7 +2307,8 @@ }; isp1: isp@fed20000 { - compatible = "renesas,r8a779g0-isp"; + compatible = "renesas,r8a779g0-isp", + "renesas,rcar-gen4-isp"; reg = <0 0xfed20000 0 0x10000>; interrupts = ; clocks = <&cpg CPG_MOD 613>; -- cgit From af9e91cb97923b79dc4be6f9eb8359c6bb98be52 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Mon, 26 Aug 2024 16:43:49 +0200 Subject: arm64: dts: renesas: r8a779a0: Add family fallback for CSISP IP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To make it easier to support new R-Car Gen4 SoCs add a family fallback compatible similar to what was done for VIN on R-Car Gen4. There is no functional change, but the addition of the family fallback in the bindings produces warnings for R-Car V3U for DTS checks if they are not added. Signed-off-by: Niklas Söderlund Reviewed-by: Laurent Pinchart Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20240826144352.3026980-4-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index bf23cc1dc7be..1f4ab27acc33 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2501,7 +2501,8 @@ }; isp0: isp@fed00000 { - compatible = "renesas,r8a779a0-isp"; + compatible = "renesas,r8a779a0-isp", + "renesas,rcar-gen4-isp"; reg = <0 0xfed00000 0 0x10000>; interrupts = ; clocks = <&cpg CPG_MOD 612>; @@ -2584,7 +2585,8 @@ }; isp1: isp@fed20000 { - compatible = "renesas,r8a779a0-isp"; + compatible = "renesas,r8a779a0-isp", + "renesas,rcar-gen4-isp"; reg = <0 0xfed20000 0 0x10000>; interrupts = ; clocks = <&cpg CPG_MOD 613>; @@ -2667,7 +2669,8 @@ }; isp2: isp@fed30000 { - compatible = "renesas,r8a779a0-isp"; + compatible = "renesas,r8a779a0-isp", + "renesas,rcar-gen4-isp"; reg = <0 0xfed30000 0 0x10000>; interrupts = ; clocks = <&cpg CPG_MOD 614>; @@ -2750,7 +2753,8 @@ }; isp3: isp@fed40000 { - compatible = "renesas,r8a779a0-isp"; + compatible = "renesas,r8a779a0-isp", + "renesas,rcar-gen4-isp"; reg = <0 0xfed40000 0 0x10000>; interrupts = ; clocks = <&cpg CPG_MOD 615>; -- cgit From cc41aa93bbafdfe4c4c9026d307adbb89c1d80fa Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Mon, 26 Aug 2024 16:43:52 +0200 Subject: arm64: dts: renesas: r8a779h0: Add family fallback for CSISP IP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The usage of the R-Car V4M CSISP bindings where merged before the bindings where approved. At that time the family fallback compatible where not part of the bindings, add them. Fixes: 2bb78d9fb7c9 ("arm64: dts: renesas: r8a779h0: Add video capture nodes") Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Reviewed-by: Laurent Pinchart Link: https://lore.kernel.org/20240826144352.3026980-7-niklas.soderlund+renesas@ragnatech.se Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi index 28ca59e735e5..12d8be3fd579 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi @@ -1829,7 +1829,8 @@ }; isp0: isp@fed00000 { - compatible = "renesas,r8a779h0-isp"; + compatible = "renesas,r8a779h0-isp", + "renesas,rcar-gen4-isp"; reg = <0 0xfed00000 0 0x10000>; interrupts = ; clocks = <&cpg CPG_MOD 612>; @@ -1912,7 +1913,8 @@ }; isp1: isp@fed20000 { - compatible = "renesas,r8a779h0-isp"; + compatible = "renesas,r8a779h0-isp", + "renesas,rcar-gen4-isp"; reg = <0 0xfed20000 0 0x10000>; interrupts = ; clocks = <&cpg CPG_MOD 613>; -- cgit