From 65e412a01bc0161175a962abd5a7fef6a62d5c8e Mon Sep 17 00:00:00 2001 From: Shengjiu Wang Date: Wed, 13 May 2020 13:30:35 +0800 Subject: ASoC: wm8962: Use force clear for WM8962_SYSCLK_ENA after reset When CLOCKING2 is non-volatile register, we need force clear the WM8962_SYSCLK_ENA bit after reset, for the value in cache maybe 0 but in hardware it is 1. Otherwise there will issue as below statement in driver. /* SYSCLK defaults to on; make sure it is off so we can safely * write to registers if the device is declocked. Fixes: c38b608504aa ("ASoC: wm8962: set CLOCKING2 as non-volatile register") Signed-off-by: Shengjiu Wang Acked-by: Charles Keepax Link: https://lore.kernel.org/r/1589347835-20554-1-git-send-email-shengjiu.wang@nxp.com Signed-off-by: Mark Brown --- sound/soc/codecs/wm8962.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/wm8962.c b/sound/soc/codecs/wm8962.c index 0a2cfff44441..08d19df8a700 100644 --- a/sound/soc/codecs/wm8962.c +++ b/sound/soc/codecs/wm8962.c @@ -3798,8 +3798,8 @@ static int wm8962_runtime_resume(struct device *dev) /* SYSCLK defaults to on; make sure it is off so we can safely * write to registers if the device is declocked. */ - regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, - WM8962_SYSCLK_ENA, 0); + regmap_write_bits(wm8962->regmap, WM8962_CLOCKING2, + WM8962_SYSCLK_ENA, 0); /* Ensure we have soft control over all registers */ regmap_update_bits(wm8962->regmap, WM8962_CLOCKING2, -- cgit From 0e36f32f6b6c4c86a6bf3d6f0940831691b0a3b0 Mon Sep 17 00:00:00 2001 From: Dan Murphy Date: Wed, 13 May 2020 09:28:07 -0500 Subject: ASoC: tlv320adcx140: Fix bias config values The device tree binding declares the ti,mic-bias-source and the ti,vref-source properties as u32. The code reads them as u8 which is incorrect. Since the device tree binding indicates them as u32 the conde needs to be updated to read u32. In addition the bias source needs to be shifted 4 bits to correctly write the register. driver family") Fixes: 37bde5acf040 ("ASoC: tlv320adcx140: Add the tlv320adcx140 codec Signed-off-by: Dan Murphy Link: https://lore.kernel.org/r/20200513142807.11802-1-dmurphy@ti.com Signed-off-by: Mark Brown --- sound/soc/codecs/tlv320adcx140.c | 13 +++++++------ sound/soc/codecs/tlv320adcx140.h | 1 + 2 files changed, 8 insertions(+), 6 deletions(-) diff --git a/sound/soc/codecs/tlv320adcx140.c b/sound/soc/codecs/tlv320adcx140.c index 0f713efde046..1d7d7b34a46e 100644 --- a/sound/soc/codecs/tlv320adcx140.c +++ b/sound/soc/codecs/tlv320adcx140.c @@ -739,11 +739,12 @@ static int adcx140_codec_probe(struct snd_soc_component *component) { struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component); int sleep_cfg_val = ADCX140_WAKE_DEV; - u8 bias_source; - u8 vref_source; + u32 bias_source; + u32 vref_source; + u8 bias_cfg; int ret; - ret = device_property_read_u8(adcx140->dev, "ti,mic-bias-source", + ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source", &bias_source); if (ret) bias_source = ADCX140_MIC_BIAS_VAL_VREF; @@ -754,7 +755,7 @@ static int adcx140_codec_probe(struct snd_soc_component *component) return -EINVAL; } - ret = device_property_read_u8(adcx140->dev, "ti,vref-source", + ret = device_property_read_u32(adcx140->dev, "ti,vref-source", &vref_source); if (ret) vref_source = ADCX140_MIC_BIAS_VREF_275V; @@ -765,7 +766,7 @@ static int adcx140_codec_probe(struct snd_soc_component *component) return -EINVAL; } - bias_source |= vref_source; + bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source; ret = adcx140_reset(adcx140); if (ret) @@ -785,7 +786,7 @@ static int adcx140_codec_probe(struct snd_soc_component *component) ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG, ADCX140_MIC_BIAS_VAL_MSK | - ADCX140_MIC_BIAS_VREF_MSK, bias_source); + ADCX140_MIC_BIAS_VREF_MSK, bias_cfg); if (ret) dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret); out: diff --git a/sound/soc/codecs/tlv320adcx140.h b/sound/soc/codecs/tlv320adcx140.h index 6d055e55909e..69de52d473f4 100644 --- a/sound/soc/codecs/tlv320adcx140.h +++ b/sound/soc/codecs/tlv320adcx140.h @@ -116,6 +116,7 @@ #define ADCX140_MIC_BIAS_VAL_VREF_1096 1 #define ADCX140_MIC_BIAS_VAL_AVDD 6 #define ADCX140_MIC_BIAS_VAL_MSK GENMASK(6, 4) +#define ADCX140_MIC_BIAS_SHIFT 4 #define ADCX140_MIC_BIAS_VREF_275V 0 #define ADCX140_MIC_BIAS_VREF_25V 1 -- cgit