From 0fb1fd20043f619e444720062e61cdc40130c0c5 Mon Sep 17 00:00:00 2001 From: Dien Pham Date: Thu, 26 Jan 2017 09:52:27 +0100 Subject: arm64: dts: r8a7796: Add I2C for DVFS device node This patch adds I2C for DVFS device node for R8A7796 SoC. Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index f7120cdedd0d..c95ad177b097 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -25,6 +25,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + i2c7 = &i2c_dvfs; }; psci { @@ -269,6 +270,19 @@ #power-domain-cells = <1>; }; + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7796", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; -- cgit From d8e62f0729bb404caa6ba42b65d5a1e4d370a6e3 Mon Sep 17 00:00:00 2001 From: Dien Pham Date: Thu, 26 Jan 2017 09:52:28 +0100 Subject: arm64: dts: r8a7796: salvator-x: Add I2C for DVFS device support This patch adds support of I2C for DVFS device for Salvator-X board on R8A7796 SoC. Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index c7f40f8f3169..61f4662db497 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -261,3 +261,7 @@ timeout-sec = <60>; status = "okay"; }; + +&i2c_dvfs { + status = "okay"; +}; -- cgit From d7e0d64a46f97f67ecbc0194ce6a394f512109c5 Mon Sep 17 00:00:00 2001 From: Keita Kobayashi Date: Thu, 26 Jan 2017 09:52:29 +0100 Subject: arm64: dts: r8a7795: Add I2C for DVFS core to dtsi This patch adds I2C for DVFS device support for R8A7795 SoC. Signed-off-by: Keita Kobayashi Signed-off-by: Gaku Inami Signed-off-by: Dien Pham Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index eac4f29aa5cd..fe266bb3d913 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -25,6 +25,7 @@ i2c4 = &i2c4; i2c5 = &i2c5; i2c6 = &i2c6; + i2c7 = &i2c_dvfs; }; psci { @@ -793,6 +794,19 @@ status = "disabled"; }; + i2c_dvfs: i2c@e60b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7795", + "renesas,rcar-gen3-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { #address-cells = <1>; #size-cells = <0>; -- cgit From 006ced572a3b2247639ce06443aff00704888001 Mon Sep 17 00:00:00 2001 From: Keita Kobayashi Date: Thu, 26 Jan 2017 09:52:30 +0100 Subject: arm64: dts: r8a7795: salvator-x: Enable I2C for DVFS device This patch enables I2C for DVFS device for for Salvator-X board on R8A7795 SoC. Signed-off-by: Keita Kobayashi Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman Reviewed-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 7a8986edcdc0..dc1177c76aa5 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -485,6 +485,10 @@ clock-frequency = <22579200>; }; +&i2c_dvfs { + status = "okay"; +}; + &avb { pinctrl-0 = <&avb_pins>; pinctrl-names = "default"; -- cgit From a262d66224c4c34bc2bee16d4d37d460a738788c Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Thu, 26 Jan 2017 18:13:52 +0300 Subject: arm64: dts: h3ulcb: Update memory node to 4 GiB map This patch adds memory region: - After changes, the H3ULCB board has the following map: Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff Bank1: 1GiB RAM : 0x000500000000 -> 0x0053fffffff Bank2: 1GiB RAM : 0x000600000000 -> 0x0063fffffff Bank3: 1GiB RAM : 0x000700000000 -> 0x0073fffffff - Before changes, the old map looked like this: Bank0: 1GiB RAM : 0x000048000000 -> 0x0007fffffff Signed-off-by: Vladimir Barinov Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index c5f8f69a4f5f..9811534f296e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -33,6 +33,21 @@ reg = <0x0 0x48000000 0x0 0x38000000>; }; + memory@500000000 { + device_type = "memory"; + reg = <0x5 0x00000000 0x0 0x40000000>; + }; + + memory@600000000 { + device_type = "memory"; + reg = <0x6 0x00000000 0x0 0x40000000>; + }; + + memory@700000000 { + device_type = "memory"; + reg = <0x7 0x00000000 0x0 0x40000000>; + }; + leds { compatible = "gpio-leds"; -- cgit From dda3887907d743385f2599fa18c765bd295ae2da Mon Sep 17 00:00:00 2001 From: Kazuya Mizuguchi Date: Wed, 1 Feb 2017 09:42:00 +0100 Subject: arm64: dts: r8a7795: Use rgmii-txid phy-mode for EthernetAVB Since commit 61fccb2d6274 ("ravb: Add tx and rx clock internal delays mode of APSR") the EthernetAVB driver enables tx and rx clock internal delay modes (TDM and RDM) depending on the phy mode as follows: phy mode | ASPR delay mode -----------+---------------- rgmii-id | TDM and RDM rgmii-rxid | RDM rgmii-txid | TDM And prior to the above commit no internal delay mode settings were implemented for any phy mode. With this and the above change present tx internal delay mode is enabled which has been observed to address failures in the case of 1Gbps communication using the by salvator-x board with the KSZ9031RNX phy. This has been reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs. With the above patch present but this patch present tx and rx internal delay modes are enabled; and with the above patch and this present absent no internal delay modes are enabled. In both cases failures have been observed when using 1Gbps communication in the environments described above. Signed-off-by: Kazuya Mizuguchi Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index fe266bb3d913..382a8987bca9 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -564,7 +564,7 @@ "ch24"; clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii-txid"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit From 0e45da1c6ea6b18616d95c697ecd6234bc504ef6 Mon Sep 17 00:00:00 2001 From: Kazuya Mizuguchi Date: Wed, 1 Feb 2017 09:42:01 +0100 Subject: arm64: dts: r8a7795: salvator-x: Fix EthernetAVB PHY timing Set PHY rxc-skew-ps to 1500 and all other values to their default values. This is intended to to address failures in the case of 1Gbps communication using the by salvator-x board with the KSZ9031RNX phy. This has been reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs. Signed-off-by: Kazuya Mizuguchi Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index dc1177c76aa5..5158ba3f9ce3 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -497,18 +497,7 @@ status = "okay"; phy0: ethernet-phy@0 { - rxc-skew-ps = <900>; - rxdv-skew-ps = <0>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txc-skew-ps = <900>; - txen-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; + rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -- cgit From 5b9fd1962f605a31842371471e559407c293131f Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Wed, 1 Feb 2017 09:42:02 +0100 Subject: arm64: dts: h3ulcb: Fix EthernetAVB PHY timing Set PHY rxc-skew-ps to 1500 and all other values to their default values. This is intended to to address failures in the case of 1Gbps communication using the by h3ulcb board with the KSZ9031RNX phy. Signed-off-by: Vladimir Barinov Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 9811534f296e..69c623faf80c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -354,18 +354,7 @@ status = "okay"; phy0: ethernet-phy@0 { - rxc-skew-ps = <900>; - rxdv-skew-ps = <0>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txc-skew-ps = <900>; - txen-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; + rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -- cgit From 325f39010b431f6a1ece74d69f10dcca2329c08d Mon Sep 17 00:00:00 2001 From: Kazuya Mizuguchi Date: Wed, 1 Feb 2017 09:42:03 +0100 Subject: arm64: dts: r8a7796: Use rgmii-txid phy-mode for EthernetAVB Since commit 61fccb2d6274 ("ravb: Add tx and rx clock internal delays mode of APSR") the EthernetAVB driver enables tx and rx clock internal delay modes (TDM and RDM) depending on the phy mode as follows: phy mode | ASPR delay mode -----------+---------------- rgmii-id | TDM and RDM rgmii-rxid | RDM rgmii-txid | TDM And prior to the above commit no internal delay mode settings were implemented for any phy mode. With this and the above change present tx internal delay mode is enabled which has been observed to address failures in the case of 1Gbps communication using the by salvator-x board with the KSZ9031RNX phy. This has been reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs. With the above patch present but this patch present tx and rx internal delay modes are enabled; and with the above patch and this present absent no internal delay modes are enabled. In both cases failures have been observed when using 1Gbps communication in the environments described above. Signed-off-by: Kazuya Mizuguchi Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index c95ad177b097..1c1c1eae9cba 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -483,7 +483,7 @@ "ch24"; clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; - phy-mode = "rgmii-id"; + phy-mode = "rgmii-txid"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- cgit From ef3f08c83fd186ab4bbad6a6250c5a347fbf6551 Mon Sep 17 00:00:00 2001 From: Kazuya Mizuguchi Date: Wed, 1 Feb 2017 09:42:04 +0100 Subject: arm64: dts: r8a7796: salvator-x: Fix EthernetAVB PHY timing Set PHY rxc-skew-ps to 1500 and all other values to their default values. This is intended to to address failures in the case of 1Gbps communication using the by salvator-x board with the KSZ9031RNX phy. This has been reported to occur with both the r8a7795 (H3) and r8a7796 (M3-W) SoCs. Signed-off-by: Kazuya Mizuguchi Signed-off-by: Takeshi Kihara Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index 61f4662db497..93ed23ab71bb 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -172,18 +172,7 @@ status = "okay"; phy0: ethernet-phy@0 { - rxc-skew-ps = <900>; - rxdv-skew-ps = <0>; - rxd0-skew-ps = <0>; - rxd1-skew-ps = <0>; - rxd2-skew-ps = <0>; - rxd3-skew-ps = <0>; - txc-skew-ps = <900>; - txen-skew-ps = <0>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; + rxc-skew-ps = <1500>; reg = <0>; interrupt-parent = <&gpio2>; interrupts = <11 IRQ_TYPE_LEVEL_LOW>; -- cgit From 68cd161072605c276d4e6c8cd06fbe7b00a0f680 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 7 Dec 2016 17:44:47 +0100 Subject: arm64: dts: r8a7796 dtsi: Add all HSCIF nodes Add the device nodes for all HSCIF serial ports, incl. clocks, and power domain. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven [simon: express register size in hex; refer to power domain in changelog] Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 ++++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 1c1c1eae9cba..714fd96b29eb 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -489,6 +489,76 @@ status = "disabled"; }; + hscif0: serial@e6540000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6540000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 520>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif1: serial@e6550000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6550000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 519>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif2: serial@e6560000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe6560000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 518>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif3: serial@e66a0000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66a0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 517>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + hscif4: serial@e66b0000 { + compatible = "renesas,hscif-r8a7796", + "renesas,rcar-gen3-hscif", + "renesas,hscif"; + reg = <0 0xe66b0000 0 0x60>; + interrupts = ; + clocks = <&cpg CPG_MOD 516>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a7796", "renesas,rcar-gen3-scif", "renesas,scif"; -- cgit From 19d76f3ec8fc6ff38f1c5ca534d75a957c8661ea Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 7 Dec 2016 17:44:26 +0100 Subject: arm64: dts: r8a7796: Add all SCIF nodes Add the device nodes for all R-Car H3 SCIF serial ports, incl. clocks and power domain. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 65 ++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 714fd96b29eb..5fb93fc043c2 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -559,6 +559,32 @@ status = "disabled"; }; + scif0: serial@e6e60000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e60000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 207>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif1: serial@e6e68000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6e68000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 206>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + scif2: serial@e6e88000 { compatible = "renesas,scif-r8a7796", "renesas,rcar-gen3-scif", "renesas,scif"; @@ -572,6 +598,45 @@ status = "disabled"; }; + scif3: serial@e6c50000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c50000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 204>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif4: serial@e6c40000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6c40000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 203>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + + scif5: serial@e6f30000 { + compatible = "renesas,scif-r8a7796", + "renesas,rcar-gen3-scif", "renesas,scif"; + reg = <0 0xe6f30000 0 64>; + interrupts = ; + clocks = <&cpg CPG_MOD 202>, + <&cpg CPG_CORE R8A7796_CLK_S3D1>, + <&scif_clk>; + clock-names = "fck", "brg_int", "scif_clk"; + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; + status = "disabled"; + }; + msiof0: spi@e6e90000 { compatible = "renesas,msiof-r8a7796", "renesas,rcar-gen3-msiof"; -- cgit From dbcae5ea4bd27409291e3329c9106f37f0118590 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 7 Dec 2016 17:44:27 +0100 Subject: arm64: dts: r8a7796: Enable SCIF DMA Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 5fb93fc043c2..951e351ddae1 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -568,6 +568,9 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x51>, <&dmac1 0x50>, + <&dmac2 0x51>, <&dmac2 0x50>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; @@ -581,6 +584,9 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x53>, <&dmac1 0x52>, + <&dmac2 0x53>, <&dmac2 0x52>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; @@ -607,6 +613,8 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x57>, <&dmac0 0x56>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; @@ -620,6 +628,8 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x59>, <&dmac0 0x58>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; @@ -633,6 +643,9 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, + <&dmac2 0x5b>, <&dmac2 0x5a>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; -- cgit From d5566d251f5e839e36db8db8105d8f8f57e54768 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Fri, 3 Feb 2017 11:38:20 +0100 Subject: arm64: dts: r8a7796: salvator-x: add SCIF1 (DEBUG1) Enables the SCIF hooked up to the DEBUG1 connector. Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index 93ed23ab71bb..74b8c653c9fe 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -18,6 +18,7 @@ aliases { serial0 = &scif2; + serial1 = &scif1; ethernet0 = &avb; }; @@ -113,6 +114,11 @@ function = "avb"; }; + scif1_pins: scif1 { + groups = "scif1_data_a", "scif1_ctrl"; + function = "scif1"; + }; + scif2_pins: scif2 { groups = "scif2_data_a"; function = "scif2"; @@ -228,6 +234,14 @@ status = "okay"; }; +&scif1 { + pinctrl-0 = <&scif1_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; + status = "okay"; +}; + &scif2 { pinctrl-0 = <&scif2_pins>; pinctrl-names = "default"; -- cgit From 6d50bb8935042c4b7747b57df064ff41295e4769 Mon Sep 17 00:00:00 2001 From: Ulrich Hecht Date: Wed, 7 Dec 2016 17:44:48 +0100 Subject: arm64: dts: r8a7796: Enable HSCIF DMA Signed-off-by: Ulrich Hecht Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 951e351ddae1..aa404ed9142e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -499,6 +499,9 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x31>, <&dmac1 0x30>, + <&dmac2 0x31>, <&dmac2 0x30>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; @@ -513,6 +516,9 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x33>, <&dmac1 0x32>, + <&dmac2 0x33>, <&dmac2 0x32>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; @@ -527,6 +533,9 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac1 0x35>, <&dmac1 0x34>, + <&dmac2 0x35>, <&dmac2 0x34>; + dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; @@ -541,6 +550,8 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x37>, <&dmac0 0x36>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; @@ -555,6 +566,8 @@ <&cpg CPG_CORE R8A7796_CLK_S3D1>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; + dmas = <&dmac0 0x39>, <&dmac0 0x38>; + dma-names = "tx", "rx"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; status = "disabled"; }; -- cgit From 799a75abdef348500bab14e873e7711afa426aaf Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 24 Feb 2017 14:59:27 +0100 Subject: arm64: dts: r8a7795: Add Cortex-A53 CPU cores This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8 cores (4 x Cortex-A57 + 4 x Cortex-A53). Based on work by Takeshi Kihara and Dirk Behme. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 46 ++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 382a8987bca9..61830697e33c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -73,6 +73,42 @@ enable-method = "psci"; }; + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A7795_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA57: cache-controller@0 { compatible = "cache"; reg = <0>; @@ -166,7 +202,7 @@ <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; @@ -307,13 +343,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; }; cpg: clock-controller@e6150000 { -- cgit From 9190748fd608dc3aa80edacab9e6818f2d6f71b6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 24 Feb 2017 14:59:28 +0100 Subject: arm64: dts: r8a7795: Add Cortex-A53 PMU node Enable the performance monitor unit for the Cortex-A53 cores on the R8A7795 SoC. Extracted from a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 61830697e33c..3573872974e0 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -340,6 +340,18 @@ <&a57_3>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&a53_0>, + <&a53_1>, + <&a53_2>, + <&a53_3>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = Date: Fri, 24 Feb 2017 14:49:13 +0100 Subject: arm64: dts: r8a7795: Upgrade to PSCI v1.0 to support Suspend-to-RAM >From PSCI v1.0, Suspend-to-RAM is supported via SYSTEM_SUSPEND PSCI function call. Hence, upgrade PSCI version for R-Car H3 to support Suspend-to-RAM. The Suspend-to-RAM is highly dependent on ARM Trusted Firwmare support since necessary callback functions will be registered after a query to ARM Trusted Firmware about SYSTEM_SUSPEND support. Since PSCI v1.0 is backward compatible with PSCI v0.2, CPU Hotplug and CPUIdle should be able to work normally with this change. Signed-off-by: Khiem Nguyen Signed-off-by: Takeshi Kihara [geert: Keep "arm,psci-0.2"] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 3573872974e0..c1e00a3e7c45 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -29,7 +29,7 @@ }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; -- cgit From b3f26910c0daafded536cf5edceab2ab469252cb Mon Sep 17 00:00:00 2001 From: Khiem Nguyen Date: Fri, 24 Feb 2017 14:49:14 +0100 Subject: arm64: dts: r8a7796: Upgrade to PSCI v1.0 to support Suspend-to-RAM >From PSCI v1.0, Suspend-to-RAM is supported via SYSTEM_SUSPEND PSCI function call. Hence, upgrade PSCI version for R-Car M3-W to support Suspend-to-RAM. The Suspend-to-RAM is highly dependent on ARM Trusted Firwmare support since necessary callback functions will be registered after a query to ARM Trusted Firmware about SYSTEM_SUSPEND support. Since PSCI v1.0 is backward compatible with PSCI v0.2, CPU Hotplug and CPUIdle should be able to work normally with this change. Signed-off-by: Khiem Nguyen Signed-off-by: Takeshi Kihara [geert: Keep "arm,psci-0.2"] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index aa404ed9142e..dbf82bc6ba64 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -29,7 +29,7 @@ }; psci { - compatible = "arm,psci-0.2"; + compatible = "arm,psci-1.0", "arm,psci-0.2"; method = "smc"; }; -- cgit From d165856de103a6d317a9c9a5782eacd5dc90a9dc Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 3 Mar 2017 14:18:16 +0100 Subject: arm64: dts: r8a7795: Remove unit-addresses and regs from integrated caches The Cortex-A57/A53 cache controllers are integrated controllers, and thus the device nodes representing them should not have unit-addresses or reg properties. Fixes: 6f7bf82cc912441f ("arm64: dts: r8a7795: Fix W=1 dtc warnings") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index c1e00a3e7c45..14772bc02125 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -109,17 +109,15 @@ enable-method = "psci"; }; - L2_CA57: cache-controller@0 { + L2_CA57: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc R8A7795_PD_CA57_SCU>; cache-unified; cache-level = <2>; }; - L2_CA53: cache-controller@100 { + L2_CA53: cache-controller-1 { compatible = "cache"; - reg = <0x100>; power-domains = <&sysc R8A7795_PD_CA53_SCU>; cache-unified; cache-level = <2>; -- cgit From 57a4fd420c6e8a04b6a87ff24d34250cd7c48f15 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 3 Mar 2017 14:18:17 +0100 Subject: arm64: dts: r8a7796: Remove unit-address and reg from integrated cache The Cortex-A57 cache controller is an integrated controller, and thus the device node representing it should not have a unit-addresses or reg property. Fixes: 1561f20760ec96db ("arm64: dts: r8a7796: Add Renesas R8A7796 SoC support") Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index dbf82bc6ba64..27f7dd9bd988 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -47,9 +47,8 @@ enable-method = "psci"; }; - L2_CA57: cache-controller@0 { + L2_CA57: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc R8A7796_PD_CA57_SCU>; cache-unified; cache-level = <2>; -- cgit From 7d73a4da2681dc5d04e8ed9f4aa96c1deed2dbc5 Mon Sep 17 00:00:00 2001 From: Niklas Söderlund Date: Mon, 5 Dec 2016 18:43:10 +0100 Subject: arm64: dts: r8a7795: salvator-x: Set drive-strength for ravb pins MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The EthernetAVB should not depend on the bootloader to setup correct drive-strength values. Values for drive-strength where found by examining the registers after the bootloader has configured the registers and successfully used the EthernetAVB. Signed-off-by: Niklas Söderlund Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 5158ba3f9ce3..277ab8484e0c 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -247,8 +247,22 @@ }; avb_pins: avb { - groups = "avb_mdc"; - function = "avb"; + mux { + groups = "avb_link", "avb_phy_int", "avb_mdc", + "avb_mii"; + function = "avb"; + }; + + pins_mdc { + groups = "avb_mdc"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", "PIN_AVB_TD0", + "PIN_AVB_TD1", "PIN_AVB_TD2", "PIN_AVB_TD3"; + drive-strength = <12>; + }; }; du_pins: du { -- cgit From b5a8ffad0eb0c1e5e601253edac163b2da9e855d Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Tue, 7 Mar 2017 05:30:06 +0000 Subject: arm64: dts: r8a7795: Tidyup Audio-DMAC channel for DVC Current Audio-DMAC is assigned "rx" as Audio-DMAC0, "tx" as Audio-DMAC1. Thus, DVC "tx" should be assigned as Audio-DMAC1, instead of Audio-DMAC0. Because of this, current platform board (using SRC/DVC/SSI) Playback/Capture both will use same Audio-DMAC0 (but it depends on audio data path). First note is that this "rx" and "tx" are from each IP point, it doesn't mean Playback/Capture. Second note is that Audio DMAC assigned on DT is only for Audio-DMAC, Audio-DMAC-peri-peri has no entry. => Audio-DMAC -> Audio-DMAC-peri-peri -- HW connection Playback case [Mem] => [SRC]--[DVC] -> [SSI]--[Codec] rx ~~~~~~~~~~~~ Capture [Mem] <= [DVC]--[SRC] <- [SSI]--[Codec] tx ~~~~~~~~~~~~ Signed-off-by: Kuninori Morimoto Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795.dtsi b/arch/arm64/boot/dts/renesas/r8a7795.dtsi index 14772bc02125..55c09f1b89c9 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7795.dtsi @@ -1075,11 +1075,11 @@ rcar_sound,dvc { dvc0: dvc-0 { - dmas = <&audma0 0xbc>; + dmas = <&audma1 0xbc>; dma-names = "tx"; }; dvc1: dvc-1 { - dmas = <&audma0 0xbe>; + dmas = <&audma1 0xbe>; dma-names = "tx"; }; }; -- cgit From 7328be4a03b10c19e49a564f4c2e3a9ebcf34ca7 Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Tue, 7 Mar 2017 19:03:22 +0100 Subject: arm64: dts: r8a7796: Add Cortex-A57 CPU cores This patch adds Cortex-A57 CPU cores to R8A7796 SoC for a total of 2 x Cortex-A57. Signed-off-by: Takeshi Kihara [geert: Rebased] Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 27f7dd9bd988..d2a2110fc7fc 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -37,7 +37,6 @@ #address-cells = <1>; #size-cells = <0>; - /* 1 core only at this point */ a57_0: cpu@0 { compatible = "arm,cortex-a57", "arm,armv8"; reg = <0x0>; @@ -47,6 +46,15 @@ enable-method = "psci"; }; + a57_1: cpu@1 { + compatible = "arm,cortex-a57","arm,armv8"; + reg = <0x1>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA57_CPU1>; + next-level-cache = <&L2_CA57>; + enable-method = "psci"; + }; + L2_CA57: cache-controller-0 { compatible = "cache"; power-domains = <&sysc R8A7796_PD_CA57_SCU>; @@ -100,7 +108,7 @@ <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -109,13 +117,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; }; wdt0: watchdog@e6020000 { -- cgit From 9fccf4d6103eeb5db88c1ae026d61b87f722414a Mon Sep 17 00:00:00 2001 From: Takeshi Kihara Date: Tue, 7 Mar 2017 19:03:23 +0100 Subject: arm64: dts: r8a7796: Add Cortex-A57 PMU node Enable the performance monitor unit for the Cortex-A57 cores on the R8A7796 SoC. Signed-off-by: Takeshi Kihara Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index d2a2110fc7fc..454e1292f910 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -252,6 +252,14 @@ reg = <0 0xe6060000 0 0x50c>; }; + pmu_a57 { + compatible = "arm,cortex-a57-pmu"; + interrupts = , + ; + interrupt-affinity = <&a57_0>, + <&a57_1>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7796-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit From a681e6d63285b879bb9bab0bd79e2021e6dcbda1 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 7 Mar 2017 19:03:24 +0100 Subject: arm64: dts: r8a7796: Add CA53 L2 cache-controller node Add a device node for the Cortex-A53 L2 cache-controller. The L2 cache for the Cortex-A53 CPU cores is 512 KiB large (organized as 32 KiB x 16 ways). Extracted from a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index 454e1292f910..b951f5ffe9e0 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -61,6 +61,13 @@ cache-unified; cache-level = <2>; }; + + L2_CA53: cache-controller-1 { + compatible = "cache"; + power-domains = <&sysc R8A7796_PD_CA53_SCU>; + cache-unified; + cache-level = <2>; + }; }; extal_clk: extal { -- cgit From b4dc3b4b1a65fec829ee8704c7647c06a8038108 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 7 Mar 2017 19:03:25 +0100 Subject: arm64: dts: r8a7796: Add Cortex-A53 CPU cores This patch adds Cortex-A53 CPU cores of R8A7796 SoC, and sets a total of 6 cores (2 x Cortex-A57 + 4 x Cortex-A53). Based on a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 46 ++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index b951f5ffe9e0..b32a180009dd 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -55,6 +55,42 @@ enable-method = "psci"; }; + a53_0: cpu@100 { + compatible = "arm,cortex-a53", "arm,armv8"; + reg = <0x100>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU0>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_1: cpu@101 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x101>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU1>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_2: cpu@102 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x102>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU2>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + + a53_3: cpu@103 { + compatible = "arm,cortex-a53","arm,armv8"; + reg = <0x103>; + device_type = "cpu"; + power-domains = <&sysc R8A7796_PD_CA53_CPU3>; + next-level-cache = <&L2_CA53>; + enable-method = "psci"; + }; + L2_CA57: cache-controller-0 { compatible = "cache"; power-domains = <&sysc R8A7796_PD_CA57_SCU>; @@ -115,7 +151,7 @@ <0x0 0xf1040000 0 0x20000>, <0x0 0xf1060000 0 0x20000>; interrupts = ; + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; @@ -124,13 +160,13 @@ timer { compatible = "arm,armv8-timer"; interrupts = , + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, , + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, ; + (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; }; wdt0: watchdog@e6020000 { -- cgit From ccc499330dbcaa8f6065bd1b10a64ca09fa96c3e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Tue, 7 Mar 2017 19:03:26 +0100 Subject: arm64: dts: r8a7796: Add Cortex-A53 PMU node Enable the performance monitor unit for the Cortex-A53 cores on the R8A7796 SoC. Extracted from a patch by Takeshi Kihara in the BSP. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a7796.dtsi b/arch/arm64/boot/dts/renesas/r8a7796.dtsi index b32a180009dd..a90abf14dc4e 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi @@ -303,6 +303,18 @@ <&a57_1>; }; + pmu_a53 { + compatible = "arm,cortex-a53-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&a53_0>, + <&a53_1>, + <&a53_2>, + <&a53_3>; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a7796-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; -- cgit From c9060f50d82fc9b548571a9adea9ebff22b3347b Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Mar 2017 14:19:13 +0100 Subject: arm64: dts: h3ulcb: Drop superfluous status update for frequency override The scif_clk device node is already enabled in r8a7795.dtsi, so there is no need to update its status again. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts index 69c623faf80c..ab352159de65 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-h3ulcb.dts @@ -228,7 +228,6 @@ &scif_clk { clock-frequency = <14745600>; - status = "okay"; }; &i2c2 { -- cgit From 971939d1da07c7b55d35aca31288cce297731c71 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Mar 2017 14:19:14 +0100 Subject: arm64: dts: r8a7795: salvator-x: Drop superfluous status updates for frequency overrides The scif_clk and pcie_bus_clk device nodes are already enabled in r8a7795.dtsi, so there is no need to update their statuses again. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts index 277ab8484e0c..f25241921067 100644 --- a/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dts @@ -362,7 +362,6 @@ &scif_clk { clock-frequency = <14745600>; - status = "okay"; }; &i2c2 { @@ -574,7 +573,6 @@ &pcie_bus_clk { clock-frequency = <100000000>; - status = "okay"; }; &pciec0 { -- cgit From cb4de4ece41a55ba125e6e8d1fa727457132dc41 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Mar 2017 14:19:15 +0100 Subject: arm64: dts: m3ulcb: Drop superfluous status update for frequency override The scif_clk device node is already enabled in r8a7796.dtsi, so there is no need to update its status again. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts index c3f064ac2cb4..372b2a944716 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts @@ -180,7 +180,6 @@ &scif_clk { clock-frequency = <14745600>; - status = "okay"; }; &wdt0 { -- cgit From 3cbe33367d4fd480a92fbc131a96fa925be9e95d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 10 Mar 2017 14:19:16 +0100 Subject: arm64: dts: r8a7796: salvator-x: Drop superfluous status update for frequency override The scif_clk device node is already enabled in r8a7796.dtsi, so there is no need to update its status again. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts index 74b8c653c9fe..c9f59b6ce33f 100644 --- a/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts +++ b/arch/arm64/boot/dts/renesas/r8a7796-salvator-x.dts @@ -250,7 +250,6 @@ &scif_clk { clock-frequency = <14745600>; - status = "okay"; }; &i2c2 { -- cgit