From 8e056b50d92ae7f4d6895d1c97a69a2a953cf97b Mon Sep 17 00:00:00 2001 From: Chaitanya Kumar Borah Date: Tue, 30 Apr 2024 14:48:25 +0530 Subject: drm/i915/audio: Fix audio time stamp programming for DP Intel hardware is capable of programming the Maud/Naud SDPs on its own based on real-time clocks. While doing so, it takes care of any deviations from the theoretical values. Programming the registers explicitly with static values can interfere with this logic. Therefore, let the HW decide the Maud and Naud SDPs on it's own. Cc: stable@vger.kernel.org # v5.17 Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8097 Co-developed-by: Kai Vehmanen Signed-off-by: Kai Vehmanen Signed-off-by: Chaitanya Kumar Borah Reviewed-by: Uma Shankar Signed-off-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240430091825.733499-1-chaitanya.kumar.borah@intel.com --- drivers/gpu/drm/i915/display/intel_audio.c | 113 ++--------------------------- 1 file changed, 8 insertions(+), 105 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 07e0c73204f3..ed81e1466c4b 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -76,19 +76,6 @@ struct intel_audio_funcs { struct intel_crtc_state *crtc_state); }; -/* DP N/M table */ -#define LC_810M 810000 -#define LC_540M 540000 -#define LC_270M 270000 -#define LC_162M 162000 - -struct dp_aud_n_m { - int sample_rate; - int clock; - u16 m; - u16 n; -}; - struct hdmi_aud_ncts { int sample_rate; int clock; @@ -96,60 +83,6 @@ struct hdmi_aud_ncts { int cts; }; -/* Values according to DP 1.4 Table 2-104 */ -static const struct dp_aud_n_m dp_aud_n_m[] = { - { 32000, LC_162M, 1024, 10125 }, - { 44100, LC_162M, 784, 5625 }, - { 48000, LC_162M, 512, 3375 }, - { 64000, LC_162M, 2048, 10125 }, - { 88200, LC_162M, 1568, 5625 }, - { 96000, LC_162M, 1024, 3375 }, - { 128000, LC_162M, 4096, 10125 }, - { 176400, LC_162M, 3136, 5625 }, - { 192000, LC_162M, 2048, 3375 }, - { 32000, LC_270M, 1024, 16875 }, - { 44100, LC_270M, 784, 9375 }, - { 48000, LC_270M, 512, 5625 }, - { 64000, LC_270M, 2048, 16875 }, - { 88200, LC_270M, 1568, 9375 }, - { 96000, LC_270M, 1024, 5625 }, - { 128000, LC_270M, 4096, 16875 }, - { 176400, LC_270M, 3136, 9375 }, - { 192000, LC_270M, 2048, 5625 }, - { 32000, LC_540M, 1024, 33750 }, - { 44100, LC_540M, 784, 18750 }, - { 48000, LC_540M, 512, 11250 }, - { 64000, LC_540M, 2048, 33750 }, - { 88200, LC_540M, 1568, 18750 }, - { 96000, LC_540M, 1024, 11250 }, - { 128000, LC_540M, 4096, 33750 }, - { 176400, LC_540M, 3136, 18750 }, - { 192000, LC_540M, 2048, 11250 }, - { 32000, LC_810M, 1024, 50625 }, - { 44100, LC_810M, 784, 28125 }, - { 48000, LC_810M, 512, 16875 }, - { 64000, LC_810M, 2048, 50625 }, - { 88200, LC_810M, 1568, 28125 }, - { 96000, LC_810M, 1024, 16875 }, - { 128000, LC_810M, 4096, 50625 }, - { 176400, LC_810M, 3136, 28125 }, - { 192000, LC_810M, 2048, 16875 }, -}; - -static const struct dp_aud_n_m * -audio_config_dp_get_n_m(const struct intel_crtc_state *crtc_state, int rate) -{ - int i; - - for (i = 0; i < ARRAY_SIZE(dp_aud_n_m); i++) { - if (rate == dp_aud_n_m[i].sample_rate && - crtc_state->port_clock == dp_aud_n_m[i].clock) - return &dp_aud_n_m[i]; - } - - return NULL; -} - static const struct { int clock; u32 config; @@ -387,47 +320,17 @@ hsw_dp_audio_config_update(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); - struct i915_audio_component *acomp = i915->display.audio.component; enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - enum port port = encoder->port; - const struct dp_aud_n_m *nm; - int rate; - u32 tmp; - - rate = acomp ? acomp->aud_sample_rate[port] : 0; - nm = audio_config_dp_get_n_m(crtc_state, rate); - if (nm) - drm_dbg_kms(&i915->drm, "using Maud %u, Naud %u\n", nm->m, - nm->n); - else - drm_dbg_kms(&i915->drm, "using automatic Maud, Naud\n"); - - tmp = intel_de_read(i915, HSW_AUD_CFG(cpu_transcoder)); - tmp &= ~AUD_CONFIG_N_VALUE_INDEX; - tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK; - tmp &= ~AUD_CONFIG_N_PROG_ENABLE; - tmp |= AUD_CONFIG_N_VALUE_INDEX; - if (nm) { - tmp &= ~AUD_CONFIG_N_MASK; - tmp |= AUD_CONFIG_N(nm->n); - tmp |= AUD_CONFIG_N_PROG_ENABLE; - } - - intel_de_write(i915, HSW_AUD_CFG(cpu_transcoder), tmp); - - tmp = intel_de_read(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder)); - tmp &= ~AUD_CONFIG_M_MASK; - tmp &= ~AUD_M_CTS_M_VALUE_INDEX; - tmp &= ~AUD_M_CTS_M_PROG_ENABLE; - - if (nm) { - tmp |= nm->m; - tmp |= AUD_M_CTS_M_VALUE_INDEX; - tmp |= AUD_M_CTS_M_PROG_ENABLE; - } + /* Enable time stamps. Let HW calculate Maud/Naud values */ + intel_de_rmw(i915, HSW_AUD_CFG(cpu_transcoder), + AUD_CONFIG_N_VALUE_INDEX | + AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK | + AUD_CONFIG_UPPER_N_MASK | + AUD_CONFIG_LOWER_N_MASK | + AUD_CONFIG_N_PROG_ENABLE, + AUD_CONFIG_N_VALUE_INDEX); - intel_de_write(i915, HSW_AUD_M_CTS_ENABLE(cpu_transcoder), tmp); } static void -- cgit From c8bafa0d9898f37cb3618f5883656cc382831533 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 30 Apr 2024 12:56:35 +0300 Subject: drm/i915: Align PLANE_SURF to 16k on ADL for async flips MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On ADL async flips apparently generate DMAR and GGTT faults (with accompanying visual glitches) unless PLANE_SURF is aligned to at least 16k. Bump up the alignment to 16k. TODO: analyze things better to figure out what is really going on here Reviewed-by: Arun R Murthy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240430095639.26390-2-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_dpt.c | 7 ++++--- drivers/gpu/drm/i915/display/intel_dpt.h | 3 ++- drivers/gpu/drm/i915/display/intel_fb.c | 17 ++++++++++++++++- drivers/gpu/drm/i915/display/intel_fb_pin.c | 10 +++++----- 4 files changed, 27 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c index b29bceff73f2..786d3f2e94c7 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.c +++ b/drivers/gpu/drm/i915/display/intel_dpt.c @@ -121,7 +121,8 @@ static void dpt_cleanup(struct i915_address_space *vm) i915_gem_object_put(dpt->obj); } -struct i915_vma *intel_dpt_pin(struct i915_address_space *vm) +struct i915_vma *intel_dpt_pin(struct i915_address_space *vm, + unsigned int alignment) { struct drm_i915_private *i915 = vm->i915; struct i915_dpt *dpt = i915_vm_to_dpt(vm); @@ -143,8 +144,8 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space *vm) if (err) continue; - vma = i915_gem_object_ggtt_pin_ww(dpt->obj, &ww, NULL, 0, 4096, - pin_flags); + vma = i915_gem_object_ggtt_pin_ww(dpt->obj, &ww, NULL, 0, + alignment, pin_flags); if (IS_ERR(vma)) { err = PTR_ERR(vma); continue; diff --git a/drivers/gpu/drm/i915/display/intel_dpt.h b/drivers/gpu/drm/i915/display/intel_dpt.h index e18a9f767b11..f467578a4950 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.h +++ b/drivers/gpu/drm/i915/display/intel_dpt.h @@ -13,7 +13,8 @@ struct i915_vma; struct intel_framebuffer; void intel_dpt_destroy(struct i915_address_space *vm); -struct i915_vma *intel_dpt_pin(struct i915_address_space *vm); +struct i915_vma *intel_dpt_pin(struct i915_address_space *vm, + unsigned int alignment); void intel_dpt_unpin(struct i915_address_space *vm); void intel_dpt_suspend(struct drm_i915_private *i915); void intel_dpt_resume(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index 86b443433e8b..bf24f48a1e76 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -805,8 +805,23 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, { struct drm_i915_private *dev_priv = to_i915(fb->dev); - if (intel_fb_uses_dpt(fb)) + if (intel_fb_uses_dpt(fb)) { + /* AUX_DIST needs only 4K alignment */ + if (intel_fb_is_ccs_aux_plane(fb, color_plane)) + return 512 * 4096; + + /* + * FIXME ADL sees GGTT/DMAR faults with async + * flips unless we align to 16k at least. + * Figure out what's going on here... + */ + if (IS_ALDERLAKE_P(dev_priv) && + !intel_fb_is_ccs_modifier(fb->modifier) && + HAS_ASYNC_FLIPS(dev_priv)) + return 512 * 16 * 1024; + return 512 * 4096; + } /* AUX_DIST needs only 4K alignment */ if (intel_fb_is_ccs_aux_plane(fb, color_plane)) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index b6df9baf481b..be095cc696ba 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -19,6 +19,7 @@ static struct i915_vma * intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, const struct i915_gtt_view *view, + unsigned int alignment, bool uses_fence, unsigned long *out_flags, struct i915_address_space *vm) @@ -28,7 +29,6 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct i915_gem_ww_ctx ww; struct i915_vma *vma; - u32 alignment; int ret; /* @@ -41,8 +41,6 @@ intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, if (WARN_ON(!i915_gem_object_is_framebuffer(obj))) return ERR_PTR(-EINVAL); - alignment = 4096 * 512; - atomic_inc(&dev_priv->gpu_error.pending_fb_pin); for_i915_gem_ww(&ww, ret, true) { @@ -267,14 +265,16 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) i915_gem_object_get_dma_address(intel_fb_obj(fb), 0); } else { struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); + unsigned int alignment = intel_surf_alignment(fb, 0); - vma = intel_dpt_pin(intel_fb->dpt_vm); + vma = intel_dpt_pin(intel_fb->dpt_vm, alignment / 512); if (IS_ERR(vma)) return PTR_ERR(vma); plane_state->ggtt_vma = vma; - vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, false, + vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, + alignment, false, &plane_state->flags, intel_fb->dpt_vm); if (IS_ERR(vma)) { intel_dpt_unpin(intel_fb->dpt_vm); -- cgit From 4df0f2ed25735e7da5a9015befda5199fe6fec73 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 30 Apr 2024 12:56:36 +0300 Subject: drm/i915: Reject async flips if we need to change DDB/watermarks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DDB/watermarks are always double buffered on the vblank, so we can't safely change them during async flips. Currently this never happens, but we'll be making changing between sync and async flips a bit more flexible, in which case we can actually end up here. Reviewed-by: Vandita Kulkarni Reviewed-by: Arun R Murthy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240430095639.26390-3-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/skl_watermark.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 7c6187b4479f..e6476aa621a7 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2540,6 +2540,12 @@ skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state, &new_crtc_state->wm.skl.plane_ddb_y[plane_id])) continue; + if (new_crtc_state->do_async_flip) { + drm_dbg_kms(&i915->drm, "[PLANE:%d:%s] Can't change DDB during async flip\n", + plane->base.base.id, plane->base.name); + return -EINVAL; + } + plane_state = intel_atomic_get_plane_state(state, plane); if (IS_ERR(plane_state)) return PTR_ERR(plane_state); @@ -2899,6 +2905,12 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state, &new_crtc_state->wm.skl.optimal)) continue; + if (new_crtc_state->do_async_flip) { + drm_dbg_kms(&i915->drm, "[PLANE:%d:%s] Can't change watermarks during async flip\n", + plane->base.base.id, plane->base.name); + return -EINVAL; + } + plane_state = intel_atomic_get_plane_state(state, plane); if (IS_ERR(plane_state)) return PTR_ERR(plane_state); -- cgit From 7c800d957173298a5c80576db7384ebfe6efc10c Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 30 Apr 2024 12:56:37 +0300 Subject: drm/i915: Allow the initial async flip to change modifier MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With Xorg+modesetting on skl+ we see the following behaviour: 1. root pixmap is X-tiled 2. client submitted buffers can be Y-tiled (w/ 'Option "dmabuf_capable"') 3. we try to switch from the X-tiled buffer to the Y-tiled buffer using an async flip (when vsync is disabled). 4. the async flip will be rejected by i915 due to the modifier change Relax the rules a bit by turning the first async flip into a sync flip so that we can change the modifier if necessary. Note that we already convert the first async flip into a sync flip on adl+ in order to reprogram the watermarks. Reviewed-by: Vandita Kulkarni Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240430095639.26390-4-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 16 +++++++++++++--- drivers/gpu/drm/i915/display/intel_display.c | 7 +++++++ 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 76d77d5a0409..769010d0ebc4 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -429,10 +429,20 @@ static bool intel_plane_do_async_flip(struct intel_plane *plane, * In platforms after DISPLAY13, we might need to override * first async flip in order to change watermark levels * as part of optimization. - * So for those, we are checking if this is a first async flip. - * For platforms earlier than DISPLAY13 we always do async flip. + * + * And let's do this for all skl+ so that we can eg. change the + * modifier as well. + * + * TODO: For older platforms there is less reason to do this as + * only X-tile is supported with async flips, though we could + * extend this so other scanout parameters (stride/etc) could + * be changed as well... + * + * FIXME: Platforms with need_async_flip_disable_wa==true will + * now end up doing two sync flips initially. Would be nice to + * combine those into just the one sync flip... */ - return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip; + return DISPLAY_VER(i915) < 9 || old_crtc_state->uapi.async_flip; } static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 273323f30ae2..a98dcbdaf7fd 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -6166,6 +6166,13 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in return -EINVAL; } + /* + * We turn the first async flip request into a sync flip + * so that we can reconfigure the plane (eg. change modifier). + */ + if (!new_crtc_state->do_async_flip) + continue; + if (old_plane_state->view.color_plane[0].mapping_stride != new_plane_state->view.color_plane[0].mapping_stride) { drm_dbg_kms(&i915->drm, -- cgit From b24d361420c46c3b1a0594f63f88b52e1afc6792 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 30 Apr 2024 12:56:38 +0300 Subject: drm/i915: Eliminate extra frame from skl-glk sync->async flip change MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On bdw-glk the sync->async flip change takes an extra frame due to the double buffering behaviour of the async flip plane control bit. Since on skl+ we are now explicitly converting the first async flip to a sync flip (in order to allow changing the modifier and/or ddb/watermarks) we are now taking two extra frames until async flips are actually active. We can drop that back down to one frame by setting the async flip bit already during the sync flip. Note that on bdw we don't currently do the extra sync flip (see intel_plane_do_async_flip()) so technically we wouldn't have to deal with this in i9xx_plane_update_arm(). But I added the relevant snippet of code there as well, just in case we ever decide to go for the extra sync flip on pre-skl platforms as well (we might, for example, want to change the fb stride). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240430095639.26390-5-ville.syrjala@linux.intel.com Reviewed-by: Arun R Murthy --- drivers/gpu/drm/i915/display/i9xx_plane.c | 5 +++++ drivers/gpu/drm/i915/display/intel_atomic_plane.c | 15 +++++++++++---- drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 +++++ 3 files changed, 21 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 0279c8aabdd1..76fc7626051b 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -455,6 +455,11 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); + /* see intel_plane_atomic_calc_changes() */ + if (plane->need_async_flip_disable_wa && + crtc_state->async_flip_planes & BIT(plane->id)) + dspcntr |= DISP_ASYNC_FLIP; + linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); if (DISPLAY_VER(dev_priv) >= 4) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 769010d0ebc4..7098a34a17c8 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -437,10 +437,6 @@ static bool intel_plane_do_async_flip(struct intel_plane *plane, * only X-tile is supported with async flips, though we could * extend this so other scanout parameters (stride/etc) could * be changed as well... - * - * FIXME: Platforms with need_async_flip_disable_wa==true will - * now end up doing two sync flips initially. Would be nice to - * combine those into just the one sync flip... */ return DISPLAY_VER(i915) < 9 || old_crtc_state->uapi.async_flip; } @@ -604,6 +600,17 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) { new_crtc_state->do_async_flip = true; new_crtc_state->async_flip_planes |= BIT(plane->id); + } else if (plane->need_async_flip_disable_wa && + new_crtc_state->uapi.async_flip) { + /* + * On platforms with double buffered async flip bit we + * set the bit already one frame early during the sync + * flip (see {i9xx,skl}_plane_update_arm()). The + * hardware will therefore be ready to perform a real + * async flip during the next commit, without having + * to wait yet another frame for the bit to latch. + */ + new_crtc_state->async_flip_planes |= BIT(plane->id); } return 0; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 860574d04f88..ad4c90344f68 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1174,6 +1174,11 @@ skl_plane_update_arm(struct intel_plane *plane, plane_ctl = plane_state->ctl | skl_plane_ctl_crtc(crtc_state); + /* see intel_plane_atomic_calc_changes() */ + if (plane->need_async_flip_disable_wa && + crtc_state->async_flip_planes & BIT(plane->id)) + plane_ctl |= PLANE_CTL_ASYNC_FLIP; + if (DISPLAY_VER(dev_priv) >= 10) plane_color_ctl = plane_state->color_ctl | glk_plane_color_ctl_crtc(crtc_state); -- cgit From 2081c6aec0a4f34e1414a6172b88ef3aaebb6120 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 30 Apr 2024 12:56:39 +0300 Subject: drm/i915: s/need_async_flip_disable_wa/need_async_flip_toggle_wa/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename need_async_flip_disable_wa to need_async_flip_toggle_wa to better reflect the fact that we need to deal with the bad PLANE_CTL_ASYNC_FLIP double buffering behaviour going both ways. Reviewed-by: Arun R Murthy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240430095639.26390-6-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++-- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/skl_universal_plane.c | 5 ++--- 5 files changed, 7 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 76fc7626051b..3442264443e5 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -456,7 +456,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, dspcntr = plane_state->ctl | i9xx_plane_ctl_crtc(crtc_state); /* see intel_plane_atomic_calc_changes() */ - if (plane->need_async_flip_disable_wa && + if (plane->need_async_flip_toggle_wa && crtc_state->async_flip_planes & BIT(plane->id)) dspcntr |= DISP_ASYNC_FLIP; @@ -878,7 +878,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) plane->enable_flip_done = vlv_primary_enable_flip_done; plane->disable_flip_done = vlv_primary_disable_flip_done; } else if (IS_BROADWELL(dev_priv)) { - plane->need_async_flip_disable_wa = true; + plane->need_async_flip_toggle_wa = true; plane->async_flip = g4x_primary_async_flip; plane->enable_flip_done = bdw_primary_enable_flip_done; plane->disable_flip_done = bdw_primary_disable_flip_done; diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 7098a34a17c8..b083b985d170 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -600,7 +600,7 @@ static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_cr if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) { new_crtc_state->do_async_flip = true; new_crtc_state->async_flip_planes |= BIT(plane->id); - } else if (plane->need_async_flip_disable_wa && + } else if (plane->need_async_flip_toggle_wa && new_crtc_state->uapi.async_flip) { /* * On platforms with double buffered async flip bit we diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a98dcbdaf7fd..ee862f5d0ff4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1140,7 +1140,7 @@ static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state, int i; for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) { - if (plane->need_async_flip_disable_wa && + if (plane->need_async_flip_toggle_wa && plane->pipe == crtc->pipe && disable_async_flip_planes & BIT(plane->id)) { /* diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 62f7a30c37dc..00eba3fbcdc6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1521,7 +1521,7 @@ struct intel_plane { enum i9xx_plane_id i9xx_plane; enum plane_id id; enum pipe pipe; - bool need_async_flip_disable_wa; + bool need_async_flip_toggle_wa; u32 frontbuffer_bit; struct { diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index ad4c90344f68..0a8e781a3648 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1175,7 +1175,7 @@ skl_plane_update_arm(struct intel_plane *plane, skl_plane_ctl_crtc(crtc_state); /* see intel_plane_atomic_calc_changes() */ - if (plane->need_async_flip_disable_wa && + if (plane->need_async_flip_toggle_wa && crtc_state->async_flip_planes & BIT(plane->id)) plane_ctl |= PLANE_CTL_ASYNC_FLIP; @@ -2371,8 +2371,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->check_plane = skl_plane_check; if (plane_id == PLANE_PRIMARY) { - plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv, - 9, 10); + plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10); plane->async_flip = skl_plane_async_flip; plane->enable_flip_done = skl_plane_enable_flip_done; plane->disable_flip_done = skl_plane_disable_flip_done; -- cgit From 4b31961a1c6388ec67c05ce4033088d9bdf00f95 Mon Sep 17 00:00:00 2001 From: Mika Kahola Date: Thu, 2 May 2024 16:17:16 +0300 Subject: drm/i915/display: Calculate crtc clock rate based on PLL parameters With HDMI monitors we bumped up a case where the crtc clock rate caused a mismatch on state verification. This was due to assumption that the SW clock rate from PLL structure would match the calculated counterpart from HW. This is not necessarily always the case and therefore we would actually need to recalculate the clock rate from SW PLL parameters. Then these SW and HW crtc clock rates can be compared with each other. The patch recalculates the crtc clock rate for SW state based on SW PLL parameters and compares the crtc clock rate calculated from the parameters found from the HW. Signed-off-by: Mika Kahola Reviewed-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240502131716.504616-1-mika.kahola@intel.com --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 8e3b13884bb8..89a195917179 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -3078,9 +3078,10 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state, const struct intel_c20pll_state *mpll_sw_state = &state->dpll_hw_state.cx0pll.c20; bool sw_use_mpllb = intel_c20phy_use_mpllb(mpll_sw_state); bool hw_use_mpllb = intel_c20phy_use_mpllb(mpll_hw_state); + int clock = intel_c20pll_calc_port_clock(encoder, mpll_sw_state); int i; - I915_STATE_WARN(i915, mpll_hw_state->clock != mpll_sw_state->clock, + I915_STATE_WARN(i915, mpll_hw_state->clock != clock, "[CRTC:%d:%s] mismatch in C20: Register CLOCK (expected %d, found %d)", crtc->base.base.id, crtc->base.name, mpll_sw_state->clock, mpll_hw_state->clock); -- cgit From 7f071dde0bc97d40d8e80a374e155b6c0cd72174 Mon Sep 17 00:00:00 2001 From: Clint Taylor Date: Tue, 30 Apr 2024 10:28:32 -0700 Subject: drm/i915/bmg: Lane reversal requires writes to both context lanes Write both CX0 Lanes for Context Toggle for all except TC pin assignment D. v2: Update title(RK) Bspec: 64539 CC: Jani Nikula Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-2-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 89a195917179..0444a1ffb030 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2337,7 +2337,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, { const struct intel_c20pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll.c20; bool dp = false; - int lane = crtc_state->lane_count > 2 ? INTEL_CX0_BOTH_LANES : INTEL_CX0_LANE0; + u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); u32 clock = crtc_state->port_clock; bool cntx; int i; @@ -2402,19 +2402,19 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, } /* 4. Program custom width to match the link protocol */ - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_WIDTH, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_WIDTH, PHY_C20_CUSTOM_WIDTH_MASK, PHY_C20_CUSTOM_WIDTH(intel_get_c20_custom_width(clock, dp)), MB_WRITE_COMMITTED); /* 5. For DP or 6. For HDMI */ if (dp) { - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(6) | PHY_C20_CUSTOM_SERDES_MASK, BIT(6) | PHY_C20_CUSTOM_SERDES(intel_c20_get_dp_rate(clock)), MB_WRITE_COMMITTED); } else { - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(7) | PHY_C20_CUSTOM_SERDES_MASK, is_hdmi_frl(clock) ? BIT(7) : 0, MB_WRITE_COMMITTED); @@ -2428,7 +2428,7 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, * 7. Write Vendor specific registers to toggle context setting to load * the updated programming toggle context bit */ - intel_cx0_rmw(encoder, lane, PHY_C20_VDR_CUSTOM_SERDES_RATE, + intel_cx0_rmw(encoder, owned_lane_mask, PHY_C20_VDR_CUSTOM_SERDES_RATE, BIT(0), cntx ? 0 : 1, MB_WRITE_COMMITTED); } -- cgit From 37153b0ad3d3c26fd4b6091b124245a4401da6fd Mon Sep 17 00:00:00 2001 From: Balasubramani Vivekanandan Date: Tue, 30 Apr 2024 10:28:33 -0700 Subject: drm/i915/bmg: Define IS_BATTLEMAGE macro Display code uses IS_BATTLEMAGE macro but the platform support doesn't exist in i915. So fake IS_BATTLEMAGE macro defined to enable building i915 code. We should make sure the macro parameter is used in the always-false expression so that we don't run into "unused variable" warnings from i915 builds if the IS_BATTLEMAGE() check is the only place the i915 pointer gets used in a function. While we're at it, also update the IS_LUNARLAKE macro to include the parameter in the false expression for consistency. Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-3-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/i915_drv.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ee0d7d5f135d..481ddce038b2 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -535,7 +535,15 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P) #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2) #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE) -#define IS_LUNARLAKE(i915) 0 +/* + * Display code shared by i915 and Xe relies on macros like IS_LUNARLAKE, + * so we need to define these even on platforms that the i915 base driver + * doesn't support. Ensure the parameter is used in the definition to + * avoid 'unused variable' warnings when compiling the shared display code + * for i915. + */ +#define IS_LUNARLAKE(i915) (0 && i915) +#define IS_BATTLEMAGE(i915) (0 && i915) #define IS_DG2_G10(i915) \ IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10) -- cgit From 080b76d8111711a726f368361e0bc9ae339fed7d Mon Sep 17 00:00:00 2001 From: Clint Taylor Date: Tue, 30 Apr 2024 10:28:34 -0700 Subject: drm/i915/xe2hpd: Initial cdclk table Add Xe2_HPD specific CDCLK table and use MTL Funcs. Bspec: 65243 CC: Lucas De Marchi Signed-off-by: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-4-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 7a833b5f2de2..b78154c82a71 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -1443,6 +1443,14 @@ static const struct intel_cdclk_vals xe2lpd_cdclk_table[] = { {} }; +/* + * Xe2_HPD always uses the minimal cdclk table from Wa_15015413771 + */ +static const struct intel_cdclk_vals xe2hpd_cdclk_table[] = { + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, + {} +}; + static const int cdclk_squash_len = 16; static int cdclk_squash_divider(u16 waveform) @@ -3778,6 +3786,9 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) >= 20) { dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; dev_priv->display.cdclk.table = xe2lpd_cdclk_table; + } else if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1)) { + dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; + dev_priv->display.cdclk.table = xe2hpd_cdclk_table; } else if (DISPLAY_VER(dev_priv) >= 14) { dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs; dev_priv->display.cdclk.table = mtl_cdclk_table; -- cgit From 68cd73716216f04ef12433a6486821a291736ce3 Mon Sep 17 00:00:00 2001 From: Radhakrishna Sripada Date: Tue, 30 Apr 2024 10:28:35 -0700 Subject: drm/i915/bmg: Extend DG2 tc check to future Discrete cards use the Port numbers TC1-4 for the offsets. The regular flow for type-c subsystem port initialization can be skipped. This check is present in DG2. Extend this to future discrete products. Signed-off-by: Radhakrishna Sripada Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-5-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ee862f5d0ff4..c62ef56ca0dc 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1894,11 +1894,10 @@ bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy) bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy) { /* - * DG2's "TC1", although TC-capable output, doesn't share the same flow - * as other platforms on the display engine side and rather rely on the - * SNPS PHY, that is programmed separately + * Discrete GPU phy's are not attached to FIA's to support TC + * subsystem Legacy or non-legacy, and only support native DP/HDMI */ - if (IS_DG2(dev_priv)) + if (IS_DGFX(dev_priv)) return false; if (DISPLAY_VER(dev_priv) >= 13) -- cgit From 32e73fef7ea2b4728d2580d043613cfeabd90b6c Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Tue, 30 Apr 2024 10:28:36 -0700 Subject: drm/i915/xe2hpd: Properly disable power in port A MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Xe2_HPD has a different value to power down port A. BSpec: 65450 Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-6-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 0444a1ffb030..8621f71e15b4 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2900,17 +2900,28 @@ void intel_mtl_pll_enable(struct intel_encoder *encoder, intel_cx0pll_enable(encoder, crtc_state); } +static u8 cx0_power_control_disable_val(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_encoder_is_c10phy(encoder)) + return CX0_P2PG_STATE_DISABLE; + + if (IS_BATTLEMAGE(i915) && encoder->port == PORT_A) + return CX0_P2PG_STATE_DISABLE; + + return CX0_P4PG_STATE_DISABLE; +} + static void intel_cx0pll_disable(struct intel_encoder *encoder) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum phy phy = intel_encoder_to_phy(encoder); - bool is_c10 = intel_encoder_is_c10phy(encoder); intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder); /* 1. Change owned PHY lane power to Disable state. */ intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES, - is_c10 ? CX0_P2PG_STATE_DISABLE : - CX0_P4PG_STATE_DISABLE); + cx0_power_control_disable_val(encoder)); /* * 2. Follow the Display Voltage Frequency Switching Sequence Before -- cgit From 96b0ffecc0b3cca0437166668c6ab6bee606ae82 Mon Sep 17 00:00:00 2001 From: Balasubramani Vivekanandan Date: Tue, 30 Apr 2024 10:28:37 -0700 Subject: drm/i915/xe2hpd: Add new C20 PHY SRAM address Xe2_HPD has different offsets for C20 PHY SRAM configuration context location. Use the display version to select the right address. Note that Xe2_LPD uses the same C20 SRAM offsets used by Xe_LPDP (i.e. MTL's display). According to the BSpec, currently, only Xe2_HPD has different offsets, so make sure it is the only display using them in the driver. v2: * Redesigned how the right offsets are selected for different display IP versions. v3: Fix white space error(RK) Bspec: 67610 Cc: Clint Taylor Cc: Gustavo Sousa Cc: Jani Nikula Signed-off-by: Balasubramani Vivekanandan Signed-off-by: Lucas De Marchi Signed-off-by: Radhakrishna Sripada Reviewed-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-7-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 65 ++++++++++++++--------- drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 48 ++++++++++++++--- 2 files changed, 81 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 8621f71e15b4..98588bba7f49 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2161,6 +2161,7 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, bool cntx; intel_wakeref_t wakeref; int i; + struct drm_i915_private *i915 = to_i915(encoder->base.dev); wakeref = intel_cx0_phy_transaction_begin(encoder); @@ -2170,42 +2171,50 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, /* Read Tx configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { if (cntx) - pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_TX_CNTX_CFG(i)); + pll_state->tx[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_B_TX_CNTX_CFG(i915, i)); else - pll_state->tx[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_TX_CNTX_CFG(i)); + pll_state->tx[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_A_TX_CNTX_CFG(i915, i)); } /* Read common configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { if (cntx) - pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_CMN_CNTX_CFG(i)); + pll_state->cmn[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_B_CMN_CNTX_CFG(i915, i)); else - pll_state->cmn[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_CMN_CNTX_CFG(i)); + pll_state->cmn[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_A_CMN_CNTX_CFG(i915, i)); } if (intel_c20phy_use_mpllb(pll_state)) { /* MPLLB configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { if (cntx) - pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLB_CNTX_CFG(i)); + pll_state->mpllb[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_B_MPLLB_CNTX_CFG(i915, i)); else - pll_state->mpllb[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLB_CNTX_CFG(i)); + pll_state->mpllb[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_A_MPLLB_CNTX_CFG(i915, i)); } } else { /* MPLLA configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { if (cntx) - pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLA_CNTX_CFG(i)); + pll_state->mplla[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_B_MPLLA_CNTX_CFG(i915, i)); else - pll_state->mplla[i] = intel_c20_sram_read(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLA_CNTX_CFG(i)); + pll_state->mplla[i] = intel_c20_sram_read(encoder, + INTEL_CX0_LANE0, + PHY_C20_A_MPLLA_CNTX_CFG(i915, i)); } } @@ -2363,17 +2372,25 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, /* 3.1 Tx configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) { if (cntx) - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_TX_CNTX_CFG(i), pll_state->tx[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_A_TX_CNTX_CFG(i915, i), + pll_state->tx[i]); else - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_TX_CNTX_CFG(i), pll_state->tx[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_B_TX_CNTX_CFG(i915, i), + pll_state->tx[i]); } /* 3.2 common configuration */ for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) { if (cntx) - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_A_CMN_CNTX_CFG(i), pll_state->cmn[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_A_CMN_CNTX_CFG(i915, i), + pll_state->cmn[i]); else - intel_c20_sram_write(encoder, INTEL_CX0_LANE0, PHY_C20_B_CMN_CNTX_CFG(i), pll_state->cmn[i]); + intel_c20_sram_write(encoder, INTEL_CX0_LANE0, + PHY_C20_B_CMN_CNTX_CFG(i915, i), + pll_state->cmn[i]); } /* 3.3 mpllb or mplla configuration */ @@ -2381,22 +2398,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915, for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) { if (cntx) intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLB_CNTX_CFG(i), + PHY_C20_A_MPLLB_CNTX_CFG(i915, i), pll_state->mpllb[i]); else intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLB_CNTX_CFG(i), + PHY_C20_B_MPLLB_CNTX_CFG(i915, i), pll_state->mpllb[i]); } } else { for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) { if (cntx) intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_A_MPLLA_CNTX_CFG(i), + PHY_C20_A_MPLLA_CNTX_CFG(i915, i), pll_state->mplla[i]); else intel_c20_sram_write(encoder, INTEL_CX0_LANE0, - PHY_C20_B_MPLLA_CNTX_CFG(i), + PHY_C20_B_MPLLA_CNTX_CFG(i915, i), pll_state->mplla[i]); } } diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h index bdd0c8c4ef97..ab3ae110b68f 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h @@ -254,18 +254,50 @@ #define PHY_C20_VDR_CUSTOM_WIDTH 0xD02 #define PHY_C20_CUSTOM_WIDTH_MASK REG_GENMASK(1, 0) #define PHY_C20_CUSTOM_WIDTH(val) REG_FIELD_PREP8(PHY_C20_CUSTOM_WIDTH_MASK, val) -#define PHY_C20_A_TX_CNTX_CFG(idx) (0xCF2E - (idx)) -#define PHY_C20_B_TX_CNTX_CFG(idx) (0xCF2A - (idx)) + +#define _MTL_C20_A_TX_CNTX_CFG 0xCF2E +#define _MTL_C20_B_TX_CNTX_CFG 0xCF2A +#define _MTL_C20_A_CMN_CNTX_CFG 0xCDAA +#define _MTL_C20_B_CMN_CNTX_CFG 0xCDA5 +#define _MTL_C20_A_MPLLA_CFG 0xCCF0 +#define _MTL_C20_B_MPLLA_CFG 0xCCE5 +#define _MTL_C20_A_MPLLB_CFG 0xCB5A +#define _MTL_C20_B_MPLLB_CFG 0xCB4E + +#define _XE2HPD_C20_A_TX_CNTX_CFG 0xCF5E +#define _XE2HPD_C20_B_TX_CNTX_CFG 0xCF5A +#define _XE2HPD_C20_A_CMN_CNTX_CFG 0xCE8E +#define _XE2HPD_C20_B_CMN_CNTX_CFG 0xCE89 +#define _XE2HPD_C20_A_MPLLA_CFG 0xCE58 +#define _XE2HPD_C20_B_MPLLA_CFG 0xCE4D +#define _XE2HPD_C20_A_MPLLB_CFG 0xCCC2 +#define _XE2HPD_C20_B_MPLLB_CFG 0xCCB6 + +#define _IS_XE2HPD_C20(i915) (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) + +#define PHY_C20_A_TX_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_TX_CNTX_CFG : _MTL_C20_A_TX_CNTX_CFG) - (idx)) +#define PHY_C20_B_TX_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_TX_CNTX_CFG : _MTL_C20_B_TX_CNTX_CFG) - (idx)) #define C20_PHY_TX_RATE REG_GENMASK(2, 0) -#define PHY_C20_A_CMN_CNTX_CFG(idx) (0xCDAA - (idx)) -#define PHY_C20_B_CMN_CNTX_CFG(idx) (0xCDA5 - (idx)) -#define PHY_C20_A_MPLLA_CNTX_CFG(idx) (0xCCF0 - (idx)) -#define PHY_C20_B_MPLLA_CNTX_CFG(idx) (0xCCE5 - (idx)) + +#define PHY_C20_A_CMN_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_CMN_CNTX_CFG : _MTL_C20_A_CMN_CNTX_CFG) - (idx)) +#define PHY_C20_B_CMN_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_CMN_CNTX_CFG : _MTL_C20_B_CMN_CNTX_CFG) - (idx)) +#define PHY_C20_A_MPLLA_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLA_CFG : _MTL_C20_A_MPLLA_CFG) - (idx)) +#define PHY_C20_B_MPLLA_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLA_CFG : _MTL_C20_B_MPLLA_CFG) - (idx)) #define C20_MPLLA_FRACEN REG_BIT(14) #define C20_FB_CLK_DIV4_EN REG_BIT(13) #define C20_MPLLA_TX_CLK_DIV_MASK REG_GENMASK(10, 8) -#define PHY_C20_A_MPLLB_CNTX_CFG(idx) (0xCB5A - (idx)) -#define PHY_C20_B_MPLLB_CNTX_CFG(idx) (0xCB4E - (idx)) + +#define PHY_C20_A_MPLLB_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_A_MPLLB_CFG : _MTL_C20_A_MPLLB_CFG) - (idx)) +#define PHY_C20_B_MPLLB_CNTX_CFG(i915, idx) \ + ((_IS_XE2HPD_C20(i915) ? _XE2HPD_C20_B_MPLLB_CFG : _MTL_C20_B_MPLLB_CFG) - (idx)) + #define C20_MPLLB_TX_CLK_DIV_MASK REG_GENMASK(15, 13) #define C20_MPLLB_FRACEN REG_BIT(13) #define C20_REF_CLK_MPLLB_DIV_MASK REG_GENMASK(12, 10) -- cgit From 75b87e9f3dab7304982e90627c7ceec108ea83c7 Mon Sep 17 00:00:00 2001 From: Balasubramani Vivekanandan Date: Tue, 30 Apr 2024 10:28:38 -0700 Subject: drm/i915/xe2hpd: Add support for eDP PLL configuration Tables for eDP PHY PLL configuration for different link rates added for Xe2_HPD. Previous platforms were using C10 PHY for eDP port whereas Xe2_HPD has C20 PHY. v2: Updated with a more appropriate Bspec number. Bspec: 74165 CC: Clint Taylor Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-8-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 147 ++++++++++++++++++++++++++- 1 file changed, 146 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 98588bba7f49..fa68a4de9103 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -945,6 +945,148 @@ static const struct intel_c20pll_state * const mtl_c20_dp_tables[] = { NULL, }; +/* + * eDP link rates with 38.4 MHz reference clock. + */ + +static const struct intel_c20pll_state xe2hpd_c20_edp_r216 = { + .clock = 216000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x50e1, + 0x2120, + 0x8e18, + 0xbfc1, + 0x9000, + 0x78f6, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r243 = { + .clock = 243000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x50fd, + 0x2120, + 0x8f18, + 0xbfc1, + 0xa200, + 0x8814, + 0x2000, + 0x0001, + 0x1000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r324 = { + .clock = 324000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x30a8, + 0x2110, + 0xcd9a, + 0xbfc1, + 0x6c00, + 0x5ab8, + 0x2000, + 0x0001, + 0x6000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r432 = { + .clock = 432000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x30e1, + 0x2110, + 0x8e18, + 0xbfc1, + 0x9000, + 0x78f6, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state xe2hpd_c20_edp_r675 = { + .clock = 675000, + .tx = { 0xbe88, + 0x4800, + 0x0000, + }, + .cmn = { 0x0500, + 0x0005, + 0x0000, + 0x0000, + }, + .mpllb = { 0x10af, + 0x2108, + 0xce1a, + 0xbfc1, + 0x7080, + 0x5e80, + 0x2000, + 0x0001, + 0x6400, + 0x0000, + 0x0000, + }, +}; + +static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = { + &mtl_c20_dp_rbr, + &xe2hpd_c20_edp_r216, + &xe2hpd_c20_edp_r243, + &mtl_c20_dp_hbr1, + &xe2hpd_c20_edp_r324, + &xe2hpd_c20_edp_r432, + &mtl_c20_dp_hbr2, + &xe2hpd_c20_edp_r675, + &mtl_c20_dp_hbr3, + NULL, +}; + /* * HDMI link rates with 38.4 MHz reference clock. */ @@ -2062,7 +2204,10 @@ intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { if (intel_crtc_has_dp_encoder(crtc_state)) - return mtl_c20_dp_tables; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) + return xe2hpd_c20_edp_tables; + else + return mtl_c20_dp_tables; else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return mtl_c20_hdmi_tables; -- cgit From 59c27724b24aa54f0dc2600f71b50e620874a050 Mon Sep 17 00:00:00 2001 From: Ravi Kumar Vodapalli Date: Tue, 30 Apr 2024 10:28:39 -0700 Subject: drm/i915/xe2hpd: update pll values in sync with Bspec DP/eDP and HDMI pll values are updated for Xe2_HPD platform v2: Removed the unsupported mtl_c20_dp_uhbr20 from xehpd_c20_dp_tables Bspec: 74165 Signed-off-by: Ravi Kumar Vodapalli Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-9-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 46 ++++++++++++++++++++++++++-- 1 file changed, 44 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index fa68a4de9103..1b1ebafa49e8 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -1087,6 +1087,41 @@ static const struct intel_c20pll_state * const xe2hpd_c20_edp_tables[] = { NULL, }; +static const struct intel_c20pll_state xe2hpd_c20_dp_uhbr13_5 = { + .clock = 1350000, /* 13.5 Gbps */ + .tx = { 0xbea0, /* tx cfg0 */ + 0x4800, /* tx cfg1 */ + 0x0000, /* tx cfg2 */ + }, + .cmn = {0x0500, /* cmn cfg0*/ + 0x0005, /* cmn cfg1 */ + 0x0000, /* cmn cfg2 */ + 0x0000, /* cmn cfg3 */ + }, + .mpllb = { 0x015f, /* mpllb cfg0 */ + 0x2205, /* mpllb cfg1 */ + 0x1b17, /* mpllb cfg2 */ + 0xffc1, /* mpllb cfg3 */ + 0xbd00, /* mpllb cfg4 */ + 0x9ec3, /* mpllb cfg5 */ + 0x2000, /* mpllb cfg6 */ + 0x0001, /* mpllb cfg7 */ + 0x4800, /* mpllb cfg8 */ + 0x0000, /* mpllb cfg9 */ + 0x0000, /* mpllb cfg10 */ + }, +}; + +static const struct intel_c20pll_state * const xe2hpd_c20_dp_tables[] = { + &mtl_c20_dp_rbr, + &mtl_c20_dp_hbr1, + &mtl_c20_dp_hbr2, + &mtl_c20_dp_hbr3, + &mtl_c20_dp_uhbr10, + &xe2hpd_c20_dp_uhbr13_5, + NULL, +}; + /* * HDMI link rates with 38.4 MHz reference clock. */ @@ -2203,13 +2238,20 @@ static const struct intel_c20pll_state * const * intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state, struct intel_encoder *encoder) { - if (intel_crtc_has_dp_encoder(crtc_state)) + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + if (intel_crtc_has_dp_encoder(crtc_state)) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) return xe2hpd_c20_edp_tables; + + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) + return xe2hpd_c20_dp_tables; else return mtl_c20_dp_tables; - else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + + } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { return mtl_c20_hdmi_tables; + } MISSING_CASE(encoder->type); return NULL; -- cgit From 2de02cb17f90df9115ae46a5d7915d8c436c9878 Mon Sep 17 00:00:00 2001 From: Lucas De Marchi Date: Tue, 30 Apr 2024 10:28:40 -0700 Subject: drm/i915/xe2hpd: Add display info Add initial display info for xe2hpd. It is similar to xelpdp, but with no PORT_B. v2: Inherit from XE_LPDP_FEATURES instead of XE_LPD_FEATURES Bspec: 67066 CC: Matt Roper Signed-off-by: Lucas De Marchi Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-10-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 120e209ee74a..56a2e17d7d9e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -771,6 +771,12 @@ static const struct intel_display_device_info xe2_lpd_display = { BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D), }; +static const struct intel_display_device_info xe2_hpd_display = { + XE_LPDP_FEATURES, + .__runtime_defaults.port_mask = BIT(PORT_A) | + BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), +}; + __diag_pop(); /* @@ -852,6 +858,7 @@ static const struct { const struct intel_display_device_info *display; } gmdid_display_map[] = { { 14, 0, &xe_lpdp_display }, + { 14, 1, &xe2_hpd_display }, { 20, 0, &xe2_lpd_display }, }; -- cgit From 0dffea1e2d762178b76c7840edd4edfa763048f0 Mon Sep 17 00:00:00 2001 From: Anusha Srivatsa Date: Tue, 30 Apr 2024 10:28:41 -0700 Subject: drm/i915/xe2hpd: Configure CHICKEN_MISC_2 before enabling planes Add step 9 from initialize display sequence. v2: Commit subject improved Bpsec: 49189 Signed-off-by: Anusha Srivatsa Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-11-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_display_power.c | 4 ++++ drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 03dc7edcc443..a860d88a65da 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1688,6 +1688,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv, if (IS_DG2(dev_priv)) intel_snps_phy_wait_for_calibration(dev_priv); + /* 9. XE2_HPD: Program CHICKEN_MISC_2 before any cursor or planes are enabled */ + if (DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 1)) + intel_de_rmw(dev_priv, CHICKEN_MISC_2, BMG_DARB_HALF_BLK_END_BURST, 1); + if (resume) intel_dmc_load_program(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e22a82a5ddd7..ae692f461982 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3449,6 +3449,7 @@ #define CHICKEN_MISC_2 _MMIO(0x42084) #define CHICKEN_MISC_DISABLE_DPT REG_BIT(30) /* adl,dg2 */ +#define BMG_DARB_HALF_BLK_END_BURST REG_BIT(27) #define KBL_ARB_FILL_SPARE_14 REG_BIT(14) #define KBL_ARB_FILL_SPARE_13 REG_BIT(13) #define GLK_CL2_PWR_DOWN REG_BIT(12) -- cgit From 772933b3ab3a8157bb718154883c248c5693d81e Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Tue, 30 Apr 2024 10:28:42 -0700 Subject: drm/i915/xe2hpd: Add max memory bandwidth algorithm Unlike DG2, Xe2_HPD does support multiple GV points with different maximum memory bandwidths, but uses a much simpler algorithm than igpu platforms use. Bspec: 64631 CC: Jani Nikula Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Radhakrishna Sripada Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-12-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_bw.c | 65 ++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++ drivers/gpu/drm/xe/xe_device_types.h | 1 + 4 files changed, 69 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 972ea887e232..47036d4abb33 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -22,6 +22,8 @@ struct intel_qgv_point { u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd; }; +#define DEPROGBWPCLIMIT 60 + struct intel_psf_gv_point { u8 clk; /* clock in multiples of 16.6666 MHz */ }; @@ -241,6 +243,9 @@ static int icl_get_qgv_points(struct drm_i915_private *dev_priv, qi->channel_width = 16; qi->deinterleave = 4; break; + case INTEL_DRAM_GDDR: + qi->channel_width = 32; + break; default: MISSING_CASE(dram_info->type); return -EINVAL; @@ -387,6 +392,12 @@ static const struct intel_sa_info mtl_sa_info = { .derating = 10, }; +static const struct intel_sa_info xe2_hpd_sa_info = { + .derating = 30, + .deprogbwlimit = 53, + /* Other values not used by simplified algorithm */ +}; + static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa) { struct intel_qgv_info qi = {}; @@ -493,7 +504,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel dclk_max = icl_sagv_max_dclk(&qi); peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max; - maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */ + maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 100); ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels); /* @@ -598,6 +609,54 @@ static void dg2_get_bw_info(struct drm_i915_private *i915) i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED; } +static int xe2_hpd_get_bw_info(struct drm_i915_private *i915, + const struct intel_sa_info *sa) +{ + struct intel_qgv_info qi = {}; + int num_channels = i915->dram_info.num_channels; + int peakbw, maxdebw; + int ret, i; + + ret = icl_get_qgv_points(i915, &qi, true); + if (ret) { + drm_dbg_kms(&i915->drm, + "Failed to get memory subsystem information, ignoring bandwidth limits"); + return ret; + } + + peakbw = num_channels * qi.channel_width / 8 * icl_sagv_max_dclk(&qi); + maxdebw = min(sa->deprogbwlimit * 1000, peakbw * DEPROGBWPCLIMIT / 10); + + for (i = 0; i < qi.num_points; i++) { + const struct intel_qgv_point *point = &qi.points[i]; + int bw = num_channels * (qi.channel_width / 8) * point->dclk; + + i915->display.bw.max[0].deratedbw[i] = + min(maxdebw, (100 - sa->derating) * bw / 100); + i915->display.bw.max[0].peakbw[i] = bw; + + drm_dbg_kms(&i915->drm, "QGV %d: deratedbw=%u peakbw: %u\n", + i, i915->display.bw.max[0].deratedbw[i], + i915->display.bw.max[0].peakbw[i]); + } + + /* Bandwidth does not depend on # of planes; set all groups the same */ + i915->display.bw.max[0].num_planes = 1; + i915->display.bw.max[0].num_qgv_points = qi.num_points; + for (i = 1; i < ARRAY_SIZE(i915->display.bw.max); i++) + memcpy(&i915->display.bw.max[i], &i915->display.bw.max[0], + sizeof(i915->display.bw.max[0])); + + /* + * Xe2_HPD should always have exactly two QGV points representing + * battery and plugged-in operation. + */ + drm_WARN_ON(&i915->drm, qi.num_points != 2); + i915->display.sagv.status = I915_SAGV_ENABLED; + + return 0; +} + static unsigned int icl_max_bw_index(struct drm_i915_private *dev_priv, int num_planes, int qgv_point) { @@ -684,7 +743,9 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv) if (!HAS_DISPLAY(dev_priv)) return; - if (DISPLAY_VER(dev_priv) >= 14) + if (DISPLAY_VER_FULL(dev_priv) >= IP_VER(14, 1) && IS_DGFX(dev_priv)) + xe2_hpd_get_bw_info(dev_priv, &xe2_hpd_sa_info); + else if (DISPLAY_VER(dev_priv) >= 14) tgl_get_bw_info(dev_priv, &mtl_sa_info); else if (IS_DG2(dev_priv)) dg2_get_bw_info(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 481ddce038b2..d1d21d433766 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -305,6 +305,7 @@ struct drm_i915_private { INTEL_DRAM_LPDDR4, INTEL_DRAM_DDR5, INTEL_DRAM_LPDDR5, + INTEL_DRAM_GDDR, } type; u8 num_qgv_points; u8 num_psf_gv_points; diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index e3287f1de774..18a879e98f03 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -640,6 +640,10 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915) case 5: dram_info->type = INTEL_DRAM_LPDDR3; break; + case 8: + drm_WARN_ON(&i915->drm, !IS_DGFX(i915)); + dram_info->type = INTEL_DRAM_GDDR; + break; default: MISSING_CASE(val); return -EINVAL; diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 2e62450d86e1..14144a3814fc 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -484,6 +484,7 @@ struct xe_device { INTEL_DRAM_LPDDR4, INTEL_DRAM_DDR5, INTEL_DRAM_LPDDR5, + INTEL_DRAM_GDDR, } type; u8 num_qgv_points; u8 num_psf_gv_points; -- cgit From 0f6a95582de3065d27b52bb75195d666a40ab575 Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Tue, 30 Apr 2024 10:28:43 -0700 Subject: drm/i915/xe2hpd: Do not program MBUS_DBOX BW credits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No display IP beyond Xe_LPD+ has "BW credits" bits in MBUS_DBOX_CTL register. Restrict the programming only to Xe_LPD+. BSpec: 49213 CC: Matt Roper Signed-off-by: José Roberto de Souza Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-13-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/skl_watermark.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index e6476aa621a7..f85980aba25e 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3616,7 +3616,7 @@ static void intel_mbus_dbox_update(struct intel_atomic_state *state) for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, new_dbuf_state->active_pipes) { u32 pipe_val = val; - if (DISPLAY_VER(i915) >= 14) { + if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) { if (xelpdp_is_only_pipe_per_dbuf_bank(crtc->pipe, new_dbuf_state->active_pipes)) pipe_val |= MBUS_DBOX_BW_8CREDITS_MTL; -- cgit From a8c026d0e67119af490b8c284a4a4b4d180fb688 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Tue, 30 Apr 2024 10:28:44 -0700 Subject: drm/i915/bmg: BMG should re-use MTL's south display logic Battlemage's south display is the same as Meteor Lake's, including the need to invert the HPD pins, which Lunar Lake does not need. Signed-off-by: Matt Roper Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Dnyaneshwar Bhadane Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-14-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/soc/intel_pch.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c index 3cad6dac06b0..542eea50093c 100644 --- a/drivers/gpu/drm/i915/soc/intel_pch.c +++ b/drivers/gpu/drm/i915/soc/intel_pch.c @@ -218,10 +218,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv) if (DISPLAY_VER(dev_priv) >= 20) { dev_priv->pch_type = PCH_LNL; return; - } else if (IS_METEORLAKE(dev_priv)) { + } else if (IS_BATTLEMAGE(dev_priv) || IS_METEORLAKE(dev_priv)) { /* * Both north display and south display are on the SoC die. - * The real PCH is uninvolved in display. + * The real PCH (if it even exists) is uninvolved in display. */ dev_priv->pch_type = PCH_MTL; return; -- cgit From c528aaa36db031591bfa9d4cb86f23dda4f413b9 Mon Sep 17 00:00:00 2001 From: Ankit Nautiyal Date: Tue, 30 Apr 2024 10:28:45 -0700 Subject: Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping" This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f. For BMG it seems that the VBT to DDI mapping does not follow DG1, and DG2, but follows ADLP mapping given in Bspec:20124. Signed-off-by: Ankit Nautiyal Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-15-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_bios.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 661842a3c2e6..cf770c866d13 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2231,15 +2231,14 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) const u8 *ddc_pin_map; int i, n_entries; - if (IS_DGFX(i915)) - return vbt_pin; - if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) { ddc_pin_map = adlp_ddc_pin_map; n_entries = ARRAY_SIZE(adlp_ddc_pin_map); } else if (IS_ALDERLAKE_S(i915)) { ddc_pin_map = adls_ddc_pin_map; n_entries = ARRAY_SIZE(adls_ddc_pin_map); + } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { + return vbt_pin; } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { ddc_pin_map = rkl_pch_tgp_ddc_pin_map; n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); -- cgit From 98b1c87a5e51b86d1fad390ad4756cc2bc03cd05 Mon Sep 17 00:00:00 2001 From: Balasubramani Vivekanandan Date: Tue, 30 Apr 2024 10:28:46 -0700 Subject: drm/i915/xe2hpd: Set maximum DP rate to UHBR13.5 Max supported speed by xe2hpd is UHBR13.5. Limit the max DP source rate to it. Bspec: 67066 Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Shekhar Chauhan Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-16-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index e05e25cd4a94..486361eb0070 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -477,6 +477,9 @@ static int mtl_max_source_rate(struct intel_dp *intel_dp) if (intel_encoder_is_c10phy(encoder)) return 810000; + if (DISPLAY_VER_FULL(to_i915(encoder->base.dev)) == IP_VER(14, 1)) + return 1350000; + return 2000000; } -- cgit From 1372708168e50c08bbbe092e00036701c7adf547 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Tue, 30 Apr 2024 10:28:47 -0700 Subject: drm/xe/gt_print: add xe_gt_err_once() Needed in an upcoming patch, where we want GT level print, but only which to trigger once to avoid flooding dmesg. Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Nirmoy Das Signed-off-by: Radhakrishna Sripada Acked-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-17-radhakrishna.sripada@intel.com --- drivers/gpu/drm/xe/xe_gt_printk.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_gt_printk.h b/drivers/gpu/drm/xe/xe_gt_printk.h index c2b004d3f48e..d6228baaff1e 100644 --- a/drivers/gpu/drm/xe/xe_gt_printk.h +++ b/drivers/gpu/drm/xe/xe_gt_printk.h @@ -13,6 +13,9 @@ #define xe_gt_printk(_gt, _level, _fmt, ...) \ drm_##_level(>_to_xe(_gt)->drm, "GT%u: " _fmt, (_gt)->info.id, ##__VA_ARGS__) +#define xe_gt_err_once(_gt, _fmt, ...) \ + xe_gt_printk((_gt), err_once, _fmt, ##__VA_ARGS__) + #define xe_gt_err(_gt, _fmt, ...) \ xe_gt_printk((_gt), err, _fmt, ##__VA_ARGS__) -- cgit From c01c6066e6fa6f13888f06a210f9a1d600590f42 Mon Sep 17 00:00:00 2001 From: Nirmoy Das Date: Tue, 30 Apr 2024 10:28:48 -0700 Subject: drm/xe/device: implement transient flush Display surfaces can be tagged as transient by mapping it using one of the various L3:XD PAT index modes on Xe2. The expectation is that KMD needs to request transient data flush at the start of flip sequence to ensure all transient data in L3 cache is flushed to memory. Add a routine for this which we can then call from the display code. v2: rebase(RK) Signed-off-by: Nirmoy Das Co-developed-by: Matthew Auld Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Acked-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-18-radhakrishna.sripada@intel.com --- drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++ drivers/gpu/drm/xe/xe_device.c | 49 ++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/xe/xe_device.h | 2 ++ 3 files changed, 54 insertions(+) diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index 94445810ccc9..26fb4943c79e 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -321,6 +321,9 @@ #define XE2LPM_L3SQCREG5 XE_REG_MCR(0xb658) +#define XE2_TDF_CTRL XE_REG(0xb418) +#define TRANSIENT_FLUSH_REQUEST REG_BIT(0) + #define XEHP_MERT_MOD_CTRL XE_REG_MCR(0xcf28) #define RENDER_MOD_CTRL XE_REG_MCR(0xcf2c) #define COMP_MOD_CTRL XE_REG_MCR(0xcf30) diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 5ef9b50a20d0..c3267a21957b 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -708,6 +708,55 @@ void xe_device_wmb(struct xe_device *xe) xe_mmio_write32(gt, SOFTWARE_FLAGS_SPR33, 0); } +/** + * xe_device_td_flush() - Flush transient L3 cache entries + * @xe: The device + * + * Display engine has direct access to memory and is never coherent with L3/L4 + * caches (or CPU caches), however KMD is responsible for specifically flushing + * transient L3 GPU cache entries prior to the flip sequence to ensure scanout + * can happen from such a surface without seeing corruption. + * + * Display surfaces can be tagged as transient by mapping it using one of the + * various L3:XD PAT index modes on Xe2. + * + * Note: On non-discrete xe2 platforms, like LNL, the entire L3 cache is flushed + * at the end of each submission via PIPE_CONTROL for compute/render, since SA + * Media is not coherent with L3 and we want to support render-vs-media + * usescases. For other engines like copy/blt the HW internally forces uncached + * behaviour, hence why we can skip the TDF on such platforms. + */ +void xe_device_td_flush(struct xe_device *xe) +{ + struct xe_gt *gt; + u8 id; + + if (!IS_DGFX(xe) || GRAPHICS_VER(xe) < 20) + return; + + for_each_gt(gt, xe, id) { + if (xe_gt_is_media_type(gt)) + continue; + + if (xe_force_wake_get(gt_to_fw(gt), XE_FW_GT)) + return; + + xe_mmio_write32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST); + /* + * FIXME: We can likely do better here with our choice of + * timeout. Currently we just assume the worst case, i.e. 150us, + * which is believed to be sufficient to cover the worst case + * scenario on current platforms if all cache entries are + * transient and need to be flushed.. + */ + if (xe_mmio_wait32(gt, XE2_TDF_CTRL, TRANSIENT_FLUSH_REQUEST, 0, + 150, NULL, false)) + xe_gt_err_once(gt, "TD flush timeout\n"); + + xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); + } +} + u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size) { return xe_device_has_flat_ccs(xe) ? diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h index 36d4434ebccc..7524a71c0d84 100644 --- a/drivers/gpu/drm/xe/xe_device.h +++ b/drivers/gpu/drm/xe/xe_device.h @@ -167,4 +167,6 @@ void xe_device_snapshot_print(struct xe_device *xe, struct drm_printer *p); u64 xe_device_canonicalize_addr(struct xe_device *xe, u64 address); u64 xe_device_uncanonicalize_addr(struct xe_device *xe, u64 address); +void xe_device_td_flush(struct xe_device *xe); + #endif -- cgit From 4071ada7ae313da2e6bb2c1ebc097bd12f9da761 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Tue, 30 Apr 2024 10:28:49 -0700 Subject: drm/i915/display: perform transient flush Perform manual transient cache flush prior to flip and at the end of frontbuffer_flush. This is needed to ensure display engine doesn't see garbage if the surface is L3:XD dirty. Testcase: igt@xe-pat@display-vs-wb-transient Signed-off-by: Matthew Auld Signed-off-by: Balasubramani Vivekanandan Acked-by: Nirmoy Das Reviewed-by: Matt Roper Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-19-radhakrishna.sripada@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 3 +++ drivers/gpu/drm/i915/display/intel_frontbuffer.c | 2 ++ drivers/gpu/drm/i915/display/intel_tdf.h | 25 ++++++++++++++++++++++++ drivers/gpu/drm/xe/Makefile | 3 ++- drivers/gpu/drm/xe/display/xe_tdf.c | 13 ++++++++++++ 5 files changed, 45 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/display/intel_tdf.h create mode 100644 drivers/gpu/drm/xe/display/xe_tdf.c diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c62ef56ca0dc..ef986b508431 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -109,6 +109,7 @@ #include "intel_sdvo.h" #include "intel_snps_phy.h" #include "intel_tc.h" +#include "intel_tdf.h" #include "intel_tv.h" #include "intel_vblank.h" #include "intel_vdsc.h" @@ -7233,6 +7234,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state) intel_atomic_commit_fence_wait(state); + intel_td_flush(dev_priv); + drm_atomic_helper_wait_for_dependencies(&state->base); drm_dp_mst_atomic_wait_for_dependencies(&state->base); intel_atomic_global_state_wait_for_dependencies(state); diff --git a/drivers/gpu/drm/i915/display/intel_frontbuffer.c b/drivers/gpu/drm/i915/display/intel_frontbuffer.c index 2ea37c0414a9..4923c340a0b6 100644 --- a/drivers/gpu/drm/i915/display/intel_frontbuffer.c +++ b/drivers/gpu/drm/i915/display/intel_frontbuffer.c @@ -65,6 +65,7 @@ #include "intel_fbc.h" #include "intel_frontbuffer.h" #include "intel_psr.h" +#include "intel_tdf.h" /** * frontbuffer_flush - flush frontbuffer @@ -93,6 +94,7 @@ static void frontbuffer_flush(struct drm_i915_private *i915, trace_intel_frontbuffer_flush(i915, frontbuffer_bits, origin); might_sleep(); + intel_td_flush(i915); intel_drrs_flush(i915, frontbuffer_bits); intel_psr_flush(i915, frontbuffer_bits, origin); intel_fbc_flush(i915, frontbuffer_bits, origin); diff --git a/drivers/gpu/drm/i915/display/intel_tdf.h b/drivers/gpu/drm/i915/display/intel_tdf.h new file mode 100644 index 000000000000..353cde21f6c2 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_tdf.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_TDF_H__ +#define __INTEL_TDF_H__ + +/* + * TDF (Transient-Data-Flush) is needed for Xe2+ where special L3:XD caching can + * be enabled through various PAT index modes. Idea is to use this caching mode + * when for example rendering onto the display surface, with the promise that + * KMD will ensure transient cache entries are always flushed by the time we do + * the display flip, since display engine is never coherent with CPU/GPU caches. + */ + +struct drm_i915_private; + +#ifdef I915 +static inline void intel_td_flush(struct drm_i915_private *i915) {} +#else +void intel_td_flush(struct drm_i915_private *i915); +#endif + +#endif diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 8321ec4f9b46..ae579b6c8763 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -204,7 +204,8 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ display/xe_dsb_buffer.o \ display/xe_fb_pin.o \ display/xe_hdcp_gsc.o \ - display/xe_plane_initial.o + display/xe_plane_initial.o \ + display/xe_tdf.o # SOC code shared with i915 xe-$(CONFIG_DRM_XE_DISPLAY) += \ diff --git a/drivers/gpu/drm/xe/display/xe_tdf.c b/drivers/gpu/drm/xe/display/xe_tdf.c new file mode 100644 index 000000000000..2c0d4e144e09 --- /dev/null +++ b/drivers/gpu/drm/xe/display/xe_tdf.c @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#include "xe_device.h" +#include "intel_display_types.h" +#include "intel_tdf.h" + +void intel_td_flush(struct drm_i915_private *i915) +{ + xe_device_td_flush(i915); +} -- cgit From ca5d5ecbb90df41b125876796e1bc85db9514da4 Mon Sep 17 00:00:00 2001 From: Balasubramani Vivekanandan Date: Tue, 30 Apr 2024 10:28:50 -0700 Subject: drm/xe/bmg: Enable the display support Enable the display support for Battlemage Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Shekhar Chauhan Signed-off-by: Radhakrishna Sripada Acked-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20240430172850.1881525-20-radhakrishna.sripada@intel.com --- drivers/gpu/drm/xe/xe_pci.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index f326dbb1cecd..d6859108cc69 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -342,6 +342,7 @@ static const struct xe_device_desc lnl_desc = { static const struct xe_device_desc bmg_desc __maybe_unused = { DGFX_FEATURES, PLATFORM(XE_BATTLEMAGE), + .has_display = true, .require_force_probe = true, }; -- cgit From 1d231cd89841d1538d984a872041e5579b403bca Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:09:55 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_EXITLINE Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_EXITLINE register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/eb1e5fe155daf2d271af76e683a1f3f33e34403a.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 7 +++++-- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f5b33335a9ae..1cbd8c6714b1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1685,7 +1685,8 @@ void intel_psr_get_config(struct intel_encoder *encoder, } if (DISPLAY_VER(dev_priv) >= 12) { - val = intel_de_read(dev_priv, TRANS_EXITLINE(cpu_transcoder)); + val = intel_de_read(dev_priv, + TRANS_EXITLINE(dev_priv, cpu_transcoder)); pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val); } unlock: @@ -1877,7 +1878,9 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, * transcoder, EXITLINE will need to be unset when disabling PSR */ if (intel_dp->psr.dc3co_exitline) - intel_de_rmw(dev_priv, TRANS_EXITLINE(cpu_transcoder), EXITLINE_MASK, + intel_de_rmw(dev_priv, + TRANS_EXITLINE(dev_priv, cpu_transcoder), + EXITLINE_MASK, intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE); if (HAS_PSR_HW_TRACKING(dev_priv) && HAS_PSR2_SEL_FETCH(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index ebc22999572c..0e0c71ea9fe3 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -9,7 +9,7 @@ #include "intel_display_reg_defs.h" #include "intel_dp_aux_regs.h" -#define TRANS_EXITLINE(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A) +#define TRANS_EXITLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A) #define EXITLINE_ENABLE REG_BIT(31) #define EXITLINE_MASK REG_GENMASK(12, 0) #define EXITLINE_SHIFT 0 -- cgit From 676a6a1c99182a193b7515faebbe3cafc653e706 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:09:56 +0300 Subject: drm/i915: pass dev_priv explicitly to EDP_PSR_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/198858bc3925c02c0975670e3ebb5ce2084ac658.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1cbd8c6714b1..57414a1375b1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -269,7 +269,7 @@ static i915_reg_t psr_ctl_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { if (DISPLAY_VER(dev_priv) >= 8) - return EDP_PSR_CTL(cpu_transcoder); + return EDP_PSR_CTL(dev_priv, cpu_transcoder); else return HSW_SRD_CTL; } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 0e0c71ea9fe3..d815f08aac2c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -23,7 +23,7 @@ #define HSW_SRD_CTL _MMIO(0x64800) #define _SRD_CTL_A 0x60800 #define _SRD_CTL_EDP 0x6f800 -#define EDP_PSR_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A) +#define EDP_PSR_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A) #define EDP_PSR_ENABLE REG_BIT(31) #define BDW_PSR_SINGLE_FRAME REG_BIT(30) #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */ -- cgit From f9f8f8471785e1f312db59d1d14304fa333754f6 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:09:57 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_PSR_IMR Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_PSR_IMR register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/09e9c11ffb669dac901c2416462a8f3dabc86020.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index c337e0597541..a9bcf249e925 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1455,7 +1455,9 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv) if (!intel_display_power_is_enabled(dev_priv, domain)) continue; - intel_uncore_write(uncore, TRANS_PSR_IMR(trans), 0xffffffff); + intel_uncore_write(uncore, + TRANS_PSR_IMR(dev_priv, trans), + 0xffffffff); intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff); } } else { diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 57414a1375b1..12b541e8bbf9 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -305,7 +305,7 @@ static i915_reg_t psr_imr_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { if (DISPLAY_VER(dev_priv) >= 12) - return TRANS_PSR_IMR(cpu_transcoder); + return TRANS_PSR_IMR(dev_priv, cpu_transcoder); else return EDP_PSR_IMR; } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index d815f08aac2c..40dc6ee7ec1d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -66,7 +66,7 @@ #define EDP_PSR_IIR _MMIO(0x64838) #define _PSR_IMR_A 0x60814 #define _PSR_IIR_A 0x60818 -#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A) +#define TRANS_PSR_IMR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A) #define TRANS_PSR_IIR(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A) #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 0 : ((trans) - TRANSCODER_A + 1) * 8) -- cgit From 7a7a4c4eeba4a546f3be6d33b6d9f37a0c3e4a3d Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:09:58 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_PSR_IIR Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_PSR_IIR register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/3a03109d11e7f55a456c3e5ef28d3ffa69582d3d.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 10 +++++++--- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index a9bcf249e925..c41f058acaff 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -876,7 +876,8 @@ gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir) struct intel_dp *intel_dp = enc_to_intel_dp(encoder); if (DISPLAY_VER(dev_priv) >= 12) - iir_reg = TRANS_PSR_IIR(intel_dp->psr.transcoder); + iir_reg = TRANS_PSR_IIR(dev_priv, + intel_dp->psr.transcoder); else iir_reg = EDP_PSR_IIR; @@ -1458,7 +1459,9 @@ void gen11_display_irq_reset(struct drm_i915_private *dev_priv) intel_uncore_write(uncore, TRANS_PSR_IMR(dev_priv, trans), 0xffffffff); - intel_uncore_write(uncore, TRANS_PSR_IIR(trans), 0xffffffff); + intel_uncore_write(uncore, + TRANS_PSR_IIR(dev_priv, trans), + 0xffffffff); } } else { intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff); @@ -1690,7 +1693,8 @@ void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) if (!intel_display_power_is_enabled(dev_priv, domain)) continue; - gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans)); + gen3_assert_iir_is_zero(uncore, + TRANS_PSR_IIR(dev_priv, trans)); } } else { gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 12b541e8bbf9..0b1f7e62470e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -314,7 +314,7 @@ static i915_reg_t psr_iir_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { if (DISPLAY_VER(dev_priv) >= 12) - return TRANS_PSR_IIR(cpu_transcoder); + return TRANS_PSR_IIR(dev_priv, cpu_transcoder); else return EDP_PSR_IIR; } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 40dc6ee7ec1d..5fd4f875ade0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -67,7 +67,7 @@ #define _PSR_IMR_A 0x60814 #define _PSR_IIR_A 0x60818 #define TRANS_PSR_IMR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A) -#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A) +#define TRANS_PSR_IIR(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A) #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 0 : ((trans) - TRANSCODER_A + 1) * 8) #define TGL_PSR_MASK REG_GENMASK(2, 0) -- cgit From cf3d5f89a669dc29d2145d5e75d5ee5efc97ddea Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:09:59 +0300 Subject: drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_AUX_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/66ec1f81be49c87cd9613ba052ce6fd50362d0e0.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 0b1f7e62470e..daeb1b65a2e5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -323,7 +323,7 @@ static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { if (DISPLAY_VER(dev_priv) >= 8) - return EDP_PSR_AUX_CTL(cpu_transcoder); + return EDP_PSR_AUX_CTL(dev_priv, cpu_transcoder); else return HSW_SRD_AUX_CTL; } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 5fd4f875ade0..a4f785bcf605 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -86,7 +86,7 @@ #define HSW_SRD_AUX_CTL _MMIO(0x64810) #define _SRD_AUX_CTL_A 0x60810 #define _SRD_AUX_CTL_EDP 0x6f810 -#define EDP_PSR_AUX_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A) +#define EDP_PSR_AUX_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A) #define EDP_PSR_AUX_CTL_TIME_OUT_MASK DP_AUX_CH_CTL_TIME_OUT_MASK #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK DP_AUX_CH_CTL_MESSAGE_SIZE_MASK #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK DP_AUX_CH_CTL_PRECHARGE_2US_MASK -- cgit From 4c3cbdb12d4d9b5581e3e6d8497747bc71c64bed Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:00 +0300 Subject: drm/i915: pass dev_priv explicitly to EDP_PSR_AUX_DATA Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_AUX_DATA register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/4e3dc15b170c2b64168e46ebf1802d63df34b4a2.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index daeb1b65a2e5..5fe9feddc0e0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -332,7 +332,7 @@ static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder, int i) { if (DISPLAY_VER(dev_priv) >= 8) - return EDP_PSR_AUX_DATA(cpu_transcoder, i); + return EDP_PSR_AUX_DATA(dev_priv, cpu_transcoder, i); else return HSW_SRD_AUX_DATA(i); } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index a4f785bcf605..6a6d7de901bc 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -96,7 +96,7 @@ #define HSW_SRD_AUX_DATA(i) _MMIO(0x64814 + (i) * 4) /* 5 registers */ #define _SRD_AUX_DATA_A 0x60814 #define _SRD_AUX_DATA_EDP 0x6f814 -#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ +#define EDP_PSR_AUX_DATA(dev_priv, tran, i) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ #define HSW_SRD_STATUS _MMIO(0x64840) #define _SRD_STATUS_A 0x60840 -- cgit From 218f3d28d113d5143f938052f77c5c1458794c56 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:01 +0300 Subject: drm/i915: pass dev_priv explicitly to EDP_PSR_STATUS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_STATUS register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/4aaa0187b16d2b96b5b4b1d775d7349c9fc28c7c.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 5fe9feddc0e0..1a52a69e1906 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -296,7 +296,7 @@ static i915_reg_t psr_status_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { if (DISPLAY_VER(dev_priv) >= 8) - return EDP_PSR_STATUS(cpu_transcoder); + return EDP_PSR_STATUS(dev_priv, cpu_transcoder); else return HSW_SRD_STATUS; } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 6a6d7de901bc..4f3e58076a48 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -101,7 +101,7 @@ #define HSW_SRD_STATUS _MMIO(0x64840) #define _SRD_STATUS_A 0x60840 #define _SRD_STATUS_EDP 0x6f840 -#define EDP_PSR_STATUS(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A) +#define EDP_PSR_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A) #define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29) #define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0) #define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1) -- cgit From 5aa0cb6b1e74830c0e354ae9fdadd7d674c3ba6b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:02 +0300 Subject: drm/i915: pass dev_priv explicitly to EDP_PSR_PERF_CNT Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_PERF_CNT register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/21805960967ab88c1418037b98fe3e051eb00608.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1a52a69e1906..162dd07c243f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -287,7 +287,7 @@ static i915_reg_t psr_perf_cnt_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { if (DISPLAY_VER(dev_priv) >= 8) - return EDP_PSR_PERF_CNT(cpu_transcoder); + return EDP_PSR_PERF_CNT(dev_priv, cpu_transcoder); else return HSW_SRD_PERF_CNT; } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 4f3e58076a48..ef7f32c98d55 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -126,7 +126,7 @@ #define HSW_SRD_PERF_CNT _MMIO(0x64844) #define _SRD_PERF_CNT_A 0x60844 #define _SRD_PERF_CNT_EDP 0x6f844 -#define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A) +#define EDP_PSR_PERF_CNT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A) #define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0) /* PSR_MASK on SKL+ */ -- cgit From 83f4ccb3f3f941b23c064f3ae898d7a34d2bbb5d Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:03 +0300 Subject: drm/i915: pass dev_priv explicitly to EDP_PSR_DEBUG Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR_DEBUG register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/187dd49632d46e67705bd258ed7f9eabdeb108b2.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 162dd07c243f..fa1fd04d3b4a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -278,7 +278,7 @@ static i915_reg_t psr_debug_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { if (DISPLAY_VER(dev_priv) >= 8) - return EDP_PSR_DEBUG(cpu_transcoder); + return EDP_PSR_DEBUG(dev_priv, cpu_transcoder); else return HSW_SRD_DEBUG; } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index ef7f32c98d55..a74705aedbb5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -133,7 +133,7 @@ #define HSW_SRD_DEBUG _MMIO(0x64860) #define _SRD_DEBUG_A 0x60860 #define _SRD_DEBUG_EDP 0x6f860 -#define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A) +#define EDP_PSR_DEBUG(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A) #define EDP_PSR_DEBUG_MASK_MAX_SLEEP REG_BIT(28) #define EDP_PSR_DEBUG_MASK_LPSP REG_BIT(27) #define EDP_PSR_DEBUG_MASK_MEMUP REG_BIT(26) -- cgit From 9b0dddd50e6810ec9c3c6792c084fdff4c76fd41 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:04 +0300 Subject: drm/i915: pass dev_priv explicitly to EDP_PSR2_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR2_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/e7df99445716ce404bbfe733dd962288a529cf0d.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++------ drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index fa1fd04d3b4a..156660ab7adf 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -932,7 +932,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) */ intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), psr_val); - intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val); + intel_de_write(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder), val); } static bool @@ -963,7 +963,7 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder), + intel_de_rmw(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder), EDP_PSR2_IDLE_FRAMES_MASK, EDP_PSR2_IDLE_FRAMES(idle_frames)); } @@ -1700,7 +1700,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp) drm_WARN_ON(&dev_priv->drm, transcoder_has_psr2(dev_priv, cpu_transcoder) && - intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)) & EDP_PSR2_ENABLE); + intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder)) & EDP_PSR2_ENABLE); drm_WARN_ON(&dev_priv->drm, intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)) & EDP_PSR_ENABLE); @@ -2011,7 +2011,8 @@ static void intel_psr_exit(struct intel_dp *intel_dp) if (!intel_dp->psr.active) { if (transcoder_has_psr2(dev_priv, cpu_transcoder)) { - val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)); + val = intel_de_read(dev_priv, + EDP_PSR2_CTL(dev_priv, cpu_transcoder)); drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); } @@ -2027,7 +2028,8 @@ static void intel_psr_exit(struct intel_dp *intel_dp) } else if (intel_dp->psr.psr2_enabled) { tgl_disallow_dc3co_on_psr2_exit(intel_dp); - val = intel_de_rmw(dev_priv, EDP_PSR2_CTL(cpu_transcoder), + val = intel_de_rmw(dev_priv, + EDP_PSR2_CTL(dev_priv, cpu_transcoder), EDP_PSR2_ENABLE, 0); drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); @@ -3529,7 +3531,8 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder)); enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; } else if (psr->psr2_enabled) { - val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)); + val = intel_de_read(dev_priv, + EDP_PSR2_CTL(dev_priv, cpu_transcoder)); enabled = val & EDP_PSR2_ENABLE; } else { val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)); diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index a74705aedbb5..785e4f9e7828 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -153,7 +153,7 @@ #define _PSR2_CTL_A 0x60900 #define _PSR2_CTL_EDP 0x6f900 -#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A) +#define EDP_PSR2_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A) #define EDP_PSR2_ENABLE REG_BIT(31) #define EDP_SU_TRACK_ENABLE REG_BIT(30) /* up to adl-p */ #define TGL_EDP_PSR2_BLOCK_COUNT_MASK REG_BIT(28) -- cgit From ccd5bc537b0842a089d158253911cff2c77608c0 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:05 +0300 Subject: drm/i915: pass dev_priv explicitly to PSR_EVENT Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR_EVENT register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/9bc5819afa46416eb8f12ac050ed4d3bcde34b63.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 4 +++- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 156660ab7adf..2dca9957a06b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -415,7 +415,9 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) if (DISPLAY_VER(dev_priv) >= 9) { u32 val; - val = intel_de_rmw(dev_priv, PSR_EVENT(cpu_transcoder), 0, 0); + val = intel_de_rmw(dev_priv, + PSR_EVENT(dev_priv, cpu_transcoder), + 0, 0); psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled); } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 785e4f9e7828..817bc372bf35 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -195,7 +195,7 @@ #define _PSR_EVENT_TRANS_C 0x62848 #define _PSR_EVENT_TRANS_D 0x63848 #define _PSR_EVENT_TRANS_EDP 0x6f848 -#define PSR_EVENT(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A) +#define PSR_EVENT(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A) #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE REG_BIT(17) #define PSR_EVENT_PSR2_DISABLED REG_BIT(16) #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN REG_BIT(15) -- cgit From d82d1a6be60de19486c96777d3322550976bed7d Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:06 +0300 Subject: drm/i915: pass dev_priv explicitly to EDP_PSR2_STATUS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the EDP_PSR2_STATUS register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/5d86a48f51ae6fa4c5a3abf098440a94d07de870.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++---- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 2dca9957a06b..36c08cd3a624 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2052,7 +2052,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) u32 psr_status_mask; if (intel_dp->psr.psr2_enabled) { - psr_status = EDP_PSR2_STATUS(cpu_transcoder); + psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder); psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; } else { psr_status = psr_status_reg(dev_priv, cpu_transcoder); @@ -2768,7 +2768,7 @@ static int _psr2_ready_for_pipe_update_locked(struct intel_dp *intel_dp) * EDP_PSR2_STATUS_STATE_DEEP_SLEEP to be cleared. */ return intel_de_wait_for_clear(dev_priv, - EDP_PSR2_STATUS(cpu_transcoder), + EDP_PSR2_STATUS(dev_priv, cpu_transcoder), EDP_PSR2_STATUS_STATE_DEEP_SLEEP, 50); } @@ -2835,7 +2835,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) return false; if (intel_dp->psr.psr2_enabled) { - reg = EDP_PSR2_STATUS(cpu_transcoder); + reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder); mask = EDP_PSR2_STATUS_STATE_MASK; } else { reg = psr_status_reg(dev_priv, cpu_transcoder); @@ -3467,7 +3467,8 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) "BUF_ON", "TG_ON" }; - val = intel_de_read(dev_priv, EDP_PSR2_STATUS(cpu_transcoder)); + val = intel_de_read(dev_priv, + EDP_PSR2_STATUS(dev_priv, cpu_transcoder)); status_val = REG_FIELD_GET(EDP_PSR2_STATUS_STATE_MASK, val); if (status_val < ARRAY_SIZE(live_status)) status = live_status[status_val]; diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 817bc372bf35..e6c62512512f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -215,7 +215,7 @@ #define _PSR2_STATUS_A 0x60940 #define _PSR2_STATUS_EDP 0x6f940 -#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A) +#define EDP_PSR2_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A) #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) -- cgit From a0d1cfa86cc9e4421e459d471bdd7faa61ee15d9 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 2 May 2024 13:39:25 +0300 Subject: drm/i915: pass dev_priv explicitly to PSR2_SU_STATUS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR2_SU_STATUS register macro. v2: Expand from _PSR2_SU_STATUS to PSR2_SU_STATUS (Rodrigo) Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20240502103925.1829104-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 3 ++- drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 36c08cd3a624..0412a2e1d638 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3569,7 +3569,8 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) * frame boundary between register reads */ for (frame = 0; frame < PSR2_SU_STATUS_FRAMES; frame += 3) { - val = intel_de_read(dev_priv, PSR2_SU_STATUS(cpu_transcoder, frame)); + val = intel_de_read(dev_priv, + PSR2_SU_STATUS(dev_priv, cpu_transcoder, frame)); su_frames_val[frame / 3] = val; } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index e6c62512512f..5504593aa9d0 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -221,8 +221,8 @@ #define _PSR2_SU_STATUS_A 0x60914 #define _PSR2_SU_STATUS_EDP 0x6f914 -#define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4) -#define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) +#define _PSR2_SU_STATUS(dev_priv, tran, index) _MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4) +#define PSR2_SU_STATUS(dev_priv, tran, frame) (_PSR2_SU_STATUS(dev_priv, tran, (frame) / 3)) #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) #define PSR2_SU_STATUS_FRAMES 8 -- cgit From dd17285e94c2462848aa6e60f0e8edc880e9c19f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:08 +0300 Subject: drm/i915: pass dev_priv explicitly to PSR2_MAN_TRK_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PSR2_MAN_TRK_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/72934c8ac3a923ca0c12fc6cdeec1e0b87ecc4a4.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 23 +++++++++++++++-------- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 0412a2e1d638..638f01f0c328 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -844,7 +844,8 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - intel_de_rmw(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), + intel_de_rmw(dev_priv, + PSR2_MAN_TRK_CTL(dev_priv, intel_dp->psr.transcoder), 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, @@ -919,10 +920,12 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) if (intel_dp->psr.psr2_sel_fetch_enabled) { u32 tmp; - tmp = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, + PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder)); drm_WARN_ON(&dev_priv->drm, !(tmp & PSR2_MAN_TRK_CTL_ENABLE)); } else if (HAS_PSR2_SEL_FETCH(dev_priv)) { - intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), 0); + intel_de_write(dev_priv, + PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), 0); } if (psr2_su_region_et_valid(intel_dp)) @@ -1681,7 +1684,8 @@ void intel_psr_get_config(struct intel_encoder *encoder, goto unlock; if (HAS_PSR2_SEL_FETCH(dev_priv)) { - val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder)); + val = intel_de_read(dev_priv, + PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder)); if (val & PSR2_MAN_TRK_CTL_ENABLE) pipe_config->enable_psr2_sel_fetch = true; } @@ -2251,7 +2255,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) if (intel_dp->psr.psr2_sel_fetch_enabled) intel_de_write(dev_priv, - PSR2_MAN_TRK_CTL(cpu_transcoder), + PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), man_trk_ctl_enable_bit_get(dev_priv) | man_trk_ctl_partial_frame_bit_get(dev_priv) | man_trk_ctl_single_full_frame_bit_get(dev_priv) | @@ -2293,7 +2297,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st break; } - intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), + intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), crtc_state->psr2_man_track_ctl); if (!crtc_state->enable_psr2_su_region_et) @@ -3014,7 +3018,9 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp) val = man_trk_ctl_enable_bit_get(dev_priv) | man_trk_ctl_partial_frame_bit_get(dev_priv) | man_trk_ctl_continuos_full_frame(dev_priv); - intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), val); + intel_de_write(dev_priv, + PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), + val); intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); intel_dp->psr.psr2_sel_fetch_cff_enabled = true; } else { @@ -3112,7 +3118,8 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) * SU configuration in case update is sent for any reason after * sff bit gets cleared by the HW on next vblank. */ - intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder), + intel_de_write(dev_priv, + PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), val); intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); intel_dp->psr.psr2_sel_fetch_cff_enabled = false; diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 5504593aa9d0..db990f30f0d5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -229,7 +229,7 @@ #define _PSR2_MAN_TRK_CTL_A 0x60910 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 -#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A) +#define PSR2_MAN_TRK_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A) #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) -- cgit From db92d423dc360ba957314e3c87ae67108216a6da Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:09 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_SRCSZ_ERLY_TPT Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_SRCSZ_ERLY_TPT register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/b37217f55702fc10190c2c5aded7d845a36766f6.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 23a122ee20c9..2118b87ccb10 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane, intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl); - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe), + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe), PIPESRC_HEIGHT(et_y_position)); } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 638f01f0c328..e3221cd5bf57 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2303,7 +2303,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st if (!crtc_state->enable_psr2_su_region_et) return; - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe), crtc_state->pipe_srcsz_early_tpt); } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index db990f30f0d5..a10cf5120efb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -249,7 +249,7 @@ /* PSR2 Early transport */ #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074 -#define PIPE_SRCSZ_ERLY_TPT(trans) _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A) +#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A) #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 -- cgit From 13b77ac5dc91a8aaac23d8be3a9a9d4c9a2dd4cf Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:10 +0300 Subject: drm/i915: pass dev_priv explicitly to ALPM_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ALPM_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/96da9be36dc93fa9a7c329f25ff963e4998998c1.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 4 ++-- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index e3221cd5bf57..e59de8500d83 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1812,7 +1812,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines); - intel_de_write(dev_priv, ALPM_CTL(cpu_transcoder), alpm_ctl); + intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl); } static void intel_psr_enable_source(struct intel_dp *intel_dp, @@ -2112,7 +2112,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) /* Panel Replay on eDP is always using ALPM aux less. */ if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { - intel_de_rmw(dev_priv, ALPM_CTL(cpu_transcoder), + intel_de_rmw(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), ALPM_CTL_ALPM_ENABLE | ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index a10cf5120efb..8d7f8408ef8e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -297,7 +297,7 @@ _SEL_FETCH_PLANE_BASE_1_A) #define _ALPM_CTL_A 0x60950 -#define ALPM_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A) +#define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A) #define ALPM_CTL_ALPM_ENABLE REG_BIT(31) #define ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(30) #define ALPM_CTL_LOBF_ENABLE REG_BIT(29) -- cgit From 94e760584a277d4fe683937a737ca2bec6e42f17 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:11 +0300 Subject: FIXME drm/i915: pass dev_priv explicitly to ALPM_CTL2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ALPM_CTL2 register macro. Reviewed-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/09acf2751cfd2f524e6ba97c3ac285495eae5c86.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 8d7f8408ef8e..bdfe3c596690 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -321,7 +321,7 @@ #define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) #define _ALPM_CTL2_A 0x60954 -#define ALPM_CTL2(tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A) +#define ALPM_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A) #define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, 24) #define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val) #define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, 16) -- cgit From 7f4eae0a9439225837c1a5d96439abfcaf1db54f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:12 +0300 Subject: drm/i915: pass dev_priv explicitly to PORT_ALPM_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_ALPM_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/86e8f5649c822ff6fa0502ad88964bfcb269c6c5.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index e59de8500d83..b93953a00deb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1790,7 +1790,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) ALPM_CTL_ALPM_AUX_LESS_ENABLE | ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS; - intel_de_write(dev_priv, PORT_ALPM_CTL(cpu_transcoder), + intel_de_write(dev_priv, + PORT_ALPM_CTL(dev_priv, cpu_transcoder), PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | @@ -2116,7 +2117,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) ALPM_CTL_ALPM_ENABLE | ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); - intel_de_rmw(dev_priv, PORT_ALPM_CTL(cpu_transcoder), + intel_de_rmw(dev_priv, + PORT_ALPM_CTL(dev_priv, cpu_transcoder), PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE, 0); } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index bdfe3c596690..eea6abe0ecfa 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -335,7 +335,7 @@ #define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) #define _PORT_ALPM_CTL_A 0x16fa2c -#define PORT_ALPM_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A) +#define PORT_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A) #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) -- cgit From accd3e041e8fe510e957513b419bac1cada04e21 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 30 Apr 2024 13:10:13 +0300 Subject: drm/i915: pass dev_priv explicitly to PORT_ALPM_LFPS_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_ALPM_LFPS_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/f8a3bbade94258852b8129c5f5918fb06ceab54b.1714471597.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 3 ++- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b93953a00deb..595eb1b3b6c6 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1798,7 +1798,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) PORT_ALPM_CTL_SILENCE_PERIOD( psr->alpm_parameters.silence_period_sym_clocks)); - intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(cpu_transcoder), + intel_de_write(dev_priv, + PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder), PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( psr->alpm_parameters.lfps_half_cycle_num_of_syms) | diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index eea6abe0ecfa..e14cb48f2614 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -345,7 +345,7 @@ #define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val) #define _PORT_ALPM_LFPS_CTL_A 0x16fa30 -#define PORT_ALPM_LFPS_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A) +#define PORT_ALPM_LFPS_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A) #define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31) #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24) #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7 -- cgit From c286f6a973c66c0d993ecab9f7162c790e7064c8 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 21 Feb 2024 18:06:24 -0700 Subject: drm/i915/bios: Fix parsing backlight BDB data MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Starting BDB version 239, hdr_dpcd_refresh_timeout is introduced to backlight BDB data. Commit 700034566d68 ("drm/i915/bios: Define more BDB contents") updated the backlight BDB data accordingly. This broke the parsing of backlight BDB data in VBT for versions 236 - 238 (both inclusive) and hence the backlight controls are not responding on units with the concerned BDB version. backlight_control information has been present in backlight BDB data from at least BDB version 191 onwards, if not before. Hence this patch extracts the backlight_control information for BDB version 191 or newer. Tested on Chromebooks using Jasperlake SoC (reports bdb->version = 236). Tested on Chromebooks using Raptorlake SoC (reports bdb->version = 251). v2: removed checking the block size of the backlight BDB data [vsyrjala: this is completely safe thanks to commit e163cfb4c96d ("drm/i915/bios: Make copies of VBT data blocks")] Fixes: 700034566d68 ("drm/i915/bios: Define more BDB contents") Cc: stable@vger.kernel.org Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: Karthikeyan Ramasubramanian Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240221180622.v2.1.I0690aa3e96a83a43b3fc33f50395d334b2981826@changeid Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_bios.c | 19 ++++--------------- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 5 ----- 2 files changed, 4 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index cf770c866d13..e193782bfce9 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1037,22 +1037,11 @@ parse_lfp_backlight(struct drm_i915_private *i915, panel->vbt.backlight.type = INTEL_BACKLIGHT_DISPLAY_DDI; panel->vbt.backlight.controller = 0; if (i915->display.vbt.version >= 191) { - size_t exp_size; + const struct lfp_backlight_control_method *method; - if (i915->display.vbt.version >= 236) - exp_size = sizeof(struct bdb_lfp_backlight_data); - else if (i915->display.vbt.version >= 234) - exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_234; - else - exp_size = EXP_BDB_LFP_BL_DATA_SIZE_REV_191; - - if (get_blocksize(backlight_data) >= exp_size) { - const struct lfp_backlight_control_method *method; - - method = &backlight_data->backlight_control[panel_type]; - panel->vbt.backlight.type = method->type; - panel->vbt.backlight.controller = method->controller; - } + method = &backlight_data->backlight_control[panel_type]; + panel->vbt.backlight.type = method->type; + panel->vbt.backlight.controller = method->controller; } panel->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 3815aa21d19f..228702c0e492 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -899,11 +899,6 @@ struct lfp_brightness_level { u16 reserved; } __packed; -#define EXP_BDB_LFP_BL_DATA_SIZE_REV_191 \ - offsetof(struct bdb_lfp_backlight_data, brightness_level) -#define EXP_BDB_LFP_BL_DATA_SIZE_REV_234 \ - offsetof(struct bdb_lfp_backlight_data, brightness_precision_bits) - struct bdb_lfp_backlight_data { u8 entry_size; struct lfp_backlight_data_entry data[16]; -- cgit From 6dd2bd94d2ef82a356c6580e3f59d93208ac4755 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 6 May 2024 13:09:02 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_CRC_CTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_CTL register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/2ac4438aa885be9d0fcf5c697beee99a4cd2c23f.1714990089.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pipe_crc.c | 12 ++++++------ drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 5a468ed6e26c..35c3dd1130ce 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -608,8 +608,8 @@ int intel_crtc_set_crc_source(struct drm_crtc *_crtc, const char *source_name) goto out; pipe_crc->source = source; - intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val); - intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); + intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val); + intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); if (!source) { if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) @@ -643,8 +643,8 @@ void intel_crtc_enable_pipe_crc(struct intel_crtc *crtc) /* Don't need pipe_crc->lock here, IRQs are not generated. */ pipe_crc->skipped = 0; - intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), val); - intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); + intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), val); + intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); } void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) @@ -658,7 +658,7 @@ void intel_crtc_disable_pipe_crc(struct intel_crtc *crtc) pipe_crc->skipped = INT_MIN; spin_unlock_irq(&pipe_crc->lock); - intel_de_write(dev_priv, PIPE_CRC_CTL(pipe), 0); - intel_de_posting_read(dev_priv, PIPE_CRC_CTL(pipe)); + intel_de_write(dev_priv, PIPE_CRC_CTL(dev_priv, pipe), 0); + intel_de_posting_read(dev_priv, PIPE_CRC_CTL(dev_priv, pipe)); intel_synchronize_irq(dev_priv); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ae692f461982..4525afafc79f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1137,7 +1137,7 @@ #define _PIPE_CRC_RES_4_B_IVB 0x61070 #define _PIPE_CRC_RES_5_B_IVB 0x61074 -#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) +#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) -- cgit From 19e74ba7f894f5e95c1c56ebcdbe1fdfcf20b9c4 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 6 May 2024 13:09:03 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_CRC_* MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_CRC_RES_* register macros. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/849315d4417a2ce60e867648d9a040c5e96bc22d.1714990089.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 24 +++++++++++++----------- drivers/gpu/drm/i915/i915_reg.h | 22 +++++++++++----------- 2 files changed, 24 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index c41f058acaff..1674570dff1e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -356,7 +356,7 @@ static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)), 0, 0, 0, 0); } @@ -364,11 +364,11 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(dev_priv, pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(dev_priv, pipe))); } static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, @@ -377,19 +377,21 @@ static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, u32 res1, res2; if (DISPLAY_VER(dev_priv) >= 3) - res1 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES1_I915(pipe)); + res1 = intel_uncore_read(&dev_priv->uncore, + PIPE_CRC_RES_RES1_I915(dev_priv, pipe)); else res1 = 0; if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) - res2 = intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RES2_G4X(pipe)); + res2 = intel_uncore_read(&dev_priv->uncore, + PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)); else res2 = 0; display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_RED(dev_priv, pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_GREEN(dev_priv, pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_BLUE(dev_priv, pipe)), res1, res2); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4525afafc79f..4a88eb9cd1f8 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1138,17 +1138,17 @@ #define _PIPE_CRC_RES_5_B_IVB 0x61074 #define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) -#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) -#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) -#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) -#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) -#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) - -#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) -#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) -#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) -#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) -#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) +#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) +#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) +#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) +#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) +#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) + +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) +#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) /* Pipe/transcoder A timing regs */ #define _TRANS_HTOTAL_A 0x60000 -- cgit From c06387ab4472fc5af857d02323fc1073ff7923e0 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 6 May 2024 13:09:04 +0300 Subject: drm/i915: pass dev_priv explicitly to PORT_DFT2_G4X MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_DFT2_G4X register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/0db8ee7b66b9660fc9fd80598257c6d36f0f506b.1714990089.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pipe_crc.c | 8 ++++---- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index 35c3dd1130ce..b3dcfee6ec0e 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -167,7 +167,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, * - DisplayPort scrambling: used for EMI reduction */ if (need_stable_symbols) { - u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X); + u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); tmp |= DC_BALANCE_RESET_VLV; switch (pipe) { @@ -183,7 +183,7 @@ static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, default: return -EINVAL; } - intel_de_write(dev_priv, PORT_DFT2_G4X, tmp); + intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); } return 0; @@ -229,7 +229,7 @@ static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, enum pipe pipe) { - u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X); + u32 tmp = intel_de_read(dev_priv, PORT_DFT2_G4X(dev_priv)); switch (pipe) { case PIPE_A: @@ -246,7 +246,7 @@ static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, } if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) tmp &= ~DC_BALANCE_RESET_VLV; - intel_de_write(dev_priv, PORT_DFT2_G4X, tmp); + intel_de_write(dev_priv, PORT_DFT2_G4X(dev_priv), tmp); } static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4a88eb9cd1f8..5670eee4a498 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1479,7 +1479,7 @@ #define PORT_DFT_I9XX _MMIO(0x61150) #define DC_BALANCE_RESET (1 << 25) -#define PORT_DFT2_G4X _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) +#define PORT_DFT2_G4X(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61154) #define DC_BALANCE_RESET_VLV (1 << 31) #define PIPE_SCRAMBLE_RESET_MASK ((1 << 14) | (0x3 << 0)) #define PIPE_C_SCRAMBLE_RESET REG_BIT(14) /* chv */ -- cgit From 7043141fbbbecfa1d26c538d502649079fe6e095 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:15 +0300 Subject: drm/i915/bios: Define eDP DSC disable bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There's a new "DSC disable" bit in the eDP VBT block. Define it. TODO: actually use it? Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 228702c0e492..09cb2ba26880 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -749,6 +749,7 @@ struct bdb_edp { struct edp_apical_params apical_params[16]; /* 203+ */ u16 edp_fast_link_training_rate[16]; /* 224+ */ u16 edp_max_port_link_rate[16]; /* 244+ */ + u16 edp_dsc_disable; /* 251+ */ } __packed; /* -- cgit From d9981f36e4f372bbf03af7a9c1f3bfdd79440589 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:16 +0300 Subject: drm/i915/bios: Remove version number comment from DEVICE_HANDLE_EFP4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DEVICE_HANDLE_EFP4 has actually been in use since the very beginning, or at least something has been occupying that bit because old VBTs actually use it, and it definitely looks to be about external displays given how its used. So let's ignore what the current spec claims and remove the misleading version number comment. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-3-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 09cb2ba26880..6600a8cf8464 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -201,7 +201,7 @@ struct bdb_general_features { #define DEVICE_HANDLE_EFP1 0x0004 #define DEVICE_HANDLE_EFP2 0x0040 #define DEVICE_HANDLE_EFP3 0x0020 -#define DEVICE_HANDLE_EFP4 0x0010 /* 194+ */ +#define DEVICE_HANDLE_EFP4 0x0010 #define DEVICE_HANDLE_EFP5 0x0002 /* 215+ */ #define DEVICE_HANDLE_EFP6 0x0001 /* 217+ */ #define DEVICE_HANDLE_EFP7 0x0100 /* 217+ */ -- cgit From 7234f948b58b04b11ec7d32c1d358887f9e700e6 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:17 +0300 Subject: drm/i915/bios: Indicate which VBT structures are based on EDID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit VBT reuses a bunch of EDID data structures. Flag those as such for clarity. I chose "bdb_edid_" as the namespace for these. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 28 ++++---- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 95 ++++++++++++++------------- 2 files changed, 62 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index e193782bfce9..47422f8dc235 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -242,13 +242,13 @@ static bool validate_lfp_data_ptrs(const void *bdb, /* fp_timing has variable size */ if (fp_timing_size < 32 || - dvo_timing_size != sizeof(struct lvds_dvo_timing) || - panel_pnp_id_size != sizeof(struct lvds_pnp_id)) + dvo_timing_size != sizeof(struct bdb_edid_dtd) || + panel_pnp_id_size != sizeof(struct bdb_edid_pnp_id)) return false; /* panel_name is not present in old VBTs */ if (panel_name_size != 0 && - panel_name_size != sizeof(struct lvds_lfp_panel_name)) + panel_name_size != sizeof(struct bdb_edid_product_name)) return false; lfp_data_size = ptrs->ptr[1].fp_timing.offset - ptrs->ptr[0].fp_timing.offset; @@ -385,8 +385,8 @@ static void *generate_lfp_data_ptrs(struct drm_i915_private *i915, block_size = get_blocksize(block); - size = fp_timing_size + sizeof(struct lvds_dvo_timing) + - sizeof(struct lvds_pnp_id); + size = fp_timing_size + sizeof(struct bdb_edid_dtd) + + sizeof(struct bdb_edid_pnp_id); if (size * 16 > block_size) return NULL; @@ -398,10 +398,10 @@ static void *generate_lfp_data_ptrs(struct drm_i915_private *i915, *(u16 *)(ptrs_block + 1) = sizeof(*ptrs); ptrs = ptrs_block + 3; - table_size = sizeof(struct lvds_pnp_id); + table_size = sizeof(struct bdb_edid_pnp_id); size = make_lfp_data_ptr(&ptrs->ptr[0].panel_pnp_id, table_size, size); - table_size = sizeof(struct lvds_dvo_timing); + table_size = sizeof(struct bdb_edid_dtd); size = make_lfp_data_ptr(&ptrs->ptr[0].dvo_timing, table_size, size); table_size = fp_timing_size; @@ -419,15 +419,15 @@ static void *generate_lfp_data_ptrs(struct drm_i915_private *i915, return NULL; } - size = fp_timing_size + sizeof(struct lvds_dvo_timing) + - sizeof(struct lvds_pnp_id); + size = fp_timing_size + sizeof(struct bdb_edid_dtd) + + sizeof(struct bdb_edid_pnp_id); for (i = 1; i < 16; i++) { next_lfp_data_ptr(&ptrs->ptr[i].fp_timing, &ptrs->ptr[i-1].fp_timing, size); next_lfp_data_ptr(&ptrs->ptr[i].dvo_timing, &ptrs->ptr[i-1].dvo_timing, size); next_lfp_data_ptr(&ptrs->ptr[i].panel_pnp_id, &ptrs->ptr[i-1].panel_pnp_id, size); } - table_size = sizeof(struct lvds_lfp_panel_name); + table_size = sizeof(struct bdb_edid_product_name); if (16 * (size + table_size) <= block_size) { ptrs->panel_name.table_size = table_size; @@ -525,7 +525,7 @@ static void init_bdb_blocks(struct drm_i915_private *i915, static void fill_detail_timing_data(struct drm_i915_private *i915, struct drm_display_mode *panel_fixed_mode, - const struct lvds_dvo_timing *dvo_timing) + const struct bdb_edid_dtd *dvo_timing) { panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) | dvo_timing->hactive_lo; @@ -579,7 +579,7 @@ fill_detail_timing_data(struct drm_i915_private *i915, drm_mode_set_name(panel_fixed_mode); } -static const struct lvds_dvo_timing * +static const struct bdb_edid_dtd * get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *data, const struct bdb_lvds_lfp_data_ptrs *ptrs, int index) @@ -601,7 +601,7 @@ get_lvds_pnp_id(const struct bdb_lvds_lfp_data *data, int index) { /* These two are supposed to have the same layout in memory. */ - BUILD_BUG_ON(sizeof(struct lvds_pnp_id) != sizeof(struct drm_edid_product_id)); + BUILD_BUG_ON(sizeof(struct bdb_edid_pnp_id) != sizeof(struct drm_edid_product_id)); return (const void *)data + ptrs->ptr[index].panel_pnp_id.offset; } @@ -835,7 +835,7 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915, const struct bdb_lvds_lfp_data *lvds_lfp_data, const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs) { - const struct lvds_dvo_timing *panel_dvo_timing; + const struct bdb_edid_dtd *panel_dvo_timing; const struct lvds_fp_timing *fp_timing; struct drm_display_mode *panel_fixed_mode; int panel_type = panel->vbt.panel_type; diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 6600a8cf8464..32a6cd01cfbe 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -39,6 +39,50 @@ #include "intel_bios.h" +/* EDID derived structures */ +struct bdb_edid_pnp_id { + u16 mfg_name; + u16 product_code; + u32 serial; + u8 mfg_week; + u8 mfg_year; +} __packed; + +struct bdb_edid_product_name { + char name[13]; +} __packed; + +struct bdb_edid_dtd { + u16 clock; /**< In 10khz */ + u8 hactive_lo; + u8 hblank_lo; + u8 hblank_hi:4; + u8 hactive_hi:4; + u8 vactive_lo; + u8 vblank_lo; + u8 vblank_hi:4; + u8 vactive_hi:4; + u8 hsync_off_lo; + u8 hsync_pulse_width_lo; + u8 vsync_pulse_width_lo:4; + u8 vsync_off_lo:4; + u8 vsync_pulse_width_hi:2; + u8 vsync_off_hi:2; + u8 hsync_pulse_width_hi:2; + u8 hsync_off_hi:2; + u8 himage_lo; + u8 vimage_lo; + u8 vimage_hi:4; + u8 himage_hi:4; + u8 h_border; + u8 v_border; + u8 rsvd1:3; + u8 digital:2; + u8 vsync_positive:1; + u8 hsync_positive:1; + u8 non_interlaced:1; +} __packed; + /** * struct vbt_header - VBT Header structure * @signature: VBT signature, always starts with "$VBT" @@ -645,39 +689,8 @@ struct bdb_sdvo_lvds_options { * Block 23 - SDVO LVDS Panel DTDs */ -struct lvds_dvo_timing { - u16 clock; /**< In 10khz */ - u8 hactive_lo; - u8 hblank_lo; - u8 hblank_hi:4; - u8 hactive_hi:4; - u8 vactive_lo; - u8 vblank_lo; - u8 vblank_hi:4; - u8 vactive_hi:4; - u8 hsync_off_lo; - u8 hsync_pulse_width_lo; - u8 vsync_pulse_width_lo:4; - u8 vsync_off_lo:4; - u8 vsync_pulse_width_hi:2; - u8 vsync_off_hi:2; - u8 hsync_pulse_width_hi:2; - u8 hsync_off_hi:2; - u8 himage_lo; - u8 vimage_lo; - u8 vimage_hi:4; - u8 himage_hi:4; - u8 h_border; - u8 v_border; - u8 rsvd1:3; - u8 digital:2; - u8 vsync_positive:1; - u8 hsync_positive:1; - u8 non_interlaced:1; -} __packed; - struct bdb_sdvo_panel_dtds { - struct lvds_dvo_timing dtds[4]; + struct bdb_edid_dtd dtds[4]; } __packed; /* @@ -828,14 +841,6 @@ struct lvds_fp_timing { u16 terminator; } __packed; -struct lvds_pnp_id { - u16 mfg_name; - u16 product_code; - u32 serial; - u8 mfg_week; - u8 mfg_year; -} __packed; - /* * For reference only. fp_timing has variable size so * the data must be accessed using the data table pointers. @@ -843,18 +848,14 @@ struct lvds_pnp_id { */ struct lvds_lfp_data_entry { struct lvds_fp_timing fp_timing; - struct lvds_dvo_timing dvo_timing; - struct lvds_pnp_id pnp_id; + struct bdb_edid_dtd dvo_timing; + struct bdb_edid_pnp_id pnp_id; } __packed; struct bdb_lvds_lfp_data { struct lvds_lfp_data_entry data[16]; } __packed; -struct lvds_lfp_panel_name { - u8 name[13]; -} __packed; - struct lvds_lfp_black_border { u8 top; /* 227+ */ u8 bottom; /* 227+ */ @@ -863,7 +864,7 @@ struct lvds_lfp_black_border { } __packed; struct bdb_lvds_lfp_data_tail { - struct lvds_lfp_panel_name panel_name[16]; /* (156-163?)+ */ + struct bdb_edid_product_name panel_name[16]; /* (156-163?)+ */ u16 scaling_enable; /* 187+ */ u8 seamless_drrs_min_refresh_rate[16]; /* 188+ */ u8 pixel_overlap_count[16]; /* 208+ */ -- cgit From 6ac67ccf4c898ff29ffba4cb4b6213deae05c8fb Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:18 +0300 Subject: drm/i915/bios: Get rid of "LVDS" from all LFP data stuff MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The LFP data applies to all kinds of display interfaces, so stop calling things by the "LVDS" name. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 170 ++++++++++----------- drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 2 +- drivers/gpu/drm/i915/display/intel_panel.c | 2 +- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 46 +++--- 5 files changed, 111 insertions(+), 111 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 47422f8dc235..060dd7d2eebe 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -174,18 +174,18 @@ static const struct { .min_size = sizeof(struct bdb_sdvo_panel_dtds), }, { .section_id = BDB_EDP, .min_size = sizeof(struct bdb_edp), }, - { .section_id = BDB_LVDS_OPTIONS, - .min_size = sizeof(struct bdb_lvds_options), }, + { .section_id = BDB_LFP_OPTIONS, + .min_size = sizeof(struct bdb_lfp_options), }, /* - * BDB_LVDS_LFP_DATA depends on BDB_LVDS_LFP_DATA_PTRS, + * BDB_LFP_DATA depends on BDB_LFP_DATA_PTRS, * so keep the two ordered. */ - { .section_id = BDB_LVDS_LFP_DATA_PTRS, - .min_size = sizeof(struct bdb_lvds_lfp_data_ptrs), }, - { .section_id = BDB_LVDS_LFP_DATA, + { .section_id = BDB_LFP_DATA_PTRS, + .min_size = sizeof(struct bdb_lfp_data_ptrs), }, + { .section_id = BDB_LFP_DATA, .min_size = 0, /* special case */ }, - { .section_id = BDB_LVDS_BACKLIGHT, - .min_size = sizeof(struct bdb_lfp_backlight_data), }, + { .section_id = BDB_LFP_BACKLIGHT, + .min_size = sizeof(struct bdb_lfp_backlight), }, { .section_id = BDB_LFP_POWER, .min_size = sizeof(struct bdb_lfp_power), }, { .section_id = BDB_MIPI_CONFIG, @@ -200,30 +200,30 @@ static const struct { static size_t lfp_data_min_size(struct drm_i915_private *i915) { - const struct bdb_lvds_lfp_data_ptrs *ptrs; + const struct bdb_lfp_data_ptrs *ptrs; size_t size; - ptrs = bdb_find_section(i915, BDB_LVDS_LFP_DATA_PTRS); + ptrs = bdb_find_section(i915, BDB_LFP_DATA_PTRS); if (!ptrs) return 0; - size = sizeof(struct bdb_lvds_lfp_data); + size = sizeof(struct bdb_lfp_data); if (ptrs->panel_name.table_size) size = max(size, ptrs->panel_name.offset + - sizeof(struct bdb_lvds_lfp_data_tail)); + sizeof(struct bdb_lfp_data_tail)); return size; } static bool validate_lfp_data_ptrs(const void *bdb, - const struct bdb_lvds_lfp_data_ptrs *ptrs) + const struct bdb_lfp_data_ptrs *ptrs) { int fp_timing_size, dvo_timing_size, panel_pnp_id_size, panel_name_size; int data_block_size, lfp_data_size; const void *data_block; int i; - data_block = find_raw_section(bdb, BDB_LVDS_LFP_DATA); + data_block = find_raw_section(bdb, BDB_LFP_DATA); if (!data_block) return false; @@ -232,7 +232,7 @@ static bool validate_lfp_data_ptrs(const void *bdb, return false; /* always 3 indicating the presence of fp_timing+dvo_timing+panel_pnp_id */ - if (ptrs->lvds_entries != 3) + if (ptrs->num_entries != 3) return false; fp_timing_size = ptrs->ptr[0].fp_timing.table_size; @@ -311,11 +311,11 @@ static bool validate_lfp_data_ptrs(const void *bdb, /* make the data table offsets relative to the data block */ static bool fixup_lfp_data_ptrs(const void *bdb, void *ptrs_block) { - struct bdb_lvds_lfp_data_ptrs *ptrs = ptrs_block; + struct bdb_lfp_data_ptrs *ptrs = ptrs_block; u32 offset; int i; - offset = raw_block_offset(bdb, BDB_LVDS_LFP_DATA); + offset = raw_block_offset(bdb, BDB_LFP_DATA); for (i = 0; i < 16; i++) { if (ptrs->ptr[i].fp_timing.offset < offset || @@ -338,7 +338,7 @@ static bool fixup_lfp_data_ptrs(const void *bdb, void *ptrs_block) return validate_lfp_data_ptrs(bdb, ptrs); } -static int make_lfp_data_ptr(struct lvds_lfp_data_ptr_table *table, +static int make_lfp_data_ptr(struct lfp_data_ptr_table *table, int table_size, int total_size) { if (total_size < table_size) @@ -350,8 +350,8 @@ static int make_lfp_data_ptr(struct lvds_lfp_data_ptr_table *table, return total_size - table_size; } -static void next_lfp_data_ptr(struct lvds_lfp_data_ptr_table *next, - const struct lvds_lfp_data_ptr_table *prev, +static void next_lfp_data_ptr(struct lfp_data_ptr_table *next, + const struct lfp_data_ptr_table *prev, int size) { next->table_size = prev->table_size; @@ -362,7 +362,7 @@ static void *generate_lfp_data_ptrs(struct drm_i915_private *i915, const void *bdb) { int i, size, table_size, block_size, offset, fp_timing_size; - struct bdb_lvds_lfp_data_ptrs *ptrs; + struct bdb_lfp_data_ptrs *ptrs; const void *block; void *ptrs_block; @@ -377,7 +377,7 @@ static void *generate_lfp_data_ptrs(struct drm_i915_private *i915, fp_timing_size = 38; - block = find_raw_section(bdb, BDB_LVDS_LFP_DATA); + block = find_raw_section(bdb, BDB_LFP_DATA); if (!block) return NULL; @@ -394,7 +394,7 @@ static void *generate_lfp_data_ptrs(struct drm_i915_private *i915, if (!ptrs_block) return NULL; - *(u8 *)(ptrs_block + 0) = BDB_LVDS_LFP_DATA_PTRS; + *(u8 *)(ptrs_block + 0) = BDB_LFP_DATA_PTRS; *(u16 *)(ptrs_block + 1) = sizeof(*ptrs); ptrs = ptrs_block + 3; @@ -408,13 +408,13 @@ static void *generate_lfp_data_ptrs(struct drm_i915_private *i915, size = make_lfp_data_ptr(&ptrs->ptr[0].fp_timing, table_size, size); if (ptrs->ptr[0].fp_timing.table_size) - ptrs->lvds_entries++; + ptrs->num_entries++; if (ptrs->ptr[0].dvo_timing.table_size) - ptrs->lvds_entries++; + ptrs->num_entries++; if (ptrs->ptr[0].panel_pnp_id.table_size) - ptrs->lvds_entries++; + ptrs->num_entries++; - if (size != 0 || ptrs->lvds_entries != 3) { + if (size != 0 || ptrs->num_entries != 3) { kfree(ptrs_block); return NULL; } @@ -461,7 +461,7 @@ init_bdb_block(struct drm_i915_private *i915, block = find_raw_section(bdb, section_id); /* Modern VBTs lack the LFP data table pointers block, make one up */ - if (!block && section_id == BDB_LVDS_LFP_DATA_PTRS) { + if (!block && section_id == BDB_LFP_DATA_PTRS) { temp_block = generate_lfp_data_ptrs(i915, bdb); if (temp_block) block = temp_block + 3; @@ -496,7 +496,7 @@ init_bdb_block(struct drm_i915_private *i915, drm_dbg_kms(&i915->drm, "Found BDB block %d (size %zu, min size %zu)\n", section_id, block_size, min_size); - if (section_id == BDB_LVDS_LFP_DATA_PTRS && + if (section_id == BDB_LFP_DATA_PTRS && !fixup_lfp_data_ptrs(bdb, entry->data + 3)) { drm_err(&i915->drm, "VBT has malformed LFP data table pointers\n"); kfree(entry); @@ -515,7 +515,7 @@ static void init_bdb_blocks(struct drm_i915_private *i915, enum bdb_block_id section_id = bdb_blocks[i].section_id; size_t min_size = bdb_blocks[i].min_size; - if (section_id == BDB_LVDS_LFP_DATA) + if (section_id == BDB_LFP_DATA) min_size = lfp_data_min_size(i915); init_bdb_block(i915, bdb, section_id, min_size); @@ -580,25 +580,25 @@ fill_detail_timing_data(struct drm_i915_private *i915, } static const struct bdb_edid_dtd * -get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *data, - const struct bdb_lvds_lfp_data_ptrs *ptrs, - int index) +get_lfp_dvo_timing(const struct bdb_lfp_data *data, + const struct bdb_lfp_data_ptrs *ptrs, + int index) { return (const void *)data + ptrs->ptr[index].dvo_timing.offset; } -static const struct lvds_fp_timing * -get_lvds_fp_timing(const struct bdb_lvds_lfp_data *data, - const struct bdb_lvds_lfp_data_ptrs *ptrs, - int index) +static const struct fp_timing * +get_lfp_fp_timing(const struct bdb_lfp_data *data, + const struct bdb_lfp_data_ptrs *ptrs, + int index) { return (const void *)data + ptrs->ptr[index].fp_timing.offset; } static const struct drm_edid_product_id * -get_lvds_pnp_id(const struct bdb_lvds_lfp_data *data, - const struct bdb_lvds_lfp_data_ptrs *ptrs, - int index) +get_lfp_pnp_id(const struct bdb_lfp_data *data, + const struct bdb_lfp_data_ptrs *ptrs, + int index) { /* These two are supposed to have the same layout in memory. */ BUILD_BUG_ON(sizeof(struct bdb_edid_pnp_id) != sizeof(struct drm_edid_product_id)); @@ -606,9 +606,9 @@ get_lvds_pnp_id(const struct bdb_lvds_lfp_data *data, return (const void *)data + ptrs->ptr[index].panel_pnp_id.offset; } -static const struct bdb_lvds_lfp_data_tail * -get_lfp_data_tail(const struct bdb_lvds_lfp_data *data, - const struct bdb_lvds_lfp_data_ptrs *ptrs) +static const struct bdb_lfp_data_tail * +get_lfp_data_tail(const struct bdb_lfp_data *data, + const struct bdb_lfp_data_ptrs *ptrs) { if (ptrs->panel_name.table_size) return (const void *)data + ptrs->panel_name.offset; @@ -627,33 +627,33 @@ static int vbt_get_panel_type(struct drm_i915_private *i915, const struct intel_bios_encoder_data *devdata, const struct drm_edid *drm_edid, bool use_fallback) { - const struct bdb_lvds_options *lvds_options; + const struct bdb_lfp_options *lfp_options; - lvds_options = bdb_find_section(i915, BDB_LVDS_OPTIONS); - if (!lvds_options) + lfp_options = bdb_find_section(i915, BDB_LFP_OPTIONS); + if (!lfp_options) return -1; - if (lvds_options->panel_type > 0xf && - lvds_options->panel_type != 0xff) { + if (lfp_options->panel_type > 0xf && + lfp_options->panel_type != 0xff) { drm_dbg_kms(&i915->drm, "Invalid VBT panel type 0x%x\n", - lvds_options->panel_type); + lfp_options->panel_type); return -1; } if (devdata && devdata->child.handle == DEVICE_HANDLE_LFP2) - return lvds_options->panel_type2; + return lfp_options->panel_type2; drm_WARN_ON(&i915->drm, devdata && devdata->child.handle != DEVICE_HANDLE_LFP1); - return lvds_options->panel_type; + return lfp_options->panel_type; } static int pnpid_get_panel_type(struct drm_i915_private *i915, const struct intel_bios_encoder_data *devdata, const struct drm_edid *drm_edid, bool use_fallback) { - const struct bdb_lvds_lfp_data *data; - const struct bdb_lvds_lfp_data_ptrs *ptrs; + const struct bdb_lfp_data *data; + const struct bdb_lfp_data_ptrs *ptrs; struct drm_edid_product_id product_id, product_id_nodate; struct drm_printer p; int i, best = -1; @@ -670,17 +670,17 @@ static int pnpid_get_panel_type(struct drm_i915_private *i915, p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, "EDID"); drm_edid_print_product_id(&p, &product_id, true); - ptrs = bdb_find_section(i915, BDB_LVDS_LFP_DATA_PTRS); + ptrs = bdb_find_section(i915, BDB_LFP_DATA_PTRS); if (!ptrs) return -1; - data = bdb_find_section(i915, BDB_LVDS_LFP_DATA); + data = bdb_find_section(i915, BDB_LFP_DATA); if (!data) return -1; for (i = 0; i < 16; i++) { const struct drm_edid_product_id *vbt_id = - get_lvds_pnp_id(data, ptrs, i); + get_lfp_pnp_id(data, ptrs, i); /* full match? */ if (!memcmp(vbt_id, &product_id, sizeof(*vbt_id))) @@ -786,25 +786,25 @@ static void parse_panel_options(struct drm_i915_private *i915, struct intel_panel *panel) { - const struct bdb_lvds_options *lvds_options; + const struct bdb_lfp_options *lfp_options; int panel_type = panel->vbt.panel_type; int drrs_mode; - lvds_options = bdb_find_section(i915, BDB_LVDS_OPTIONS); - if (!lvds_options) + lfp_options = bdb_find_section(i915, BDB_LFP_OPTIONS); + if (!lfp_options) return; - panel->vbt.lvds_dither = lvds_options->pixel_dither; + panel->vbt.lvds_dither = lfp_options->pixel_dither; /* * Empirical evidence indicates the block size can be * either 4,14,16,24+ bytes. For older VBTs no clear * relationship between the block size vs. BDB version. */ - if (get_blocksize(lvds_options) < 16) + if (get_blocksize(lfp_options) < 16) return; - drrs_mode = panel_bits(lvds_options->dps_panel_type_bits, + drrs_mode = panel_bits(lfp_options->dps_panel_type_bits, panel_type, 2); /* * VBT has static DRRS = 0 and seamless DRRS = 2. @@ -832,17 +832,17 @@ parse_panel_options(struct drm_i915_private *i915, static void parse_lfp_panel_dtd(struct drm_i915_private *i915, struct intel_panel *panel, - const struct bdb_lvds_lfp_data *lvds_lfp_data, - const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs) + const struct bdb_lfp_data *lfp_data, + const struct bdb_lfp_data_ptrs *lfp_data_ptrs) { const struct bdb_edid_dtd *panel_dvo_timing; - const struct lvds_fp_timing *fp_timing; + const struct fp_timing *fp_timing; struct drm_display_mode *panel_fixed_mode; int panel_type = panel->vbt.panel_type; - panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data, - lvds_lfp_data_ptrs, - panel_type); + panel_dvo_timing = get_lfp_dvo_timing(lfp_data, + lfp_data_ptrs, + panel_type); panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); if (!panel_fixed_mode) @@ -850,15 +850,15 @@ parse_lfp_panel_dtd(struct drm_i915_private *i915, fill_detail_timing_data(i915, panel_fixed_mode, panel_dvo_timing); - panel->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; + panel->vbt.lfp_vbt_mode = panel_fixed_mode; drm_dbg_kms(&i915->drm, "Found panel mode in BIOS VBT legacy lfp table: " DRM_MODE_FMT "\n", DRM_MODE_ARG(panel_fixed_mode)); - fp_timing = get_lvds_fp_timing(lvds_lfp_data, - lvds_lfp_data_ptrs, - panel_type); + fp_timing = get_lfp_fp_timing(lfp_data, + lfp_data_ptrs, + panel_type); /* check the resolution, just to be sure */ if (fp_timing->x_res == panel_fixed_mode->hdisplay && @@ -874,25 +874,25 @@ static void parse_lfp_data(struct drm_i915_private *i915, struct intel_panel *panel) { - const struct bdb_lvds_lfp_data *data; - const struct bdb_lvds_lfp_data_tail *tail; - const struct bdb_lvds_lfp_data_ptrs *ptrs; + const struct bdb_lfp_data *data; + const struct bdb_lfp_data_tail *tail; + const struct bdb_lfp_data_ptrs *ptrs; const struct drm_edid_product_id *pnp_id; struct drm_printer p; int panel_type = panel->vbt.panel_type; - ptrs = bdb_find_section(i915, BDB_LVDS_LFP_DATA_PTRS); + ptrs = bdb_find_section(i915, BDB_LFP_DATA_PTRS); if (!ptrs) return; - data = bdb_find_section(i915, BDB_LVDS_LFP_DATA); + data = bdb_find_section(i915, BDB_LFP_DATA); if (!data) return; - if (!panel->vbt.lfp_lvds_vbt_mode) + if (!panel->vbt.lfp_vbt_mode) parse_lfp_panel_dtd(i915, panel, data, ptrs); - pnp_id = get_lvds_pnp_id(data, ptrs, panel_type); + pnp_id = get_lfp_pnp_id(data, ptrs, panel_type); p = drm_dbg_printer(&i915->drm, DRM_UT_KMS, "Panel"); drm_edid_print_product_id(&p, pnp_id, false); @@ -1001,19 +1001,19 @@ parse_generic_dtd(struct drm_i915_private *i915, "Found panel mode in BIOS VBT generic dtd table: " DRM_MODE_FMT "\n", DRM_MODE_ARG(panel_fixed_mode)); - panel->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; + panel->vbt.lfp_vbt_mode = panel_fixed_mode; } static void parse_lfp_backlight(struct drm_i915_private *i915, struct intel_panel *panel) { - const struct bdb_lfp_backlight_data *backlight_data; + const struct bdb_lfp_backlight *backlight_data; const struct lfp_backlight_data_entry *entry; int panel_type = panel->vbt.panel_type; u16 level; - backlight_data = bdb_find_section(i915, BDB_LVDS_BACKLIGHT); + backlight_data = bdb_find_section(i915, BDB_LFP_BACKLIGHT); if (!backlight_data) return; @@ -1677,7 +1677,7 @@ parse_mipi_config(struct drm_i915_private *i915, panel->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; /* Block #40 is already parsed and panel_fixed_mode is - * stored in i915->lfp_lvds_vbt_mode + * stored in i915->lfp_vbt_mode * resuse this when needed */ @@ -3306,8 +3306,8 @@ void intel_bios_fini_panel(struct intel_panel *panel) { kfree(panel->vbt.sdvo_lvds_vbt_mode); panel->vbt.sdvo_lvds_vbt_mode = NULL; - kfree(panel->vbt.lfp_lvds_vbt_mode); - panel->vbt.lfp_lvds_vbt_mode = NULL; + kfree(panel->vbt.lfp_vbt_mode); + panel->vbt.lfp_vbt_mode = NULL; kfree(panel->vbt.dsi.data); panel->vbt.dsi.data = NULL; kfree(panel->vbt.dsi.pps); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 00eba3fbcdc6..a06a154d587b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -305,7 +305,7 @@ enum drrs_type { }; struct intel_vbt_panel_data { - struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ + struct drm_display_mode *lfp_vbt_mode; /* if any */ struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ /* Feature bits */ diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index a5d7fc8418c9..cdc9dadb578d 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -751,7 +751,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id) struct intel_connector *connector = intel_dsi->attached_connector; struct mipi_config *mipi_config = connector->panel.vbt.dsi.config; struct mipi_pps_data *pps = connector->panel.vbt.dsi.pps; - struct drm_display_mode *mode = connector->panel.vbt.lfp_lvds_vbt_mode; + struct drm_display_mode *mode = connector->panel.vbt.lfp_vbt_mode; u16 burst_mode_ratio; enum port port; diff --git a/drivers/gpu/drm/i915/display/intel_panel.c b/drivers/gpu/drm/i915/display/intel_panel.c index 6f4ff6a89c32..71454ddef20f 100644 --- a/drivers/gpu/drm/i915/display/intel_panel.c +++ b/drivers/gpu/drm/i915/display/intel_panel.c @@ -352,7 +352,7 @@ void intel_panel_add_vbt_lfp_fixed_mode(struct intel_connector *connector) struct drm_i915_private *i915 = to_i915(connector->base.dev); const struct drm_display_mode *mode; - mode = connector->panel.vbt.lfp_lvds_vbt_mode; + mode = connector->panel.vbt.lfp_vbt_mode; if (!mode) return; diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 32a6cd01cfbe..c02d808d9e35 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -165,10 +165,10 @@ enum bdb_block_id { BDB_SDVO_LVDS_POWER_SEQ = 25, BDB_TV_OPTIONS = 26, BDB_EDP = 27, - BDB_LVDS_OPTIONS = 40, - BDB_LVDS_LFP_DATA_PTRS = 41, - BDB_LVDS_LFP_DATA = 42, - BDB_LVDS_BACKLIGHT = 43, + BDB_LFP_OPTIONS = 40, + BDB_LFP_DATA_PTRS = 41, + BDB_LFP_DATA = 42, + BDB_LFP_BACKLIGHT = 43, BDB_LFP_POWER = 44, BDB_MIPI_CONFIG = 52, BDB_MIPI_SEQUENCE = 53, @@ -769,7 +769,7 @@ struct bdb_edp { * Block 40 - LFP Data Block */ -struct bdb_lvds_options { +struct bdb_lfp_options { u8 panel_type; u8 panel_type2; /* 212+ */ /* LVDS capabilities, stored in a dword */ @@ -802,22 +802,22 @@ struct bdb_lvds_options { /* * Block 41 - LFP Data Table Pointers */ -struct lvds_lfp_data_ptr_table { +struct lfp_data_ptr_table { u16 offset; /* offsets are from start of bdb */ u8 table_size; } __packed; /* LFP pointer table contains entries to the struct below */ -struct lvds_lfp_data_ptr { - struct lvds_lfp_data_ptr_table fp_timing; - struct lvds_lfp_data_ptr_table dvo_timing; - struct lvds_lfp_data_ptr_table panel_pnp_id; +struct lfp_data_ptr { + struct lfp_data_ptr_table fp_timing; + struct lfp_data_ptr_table dvo_timing; + struct lfp_data_ptr_table panel_pnp_id; } __packed; -struct bdb_lvds_lfp_data_ptrs { - u8 lvds_entries; - struct lvds_lfp_data_ptr ptr[16]; - struct lvds_lfp_data_ptr_table panel_name; /* (156-163?)+ */ +struct bdb_lfp_data_ptrs { + u8 num_entries; + struct lfp_data_ptr ptr[16]; + struct lfp_data_ptr_table panel_name; /* (156-163?)+ */ } __packed; /* @@ -825,7 +825,7 @@ struct bdb_lvds_lfp_data_ptrs { */ /* LFP data has 3 blocks per entry */ -struct lvds_fp_timing { +struct fp_timing { u16 x_res; u16 y_res; u32 lvds_reg; @@ -846,29 +846,29 @@ struct lvds_fp_timing { * the data must be accessed using the data table pointers. * Do not use this directly! */ -struct lvds_lfp_data_entry { - struct lvds_fp_timing fp_timing; +struct lfp_data_entry { + struct fp_timing fp_timing; struct bdb_edid_dtd dvo_timing; struct bdb_edid_pnp_id pnp_id; } __packed; -struct bdb_lvds_lfp_data { - struct lvds_lfp_data_entry data[16]; +struct bdb_lfp_data { + struct lfp_data_entry data[16]; } __packed; -struct lvds_lfp_black_border { +struct lfp_black_border { u8 top; /* 227+ */ u8 bottom; /* 227+ */ u8 left; /* 238+ */ u8 right; /* 238+ */ } __packed; -struct bdb_lvds_lfp_data_tail { +struct bdb_lfp_data_tail { struct bdb_edid_product_name panel_name[16]; /* (156-163?)+ */ u16 scaling_enable; /* 187+ */ u8 seamless_drrs_min_refresh_rate[16]; /* 188+ */ u8 pixel_overlap_count[16]; /* 208+ */ - struct lvds_lfp_black_border black_border[16]; /* 227+ */ + struct lfp_black_border black_border[16]; /* 227+ */ u16 dual_lfp_port_sync_enable; /* 231+ */ u16 gpu_dithering_for_banding_artifacts; /* 245+ */ } __packed; @@ -901,7 +901,7 @@ struct lfp_brightness_level { u16 reserved; } __packed; -struct bdb_lfp_backlight_data { +struct bdb_lfp_backlight { u8 entry_size; struct lfp_backlight_data_entry data[16]; u8 level[16]; /* 162-233 */ -- cgit From 8e26690851f9b49551dc6c48c720700f44c8986a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:19 +0300 Subject: drm/i915/bios: Rename SDVO DTD blocks a bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The SDVO LVDS blocks are specifically about LVDS, so stick to naming that reflects that. This also makes the names match the spec. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-6-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 23 +++++++++++------------ drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12 ++++++------ 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 060dd7d2eebe..b0a49b2f957f 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -170,8 +170,8 @@ static const struct { .min_size = sizeof(struct bdb_driver_features), }, { .section_id = BDB_SDVO_LVDS_OPTIONS, .min_size = sizeof(struct bdb_sdvo_lvds_options), }, - { .section_id = BDB_SDVO_PANEL_DTDS, - .min_size = sizeof(struct bdb_sdvo_panel_dtds), }, + { .section_id = BDB_SDVO_LVDS_DTD, + .min_size = sizeof(struct bdb_sdvo_lvds_dtd), }, { .section_id = BDB_EDP, .min_size = sizeof(struct bdb_edp), }, { .section_id = BDB_LFP_OPTIONS, @@ -1091,19 +1091,18 @@ parse_lfp_backlight(struct drm_i915_private *i915, panel->vbt.backlight.controller); } -/* Try to find sdvo panel data */ static void -parse_sdvo_panel_data(struct drm_i915_private *i915, - struct intel_panel *panel) +parse_sdvo_lvds_data(struct drm_i915_private *i915, + struct intel_panel *panel) { - const struct bdb_sdvo_panel_dtds *dtds; + const struct bdb_sdvo_lvds_dtd *dtd; struct drm_display_mode *panel_fixed_mode; int index; index = i915->display.params.vbt_sdvo_panel_type; if (index == -2) { drm_dbg_kms(&i915->drm, - "Ignore SDVO panel mode from BIOS VBT tables.\n"); + "Ignore SDVO LVDS mode from BIOS VBT tables.\n"); return; } @@ -1117,20 +1116,20 @@ parse_sdvo_panel_data(struct drm_i915_private *i915, index = sdvo_lvds_options->panel_type; } - dtds = bdb_find_section(i915, BDB_SDVO_PANEL_DTDS); - if (!dtds) + dtd = bdb_find_section(i915, BDB_SDVO_LVDS_DTD); + if (!dtd) return; panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); if (!panel_fixed_mode) return; - fill_detail_timing_data(i915, panel_fixed_mode, &dtds->dtds[index]); + fill_detail_timing_data(i915, panel_fixed_mode, &dtd->dtd[index]); panel->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; drm_dbg_kms(&i915->drm, - "Found SDVO panel mode in BIOS VBT tables: " DRM_MODE_FMT "\n", + "Found SDVO LVDS mode in BIOS VBT tables: " DRM_MODE_FMT "\n", DRM_MODE_ARG(panel_fixed_mode)); } @@ -3257,7 +3256,7 @@ static void intel_bios_init_panel(struct drm_i915_private *i915, parse_generic_dtd(i915, panel); parse_lfp_data(i915, panel); parse_lfp_backlight(i915, panel); - parse_sdvo_panel_data(i915, panel); + parse_sdvo_lvds_data(i915, panel); parse_panel_driver_features(i915, panel); parse_power_conservation_features(i915, panel); parse_edp(i915, panel); diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index c02d808d9e35..038f489d034c 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -160,9 +160,9 @@ enum bdb_block_id { BDB_OEM_CUSTOM = 20, BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ BDB_SDVO_LVDS_OPTIONS = 22, - BDB_SDVO_PANEL_DTDS = 23, - BDB_SDVO_LVDS_PNP_IDS = 24, - BDB_SDVO_LVDS_POWER_SEQ = 25, + BDB_SDVO_LVDS_DTD = 23, + BDB_SDVO_LVDS_PNP_ID = 24, + BDB_SDVO_LVDS_PPS = 25, BDB_TV_OPTIONS = 26, BDB_EDP = 27, BDB_LFP_OPTIONS = 40, @@ -686,11 +686,11 @@ struct bdb_sdvo_lvds_options { } __packed; /* - * Block 23 - SDVO LVDS Panel DTDs + * Block 23 - SDVO LVDS DTD */ -struct bdb_sdvo_panel_dtds { - struct bdb_edid_dtd dtds[4]; +struct bdb_sdvo_lvds_dtd { + struct bdb_edid_dtd dtd[4]; } __packed; /* -- cgit From 10632fcbf057af326e8b7d9b18120f939f4f1aa0 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:20 +0300 Subject: drm/i915/bios: Define "TV" child device handle MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Child device 0x2 used to be "TV" until redefined to mean EFP5 in version 215. Add a define for the old meaning as well. Technically it was probably deprecated a lot before version 215 since native TV encoders were last seen on CTG, and SDVO was fully gone by HSW. So something like "???-164" might also be a reasonable way to document this, but no real harm in saying "???-214" since nothing else presumably occupied that bit in the meantime. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-7-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 038f489d034c..e616beb62b39 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -242,6 +242,7 @@ struct bdb_general_features { /* Device handle */ #define DEVICE_HANDLE_CRT 0x0001 +#define DEVICE_HANDLE_TV 0x0002 /* ???-214 */ #define DEVICE_HANDLE_EFP1 0x0004 #define DEVICE_HANDLE_EFP2 0x0040 #define DEVICE_HANDLE_EFP3 0x0020 -- cgit From e760a7dade4ba88d417e355ca7a109571abe2ac3 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:21 +0300 Subject: drm/i915/bios: Flag "VBIOS only" VBT data blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Several data blocks are mean to be consumbed by VBIOS only. Flag them as such. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-8-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index e616beb62b39..b81b25cfdc74 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -144,15 +144,15 @@ enum bdb_block_id { BDB_OLD_TOGGLE_LIST = 3, BDB_MODE_SUPPORT_LIST = 4, BDB_GENERIC_MODE_TABLE = 5, - BDB_EXT_MMIO_REGS = 6, - BDB_SWF_IO = 7, - BDB_SWF_MMIO = 8, + BDB_EXT_MMIO_REGS = 6, /* VBIOS only */ + BDB_SWF_IO = 7, /* VBIOS only */ + BDB_SWF_MMIO = 8, /* VBIOS only */ BDB_PSR = 9, BDB_MODE_REMOVAL_TABLE = 10, BDB_CHILD_DEVICE_TABLE = 11, BDB_DRIVER_FEATURES = 12, BDB_DRIVER_PERSISTENCE = 13, - BDB_EXT_TABLE_PTRS = 14, + BDB_EXT_TABLE_PTRS = 14, /* VBIOS only */ BDB_DOT_CLOCK_OVERRIDE = 15, BDB_DISPLAY_SELECT = 16, BDB_DRIVER_ROTATION = 18, @@ -174,7 +174,7 @@ enum bdb_block_id { BDB_MIPI_SEQUENCE = 53, BDB_COMPRESSION_PARAMETERS = 56, BDB_GENERIC_DTD = 58, - BDB_SKIP = 254, /* VBIOS private block, ignore */ + BDB_SKIP = 254, /* VBIOS only */ }; /* -- cgit From a17b317c11fa1d66e2a0bfcf680e3eb6a14a5c57 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:22 +0300 Subject: drm/i915/bios: Add version notes for some blocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document which VBT blocks were defined in which BDB version, for the cases where the spec actually states this accurately. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index b81b25cfdc74..6858a7631eee 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -147,7 +147,7 @@ enum bdb_block_id { BDB_EXT_MMIO_REGS = 6, /* VBIOS only */ BDB_SWF_IO = 7, /* VBIOS only */ BDB_SWF_MMIO = 8, /* VBIOS only */ - BDB_PSR = 9, + BDB_PSR = 9, /* 165+ */ BDB_MODE_REMOVAL_TABLE = 10, BDB_CHILD_DEVICE_TABLE = 11, BDB_DRIVER_FEATURES = 12, @@ -170,10 +170,10 @@ enum bdb_block_id { BDB_LFP_DATA = 42, BDB_LFP_BACKLIGHT = 43, BDB_LFP_POWER = 44, - BDB_MIPI_CONFIG = 52, - BDB_MIPI_SEQUENCE = 53, - BDB_COMPRESSION_PARAMETERS = 56, - BDB_GENERIC_DTD = 58, + BDB_MIPI_CONFIG = 52, /* 175+ */ + BDB_MIPI_SEQUENCE = 53, /* 177+ */ + BDB_COMPRESSION_PARAMETERS = 56, /* 213+ */ + BDB_GENERIC_DTD = 58, /* 229+ */ BDB_SKIP = 254, /* VBIOS only */ }; -- cgit From c58f254be3bd6276133735c8b7762c51589b4d03 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:23 +0300 Subject: drm/i915/bios: Define VBT block 3 (Display Toggle Option) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 3 (Display Toggle Option). On modern VBTs this is just a single byte, but on ALM there is also some extra to do with toggle lists or something. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-10-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 6858a7631eee..816d81071437 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -141,7 +141,7 @@ struct bdb_header { enum bdb_block_id { BDB_GENERAL_FEATURES = 1, BDB_GENERAL_DEFINITIONS = 2, - BDB_OLD_TOGGLE_LIST = 3, + BDB_DISPLAY_TOGGLE = 3, BDB_MODE_SUPPORT_LIST = 4, BDB_GENERIC_MODE_TABLE = 5, BDB_EXT_MMIO_REGS = 6, /* VBIOS only */ @@ -561,6 +561,16 @@ struct bdb_general_definitions { u8 devices[]; } __packed; +/* + * Block 3 - Display Toggle Option Block + */ + +struct bdb_display_toggle { + u8 feature_bits; + u16 num_entries; /* ALM only */ + u16 list[]; /* ALM only */ +} __packed; + /* * Block 9 - SRD Feature Block */ -- cgit From 22794e6cee284c154a464ef6c58219e35739a3fe Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:24 +0300 Subject: drm/i915/bios: Define VBT block 4 (Mode Support List) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 4 (Mode Support List). Slightly crazy layout with a variable length list at the start, followed by the length of said list. No real idea what these "Intel mode numbers" really are. What I see in real world VBTs seems to be always the same list of 26 numbers, ranging between 0x30 and 0x84. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-11-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 816d81071437..a49d84401df1 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -571,6 +571,15 @@ struct bdb_display_toggle { u16 list[]; /* ALM only */ } __packed; +/* + * Block 4 - Mode Support List + */ + +struct bdb_mode_support_list { + u8 intel_mode_number[0]; + u16 mode_list_length; +} __packed; + /* * Block 9 - SRD Feature Block */ -- cgit From 2e8b8073178a898f56e6d1512de016f644306fb5 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:25 +0300 Subject: drm/i915/bios: Define VBT block 5 (Generic Mode Table) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 5 (Generic Mode Table). Details were mostly gleaned from some VBIOS sources. There are apparently two variants of the block: ALM only vs. MGM, defined here as bdb_generic_mode_table_alm and bdb_generic_mode_table_mgm. And those are the only two platforms where I've seen this block. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-12-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 54 +++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index a49d84401df1..a38193d158e3 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -580,6 +580,60 @@ struct bdb_mode_support_list { u16 mode_list_length; } __packed; +/* + * Block 5 - Generic Mode Table + */ + +struct generic_mode_table { + u16 x_res; + u16 y_res; + u8 color_depths; + u8 refresh_rate[3]; + u8 reserved; + u8 text_cols; + u8 text_rows; + u8 font_height; + u16 page_size; + u8 misc; +} __packed; + +struct generic_mode_timings { + u32 dotclock_khz; + u16 hdisplay; + u16 htotal; + u16 hblank_start; + u16 hblank_end; + u16 hsync_start; + u16 hsync_end; + u16 vdisplay; + u16 vtotal; + u16 vblank_start; + u16 vblank_end; + u16 vsync_start; + u16 vsync_end; +} __packed; + +struct generic_mode_timings_alm { + struct generic_mode_timings timings; + u8 wm_8bpp; + u8 burst_8bpp; + u8 wm_16bpp; + u8 burst_16bpp; + u8 wm_32bpp; + u8 burst_32bpp; +} __packed; + +struct bdb_generic_mode_table_alm { + struct generic_mode_table table; + struct generic_mode_timings_alm timings[3]; +} __packed; + +struct bdb_generic_mode_table_mgm { + u16 mode_flag; + struct generic_mode_table table; + struct generic_mode_timings timings[3]; +} __packed; + /* * Block 9 - SRD Feature Block */ -- cgit From 2318da471a8af705083836967ad3acd13ee59d3c Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:26 +0300 Subject: drm/i915/bios: Define VBT blocks 6,7,8 (register tables) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents for VBT blocks: - Block 6 (Extended MMIO Register Table) - Block 7 (IO Software Flag Table) - Block 8 (MMIO SWF Register Table) All of these use the same basic layout, with two known variants: - data_access_size==0xce -> offset,value tuples are u8,u8 - data_access_size==0x02 -> offset,value tuples are u32,u32 Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-13-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index a38193d158e3..8aff4816f463 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -634,6 +634,22 @@ struct bdb_generic_mode_table_mgm { struct generic_mode_timings timings[3]; } __packed; +/* + * Block 6 - Extended MMIO Register Table, VBIOS only + * Block 7 - IO Software Flag Table, VBIOS only + * Block 8 - MMIO SWF Register Table, VBIOS only + */ +struct bdb_reg_table { + u16 table_id; + u8 data_access_size; + /* + * offset,value tuples: + * data_access_size==0xce -> u8,u8 + * data_access_size==0x02 -> u32,u32 + */ + /* u16 table_end_marker; */ +} __packed; + /* * Block 9 - SRD Feature Block */ -- cgit From 98fe6aed8ae8590065eca04b6f0be98ae64c066a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:27 +0300 Subject: drm/i915/bios: Define VBT block 10 (Mode Removal Table) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 10 (Mode Removal Table). There seem to be two variants: - 8 byte entries for desktop systems - 10 byte entries for mobile systems, with the extra panel_flags being a bitmask of LFPs It seems starting from HSW only the mobile variant is used anymore. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-14-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 8aff4816f463..c4435438508e 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -677,6 +677,29 @@ struct bdb_psr { u32 psr2_tp2_tp3_wakeup_time; /* 226+ */ } __packed; +/* + * Block 10 - Mode Removal Table + */ + +struct mode_removal_table { + u16 x_res; + u16 y_res; + u8 bpp; + u16 refresh_rate; + u8 removal_flags; + u16 panel_flags; +} __packed; + +struct bdb_mode_removal { + u8 row_size; /* 8 or 10 bytes */ + /* + * VBT spec says this is always 20 entries, + * but ALM seems to have only 15 entries. + */ + struct mode_removal_table modes[]; + /* u16 terminator; 0x0000 */ +} __packed; + /* * Block 12 - Driver Features Data Block */ -- cgit From 2f1aa210fefa08dc998ccffbf5a67d5be11edf3e Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:28 +0300 Subject: drm/i915/bios: Define VBT block 12 (Driver Persistent Algorithm) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 12 (Driver Persistent Algorithm). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-15-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index c4435438508e..741ad566f0cc 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -778,6 +778,25 @@ struct bdb_driver_features { u16 pc_feature_valid:1; /* 159+ */ } __packed; +/* + * Block 13 - Driver Persistent Algorithm + */ + +struct bdb_driver_persistence { + u16 hotkey_persistent_algorithm:1; + u16 lid_switch_persistent_algorithm:1; + u16 power_management_persistent_algorithm:1; + u16 hotkey_persistent_on_mds_twin:1; + u16 hotkey_persistent_on_refresh_rate:1; + u16 hotkey_persistent_on_restore_pipe:1; + u16 hotkey_persistent_on_mode:1; + u16 edid_persistent_on_mode:1; + u16 dvo_hotplug_persistent_on_mode:1; + u16 docking_persistent_algorithm:1; + u16 rsvd:6; + u8 persistent_max_config; +} __packed; + /* * Block 22 - SDVO LVDS General Options */ -- cgit From f7d5b5ff088fc85baa563182f5ff2cd501ed56d5 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:29 +0300 Subject: drm/i915/bios: Define VBT block 15 (Dot Clock Override Table) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 15 (Dot Clock Override Table) The contents were reverse engineered by intuition. The gen2 stuff seems solid as I can verify that against real world VBT data. The gen3 stuff less so as all the gen3+ VBTs I have just filla the entire block with zeroes. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-16-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 30 +++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 741ad566f0cc..75c702c9890b 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -797,6 +797,36 @@ struct bdb_driver_persistence { u8 persistent_max_config; } __packed; +/* + * Block 15 - Dot Clock Override Table + */ + +struct dot_clock_override_entry_gen2 { + u32 dotclock; + u8 n; + u8 m1; + u8 m2; + u8 p1:5; + u8 p1_div_by_2:1; + u8 reserved:1; + u8 p2_div_by_4:1; +} __packed; + +struct dot_clock_override_entry_gen3 { + u32 dotclock; + u8 n; + u8 m1; + u8 m2; + u8 p1; + u8 p2; +} __packed; + +struct bdb_dot_clock_override { + u8 row_size; /* 8 == gen2, 9 == gen3+ */ + u8 num_rows; + struct dot_clock_override_entry_gen3 table[]; /* or _gen2 */ +} __packed; + /* * Block 22 - SDVO LVDS General Options */ -- cgit From 55c6b98676ed667f8900d46257b96eff47abef55 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:30 +0300 Subject: drm/i915/bios: Define ALM only VBT block 9 contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For some reason ALM VBT has two dot clock override tables. One as the normal block 15 and a second one as block 9. The table in block 9 has no row_size/num_rows information. On my Fujitsu Lifebook S6010 only the block 9 table has actual data in it. Block 15 is present but all zeroes. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-17-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 31 +++++++++++++++++---------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 75c702c9890b..0a3a7e3d1d99 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -147,6 +147,7 @@ enum bdb_block_id { BDB_EXT_MMIO_REGS = 6, /* VBIOS only */ BDB_SWF_IO = 7, /* VBIOS only */ BDB_SWF_MMIO = 8, /* VBIOS only */ + BDB_DOT_CLOCK_OVERRIDE_ALM = 9, BDB_PSR = 9, /* 165+ */ BDB_MODE_REMOVAL_TABLE = 10, BDB_CHILD_DEVICE_TABLE = 11, @@ -650,6 +651,25 @@ struct bdb_reg_table { /* u16 table_end_marker; */ } __packed; +/* + * Block 9 - Undocumented table (ALM only) + */ + +struct dot_clock_override_entry_gen2 { + u32 dotclock; + u8 n; + u8 m1; + u8 m2; + u8 p1:5; + u8 p1_div_by_2:1; + u8 reserved:1; + u8 p2_div_by_4:1; +} __packed; + +struct bdb_dot_clock_override_alm { + struct dot_clock_override_entry_gen2 t[0]; +} __packed; + /* * Block 9 - SRD Feature Block */ @@ -801,17 +821,6 @@ struct bdb_driver_persistence { * Block 15 - Dot Clock Override Table */ -struct dot_clock_override_entry_gen2 { - u32 dotclock; - u8 n; - u8 m1; - u8 m2; - u8 p1:5; - u8 p1_div_by_2:1; - u8 reserved:1; - u8 p2_div_by_4:1; -} __packed; - struct dot_clock_override_entry_gen3 { u32 dotclock; u8 n; -- cgit From 8e94221f78018338e1a5791cec0394b13dd0b13d Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:31 +0300 Subject: drm/i915/bios: Define VBT block 17 (SV Test Functions) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 17 (SV Test Functions). Nothing real here for us, but might as well define it for completeness. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-18-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 0a3a7e3d1d99..43e96260a532 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -156,6 +156,7 @@ enum bdb_block_id { BDB_EXT_TABLE_PTRS = 14, /* VBIOS only */ BDB_DOT_CLOCK_OVERRIDE = 15, BDB_DISPLAY_SELECT = 16, + BDB_SV_TEST_FUNCTIONS = 17, BDB_DRIVER_ROTATION = 18, BDB_DISPLAY_REMOVE = 19, BDB_OEM_CUSTOM = 20, @@ -836,6 +837,14 @@ struct bdb_dot_clock_override { struct dot_clock_override_entry_gen3 table[]; /* or _gen2 */ } __packed; +/* + * Block 17 - SV Test Functions + */ + +struct bdb_sv_test_functions { + u8 sv_bits[8]; +} __packed; + /* * Block 22 - SDVO LVDS General Options */ -- cgit From 95f4cbc8fb323b5174dcdde87da0b04161796a63 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:32 +0300 Subject: drm/i915/bios: Define VBT block 18 (Driver Rotation) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of block 18 (Driver Rotation). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-19-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 43e96260a532..09d16704936b 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -845,6 +845,18 @@ struct bdb_sv_test_functions { u8 sv_bits[8]; } __packed; +/* + * Block 18 - Driver Rotation + */ + +struct bdb_driver_rotation { + u8 rotation_enable; + u8 rotation_flags_1; + u16 rotation_flags_2; + u32 rotation_flags_3; + u32 rotation_flags_4; +} __packed; + /* * Block 22 - SDVO LVDS General Options */ -- cgit From e547b97e9d79c1b8a8f935a398a41bb3d9bf4c48 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:33 +0300 Subject: drm/i915/bios: Define VBT blocks 16,29,31 (Toggle List) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contenst is VBT blocks 16,19,31 (Toggle List). There are three variants of this block: pre-IVB, IVB, HSW+, with each having slightly different entries. Curiously many HSW/BDW machines seem to have both the IVB and HSW+ variants in their VBTs simultanously. No idea why. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-20-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 63 ++++++++++++++++++++++++++- 1 file changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 09d16704936b..63cfb1684c71 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -155,7 +155,7 @@ enum bdb_block_id { BDB_DRIVER_PERSISTENCE = 13, BDB_EXT_TABLE_PTRS = 14, /* VBIOS only */ BDB_DOT_CLOCK_OVERRIDE = 15, - BDB_DISPLAY_SELECT = 16, + BDB_DISPLAY_SELECT_OLD = 16, BDB_SV_TEST_FUNCTIONS = 17, BDB_DRIVER_ROTATION = 18, BDB_DISPLAY_REMOVE = 19, @@ -167,6 +167,8 @@ enum bdb_block_id { BDB_SDVO_LVDS_PPS = 25, BDB_TV_OPTIONS = 26, BDB_EDP = 27, + BDB_DISPLAY_SELECT_IVB = 29, /* 164+ */ + BDB_DISPLAY_SELECT_HSW = 31, /* 166+ */ BDB_LFP_OPTIONS = 40, BDB_LFP_DATA_PTRS = 41, BDB_LFP_DATA = 42, @@ -837,6 +839,27 @@ struct bdb_dot_clock_override { struct dot_clock_override_entry_gen3 table[]; /* or _gen2 */ } __packed; +/* + * Block 16 - Toggle List Block (pre-HSW) + */ + +struct toggle_list_entry_old { + u8 display_select_pipe_a; + u8 display_select_pipe_b; + u8 caps; +} __packed; + +struct toggle_list_table_old { + u16 num_entries; + u8 entry_size; + struct toggle_list_entry_old list[]; +} __packed; + +struct bdb_display_select_old { + /* each table has variable size! */ + struct toggle_list_table_old tables[4]; +} __packed; + /* * Block 17 - SV Test Functions */ @@ -957,6 +980,44 @@ struct bdb_edp { u16 edp_dsc_disable; /* 251+ */ } __packed; +/* + * Block 29 - Toggle List Block (IVB) + */ + +struct toggle_list_entry_ivb { + u8 display_select; +} __packed; + +struct toggle_list_table_ivb { + u16 num_entries; + u8 entry_size; + struct toggle_list_entry_ivb list[]; +} __packed; + +struct bdb_display_select_ivb { + /* each table has variable size! */ + struct toggle_list_table_ivb tables[4]; +} __packed; + +/* + * Block 31 - Toggle List Block (HSW+) + */ + +struct toggle_list_entry_hsw { + u16 display_select; +} __packed; + +struct toggle_list_table_hsw { + u16 num_entries; + u8 entry_size; + struct toggle_list_entry_hsw list[]; +} __packed; + +struct bdb_display_select_hsw { + /* each table has variable size! */ + struct toggle_list_table_hsw tables[4]; +} __packed; + /* * Block 40 - LFP Data Block */ -- cgit From e225161e2aff5dffd1ff754d86c17c7f9b6457f5 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:34 +0300 Subject: drm/i915/bios: Define VBT blocks 19,30,32 (Display Configuration Removal Table) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contenst is VBT blocks 19,30,32 (Display Configuration Removal Table) contents. There are three variants of this block: pre-IVB, IVB, HSW+, with each having slightly different entries. Curiously many HSW/BDW machines seem to have both the IVB and HSW+ variants in their VBTs simultanously. No idea why. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-21-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 47 ++++++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 63cfb1684c71..0ae1d242a420 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -158,7 +158,7 @@ enum bdb_block_id { BDB_DISPLAY_SELECT_OLD = 16, BDB_SV_TEST_FUNCTIONS = 17, BDB_DRIVER_ROTATION = 18, - BDB_DISPLAY_REMOVE = 19, + BDB_DISPLAY_REMOVE_OLD = 19, BDB_OEM_CUSTOM = 20, BDB_EFP_LIST = 21, /* workarounds for VGA hsync/vsync */ BDB_SDVO_LVDS_OPTIONS = 22, @@ -168,7 +168,9 @@ enum bdb_block_id { BDB_TV_OPTIONS = 26, BDB_EDP = 27, BDB_DISPLAY_SELECT_IVB = 29, /* 164+ */ + BDB_DISPLAY_REMOVE_IVB = 30, /* 164+ */ BDB_DISPLAY_SELECT_HSW = 31, /* 166+ */ + BDB_DISPLAY_REMOVE_HSW = 32, /* 166+ */ BDB_LFP_OPTIONS = 40, BDB_LFP_DATA_PTRS = 41, BDB_LFP_DATA = 42, @@ -880,6 +882,21 @@ struct bdb_driver_rotation { u32 rotation_flags_4; } __packed; +/* + * Block 19 - Display Configuration Removal Table (pre-IVB) + */ + +struct display_remove_entry_old { + u8 display_select_pipe_a; + u8 display_select_pipe_b; +} __packed; + +struct bdb_display_remove_old { + u8 num_entries; + u8 entry_size; + struct display_remove_entry_old table[]; +} __packed; + /* * Block 22 - SDVO LVDS General Options */ @@ -999,6 +1016,20 @@ struct bdb_display_select_ivb { struct toggle_list_table_ivb tables[4]; } __packed; +/* + * Block 30 - Display Configuration Removal Table (IVB) + */ + +struct display_remove_entry_ivb { + u8 display_select; +} __packed; + +struct bdb_display_remove_ivb { + u8 num_entries; + u8 entry_size; + struct display_remove_entry_ivb table[]; +} __packed; + /* * Block 31 - Toggle List Block (HSW+) */ @@ -1018,6 +1049,20 @@ struct bdb_display_select_hsw { struct toggle_list_table_hsw tables[4]; } __packed; +/* + * Block 32 - Display Configuration Removal Table (HSW+) + */ + +struct display_remove_entry_hsw { + u16 display_select; +} __packed; + +struct bdb_display_remove_hsw { + u8 num_entries; + u8 entry_size; + struct display_remove_entry_hsw table[]; +} __packed; + /* * Block 40 - LFP Data Block */ -- cgit From afa1bf2d5df261e3e0dbecce1204106f11a8d351 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:35 +0300 Subject: drm/i915/bios: Define VBT block 20 (OEM Customizable Modes) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 20 (OEM Customizable Modes). Each entry is either 26 or 28 bytes, depending on the BDB version. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-22-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 0ae1d242a420..bf1f2848f4cb 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -897,6 +897,30 @@ struct bdb_display_remove_old { struct display_remove_entry_old table[]; } __packed; +/* + * Block 20 - OEM Customizable Modes + */ + +struct oem_mode { + u8 enable_in_vbios:1; + u8 enable_in_os:1; + u8 enable_in_gop:1; /* 207+ */ + u8 reserved:5; + u8 display_flags; /* ???-216 */ + u16 x_res; + u16 y_res; + u8 color_depth; + u8 refresh_rate; + struct bdb_edid_dtd dtd; + u16 display_flags_2; /* 217+ */ +} __packed; + +struct bdb_oem_custom { + u8 num_entries; + u8 entry_size; + struct oem_mode modes[]; +} __packed; + /* * Block 22 - SDVO LVDS General Options */ -- cgit From 9bc6b35635318f36adf5b526ae85302605646a57 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:36 +0300 Subject: drm/i915/bios: Define VBT block 21 (EFP List) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 21 (EFP List). Specs are nowhere to be found, but real world data suggests that each entry is just the first four bytes of the EDID PnP ID structure. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-23-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index bf1f2848f4cb..012a6719ac1f 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -921,6 +921,21 @@ struct bdb_oem_custom { struct oem_mode modes[]; } __packed; +/* + * Block 21 - EFP List + */ + +struct efp_entry { + u16 mfg_name; + u16 product_code; +} __packed; + +struct bdb_efp_list { + u8 num_entries; + u8 entry_size; + struct efp_entry efp[]; +} __packed; + /* * Block 22 - SDVO LVDS General Options */ -- cgit From fdbebda16c29e0d5c456e8012801ebbcb4f78b30 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:37 +0300 Subject: drm/i915/bios: Define VBT block 24 (SDVO LVDS PnP ID) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 24 (SDVO LVDS PnP ID). The descriotion is not part of the VBT spec anymore, but the layout is rather obsvious. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-24-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 012a6719ac1f..309197cec806 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -964,6 +964,14 @@ struct bdb_sdvo_lvds_dtd { struct bdb_edid_dtd dtd[4]; } __packed; +/* + * Block 24 - SDVO LVDS PnP ID + */ + +struct bdb_sdvo_lvds_pnp_id { + struct bdb_edid_pnp_id pnp_id[4]; +} __packed; + /* * Block 27 - eDP VBT Block */ -- cgit From 76f1cf76ef4197663593b85b8b911ac6cf809489 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:38 +0300 Subject: drm/i915/bios: Define VBT block 25 (SDVO LVDS PPS) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 25 (SDVO LVDS PPS). Not 100% sure about the order of the fields as this is not documented in the VBT spec anymore, but this order matches what is included as part of the power sequencing SDVO commands (struct sdvo_panel_power_sequencing). Also the real world VBT data I have looks OK with this definition. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-25-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 309197cec806..c6a3a30cb4b2 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -972,6 +972,22 @@ struct bdb_sdvo_lvds_pnp_id { struct bdb_edid_pnp_id pnp_id[4]; } __packed; +/* + * Block 25 - SDVO LVDS PPS + */ + +struct sdvo_lvds_pps { + u16 t0; /* power on */ + u16 t1; /* backlight on */ + u16 t2; /* backlight off */ + u16 t3; /* power off */ + u16 t4; /* power cycle */ +} __packed; + +struct bdb_sdvo_lvds_pps { + struct sdvo_lvds_pps pps[4]; +} __packed; + /* * Block 27 - eDP VBT Block */ -- cgit From 9bda347a7d5c669be2184a6b6d35bbf1144e04d3 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:39 +0300 Subject: drm/i915/bios: Define VBT block 26 (TV Options) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 26 (TV Options). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-26-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index c6a3a30cb4b2..778bb4ee8c65 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -988,6 +988,18 @@ struct bdb_sdvo_lvds_pps { struct sdvo_lvds_pps pps[4]; } __packed; +/* + * Block 26 - TV Options Block + */ + +struct bdb_tv_options { + u16 underscan_overscan_hdtv_component:2; + u16 rsvd1:10; + u16 underscan_overscan_hdtv_dvi:2; + u16 add_modes_to_avoid_overscan_issue:1; + u16 d_connector_support:1; +} __packed; + /* * Block 27 - eDP VBT Block */ -- cgit From 9f15bc83822b988b61be1179ae43d5d765071962 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:40 +0300 Subject: drm/i915/bios: Define VBT block 28 (EFP DTD) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 28 (EFP DTD). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-27-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 778bb4ee8c65..606c79eaa416 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -167,6 +167,7 @@ enum bdb_block_id { BDB_SDVO_LVDS_PPS = 25, BDB_TV_OPTIONS = 26, BDB_EDP = 27, + BDB_EFP_DTD = 28, /* 161+ */ BDB_DISPLAY_SELECT_IVB = 29, /* 164+ */ BDB_DISPLAY_REMOVE_IVB = 30, /* 164+ */ BDB_DISPLAY_SELECT_HSW = 31, /* 166+ */ @@ -1072,6 +1073,14 @@ struct bdb_edp { u16 edp_dsc_disable; /* 251+ */ } __packed; +/* + * Block 28 - EFP DTD Block + */ + +struct bdb_efp_dtd { + struct bdb_edid_dtd dtd[3]; +} __packed; + /* * Block 29 - Toggle List Block (IVB) */ -- cgit From bc2dcfb6b68c91a658c5fd5e0d78392846980da4 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:41 +0300 Subject: drm/i915/bios: Define VBT block 45 (eDP BFI) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 45 (eDP BFI). Note that I've not actually seen any real world VBTs with this block. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-28-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 606c79eaa416..a9c06e00cbdf 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -177,6 +177,7 @@ enum bdb_block_id { BDB_LFP_DATA = 42, BDB_LFP_BACKLIGHT = 43, BDB_LFP_POWER = 44, + BDB_EDP_BFI = 45, /* 160+ */ BDB_MIPI_CONFIG = 52, /* 175+ */ BDB_MIPI_SEQUENCE = 53, /* 177+ */ BDB_COMPRESSION_PARAMETERS = 56, /* 213+ */ @@ -1342,6 +1343,22 @@ struct bdb_lfp_power { struct aggressiveness_profile2_entry aggressiveness2[16]; /* 247+ */ } __packed; +/* + * Block 45 - eDP BFI Block + */ + +struct edp_bfi { + u8 enable_bfi_in_driver:1; + u8 enable_brightness_control_in_cui:1; + u8 reserved:6; + u8 brightness_percentage_when_bfi_disabled; +} __packed; + +struct bdb_edp_bfi { + u8 bfi_structure_size; + struct edp_bfi bfi[16]; +} __packed; + /* * Block 52 - MIPI Configuration Block */ -- cgit From cb094188f5ca64f5fcc6e1bbcb0f3950766e5027 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:42 +0300 Subject: drm/i915/bios: Define VBT block 46 (Chromaticity For Narrow Gamut Panel) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 46 (Chromaticity For Narrow Gamut Panel). One entry per panel. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-29-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index a9c06e00cbdf..1cc52658684f 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -178,6 +178,7 @@ enum bdb_block_id { BDB_LFP_BACKLIGHT = 43, BDB_LFP_POWER = 44, BDB_EDP_BFI = 45, /* 160+ */ + BDB_CHROMATICITY = 46, /* 169+ */ BDB_MIPI_CONFIG = 52, /* 175+ */ BDB_MIPI_SEQUENCE = 53, /* 177+ */ BDB_COMPRESSION_PARAMETERS = 56, /* 213+ */ @@ -1359,6 +1360,31 @@ struct bdb_edp_bfi { struct edp_bfi bfi[16]; } __packed; +/* + * Block 46 - Chromaticity For Narrow Gamut Panel Configuration Block + */ + +struct chromaticity { + u8 chromaticity_enable:1; + u8 chromaticity_from_edid_base_block:1; + u8 rsvd:6; + + u8 red_green; + u8 blue_white; + u8 red_x; + u8 red_y; + u8 green_x; + u8 green_y; + u8 blue_x; + u8 blue_y; + u8 white_x; + u8 white_y; +} __packed; + +struct bdb_chromaticity { + struct chromaticity chromaticity[16]; +} __packed; + /* * Block 52 - MIPI Configuration Block */ -- cgit From 4baedbe2c38f05d2e7121e0f78fc3469011b0dfd Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:43 +0300 Subject: drm/i915/bios: Define VBT block 51 (Fixed Set Mode Table) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 51 (Fixed Set Mode Table). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-30-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 1cc52658684f..11c4b5bb2151 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -179,6 +179,7 @@ enum bdb_block_id { BDB_LFP_POWER = 44, BDB_EDP_BFI = 45, /* 160+ */ BDB_CHROMATICITY = 46, /* 169+ */ + BDB_FIXED_SET_MODE = 51, /* 172+ */ BDB_MIPI_CONFIG = 52, /* 175+ */ BDB_MIPI_SEQUENCE = 53, /* 177+ */ BDB_COMPRESSION_PARAMETERS = 56, /* 213+ */ @@ -1385,6 +1386,16 @@ struct bdb_chromaticity { struct chromaticity chromaticity[16]; } __packed; +/* + * Block 51 - Fixed Set Mode Table + */ + +struct bdb_fixed_set_mode { + u8 enable; + u32 x_res; + u32 y_res; +} __packed; + /* * Block 52 - MIPI Configuration Block */ -- cgit From a7566ba47ba6c97df369fe7acf820d07ff3a9191 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:44 +0300 Subject: drm/i915/bios: Define VBT block 55 (RGB Palette Table) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 55 (RGB Palette Table). Note that I've not actually seen any real world VBTs with this block. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-31-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 11c4b5bb2151..089c3d2276db 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -182,6 +182,7 @@ enum bdb_block_id { BDB_FIXED_SET_MODE = 51, /* 172+ */ BDB_MIPI_CONFIG = 52, /* 175+ */ BDB_MIPI_SEQUENCE = 53, /* 177+ */ + BDB_RGB_PALETTE = 54, /* 180+ */ BDB_COMPRESSION_PARAMETERS = 56, /* 213+ */ BDB_GENERIC_DTD = 58, /* 229+ */ BDB_SKIP = 254, /* VBIOS only */ @@ -1418,6 +1419,17 @@ struct bdb_mipi_sequence { u8 data[]; /* up to 6 variable length blocks */ } __packed; +/* + * Block 55 - RGB Palette Table + */ + +struct bdb_rgb_palette { + u8 is_enabled; + u8 red[256]; + u8 blue[256]; + u8 green[256]; +} __packed; + /* * Block 56 - Compression Parameters */ -- cgit From 2b22b1b88c739348b79284ad3a216b7f3cb141c7 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:45 +0300 Subject: drm/i915/bios: Define VBT block 57 (Vswing PreEmphasis Table) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 57 (Vswing PreEmphasis Table). The contents is highly platform specific. The columns of the table corresponding to some set of PHY/etc registers. The rows corresponding to all legal vswing+pre-emphasis combinations (ie. should be 10 rows in each table). And each table corresponds to a platform specific (mostly undocumented) mapping based on link rate/eDP low-vswing/etc. parameters. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-32-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 089c3d2276db..2e900e42de31 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -184,6 +184,7 @@ enum bdb_block_id { BDB_MIPI_SEQUENCE = 53, /* 177+ */ BDB_RGB_PALETTE = 54, /* 180+ */ BDB_COMPRESSION_PARAMETERS = 56, /* 213+ */ + BDB_VSWING_PREEMPH = 57, /* 218+ */ BDB_GENERIC_DTD = 58, /* 229+ */ BDB_SKIP = 254, /* VBIOS only */ }; @@ -1481,6 +1482,16 @@ struct bdb_compression_parameters { struct dsc_compression_parameters_entry data[16]; } __packed; +/* + * Block 57 - Vswing PreEmphasis Table + */ + +struct bdb_vswing_preemph { + u8 num_tables; + u8 num_columns; + u32 tables[]; +} __packed; + /* * Block 58 - Generic DTD Block */ -- cgit From d9a6dfdbe7d4daa8db017ad690144d3116db1d1d Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:46 +0300 Subject: drm/i915/bios: Define VBT block 50 (MIPI) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 50 (MIPI). This was some easly attempt at a MIPI DSI stuff. I'm not sure this was ever actually used (I certainly don't have any VBTs with this block), but here's some kind of definition for it anyway. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-33-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 47 +++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 2e900e42de31..19c2341931b3 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -179,6 +179,7 @@ enum bdb_block_id { BDB_LFP_POWER = 44, BDB_EDP_BFI = 45, /* 160+ */ BDB_CHROMATICITY = 46, /* 169+ */ + BDB_MIPI = 50, /* 170-172 */ BDB_FIXED_SET_MODE = 51, /* 172+ */ BDB_MIPI_CONFIG = 52, /* 175+ */ BDB_MIPI_SEQUENCE = 53, /* 177+ */ @@ -1388,6 +1389,52 @@ struct bdb_chromaticity { struct chromaticity chromaticity[16]; } __packed; +/* + * Block 50 - MIPI Block + */ + +struct mipi_data { + u16 panel_identifier; + u16 bridge_revision; + + u32 dithering:1; + u32 pixel_format_18bpp:1; + u32 reserved1:1; + u32 dphy_params_valid:1; + u32 reserved2:28; + + u16 port_info; + + u16 reserved3:2; + u16 num_lanes:2; + u16 reserved4:12; + + u16 virtual_channel_num:2; + u16 video_transfer_mode:2; + u16 reserved5:12; + + u32 dsi_ddr_clock; + u32 renesas_bridge_ref_clock; + u16 power_conservation; + + u32 prepare_count:5; + u32 reserved6:3; + u32 clk_zero_count:8; + u32 trail_count:5; + u32 reserved7:3; + u32 exit_zero_count:6; + u32 reserved8:2; + + u32 high_low_switch_count; + u32 lp_byte_clock; + u32 clock_lane_switch_time_counter; + u32 panel_color_depth; +} __packed; + +struct bdb_mipi { + struct mipi_data mipi[16]; +} __packed; + /* * Block 51 - Fixed Set Mode Table */ -- cgit From 62b695b8c92ecfd26f486615f4075fe0862dbf7a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:47 +0300 Subject: drm/i915/bios: Define VBT block 55 (Compression Parameters) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of the obsolete VBT block 55 (Compression Parameters). This was some early attempt at defining the compression parameters. However the spec says: "This block is obsolete and should not be consumed for any compression programming." Block 56 is the replacement that should actually be used. So let's just name the obsolete old block but not even bother defining the contents. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-34-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 19c2341931b3..1cab8cce6a2c 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -184,6 +184,7 @@ enum bdb_block_id { BDB_MIPI_CONFIG = 52, /* 175+ */ BDB_MIPI_SEQUENCE = 53, /* 177+ */ BDB_RGB_PALETTE = 54, /* 180+ */ + BDB_COMPRESSION_PARAMETERS_OLD = 55, /* 198-212 */ BDB_COMPRESSION_PARAMETERS = 56, /* 213+ */ BDB_VSWING_PREEMPH = 57, /* 218+ */ BDB_GENERIC_DTD = 58, /* 229+ */ -- cgit From c23e1dc1d508f8a5209f11f54b5d6ec8e8ae4ace Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:48 +0300 Subject: drm/i915/bios: Define VBT block 252 (int15 Hook) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Declare that VBT block 252 is the "int15 hook". This is some VBIOS only juju so don't bother with a full definition. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-35-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 1cab8cce6a2c..3168c0bd5e23 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -188,6 +188,7 @@ enum bdb_block_id { BDB_COMPRESSION_PARAMETERS = 56, /* 213+ */ BDB_VSWING_PREEMPH = 57, /* 218+ */ BDB_GENERIC_DTD = 58, /* 229+ */ + BDB_INT15_HOOK = 252, /* VBIOS only */ BDB_SKIP = 254, /* VBIOS only */ }; -- cgit From cd6891f8e3714172cb2ff374d07cb6884b44b530 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 3 May 2024 15:24:49 +0300 Subject: drm/i915/bios: Define VBT block 253 (PRD Table) contents MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define the contents of VBT block 253 (PRD Table). Unfortunately the block has two definitions, with the cutoff supposedly happening on ICL vs. TGL. Also according to some notes it might be that the VBIOS (if that's still a thing) still uses the old definition even on TGL+. Quite the mess. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240503122449.27266-36-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 3168c0bd5e23..862c5923b83d 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -189,6 +189,7 @@ enum bdb_block_id { BDB_VSWING_PREEMPH = 57, /* 218+ */ BDB_GENERIC_DTD = 58, /* 229+ */ BDB_INT15_HOOK = 252, /* VBIOS only */ + BDB_PRD_TABLE = 253, BDB_SKIP = 254, /* VBIOS only */ }; @@ -1571,4 +1572,29 @@ struct bdb_generic_dtd { struct generic_dtd_entry dtd[]; /* up to 24 DTD's */ } __packed; +/* + * Block 253 - PRD Table + */ + +struct prd_entry_old { + u8 displays_attached; + u8 display_in_pipe_a; + u8 display_in_pipe_b; +} __packed; + +struct bdb_prd_table_old { + struct prd_entry_old list[0]; /* ???-216 */ + u16 num_entries; /* ???-216 */ +} __packed; + +struct prd_entry_new { + u16 primary_display; + u16 secondary_display; +} __packed; + +struct bdb_prd_table_new { + u16 num_entries; /* 217+ */ + struct prd_entry_new list[]; /* 217+ */ +} __packed; + #endif /* _INTEL_VBT_DEFS_H_ */ -- cgit From 0097ecd06d9dcf671da4bc643d215a4696f1c130 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 8 Apr 2024 22:06:09 +0300 Subject: drm/i915: Use drm_crtc_vblank_crtc() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace the open coded drm_crtc_vblank_crtc() with the real thing. Cc: intel-gfx@lists.freedesktop.org Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240408190611.24914-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crtc.c | 3 +-- drivers/gpu/drm/i915/display/intel_vblank.c | 16 +++++----------- 2 files changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 25593f6aae7d..339010384b86 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -78,8 +78,7 @@ void intel_wait_for_vblank_if_active(struct drm_i915_private *i915, u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) { - struct drm_device *dev = crtc->base.dev; - struct drm_vblank_crtc *vblank = &dev->vblank[drm_crtc_index(&crtc->base)]; + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); if (!crtc->active) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index baf7354cb6e2..951190bcbc50 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -132,8 +132,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc) static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct drm_vblank_crtc *vblank = - &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); const struct drm_display_mode *mode = &vblank->hwmode; u32 htotal = mode->crtc_htotal; u32 clock = mode->crtc_clock; @@ -178,8 +177,7 @@ static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc) */ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) { - struct drm_vblank_crtc *vblank = - &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); const struct drm_display_mode *mode = &vblank->hwmode; u32 vblank_start = mode->crtc_vblank_start; u32 vtotal = mode->crtc_vtotal; @@ -200,17 +198,14 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - const struct drm_display_mode *mode; - struct drm_vblank_crtc *vblank; + struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); + const struct drm_display_mode *mode = &vblank->hwmode; enum pipe pipe = crtc->pipe; int position, vtotal; if (!crtc->active) return 0; - vblank = &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; - mode = &vblank->hwmode; - if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP) return __intel_get_crtc_scanline_from_timestamp(crtc); @@ -254,8 +249,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline) { - const struct drm_vblank_crtc *vblank = - &crtc->base.dev->vblank[drm_crtc_index(&crtc->base)]; + const struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); const struct drm_display_mode *mode = &vblank->hwmode; int vtotal; -- cgit From 6907d4fa5ecac7b08fb5ee5536e48b0a3895be31 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 6 May 2024 21:33:31 +0300 Subject: drm/xe: Nuke xe's copy of intel_fbdev_fb.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For some reason xe and i915 each have an identical (fortunately) copy of intel_fbdev_fb.h. The xe copy actually only gets included by xe's intel_fbdev_fb.c, and the i915 copy by everyone else, include intel_fbdev.c which is the actual caller of the functions declared in the header. This means the xe and i915 headers are free to define/declare completely incompatible things and the build would still succeed as long as the symbol names match. That is not a good thing, so let's nuke xe's copy of the header so that everyone will use the same header, and be forced to agree on the same API/ABI. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240506183331.7720-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula Acked-by: Lucas De Marchi --- drivers/gpu/drm/xe/display/intel_fbdev_fb.h | 21 --------------------- 1 file changed, 21 deletions(-) delete mode 100644 drivers/gpu/drm/xe/display/intel_fbdev_fb.h diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.h b/drivers/gpu/drm/xe/display/intel_fbdev_fb.h deleted file mode 100644 index ea186772e0bb..000000000000 --- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.h +++ /dev/null @@ -1,21 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#ifndef __INTEL_FBDEV_FB_H__ -#define __INTEL_FBDEV_FB_H__ - -struct drm_fb_helper; -struct drm_fb_helper_surface_size; -struct drm_i915_gem_object; -struct drm_i915_private; -struct fb_info; -struct i915_vma; - -struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, - struct drm_fb_helper_surface_size *sizes); -int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info, - struct drm_i915_gem_object *obj, struct i915_vma *vma); - -#endif -- cgit From 6a3691ca4799997b90da50883c170edb67bd6c49 Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 7 May 2024 11:52:44 +0530 Subject: drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on HDMI Disable HDCP Line Rekeying when HDCP ver > 1.4 and when we are on HDMI TMDS operation for DISPLAY_VER >= 14. --v2 -Wa to be mentioned in comments not in commit message [Jani] -Remove blankline [Jani] --v3 -No need to write what is being done in comments when code is self explanatory [Jani] --v4 -Add comment regarding need of this WA when in TMDS mode [Chaitanya] -Write in chicken register for MTL [CHaitanya] --v5 -Fix comment [Chaitanya] -Use correct set and clear value in intel_de_rmw [Chaitanya] --v6 -No need to define C, D chicken bits it gets calculated [Animesh] Bspec: 49273 Bspec: 69964 Signed-off-by: Suraj Kandpal Reviewed-by: Chaitanya Kumar Borah Signed-off-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240507062243.1076047-2-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_hdcp.c | 23 +++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ 2 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index d5ed4c7dfbc0..02cbbbfd8e25 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -30,6 +30,27 @@ #define KEY_LOAD_TRIES 5 #define HDCP2_LC_RETRY_CNT 3 +/* WA: 16022217614 */ +static void +intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, + struct intel_hdcp *hdcp) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + + /* Here we assume HDMI is in TMDS mode of operation */ + if (encoder->type != INTEL_OUTPUT_HDMI) + return; + + if (DISPLAY_VER(dev_priv) >= 14) { + if (IS_METEORLAKE(dev_priv)) + intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), + 0, HDCP_LINE_REKEY_DISABLE); + else + intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder), + 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE); + } +} + static int intel_conn_to_vcpi(struct intel_atomic_state *state, struct intel_connector *connector) { @@ -2005,6 +2026,8 @@ static int _intel_hdcp2_enable(struct intel_atomic_state *state, connector->base.base.id, connector->base.name, hdcp->content_type); + intel_hdcp_disable_hdcp_line_rekeying(connector->encoder, hdcp); + ret = hdcp2_authenticate_and_encrypt(state, connector); if (ret) { drm_dbg_kms(&i915->drm, "HDCP2 Type%d Enabling Failed. (%d)\n", diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5670eee4a498..adea3882832d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3520,6 +3520,7 @@ #define DP_FEC_BS_JITTER_WA REG_BIT(15) #define PSR2_VSC_ENABLE_PROG_HEADER REG_BIT(12) #define DP_DSC_INSERT_SF_AT_EOL_WA REG_BIT(4) +#define HDCP_LINE_REKEY_DISABLE REG_BIT(0) #define DISP_ARB_CTL _MMIO(0x45000) #define DISP_FBC_MEMORY_WAKE REG_BIT(31) @@ -4521,6 +4522,7 @@ enum skl_power_gate { #define TRANS_DDI_EDP_INPUT_B_ONOFF (5 << 12) #define TRANS_DDI_EDP_INPUT_C_ONOFF (6 << 12) #define TRANS_DDI_EDP_INPUT_D_ONOFF (7 << 12) +#define TRANS_DDI_HDCP_LINE_REKEY_DISABLE REG_BIT(12) #define TRANS_DDI_MST_TRANSPORT_SELECT_MASK REG_GENMASK(11, 10) #define TRANS_DDI_MST_TRANSPORT_SELECT(trans) \ REG_FIELD_PREP(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, trans) -- cgit From 975a0f68f0d532d98ed3a8e385f82a46eea3d91a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 8 May 2024 18:47:47 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VRR_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/d86be64197d547085e857b09dacd21f4ee6b1517.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vrr.c | 13 ++++++++----- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 894ee97b3e1b..b1136aee775f 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -213,13 +213,15 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) 0, PIPE_VBLANK_WITH_DELAY); if (!crtc_state->vrr.flipline) { - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), 0); + intel_de_write(dev_priv, + TRANS_VRR_CTL(dev_priv, cpu_transcoder), 0); return; } intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), trans_vrr_ctl(crtc_state)); + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), + trans_vrr_ctl(crtc_state)); intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); } @@ -263,7 +265,7 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) VRR_VSYNC_END(crtc_state->vrr.vsync_end) | VRR_VSYNC_START(crtc_state->vrr.vsync_start)); - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); } @@ -276,7 +278,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->vrr.enable) return; - intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), trans_vrr_ctl(old_crtc_state)); intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder), VRR_STATUS_VRR_EN_LIVE, 1000); @@ -292,7 +294,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 trans_vrr_ctl, trans_vrr_vsync; - trans_vrr_ctl = intel_de_read(dev_priv, TRANS_VRR_CTL(cpu_transcoder)); + trans_vrr_ctl = intel_de_read(dev_priv, + TRANS_VRR_CTL(dev_priv, cpu_transcoder)); crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index adea3882832d..7c4a24d73d39 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1233,7 +1233,7 @@ #define _TRANS_VRR_CTL_B 0x61420 #define _TRANS_VRR_CTL_C 0x62420 #define _TRANS_VRR_CTL_D 0x63420 -#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) -- cgit From eadb8f40e1ed3c5cc36169d4ad9b7c49af98d950 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 8 May 2024 18:47:48 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAX Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_VMAX register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/6256642f1943b87650fdf600ef08f6d3b8617a87.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index b1136aee775f..d9024ccf6098 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -219,7 +219,8 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) } intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); - intel_de_write(dev_priv, TRANS_VRR_VMAX(cpu_transcoder), crtc_state->vrr.vmax - 1); + intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder), + crtc_state->vrr.vmax - 1); intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), trans_vrr_ctl(crtc_state)); intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); @@ -309,7 +310,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) { crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; - crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(cpu_transcoder)) + 1; + crtc_state->vrr.vmax = intel_de_read(dev_priv, + TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1; crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7c4a24d73d39..e24a6998babd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1247,7 +1247,7 @@ #define _TRANS_VRR_VMAX_B 0x61424 #define _TRANS_VRR_VMAX_C 0x62424 #define _TRANS_VRR_VMAX_D 0x63424 -#define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) +#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) #define VRR_VMAX_MASK REG_GENMASK(19, 0) #define _TRANS_VRR_VMIN_A 0x60434 -- cgit From d9d2f4419554b0ff1478d35c97740f00af0b05b0 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 8 May 2024 18:47:49 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VRR_VMIN Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_VMIN register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/ac1c6545a80e4cbdc98f54f8d67e69fd46cdcc91.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index d9024ccf6098..fd0f0794f6dc 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -218,7 +218,8 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) return; } - intel_de_write(dev_priv, TRANS_VRR_VMIN(cpu_transcoder), crtc_state->vrr.vmin - 1); + intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder), + crtc_state->vrr.vmin - 1); intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder), crtc_state->vrr.vmax - 1); intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), @@ -312,7 +313,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1; - crtc_state->vrr.vmin = intel_de_read(dev_priv, TRANS_VRR_VMIN(cpu_transcoder)) + 1; + crtc_state->vrr.vmin = intel_de_read(dev_priv, + TRANS_VRR_VMIN(dev_priv, cpu_transcoder)) + 1; } if (crtc_state->vrr.enable) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e24a6998babd..90f73b5ede3a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1254,7 +1254,7 @@ #define _TRANS_VRR_VMIN_B 0x61434 #define _TRANS_VRR_VMIN_C 0x62434 #define _TRANS_VRR_VMIN_D 0x63434 -#define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) +#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) #define VRR_VMIN_MASK REG_GENMASK(15, 0) #define _TRANS_VRR_VMAXSHIFT_A 0x60428 -- cgit From 3043b74f2ebd5809e0cc8aae3621f1e2c37711d3 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 8 May 2024 18:47:50 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VRR_VMAXSHIFT Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_VMAXSHIFT register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/6117aa8936a8e91c58a7a0bada21f266c79a0e5f.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 90f73b5ede3a..3b22b9fc0bf5 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1261,7 +1261,7 @@ #define _TRANS_VRR_VMAXSHIFT_B 0x61428 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 -#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(dev_priv, trans, \ +#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ _TRANS_VRR_VMAXSHIFT_A) #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) #define VRR_VMAXSHIFT_DEC REG_BIT(16) -- cgit From 8ae4afceed9e582bba0a27e4a2e69c2daf5b466b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 8 May 2024 18:47:51 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VRR_STATUS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_STATUS register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/57285c891b10d4827423c20563f2b4a2632e65c1.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index fd0f0794f6dc..05cbd6e4fc60 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -282,7 +282,8 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), trans_vrr_ctl(old_crtc_state)); - intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(cpu_transcoder), + intel_de_wait_for_clear(dev_priv, + TRANS_VRR_STATUS(dev_priv, cpu_transcoder), VRR_STATUS_VRR_EN_LIVE, 1000); intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3b22b9fc0bf5..eddd355ca814 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1271,7 +1271,7 @@ #define _TRANS_VRR_STATUS_B 0x6142C #define _TRANS_VRR_STATUS_C 0x6242C #define _TRANS_VRR_STATUS_D 0x6342C -#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) #define VRR_STATUS_VMAX_REACHED REG_BIT(31) #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) -- cgit From 2e6cb8775f5cf4867917d00d4293bc5537afbd46 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 8 May 2024 18:47:52 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VRR_VTOTAL_PREV Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_VTOTAL_PREV register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/de2c305ffef3df1112234baeae944b8dc84d0707.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index eddd355ca814..a4313f3180e0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1291,7 +1291,7 @@ #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 -#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(dev_priv, trans, \ +#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ _TRANS_VRR_VTOTAL_PREV_A) #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) -- cgit From e050e2acedcfd82b472cb40e9a2e7b762f7997ed Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 8 May 2024 18:47:53 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VRR_FLIPLINE Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_FLIPLINE register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/fd8b6a7c71ba908a55a7b40dc54a1d4cf920056c.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vrr.c | 6 ++++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 05cbd6e4fc60..e7709b06b92c 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -224,7 +224,8 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) crtc_state->vrr.vmax - 1); intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), trans_vrr_ctl(crtc_state)); - intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder), crtc_state->vrr.flipline - 1); + intel_de_write(dev_priv, TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder), + crtc_state->vrr.flipline - 1); } void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) @@ -311,7 +312,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) REG_FIELD_GET(VRR_CTL_PIPELINE_FULL_MASK, trans_vrr_ctl); if (trans_vrr_ctl & VRR_CTL_FLIP_LINE_EN) { - crtc_state->vrr.flipline = intel_de_read(dev_priv, TRANS_VRR_FLIPLINE(cpu_transcoder)) + 1; + crtc_state->vrr.flipline = intel_de_read(dev_priv, + TRANS_VRR_FLIPLINE(dev_priv, cpu_transcoder)) + 1; crtc_state->vrr.vmax = intel_de_read(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder)) + 1; crtc_state->vrr.vmin = intel_de_read(dev_priv, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a4313f3180e0..b581e0920c24 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1302,7 +1302,7 @@ #define _TRANS_VRR_FLIPLINE_B 0x61438 #define _TRANS_VRR_FLIPLINE_C 0x62438 #define _TRANS_VRR_FLIPLINE_D 0x63438 -#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(dev_priv, trans, \ +#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ _TRANS_VRR_FLIPLINE_A) #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) -- cgit From 48d47a40835376b9a8365d089ed626b7d79f3795 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 8 May 2024 18:47:54 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VRR_STATUS2 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_STATUS2 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/a8e095f1ac3b3d41343f7e6d8dd191e9e2a6d76a.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b581e0920c24..feb466288b9e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1310,7 +1310,7 @@ #define _TRANS_VRR_STATUS2_B 0x6143C #define _TRANS_VRR_STATUS2_C 0x6243C #define _TRANS_VRR_STATUS2_D 0x6343C -#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) +#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) #define _TRANS_PUSH_A 0x60A70 -- cgit From 0f5b235f87604ab745d918aaeca678fac42bfd7a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 8 May 2024 18:47:55 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_PUSH Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_PUSH register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/5b2a4eea42cf76830a829d8a543d877cad0fc52d.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++---- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index e7709b06b92c..5031b7ac8007 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -237,7 +237,7 @@ void intel_vrr_send_push(const struct intel_crtc_state *crtc_state) if (!crtc_state->vrr.enable) return; - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), + intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), TRANS_PUSH_EN | TRANS_PUSH_SEND); } @@ -250,7 +250,7 @@ bool intel_vrr_is_push_sent(const struct intel_crtc_state *crtc_state) if (!crtc_state->vrr.enable) return false; - return intel_de_read(dev_priv, TRANS_PUSH(cpu_transcoder)) & TRANS_PUSH_SEND; + return intel_de_read(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder)) & TRANS_PUSH_SEND; } void intel_vrr_enable(const struct intel_crtc_state *crtc_state) @@ -261,7 +261,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) if (!crtc_state->vrr.enable) return; - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), TRANS_PUSH_EN); + intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), + TRANS_PUSH_EN); if (HAS_AS_SDP(dev_priv)) intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), @@ -286,7 +287,7 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) intel_de_wait_for_clear(dev_priv, TRANS_VRR_STATUS(dev_priv, cpu_transcoder), VRR_STATUS_VRR_EN_LIVE, 1000); - intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); + intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 0); if (HAS_AS_SDP(dev_priv)) intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), 0); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index feb466288b9e..70c4110b76dd 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1317,7 +1317,7 @@ #define _TRANS_PUSH_B 0x61A70 #define _TRANS_PUSH_C 0x62A70 #define _TRANS_PUSH_D 0x63A70 -#define TRANS_PUSH(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) +#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) #define TRANS_PUSH_EN REG_BIT(31) #define TRANS_PUSH_SEND REG_BIT(30) -- cgit From deac76110108a362cf791780258a0c1474e5cb0e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 8 May 2024 18:47:56 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VRR_VSYNC Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VRR_VSYNC register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/61b464bedfd75a97ca214e066be5417d790ccb26.1715183162.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vrr.c | 9 ++++++--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5031b7ac8007..5f3657aa8313 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -265,7 +265,8 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) TRANS_PUSH_EN); if (HAS_AS_SDP(dev_priv)) - intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), + intel_de_write(dev_priv, + TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), VRR_VSYNC_END(crtc_state->vrr.vsync_end) | VRR_VSYNC_START(crtc_state->vrr.vsync_start)); @@ -290,7 +291,8 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) intel_de_write(dev_priv, TRANS_PUSH(dev_priv, cpu_transcoder), 0); if (HAS_AS_SDP(dev_priv)) - intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), 0); + intel_de_write(dev_priv, + TRANS_VRR_VSYNC(dev_priv, cpu_transcoder), 0); } void intel_vrr_get_config(struct intel_crtc_state *crtc_state) @@ -326,7 +328,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) if (HAS_AS_SDP(dev_priv)) { trans_vrr_vsync = - intel_de_read(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder)); + intel_de_read(dev_priv, + TRANS_VRR_VSYNC(dev_priv, cpu_transcoder)); crtc_state->vrr.vsync_start = REG_FIELD_GET(VRR_VSYNC_START_MASK, trans_vrr_vsync); crtc_state->vrr.vsync_end = diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 70c4110b76dd..256d73c25701 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1322,7 +1322,7 @@ #define TRANS_PUSH_SEND REG_BIT(30) #define _TRANS_VRR_VSYNC_A 0x60078 -#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) -- cgit From 7050ef3554190769843009661b48abca2d1e33b9 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 6 May 2024 15:57:10 +0300 Subject: drm/i915: Split gen2 vs. gen3 .max_stride() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Plane .max_stride() is already a vfunc so having one made up of two branches based on the display version is silly. Split i9xx_plane_max_stride() into gen2 vs. gen3 variants so that we get rid of said check. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240506125718.26001-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 32 +++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 3442264443e5..21303fa4f08f 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -741,23 +741,25 @@ i965_plane_max_stride(struct intel_plane *plane, } static unsigned int -i9xx_plane_max_stride(struct intel_plane *plane, +i915_plane_max_stride(struct intel_plane *plane, u32 pixel_format, u64 modifier, unsigned int rotation) { - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); + if (modifier == I915_FORMAT_MOD_X_TILED) + return 8 * 1024; + else + return 16 * 1024; +} - if (DISPLAY_VER(dev_priv) >= 3) { - if (modifier == I915_FORMAT_MOD_X_TILED) - return 8*1024; - else - return 16*1024; - } else { - if (plane->i9xx_plane == PLANE_C) - return 4*1024; - else - return 8*1024; - } +static unsigned int +i8xx_plane_max_stride(struct intel_plane *plane, + u32 pixel_format, u64 modifier, + unsigned int rotation) +{ + if (plane->i9xx_plane == PLANE_C) + return 4 * 1024; + else + return 8 * 1024; } static const struct drm_plane_funcs i965_plane_funcs = { @@ -854,8 +856,10 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) if (HAS_GMCH(dev_priv)) { if (DISPLAY_VER(dev_priv) >= 4) plane->max_stride = i965_plane_max_stride; + else if (DISPLAY_VER(dev_priv) == 3) + plane->max_stride = i915_plane_max_stride; else - plane->max_stride = i9xx_plane_max_stride; + plane->max_stride = i8xx_plane_max_stride; } else { if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) plane->max_stride = hsw_primary_max_stride; -- cgit From 1301ce346aae3236e9956a2f4b618bf559335819 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 6 May 2024 15:57:11 +0300 Subject: drm/i915: Clean up skl+ plane stride limits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit skl_plane_max_stride() is pretty messy. Streamline it and split it into clear skl+ vs. adl+ variants. TODO: Deal with icl and tgl strude limits properly Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240506125718.26001-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 65 ++++++++++++---------- 1 file changed, 37 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 0a8e781a3648..b8103d6ebc1f 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -461,41 +461,46 @@ static int icl_plane_max_height(const struct drm_framebuffer *fb, } static unsigned int -skl_plane_max_stride(struct intel_plane *plane, - u32 pixel_format, u64 modifier, - unsigned int rotation) +plane_max_stride(struct intel_plane *plane, + u32 pixel_format, u64 modifier, + unsigned int rotation, + unsigned int max_pixels, + unsigned int max_bytes) { - struct drm_i915_private *i915 = to_i915(plane->base.dev); const struct drm_format_info *info = drm_format_info(pixel_format); int cpp = info->cpp[0]; - int max_horizontal_pixels = 8192; - int max_stride_bytes; - - if (DISPLAY_VER(i915) >= 13) { - /* - * The stride in bytes must not exceed of the size - * of 128K bytes. For pixel formats of 64bpp will allow - * for a 16K pixel surface. - */ - max_stride_bytes = 131072; - if (cpp == 8) - max_horizontal_pixels = 16384; - else - max_horizontal_pixels = 65536; - } else { - /* - * "The stride in bytes must not exceed the - * of the size of 8K pixels and 32K bytes." - */ - max_stride_bytes = 32768; - } if (drm_rotation_90_or_270(rotation)) - return min(max_horizontal_pixels, max_stride_bytes / cpp); + return min(max_pixels, max_bytes / cpp); else - return min(max_horizontal_pixels * cpp, max_stride_bytes); + return min(max_pixels * cpp, max_bytes); +} + +static unsigned int +adl_plane_max_stride(struct intel_plane *plane, + u32 pixel_format, u64 modifier, + unsigned int rotation) +{ + unsigned int max_pixels = 65536; /* PLANE_OFFSET limit */ + unsigned int max_bytes = 128 * 1024; + + return plane_max_stride(plane, pixel_format, + modifier, rotation, + max_pixels, max_bytes); } +static unsigned int +skl_plane_max_stride(struct intel_plane *plane, + u32 pixel_format, u64 modifier, + unsigned int rotation) +{ + unsigned int max_pixels = 8192; /* PLANE_OFFSET limit */ + unsigned int max_bytes = 32 * 1024; + + return plane_max_stride(plane, pixel_format, + modifier, rotation, + max_pixels, max_bytes); +} /* Preoffset values for YUV to RGB Conversion */ #define PREOFF_YUV_TO_RGB_HI 0x1800 @@ -2357,7 +2362,11 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->min_cdclk = skl_plane_min_cdclk; } - plane->max_stride = skl_plane_max_stride; + if (DISPLAY_VER(dev_priv) >= 13) + plane->max_stride = adl_plane_max_stride; + else + plane->max_stride = skl_plane_max_stride; + if (DISPLAY_VER(dev_priv) >= 11) { plane->update_noarm = icl_plane_update_noarm; plane->update_arm = icl_plane_update_arm; -- cgit From c22a814bc2176f73fdf563e2cc2c4044c5d4a044 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 6 May 2024 15:57:12 +0300 Subject: drm/i915: Drop 'uses_fence' parameter from intel_pin_fb_obj_dpt() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fence regions are only relevant for GGTT, not DPT. Drop the pointless 'uses_fence' argument from intel_pin_fb_obj_dpt(). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240506125718.26001-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_fb_pin.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index be095cc696ba..2b50c1946c63 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -20,7 +20,6 @@ static struct i915_vma * intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, const struct i915_gtt_view *view, unsigned int alignment, - bool uses_fence, unsigned long *out_flags, struct i915_address_space *vm) { @@ -274,8 +273,8 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) plane_state->ggtt_vma = vma; vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, - alignment, false, - &plane_state->flags, intel_fb->dpt_vm); + alignment, &plane_state->flags, + intel_fb->dpt_vm); if (IS_ERR(vma)) { intel_dpt_unpin(intel_fb->dpt_vm); plane_state->ggtt_vma = NULL; -- cgit From e5f827c5796f1da029fdc36bb64df0f01c49d2d7 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 6 May 2024 15:57:13 +0300 Subject: drm/i915: Extract intel_plane_needs_physical() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Pull the "does this plane need a physical address?" check into a small helper. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240506125718.26001-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++ drivers/gpu/drm/i915/display/intel_atomic_plane.h | 1 + drivers/gpu/drm/i915/display/intel_fb_pin.c | 9 +++------ 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index b083b985d170..27224ecdc94c 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -144,6 +144,14 @@ intel_plane_destroy_state(struct drm_plane *plane, kfree(plane_state); } +bool intel_plane_needs_physical(struct intel_plane *plane) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + + return plane->id == PLANE_CURSOR && + DISPLAY_INFO(i915)->cursor_needs_physical; +} + unsigned int intel_adjusted_rate(const struct drm_rect *src, const struct drm_rect *dst, unsigned int rate) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.h b/drivers/gpu/drm/i915/display/intel_atomic_plane.h index 191dad0efc8e..e7a0699f17c8 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.h +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.h @@ -66,5 +66,6 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state); void intel_plane_set_invisible(struct intel_crtc_state *crtc_state, struct intel_plane_state *plane_state); void intel_plane_helper_add(struct intel_plane *plane); +bool intel_plane_needs_physical(struct intel_plane *plane); #endif /* __INTEL_ATOMIC_PLANE_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 2b50c1946c63..5b71d9488184 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -11,6 +11,7 @@ #include "gem/i915_gem_object.h" #include "i915_drv.h" +#include "intel_atomic_plane.h" #include "intel_display_types.h" #include "intel_dpt.h" #include "intel_fb.h" @@ -236,15 +237,11 @@ void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) int intel_plane_pin_fb(struct intel_plane_state *plane_state) { struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_i915_private *dev_priv = to_i915(plane->base.dev); struct drm_framebuffer *fb = plane_state->hw.fb; struct i915_vma *vma; - bool phys_cursor = - plane->id == PLANE_CURSOR && - DISPLAY_INFO(dev_priv)->cursor_needs_physical; if (!intel_fb_uses_dpt(fb)) { - vma = intel_pin_and_fence_fb_obj(fb, phys_cursor, + vma = intel_pin_and_fence_fb_obj(fb, intel_plane_needs_physical(plane), &plane_state->view.gtt, intel_plane_uses_fence(plane_state), &plane_state->flags); @@ -259,7 +256,7 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) * will trigger might_sleep() even if it won't actually sleep, * which is the case when the fb has already been pinned. */ - if (phys_cursor) + if (intel_plane_needs_physical(plane)) plane_state->phys_dma_addr = i915_gem_object_get_dma_address(intel_fb_obj(fb), 0); } else { -- cgit From 56ac367dbf8d72274b0a77b817e583b6d6171191 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 6 May 2024 15:57:14 +0300 Subject: drm/i915: Polish types in fb calculations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Be a bit more consistent in our use of integer types in the fb related calculatiosn. u32 we generally only use for ggtt offsets and such, and everything else can be regular (unsigned) ints. There's also an overabundance of consts for local variables in skl_check_main_surface() which is not something we generally do. So get rid of those while at it. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240506125718.26001-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_fb.c | 27 +++++++++---------- drivers/gpu/drm/i915/display/intel_fb_pin.c | 2 +- drivers/gpu/drm/i915/display/skl_universal_plane.c | 31 +++++++++++----------- 4 files changed, 30 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 21303fa4f08f..ea4d8ba55ad8 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -266,7 +266,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state) * despite them not using the linear offset anymore. */ if (DISPLAY_VER(dev_priv) >= 4 && fb->modifier == I915_FORMAT_MOD_X_TILED) { - u32 alignment = intel_surf_alignment(fb, 0); + unsigned int alignment = intel_surf_alignment(fb, 0); int cpp = fb->format->cpp[0]; while ((src_x + src_w) * cpp > plane_state->view.color_plane[0].mapping_stride) { diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index bf24f48a1e76..b6638726949d 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -1045,7 +1045,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *i915, int color_plane, unsigned int pitch, unsigned int rotation, - u32 alignment) + unsigned int alignment) { unsigned int cpp = fb->format->cpp[color_plane]; u32 offset, offset_aligned; @@ -1102,8 +1102,8 @@ u32 intel_plane_compute_aligned_offset(int *x, int *y, struct drm_i915_private *i915 = to_i915(intel_plane->base.dev); const struct drm_framebuffer *fb = state->hw.fb; unsigned int rotation = state->hw.rotation; - int pitch = state->view.color_plane[color_plane].mapping_stride; - u32 alignment; + unsigned int pitch = state->view.color_plane[color_plane].mapping_stride; + unsigned int alignment; if (intel_plane->id == PLANE_CURSOR) alignment = intel_cursor_alignment(i915); @@ -1120,8 +1120,7 @@ static int intel_fb_offset_to_xy(int *x, int *y, int color_plane) { struct drm_i915_private *i915 = to_i915(fb->dev); - unsigned int height; - u32 alignment, unused; + unsigned int height, alignment, unused; if (DISPLAY_VER(i915) >= 12 && !intel_fb_needs_pot_stride_remap(to_intel_framebuffer(fb)) && @@ -1508,8 +1507,8 @@ static u32 calc_plane_remap_info(const struct intel_framebuffer *fb, int color_p check_array_bounds(i915, view->gtt.remapped.plane, color_plane); if (view->gtt.remapped.plane_alignment) { - unsigned int aligned_offset = ALIGN(gtt_offset, - view->gtt.remapped.plane_alignment); + u32 aligned_offset = ALIGN(gtt_offset, + view->gtt.remapped.plane_alignment); size += aligned_offset - gtt_offset; gtt_offset = aligned_offset; @@ -1795,16 +1794,16 @@ u32 intel_fb_max_stride(struct drm_i915_private *dev_priv, return 128 * 1024; } -static u32 +static unsigned int intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane) { struct drm_i915_private *dev_priv = to_i915(fb->dev); - u32 tile_width; + unsigned int tile_width; if (is_surface_linear(fb, color_plane)) { - u32 max_stride = intel_plane_fb_max_stride(dev_priv, - fb->format->format, - fb->modifier); + unsigned int max_stride = intel_plane_fb_max_stride(dev_priv, + fb->format->format, + fb->modifier); /* * To make remapping with linear generally feasible @@ -2061,7 +2060,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); for (i = 0; i < fb->format->num_planes; i++) { - u32 stride_alignment; + unsigned int stride_alignment; if (mode_cmd->handles[i] != mode_cmd->handles[0]) { drm_dbg_kms(&dev_priv->drm, "bad plane %d handle\n", @@ -2078,7 +2077,7 @@ int intel_framebuffer_init(struct intel_framebuffer *intel_fb, } if (intel_fb_is_gen12_ccs_aux_plane(fb, i)) { - int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i); + unsigned int ccs_aux_stride = gen12_ccs_aux_stride(intel_fb, i); if (fb->pitches[i] != ccs_aux_stride) { drm_dbg_kms(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 5b71d9488184..041f09f76628 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -113,9 +113,9 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, struct drm_i915_gem_object *obj = intel_fb_obj(fb); intel_wakeref_t wakeref; struct i915_gem_ww_ctx ww; + unsigned int alignment; struct i915_vma *vma; unsigned int pinctl; - u32 alignment; int ret; if (drm_WARN_ON(dev, !i915_gem_object_is_framebuffer(obj))) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index b8103d6ebc1f..7b79704fa674 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1619,7 +1619,7 @@ skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, int aux_x = plane_state->view.color_plane[ccs_plane].x; int aux_y = plane_state->view.color_plane[ccs_plane].y; u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; - u32 alignment = intel_surf_alignment(fb, ccs_plane); + unsigned int alignment = intel_surf_alignment(fb, ccs_plane); int hsub; int vsub; @@ -1639,8 +1639,7 @@ skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, plane_state, ccs_plane, aux_offset, - aux_offset - - alignment); + aux_offset - alignment); aux_x = x * hsub + aux_x % hsub; aux_y = y * vsub + aux_y % vsub; } @@ -1662,10 +1661,10 @@ int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state, struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; - const int aux_plane = skl_main_to_aux_plane(fb, 0); - const u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; - const u32 alignment = intel_surf_alignment(fb, 0); - const int w = drm_rect_width(&plane_state->uapi.src) >> 16; + int aux_plane = skl_main_to_aux_plane(fb, 0); + u32 aux_offset = plane_state->view.color_plane[aux_plane].offset; + unsigned int alignment = intel_surf_alignment(fb, 0); + int w = drm_rect_width(&plane_state->uapi.src) >> 16; intel_add_fb_offsets(x, y, plane_state, 0); *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0); @@ -1712,16 +1711,16 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state) struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); struct drm_i915_private *dev_priv = to_i915(plane->base.dev); const struct drm_framebuffer *fb = plane_state->hw.fb; - const unsigned int rotation = plane_state->hw.rotation; + unsigned int rotation = plane_state->hw.rotation; int x = plane_state->uapi.src.x1 >> 16; int y = plane_state->uapi.src.y1 >> 16; - const int w = drm_rect_width(&plane_state->uapi.src) >> 16; - const int h = drm_rect_height(&plane_state->uapi.src) >> 16; - const int min_width = intel_plane_min_width(plane, fb, 0, rotation); - const int max_width = intel_plane_max_width(plane, fb, 0, rotation); - const int max_height = intel_plane_max_height(plane, fb, 0, rotation); - const int aux_plane = skl_main_to_aux_plane(fb, 0); - const u32 alignment = intel_surf_alignment(fb, 0); + int w = drm_rect_width(&plane_state->uapi.src) >> 16; + int h = drm_rect_height(&plane_state->uapi.src) >> 16; + int min_width = intel_plane_min_width(plane, fb, 0, rotation); + int max_width = intel_plane_max_width(plane, fb, 0, rotation); + int max_height = intel_plane_max_height(plane, fb, 0, rotation); + unsigned int alignment = intel_surf_alignment(fb, 0); + int aux_plane = skl_main_to_aux_plane(fb, 0); u32 offset; int ret; @@ -1809,7 +1808,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) if (ccs_plane) { u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset; - u32 alignment = intel_surf_alignment(fb, uv_plane); + unsigned int alignment = intel_surf_alignment(fb, uv_plane); if (offset > aux_offset) offset = intel_plane_adjust_aligned_offset(&x, &y, -- cgit From 79c520bc0fbb4e763316659d03d54196fbbb5f4a Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 7 May 2024 09:34:01 +0530 Subject: drm/i915/dp: Make has_gamut_metadata_dip() non static Make has_gamut_metadata_dip() non static so it can also be used to at other places eg in intel_dp_aux_backlight. So that we can check if HW is capable of sending SDP which helps us decide if we use AUX based HDR control or via SDP. --v2 -State reason the function is needed [Arun] Signed-off-by: Suraj Kandpal Reviewed-by: Arun R Murthy Signed-off-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240507040407.1056061-2-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 6 +++--- drivers/gpu/drm/i915/display/intel_dp.h | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 486361eb0070..6b8a94d0ca99 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -6364,8 +6364,8 @@ bool intel_dp_is_port_edp(struct drm_i915_private *i915, enum port port) return _intel_dp_is_port_edp(i915, devdata, port); } -static bool -has_gamut_metadata_dip(struct intel_encoder *encoder) +bool +intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); enum port port = encoder->port; @@ -6412,7 +6412,7 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect intel_attach_dp_colorspace_property(connector); } - if (has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) + if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base)) drm_connector_attach_hdr_output_metadata_property(connector); if (HAS_VRR(dev_priv)) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 106ecfde36d9..aad2223df2a3 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -196,5 +196,6 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, struct link_config_limits *limits); void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector); +bool intel_dp_has_gamut_metadata_dip(struct intel_encoder *encoder); #endif /* __INTEL_DP_H__ */ -- cgit From dabe0f9f2b17088c51a9c50b990fba19e9a7e1d4 Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 7 May 2024 09:34:02 +0530 Subject: drm/i915/dp: Rename intel struct inside intel_panel Rename intel to intel cap which is present inside panel.edp struct to make it more sensible to tell us what it contains. Signed-off-by: Suraj Kandpal Reviewed-by: Arun R Murthy Signed-off-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240507040407.1056061-3-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 14 +++++++------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index a06a154d587b..b7a385824f98 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -401,7 +401,7 @@ struct intel_panel { } vesa; struct { bool sdr_uses_aux; - } intel; + } intel_cap; } edp; struct backlight_device *device; diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 4f58efdc688a..44bc6fa04332 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -156,7 +156,7 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector) return false; } - panel->backlight.edp.intel.sdr_uses_aux = + panel->backlight.edp.intel_cap.sdr_uses_aux = tcon_cap[2] & INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAP; return true; @@ -178,7 +178,7 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe } if (!(tmp & INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE)) { - if (!panel->backlight.edp.intel.sdr_uses_aux) { + if (!panel->backlight.edp.intel_cap.sdr_uses_aux) { u32 pwm_level = panel->backlight.pwm_funcs->get(connector, pipe); return intel_backlight_level_from_pwm(connector, pwm_level); @@ -221,7 +221,7 @@ intel_dp_aux_hdr_set_backlight(const struct drm_connector_state *conn_state, u32 struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_panel *panel = &connector->panel; - if (panel->backlight.edp.intel.sdr_uses_aux) { + if (panel->backlight.edp.intel_cap.sdr_uses_aux) { intel_dp_aux_hdr_set_aux_backlight(conn_state, level); } else { const u32 pwm_level = intel_backlight_level_to_pwm(connector, level); @@ -251,7 +251,7 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state, } ctrl = old_ctrl; - if (panel->backlight.edp.intel.sdr_uses_aux) { + if (panel->backlight.edp.intel_cap.sdr_uses_aux) { ctrl |= INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE; intel_dp_aux_hdr_set_aux_backlight(conn_state, level); } else { @@ -275,7 +275,7 @@ intel_dp_aux_hdr_disable_backlight(const struct drm_connector_state *conn_state, struct intel_panel *panel = &connector->panel; /* Nothing to do for AUX based backlight controls */ - if (panel->backlight.edp.intel.sdr_uses_aux) + if (panel->backlight.edp.intel_cap.sdr_uses_aux) return; /* Note we want the actual pwm_level to be 0, regardless of pwm_min */ @@ -298,9 +298,9 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] SDR backlight is controlled through %s\n", connector->base.base.id, connector->base.name, - dpcd_vs_pwm_str(panel->backlight.edp.intel.sdr_uses_aux)); + dpcd_vs_pwm_str(panel->backlight.edp.intel_cap.sdr_uses_aux)); - if (!panel->backlight.edp.intel.sdr_uses_aux) { + if (!panel->backlight.edp.intel_cap.sdr_uses_aux) { ret = panel->backlight.pwm_funcs->setup(connector, pipe); if (ret < 0) { drm_err(&i915->drm, -- cgit From 7d24900c8460e6eef1bbfa5db1d5bbed7bfa45ef Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 7 May 2024 09:34:03 +0530 Subject: drm/i915/dp: Add TCON HDR capability checks Add checks to see the HDR capability of TCON panel. Signed-off-by: Suraj Kandpal Reviewed-by: Arun R Murthy Signed-off-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240507040407.1056061-4-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 5 +++++ drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 10 ++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index b7a385824f98..fec3de25ea54 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -401,6 +401,11 @@ struct intel_panel { } vesa; struct { bool sdr_uses_aux; + bool supports_2084_decode; + bool supports_2020_gamut; + bool supports_segmented_backlight; + bool supports_sdp_colorimetry; + bool supports_tone_mapping; } intel_cap; } edp; diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 44bc6fa04332..63d99afba398 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -158,6 +158,16 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector) panel->backlight.edp.intel_cap.sdr_uses_aux = tcon_cap[2] & INTEL_EDP_SDR_TCON_BRIGHTNESS_AUX_CAP; + panel->backlight.edp.intel_cap.supports_2084_decode = + tcon_cap[1] & INTEL_EDP_HDR_TCON_2084_DECODE_CAP; + panel->backlight.edp.intel_cap.supports_2020_gamut = + tcon_cap[1] & INTEL_EDP_HDR_TCON_2020_GAMUT_CAP; + panel->backlight.edp.intel_cap.supports_segmented_backlight = + tcon_cap[1] & INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_CAP; + panel->backlight.edp.intel_cap.supports_sdp_colorimetry = + tcon_cap[1] & INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_CAP; + panel->backlight.edp.intel_cap.supports_tone_mapping = + tcon_cap[1] & INTEL_EDP_HDR_TCON_TONE_MAPPING_CAP; return true; } -- cgit From 7ac0331344168414cea48ea377b93d78fea8644f Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 7 May 2024 09:34:04 +0530 Subject: drm/i915/dp: Fix Register bit naming Change INTEL_EDP_HDR_TCON_SDP_COLORIMETRY enable to INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX as this bit tells TCON to ignore DPCD colorimetry values and take the one's sent through SDP. --v2 -Fix typo in commit message [Arun] Signed-off-by: Suraj Kandpal Reviewed-by: Arun R Murthy Signed-off-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240507040407.1056061-5-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 63d99afba398..85205aeb3e9a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -74,7 +74,7 @@ # define INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE BIT(4) # define INTEL_EDP_HDR_TCON_SRGB_TO_PANEL_GAMUT_ENABLE BIT(5) /* Bit 6 is reserved */ -# define INTEL_EDP_HDR_TCON_SDP_COLORIMETRY_ENABLE BIT(7) +# define INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX BIT(7) #define INTEL_EDP_HDR_CONTENT_LUMINANCE 0x346 /* Pre-TGL+ */ #define INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE 0x34A -- cgit From f60ce4bd058cdc54bd7a2eb6067cbbf054cda1a2 Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 7 May 2024 09:34:05 +0530 Subject: drm/i915/dp: Drop comments on EDP HDR DPCD registers Drop comments for EDP HDR DPCD registers as the code and conditions will tell us what can be written where. --v2 -Drop the comments altogether instead of just renaming them [Sebastian] Signed-off-by: Suraj Kandpal Reviewed-by: Arun R Murthy Signed-off-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240507040407.1056061-6-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 85205aeb3e9a..1ee693df0563 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -69,14 +69,14 @@ #define INTEL_EDP_HDR_GETSET_CTRL_PARAMS 0x344 # define INTEL_EDP_HDR_TCON_2084_DECODE_ENABLE BIT(0) # define INTEL_EDP_HDR_TCON_2020_GAMUT_ENABLE BIT(1) -# define INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE BIT(2) /* Pre-TGL+ */ +# define INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE BIT(2) # define INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_ENABLE BIT(3) # define INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE BIT(4) # define INTEL_EDP_HDR_TCON_SRGB_TO_PANEL_GAMUT_ENABLE BIT(5) /* Bit 6 is reserved */ # define INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX BIT(7) -#define INTEL_EDP_HDR_CONTENT_LUMINANCE 0x346 /* Pre-TGL+ */ +#define INTEL_EDP_HDR_CONTENT_LUMINANCE 0x346 #define INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE 0x34A #define INTEL_EDP_SDR_LUMINANCE_LEVEL 0x352 #define INTEL_EDP_BRIGHTNESS_NITS_LSB 0x354 -- cgit From b0944c983d274ac485f44f1b0d3a31a52fc3f6e2 Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 7 May 2024 09:34:06 +0530 Subject: drm/i915/dp: Enable AUX based backlight for HDR As of now whenerver HDR is switched on we use the PWM to change the backlight as opposed to AUX based backlight changes in terms of nits. This patch writes to the appropriate DPCD registers to enable aux based backlight using values in nits. --v2 -Fix max_cll and max_fall assignment [Jani] -Fix the size sent in drm_dpcd_write [Jani] --v3 -Content Luminance needs to be sent only for pre-ICL after that it is directly picked up from hdr metadata [Ville] --v4 -Add checks for HDR TCON cap bits [Ville] -Check eotf of hdr_output_data and sets bits base of that value. --v5 -Fix capability check bits. -Check colorspace before setting BT2020 --v6 -Use intel_dp_has_gamut_dip to check if we have capability to send sdp [Ville] -Seprate filling of all hdr tcon related bits into it's own function. -Check eotf data to make sure we are in HDR mode [Sebastian] --v7 -Fix confusion function name for hdr mode check [Jani] -Fix the condition which tells us if we are in HDR mode or not [Sebastian] --v8 -Call fill_hdr_tcon_param unconditionally as some parameters may not be dependent on the fact if we are in hdr mode or not [Sebastian] -Fix some conditions after change in hdr mode check [Sebastian] Signed-off-by: Suraj Kandpal Reviewed-by: Sebastian Wick Signed-off-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240507040407.1056061-7-suraj.kandpal@intel.com --- .../gpu/drm/i915/display/intel_dp_aux_backlight.c | 98 +++++++++++++++++++--- 1 file changed, 87 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 1ee693df0563..da42f6704930 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -40,11 +40,6 @@ #include "intel_dp.h" #include "intel_dp_aux_backlight.h" -/* TODO: - * Implement HDR, right now we just implement the bare minimum to bring us back into SDR mode so we - * can make people's backlights work in the mean time - */ - /* * DP AUX registers for Intel's proprietary HDR backlight interface. We define * them here since we'll likely be the only driver to ever use these. @@ -127,9 +122,6 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector) if (ret != sizeof(tcon_cap)) return false; - if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP)) - return false; - drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Detected %s HDR backlight interface version %d\n", connector->base.base.id, connector->base.name, is_intel_tcon_cap(tcon_cap) ? "Intel" : "unsupported", tcon_cap[0]); @@ -137,6 +129,9 @@ intel_dp_aux_supports_hdr_backlight(struct intel_connector *connector) if (!is_intel_tcon_cap(tcon_cap)) return false; + if (!(tcon_cap[1] & INTEL_EDP_HDR_TCON_BRIGHTNESS_NITS_CAP)) + return false; + /* * If we don't have HDR static metadata there is no way to * runtime detect used range for nits based control. For now @@ -225,13 +220,27 @@ intel_dp_aux_hdr_set_aux_backlight(const struct drm_connector_state *conn_state, connector->base.base.id, connector->base.name); } +static bool +intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state) +{ + struct hdr_output_metadata *hdr_metadata; + + if (!conn_state->hdr_output_metadata) + return false; + + hdr_metadata = conn_state->hdr_output_metadata->data; + + return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084; +} + static void intel_dp_aux_hdr_set_backlight(const struct drm_connector_state *conn_state, u32 level) { struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_panel *panel = &connector->panel; - if (panel->backlight.edp.intel_cap.sdr_uses_aux) { + if (intel_dp_in_hdr_mode(conn_state) || + panel->backlight.edp.intel_cap.sdr_uses_aux) { intel_dp_aux_hdr_set_aux_backlight(conn_state, level); } else { const u32 pwm_level = intel_backlight_level_to_pwm(connector, level); @@ -240,6 +249,64 @@ intel_dp_aux_hdr_set_backlight(const struct drm_connector_state *conn_state, u32 } } +static void +intel_dp_aux_write_content_luminance(struct intel_connector *connector, + struct hdr_output_metadata *hdr_metadata) +{ + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + int ret; + u8 buf[4]; + + if (!intel_dp_has_gamut_metadata_dip(connector->encoder)) + return; + + buf[0] = hdr_metadata->hdmi_metadata_type1.max_cll & 0xFF; + buf[1] = (hdr_metadata->hdmi_metadata_type1.max_cll & 0xFF00) >> 8; + buf[2] = hdr_metadata->hdmi_metadata_type1.max_fall & 0xFF; + buf[3] = (hdr_metadata->hdmi_metadata_type1.max_fall & 0xFF00) >> 8; + + ret = drm_dp_dpcd_write(&intel_dp->aux, + INTEL_EDP_HDR_CONTENT_LUMINANCE, + buf, sizeof(buf)); + if (ret < 0) + drm_dbg_kms(&i915->drm, + "Content Luminance DPCD reg write failed, err:-%d\n", + ret); +} + +static void +intel_dp_aux_fill_hdr_tcon_params(const struct drm_connector_state *conn_state, u8 *ctrl) +{ + struct intel_connector *connector = to_intel_connector(conn_state->connector); + struct intel_panel *panel = &connector->panel; + struct drm_i915_private *i915 = to_i915(connector->base.dev); + + /* + * According to spec segmented backlight needs to be set whenever panel is in + * HDR mode. + */ + if (intel_dp_in_hdr_mode(conn_state)) { + *ctrl |= INTEL_EDP_HDR_TCON_SEGMENTED_BACKLIGHT_ENABLE; + *ctrl |= INTEL_EDP_HDR_TCON_2084_DECODE_ENABLE; + } + + if (DISPLAY_VER(i915) < 11) + *ctrl &= ~INTEL_EDP_HDR_TCON_TONE_MAPPING_ENABLE; + + if (panel->backlight.edp.intel_cap.supports_2020_gamut && + (conn_state->colorspace == DRM_MODE_COLORIMETRY_BT2020_RGB || + conn_state->colorspace == DRM_MODE_COLORIMETRY_BT2020_YCC || + conn_state->colorspace == DRM_MODE_COLORIMETRY_BT2020_CYCC)) + *ctrl |= INTEL_EDP_HDR_TCON_2020_GAMUT_ENABLE; + + if (panel->backlight.edp.intel_cap.supports_sdp_colorimetry && + intel_dp_has_gamut_metadata_dip(connector->encoder)) + *ctrl |= INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX; + else + *ctrl &= ~INTEL_EDP_HDR_TCON_SDP_OVERRIDE_AUX; +} + static void intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state, u32 level) @@ -248,6 +315,7 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state, struct intel_panel *panel = &connector->panel; struct drm_i915_private *i915 = to_i915(connector->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + struct hdr_output_metadata *hdr_metadata; int ret; u8 old_ctrl, ctrl; @@ -261,8 +329,10 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state, } ctrl = old_ctrl; - if (panel->backlight.edp.intel_cap.sdr_uses_aux) { + if (intel_dp_in_hdr_mode(conn_state) || + panel->backlight.edp.intel_cap.sdr_uses_aux) { ctrl |= INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE; + intel_dp_aux_hdr_set_aux_backlight(conn_state, level); } else { u32 pwm_level = intel_backlight_level_to_pwm(connector, level); @@ -272,10 +342,17 @@ intel_dp_aux_hdr_enable_backlight(const struct intel_crtc_state *crtc_state, ctrl &= ~INTEL_EDP_HDR_TCON_BRIGHTNESS_AUX_ENABLE; } + intel_dp_aux_fill_hdr_tcon_params(conn_state, &ctrl); + if (ctrl != old_ctrl && drm_dp_dpcd_writeb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, ctrl) != 1) drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to configure DPCD brightness controls\n", connector->base.base.id, connector->base.name); + + if (intel_dp_in_hdr_mode(conn_state)) { + hdr_metadata = conn_state->hdr_output_metadata->data; + intel_dp_aux_write_content_luminance(connector, hdr_metadata); + } } static void @@ -332,7 +409,6 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi connector->base.base.id, connector->base.name, panel->backlight.min, panel->backlight.max); - panel->backlight.level = intel_dp_aux_hdr_get_backlight(connector, pipe); panel->backlight.enabled = panel->backlight.level != 0; -- cgit From 84ceb14076592abd08d06d403ebe18aa60d5d505 Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 7 May 2024 09:34:07 +0530 Subject: drm/i915/dp: Write panel override luminance values Write panel override luminance values which helps the TCON decide if tone mapping needs to be enabled or not. Signed-off-by: Suraj Kandpal Reviewed-by: Sebastian Wick Signed-off-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240507040407.1056061-8-suraj.kandpal@intel.com --- .../gpu/drm/i915/display/intel_dp_aux_backlight.c | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index da42f6704930..8ce60d53dcde 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -374,6 +374,29 @@ static const char *dpcd_vs_pwm_str(bool aux) return aux ? "DPCD" : "PWM"; } +static void +intel_dp_aux_write_panel_luminance_override(struct intel_connector *connector) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_panel *panel = &connector->panel; + struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); + int ret; + u8 buf[4] = {}; + + buf[0] = panel->backlight.min & 0xFF; + buf[1] = (panel->backlight.min & 0xFF00) >> 8; + buf[2] = panel->backlight.max & 0xFF; + buf[3] = (panel->backlight.max & 0xFF00) >> 8; + + ret = drm_dp_dpcd_write(&intel_dp->aux, + INTEL_EDP_HDR_PANEL_LUMINANCE_OVERRIDE, + buf, sizeof(buf)); + if (ret < 0) + drm_dbg_kms(&i915->drm, + "Panel Luminance DPCD reg write failed, err:-%d\n", + ret); +} + static int intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pipe) { @@ -405,6 +428,8 @@ intel_dp_aux_hdr_setup_backlight(struct intel_connector *connector, enum pipe pi panel->backlight.min = 0; } + intel_dp_aux_write_panel_luminance_override(connector); + drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Using AUX HDR interface for backlight control (range %d..%d)\n", connector->base.base.id, connector->base.name, panel->backlight.min, panel->backlight.max); -- cgit From 56c12ec72ae8bd90cce1ea59dba2b93f986606be Mon Sep 17 00:00:00 2001 From: Uma Shankar Date: Thu, 9 May 2024 11:05:08 +0530 Subject: drm/i915: Implement Audio WA_14020863754 WA_14020863754: Corner case with Min Hblank Fix can cause audio hang Issue: Previously a fix was made to avoid issues with extremely small hblanks, called the "Min Hblank Fix". However, this can potentially cause an audio hang. Workaround : During "Audio Programming Sequence" Audio Enabling - When DP mode is enabled Set mmio offset 0x65F1C bit 18 = 1b, before step #1 "Enable audio Presence Detect" During "Audio Programming Sequence" Audio Disabling - When DP mode is enabled Clear mmio offset 0x65F1C bit 18 = 0b, after step #6 "Disable Audio PD (Presence Detect)" If not clearing PD bit, must also not clear 0x65F1C bit 18 (leave = 1b) v2: Update the platform checks (Jani Nikula) v3: Limited the WA to LNL and BMG, added a helper (Matt Roper) v4: Updated the bit naming, fixed redundant if statement Signed-off-by: Uma Shankar Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/20240509053508.2807834-1-uma.shankar@intel.com --- drivers/gpu/drm/i915/display/intel_audio.c | 15 +++++++++++++++ drivers/gpu/drm/i915/display/intel_audio_regs.h | 3 +++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index ed81e1466c4b..adde87900557 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -183,6 +183,15 @@ static const struct hdmi_aud_ncts hdmi_aud_ncts_36bpp[] = { { 192000, TMDS_445_5M, 20480, 371250 }, }; +/* + * WA_14020863754: Implement Audio Workaround + * Corner case with Min Hblank Fix can cause audio hang + */ +static bool needs_wa_14020863754(struct drm_i915_private *i915) +{ + return (DISPLAY_VER(i915) == 20 || IS_BATTLEMAGE(i915)); +} + /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ static u32 audio_config_hdmi_pixel_clock(const struct intel_crtc_state *crtc_state) { @@ -415,6 +424,9 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder, intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, AUDIO_OUTPUT_ENABLE(cpu_transcoder), 0); + if (needs_wa_14020863754(i915)) + intel_de_rmw(i915, AUD_CHICKENBIT_REG3, DACBE_DISABLE_MIN_HBLANK_FIX, 0); + mutex_unlock(&i915->display.audio.mutex); } @@ -540,6 +552,9 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder, if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP)) enable_audio_dsc_wa(encoder, crtc_state); + if (needs_wa_14020863754(i915)) + intel_de_rmw(i915, AUD_CHICKENBIT_REG3, 0, DACBE_DISABLE_MIN_HBLANK_FIX); + /* Enable audio presence detect */ intel_de_rmw(i915, HSW_AUD_PIN_ELD_CP_VLD, 0, AUDIO_OUTPUT_ENABLE(cpu_transcoder)); diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h index 88ea2740365d..4c31844d21df 100644 --- a/drivers/gpu/drm/i915/display/intel_audio_regs.h +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h @@ -164,4 +164,7 @@ _VLV_AUD_PORT_EN_D_DBG) #define VLV_AMP_MUTE (1 << 1) +#define AUD_CHICKENBIT_REG3 _MMIO(0x65F1C) +#define DACBE_DISABLE_MIN_HBLANK_FIX REG_BIT(18) + #endif /* __INTEL_AUDIO_REGS_H__ */ -- cgit From 67f5728a895454108383d46e14ccecf8db117ea3 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 6 May 2024 15:57:15 +0300 Subject: drm/i915: Constify 'fb' in during pinning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make the 'fb' pointers const in the pinning code. We never want to mutate these. Also nuke a few aliasing fb vs. intel_fb cases by just using the more specific type everywhere in the same function. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240506125718.26001-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula Acked-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_fb_pin.c | 33 ++++++++++++++--------------- drivers/gpu/drm/i915/display/intel_fb_pin.h | 2 +- drivers/gpu/drm/xe/display/xe_fb_pin.c | 8 +++---- 3 files changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 041f09f76628..7971656982a6 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -18,7 +18,7 @@ #include "intel_fb_pin.h" static struct i915_vma * -intel_pin_fb_obj_dpt(struct drm_framebuffer *fb, +intel_pin_fb_obj_dpt(const struct drm_framebuffer *fb, const struct i915_gtt_view *view, unsigned int alignment, unsigned long *out_flags, @@ -102,7 +102,7 @@ err: } struct i915_vma * -intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, +intel_pin_and_fence_fb_obj(const struct drm_framebuffer *fb, bool phys_cursor, const struct i915_gtt_view *view, bool uses_fence, @@ -237,11 +237,12 @@ void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) int intel_plane_pin_fb(struct intel_plane_state *plane_state) { struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane); - struct drm_framebuffer *fb = plane_state->hw.fb; + const struct intel_framebuffer *fb = + to_intel_framebuffer(plane_state->hw.fb); struct i915_vma *vma; - if (!intel_fb_uses_dpt(fb)) { - vma = intel_pin_and_fence_fb_obj(fb, intel_plane_needs_physical(plane), + if (!intel_fb_uses_dpt(&fb->base)) { + vma = intel_pin_and_fence_fb_obj(&fb->base, intel_plane_needs_physical(plane), &plane_state->view.gtt, intel_plane_uses_fence(plane_state), &plane_state->flags); @@ -258,22 +259,21 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) */ if (intel_plane_needs_physical(plane)) plane_state->phys_dma_addr = - i915_gem_object_get_dma_address(intel_fb_obj(fb), 0); + i915_gem_object_get_dma_address(intel_fb_obj(&fb->base), 0); } else { - struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); - unsigned int alignment = intel_surf_alignment(fb, 0); + unsigned int alignment = intel_surf_alignment(&fb->base, 0); - vma = intel_dpt_pin(intel_fb->dpt_vm, alignment / 512); + vma = intel_dpt_pin(fb->dpt_vm, alignment / 512); if (IS_ERR(vma)) return PTR_ERR(vma); plane_state->ggtt_vma = vma; - vma = intel_pin_fb_obj_dpt(fb, &plane_state->view.gtt, + vma = intel_pin_fb_obj_dpt(&fb->base, &plane_state->view.gtt, alignment, &plane_state->flags, - intel_fb->dpt_vm); + fb->dpt_vm); if (IS_ERR(vma)) { - intel_dpt_unpin(intel_fb->dpt_vm); + intel_dpt_unpin(fb->dpt_vm); plane_state->ggtt_vma = NULL; return PTR_ERR(vma); } @@ -288,22 +288,21 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) { - struct drm_framebuffer *fb = old_plane_state->hw.fb; + const struct intel_framebuffer *fb = + to_intel_framebuffer(old_plane_state->hw.fb); struct i915_vma *vma; - if (!intel_fb_uses_dpt(fb)) { + if (!intel_fb_uses_dpt(&fb->base)) { vma = fetch_and_zero(&old_plane_state->ggtt_vma); if (vma) intel_unpin_fb_vma(vma, old_plane_state->flags); } else { - struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); - vma = fetch_and_zero(&old_plane_state->dpt_vma); if (vma) intel_unpin_fb_vma(vma, old_plane_state->flags); vma = fetch_and_zero(&old_plane_state->ggtt_vma); if (vma) - intel_dpt_unpin(intel_fb->dpt_vm); + intel_dpt_unpin(fb->dpt_vm); } } diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h index de0efaa25905..edcebe75afd7 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -14,7 +14,7 @@ struct intel_plane_state; struct i915_gtt_view; struct i915_vma * -intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, +intel_pin_and_fence_fb_obj(const struct drm_framebuffer *fb, bool phys_cursor, const struct i915_gtt_view *view, bool uses_fence, diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 3e1ae37c4c8b..8b7ca3268834 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -77,7 +77,7 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, *dpt_ofs = ALIGN(*dpt_ofs, 4096); } -static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb, +static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb, const struct i915_gtt_view *view, struct i915_vma *vma) { @@ -181,7 +181,7 @@ write_ggtt_rotated(struct xe_bo *bo, struct xe_ggtt *ggtt, u32 *ggtt_ofs, u32 bo } } -static int __xe_pin_fb_vma_ggtt(struct intel_framebuffer *fb, +static int __xe_pin_fb_vma_ggtt(const struct intel_framebuffer *fb, const struct i915_gtt_view *view, struct i915_vma *vma) { @@ -249,7 +249,7 @@ out: return ret; } -static struct i915_vma *__xe_pin_fb_vma(struct intel_framebuffer *fb, +static struct i915_vma *__xe_pin_fb_vma(const struct intel_framebuffer *fb, const struct i915_gtt_view *view) { struct drm_device *dev = fb->base.dev; @@ -333,7 +333,7 @@ static void __xe_unpin_fb_vma(struct i915_vma *vma) } struct i915_vma * -intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, +intel_pin_and_fence_fb_obj(const struct drm_framebuffer *fb, bool phys_cursor, const struct i915_gtt_view *view, bool uses_fence, -- cgit From 6eca4dbe499890ce4340f49d309029e131e1e3e7 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 13:22:33 +0300 Subject: drm/i915: Change intel_fbdev_fb_alloc() return type MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change intel_fbdev_fb_alloc() to return struct intel_fb instead of struct drm_framebuffer. Let's us eliminate some annoying aliasing variables in the fbdev setup code. v2: Assing the results to the correct variable (Jani) Fix xe's copy Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510102233.25057-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula Acked-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_fbdev.c | 9 ++++----- drivers/gpu/drm/i915/display/intel_fbdev_fb.c | 6 +++--- drivers/gpu/drm/i915/display/intel_fbdev_fb.h | 4 ++-- drivers/gpu/drm/xe/display/intel_fbdev_fb.c | 9 +++++---- 4 files changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index bda702c2cab8..4bbbf481bb3a 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -207,13 +207,12 @@ static int intelfb_create(struct drm_fb_helper *helper, intel_fb = ifbdev->fb = NULL; } if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(&intel_fb->base))) { - struct drm_framebuffer *fb; drm_dbg_kms(&dev_priv->drm, "no BIOS fb, allocating a new one\n"); - fb = intel_fbdev_fb_alloc(helper, sizes); - if (IS_ERR(fb)) - return PTR_ERR(fb); - intel_fb = ifbdev->fb = to_intel_framebuffer(fb); + intel_fb = intel_fbdev_fb_alloc(helper, sizes); + if (IS_ERR(intel_fb)) + return PTR_ERR(intel_fb); + ifbdev->fb = intel_fb; } else { drm_dbg_kms(&dev_priv->drm, "re-using BIOS fb\n"); prealloc = true; diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c index 0665f943f65f..497525ef9668 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.c @@ -11,8 +11,8 @@ #include "intel_display_types.h" #include "intel_fbdev_fb.h" -struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, - struct drm_fb_helper_surface_size *sizes) +struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes) { struct drm_framebuffer *fb; struct drm_device *dev = helper->dev; @@ -63,7 +63,7 @@ struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, fb = intel_framebuffer_create(obj, &mode_cmd); i915_gem_object_put(obj); - return fb; + return to_intel_framebuffer(fb); } int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info, diff --git a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h index a395b2c65d33..4832fe688fbf 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev_fb.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev_fb.h @@ -13,8 +13,8 @@ struct drm_i915_private; struct fb_info; struct i915_vma; -struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, - struct drm_fb_helper_surface_size *sizes); +struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes); int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info, struct drm_i915_gem_object *obj, struct i915_vma *vma); diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c index 9e4bcfdbc7e5..f6bf5896ff1b 100644 --- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c +++ b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c @@ -13,8 +13,8 @@ #include "i915_drv.h" #include "intel_display_types.h" -struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, - struct drm_fb_helper_surface_size *sizes) +struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes) { struct drm_framebuffer *fb; struct drm_device *dev = helper->dev; @@ -70,10 +70,11 @@ struct drm_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, } drm_gem_object_put(intel_bo_to_drm_bo(obj)); - return fb; + + return to_intel_framebuffer(fb); err: - return fb; + return ERR_CAST(fb); } int intel_fbdev_fb_fill_info(struct drm_i915_private *i915, struct fb_info *info, -- cgit From 9e9402b64a9bb217be5a713758082808425b64ae Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 13:22:57 +0300 Subject: drm/i915: Cleanup fbdev fb setup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We use a mix of 'intel_fb' vs. 'ifbdev->fb' in the same function. Both should be pointing at the same thing. Make things less confusing by just getting existing fb from 'ifbdev->fb' at the start and then sticking with the local 'fb' (renamed from the 'intel_fb') until the very end. v2: rebase Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510102257.25096-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_fbdev.c | 38 ++++++++++++++++-------------- 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 4bbbf481bb3a..e898018ab76a 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -175,7 +175,7 @@ static int intelfb_create(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) { struct intel_fbdev *ifbdev = to_intel_fbdev(helper); - struct intel_framebuffer *intel_fb = ifbdev->fb; + struct intel_framebuffer *fb = ifbdev->fb; struct drm_device *dev = helper->dev; struct drm_i915_private *dev_priv = to_i915(dev); const struct i915_gtt_view view = { @@ -195,29 +195,30 @@ static int intelfb_create(struct drm_fb_helper *helper, if (ret) return ret; - if (intel_fb && - (sizes->fb_width > intel_fb->base.width || - sizes->fb_height > intel_fb->base.height)) { + ifbdev->fb = NULL; + + if (fb && + (sizes->fb_width > fb->base.width || + sizes->fb_height > fb->base.height)) { drm_dbg_kms(&dev_priv->drm, "BIOS fb too small (%dx%d), we require (%dx%d)," " releasing it\n", - intel_fb->base.width, intel_fb->base.height, + fb->base.width, fb->base.height, sizes->fb_width, sizes->fb_height); - drm_framebuffer_put(&intel_fb->base); - intel_fb = ifbdev->fb = NULL; + drm_framebuffer_put(&fb->base); + fb = NULL; } - if (!intel_fb || drm_WARN_ON(dev, !intel_fb_obj(&intel_fb->base))) { + if (!fb || drm_WARN_ON(dev, !intel_fb_obj(&fb->base))) { drm_dbg_kms(&dev_priv->drm, "no BIOS fb, allocating a new one\n"); - intel_fb = intel_fbdev_fb_alloc(helper, sizes); - if (IS_ERR(intel_fb)) - return PTR_ERR(intel_fb); - ifbdev->fb = intel_fb; + fb = intel_fbdev_fb_alloc(helper, sizes); + if (IS_ERR(fb)) + return PTR_ERR(fb); } else { drm_dbg_kms(&dev_priv->drm, "re-using BIOS fb\n"); prealloc = true; - sizes->fb_width = intel_fb->base.width; - sizes->fb_height = intel_fb->base.height; + sizes->fb_width = fb->base.width; + sizes->fb_height = fb->base.height; } wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); @@ -226,7 +227,7 @@ static int intelfb_create(struct drm_fb_helper *helper, * This also validates that any existing fb inherited from the * BIOS is suitable for own access. */ - vma = intel_pin_and_fence_fb_obj(&ifbdev->fb->base, false, + vma = intel_pin_and_fence_fb_obj(&fb->base, false, &view, false, &flags); if (IS_ERR(vma)) { ret = PTR_ERR(vma); @@ -240,11 +241,11 @@ static int intelfb_create(struct drm_fb_helper *helper, goto out_unpin; } - ifbdev->helper.fb = &ifbdev->fb->base; + ifbdev->helper.fb = &fb->base; info->fbops = &intelfb_ops; - obj = intel_fb_obj(&intel_fb->base); + obj = intel_fb_obj(&fb->base); ret = intel_fbdev_fb_fill_info(dev_priv, info, obj, vma); if (ret) @@ -262,8 +263,9 @@ static int intelfb_create(struct drm_fb_helper *helper, /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ drm_dbg_kms(&dev_priv->drm, "allocated %dx%d fb: 0x%08x\n", - ifbdev->fb->base.width, ifbdev->fb->base.height, + fb->base.width, fb->base.height, i915_ggtt_offset(vma)); + ifbdev->fb = fb; ifbdev->vma = vma; ifbdev->vma_flags = flags; -- cgit From c7df997b260919e4d18b2dee21cae6bcf765babc Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 6 May 2024 15:57:18 +0300 Subject: drm/i915: Rename the fb pinning functions to indicate the address space MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename the fb pinning functions such that their name directly informs us what gets pinned into which address space. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240506125718.26001-10-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula Acked-by: Lucas De Marchi --- drivers/gpu/drm/i915/display/intel_dpt.c | 6 ++-- drivers/gpu/drm/i915/display/intel_dpt.h | 6 ++-- drivers/gpu/drm/i915/display/intel_fb_pin.c | 46 +++++++++++++-------------- drivers/gpu/drm/i915/display/intel_fb_pin.h | 12 +++---- drivers/gpu/drm/i915/display/intel_fbdev.c | 8 ++--- drivers/gpu/drm/xe/display/xe_fb_pin.c | 12 +++---- drivers/gpu/drm/xe/display/xe_plane_initial.c | 4 +-- 7 files changed, 47 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpt.c b/drivers/gpu/drm/i915/display/intel_dpt.c index 786d3f2e94c7..73a1918e2537 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.c +++ b/drivers/gpu/drm/i915/display/intel_dpt.c @@ -121,8 +121,8 @@ static void dpt_cleanup(struct i915_address_space *vm) i915_gem_object_put(dpt->obj); } -struct i915_vma *intel_dpt_pin(struct i915_address_space *vm, - unsigned int alignment) +struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm, + unsigned int alignment) { struct drm_i915_private *i915 = vm->i915; struct i915_dpt *dpt = i915_vm_to_dpt(vm); @@ -173,7 +173,7 @@ struct i915_vma *intel_dpt_pin(struct i915_address_space *vm, return err ? ERR_PTR(err) : vma; } -void intel_dpt_unpin(struct i915_address_space *vm) +void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm) { struct i915_dpt *dpt = i915_vm_to_dpt(vm); diff --git a/drivers/gpu/drm/i915/display/intel_dpt.h b/drivers/gpu/drm/i915/display/intel_dpt.h index f467578a4950..ff18a525bfbe 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt.h +++ b/drivers/gpu/drm/i915/display/intel_dpt.h @@ -13,9 +13,9 @@ struct i915_vma; struct intel_framebuffer; void intel_dpt_destroy(struct i915_address_space *vm); -struct i915_vma *intel_dpt_pin(struct i915_address_space *vm, - unsigned int alignment); -void intel_dpt_unpin(struct i915_address_space *vm); +struct i915_vma *intel_dpt_pin_to_ggtt(struct i915_address_space *vm, + unsigned int alignment); +void intel_dpt_unpin_from_ggtt(struct i915_address_space *vm); void intel_dpt_suspend(struct drm_i915_private *i915); void intel_dpt_resume(struct drm_i915_private *i915); struct i915_address_space * diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.c b/drivers/gpu/drm/i915/display/intel_fb_pin.c index 7971656982a6..1acc11fa19f4 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.c +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.c @@ -18,11 +18,11 @@ #include "intel_fb_pin.h" static struct i915_vma * -intel_pin_fb_obj_dpt(const struct drm_framebuffer *fb, - const struct i915_gtt_view *view, - unsigned int alignment, - unsigned long *out_flags, - struct i915_address_space *vm) +intel_fb_pin_to_dpt(const struct drm_framebuffer *fb, + const struct i915_gtt_view *view, + unsigned int alignment, + unsigned long *out_flags, + struct i915_address_space *vm) { struct drm_device *dev = fb->dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -102,11 +102,11 @@ err: } struct i915_vma * -intel_pin_and_fence_fb_obj(const struct drm_framebuffer *fb, - bool phys_cursor, - const struct i915_gtt_view *view, - bool uses_fence, - unsigned long *out_flags) +intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, + bool phys_cursor, + const struct i915_gtt_view *view, + bool uses_fence, + unsigned long *out_flags) { struct drm_device *dev = fb->dev; struct drm_i915_private *dev_priv = to_i915(dev); @@ -226,7 +226,7 @@ err: return vma; } -void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) +void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) { if (flags & PLANE_HAS_FENCE) i915_vma_unpin_fence(vma); @@ -242,10 +242,10 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) struct i915_vma *vma; if (!intel_fb_uses_dpt(&fb->base)) { - vma = intel_pin_and_fence_fb_obj(&fb->base, intel_plane_needs_physical(plane), - &plane_state->view.gtt, - intel_plane_uses_fence(plane_state), - &plane_state->flags); + vma = intel_fb_pin_to_ggtt(&fb->base, intel_plane_needs_physical(plane), + &plane_state->view.gtt, + intel_plane_uses_fence(plane_state), + &plane_state->flags); if (IS_ERR(vma)) return PTR_ERR(vma); @@ -263,17 +263,17 @@ int intel_plane_pin_fb(struct intel_plane_state *plane_state) } else { unsigned int alignment = intel_surf_alignment(&fb->base, 0); - vma = intel_dpt_pin(fb->dpt_vm, alignment / 512); + vma = intel_dpt_pin_to_ggtt(fb->dpt_vm, alignment / 512); if (IS_ERR(vma)) return PTR_ERR(vma); plane_state->ggtt_vma = vma; - vma = intel_pin_fb_obj_dpt(&fb->base, &plane_state->view.gtt, - alignment, &plane_state->flags, - fb->dpt_vm); + vma = intel_fb_pin_to_dpt(&fb->base, &plane_state->view.gtt, + alignment, &plane_state->flags, + fb->dpt_vm); if (IS_ERR(vma)) { - intel_dpt_unpin(fb->dpt_vm); + intel_dpt_unpin_from_ggtt(fb->dpt_vm); plane_state->ggtt_vma = NULL; return PTR_ERR(vma); } @@ -295,14 +295,14 @@ void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state) if (!intel_fb_uses_dpt(&fb->base)) { vma = fetch_and_zero(&old_plane_state->ggtt_vma); if (vma) - intel_unpin_fb_vma(vma, old_plane_state->flags); + intel_fb_unpin_vma(vma, old_plane_state->flags); } else { vma = fetch_and_zero(&old_plane_state->dpt_vma); if (vma) - intel_unpin_fb_vma(vma, old_plane_state->flags); + intel_fb_unpin_vma(vma, old_plane_state->flags); vma = fetch_and_zero(&old_plane_state->ggtt_vma); if (vma) - intel_dpt_unpin(fb->dpt_vm); + intel_dpt_unpin_from_ggtt(fb->dpt_vm); } } diff --git a/drivers/gpu/drm/i915/display/intel_fb_pin.h b/drivers/gpu/drm/i915/display/intel_fb_pin.h index edcebe75afd7..3f8245edcd15 100644 --- a/drivers/gpu/drm/i915/display/intel_fb_pin.h +++ b/drivers/gpu/drm/i915/display/intel_fb_pin.h @@ -14,13 +14,13 @@ struct intel_plane_state; struct i915_gtt_view; struct i915_vma * -intel_pin_and_fence_fb_obj(const struct drm_framebuffer *fb, - bool phys_cursor, - const struct i915_gtt_view *view, - bool uses_fence, - unsigned long *out_flags); +intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, + bool phys_cursor, + const struct i915_gtt_view *view, + bool uses_fence, + unsigned long *out_flags); -void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags); +void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags); int intel_plane_pin_fb(struct intel_plane_state *plane_state); void intel_plane_unpin_fb(struct intel_plane_state *old_plane_state); diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index e898018ab76a..5ad0b4c8a0fd 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -146,7 +146,7 @@ static void intel_fbdev_fb_destroy(struct fb_info *info) * the info->screen_base mmaping. Leaking the VMA is simpler than * trying to rectify all the possible error paths leading here. */ - intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags); + intel_fb_unpin_vma(ifbdev->vma, ifbdev->vma_flags); drm_framebuffer_remove(&ifbdev->fb->base); drm_client_release(&fb_helper->client); @@ -227,8 +227,8 @@ static int intelfb_create(struct drm_fb_helper *helper, * This also validates that any existing fb inherited from the * BIOS is suitable for own access. */ - vma = intel_pin_and_fence_fb_obj(&fb->base, false, - &view, false, &flags); + vma = intel_fb_pin_to_ggtt(&fb->base, false, + &view, false, &flags); if (IS_ERR(vma)) { ret = PTR_ERR(vma); goto out_unlock; @@ -274,7 +274,7 @@ static int intelfb_create(struct drm_fb_helper *helper, return 0; out_unpin: - intel_unpin_fb_vma(vma, flags); + intel_fb_unpin_vma(vma, flags); out_unlock: intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); return ret; diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 8b7ca3268834..36e15c4961c1 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -333,18 +333,18 @@ static void __xe_unpin_fb_vma(struct i915_vma *vma) } struct i915_vma * -intel_pin_and_fence_fb_obj(const struct drm_framebuffer *fb, - bool phys_cursor, - const struct i915_gtt_view *view, - bool uses_fence, - unsigned long *out_flags) +intel_fb_pin_to_ggtt(const struct drm_framebuffer *fb, + bool phys_cursor, + const struct i915_gtt_view *view, + bool uses_fence, + unsigned long *out_flags) { *out_flags = 0; return __xe_pin_fb_vma(to_intel_framebuffer(fb), view); } -void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags) +void intel_fb_unpin_vma(struct i915_vma *vma, unsigned long flags) { __xe_unpin_fb_vma(vma); } diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c index 9693c56d386b..9eaa29e733e1 100644 --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c @@ -211,8 +211,8 @@ intel_find_initial_plane_obj(struct intel_crtc *crtc, intel_fb_fill_view(to_intel_framebuffer(fb), plane_state->uapi.rotation, &plane_state->view); - vma = intel_pin_and_fence_fb_obj(fb, false, &plane_state->view.gtt, - false, &plane_state->flags); + vma = intel_fb_pin_to_ggtt(fb, false, &plane_state->view.gtt, + false, &plane_state->flags); if (IS_ERR(vma)) goto nofb; -- cgit From bd7247e6df124dc9dfe048e319f364e0613d54c3 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 May 2024 12:43:12 +0300 Subject: drm/xe/display: remove unused xe->enabled_irq_mask The xe->enabled_irq_mask member has never been used for anything. Acked-by: Lucas De Marchi Reviewed-by: Himal Prasad Ghimiray Link: https://patchwork.freedesktop.org/patch/msgid/20240510094313.3422982-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/xe/display/xe_display.c | 1 - drivers/gpu/drm/xe/xe_device_types.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index 0de0566e5b39..fbe2c2eddea9 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -97,7 +97,6 @@ int xe_display_create(struct xe_device *xe) xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0); drmm_mutex_init(&xe->drm, &xe->sb_lock); - xe->enabled_irq_mask = ~0; return drmm_add_action_or_reset(&xe->drm, display_destroy, NULL); } diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index 14144a3814fc..fd343a1cb9b5 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -505,8 +505,6 @@ struct xe_device { /* only to allow build, not used functionally */ u32 irq_mask; - u32 enabled_irq_mask; - struct intel_uncore { spinlock_t lock; } uncore; -- cgit From 8a5fc5f0031edcc9fef547866547b748c2bdb039 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 May 2024 12:43:13 +0300 Subject: drm/xe/display: remove unused xe->sb_lock Nothing in xe needs xe->sb_lock. None of the i915 display code using ->sb_lock gets built with xe, and in any case that would be wrong as xe uses gt->pcode.lock for this. Acked-by: Lucas De Marchi Reviewed-by: Himal Prasad Ghimiray Link: https://patchwork.freedesktop.org/patch/msgid/20240510094313.3422982-2-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/xe/display/xe_display.c | 2 -- drivers/gpu/drm/xe/xe_device_types.h | 3 --- 2 files changed, 5 deletions(-) diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index fbe2c2eddea9..a2c39bcc7677 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -96,8 +96,6 @@ int xe_display_create(struct xe_device *xe) xe->display.hotplug.dp_wq = alloc_ordered_workqueue("xe-dp", 0); - drmm_mutex_init(&xe->drm, &xe->sb_lock); - return drmm_add_action_or_reset(&xe->drm, display_destroy, NULL); } diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index fd343a1cb9b5..7674afbb3a30 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -499,9 +499,6 @@ struct xe_device { /* To shut up runtime pm macros.. */ struct xe_runtime_pm {} runtime_pm; - /* For pcode */ - struct mutex sb_lock; - /* only to allow build, not used functionally */ u32 irq_mask; -- cgit From ce698dcf10d5d85c712b8cf3140d125e3112daf9 Mon Sep 17 00:00:00 2001 From: Luca Coelho Date: Fri, 10 May 2024 12:05:02 +0300 Subject: Documentation/i915: remove kernel-doc for DMC wakelocks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The function descriptions are optional and have not yet been added to the DMC wakelock code, so we shouldn't try to use it. Since this is a regression, remove the kernel-doc entry for DMC wakelocks for now. The proper documentation will be added in a future patch. Fixes: 765425f598c2 ("drm/i915/display: add support for DMC wakelocks") Signed-off-by: Luca Coelho Reviewed-by: Jani Nikula Signed-off-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240510090502.667556-1-luciano.coelho@intel.com --- Documentation/gpu/i915.rst | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 17261ba18313..3113e36f14cf 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -210,9 +210,6 @@ DMC wakelock support .. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c :doc: DMC wakelock support -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c - :internal: - Video BIOS Table (VBT) ---------------------- -- cgit From 1e52db8a439b147f314681129f9ee33f16900767 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:12 +0300 Subject: drm/i915/psr: Rename has_psr2 as has_sel_update MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are going to reuse has_psr2 for panel_replay as well. Rename it as has_sel_update to avoid confusion. v3: do not add has_psr check into psr2 case in intel_dp_compute_vsc_sdp v2: Rebase Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-2-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++----- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index ccaa4cb2809b..1da4c122c52e 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -251,9 +251,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, drm_printf(&p, "sdp split: %s\n", str_enabled_disabled(pipe_config->sdp_split_enable)); - drm_printf(&p, "psr: %s, psr2: %s, panel replay: %s, selective fetch: %s\n", + drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n", str_enabled_disabled(pipe_config->has_psr), - str_enabled_disabled(pipe_config->has_psr2), + str_enabled_disabled(pipe_config->has_sel_update), str_enabled_disabled(pipe_config->has_panel_replay), str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ef986b508431..4035b3ec311d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5320,7 +5320,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, */ if (current_config->has_panel_replay || pipe_config->has_panel_replay) { PIPE_CONF_CHECK_BOOL(has_psr); - PIPE_CONF_CHECK_BOOL(has_psr2); + PIPE_CONF_CHECK_BOOL(has_sel_update); PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); PIPE_CONF_CHECK_BOOL(enable_psr2_su_region_et); PIPE_CONF_CHECK_BOOL(has_panel_replay); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index fec3de25ea54..10e41e67b569 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1194,7 +1194,7 @@ struct intel_crtc_state { /* PSR is supported but might not be enabled due the lack of enabled planes */ bool has_psr; - bool has_psr2; + bool has_sel_update; bool enable_psr2_sel_fetch; bool enable_psr2_su_region_et; bool req_psr2_sdp_prior_scanline; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 6b8a94d0ca99..a6ddeadb61db 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2663,7 +2663,7 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, vsc); - } else if (crtc_state->has_psr2) { + } else if (crtc_state->has_sel_update) { /* * [PSR2 without colorimetry] * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 151dcd0c45b6..984f13d8c0c8 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1251,7 +1251,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 */ - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_psr2) { + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 595eb1b3b6c6..74e2ee9a48fa 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -653,7 +653,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); u8 dpcd_val = DP_PSR_ENABLE; - if (crtc_state->has_psr2) { + if (crtc_state->has_sel_update) { /* Enable ALPM at sink for psr2 */ if (!crtc_state->has_panel_replay) { drm_dp_dpcd_writeb(&intel_dp->aux, @@ -1644,7 +1644,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (!crtc_state->has_psr) return; - crtc_state->has_psr2 = intel_psr2_config_valid(intel_dp, crtc_state); + crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, crtc_state); } void intel_psr_get_config(struct intel_encoder *encoder, @@ -1677,7 +1677,7 @@ void intel_psr_get_config(struct intel_encoder *encoder, pipe_config->has_psr = true; } - pipe_config->has_psr2 = intel_dp->psr.psr2_enabled; + pipe_config->has_sel_update = intel_dp->psr.psr2_enabled; pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); if (!intel_dp->psr.psr2_enabled) @@ -1971,7 +1971,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); - intel_dp->psr.psr2_enabled = crtc_state->has_psr2; + intel_dp->psr.psr2_enabled = crtc_state->has_sel_update; intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; intel_dp->psr.busy_frontbuffer_bits = 0; intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; @@ -2702,7 +2702,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); needs_to_disable |= !new_crtc_state->has_psr; needs_to_disable |= !new_crtc_state->active_planes; - needs_to_disable |= new_crtc_state->has_psr2 != psr->psr2_enabled; + needs_to_disable |= new_crtc_state->has_sel_update != psr->psr2_enabled; needs_to_disable |= DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled; -- cgit From d07a578703dbf839ea39bffc425fba2321f45543 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:13 +0300 Subject: drm/i915/display: Do not print "psr: enabled" for on Panel Replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After setting has_psr for panel replay as well crtc state dump is improperly printing "psr: enabled" for Panel Replay as well. Fix this by checking also has_panel_replay. Fixes: 5afa6e496098 ("drm/i915/psr: Set intel_crtc_state->has_psr on panel replay as well") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-3-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_crtc_state_dump.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 1da4c122c52e..bddcc9edeab4 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -252,7 +252,8 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, str_enabled_disabled(pipe_config->sdp_split_enable)); drm_printf(&p, "psr: %s, selective update: %s, panel replay: %s, selective fetch: %s\n", - str_enabled_disabled(pipe_config->has_psr), + str_enabled_disabled(pipe_config->has_psr && + !pipe_config->has_panel_replay), str_enabled_disabled(pipe_config->has_sel_update), str_enabled_disabled(pipe_config->has_panel_replay), str_enabled_disabled(pipe_config->enable_psr2_sel_fetch)); -- cgit From 56e65164b832d777c1f0a8af47af8cc26e6506d5 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:14 +0300 Subject: drm/i915/dp: Use always vsc revision 0x6 for Panel Replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are about to enable Panel Replay Selective update mode. Vsc revision 0x6 for Panel Replay no matter if it is selective update or full frame update mode. Take this into account when preparing VSC SDP package. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-4-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a6ddeadb61db..098454262609 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2663,14 +2663,6 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, vsc); - } else if (crtc_state->has_sel_update) { - /* - * [PSR2 without colorimetry] - * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 - * 3D stereo + PSR/PSR2 + Y-coordinate. - */ - vsc->revision = 0x4; - vsc->length = 0xe; } else if (crtc_state->has_panel_replay) { /* * [Panel Replay without colorimetry info] @@ -2679,6 +2671,14 @@ static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, */ vsc->revision = 0x6; vsc->length = 0x10; + } else if (crtc_state->has_sel_update) { + /* + * [PSR2 without colorimetry] + * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 + * 3D stereo + PSR/PSR2 + Y-coordinate. + */ + vsc->revision = 0x4; + vsc->length = 0xe; } else { /* * [PSR1] -- cgit From ba7cf33f233efcd7e0a20ae8a73ffe75bf7337dc Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:15 +0300 Subject: drm/i915/psr: Rename psr2_enabled as sel_update_enabled MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are about to reuse psr2_enabled for panel replay as well. Rename it as sel_update_enabled to avoid confusion. v3: Rebase v2: Rebase Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-5-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 52 +++++++++++----------- 2 files changed, 27 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 10e41e67b569..e140f79da006 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1700,7 +1700,7 @@ struct intel_psr { unsigned int busy_frontbuffer_bits; bool sink_psr2_support; bool link_standby; - bool psr2_enabled; + bool sel_update_enabled; bool psr2_sel_fetch_enabled; bool psr2_sel_fetch_cff_enabled; bool req_psr2_sdp_prior_scanline; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 74e2ee9a48fa..820499f420ba 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -356,12 +356,12 @@ static void psr_irq_control(struct intel_dp *intel_dp) } static void psr_event_print(struct drm_i915_private *i915, - u32 val, bool psr2_enabled) + u32 val, bool sel_update_enabled) { drm_dbg_kms(&i915->drm, "PSR exit events: 0x%x\n", val); if (val & PSR_EVENT_PSR2_WD_TIMER_EXPIRE) drm_dbg_kms(&i915->drm, "\tPSR2 watchdog timer expired\n"); - if ((val & PSR_EVENT_PSR2_DISABLED) && psr2_enabled) + if ((val & PSR_EVENT_PSR2_DISABLED) && sel_update_enabled) drm_dbg_kms(&i915->drm, "\tPSR2 disabled\n"); if (val & PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) drm_dbg_kms(&i915->drm, "\tSU dirty FIFO underrun\n"); @@ -389,7 +389,7 @@ static void psr_event_print(struct drm_i915_private *i915, drm_dbg_kms(&i915->drm, "\tVBI enabled\n"); if (val & PSR_EVENT_LPSP_MODE_EXIT) drm_dbg_kms(&i915->drm, "\tLPSP mode exited\n"); - if ((val & PSR_EVENT_PSR_DISABLE) && !psr2_enabled) + if ((val & PSR_EVENT_PSR_DISABLE) && !sel_update_enabled) drm_dbg_kms(&i915->drm, "\tPSR disabled\n"); } @@ -419,7 +419,7 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) PSR_EVENT(dev_priv, cpu_transcoder), 0, 0); - psr_event_print(dev_priv, val, intel_dp->psr.psr2_enabled); + psr_event_print(dev_priv, val, intel_dp->psr.sel_update_enabled); } } @@ -1677,10 +1677,10 @@ void intel_psr_get_config(struct intel_encoder *encoder, pipe_config->has_psr = true; } - pipe_config->has_sel_update = intel_dp->psr.psr2_enabled; + pipe_config->has_sel_update = intel_dp->psr.sel_update_enabled; pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); - if (!intel_dp->psr.psr2_enabled) + if (!intel_dp->psr.sel_update_enabled) goto unlock; if (HAS_PSR2_SEL_FETCH(dev_priv)) { @@ -1718,7 +1718,7 @@ static void intel_psr_activate(struct intel_dp *intel_dp) /* psr1, psr2 and panel-replay are mutually exclusive.*/ if (intel_dp->psr.panel_replay_enabled) dg2_activate_panel_replay(intel_dp); - else if (intel_dp->psr.psr2_enabled) + else if (intel_dp->psr.sel_update_enabled) hsw_activate_psr2(intel_dp); else hsw_activate_psr1(intel_dp); @@ -1777,7 +1777,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) struct intel_psr *psr = &intel_dp->psr; u32 alpm_ctl; - if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.psr2_enabled && + if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && !intel_dp_is_edp(intel_dp))) return; @@ -1905,7 +1905,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, */ wm_optimization_wa(intel_dp, crtc_state); - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.sel_update_enabled) { if (DISPLAY_VER(dev_priv) == 9) intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder), 0, PSR2_VSC_ENABLE_PROG_HEADER | @@ -1971,7 +1971,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_WARN_ON(&dev_priv->drm, intel_dp->psr.enabled); - intel_dp->psr.psr2_enabled = crtc_state->has_sel_update; + intel_dp->psr.sel_update_enabled = crtc_state->has_sel_update; intel_dp->psr.panel_replay_enabled = crtc_state->has_panel_replay; intel_dp->psr.busy_frontbuffer_bits = 0; intel_dp->psr.pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe; @@ -1992,7 +1992,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, drm_dbg_kms(&dev_priv->drm, "Enabling Panel Replay\n"); } else { drm_dbg_kms(&dev_priv->drm, "Enabling PSR%s\n", - intel_dp->psr.psr2_enabled ? "2" : "1"); + intel_dp->psr.sel_update_enabled ? "2" : "1"); /* * Panel replay has to be enabled before link training: doing it @@ -2033,7 +2033,7 @@ static void intel_psr_exit(struct intel_dp *intel_dp) if (intel_dp->psr.panel_replay_enabled) { intel_de_rmw(dev_priv, TRANS_DP2_CTL(intel_dp->psr.transcoder), TRANS_DP2_PANEL_REPLAY_ENABLE, 0); - } else if (intel_dp->psr.psr2_enabled) { + } else if (intel_dp->psr.sel_update_enabled) { tgl_disallow_dc3co_on_psr2_exit(intel_dp); val = intel_de_rmw(dev_priv, @@ -2057,7 +2057,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) i915_reg_t psr_status; u32 psr_status_mask; - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.sel_update_enabled) { psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder); psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; } else { @@ -2085,7 +2085,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) drm_dbg_kms(&dev_priv->drm, "Disabling Panel Replay\n"); else drm_dbg_kms(&dev_priv->drm, "Disabling PSR%s\n", - intel_dp->psr.psr2_enabled ? "2" : "1"); + intel_dp->psr.sel_update_enabled ? "2" : "1"); intel_psr_exit(intel_dp); intel_psr_wait_exit_locked(intel_dp); @@ -2098,7 +2098,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, wa_16013835468_bit_get(intel_dp), 0); - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.sel_update_enabled) { /* Wa_16012604467:adlp,mtl[a0,b0] */ if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, @@ -2128,12 +2128,12 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_psr_get_enable_sink_offset(intel_dp), 0); if (!intel_dp->psr.panel_replay_enabled && - intel_dp->psr.psr2_enabled) + intel_dp->psr.sel_update_enabled) drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); intel_dp->psr.enabled = false; intel_dp->psr.panel_replay_enabled = false; - intel_dp->psr.psr2_enabled = false; + intel_dp->psr.sel_update_enabled = false; intel_dp->psr.psr2_sel_fetch_enabled = false; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; } @@ -2702,7 +2702,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); needs_to_disable |= !new_crtc_state->has_psr; needs_to_disable |= !new_crtc_state->active_planes; - needs_to_disable |= new_crtc_state->has_sel_update != psr->psr2_enabled; + needs_to_disable |= new_crtc_state->has_sel_update != psr->sel_update_enabled; needs_to_disable |= DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled; @@ -2820,7 +2820,7 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat if (!intel_dp->psr.enabled) continue; - if (intel_dp->psr.psr2_enabled) + if (intel_dp->psr.sel_update_enabled) ret = _psr2_ready_for_pipe_update_locked(intel_dp); else ret = _psr1_ready_for_pipe_update_locked(intel_dp); @@ -2841,7 +2841,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) if (!intel_dp->psr.enabled) return false; - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.sel_update_enabled) { reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder); mask = EDP_PSR2_STATUS_STATE_MASK; } else { @@ -3084,7 +3084,7 @@ tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits, { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.psr2_enabled || + if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled || !intel_dp->psr.active) return; @@ -3283,7 +3283,7 @@ static void psr_alpm_check(struct intel_dp *intel_dp) u8 val; int r; - if (!psr->psr2_enabled) + if (!psr->sel_update_enabled) return; r = drm_dp_dpcd_readb(aux, DP_RECEIVER_ALPM_STATUS, &val); @@ -3463,7 +3463,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) const char *status = "unknown"; u32 val, status_val; - if (intel_dp->psr.psr2_enabled) { + if (intel_dp->psr.sel_update_enabled) { static const char * const live_status[] = { "IDLE", "CAPTURE", @@ -3528,7 +3528,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) if (psr->panel_replay_enabled) status = "Panel Replay Enabled"; else if (psr->enabled) - status = psr->psr2_enabled ? "PSR2 enabled" : "PSR1 enabled"; + status = psr->sel_update_enabled ? "PSR2 enabled" : "PSR1 enabled"; else status = "disabled"; seq_printf(m, "PSR mode: %s\n", status); @@ -3543,7 +3543,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) if (psr->panel_replay_enabled) { val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder)); enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; - } else if (psr->psr2_enabled) { + } else if (psr->sel_update_enabled) { val = intel_de_read(dev_priv, EDP_PSR2_CTL(dev_priv, cpu_transcoder)); enabled = val & EDP_PSR2_ENABLE; @@ -3570,7 +3570,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) seq_printf(m, "Last exit at: %lld\n", psr->last_exit); } - if (psr->psr2_enabled) { + if (psr->sel_update_enabled) { u32 su_frames_val[3]; int frame; -- cgit From 4b526132cce81cd2430d6548ea031b364538c5c0 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:16 +0300 Subject: drm/panelreplay: dpcd register definition for panelreplay SU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add definitions for panel replay selective update v2: Remove unnecessary Cc from commit message Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Acked-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-6-jouni.hogander@intel.com --- include/drm/display/drm_dp.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 0b032faa8cf2..906949ca3cee 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -548,6 +548,12 @@ # define DP_PANEL_REPLAY_SUPPORT (1 << 0) # define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) +#define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1 +# define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5) + +#define DP_PANEL_PANEL_REPLAY_X_GRANULARITY 0xb2 +#define DP_PANEL_PANEL_REPLAY_Y_GRANULARITY 0xb4 + /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ -- cgit From 3a745dfc715c50d57e52be744c05c66d65853e94 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:17 +0300 Subject: drm/i915/psr: Detect panel replay selective update support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add new boolean to store panel replay selective update support of sink into intel_psr struct. Detect panel replay selective update support and store it into this new boolean. v3: Clear sink_panel_replay_su_support in intel_dp_detect v2: Merge adding new boolean into this patch Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-7-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 10 ++++++++-- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index e140f79da006..9678c2b157f6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1724,6 +1724,7 @@ struct intel_psr { u16 su_y_granularity; bool source_panel_replay_support; bool sink_panel_replay_support; + bool sink_panel_replay_su_support; bool panel_replay_enabled; u32 dc3co_exitline; u32 dc3co_exit_delay; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 098454262609..c0a3b6d50681 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5861,6 +5861,7 @@ intel_dp_detect(struct drm_connector *connector, memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd)); intel_dp->psr.sink_panel_replay_support = false; + intel_dp->psr.sink_panel_replay_su_support = false; intel_dp_mst_disconnect(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 820499f420ba..0a5ce29f09d1 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -522,9 +522,15 @@ static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) return; } - drm_dbg_kms(&i915->drm, - "Panel replay is supported by panel\n"); intel_dp->psr.sink_panel_replay_support = true; + + if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT) + intel_dp->psr.sink_panel_replay_su_support = true; + + drm_dbg_kms(&i915->drm, + "Panel replay %sis supported by panel\n", + intel_dp->psr.sink_panel_replay_su_support ? + "selective_update " : ""); } static void _psr_init_dpcd(struct intel_dp *intel_dp) -- cgit From d210d8c0df2f05a081758f3b0b9dc2f4f247b661 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:18 +0300 Subject: drm/i915/psr: Modify intel_dp_get_su_granularity to support panel replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently intel_dp_get_su_granularity doesn't support panel replay. This fix modifies it to support panel replay as well. v4: - use drm_dp_dpcd_readb instead of drm_dp_dpcd_read - ensure return value is 0 if drm_dp_dpcd_readb fails v3: use correct offset for DP_PANEL_PANEL_REPLAY_CAPABILITY v2: rely on PSR definitions on common bits Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-8-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 62 ++++++++++++++++++++++++++++---- 1 file changed, 55 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 0a5ce29f09d1..6d1f442f3d14 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -468,6 +468,40 @@ static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) return val; } +static u8 intel_dp_get_su_capability(struct intel_dp *intel_dp) +{ + u8 su_capability = 0; + + if (intel_dp->psr.sink_panel_replay_su_support) + drm_dp_dpcd_readb(&intel_dp->aux, + DP_PANEL_PANEL_REPLAY_CAPABILITY, + &su_capability); + else + su_capability = intel_dp->psr_dpcd[1]; + + return su_capability; +} + +static unsigned int +intel_dp_get_su_x_granularity_offset(struct intel_dp *intel_dp) +{ + return intel_dp->psr.sink_panel_replay_su_support ? + DP_PANEL_PANEL_REPLAY_X_GRANULARITY : + DP_PSR2_SU_X_GRANULARITY; +} + +static unsigned int +intel_dp_get_su_y_granularity_offset(struct intel_dp *intel_dp) +{ + return intel_dp->psr.sink_panel_replay_su_support ? + DP_PANEL_PANEL_REPLAY_Y_GRANULARITY : + DP_PSR2_SU_Y_GRANULARITY; +} + +/* + * Note: Bits related to granularity are same in panel replay and psr + * registers. Rely on PSR definitions on these "common" bits. + */ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -475,18 +509,29 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) u16 w; u8 y; - /* If sink don't have specific granularity requirements set legacy ones */ - if (!(intel_dp->psr_dpcd[1] & DP_PSR2_SU_GRANULARITY_REQUIRED)) { + /* + * TODO: Do we need to take into account panel supporting both PSR and + * Panel replay? + */ + + /* + * If sink don't have specific granularity requirements set legacy + * ones. + */ + if (!(intel_dp_get_su_capability(intel_dp) & + DP_PSR2_SU_GRANULARITY_REQUIRED)) { /* As PSR2 HW sends full lines, we do not care about x granularity */ w = 4; y = 4; goto exit; } - r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_X_GRANULARITY, &w, 2); + r = drm_dp_dpcd_read(&intel_dp->aux, + intel_dp_get_su_x_granularity_offset(intel_dp), + &w, 2); if (r != 2) drm_dbg_kms(&i915->drm, - "Unable to read DP_PSR2_SU_X_GRANULARITY\n"); + "Unable to read selective update x granularity\n"); /* * Spec says that if the value read is 0 the default granularity should * be used instead. @@ -494,10 +539,12 @@ static void intel_dp_get_su_granularity(struct intel_dp *intel_dp) if (r != 2 || w == 0) w = 4; - r = drm_dp_dpcd_read(&intel_dp->aux, DP_PSR2_SU_Y_GRANULARITY, &y, 1); + r = drm_dp_dpcd_read(&intel_dp->aux, + intel_dp_get_su_y_granularity_offset(intel_dp), + &y, 1); if (r != 1) { drm_dbg_kms(&i915->drm, - "Unable to read DP_PSR2_SU_Y_GRANULARITY\n"); + "Unable to read selective update y granularity\n"); y = 4; } if (y == 0) @@ -590,7 +637,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) if (intel_dp->psr_dpcd[0]) _psr_init_dpcd(intel_dp); - if (intel_dp->psr.sink_psr2_support) + if (intel_dp->psr.sink_psr2_support || + intel_dp->psr.sink_panel_replay_su_support) intel_dp_get_su_granularity(intel_dp); } -- cgit From 29fb595d48758a6804f6f5ad29df9508eeba242b Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:19 +0300 Subject: drm/i915/psr: Panel replay uses SRD_STATUS to track it's status MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit DP Panel replay uses SRD_STATUS to track it's status despite selective update mode. Bspec: 53370, 68920 v4: - use PSR2_STATUS for eDP Panel Replay - handle intel_psr_wait_exit_locked as well v3: - do not use PSR2_STATUS for PSR1 v2: - use intel_dp_is_edp to differentiate - modify debugfs status as well Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-9-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 6d1f442f3d14..532a80a3eeea 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2111,7 +2111,8 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) i915_reg_t psr_status; u32 psr_status_mask; - if (intel_dp->psr.sel_update_enabled) { + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || + intel_dp->psr.panel_replay_enabled)) { psr_status = EDP_PSR2_STATUS(dev_priv, cpu_transcoder); psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; } else { @@ -2849,6 +2850,13 @@ static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp) EDP_PSR_STATUS_STATE_MASK, 50); } +static int _panel_replay_ready_for_pipe_update_locked(struct intel_dp *intel_dp) +{ + return intel_dp_is_edp(intel_dp) ? + _psr2_ready_for_pipe_update_locked(intel_dp) : + _psr1_ready_for_pipe_update_locked(intel_dp); +} + /** * intel_psr_wait_for_idle_locked - wait for PSR be ready for a pipe update * @new_crtc_state: new CRTC state @@ -2874,7 +2882,9 @@ void intel_psr_wait_for_idle_locked(const struct intel_crtc_state *new_crtc_stat if (!intel_dp->psr.enabled) continue; - if (intel_dp->psr.sel_update_enabled) + if (intel_dp->psr.panel_replay_enabled) + ret = _panel_replay_ready_for_pipe_update_locked(intel_dp); + else if (intel_dp->psr.sel_update_enabled) ret = _psr2_ready_for_pipe_update_locked(intel_dp); else ret = _psr1_ready_for_pipe_update_locked(intel_dp); @@ -2895,7 +2905,8 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) if (!intel_dp->psr.enabled) return false; - if (intel_dp->psr.sel_update_enabled) { + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || + intel_dp->psr.panel_replay_enabled)) { reg = EDP_PSR2_STATUS(dev_priv, cpu_transcoder); mask = EDP_PSR2_STATUS_STATE_MASK; } else { @@ -3517,7 +3528,8 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) const char *status = "unknown"; u32 val, status_val; - if (intel_dp->psr.sel_update_enabled) { + if (intel_dp_is_edp(intel_dp) && (intel_dp->psr.sel_update_enabled || + intel_dp->psr.panel_replay_enabled)) { static const char * const live_status[] = { "IDLE", "CAPTURE", -- cgit From 54599011b7569f6bb027b17248015c622705d741 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:20 +0300 Subject: drm/i915/psr: Do not apply workarounds in case of panel replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are some workarounds that are not applicable for panel replay. Do not apply these if panel replay is used. Bspec: 66624, 50422 Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-10-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_fbc.c | 5 +++-- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++- drivers/gpu/drm/i915/display/intel_psr.c | 16 ++++++++++------ 3 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 984f13d8c0c8..50dd8eb9012e 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1251,7 +1251,8 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, * Recommendation is to keep this combination disabled * Bspec: 50422 HSD: 14010260002 */ - if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update) { + if (IS_DISPLAY_VER(i915, 12, 14) && crtc_state->has_sel_update && + !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR2 enabled"; return 0; } @@ -1259,7 +1260,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, /* Wa_14016291713 */ if ((IS_DISPLAY_VER(i915, 12, 13) || IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_C0)) && - crtc_state->has_psr) { + crtc_state->has_psr && !crtc_state->has_panel_replay) { plane_state->no_fbc_reason = "PSR1 enabled (Wa_14016291713)"; return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 5f6deceaf8ba..0faf2afa1c09 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -532,7 +532,8 @@ void hsw_write_infoframe(struct intel_encoder *encoder, 0); /* Wa_14013475917 */ - if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && type == DP_SDP_VSC)) + if (!(IS_DISPLAY_VER(dev_priv, 13, 14) && crtc_state->has_psr && + !crtc_state->has_panel_replay && type == DP_SDP_VSC)) val |= hsw_infoframe_enable(type); if (type == DP_SDP_VSC) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 532a80a3eeea..0d90c49d2233 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1970,13 +1970,15 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, * All supported adlp panels have 1-based X granularity, this may * cause issues if non-supported panels are used. */ - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || - IS_ALDERLAKE_P(dev_priv)) + if (!intel_dp->psr.panel_replay_enabled && + (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || + IS_ALDERLAKE_P(dev_priv))) intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), 0, ADLP_1_BASED_X_GRANULARITY); /* Wa_16012604467:adlp,mtl[a0,b0] */ - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) + if (!intel_dp->psr.panel_replay_enabled && + IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0, MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); @@ -2155,7 +2157,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) if (intel_dp->psr.sel_update_enabled) { /* Wa_16012604467:adlp,mtl[a0,b0] */ - if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) + if (!intel_dp->psr.panel_replay_enabled && + IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, MTL_CLKGATE_DIS_TRANS(cpu_transcoder), MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); @@ -2642,8 +2645,9 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, goto skip_sel_fetch_set_loop; /* Wa_14014971492 */ - if ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || - IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv)) && + if (!crtc_state->has_panel_replay && + ((IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0) || + IS_ALDERLAKE_P(dev_priv) || IS_TIGERLAKE(dev_priv))) && crtc_state->splitter.enable) crtc_state->psr2_su_area.y1 = 0; -- cgit From 328add8892c261f28dbf2ef060e8a0707f795c43 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:21 +0300 Subject: drm/i915/psr: Update PSR module parameter descriptions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are re-using PSR module parameters for panel replay. Update module parameter descriptions with panel replay information: enable_psr: -1 (default) == follow what is in VBT 0 == disable PSR/PR 1 == Allow PSR1 and PR full frame update 2 == allow PSR1/PSR2 and PR Selective Update enable_psr2_sel_fetch 0 == disable selective fetch for PSR and PR 1 (default) == allow selective fetch for PSR PR Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-11-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_display_params.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index 1799a6643128..aebdb7b59dbf 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -106,7 +106,8 @@ intel_display_param_named_unsafe(enable_fbc, int, 0400, intel_display_param_named_unsafe(enable_psr, int, 0400, "Enable PSR " - "(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) " + "(0=disabled, 1=enable up to PSR1 and Panel Replay full frame update, " + "2=enable up to PSR2 and Panel Replay Selective Update) " "Default: -1 (use per-chip default)"); intel_display_param_named(psr_safest_params, bool, 0400, @@ -116,7 +117,7 @@ intel_display_param_named(psr_safest_params, bool, 0400, "Default: 0"); intel_display_param_named_unsafe(enable_psr2_sel_fetch, bool, 0400, - "Enable PSR2 selective fetch " + "Enable PSR2 and Panel Replay selective fetch " "(0=disabled, 1=enabled) " "Default: 1"); -- cgit From c66c670ded611ba4528898a2520996e5f55cb03e Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:22 +0300 Subject: drm/i915/psr: Split intel_psr2_config_valid for panel replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Part of intel_psr2_config_valid is valid for panel replay. rename it as intel_sel_update_config_valid. Split psr2 specific part and name it as intel_psr2_config_valid. v3: - move early transport check to psr2 specific check - check intel_psr2_config_valid only for non-Panel Replay case v2: - use psr2_global_enabled for panel replay as well - goto unsupported instead of return when global enabled check fails Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-12-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 76 +++++++++++++++++++------------- 1 file changed, 46 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 0d90c49d2233..12ddf84e8d02 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1147,9 +1147,6 @@ static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp, return false; } - if (psr2_su_region_et_valid(intel_dp)) - crtc_state->enable_psr2_su_region_et = true; - return crtc_state->enable_psr2_sel_fetch = true; } @@ -1520,11 +1517,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (!psr2_global_enabled(intel_dp)) { - drm_dbg_kms(&dev_priv->drm, "PSR2 disabled by flag\n"); - return false; - } - /* * DSC and PSR2 cannot be enabled simultaneously. If a requested * resolution requires DSC to be enabled, priority is given to DSC @@ -1537,12 +1529,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (crtc_state->crc_enabled) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled because it would inhibit pipe CRC calculation\n"); - return false; - } - if (DISPLAY_VER(dev_priv) >= 12) { psr_max_h = 5120; psr_max_v = 3200; @@ -1593,30 +1579,60 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (HAS_PSR2_SEL_FETCH(dev_priv)) { - if (!intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && - !HAS_PSR_HW_TRACKING(dev_priv)) { - drm_dbg_kms(&dev_priv->drm, - "PSR2 not enabled, selective fetch not valid and no HW tracking available\n"); - return false; - } - } - - if (!psr2_granularity_check(intel_dp, crtc_state)) { - drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, SU granularity not compatible\n"); - goto unsupported; - } - if (!crtc_state->enable_psr2_sel_fetch && (crtc_hdisplay > psr_max_h || crtc_vdisplay > psr_max_v)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, resolution %dx%d > max supported %dx%d\n", crtc_hdisplay, crtc_vdisplay, psr_max_h, psr_max_v); - goto unsupported; + return false; } tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); + + if (psr2_su_region_et_valid(intel_dp)) + crtc_state->enable_psr2_su_region_et = true; + + return true; +} + +static bool intel_sel_update_config_valid(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + + if (HAS_PSR2_SEL_FETCH(dev_priv) && + !intel_psr2_sel_fetch_config_valid(intel_dp, crtc_state) && + !HAS_PSR_HW_TRACKING(dev_priv)) { + drm_dbg_kms(&dev_priv->drm, + "Selective update not enabled, selective fetch not valid and no HW tracking available\n"); + goto unsupported; + } + + if (!psr2_global_enabled(intel_dp)) { + drm_dbg_kms(&dev_priv->drm, "Selective update disabled by flag\n"); + goto unsupported; + } + + if (!crtc_state->has_panel_replay && !intel_psr2_config_valid(intel_dp, crtc_state)) + goto unsupported; + + if (crtc_state->has_panel_replay && (DISPLAY_VER(dev_priv) < 14 || + !intel_dp->psr.sink_panel_replay_su_support)) + goto unsupported; + + if (crtc_state->crc_enabled) { + drm_dbg_kms(&dev_priv->drm, + "Selective update not enabled because it would inhibit pipe CRC calculation\n"); + goto unsupported; + } + + if (!psr2_granularity_check(intel_dp, crtc_state)) { + drm_dbg_kms(&dev_priv->drm, + "Selective update not enabled, SU granularity not compatible\n"); + goto unsupported; + } + return true; unsupported: @@ -1698,7 +1714,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, if (!crtc_state->has_psr) return; - crtc_state->has_sel_update = intel_psr2_config_valid(intel_dp, crtc_state); + crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); } void intel_psr_get_config(struct intel_encoder *encoder, -- cgit From 3425b2205d30c9d639217a32368422e4ab95e999 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 10 May 2024 12:38:23 +0300 Subject: drm/i915/psr: Add panel replay sel update support to debugfs interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add panel replay selective update support to debugfs status interface. In case of sink supporting panel replay we will print out: Sink support: PSR = no, Panel Replay = yes, Panel Replay Selective Update = yes and PSR mode will look like this if printing out enabled panel replay selective update: PSR mode: Panel Replay Selective Update Enabled Current PSR and panel replay printouts remain same. Cc: Kunal Joshi Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240510093823.3146455-13-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 12ddf84e8d02..2514ac48312b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3603,7 +3603,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) if (psr->sink_support) seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); - seq_printf(m, ", Panel Replay = %s\n", str_yes_no(psr->sink_panel_replay_support)); + seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); + seq_printf(m, ", Panel Replay Selective Update = %s\n", + str_yes_no(psr->sink_panel_replay_su_support)); if (!(psr->sink_support || psr->sink_panel_replay_support)) return 0; @@ -3612,9 +3614,10 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) mutex_lock(&psr->lock); if (psr->panel_replay_enabled) - status = "Panel Replay Enabled"; + status = psr->sel_update_enabled ? "Panel Replay Selective Update Enabled" : + "Panel Replay Enabled"; else if (psr->enabled) - status = psr->sel_update_enabled ? "PSR2 enabled" : "PSR1 enabled"; + status = psr->sel_update_enabled ? "PSR2" : "PSR1"; else status = "disabled"; seq_printf(m, "PSR mode: %s\n", status); -- cgit From af52e168fd5a7b579c349cb67b5d253433b12212 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:14 +0300 Subject: drm/i915: Nuke _MMIO_PLANE_GAMC() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit _MMIO_PLANE_GAMC() is some leftover macro that is never used. Get rid of it. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 256d73c25701..0f4a2d542d81 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -5151,8 +5151,6 @@ enum skl_power_gate { #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) #define WM_DBG_DISALLOW_SPRITE (1 << 2) -#define _MMIO_PLANE_GAMC(plane, i, a, b) _MMIO(_PIPE(plane, a, b) + (i) * 4) - /* Plane CSC Registers */ #define _PLANE_CSC_RY_GY_1_A 0x70210 #define _PLANE_CSC_RY_GY_2_A 0x70310 -- cgit From 8c8667682e8414fd766c376219487a085f03e823 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:15 +0300 Subject: drm/i915: Extract skl_universal_plane_regs.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move most of the SKL+ universal plane register definitions into their own file. Declutters i915_reg.h a bit more. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_dpt_common.c | 1 + drivers/gpu/drm/i915/display/skl_universal_plane.c | 1 + .../drm/i915/display/skl_universal_plane_regs.h | 405 +++++++++++++++++++++ drivers/gpu/drm/i915/display/skl_watermark.c | 1 + drivers/gpu/drm/i915/gvt/dmabuf.c | 3 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 395 -------------------- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 10 files changed, 414 insertions(+), 396 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 4035b3ec311d..9bb019fc9787 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -119,6 +119,7 @@ #include "intel_wm.h" #include "skl_scaler.h" #include "skl_universal_plane.h" +#include "skl_universal_plane_regs.h" #include "skl_watermark.h" #include "vlv_dpio_phy_regs.h" #include "vlv_dsi.h" diff --git a/drivers/gpu/drm/i915/display/intel_dpt_common.c b/drivers/gpu/drm/i915/display/intel_dpt_common.c index cdba47165c04..573f72068899 100644 --- a/drivers/gpu/drm/i915/display/intel_dpt_common.c +++ b/drivers/gpu/drm/i915/display/intel_dpt_common.c @@ -7,6 +7,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_dpt_common.h" +#include "skl_universal_plane_regs.h" void intel_dpt_configure(struct intel_crtc *crtc) { diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 7b79704fa674..d7b7476dc699 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -21,6 +21,7 @@ #include "intel_psr_regs.h" #include "skl_scaler.h" #include "skl_universal_plane.h" +#include "skl_universal_plane_regs.h" #include "skl_watermark.h" #include "pxp/intel_pxp.h" diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h new file mode 100644 index 000000000000..7e34470beb74 --- /dev/null +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -0,0 +1,405 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __SKL_UNIVERSAL_PLANE_REGS_H__ +#define __SKL_UNIVERSAL_PLANE_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define _PLANE_CTL_1_A 0x70180 +#define _PLANE_CTL_2_A 0x70280 +#define _PLANE_CTL_3_A 0x70380 +#define PLANE_CTL_ENABLE REG_BIT(31) +#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ +#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ +#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ +#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) +/* + * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition + * expanded to include bit 23 as well. However, the shift-24 based values + * correctly map to the same formats in ICL, as long as bit 23 is set to 0 + */ +#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ +#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ +#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) +#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) +#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) +#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) +#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) +#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) +#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) +#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) +#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) +#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) +#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) +#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) +#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) +#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) +#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) +#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) +#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) +#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ +#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) +#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) +#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) +#define PLANE_CTL_ORDER_RGBX REG_BIT(20) +#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) +#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) +#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) +#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) +#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) +#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) +#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) +#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) +#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) +#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ +#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ +#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) +#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) +#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) +#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) +#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) +#define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) +#define PLANE_CTL_ASYNC_FLIP REG_BIT(9) +#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) +#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ +#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ +#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) +#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) +#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) +#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) +#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) +#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) +#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) +#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) +#define _PLANE_STRIDE_1_A 0x70188 +#define _PLANE_STRIDE_2_A 0x70288 +#define _PLANE_STRIDE_3_A 0x70388 +#define PLANE_STRIDE__MASK REG_GENMASK(11, 0) +#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) +#define _PLANE_POS_1_A 0x7018c +#define _PLANE_POS_2_A 0x7028c +#define _PLANE_POS_3_A 0x7038c +#define PLANE_POS_Y_MASK REG_GENMASK(31, 16) +#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) +#define PLANE_POS_X_MASK REG_GENMASK(15, 0) +#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) +#define _PLANE_SIZE_1_A 0x70190 +#define _PLANE_SIZE_2_A 0x70290 +#define _PLANE_SIZE_3_A 0x70390 +#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) +#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) +#define PLANE_WIDTH_MASK REG_GENMASK(15, 0) +#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) +#define _PLANE_SURF_1_A 0x7019c +#define _PLANE_SURF_2_A 0x7029c +#define _PLANE_SURF_3_A 0x7039c +#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) +#define PLANE_SURF_DECRYPT REG_BIT(2) +#define _PLANE_OFFSET_1_A 0x701a4 +#define _PLANE_OFFSET_2_A 0x702a4 +#define _PLANE_OFFSET_3_A 0x703a4 +#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) +#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) +#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) +#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) +#define _PLANE_KEYVAL_1_A 0x70194 +#define _PLANE_KEYVAL_2_A 0x70294 +#define _PLANE_KEYMSK_1_A 0x70198 +#define _PLANE_KEYMSK_2_A 0x70298 +#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) +#define _PLANE_KEYMAX_1_A 0x701a0 +#define _PLANE_KEYMAX_2_A 0x702a0 +#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) +#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) +#define _PLANE_SURFLIVE_1_A 0x701ac +#define _PLANE_SURFLIVE_2_A 0x702ac +#define _PLANE_CC_VAL_1_A 0x701b4 +#define _PLANE_CC_VAL_2_A 0x702b4 +#define _PLANE_AUX_DIST_1_A 0x701c0 +#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) +#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) +#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) +#define _PLANE_AUX_DIST_2_A 0x702c0 +#define _PLANE_AUX_OFFSET_1_A 0x701c4 +#define _PLANE_AUX_OFFSET_2_A 0x702c4 +#define _PLANE_CUS_CTL_1_A 0x701c8 +#define _PLANE_CUS_CTL_2_A 0x702c8 +#define PLANE_CUS_ENABLE REG_BIT(31) +#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) +#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) +#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) +#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) +#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) +#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) +#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) +#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) +#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) +#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) +#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) +#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) +#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) +#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ +#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ +#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ +#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ +#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) +#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ +#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ +#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ +#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) +#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) +#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) +#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) +#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) +#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) +#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) +#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) +#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) +#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) +#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) +#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */ +#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */ +#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ +#define _PLANE_BUF_CFG_1_A 0x7027c +#define _PLANE_BUF_CFG_2_A 0x7037c +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ +#define PLANE_BUF_END_MASK REG_GENMASK(27, 16) +#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) +#define PLANE_BUF_START_MASK REG_GENMASK(11, 0) +#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) +#define _PLANE_NV12_BUF_CFG_1_A 0x70278 +#define _PLANE_NV12_BUF_CFG_2_A 0x70378 + +#define _PLANE_CC_VAL_1_B 0x711b4 +#define _PLANE_CC_VAL_2_B 0x712b4 +#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) +#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) +#define PLANE_CC_VAL(pipe, plane, dw) \ + _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) + +/* Input CSC Register Definitions */ +#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 +#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 + +#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 +#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 + +#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ + _PLANE_INPUT_CSC_RY_GY_1_B) +#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ + _PLANE_INPUT_CSC_RY_GY_2_B) + +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) + +#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 +#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 + +#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 +#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 + +#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ + _PLANE_INPUT_CSC_PREOFF_HI_1_B) +#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ + _PLANE_INPUT_CSC_PREOFF_HI_2_B) +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) + +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 + +#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 +#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 + +#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ + _PLANE_INPUT_CSC_POSTOFF_HI_1_B) +#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ + _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2_B) +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) + +#define _PLANE_CTL_1_B 0x71180 +#define _PLANE_CTL_2_B 0x71280 +#define _PLANE_CTL_3_B 0x71380 +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) +#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) +#define PLANE_CTL(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) + +#define _PLANE_STRIDE_1_B 0x71188 +#define _PLANE_STRIDE_2_B 0x71288 +#define _PLANE_STRIDE_3_B 0x71388 +#define _PLANE_STRIDE_1(pipe) \ + _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) +#define _PLANE_STRIDE_2(pipe) \ + _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) +#define _PLANE_STRIDE_3(pipe) \ + _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) +#define PLANE_STRIDE(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) + +#define _PLANE_POS_1_B 0x7118c +#define _PLANE_POS_2_B 0x7128c +#define _PLANE_POS_3_B 0x7138c +#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) +#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) +#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) +#define PLANE_POS(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) + +#define _PLANE_SIZE_1_B 0x71190 +#define _PLANE_SIZE_2_B 0x71290 +#define _PLANE_SIZE_3_B 0x71390 +#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) +#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) +#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) +#define PLANE_SIZE(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) + +#define _PLANE_SURF_1_B 0x7119c +#define _PLANE_SURF_2_B 0x7129c +#define _PLANE_SURF_3_B 0x7139c +#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) +#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) +#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) +#define PLANE_SURF(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) + +#define _PLANE_OFFSET_1_B 0x711a4 +#define _PLANE_OFFSET_2_B 0x712a4 +#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) +#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) +#define PLANE_OFFSET(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) + +#define _PLANE_KEYVAL_1_B 0x71194 +#define _PLANE_KEYVAL_2_B 0x71294 +#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) +#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) +#define PLANE_KEYVAL(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) + +#define _PLANE_KEYMSK_1_B 0x71198 +#define _PLANE_KEYMSK_2_B 0x71298 +#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) +#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) +#define PLANE_KEYMSK(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) + +#define _PLANE_KEYMAX_1_B 0x711a0 +#define _PLANE_KEYMAX_2_B 0x712a0 +#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) +#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) +#define PLANE_KEYMAX(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) + +#define _PLANE_SURFLIVE_1_B 0x711ac +#define _PLANE_SURFLIVE_2_B 0x712ac +#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B) +#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) +#define PLANE_SURFLIVE(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe)) + +#define _PLANE_CHICKEN_1_B 0x7126c +#define _PLANE_CHICKEN_2_B 0x7136c +#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B) +#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) +#define PLANE_CHICKEN(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe)) + +#define _PLANE_AUX_DIST_1_B 0x711c0 +#define _PLANE_AUX_DIST_2_B 0x712c0 +#define _PLANE_AUX_DIST_1(pipe) \ + _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) +#define _PLANE_AUX_DIST_2(pipe) \ + _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) +#define PLANE_AUX_DIST(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) + +#define _PLANE_AUX_OFFSET_1_B 0x711c4 +#define _PLANE_AUX_OFFSET_2_B 0x712c4 +#define _PLANE_AUX_OFFSET_1(pipe) \ + _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) +#define _PLANE_AUX_OFFSET_2(pipe) \ + _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) +#define PLANE_AUX_OFFSET(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) + +#define _PLANE_CUS_CTL_1_B 0x711c8 +#define _PLANE_CUS_CTL_2_B 0x712c8 +#define _PLANE_CUS_CTL_1(pipe) \ + _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) +#define _PLANE_CUS_CTL_2(pipe) \ + _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) +#define PLANE_CUS_CTL(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) + +#define _PLANE_COLOR_CTL_1_B 0x711CC +#define _PLANE_COLOR_CTL_2_B 0x712CC +#define _PLANE_COLOR_CTL_3_B 0x713CC +#define _PLANE_COLOR_CTL_1(pipe) \ + _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) +#define _PLANE_COLOR_CTL_2(pipe) \ + _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) +#define PLANE_COLOR_CTL(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) + +/* Plane CSC Registers */ +#define _PLANE_CSC_RY_GY_1_A 0x70210 +#define _PLANE_CSC_RY_GY_2_A 0x70310 + +#define _PLANE_CSC_RY_GY_1_B 0x71210 +#define _PLANE_CSC_RY_GY_2_B 0x71310 + +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ + _PLANE_CSC_RY_GY_1_B) +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \ + _PLANE_CSC_RY_GY_2_B) +#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ + _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ + _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) + +#define _PLANE_CSC_PREOFF_HI_1_A 0x70228 +#define _PLANE_CSC_PREOFF_HI_2_A 0x70328 + +#define _PLANE_CSC_PREOFF_HI_1_B 0x71228 +#define _PLANE_CSC_PREOFF_HI_2_B 0x71328 + +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ + _PLANE_CSC_PREOFF_HI_1_B) +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ + _PLANE_CSC_PREOFF_HI_2_B) +#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ + (index) * 4) + +#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 +#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 + +#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 +#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 + +#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ + _PLANE_CSC_POSTOFF_HI_1_B) +#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ + _PLANE_CSC_POSTOFF_HI_2_B) +#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ + (index) * 4) + +#endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index f85980aba25e..53a565c673e2 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -21,6 +21,7 @@ #include "intel_fixed.h" #include "intel_pcode.h" #include "intel_wm.h" +#include "skl_universal_plane_regs.h" #include "skl_watermark.h" #include "skl_watermark_regs.h" diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c b/drivers/gpu/drm/i915/gvt/dmabuf.c index 6834f9fe40cf..9efc3ca0ce82 100644 --- a/drivers/gpu/drm/i915/gvt/dmabuf.c +++ b/drivers/gpu/drm/i915/gvt/dmabuf.c @@ -37,9 +37,10 @@ #include "gem/i915_gem_dmabuf.h" #include "i915_drv.h" -#include "i915_reg.h" #include "gvt.h" +#include "display/skl_universal_plane_regs.h" + #define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12)) static int vgpu_gem_get_pages(struct drm_i915_gem_object *obj) diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 4140da68aabb..dd6eb0ae003a 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -41,6 +41,7 @@ #include "i915_reg.h" #include "display/intel_sprite_regs.h" +#include "display/skl_universal_plane_regs.h" #define PRIMARY_FORMAT_NUM 16 struct pixel_format { diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 102eb354fed6..aae0443015f0 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -51,6 +51,7 @@ #include "display/intel_pps_regs.h" #include "display/intel_psr_regs.h" #include "display/intel_sprite_regs.h" +#include "display/skl_universal_plane_regs.h" #include "display/skl_watermark_regs.h" #include "display/vlv_dsi_pll_regs.h" #include "gt/intel_gt_regs.h" diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0f4a2d542d81..08725dc7883e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2481,358 +2481,6 @@ #define _PIPEDSI0CONF 0x7b008 #define _PIPEDSI1CONF 0x7b808 -/* Skylake plane registers */ - -#define _PLANE_CTL_1_A 0x70180 -#define _PLANE_CTL_2_A 0x70280 -#define _PLANE_CTL_3_A 0x70380 -#define PLANE_CTL_ENABLE REG_BIT(31) -#define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ -#define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ -#define PLANE_CTL_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-GLK */ -#define PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) -/* - * ICL+ uses the same PLANE_CTL_FORMAT bits, but the field definition - * expanded to include bit 23 as well. However, the shift-24 based values - * correctly map to the same formats in ICL, as long as bit 23 is set to 0 - */ -#define PLANE_CTL_FORMAT_MASK_SKL REG_GENMASK(27, 24) /* pre-icl */ -#define PLANE_CTL_FORMAT_MASK_ICL REG_GENMASK(27, 23) /* icl+ */ -#define PLANE_CTL_FORMAT_YUV422 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 0) -#define PLANE_CTL_FORMAT_NV12 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 1) -#define PLANE_CTL_FORMAT_XRGB_2101010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 2) -#define PLANE_CTL_FORMAT_P010 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 3) -#define PLANE_CTL_FORMAT_XRGB_8888 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 4) -#define PLANE_CTL_FORMAT_P012 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 5) -#define PLANE_CTL_FORMAT_XRGB_16161616F REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 6) -#define PLANE_CTL_FORMAT_P016 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 7) -#define PLANE_CTL_FORMAT_XYUV REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 8) -#define PLANE_CTL_FORMAT_INDEXED REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 12) -#define PLANE_CTL_FORMAT_RGB_565 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_SKL, 14) -#define PLANE_CTL_FORMAT_Y210 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 1) -#define PLANE_CTL_FORMAT_Y212 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 3) -#define PLANE_CTL_FORMAT_Y216 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 5) -#define PLANE_CTL_FORMAT_Y410 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) -#define PLANE_CTL_FORMAT_Y412 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) -#define PLANE_CTL_FORMAT_Y416 REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) -#define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK */ -#define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) -#define PLANE_CTL_KEY_ENABLE_SOURCE REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) -#define PLANE_CTL_KEY_ENABLE_DESTINATION REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 2) -#define PLANE_CTL_ORDER_RGBX REG_BIT(20) -#define PLANE_CTL_YUV420_Y_PLANE REG_BIT(19) -#define PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) -#define PLANE_CTL_YUV422_ORDER_MASK REG_GENMASK(17, 16) -#define PLANE_CTL_YUV422_ORDER_YUYV REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 0) -#define PLANE_CTL_YUV422_ORDER_UYVY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 1) -#define PLANE_CTL_YUV422_ORDER_YVYU REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 2) -#define PLANE_CTL_YUV422_ORDER_VYUY REG_FIELD_PREP(PLANE_CTL_YUV422_ORDER_MASK, 3) -#define PLANE_CTL_RENDER_DECOMPRESSION_ENABLE REG_BIT(15) -#define PLANE_CTL_TRICKLE_FEED_DISABLE REG_BIT(14) -#define PLANE_CTL_CLEAR_COLOR_DISABLE REG_BIT(13) /* TGL+ */ -#define PLANE_CTL_PLANE_GAMMA_DISABLE REG_BIT(13) /* Pre-GLK */ -#define PLANE_CTL_TILED_MASK REG_GENMASK(12, 10) -#define PLANE_CTL_TILED_LINEAR REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 0) -#define PLANE_CTL_TILED_X REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 1) -#define PLANE_CTL_TILED_Y REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 4) -#define PLANE_CTL_TILED_YF REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) -#define PLANE_CTL_TILED_4 REG_FIELD_PREP(PLANE_CTL_TILED_MASK, 5) -#define PLANE_CTL_ASYNC_FLIP REG_BIT(9) -#define PLANE_CTL_FLIP_HORIZONTAL REG_BIT(8) -#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE REG_BIT(4) /* TGL+ */ -#define PLANE_CTL_ALPHA_MASK REG_GENMASK(5, 4) /* Pre-GLK */ -#define PLANE_CTL_ALPHA_DISABLE REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 0) -#define PLANE_CTL_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 2) -#define PLANE_CTL_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_CTL_ALPHA_MASK, 3) -#define PLANE_CTL_ROTATE_MASK REG_GENMASK(1, 0) -#define PLANE_CTL_ROTATE_0 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 0) -#define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) -#define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) -#define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) -#define _PLANE_STRIDE_1_A 0x70188 -#define _PLANE_STRIDE_2_A 0x70288 -#define _PLANE_STRIDE_3_A 0x70388 -#define PLANE_STRIDE__MASK REG_GENMASK(11, 0) -#define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) -#define _PLANE_POS_1_A 0x7018c -#define _PLANE_POS_2_A 0x7028c -#define _PLANE_POS_3_A 0x7038c -#define PLANE_POS_Y_MASK REG_GENMASK(31, 16) -#define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) -#define PLANE_POS_X_MASK REG_GENMASK(15, 0) -#define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) -#define _PLANE_SIZE_1_A 0x70190 -#define _PLANE_SIZE_2_A 0x70290 -#define _PLANE_SIZE_3_A 0x70390 -#define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) -#define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) -#define PLANE_WIDTH_MASK REG_GENMASK(15, 0) -#define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) -#define _PLANE_SURF_1_A 0x7019c -#define _PLANE_SURF_2_A 0x7029c -#define _PLANE_SURF_3_A 0x7039c -#define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) -#define PLANE_SURF_DECRYPT REG_BIT(2) -#define _PLANE_OFFSET_1_A 0x701a4 -#define _PLANE_OFFSET_2_A 0x702a4 -#define _PLANE_OFFSET_3_A 0x703a4 -#define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) -#define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) -#define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) -#define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) -#define _PLANE_KEYVAL_1_A 0x70194 -#define _PLANE_KEYVAL_2_A 0x70294 -#define _PLANE_KEYMSK_1_A 0x70198 -#define _PLANE_KEYMSK_2_A 0x70298 -#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) -#define _PLANE_KEYMAX_1_A 0x701a0 -#define _PLANE_KEYMAX_2_A 0x702a0 -#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) -#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) -#define _PLANE_SURFLIVE_1_A 0x701ac -#define _PLANE_SURFLIVE_2_A 0x702ac -#define _PLANE_CC_VAL_1_A 0x701b4 -#define _PLANE_CC_VAL_2_A 0x702b4 -#define _PLANE_AUX_DIST_1_A 0x701c0 -#define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) -#define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) -#define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) -#define _PLANE_AUX_DIST_2_A 0x702c0 -#define _PLANE_AUX_OFFSET_1_A 0x701c4 -#define _PLANE_AUX_OFFSET_2_A 0x702c4 -#define _PLANE_CUS_CTL_1_A 0x701c8 -#define _PLANE_CUS_CTL_2_A 0x702c8 -#define PLANE_CUS_ENABLE REG_BIT(31) -#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) -#define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) -#define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) -#define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) -#define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) -#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) -#define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) -#define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) -#define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) -#define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) -#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) -#define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) -#define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) -#define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) -#define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) -#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ -#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ -#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ -#define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ -#define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) -#define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ -#define PLANE_COLOR_PLANE_CSC_ENABLE REG_BIT(21) /* ICL+ */ -#define PLANE_COLOR_INPUT_CSC_ENABLE REG_BIT(20) /* ICL+ */ -#define PLANE_COLOR_CSC_MODE_MASK REG_GENMASK(19, 17) -#define PLANE_COLOR_CSC_MODE_BYPASS REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 0) -#define PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 1) -#define PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 2) -#define PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 3) -#define PLANE_COLOR_CSC_MODE_RGB709_TO_RGB2020 REG_FIELD_PREP(PLANE_COLOR_CSC_MODE_MASK, 4) -#define PLANE_COLOR_PLANE_GAMMA_DISABLE REG_BIT(13) -#define PLANE_COLOR_ALPHA_MASK REG_GENMASK(5, 4) -#define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) -#define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) -#define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) -#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */ -#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */ -#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ -#define _PLANE_BUF_CFG_1_A 0x7027c -#define _PLANE_BUF_CFG_2_A 0x7037c -/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ -#define PLANE_BUF_END_MASK REG_GENMASK(27, 16) -#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) -#define PLANE_BUF_START_MASK REG_GENMASK(11, 0) -#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) -#define _PLANE_NV12_BUF_CFG_1_A 0x70278 -#define _PLANE_NV12_BUF_CFG_2_A 0x70378 - -#define _PLANE_CC_VAL_1_B 0x711b4 -#define _PLANE_CC_VAL_2_B 0x712b4 -#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) -#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) -#define PLANE_CC_VAL(pipe, plane, dw) \ - _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) - -/* Input CSC Register Definitions */ -#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 -#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 - -#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 -#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 - -#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ - _PLANE_INPUT_CSC_RY_GY_1_B) -#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ - _PLANE_INPUT_CSC_RY_GY_2_B) - -#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ - _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) - -#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 -#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 - -#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 -#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 - -#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ - _PLANE_INPUT_CSC_PREOFF_HI_1_B) -#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ - _PLANE_INPUT_CSC_PREOFF_HI_2_B) -#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ - _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) - -#define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 -#define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 - -#define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 -#define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 - -#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ - _PLANE_INPUT_CSC_POSTOFF_HI_1_B) -#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ - _PLANE_INPUT_CSC_POSTOFF_HI_2_B) -#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ - _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) - -#define _PLANE_CTL_1_B 0x71180 -#define _PLANE_CTL_2_B 0x71280 -#define _PLANE_CTL_3_B 0x71380 -#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) -#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) -#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) -#define PLANE_CTL(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) - -#define _PLANE_STRIDE_1_B 0x71188 -#define _PLANE_STRIDE_2_B 0x71288 -#define _PLANE_STRIDE_3_B 0x71388 -#define _PLANE_STRIDE_1(pipe) \ - _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) -#define _PLANE_STRIDE_2(pipe) \ - _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) -#define _PLANE_STRIDE_3(pipe) \ - _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) -#define PLANE_STRIDE(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) - -#define _PLANE_POS_1_B 0x7118c -#define _PLANE_POS_2_B 0x7128c -#define _PLANE_POS_3_B 0x7138c -#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) -#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) -#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) -#define PLANE_POS(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) - -#define _PLANE_SIZE_1_B 0x71190 -#define _PLANE_SIZE_2_B 0x71290 -#define _PLANE_SIZE_3_B 0x71390 -#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) -#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) -#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) -#define PLANE_SIZE(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) - -#define _PLANE_SURF_1_B 0x7119c -#define _PLANE_SURF_2_B 0x7129c -#define _PLANE_SURF_3_B 0x7139c -#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) -#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) -#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) -#define PLANE_SURF(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) - -#define _PLANE_OFFSET_1_B 0x711a4 -#define _PLANE_OFFSET_2_B 0x712a4 -#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) -#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) -#define PLANE_OFFSET(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) - -#define _PLANE_KEYVAL_1_B 0x71194 -#define _PLANE_KEYVAL_2_B 0x71294 -#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) -#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) -#define PLANE_KEYVAL(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) - -#define _PLANE_KEYMSK_1_B 0x71198 -#define _PLANE_KEYMSK_2_B 0x71298 -#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) -#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) -#define PLANE_KEYMSK(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) - -#define _PLANE_KEYMAX_1_B 0x711a0 -#define _PLANE_KEYMAX_2_B 0x712a0 -#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) -#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) -#define PLANE_KEYMAX(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) - -#define _PLANE_SURFLIVE_1_B 0x711ac -#define _PLANE_SURFLIVE_2_B 0x712ac -#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B) -#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) -#define PLANE_SURFLIVE(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe)) - -#define _PLANE_CHICKEN_1_B 0x7126c -#define _PLANE_CHICKEN_2_B 0x7136c -#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B) -#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) -#define PLANE_CHICKEN(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe)) - -#define _PLANE_AUX_DIST_1_B 0x711c0 -#define _PLANE_AUX_DIST_2_B 0x712c0 -#define _PLANE_AUX_DIST_1(pipe) \ - _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) -#define _PLANE_AUX_DIST_2(pipe) \ - _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) -#define PLANE_AUX_DIST(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) - -#define _PLANE_AUX_OFFSET_1_B 0x711c4 -#define _PLANE_AUX_OFFSET_2_B 0x712c4 -#define _PLANE_AUX_OFFSET_1(pipe) \ - _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) -#define _PLANE_AUX_OFFSET_2(pipe) \ - _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) -#define PLANE_AUX_OFFSET(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) - -#define _PLANE_CUS_CTL_1_B 0x711c8 -#define _PLANE_CUS_CTL_2_B 0x712c8 -#define _PLANE_CUS_CTL_1(pipe) \ - _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) -#define _PLANE_CUS_CTL_2(pipe) \ - _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) -#define PLANE_CUS_CTL(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) - -#define _PLANE_COLOR_CTL_1_B 0x711CC -#define _PLANE_COLOR_CTL_2_B 0x712CC -#define _PLANE_COLOR_CTL_3_B 0x713CC -#define _PLANE_COLOR_CTL_1(pipe) \ - _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) -#define _PLANE_COLOR_CTL_2(pipe) \ - _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) -#define PLANE_COLOR_CTL(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) /* VBIOS regs */ #define VGACNTRL _MMIO(0x71400) @@ -5151,49 +4799,6 @@ enum skl_power_gate { #define WM_DBG_DISALLOW_MAXFIFO (1 << 1) #define WM_DBG_DISALLOW_SPRITE (1 << 2) -/* Plane CSC Registers */ -#define _PLANE_CSC_RY_GY_1_A 0x70210 -#define _PLANE_CSC_RY_GY_2_A 0x70310 - -#define _PLANE_CSC_RY_GY_1_B 0x71210 -#define _PLANE_CSC_RY_GY_2_B 0x71310 - -#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ - _PLANE_CSC_RY_GY_1_B) -#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \ - _PLANE_CSC_RY_GY_2_B) -#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ - _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ - _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) - -#define _PLANE_CSC_PREOFF_HI_1_A 0x70228 -#define _PLANE_CSC_PREOFF_HI_2_A 0x70328 - -#define _PLANE_CSC_PREOFF_HI_1_B 0x71228 -#define _PLANE_CSC_PREOFF_HI_2_B 0x71328 - -#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ - _PLANE_CSC_PREOFF_HI_1_B) -#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ - _PLANE_CSC_PREOFF_HI_2_B) -#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ - (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ - (index) * 4) - -#define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 -#define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 - -#define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 -#define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 - -#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ - _PLANE_CSC_POSTOFF_HI_1_B) -#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ - _PLANE_CSC_POSTOFF_HI_2_B) -#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ - (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ - (index) * 4) - /* Gen4+ Timestamp and Pipe Frame time stamp registers */ #define GEN4_TIMESTAMP _MMIO(0x2358) #define ILK_TIMESTAMP_HI _MMIO(0x70070) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index e1a35f70b544..178eba121881 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -16,6 +16,7 @@ #include "display/intel_lvds_regs.h" #include "display/intel_psr_regs.h" #include "display/intel_sprite_regs.h" +#include "display/skl_universal_plane_regs.h" #include "display/skl_watermark_regs.h" #include "display/vlv_dsi_pll_regs.h" #include "gt/intel_engine_regs.h" -- cgit From 8cecf4aec31397f2cd7f9a1d277bef374dfea5c6 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:16 +0300 Subject: drm/i915: Extract intel_cursor_regs.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move most cursor register definitions into their own file. Declutters i915_reg.h a bit more. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 1 + drivers/gpu/drm/i915/display/intel_cursor_regs.h | 78 ++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 1 + drivers/gpu/drm/i915/gvt/display.c | 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 70 --------------------- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 8 files changed, 84 insertions(+), 70 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_cursor_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 2118b87ccb10..d2b459634732 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -14,6 +14,7 @@ #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_cursor.h" +#include "intel_cursor_regs.h" #include "intel_de.h" #include "intel_display.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h new file mode 100644 index 000000000000..62f7fb5c3f10 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_CURSOR_REGS_H__ +#define __INTEL_CURSOR_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define _CURACNTR 0x70080 +/* Old style CUR*CNTR flags (desktop 8xx) */ +#define CURSOR_ENABLE REG_BIT(31) +#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) +#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) +#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ +#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) +#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) +#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) +#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) +#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) +#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) +/* New style CUR*CNTR flags */ +#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ +#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ +#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) +#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) +#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) +#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ +#define MCURSOR_ROTATE_180 REG_BIT(15) +#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) +#define MCURSOR_MODE_MASK 0x27 +#define MCURSOR_MODE_DISABLE 0x00 +#define MCURSOR_MODE_128_32B_AX 0x02 +#define MCURSOR_MODE_256_32B_AX 0x03 +#define MCURSOR_MODE_64_2B 0x04 +#define MCURSOR_MODE_64_32B_AX 0x07 +#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) +#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) +#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) +#define _CURABASE 0x70084 +#define _CURAPOS 0x70088 +#define _CURAPOS_ERLY_TPT 0x7008c +#define CURSOR_POS_Y_SIGN REG_BIT(31) +#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) +#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) +#define CURSOR_POS_X_SIGN REG_BIT(15) +#define CURSOR_POS_X_MASK REG_GENMASK(14, 0) +#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) +#define _CURASIZE 0x700a0 /* 845/865 */ +#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) +#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) +#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) +#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) +#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ +#define CUR_FBC_EN REG_BIT(31) +#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) +#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) +#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ +#define _CURASURFLIVE 0x700ac /* g4x+ */ +#define _CURBCNTR 0x700c0 +#define _CURBBASE 0x700c4 +#define _CURBPOS 0x700c8 + +#define _CURBCNTR_IVB 0x71080 +#define _CURBBASE_IVB 0x71084 +#define _CURBPOS_IVB 0x71088 + +#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) +#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) +#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) +#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) +#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) +#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) +#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) +#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) + +#endif /* __INTEL_CURSOR_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9bb019fc9787..e29073b90860 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -65,6 +65,7 @@ #include "intel_crt.h" #include "intel_crtc.h" #include "intel_crtc_state_dump.h" +#include "intel_cursor_regs.h" #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_driver.h" diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 2514ac48312b..98dfd537070c 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -29,6 +29,7 @@ #include "i915_reg.h" #include "intel_atomic.h" #include "intel_crtc.h" +#include "intel_cursor_regs.h" #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 2b7df7fcf369..527e0bb2b15e 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -37,6 +37,7 @@ #include "gvt.h" #include "display/bxt_dpio_phy_regs.h" +#include "display/intel_cursor_regs.h" #include "display/intel_display.h" #include "display/intel_dpio_phy.h" #include "display/intel_sprite_regs.h" diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index dd6eb0ae003a..ac3ec9d1ef5f 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -40,6 +40,7 @@ #include "i915_pvinfo.h" #include "i915_reg.h" +#include "display/intel_cursor_regs.h" #include "display/intel_sprite_regs.h" #include "display/skl_universal_plane_regs.h" diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 08725dc7883e..52b029cd3981 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1762,8 +1762,6 @@ #define PIPE_LINK_M_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X) #define PIPE_LINK_N_G4X(pipe) _MMIO_PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X) -/* Display & cursor control */ - /* Pipe A */ #define _PIPEADSL 0x70000 #define PIPEDSL_CURR_FIELD REG_BIT(31) /* ctg+ */ @@ -2266,74 +2264,6 @@ #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) -/* Cursor A & B regs */ -#define _CURACNTR 0x70080 -/* Old style CUR*CNTR flags (desktop 8xx) */ -#define CURSOR_ENABLE REG_BIT(31) -#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) -#define CURSOR_STRIDE_MASK REG_GENMASK(29, 28) -#define CURSOR_STRIDE(stride) REG_FIELD_PREP(CURSOR_STRIDE_MASK, ffs(stride) - 9) /* 256,512,1k,2k */ -#define CURSOR_FORMAT_MASK REG_GENMASK(26, 24) -#define CURSOR_FORMAT_2C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 0) -#define CURSOR_FORMAT_3C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 1) -#define CURSOR_FORMAT_4C REG_FIELD_PREP(CURSOR_FORMAT_MASK, 2) -#define CURSOR_FORMAT_ARGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 4) -#define CURSOR_FORMAT_XRGB REG_FIELD_PREP(CURSOR_FORMAT_MASK, 5) -/* New style CUR*CNTR flags */ -#define MCURSOR_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ -#define MCURSOR_ARB_SLOTS(x) REG_FIELD_PREP(MCURSOR_ARB_SLOTS_MASK, (x)) /* icl+ */ -#define MCURSOR_PIPE_SEL_MASK REG_GENMASK(29, 28) -#define MCURSOR_PIPE_SEL(pipe) REG_FIELD_PREP(MCURSOR_PIPE_SEL_MASK, (pipe)) -#define MCURSOR_PIPE_GAMMA_ENABLE REG_BIT(26) -#define MCURSOR_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ -#define MCURSOR_ROTATE_180 REG_BIT(15) -#define MCURSOR_TRICKLE_FEED_DISABLE REG_BIT(14) -#define MCURSOR_MODE_MASK 0x27 -#define MCURSOR_MODE_DISABLE 0x00 -#define MCURSOR_MODE_128_32B_AX 0x02 -#define MCURSOR_MODE_256_32B_AX 0x03 -#define MCURSOR_MODE_64_2B 0x04 -#define MCURSOR_MODE_64_32B_AX 0x07 -#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) -#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) -#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) -#define _CURABASE 0x70084 -#define _CURAPOS 0x70088 -#define _CURAPOS_ERLY_TPT 0x7008c -#define CURSOR_POS_Y_SIGN REG_BIT(31) -#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) -#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) -#define CURSOR_POS_X_SIGN REG_BIT(15) -#define CURSOR_POS_X_MASK REG_GENMASK(14, 0) -#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) -#define _CURASIZE 0x700a0 /* 845/865 */ -#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) -#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) -#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) -#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) -#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ -#define CUR_FBC_EN REG_BIT(31) -#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) -#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) -#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ -#define _CURASURFLIVE 0x700ac /* g4x+ */ -#define _CURBCNTR 0x700c0 -#define _CURBBASE 0x700c4 -#define _CURBPOS 0x700c8 - -#define _CURBCNTR_IVB 0x71080 -#define _CURBBASE_IVB 0x71084 -#define _CURBPOS_IVB 0x71088 - -#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) -#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) -#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) -#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) -#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) -#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) -#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) -#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) - /* Display A control */ #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ #define _DSPACNTR 0x70180 diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 178eba121881..3b79c1c84b79 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -7,6 +7,7 @@ #include "display/intel_audio_regs.h" #include "display/intel_backlight_regs.h" #include "display/intel_color_regs.h" +#include "display/intel_cursor_regs.h" #include "display/intel_display_types.h" #include "display/intel_dmc_regs.h" #include "display/intel_dp_aux_regs.h" -- cgit From 88b2f5fbcc4c42e0cc5349577d750dc2a66cb58a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:17 +0300 Subject: drm/i915: Move skl+ wm/ddb registers to proper headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On SKL+ the watermark/DDB registers are proper per-plane registers. Move the definitons to their respective files. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 20 ++++++ .../drm/i915/display/skl_universal_plane_regs.h | 64 +++++++++++++++++ drivers/gpu/drm/i915/display/skl_watermark.c | 1 + drivers/gpu/drm/i915/display/skl_watermark_regs.h | 83 ---------------------- drivers/gpu/drm/i915/gvt/handlers.c | 1 + 5 files changed, 86 insertions(+), 83 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 62f7fb5c3f10..a478ef5787c5 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -75,4 +75,24 @@ #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) +/* skl+ */ +#define _CUR_WM_A_0 0x70140 +#define _CUR_WM_B_0 0x71140 +#define _CUR_WM_SAGV_A 0x70158 +#define _CUR_WM_SAGV_B 0x71158 +#define _CUR_WM_SAGV_TRANS_A 0x7015C +#define _CUR_WM_SAGV_TRANS_B 0x7115C +#define _CUR_WM_TRANS_A 0x70168 +#define _CUR_WM_TRANS_B 0x71168 +#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) +#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) +#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) +#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) +#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) + +/* skl+ */ +#define _CUR_BUF_CFG_A 0x7017c +#define _CUR_BUF_CFG_B 0x7117c +#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) + #endif /* __INTEL_CURSOR_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 7e34470beb74..2222d0c760e8 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -402,4 +402,68 @@ (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ (index) * 4) +#define _PLANE_WM_1_A_0 0x70240 +#define _PLANE_WM_1_B_0 0x71240 +#define _PLANE_WM_2_A_0 0x70340 +#define _PLANE_WM_2_B_0 0x71340 +#define _PLANE_WM_SAGV_1_A 0x70258 +#define _PLANE_WM_SAGV_1_B 0x71258 +#define _PLANE_WM_SAGV_2_A 0x70358 +#define _PLANE_WM_SAGV_2_B 0x71358 +#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C +#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C +#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C +#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C +#define _PLANE_WM_TRANS_1_A 0x70268 +#define _PLANE_WM_TRANS_1_B 0x71268 +#define _PLANE_WM_TRANS_2_A 0x70368 +#define _PLANE_WM_TRANS_2_B 0x71368 +#define PLANE_WM_EN (1 << 31) +#define PLANE_WM_IGNORE_LINES (1 << 30) +#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) +#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) + +#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) +#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) +#define _PLANE_WM_BASE(pipe, plane) \ + _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) +#define PLANE_WM(pipe, plane, level) \ + _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) +#define _PLANE_WM_SAGV_1(pipe) \ + _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) +#define _PLANE_WM_SAGV_2(pipe) \ + _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) +#define PLANE_WM_SAGV(pipe, plane) \ + _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) +#define _PLANE_WM_SAGV_TRANS_1(pipe) \ + _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) +#define _PLANE_WM_SAGV_TRANS_2(pipe) \ + _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) +#define PLANE_WM_SAGV_TRANS(pipe, plane) \ + _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) +#define _PLANE_WM_TRANS_1(pipe) \ + _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) +#define _PLANE_WM_TRANS_2(pipe) \ + _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) +#define PLANE_WM_TRANS(pipe, plane) \ + _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) + +#define _PLANE_BUF_CFG_1_B 0x7127c +#define _PLANE_BUF_CFG_2_B 0x7137c +#define _PLANE_BUF_CFG_1(pipe) \ + _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) +#define _PLANE_BUF_CFG_2(pipe) \ + _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) +#define PLANE_BUF_CFG(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) + +#define _PLANE_NV12_BUF_CFG_1_B 0x71278 +#define _PLANE_NV12_BUF_CFG_2_B 0x71378 +#define _PLANE_NV12_BUF_CFG_1(pipe) \ + _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) +#define _PLANE_NV12_BUF_CFG_2(pipe) \ + _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) +#define PLANE_NV12_BUF_CFG(pipe, plane) \ + _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) + #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 53a565c673e2..2a2073bf3aca 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -13,6 +13,7 @@ #include "intel_bw.h" #include "intel_cdclk.h" #include "intel_crtc.h" +#include "intel_cursor_regs.h" #include "intel_de.h" #include "intel_display.h" #include "intel_display_power.h" diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h index 269163fa3350..c5572fc0e847 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h @@ -43,89 +43,6 @@ #define MBUS_TRANSLATION_THROTTLE_MIN_MASK REG_GENMASK(15, 13) #define MBUS_TRANSLATION_THROTTLE_MIN(val) REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val) -/* Watermark register definitions for SKL */ -#define _CUR_WM_A_0 0x70140 -#define _CUR_WM_B_0 0x71140 -#define _CUR_WM_SAGV_A 0x70158 -#define _CUR_WM_SAGV_B 0x71158 -#define _CUR_WM_SAGV_TRANS_A 0x7015C -#define _CUR_WM_SAGV_TRANS_B 0x7115C -#define _CUR_WM_TRANS_A 0x70168 -#define _CUR_WM_TRANS_B 0x71168 -#define _PLANE_WM_1_A_0 0x70240 -#define _PLANE_WM_1_B_0 0x71240 -#define _PLANE_WM_2_A_0 0x70340 -#define _PLANE_WM_2_B_0 0x71340 -#define _PLANE_WM_SAGV_1_A 0x70258 -#define _PLANE_WM_SAGV_1_B 0x71258 -#define _PLANE_WM_SAGV_2_A 0x70358 -#define _PLANE_WM_SAGV_2_B 0x71358 -#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C -#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C -#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C -#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C -#define _PLANE_WM_TRANS_1_A 0x70268 -#define _PLANE_WM_TRANS_1_B 0x71268 -#define _PLANE_WM_TRANS_2_A 0x70368 -#define _PLANE_WM_TRANS_2_B 0x71368 -#define PLANE_WM_EN (1 << 31) -#define PLANE_WM_IGNORE_LINES (1 << 30) -#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) -#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) - -#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) -#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) -#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) -#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) -#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) -#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) -#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) -#define _PLANE_WM_BASE(pipe, plane) \ - _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) -#define PLANE_WM(pipe, plane, level) \ - _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) -#define _PLANE_WM_SAGV_1(pipe) \ - _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) -#define _PLANE_WM_SAGV_2(pipe) \ - _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) -#define PLANE_WM_SAGV(pipe, plane) \ - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) -#define _PLANE_WM_SAGV_TRANS_1(pipe) \ - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) -#define _PLANE_WM_SAGV_TRANS_2(pipe) \ - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) -#define PLANE_WM_SAGV_TRANS(pipe, plane) \ - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) -#define _PLANE_WM_TRANS_1(pipe) \ - _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) -#define _PLANE_WM_TRANS_2(pipe) \ - _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) -#define PLANE_WM_TRANS(pipe, plane) \ - _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) - -#define _PLANE_BUF_CFG_1_B 0x7127c -#define _PLANE_BUF_CFG_2_B 0x7137c -#define _PLANE_BUF_CFG_1(pipe) \ - _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) -#define _PLANE_BUF_CFG_2(pipe) \ - _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) -#define PLANE_BUF_CFG(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) - -#define _PLANE_NV12_BUF_CFG_1_B 0x71278 -#define _PLANE_NV12_BUF_CFG_2_B 0x71378 -#define _PLANE_NV12_BUF_CFG_1(pipe) \ - _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) -#define _PLANE_NV12_BUF_CFG_2(pipe) \ - _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) -#define PLANE_NV12_BUF_CFG(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) - -/* SKL new cursor registers */ -#define _CUR_BUF_CFG_A 0x7017c -#define _CUR_BUF_CFG_B 0x7117c -#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) - /* * The below are numbered starting from "S1" on gen11/gen12, but starting * with display 13, the bspec switches to a 0-based numbering scheme diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index aae0443015f0..6c857beb5083 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -42,6 +42,7 @@ #include "i915_pvinfo.h" #include "intel_mchbar_regs.h" #include "display/bxt_dpio_phy_regs.h" +#include "display/intel_cursor_regs.h" #include "display/intel_display_types.h" #include "display/intel_dmc_regs.h" #include "display/intel_dp_aux_regs.h" -- cgit From b86f87af3460747a829508d26a0fdf42daf807bd Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:18 +0300 Subject: drm/i915/gvt: Use the proper PLANE_AUX_DIST() define MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Stop hand rolling PLANE_AUX_DIST() and just use the real thing. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/handlers.c | 28 ++++++++++++++-------------- drivers/gpu/drm/i915/gvt/reg.h | 1 - drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++++++++++++------------ 3 files changed, 26 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 6c857beb5083..6b02612ddef5 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2678,20 +2678,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); - - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); - - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C0(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); + + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); + + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h index d8216c63c39a..e8a56faafe95 100644 --- a/drivers/gpu/drm/i915/gvt/reg.h +++ b/drivers/gpu/drm/i915/gvt/reg.h @@ -57,7 +57,6 @@ #define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B) -#define _REG_701C0(pipe, plane) (0x701c0 + pipe * 0x1000 + (plane - 1) * 0x100) #define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100) #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe)) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 3b79c1c84b79..cf45342a6db0 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -1006,18 +1006,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 1)); MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 2)); MMIO_D(PLANE_NV12_BUF_CFG(PIPE_C, 3)); - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 1))); - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 2))); - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 3))); - MMIO_D(_MMIO(_REG_701C0(PIPE_A, 4))); - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 1))); - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 2))); - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 3))); - MMIO_D(_MMIO(_REG_701C0(PIPE_B, 4))); - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 1))); - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 2))); - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 3))); - MMIO_D(_MMIO(_REG_701C0(PIPE_C, 4))); + MMIO_D(PLANE_AUX_DIST(PIPE_A, 0)); + MMIO_D(PLANE_AUX_DIST(PIPE_A, 1)); + MMIO_D(PLANE_AUX_DIST(PIPE_A, 2)); + MMIO_D(PLANE_AUX_DIST(PIPE_A, 3)); + MMIO_D(PLANE_AUX_DIST(PIPE_B, 0)); + MMIO_D(PLANE_AUX_DIST(PIPE_B, 1)); + MMIO_D(PLANE_AUX_DIST(PIPE_B, 2)); + MMIO_D(PLANE_AUX_DIST(PIPE_B, 3)); + MMIO_D(PLANE_AUX_DIST(PIPE_C, 0)); + MMIO_D(PLANE_AUX_DIST(PIPE_C, 1)); + MMIO_D(PLANE_AUX_DIST(PIPE_C, 2)); + MMIO_D(PLANE_AUX_DIST(PIPE_C, 3)); MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1))); MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2))); MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3))); -- cgit From 9d7d1e8b1c13322982da169176cbdd94f66f371d Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:19 +0300 Subject: drm/i915/gvt: Use the proper PLANE_AUX_OFFSET() define MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Stop hand rolling PLANE_AUX_OFFSET() and just use the real thing. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/handlers.c | 28 ++++++++++++++-------------- drivers/gpu/drm/i915/gvt/reg.h | 2 -- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 24 ++++++++++++------------ 3 files changed, 26 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 6b02612ddef5..6f633035618e 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2693,20 +2693,20 @@ static int init_skl_mmio_info(struct intel_gvt *gvt) MMIO_DH(PLANE_AUX_DIST(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); MMIO_DH(PLANE_AUX_DIST(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_A, 4)), D_SKL_PLUS, NULL, NULL); - - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_B, 4)), D_SKL_PLUS, NULL, NULL); - - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 1)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 2)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 3)), D_SKL_PLUS, NULL, NULL); - MMIO_DH(_MMIO(_REG_701C4(PIPE_C, 4)), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_A, 3), D_SKL_PLUS, NULL, NULL); + + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); + + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); + MMIO_DH(PLANE_AUX_OFFSET(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); MMIO_DFH(BDW_SCRATCH1, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL); diff --git a/drivers/gpu/drm/i915/gvt/reg.h b/drivers/gpu/drm/i915/gvt/reg.h index e8a56faafe95..90d8eb1761a3 100644 --- a/drivers/gpu/drm/i915/gvt/reg.h +++ b/drivers/gpu/drm/i915/gvt/reg.h @@ -57,8 +57,6 @@ #define VGT_SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _PLANE_STRIDE_2_B) -#define _REG_701C4(pipe, plane) (0x701c4 + pipe * 0x1000 + (plane - 1) * 0x100) - #define SKL_FLIP_EVENT(pipe, plane) (PRIMARY_A_FLIP_DONE + (plane) * 3 + (pipe)) #define REG50080_FLIP_TYPE_MASK 0x3 diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index cf45342a6db0..ad3bf60855bc 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -1018,18 +1018,18 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PLANE_AUX_DIST(PIPE_C, 1)); MMIO_D(PLANE_AUX_DIST(PIPE_C, 2)); MMIO_D(PLANE_AUX_DIST(PIPE_C, 3)); - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 1))); - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 2))); - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 3))); - MMIO_D(_MMIO(_REG_701C4(PIPE_A, 4))); - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 1))); - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 2))); - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 3))); - MMIO_D(_MMIO(_REG_701C4(PIPE_B, 4))); - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 1))); - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 2))); - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 3))); - MMIO_D(_MMIO(_REG_701C4(PIPE_C, 4))); + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 0)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 1)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 2)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_A, 3)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 0)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 1)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 2)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_B, 3)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 0)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2)); + MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3)); MMIO_D(_MMIO(_PLANE_CTL_3_A)); MMIO_D(_MMIO(_PLANE_CTL_3_B)); MMIO_D(_MMIO(0x72380)); -- cgit From 72d2031070e26f1de192cbcbbb45ba774183ab30 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:20 +0300 Subject: drm/i915/gvt: Use the full PLANE_KEY*() defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Stop hand rolling PLANE_KEY*() register defines and just use the real thing. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index ad3bf60855bc..b53c98cd6d7f 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -1075,15 +1075,15 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(_MMIO(0x70034)); MMIO_D(_MMIO(0x71034)); MMIO_D(_MMIO(0x72034)); - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_A))); - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_B))); - MMIO_D(_MMIO(_PLANE_KEYVAL_1(PIPE_C))); - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_A))); - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_B))); - MMIO_D(_MMIO(_PLANE_KEYMAX_1(PIPE_C))); - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_A))); - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_B))); - MMIO_D(_MMIO(_PLANE_KEYMSK_1(PIPE_C))); + MMIO_D(PLANE_KEYVAL(PIPE_A, 0)); + MMIO_D(PLANE_KEYVAL(PIPE_B, 0)); + MMIO_D(PLANE_KEYVAL(PIPE_C, 0)); + MMIO_D(PLANE_KEYMAX(PIPE_A, 0)); + MMIO_D(PLANE_KEYMAX(PIPE_B, 0)); + MMIO_D(PLANE_KEYMAX(PIPE_C, 0)); + MMIO_D(PLANE_KEYMSK(PIPE_A, 0)); + MMIO_D(PLANE_KEYMSK(PIPE_B, 0)); + MMIO_D(PLANE_KEYMSK(PIPE_C, 0)); MMIO_D(_MMIO(0x44500)); #define CSFE_CHICKEN1_REG(base) _MMIO((base) + 0xD4) MMIO_RING_D(CSFE_CHICKEN1_REG); -- cgit From 94b110106b48bd84be6c7fca3bc36a77f974a9a1 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:21 +0300 Subject: drm/i915/gvt: Use PLANE_CTL and PLANE_SURF defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Stop hand rolling PLANE_CTL and PLANE_SURF for the third plane and just use the real thing. Cc: Zhenyu Wang CC: Zhi Wang Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index b53c98cd6d7f..843bdb46d49c 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -1030,12 +1030,12 @@ static int iterate_skl_plus_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 1)); MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 2)); MMIO_D(PLANE_AUX_OFFSET(PIPE_C, 3)); - MMIO_D(_MMIO(_PLANE_CTL_3_A)); - MMIO_D(_MMIO(_PLANE_CTL_3_B)); - MMIO_D(_MMIO(0x72380)); - MMIO_D(_MMIO(0x7239c)); - MMIO_D(_MMIO(_PLANE_SURF_3_A)); - MMIO_D(_MMIO(_PLANE_SURF_3_B)); + MMIO_D(PLANE_CTL(PIPE_A, 2)); + MMIO_D(PLANE_CTL(PIPE_B, 2)); + MMIO_D(PLANE_CTL(PIPE_C, 2)); + MMIO_D(PLANE_SURF(PIPE_A, 2)); + MMIO_D(PLANE_SURF(PIPE_B, 2)); + MMIO_D(PLANE_SURF(PIPE_C, 2)); MMIO_D(DMC_SSP_BASE); MMIO_D(DMC_HTP_SKL); MMIO_D(DMC_LAST_WRITE); -- cgit From 86a30fb1224d407cb03e178d4cbebc94e1c38463 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 13 May 2024 19:58:42 +0300 Subject: drm/i915: Drop useless PLANE_FOO_3 register defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We only need register defines for the first two planes on the first two pipes. Nuke everything else. v2: Drop a few more that snuck through Reviewed-by: Jani Nikula #v1 Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240513165842.15199-1-ville.syrjala@linux.intel.com --- .../gpu/drm/i915/display/skl_universal_plane_regs.h | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 2222d0c760e8..49278584caa7 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -10,7 +10,6 @@ #define _PLANE_CTL_1_A 0x70180 #define _PLANE_CTL_2_A 0x70280 -#define _PLANE_CTL_3_A 0x70380 #define PLANE_CTL_ENABLE REG_BIT(31) #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ @@ -76,31 +75,26 @@ #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) #define _PLANE_STRIDE_1_A 0x70188 #define _PLANE_STRIDE_2_A 0x70288 -#define _PLANE_STRIDE_3_A 0x70388 #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) #define _PLANE_POS_1_A 0x7018c #define _PLANE_POS_2_A 0x7028c -#define _PLANE_POS_3_A 0x7038c #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) #define PLANE_POS_X_MASK REG_GENMASK(15, 0) #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) #define _PLANE_SIZE_1_A 0x70190 #define _PLANE_SIZE_2_A 0x70290 -#define _PLANE_SIZE_3_A 0x70390 #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) #define _PLANE_SURF_1_A 0x7019c #define _PLANE_SURF_2_A 0x7029c -#define _PLANE_SURF_3_A 0x7039c #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) #define PLANE_SURF_DECRYPT REG_BIT(2) #define _PLANE_OFFSET_1_A 0x701a4 #define _PLANE_OFFSET_2_A 0x702a4 -#define _PLANE_OFFSET_3_A 0x703a4 #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) @@ -145,7 +139,6 @@ #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) #define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ #define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ -#define _PLANE_COLOR_CTL_3_A 0x703CC /* GLK+ */ #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ @@ -234,49 +227,38 @@ #define _PLANE_CTL_1_B 0x71180 #define _PLANE_CTL_2_B 0x71280 -#define _PLANE_CTL_3_B 0x71380 #define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) #define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) -#define _PLANE_CTL_3(pipe) _PIPE(pipe, _PLANE_CTL_3_A, _PLANE_CTL_3_B) #define PLANE_CTL(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) #define _PLANE_STRIDE_1_B 0x71188 #define _PLANE_STRIDE_2_B 0x71288 -#define _PLANE_STRIDE_3_B 0x71388 #define _PLANE_STRIDE_1(pipe) \ _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) #define _PLANE_STRIDE_2(pipe) \ _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) -#define _PLANE_STRIDE_3(pipe) \ - _PIPE(pipe, _PLANE_STRIDE_3_A, _PLANE_STRIDE_3_B) #define PLANE_STRIDE(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) #define _PLANE_POS_1_B 0x7118c #define _PLANE_POS_2_B 0x7128c -#define _PLANE_POS_3_B 0x7138c #define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) #define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) -#define _PLANE_POS_3(pipe) _PIPE(pipe, _PLANE_POS_3_A, _PLANE_POS_3_B) #define PLANE_POS(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) #define _PLANE_SIZE_1_B 0x71190 #define _PLANE_SIZE_2_B 0x71290 -#define _PLANE_SIZE_3_B 0x71390 #define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) #define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) -#define _PLANE_SIZE_3(pipe) _PIPE(pipe, _PLANE_SIZE_3_A, _PLANE_SIZE_3_B) #define PLANE_SIZE(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) #define _PLANE_SURF_1_B 0x7119c #define _PLANE_SURF_2_B 0x7129c -#define _PLANE_SURF_3_B 0x7139c #define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) #define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) -#define _PLANE_SURF_3(pipe) _PIPE(pipe, _PLANE_SURF_3_A, _PLANE_SURF_3_B) #define PLANE_SURF(pipe, plane) \ _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) @@ -351,7 +333,6 @@ #define _PLANE_COLOR_CTL_1_B 0x711CC #define _PLANE_COLOR_CTL_2_B 0x712CC -#define _PLANE_COLOR_CTL_3_B 0x713CC #define _PLANE_COLOR_CTL_1(pipe) \ _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) #define _PLANE_COLOR_CTL_2(pipe) \ -- cgit From 14947416b1e412123ecb6cb7e819ebb4c74b1f81 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 13 May 2024 19:59:09 +0300 Subject: drm/i915: Shuffle the skl+ plane register definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rearrange the plane skl+ universal plane register definitions: - keep everything related to the same register in one place - sort based on register offset - unify the whitespace/etc a bit v2: Define register contents after all offsets (Jani) Cc: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240513165909.15234-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- .../drm/i915/display/skl_universal_plane_regs.h | 485 +++++++++------------ 1 file changed, 202 insertions(+), 283 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 49278584caa7..5fcd5898af4f 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -10,6 +10,11 @@ #define _PLANE_CTL_1_A 0x70180 #define _PLANE_CTL_2_A 0x70280 +#define _PLANE_CTL_1_B 0x71180 +#define _PLANE_CTL_2_B 0x71280 +#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) +#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) +#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) #define PLANE_CTL_ENABLE REG_BIT(31) #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ @@ -73,54 +78,132 @@ #define PLANE_CTL_ROTATE_90 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 1) #define PLANE_CTL_ROTATE_180 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 2) #define PLANE_CTL_ROTATE_270 REG_FIELD_PREP(PLANE_CTL_ROTATE_MASK, 3) + #define _PLANE_STRIDE_1_A 0x70188 #define _PLANE_STRIDE_2_A 0x70288 +#define _PLANE_STRIDE_1_B 0x71188 +#define _PLANE_STRIDE_2_B 0x71288 +#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) +#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) +#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) + #define _PLANE_POS_1_A 0x7018c #define _PLANE_POS_2_A 0x7028c +#define _PLANE_POS_1_B 0x7118c +#define _PLANE_POS_2_B 0x7128c +#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) +#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) +#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) #define PLANE_POS_X_MASK REG_GENMASK(15, 0) #define PLANE_POS_X(x) REG_FIELD_PREP(PLANE_POS_X_MASK, (x)) + #define _PLANE_SIZE_1_A 0x70190 #define _PLANE_SIZE_2_A 0x70290 +#define _PLANE_SIZE_1_B 0x71190 +#define _PLANE_SIZE_2_B 0x71290 +#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) +#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) +#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) #define PLANE_WIDTH(w) REG_FIELD_PREP(PLANE_WIDTH_MASK, (w)) + +#define _PLANE_KEYVAL_1_A 0x70194 +#define _PLANE_KEYVAL_2_A 0x70294 +#define _PLANE_KEYVAL_1_B 0x71194 +#define _PLANE_KEYVAL_2_B 0x71294 +#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) +#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) +#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) + +#define _PLANE_KEYMSK_1_A 0x70198 +#define _PLANE_KEYMSK_2_A 0x70298 +#define _PLANE_KEYMSK_1_B 0x71198 +#define _PLANE_KEYMSK_2_B 0x71298 +#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) +#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) +#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) +#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) + #define _PLANE_SURF_1_A 0x7019c #define _PLANE_SURF_2_A 0x7029c +#define _PLANE_SURF_1_B 0x7119c +#define _PLANE_SURF_2_B 0x7129c +#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) +#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) +#define PLANE_SURF(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) #define PLANE_SURF_DECRYPT REG_BIT(2) + +#define _PLANE_KEYMAX_1_A 0x701a0 +#define _PLANE_KEYMAX_2_A 0x702a0 +#define _PLANE_KEYMAX_1_B 0x711a0 +#define _PLANE_KEYMAX_2_B 0x712a0 +#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) +#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) +#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) +#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) +#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) + #define _PLANE_OFFSET_1_A 0x701a4 #define _PLANE_OFFSET_2_A 0x702a4 +#define _PLANE_OFFSET_1_B 0x711a4 +#define _PLANE_OFFSET_2_B 0x712a4 +#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) +#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) +#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) #define PLANE_OFFSET_X(x) REG_FIELD_PREP(PLANE_OFFSET_X_MASK, (x)) -#define _PLANE_KEYVAL_1_A 0x70194 -#define _PLANE_KEYVAL_2_A 0x70294 -#define _PLANE_KEYMSK_1_A 0x70198 -#define _PLANE_KEYMSK_2_A 0x70298 -#define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) -#define _PLANE_KEYMAX_1_A 0x701a0 -#define _PLANE_KEYMAX_2_A 0x702a0 -#define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) -#define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) + #define _PLANE_SURFLIVE_1_A 0x701ac #define _PLANE_SURFLIVE_2_A 0x702ac +#define _PLANE_SURFLIVE_1_B 0x711ac +#define _PLANE_SURFLIVE_2_B 0x712ac +#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B) +#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) +#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe)) + #define _PLANE_CC_VAL_1_A 0x701b4 #define _PLANE_CC_VAL_2_A 0x702b4 +#define _PLANE_CC_VAL_1_B 0x711b4 +#define _PLANE_CC_VAL_2_B 0x712b4 +#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) +#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) +#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) + #define _PLANE_AUX_DIST_1_A 0x701c0 +#define _PLANE_AUX_DIST_2_A 0x702c0 +#define _PLANE_AUX_DIST_1_B 0x711c0 +#define _PLANE_AUX_DIST_2_B 0x712c0 +#define _PLANE_AUX_DIST_1(pipe) _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) +#define _PLANE_AUX_DIST_2(pipe) _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) +#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) -#define _PLANE_AUX_DIST_2_A 0x702c0 + #define _PLANE_AUX_OFFSET_1_A 0x701c4 #define _PLANE_AUX_OFFSET_2_A 0x702c4 +#define _PLANE_AUX_OFFSET_1_B 0x711c4 +#define _PLANE_AUX_OFFSET_2_B 0x712c4 +#define _PLANE_AUX_OFFSET_1(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) +#define _PLANE_AUX_OFFSET_2(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) +#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) + #define _PLANE_CUS_CTL_1_A 0x701c8 #define _PLANE_CUS_CTL_2_A 0x702c8 +#define _PLANE_CUS_CTL_1_B 0x711c8 +#define _PLANE_CUS_CTL_2_B 0x712c8 +#define _PLANE_CUS_CTL_1(pipe) _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) +#define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) +#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) #define PLANE_CUS_ENABLE REG_BIT(31) #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) @@ -137,8 +220,14 @@ #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) #define PLANE_CUS_VPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 2) -#define _PLANE_COLOR_CTL_1_A 0x701CC /* GLK+ */ -#define _PLANE_COLOR_CTL_2_A 0x702CC /* GLK+ */ + +#define _PLANE_COLOR_CTL_1_A 0x701cc /* GLK+ */ +#define _PLANE_COLOR_CTL_2_A 0x702cc +#define _PLANE_COLOR_CTL_1_B 0x711cc +#define _PLANE_COLOR_CTL_2_B 0x712cc +#define _PLANE_COLOR_CTL_1(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) +#define _PLANE_COLOR_CTL_2(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) +#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ @@ -155,296 +244,126 @@ #define PLANE_COLOR_ALPHA_DISABLE REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 0) #define PLANE_COLOR_ALPHA_SW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 2) #define PLANE_COLOR_ALPHA_HW_PREMULTIPLY REG_FIELD_PREP(PLANE_COLOR_ALPHA_MASK, 3) -#define _PLANE_CHICKEN_1_A 0x7026C /* tgl+ */ -#define _PLANE_CHICKEN_2_A 0x7036C /* tgl+ */ -#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ -#define _PLANE_BUF_CFG_1_A 0x7027c -#define _PLANE_BUF_CFG_2_A 0x7037c -/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ -#define PLANE_BUF_END_MASK REG_GENMASK(27, 16) -#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) -#define PLANE_BUF_START_MASK REG_GENMASK(11, 0) -#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) -#define _PLANE_NV12_BUF_CFG_1_A 0x70278 -#define _PLANE_NV12_BUF_CFG_2_A 0x70378 -#define _PLANE_CC_VAL_1_B 0x711b4 -#define _PLANE_CC_VAL_2_B 0x712b4 -#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) -#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) -#define PLANE_CC_VAL(pipe, plane, dw) \ - _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) - -/* Input CSC Register Definitions */ -#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701E0 -#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702E0 - -#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711E0 -#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712E0 - -#define _PLANE_INPUT_CSC_RY_GY_1(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, \ - _PLANE_INPUT_CSC_RY_GY_1_B) -#define _PLANE_INPUT_CSC_RY_GY_2(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, \ - _PLANE_INPUT_CSC_RY_GY_2_B) - -#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, \ - _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) - -#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701F8 -#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702F8 - -#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711F8 -#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712F8 - -#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, \ - _PLANE_INPUT_CSC_PREOFF_HI_1_B) -#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, \ - _PLANE_INPUT_CSC_PREOFF_HI_2_B) -#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, \ - _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) +#define _PLANE_INPUT_CSC_RY_GY_1_A 0x701e0 +#define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0 +#define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0 +#define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0 +#define _PLANE_INPUT_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B) +#define _PLANE_INPUT_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B) +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) + +#define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8 +#define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8 +#define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8 +#define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8 +#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B) +#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B) +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 - #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 - -#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, \ - _PLANE_INPUT_CSC_POSTOFF_HI_1_B) -#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) \ - _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, \ - _PLANE_INPUT_CSC_POSTOFF_HI_2_B) -#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, \ - _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) - -#define _PLANE_CTL_1_B 0x71180 -#define _PLANE_CTL_2_B 0x71280 -#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) -#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) -#define PLANE_CTL(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) - -#define _PLANE_STRIDE_1_B 0x71188 -#define _PLANE_STRIDE_2_B 0x71288 -#define _PLANE_STRIDE_1(pipe) \ - _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) -#define _PLANE_STRIDE_2(pipe) \ - _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) -#define PLANE_STRIDE(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) - -#define _PLANE_POS_1_B 0x7118c -#define _PLANE_POS_2_B 0x7128c -#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) -#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) -#define PLANE_POS(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) - -#define _PLANE_SIZE_1_B 0x71190 -#define _PLANE_SIZE_2_B 0x71290 -#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) -#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) -#define PLANE_SIZE(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) - -#define _PLANE_SURF_1_B 0x7119c -#define _PLANE_SURF_2_B 0x7129c -#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) -#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) -#define PLANE_SURF(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) - -#define _PLANE_OFFSET_1_B 0x711a4 -#define _PLANE_OFFSET_2_B 0x712a4 -#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) -#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) -#define PLANE_OFFSET(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) - -#define _PLANE_KEYVAL_1_B 0x71194 -#define _PLANE_KEYVAL_2_B 0x71294 -#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) -#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) -#define PLANE_KEYVAL(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) - -#define _PLANE_KEYMSK_1_B 0x71198 -#define _PLANE_KEYMSK_2_B 0x71298 -#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) -#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) -#define PLANE_KEYMSK(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) - -#define _PLANE_KEYMAX_1_B 0x711a0 -#define _PLANE_KEYMAX_2_B 0x712a0 -#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) -#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) -#define PLANE_KEYMAX(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) - -#define _PLANE_SURFLIVE_1_B 0x711ac -#define _PLANE_SURFLIVE_2_B 0x712ac -#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B) -#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) -#define PLANE_SURFLIVE(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe)) - -#define _PLANE_CHICKEN_1_B 0x7126c -#define _PLANE_CHICKEN_2_B 0x7136c -#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B) -#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) -#define PLANE_CHICKEN(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe)) - -#define _PLANE_AUX_DIST_1_B 0x711c0 -#define _PLANE_AUX_DIST_2_B 0x712c0 -#define _PLANE_AUX_DIST_1(pipe) \ - _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) -#define _PLANE_AUX_DIST_2(pipe) \ - _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) -#define PLANE_AUX_DIST(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) - -#define _PLANE_AUX_OFFSET_1_B 0x711c4 -#define _PLANE_AUX_OFFSET_2_B 0x712c4 -#define _PLANE_AUX_OFFSET_1(pipe) \ - _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) -#define _PLANE_AUX_OFFSET_2(pipe) \ - _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) -#define PLANE_AUX_OFFSET(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) - -#define _PLANE_CUS_CTL_1_B 0x711c8 -#define _PLANE_CUS_CTL_2_B 0x712c8 -#define _PLANE_CUS_CTL_1(pipe) \ - _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) -#define _PLANE_CUS_CTL_2(pipe) \ - _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) -#define PLANE_CUS_CTL(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) - -#define _PLANE_COLOR_CTL_1_B 0x711CC -#define _PLANE_COLOR_CTL_2_B 0x712CC -#define _PLANE_COLOR_CTL_1(pipe) \ - _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) -#define _PLANE_COLOR_CTL_2(pipe) \ - _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) -#define PLANE_COLOR_CTL(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) - -/* Plane CSC Registers */ -#define _PLANE_CSC_RY_GY_1_A 0x70210 -#define _PLANE_CSC_RY_GY_2_A 0x70310 - -#define _PLANE_CSC_RY_GY_1_B 0x71210 -#define _PLANE_CSC_RY_GY_2_B 0x71310 - -#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, \ - _PLANE_CSC_RY_GY_1_B) -#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, \ - _PLANE_CSC_RY_GY_2_B) -#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_PLANE(plane, \ - _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, \ - _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) +#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B) +#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B) +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) + +#define _PLANE_CSC_RY_GY_1_A 0x70210 +#define _PLANE_CSC_RY_GY_2_A 0x70310 +#define _PLANE_CSC_RY_GY_1_B 0x71210 +#define _PLANE_CSC_RY_GY_2_B 0x71310 +#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B) +#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B) +#define PLANE_CSC_COEFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 - #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 - -#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, \ - _PLANE_CSC_PREOFF_HI_1_B) -#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, \ - _PLANE_CSC_PREOFF_HI_2_B) -#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + \ - (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + \ - (index) * 4) +#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B) +#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B) +#define PLANE_CSC_PREOFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4) #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 - #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 +#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B) +#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B) +#define PLANE_CSC_POSTOFF(pipe, plane, index) \ + _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4) + +#define _PLANE_WM_1_A_0 0x70240 +#define _PLANE_WM_1_B_0 0x71240 +#define _PLANE_WM_2_A_0 0x70340 +#define _PLANE_WM_2_B_0 0x71340 +#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) +#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) +#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) +#define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) +#define PLANE_WM_EN (1 << 31) +#define PLANE_WM_IGNORE_LINES (1 << 30) +#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) +#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) + +#define _PLANE_WM_SAGV_1_A 0x70258 +#define _PLANE_WM_SAGV_1_B 0x71258 +#define _PLANE_WM_SAGV_2_A 0x70358 +#define _PLANE_WM_SAGV_2_B 0x71358 +#define _PLANE_WM_SAGV_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) +#define _PLANE_WM_SAGV_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) +#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) + +#define _PLANE_WM_SAGV_TRANS_1_A 0x7025c +#define _PLANE_WM_SAGV_TRANS_1_B 0x7125c +#define _PLANE_WM_SAGV_TRANS_2_A 0x7035c +#define _PLANE_WM_SAGV_TRANS_2_B 0x7135c +#define _PLANE_WM_SAGV_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) +#define _PLANE_WM_SAGV_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) +#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) + +#define _PLANE_WM_TRANS_1_A 0x70268 +#define _PLANE_WM_TRANS_1_B 0x71268 +#define _PLANE_WM_TRANS_2_A 0x70368 +#define _PLANE_WM_TRANS_2_B 0x71368 +#define _PLANE_WM_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) +#define _PLANE_WM_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) +#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) + +#define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */ +#define _PLANE_CHICKEN_2_A 0x7036c +#define _PLANE_CHICKEN_1_B 0x7126c +#define _PLANE_CHICKEN_2_B 0x7136c +#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B) +#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) +#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe)) +#define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ -#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, \ - _PLANE_CSC_POSTOFF_HI_1_B) -#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, \ - _PLANE_CSC_POSTOFF_HI_2_B) -#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + \ - (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ - (index) * 4) - -#define _PLANE_WM_1_A_0 0x70240 -#define _PLANE_WM_1_B_0 0x71240 -#define _PLANE_WM_2_A_0 0x70340 -#define _PLANE_WM_2_B_0 0x71340 -#define _PLANE_WM_SAGV_1_A 0x70258 -#define _PLANE_WM_SAGV_1_B 0x71258 -#define _PLANE_WM_SAGV_2_A 0x70358 -#define _PLANE_WM_SAGV_2_B 0x71358 -#define _PLANE_WM_SAGV_TRANS_1_A 0x7025C -#define _PLANE_WM_SAGV_TRANS_1_B 0x7125C -#define _PLANE_WM_SAGV_TRANS_2_A 0x7035C -#define _PLANE_WM_SAGV_TRANS_2_B 0x7135C -#define _PLANE_WM_TRANS_1_A 0x70268 -#define _PLANE_WM_TRANS_1_B 0x71268 -#define _PLANE_WM_TRANS_2_A 0x70368 -#define _PLANE_WM_TRANS_2_B 0x71368 -#define PLANE_WM_EN (1 << 31) -#define PLANE_WM_IGNORE_LINES (1 << 30) -#define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) -#define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) - -#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) -#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) -#define _PLANE_WM_BASE(pipe, plane) \ - _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) -#define PLANE_WM(pipe, plane, level) \ - _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) -#define _PLANE_WM_SAGV_1(pipe) \ - _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) -#define _PLANE_WM_SAGV_2(pipe) \ - _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) -#define PLANE_WM_SAGV(pipe, plane) \ - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) -#define _PLANE_WM_SAGV_TRANS_1(pipe) \ - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) -#define _PLANE_WM_SAGV_TRANS_2(pipe) \ - _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) -#define PLANE_WM_SAGV_TRANS(pipe, plane) \ - _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) -#define _PLANE_WM_TRANS_1(pipe) \ - _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) -#define _PLANE_WM_TRANS_2(pipe) \ - _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) -#define PLANE_WM_TRANS(pipe, plane) \ - _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) +#define _PLANE_NV12_BUF_CFG_1_A 0x70278 +#define _PLANE_NV12_BUF_CFG_2_A 0x70378 +#define _PLANE_NV12_BUF_CFG_1_B 0x71278 +#define _PLANE_NV12_BUF_CFG_2_B 0x71378 +#define _PLANE_NV12_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) +#define _PLANE_NV12_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) +#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) +#define _PLANE_BUF_CFG_1_A 0x7027c +#define _PLANE_BUF_CFG_2_A 0x7037c #define _PLANE_BUF_CFG_1_B 0x7127c #define _PLANE_BUF_CFG_2_B 0x7137c -#define _PLANE_BUF_CFG_1(pipe) \ - _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) -#define _PLANE_BUF_CFG_2(pipe) \ - _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) -#define PLANE_BUF_CFG(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) - -#define _PLANE_NV12_BUF_CFG_1_B 0x71278 -#define _PLANE_NV12_BUF_CFG_2_B 0x71378 -#define _PLANE_NV12_BUF_CFG_1(pipe) \ - _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) -#define _PLANE_NV12_BUF_CFG_2(pipe) \ - _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) -#define PLANE_NV12_BUF_CFG(pipe, plane) \ - _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) +#define _PLANE_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) +#define _PLANE_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) +#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ +#define PLANE_BUF_END_MASK REG_GENMASK(27, 16) +#define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) +#define PLANE_BUF_START_MASK REG_GENMASK(11, 0) +#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */ -- cgit From 7deb50baf87a026a20c6e89f19f9e31dae329bc3 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 13 May 2024 19:59:45 +0300 Subject: drm/i915: Use REG_BIT for PLANE_WM bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A couple of PLANE_WM bits were still using the hand rolled (1< Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240513165945.15285-1-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 5fcd5898af4f..e8d399592fd3 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -307,8 +307,8 @@ #define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) #define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) #define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) -#define PLANE_WM_EN (1 << 31) -#define PLANE_WM_IGNORE_LINES (1 << 30) +#define PLANE_WM_EN REG_BIT(31) +#define PLANE_WM_IGNORE_LINES REG_BIT(30) #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) #define PLANE_WM_BLOCKS_MASK REG_GENMASK(11, 0) -- cgit From b7d4e9074ac06ea507f1927192ddf6c9cae8e085 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 13 May 2024 20:00:08 +0300 Subject: drm/i915: Drop a few unwanted tabs from skl+ plane reg defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A few extra tabs have snuck into the skl+ plane register bit definitions. Remove them. v2: Rebase Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240513170008.15338-1-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index e8d399592fd3..0b4f97059479 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -205,17 +205,17 @@ #define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) #define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) #define PLANE_CUS_ENABLE REG_BIT(31) -#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) +#define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) #define PLANE_CUS_Y_PLANE_5_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) #define PLANE_CUS_Y_PLANE_6_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) #define PLANE_CUS_Y_PLANE_7_ICL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 1) -#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) +#define PLANE_CUS_HPHASE_SIGN_NEGATIVE REG_BIT(19) #define PLANE_CUS_HPHASE_MASK REG_GENMASK(17, 16) #define PLANE_CUS_HPHASE_0 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 0) #define PLANE_CUS_HPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 1) #define PLANE_CUS_HPHASE_0_5 REG_FIELD_PREP(PLANE_CUS_HPHASE_MASK, 2) -#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) +#define PLANE_CUS_VPHASE_SIGN_NEGATIVE REG_BIT(15) #define PLANE_CUS_VPHASE_MASK REG_GENMASK(13, 12) #define PLANE_CUS_VPHASE_0 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 0) #define PLANE_CUS_VPHASE_0_25 REG_FIELD_PREP(PLANE_CUS_VPHASE_MASK, 1) -- cgit From 6f320c6a00ce4c7d917021b64bab1571b860915c Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 13 May 2024 20:00:40 +0300 Subject: drm/i915: Refactor skl+ plane register offset calculations MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently every skl+ plane register defines some intermediate macros to calculate the final register offset. Pull all of that into common macros, simplifying the final register offset stuff into just five defines: - raw register offsets for the planes 1 and 2 on pipes A and B - the final parametrized macro v2: Rebase Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240513170040.15393-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- .../drm/i915/display/skl_universal_plane_regs.h | 185 +++++++++++---------- 1 file changed, 93 insertions(+), 92 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 0b4f97059479..cb3bdd71b6b2 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -8,13 +8,22 @@ #include "intel_display_reg_defs.h" +#define _SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + _PLANE((plane), _PIPE((pipe), (reg_1_a), (reg_1_b)), _PIPE((pipe), (reg_2_a), (reg_2_b))) +#define _SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + (_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)) + (dw) * 4) +#define _MMIO_SKL_PLANE(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + _MMIO(_SKL_PLANE((pipe), (plane), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) +#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ + _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) + #define _PLANE_CTL_1_A 0x70180 #define _PLANE_CTL_2_A 0x70280 #define _PLANE_CTL_1_B 0x71180 #define _PLANE_CTL_2_B 0x71280 -#define _PLANE_CTL_1(pipe) _PIPE(pipe, _PLANE_CTL_1_A, _PLANE_CTL_1_B) -#define _PLANE_CTL_2(pipe) _PIPE(pipe, _PLANE_CTL_2_A, _PLANE_CTL_2_B) -#define PLANE_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CTL_1(pipe), _PLANE_CTL_2(pipe)) +#define PLANE_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_CTL_1_A, _PLANE_CTL_1_B, \ + _PLANE_CTL_2_A, _PLANE_CTL_2_B) #define PLANE_CTL_ENABLE REG_BIT(31) #define PLANE_CTL_ARB_SLOTS_MASK REG_GENMASK(30, 28) /* icl+ */ #define PLANE_CTL_ARB_SLOTS(x) REG_FIELD_PREP(PLANE_CTL_ARB_SLOTS_MASK, (x)) /* icl+ */ @@ -83,9 +92,9 @@ #define _PLANE_STRIDE_2_A 0x70288 #define _PLANE_STRIDE_1_B 0x71188 #define _PLANE_STRIDE_2_B 0x71288 -#define _PLANE_STRIDE_1(pipe) _PIPE(pipe, _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B) -#define _PLANE_STRIDE_2(pipe) _PIPE(pipe, _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) -#define PLANE_STRIDE(pipe, plane) _MMIO_PLANE(plane, _PLANE_STRIDE_1(pipe), _PLANE_STRIDE_2(pipe)) +#define PLANE_STRIDE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_STRIDE_1_A, _PLANE_STRIDE_1_B, \ + _PLANE_STRIDE_2_A, _PLANE_STRIDE_2_B) #define PLANE_STRIDE__MASK REG_GENMASK(11, 0) #define PLANE_STRIDE_(stride) REG_FIELD_PREP(PLANE_STRIDE__MASK, (stride)) @@ -93,9 +102,9 @@ #define _PLANE_POS_2_A 0x7028c #define _PLANE_POS_1_B 0x7118c #define _PLANE_POS_2_B 0x7128c -#define _PLANE_POS_1(pipe) _PIPE(pipe, _PLANE_POS_1_A, _PLANE_POS_1_B) -#define _PLANE_POS_2(pipe) _PIPE(pipe, _PLANE_POS_2_A, _PLANE_POS_2_B) -#define PLANE_POS(pipe, plane) _MMIO_PLANE(plane, _PLANE_POS_1(pipe), _PLANE_POS_2(pipe)) +#define PLANE_POS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_POS_1_A, _PLANE_POS_1_B, \ + _PLANE_POS_2_A, _PLANE_POS_2_B) #define PLANE_POS_Y_MASK REG_GENMASK(31, 16) #define PLANE_POS_Y(y) REG_FIELD_PREP(PLANE_POS_Y_MASK, (y)) #define PLANE_POS_X_MASK REG_GENMASK(15, 0) @@ -105,9 +114,9 @@ #define _PLANE_SIZE_2_A 0x70290 #define _PLANE_SIZE_1_B 0x71190 #define _PLANE_SIZE_2_B 0x71290 -#define _PLANE_SIZE_1(pipe) _PIPE(pipe, _PLANE_SIZE_1_A, _PLANE_SIZE_1_B) -#define _PLANE_SIZE_2(pipe) _PIPE(pipe, _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) -#define PLANE_SIZE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SIZE_1(pipe), _PLANE_SIZE_2(pipe)) +#define PLANE_SIZE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_SIZE_1_A, _PLANE_SIZE_1_B, \ + _PLANE_SIZE_2_A, _PLANE_SIZE_2_B) #define PLANE_HEIGHT_MASK REG_GENMASK(31, 16) #define PLANE_HEIGHT(h) REG_FIELD_PREP(PLANE_HEIGHT_MASK, (h)) #define PLANE_WIDTH_MASK REG_GENMASK(15, 0) @@ -117,26 +126,26 @@ #define _PLANE_KEYVAL_2_A 0x70294 #define _PLANE_KEYVAL_1_B 0x71194 #define _PLANE_KEYVAL_2_B 0x71294 -#define _PLANE_KEYVAL_1(pipe) _PIPE(pipe, _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B) -#define _PLANE_KEYVAL_2(pipe) _PIPE(pipe, _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) -#define PLANE_KEYVAL(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYVAL_1(pipe), _PLANE_KEYVAL_2(pipe)) +#define PLANE_KEYVAL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane),\ + _PLANE_KEYVAL_1_A, _PLANE_KEYVAL_1_B, \ + _PLANE_KEYVAL_2_A, _PLANE_KEYVAL_2_B) #define _PLANE_KEYMSK_1_A 0x70198 #define _PLANE_KEYMSK_2_A 0x70298 #define _PLANE_KEYMSK_1_B 0x71198 #define _PLANE_KEYMSK_2_B 0x71298 -#define _PLANE_KEYMSK_1(pipe) _PIPE(pipe, _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B) -#define _PLANE_KEYMSK_2(pipe) _PIPE(pipe, _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) -#define PLANE_KEYMSK(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMSK_1(pipe), _PLANE_KEYMSK_2(pipe)) +#define PLANE_KEYMSK(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_KEYMSK_1_A, _PLANE_KEYMSK_1_B, \ + _PLANE_KEYMSK_2_A, _PLANE_KEYMSK_2_B) #define PLANE_KEYMSK_ALPHA_ENABLE REG_BIT(31) #define _PLANE_SURF_1_A 0x7019c #define _PLANE_SURF_2_A 0x7029c #define _PLANE_SURF_1_B 0x7119c #define _PLANE_SURF_2_B 0x7129c -#define _PLANE_SURF_1(pipe) _PIPE(pipe, _PLANE_SURF_1_A, _PLANE_SURF_1_B) -#define _PLANE_SURF_2(pipe) _PIPE(pipe, _PLANE_SURF_2_A, _PLANE_SURF_2_B) -#define PLANE_SURF(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURF_1(pipe), _PLANE_SURF_2(pipe)) +#define PLANE_SURF(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_SURF_1_A, _PLANE_SURF_1_B, \ + _PLANE_SURF_2_A, _PLANE_SURF_2_B) #define PLANE_SURF_ADDR_MASK REG_GENMASK(31, 12) #define PLANE_SURF_DECRYPT REG_BIT(2) @@ -144,9 +153,9 @@ #define _PLANE_KEYMAX_2_A 0x702a0 #define _PLANE_KEYMAX_1_B 0x711a0 #define _PLANE_KEYMAX_2_B 0x712a0 -#define _PLANE_KEYMAX_1(pipe) _PIPE(pipe, _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B) -#define _PLANE_KEYMAX_2(pipe) _PIPE(pipe, _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) -#define PLANE_KEYMAX(pipe, plane) _MMIO_PLANE(plane, _PLANE_KEYMAX_1(pipe), _PLANE_KEYMAX_2(pipe)) +#define PLANE_KEYMAX(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_KEYMAX_1_A, _PLANE_KEYMAX_1_B, \ + _PLANE_KEYMAX_2_A, _PLANE_KEYMAX_2_B) #define PLANE_KEYMAX_ALPHA_MASK REG_GENMASK(31, 24) #define PLANE_KEYMAX_ALPHA(a) REG_FIELD_PREP(PLANE_KEYMAX_ALPHA_MASK, (a)) @@ -154,9 +163,9 @@ #define _PLANE_OFFSET_2_A 0x702a4 #define _PLANE_OFFSET_1_B 0x711a4 #define _PLANE_OFFSET_2_B 0x712a4 -#define _PLANE_OFFSET_1(pipe) _PIPE(pipe, _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B) -#define _PLANE_OFFSET_2(pipe) _PIPE(pipe, _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) -#define PLANE_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_OFFSET_1(pipe), _PLANE_OFFSET_2(pipe)) +#define PLANE_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_OFFSET_1_A, _PLANE_OFFSET_1_B, \ + _PLANE_OFFSET_2_A, _PLANE_OFFSET_2_B) #define PLANE_OFFSET_Y_MASK REG_GENMASK(31, 16) #define PLANE_OFFSET_Y(y) REG_FIELD_PREP(PLANE_OFFSET_Y_MASK, (y)) #define PLANE_OFFSET_X_MASK REG_GENMASK(15, 0) @@ -166,25 +175,25 @@ #define _PLANE_SURFLIVE_2_A 0x702ac #define _PLANE_SURFLIVE_1_B 0x711ac #define _PLANE_SURFLIVE_2_B 0x712ac -#define _PLANE_SURFLIVE_1(pipe) _PIPE(pipe, _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B) -#define _PLANE_SURFLIVE_2(pipe) _PIPE(pipe, _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) -#define PLANE_SURFLIVE(pipe, plane) _MMIO_PLANE(plane, _PLANE_SURFLIVE_1(pipe), _PLANE_SURFLIVE_2(pipe)) +#define PLANE_SURFLIVE(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_SURFLIVE_1_A, _PLANE_SURFLIVE_1_B, \ + _PLANE_SURFLIVE_2_A, _PLANE_SURFLIVE_2_B) #define _PLANE_CC_VAL_1_A 0x701b4 #define _PLANE_CC_VAL_2_A 0x702b4 #define _PLANE_CC_VAL_1_B 0x711b4 #define _PLANE_CC_VAL_2_B 0x712b4 -#define _PLANE_CC_VAL_1(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B) + (dw) * 4) -#define _PLANE_CC_VAL_2(pipe, dw) (_PIPE(pipe, _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) + (dw) * 4) -#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_PLANE((plane), _PLANE_CC_VAL_1((pipe), (dw)), _PLANE_CC_VAL_2((pipe), (dw))) +#define PLANE_CC_VAL(pipe, plane, dw) _MMIO_SKL_PLANE_DW((pipe), (plane), (dw), \ + _PLANE_CC_VAL_1_A, _PLANE_CC_VAL_1_B, \ + _PLANE_CC_VAL_2_A, _PLANE_CC_VAL_2_B) #define _PLANE_AUX_DIST_1_A 0x701c0 #define _PLANE_AUX_DIST_2_A 0x702c0 #define _PLANE_AUX_DIST_1_B 0x711c0 #define _PLANE_AUX_DIST_2_B 0x712c0 -#define _PLANE_AUX_DIST_1(pipe) _PIPE(pipe, _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B) -#define _PLANE_AUX_DIST_2(pipe) _PIPE(pipe, _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) -#define PLANE_AUX_DIST(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_DIST_1(pipe), _PLANE_AUX_DIST_2(pipe)) +#define PLANE_AUX_DIST(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_AUX_DIST_1_A, _PLANE_AUX_DIST_1_B, \ + _PLANE_AUX_DIST_2_A, _PLANE_AUX_DIST_2_B) #define PLANE_AUX_DISTANCE_MASK REG_GENMASK(31, 12) #define PLANE_AUX_STRIDE_MASK REG_GENMASK(11, 0) #define PLANE_AUX_STRIDE(stride) REG_FIELD_PREP(PLANE_AUX_STRIDE_MASK, (stride)) @@ -193,17 +202,17 @@ #define _PLANE_AUX_OFFSET_2_A 0x702c4 #define _PLANE_AUX_OFFSET_1_B 0x711c4 #define _PLANE_AUX_OFFSET_2_B 0x712c4 -#define _PLANE_AUX_OFFSET_1(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B) -#define _PLANE_AUX_OFFSET_2(pipe) _PIPE(pipe, _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) -#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_PLANE(plane, _PLANE_AUX_OFFSET_1(pipe), _PLANE_AUX_OFFSET_2(pipe)) +#define PLANE_AUX_OFFSET(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_AUX_OFFSET_1_A, _PLANE_AUX_OFFSET_1_B, \ + _PLANE_AUX_OFFSET_2_A, _PLANE_AUX_OFFSET_2_B) #define _PLANE_CUS_CTL_1_A 0x701c8 #define _PLANE_CUS_CTL_2_A 0x702c8 #define _PLANE_CUS_CTL_1_B 0x711c8 #define _PLANE_CUS_CTL_2_B 0x712c8 -#define _PLANE_CUS_CTL_1(pipe) _PIPE(pipe, _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B) -#define _PLANE_CUS_CTL_2(pipe) _PIPE(pipe, _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) -#define PLANE_CUS_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_CUS_CTL_1(pipe), _PLANE_CUS_CTL_2(pipe)) +#define PLANE_CUS_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_CUS_CTL_1_A, _PLANE_CUS_CTL_1_B, \ + _PLANE_CUS_CTL_2_A, _PLANE_CUS_CTL_2_B) #define PLANE_CUS_ENABLE REG_BIT(31) #define PLANE_CUS_Y_PLANE_MASK REG_BIT(30) #define PLANE_CUS_Y_PLANE_4_RKL REG_FIELD_PREP(PLANE_CUS_Y_PLANE_MASK, 0) @@ -225,9 +234,9 @@ #define _PLANE_COLOR_CTL_2_A 0x702cc #define _PLANE_COLOR_CTL_1_B 0x711cc #define _PLANE_COLOR_CTL_2_B 0x712cc -#define _PLANE_COLOR_CTL_1(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B) -#define _PLANE_COLOR_CTL_2(pipe) _PIPE(pipe, _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) -#define PLANE_COLOR_CTL(pipe, plane) _MMIO_PLANE(plane, _PLANE_COLOR_CTL_1(pipe), _PLANE_COLOR_CTL_2(pipe)) +#define PLANE_COLOR_CTL(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_COLOR_CTL_1_A, _PLANE_COLOR_CTL_1_B, \ + _PLANE_COLOR_CTL_2_A, _PLANE_COLOR_CTL_2_B) #define PLANE_COLOR_PIPE_GAMMA_ENABLE REG_BIT(30) /* Pre-ICL */ #define PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) #define PLANE_COLOR_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-ICL */ @@ -249,64 +258,56 @@ #define _PLANE_INPUT_CSC_RY_GY_2_A 0x702e0 #define _PLANE_INPUT_CSC_RY_GY_1_B 0x711e0 #define _PLANE_INPUT_CSC_RY_GY_2_B 0x712e0 -#define _PLANE_INPUT_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B) -#define _PLANE_INPUT_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B) -#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_RY_GY_2(pipe) + (index) * 4) +#define PLANE_INPUT_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ + _PLANE_INPUT_CSC_RY_GY_1_A, _PLANE_INPUT_CSC_RY_GY_1_B, \ + _PLANE_INPUT_CSC_RY_GY_2_A, _PLANE_INPUT_CSC_RY_GY_2_B) #define _PLANE_INPUT_CSC_PREOFF_HI_1_A 0x701f8 #define _PLANE_INPUT_CSC_PREOFF_HI_2_A 0x702f8 #define _PLANE_INPUT_CSC_PREOFF_HI_1_B 0x711f8 #define _PLANE_INPUT_CSC_PREOFF_HI_2_B 0x712f8 -#define _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B) -#define _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B) -#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_PREOFF_HI_2(pipe) + (index) * 4) +#define PLANE_INPUT_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ + _PLANE_INPUT_CSC_PREOFF_HI_1_A, _PLANE_INPUT_CSC_PREOFF_HI_1_B, \ + _PLANE_INPUT_CSC_PREOFF_HI_2_A, _PLANE_INPUT_CSC_PREOFF_HI_2_B) #define _PLANE_INPUT_CSC_POSTOFF_HI_1_A 0x70204 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_A 0x70304 #define _PLANE_INPUT_CSC_POSTOFF_HI_1_B 0x71204 #define _PLANE_INPUT_CSC_POSTOFF_HI_2_B 0x71304 -#define _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B) -#define _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B) -#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_INPUT_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_INPUT_CSC_POSTOFF_HI_2(pipe) + (index) * 4) +#define PLANE_INPUT_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ + _PLANE_INPUT_CSC_POSTOFF_HI_1_A, _PLANE_INPUT_CSC_POSTOFF_HI_1_B, \ + _PLANE_INPUT_CSC_POSTOFF_HI_2_A, _PLANE_INPUT_CSC_POSTOFF_HI_2_B) #define _PLANE_CSC_RY_GY_1_A 0x70210 #define _PLANE_CSC_RY_GY_2_A 0x70310 #define _PLANE_CSC_RY_GY_1_B 0x71210 #define _PLANE_CSC_RY_GY_2_B 0x71310 -#define _PLANE_CSC_RY_GY_1(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B) -#define _PLANE_CSC_RY_GY_2(pipe) _PIPE(pipe, _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B) -#define PLANE_CSC_COEFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_CSC_RY_GY_1(pipe) + (index) * 4, _PLANE_CSC_RY_GY_2(pipe) + (index) * 4) +#define PLANE_CSC_COEFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ + _PLANE_CSC_RY_GY_1_A, _PLANE_CSC_RY_GY_1_B, \ + _PLANE_CSC_RY_GY_2_A, _PLANE_CSC_RY_GY_2_B) #define _PLANE_CSC_PREOFF_HI_1_A 0x70228 #define _PLANE_CSC_PREOFF_HI_2_A 0x70328 #define _PLANE_CSC_PREOFF_HI_1_B 0x71228 #define _PLANE_CSC_PREOFF_HI_2_B 0x71328 -#define _PLANE_CSC_PREOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B) -#define _PLANE_CSC_PREOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B) -#define PLANE_CSC_PREOFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_CSC_PREOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_PREOFF_HI_2(pipe) + (index) * 4) +#define PLANE_CSC_PREOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ + _PLANE_CSC_PREOFF_HI_1_A, _PLANE_CSC_PREOFF_HI_1_B, \ + _PLANE_CSC_PREOFF_HI_2_A, _PLANE_CSC_PREOFF_HI_2_B) #define _PLANE_CSC_POSTOFF_HI_1_A 0x70234 #define _PLANE_CSC_POSTOFF_HI_2_A 0x70334 #define _PLANE_CSC_POSTOFF_HI_1_B 0x71234 #define _PLANE_CSC_POSTOFF_HI_2_B 0x71334 -#define _PLANE_CSC_POSTOFF_HI_1(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B) -#define _PLANE_CSC_POSTOFF_HI_2(pipe) _PIPE(pipe, _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B) -#define PLANE_CSC_POSTOFF(pipe, plane, index) \ - _MMIO_PLANE(plane, _PLANE_CSC_POSTOFF_HI_1(pipe) + (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + (index) * 4) - +#define PLANE_CSC_POSTOFF(pipe, plane, index) _MMIO_SKL_PLANE_DW((pipe), (plane), (index), \ + _PLANE_CSC_POSTOFF_HI_1_A, _PLANE_CSC_POSTOFF_HI_1_B, \ + _PLANE_CSC_POSTOFF_HI_2_A, _PLANE_CSC_POSTOFF_HI_2_B) #define _PLANE_WM_1_A_0 0x70240 #define _PLANE_WM_1_B_0 0x71240 #define _PLANE_WM_2_A_0 0x70340 #define _PLANE_WM_2_B_0 0x71340 -#define _PLANE_WM_1(pipe) _PIPE(pipe, _PLANE_WM_1_A_0, _PLANE_WM_1_B_0) -#define _PLANE_WM_2(pipe) _PIPE(pipe, _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) -#define _PLANE_WM_BASE(pipe, plane) _PLANE(plane, _PLANE_WM_1(pipe), _PLANE_WM_2(pipe)) -#define PLANE_WM(pipe, plane, level) _MMIO(_PLANE_WM_BASE(pipe, plane) + ((4) * (level))) +#define PLANE_WM(pipe, plane, level) _MMIO_SKL_PLANE_DW((pipe), (plane), (level), \ + _PLANE_WM_1_A_0, _PLANE_WM_1_B_0, \ + _PLANE_WM_2_A_0, _PLANE_WM_2_B_0) #define PLANE_WM_EN REG_BIT(31) #define PLANE_WM_IGNORE_LINES REG_BIT(30) #define PLANE_WM_LINES_MASK REG_GENMASK(26, 14) @@ -316,50 +317,50 @@ #define _PLANE_WM_SAGV_1_B 0x71258 #define _PLANE_WM_SAGV_2_A 0x70358 #define _PLANE_WM_SAGV_2_B 0x71358 -#define _PLANE_WM_SAGV_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B) -#define _PLANE_WM_SAGV_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) -#define PLANE_WM_SAGV(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_1(pipe), _PLANE_WM_SAGV_2(pipe))) +#define PLANE_WM_SAGV(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_WM_SAGV_1_A, _PLANE_WM_SAGV_1_B, \ + _PLANE_WM_SAGV_2_A, _PLANE_WM_SAGV_2_B) #define _PLANE_WM_SAGV_TRANS_1_A 0x7025c #define _PLANE_WM_SAGV_TRANS_1_B 0x7125c #define _PLANE_WM_SAGV_TRANS_2_A 0x7035c #define _PLANE_WM_SAGV_TRANS_2_B 0x7135c -#define _PLANE_WM_SAGV_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B) -#define _PLANE_WM_SAGV_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) -#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_SAGV_TRANS_1(pipe), _PLANE_WM_SAGV_TRANS_2(pipe))) +#define PLANE_WM_SAGV_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_WM_SAGV_TRANS_1_A, _PLANE_WM_SAGV_TRANS_1_B, \ + _PLANE_WM_SAGV_TRANS_2_A, _PLANE_WM_SAGV_TRANS_2_B) #define _PLANE_WM_TRANS_1_A 0x70268 #define _PLANE_WM_TRANS_1_B 0x71268 #define _PLANE_WM_TRANS_2_A 0x70368 #define _PLANE_WM_TRANS_2_B 0x71368 -#define _PLANE_WM_TRANS_1(pipe) _PIPE(pipe, _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B) -#define _PLANE_WM_TRANS_2(pipe) _PIPE(pipe, _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) -#define PLANE_WM_TRANS(pipe, plane) _MMIO(_PLANE(plane, _PLANE_WM_TRANS_1(pipe), _PLANE_WM_TRANS_2(pipe))) +#define PLANE_WM_TRANS(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_WM_TRANS_1_A, _PLANE_WM_TRANS_1_B, \ + _PLANE_WM_TRANS_2_A, _PLANE_WM_TRANS_2_B) #define _PLANE_CHICKEN_1_A 0x7026c /* tgl+ */ #define _PLANE_CHICKEN_2_A 0x7036c #define _PLANE_CHICKEN_1_B 0x7126c #define _PLANE_CHICKEN_2_B 0x7136c -#define _PLANE_CHICKEN_1(pipe) _PIPE(pipe, _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B) -#define _PLANE_CHICKEN_2(pipe) _PIPE(pipe, _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) -#define PLANE_CHICKEN(pipe, plane) _MMIO_PLANE(plane, _PLANE_CHICKEN_1(pipe), _PLANE_CHICKEN_2(pipe)) +#define PLANE_CHICKEN(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_CHICKEN_1_A, _PLANE_CHICKEN_1_B, \ + _PLANE_CHICKEN_2_A, _PLANE_CHICKEN_2_B) #define PLANE_CHICKEN_DISABLE_DPT REG_BIT(19) /* mtl+ */ #define _PLANE_NV12_BUF_CFG_1_A 0x70278 #define _PLANE_NV12_BUF_CFG_2_A 0x70378 #define _PLANE_NV12_BUF_CFG_1_B 0x71278 #define _PLANE_NV12_BUF_CFG_2_B 0x71378 -#define _PLANE_NV12_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B) -#define _PLANE_NV12_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) -#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_NV12_BUF_CFG_1(pipe), _PLANE_NV12_BUF_CFG_2(pipe)) +#define PLANE_NV12_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_NV12_BUF_CFG_1_A, _PLANE_NV12_BUF_CFG_1_B, \ + _PLANE_NV12_BUF_CFG_2_A, _PLANE_NV12_BUF_CFG_2_B) #define _PLANE_BUF_CFG_1_A 0x7027c #define _PLANE_BUF_CFG_2_A 0x7037c #define _PLANE_BUF_CFG_1_B 0x7127c #define _PLANE_BUF_CFG_2_B 0x7137c -#define _PLANE_BUF_CFG_1(pipe) _PIPE(pipe, _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B) -#define _PLANE_BUF_CFG_2(pipe) _PIPE(pipe, _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) -#define PLANE_BUF_CFG(pipe, plane) _MMIO_PLANE(plane, _PLANE_BUF_CFG_1(pipe), _PLANE_BUF_CFG_2(pipe)) +#define PLANE_BUF_CFG(pipe, plane) _MMIO_SKL_PLANE((pipe), (plane), \ + _PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \ + _PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B) /* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ #define PLANE_BUF_END_MASK REG_GENMASK(27, 16) #define PLANE_BUF_END(end) REG_FIELD_PREP(PLANE_BUF_END_MASK, (end)) -- cgit From 1b455361d57016e820803b9c61eb68cd1db48a88 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:27 +0300 Subject: drm/i915: Extract skl_plane_{wm,ddb}_reg_val() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extract helpers to calculate the final wm/ddb register values for skl+. Will allow me to more cleanly remove the register write wrappers for these registers. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-15-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/skl_watermark.c | 29 ++++++++++++++++++---------- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 2a2073bf3aca..8a0a26ab8e6a 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2365,21 +2365,23 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state, return skl_wm_check_vblank(crtc_state); } +static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry) +{ + if (!entry->end) + return 0; + + return PLANE_BUF_END(entry->end - 1) | + PLANE_BUF_START(entry->start); +} + static void skl_ddb_entry_write(struct drm_i915_private *i915, i915_reg_t reg, const struct skl_ddb_entry *entry) { - if (entry->end) - intel_de_write_fw(i915, reg, - PLANE_BUF_END(entry->end - 1) | - PLANE_BUF_START(entry->start)); - else - intel_de_write_fw(i915, reg, 0); + intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry)); } -static void skl_write_wm_level(struct drm_i915_private *i915, - i915_reg_t reg, - const struct skl_wm_level *level) +static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) { u32 val = 0; @@ -2390,7 +2392,14 @@ static void skl_write_wm_level(struct drm_i915_private *i915, val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); - intel_de_write_fw(i915, reg, val); + return val; +} + +static void skl_write_wm_level(struct drm_i915_private *i915, + i915_reg_t reg, + const struct skl_wm_level *level) +{ + intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level)); } void skl_write_plane_wm(struct intel_plane *plane, -- cgit From 09fc93141d4c6ba3f6e78ce3c995c9dedac4a37c Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:28 +0300 Subject: drm/i915: Nuke skl_write_wm_level() and skl_ddb_entry_write() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Get rid of skl_ddb_entry_write() and skl_write_wm_level() and just call intel_de_write_fw() directly. This is prep work towards DSB based plane updates where these wrappers are more of a hinderance. Done with cocci mostly: @@ expression D, R, L; @@ - skl_write_wm_level(D, R, L) + intel_de_write_fw(D, R, skl_plane_wm_reg_val(L)) @@ expression D, R, B; @@ - skl_ddb_entry_write(D, R, B) + intel_de_write_fw(D, R, skl_plane_ddb_reg_val(B)) Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-16-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/skl_watermark.c | 57 +++++++++++----------------- 1 file changed, 22 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 8a0a26ab8e6a..1daceb8ef9de 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2374,13 +2374,6 @@ static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry) PLANE_BUF_START(entry->start); } -static void skl_ddb_entry_write(struct drm_i915_private *i915, - i915_reg_t reg, - const struct skl_ddb_entry *entry) -{ - intel_de_write_fw(i915, reg, skl_plane_ddb_reg_val(entry)); -} - static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) { u32 val = 0; @@ -2395,13 +2388,6 @@ static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) return val; } -static void skl_write_wm_level(struct drm_i915_private *i915, - i915_reg_t reg, - const struct skl_wm_level *level) -{ - intel_de_write_fw(i915, reg, skl_plane_wm_reg_val(level)); -} - void skl_write_plane_wm(struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { @@ -2416,27 +2402,27 @@ void skl_write_plane_wm(struct intel_plane *plane, int level; for (level = 0; level < i915->display.wm.num_levels; level++) - skl_write_wm_level(i915, PLANE_WM(pipe, plane_id, level), - skl_plane_wm_level(pipe_wm, plane_id, level)); + intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level), + skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); - skl_write_wm_level(i915, PLANE_WM_TRANS(pipe, plane_id), - skl_plane_trans_wm(pipe_wm, plane_id)); + intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id), + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); if (HAS_HW_SAGV_WM(i915)) { const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; - skl_write_wm_level(i915, PLANE_WM_SAGV(pipe, plane_id), - &wm->sagv.wm0); - skl_write_wm_level(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id), - &wm->sagv.trans_wm); + intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id), + skl_plane_wm_reg_val(&wm->sagv.wm0)); + intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id), + skl_plane_wm_reg_val(&wm->sagv.trans_wm)); } - skl_ddb_entry_write(i915, - PLANE_BUF_CFG(pipe, plane_id), ddb); + intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id), + skl_plane_ddb_reg_val(ddb)); if (DISPLAY_VER(i915) < 11) - skl_ddb_entry_write(i915, - PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_y); + intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id), + skl_plane_ddb_reg_val(ddb_y)); } void skl_write_cursor_wm(struct intel_plane *plane, @@ -2451,22 +2437,23 @@ void skl_write_cursor_wm(struct intel_plane *plane, int level; for (level = 0; level < i915->display.wm.num_levels; level++) - skl_write_wm_level(i915, CUR_WM(pipe, level), - skl_plane_wm_level(pipe_wm, plane_id, level)); + intel_de_write_fw(i915, CUR_WM(pipe, level), + skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); - skl_write_wm_level(i915, CUR_WM_TRANS(pipe), - skl_plane_trans_wm(pipe_wm, plane_id)); + intel_de_write_fw(i915, CUR_WM_TRANS(pipe), + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); if (HAS_HW_SAGV_WM(i915)) { const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; - skl_write_wm_level(i915, CUR_WM_SAGV(pipe), - &wm->sagv.wm0); - skl_write_wm_level(i915, CUR_WM_SAGV_TRANS(pipe), - &wm->sagv.trans_wm); + intel_de_write_fw(i915, CUR_WM_SAGV(pipe), + skl_plane_wm_reg_val(&wm->sagv.wm0)); + intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe), + skl_plane_wm_reg_val(&wm->sagv.trans_wm)); } - skl_ddb_entry_write(i915, CUR_BUF_CFG(pipe), ddb); + intel_de_write_fw(i915, CUR_BUF_CFG(pipe), + skl_plane_ddb_reg_val(ddb)); } static bool skl_wm_level_equals(const struct skl_wm_level *l1, -- cgit From 19be15dcc0f6bcb4be9109faf2d50771fc9a80e1 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 10 May 2024 18:23:29 +0300 Subject: drm/i915: Handle SKL+ WM/DDB registers next to all other plane registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having the plane WM/DDB regitster write functions in skl_watermarks.c is rather annoying when trying to implement DSB based plane updates. Move them into the respective files that handle all other plane register writes. Less places where I need to worry about the DSB vs. MMIO decisions. The downside is that we spread the wm struct details a bit further afield. But if that becomes too annoying we can probably abstract things a bit more with a few extra functions. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240510152329.24098-17-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 32 ++++++++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 60 ++++++++++++++ drivers/gpu/drm/i915/display/skl_universal_plane.h | 5 ++ drivers/gpu/drm/i915/display/skl_watermark.c | 95 +--------------------- drivers/gpu/drm/i915/display/skl_watermark.h | 13 +-- 5 files changed, 107 insertions(+), 98 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index d2b459634732..3ecab15d1431 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -24,6 +24,7 @@ #include "intel_psr.h" #include "intel_psr_regs.h" #include "intel_vblank.h" +#include "skl_universal_plane.h" #include "skl_watermark.h" #include "gem/i915_gem_object.h" @@ -556,6 +557,37 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane, } } +static void skl_write_cursor_wm(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + enum plane_id plane_id = plane->id; + enum pipe pipe = plane->pipe; + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; + const struct skl_ddb_entry *ddb = + &crtc_state->wm.skl.plane_ddb[plane_id]; + int level; + + for (level = 0; level < i915->display.wm.num_levels; level++) + intel_de_write_fw(i915, CUR_WM(pipe, level), + skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); + + intel_de_write_fw(i915, CUR_WM_TRANS(pipe), + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); + + if (HAS_HW_SAGV_WM(i915)) { + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; + + intel_de_write_fw(i915, CUR_WM_SAGV(pipe), + skl_plane_wm_reg_val(&wm->sagv.wm0)); + intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe), + skl_plane_wm_reg_val(&wm->sagv.trans_wm)); + } + + intel_de_write_fw(i915, CUR_BUF_CFG(pipe), + skl_plane_ddb_reg_val(ddb)); +} + /* TODO: split into noarm+arm pair */ static void i9xx_cursor_update_arm(struct intel_plane *plane, const struct intel_crtc_state *crtc_state, diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index d7b7476dc699..32d10e62b2b9 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -622,6 +622,66 @@ static u32 skl_plane_stride(const struct intel_plane_state *plane_state, return stride / skl_plane_stride_mult(fb, color_plane, rotation); } +u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry) +{ + if (!entry->end) + return 0; + + return PLANE_BUF_END(entry->end - 1) | + PLANE_BUF_START(entry->start); +} + +u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) +{ + u32 val = 0; + + if (level->enable) + val |= PLANE_WM_EN; + if (level->ignore_lines) + val |= PLANE_WM_IGNORE_LINES; + val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); + val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); + + return val; +} + +static void skl_write_plane_wm(struct intel_plane *plane, + const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(plane->base.dev); + enum plane_id plane_id = plane->id; + enum pipe pipe = plane->pipe; + const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; + const struct skl_ddb_entry *ddb = + &crtc_state->wm.skl.plane_ddb[plane_id]; + const struct skl_ddb_entry *ddb_y = + &crtc_state->wm.skl.plane_ddb_y[plane_id]; + int level; + + for (level = 0; level < i915->display.wm.num_levels; level++) + intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level), + skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); + + intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id), + skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); + + if (HAS_HW_SAGV_WM(i915)) { + const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; + + intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id), + skl_plane_wm_reg_val(&wm->sagv.wm0)); + intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id), + skl_plane_wm_reg_val(&wm->sagv.trans_wm)); + } + + intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id), + skl_plane_ddb_reg_val(ddb)); + + if (DISPLAY_VER(i915) < 11) + intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id), + skl_plane_ddb_reg_val(ddb_y)); +} + static void skl_plane_disable_arm(struct intel_plane *plane, const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h index e92e00c01b29..8eb4521ee851 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h @@ -12,6 +12,8 @@ struct drm_i915_private; struct intel_crtc; struct intel_initial_plane_config; struct intel_plane_state; +struct skl_ddb_entry; +struct skl_wm_level; enum pipe; enum plane_id; @@ -35,4 +37,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, u8 icl_hdr_plane_mask(void); bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id); +u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry); +u32 skl_plane_wm_reg_val(const struct skl_wm_level *level); + #endif diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 1daceb8ef9de..2064f72da675 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -1396,7 +1396,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state) return data_rate; } -static const struct skl_wm_level * +const struct skl_wm_level * skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, enum plane_id plane_id, int level) @@ -1409,7 +1409,7 @@ skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, return &wm->wm[level]; } -static const struct skl_wm_level * +const struct skl_wm_level * skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, enum plane_id plane_id) { @@ -2365,97 +2365,6 @@ static int skl_build_pipe_wm(struct intel_atomic_state *state, return skl_wm_check_vblank(crtc_state); } -static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry) -{ - if (!entry->end) - return 0; - - return PLANE_BUF_END(entry->end - 1) | - PLANE_BUF_START(entry->start); -} - -static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) -{ - u32 val = 0; - - if (level->enable) - val |= PLANE_WM_EN; - if (level->ignore_lines) - val |= PLANE_WM_IGNORE_LINES; - val |= REG_FIELD_PREP(PLANE_WM_BLOCKS_MASK, level->blocks); - val |= REG_FIELD_PREP(PLANE_WM_LINES_MASK, level->lines); - - return val; -} - -void skl_write_plane_wm(struct intel_plane *plane, - const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *i915 = to_i915(plane->base.dev); - enum plane_id plane_id = plane->id; - enum pipe pipe = plane->pipe; - const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; - const struct skl_ddb_entry *ddb = - &crtc_state->wm.skl.plane_ddb[plane_id]; - const struct skl_ddb_entry *ddb_y = - &crtc_state->wm.skl.plane_ddb_y[plane_id]; - int level; - - for (level = 0; level < i915->display.wm.num_levels; level++) - intel_de_write_fw(i915, PLANE_WM(pipe, plane_id, level), - skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); - - intel_de_write_fw(i915, PLANE_WM_TRANS(pipe, plane_id), - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); - - if (HAS_HW_SAGV_WM(i915)) { - const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; - - intel_de_write_fw(i915, PLANE_WM_SAGV(pipe, plane_id), - skl_plane_wm_reg_val(&wm->sagv.wm0)); - intel_de_write_fw(i915, PLANE_WM_SAGV_TRANS(pipe, plane_id), - skl_plane_wm_reg_val(&wm->sagv.trans_wm)); - } - - intel_de_write_fw(i915, PLANE_BUF_CFG(pipe, plane_id), - skl_plane_ddb_reg_val(ddb)); - - if (DISPLAY_VER(i915) < 11) - intel_de_write_fw(i915, PLANE_NV12_BUF_CFG(pipe, plane_id), - skl_plane_ddb_reg_val(ddb_y)); -} - -void skl_write_cursor_wm(struct intel_plane *plane, - const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *i915 = to_i915(plane->base.dev); - enum plane_id plane_id = plane->id; - enum pipe pipe = plane->pipe; - const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; - const struct skl_ddb_entry *ddb = - &crtc_state->wm.skl.plane_ddb[plane_id]; - int level; - - for (level = 0; level < i915->display.wm.num_levels; level++) - intel_de_write_fw(i915, CUR_WM(pipe, level), - skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); - - intel_de_write_fw(i915, CUR_WM_TRANS(pipe), - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); - - if (HAS_HW_SAGV_WM(i915)) { - const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; - - intel_de_write_fw(i915, CUR_WM_SAGV(pipe), - skl_plane_wm_reg_val(&wm->sagv.wm0)); - intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe), - skl_plane_wm_reg_val(&wm->sagv.trans_wm)); - } - - intel_de_write_fw(i915, CUR_BUF_CFG(pipe), - skl_plane_ddb_reg_val(ddb)); -} - static bool skl_wm_level_equals(const struct skl_wm_level *l1, const struct skl_wm_level *l2) { diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h index 91f92c0e706e..78b121941237 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.h +++ b/drivers/gpu/drm/i915/display/skl_watermark.h @@ -18,6 +18,8 @@ struct intel_bw_state; struct intel_crtc; struct intel_crtc_state; struct intel_plane; +struct skl_pipe_wm; +struct skl_wm_level; u8 intel_enabled_dbuf_slices_mask(struct drm_i915_private *i915); @@ -30,11 +32,6 @@ bool intel_has_sagv(struct drm_i915_private *i915); u32 skl_ddb_dbuf_slice_mask(struct drm_i915_private *i915, const struct skl_ddb_entry *entry); -void skl_write_plane_wm(struct intel_plane *plane, - const struct intel_crtc_state *crtc_state); -void skl_write_cursor_wm(struct intel_plane *plane, - const struct intel_crtc_state *crtc_state); - bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, const struct skl_ddb_entry *entries, int num_entries, int ignore_idx); @@ -51,6 +48,12 @@ unsigned int skl_watermark_max_latency(struct drm_i915_private *i915, int initial_wm_level); void skl_wm_init(struct drm_i915_private *i915); +const struct skl_wm_level *skl_plane_wm_level(const struct skl_pipe_wm *pipe_wm, + enum plane_id plane_id, + int level); +const struct skl_wm_level *skl_plane_trans_wm(const struct skl_pipe_wm *pipe_wm, + enum plane_id plane_id); + struct intel_dbuf_state { struct intel_global_state base; -- cgit From 432ed92bfb5576865cd1fcc4cfed8a84d731b54a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 May 2024 14:22:14 +0300 Subject: drm/i915/pciids: add INTEL_PNV_IDS(), use acronym Most other PCI ID macros use platform acronyms. Follow suit for PNV. Add INTEL_PNV_IDS() to identify all PNVs. Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Reviewed-by: Rodrigo Vivi Acked-by: Bjorn Helgaas Link: https://patchwork.freedesktop.org/patch/msgid/5f9b34a2cd388244be03263a5147776bfe64d5ac.1715340032.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- arch/x86/kernel/early-quirks.c | 3 +-- drivers/gpu/drm/i915/display/intel_display_device.c | 3 +-- drivers/gpu/drm/i915/i915_pci.c | 4 ++-- include/drm/i915_pciids.h | 8 ++++++-- 4 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 59f4aefc6bc1..f50394a00fca 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -527,8 +527,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_I945G_IDS(&gen3_early_ops), INTEL_I945GM_IDS(&gen3_early_ops), INTEL_VLV_IDS(&gen6_early_ops), - INTEL_PINEVIEW_G_IDS(&gen3_early_ops), - INTEL_PINEVIEW_M_IDS(&gen3_early_ops), + INTEL_PNV_IDS(&gen3_early_ops), INTEL_I965G_IDS(&gen3_early_ops), INTEL_G33_IDS(&gen3_early_ops), INTEL_I965GM_IDS(&gen3_early_ops), diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 56a2e17d7d9e..0e0f5a36507d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -815,8 +815,7 @@ static const struct { INTEL_I965GM_IDS(&i965gm_display), INTEL_GM45_IDS(&gm45_display), INTEL_G45_IDS(&g45_display), - INTEL_PINEVIEW_G_IDS(&pnv_display), - INTEL_PINEVIEW_M_IDS(&pnv_display), + INTEL_PNV_IDS(&pnv_display), INTEL_IRONLAKE_D_IDS(&ilk_d_display), INTEL_IRONLAKE_M_IDS(&ilk_m_display), INTEL_SNB_D_IDS(&snb_display), diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 405ca17a990b..406e675c532a 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -810,8 +810,8 @@ static const struct pci_device_id pciidlist[] = { INTEL_I965GM_IDS(&i965gm_info), INTEL_GM45_IDS(&gm45_info), INTEL_G45_IDS(&g45_info), - INTEL_PINEVIEW_G_IDS(&pnv_g_info), - INTEL_PINEVIEW_M_IDS(&pnv_m_info), + INTEL_PNV_G_IDS(&pnv_g_info), + INTEL_PNV_M_IDS(&pnv_m_info), INTEL_IRONLAKE_D_IDS(&ilk_d_info), INTEL_IRONLAKE_M_IDS(&ilk_m_info), INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 85ce33ad6e26..21942a3c823b 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -108,12 +108,16 @@ INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \ INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */ -#define INTEL_PINEVIEW_G_IDS(info) \ +#define INTEL_PNV_G_IDS(info) \ INTEL_VGA_DEVICE(0xa001, info) -#define INTEL_PINEVIEW_M_IDS(info) \ +#define INTEL_PNV_M_IDS(info) \ INTEL_VGA_DEVICE(0xa011, info) +#define INTEL_PNV_IDS(info) \ + INTEL_PNV_G_IDS(info), \ + INTEL_PNV_M_IDS(info) + #define INTEL_IRONLAKE_D_IDS(info) \ INTEL_VGA_DEVICE(0x0042, info) -- cgit From 41c0f8a36f15fab58cbbcf64f641250230725da8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 May 2024 14:22:15 +0300 Subject: drm/i915/pciids: add INTEL_ILK_IDS(), use acronym Most other PCI ID macros use platform acronyms. Follow suit for ILK. Add INTEL_ILK_IDS() to identify all ILKs. Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Reviewed-by: Rodrigo Vivi Acked-by: Bjorn Helgaas Link: https://patchwork.freedesktop.org/patch/msgid/27ada56363cfa6a5b093cb31908a4b89aa912621.1715340032.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- arch/x86/kernel/early-quirks.c | 3 +-- drivers/gpu/drm/i915/display/intel_display_device.c | 4 ++-- drivers/gpu/drm/i915/i915_pci.c | 4 ++-- include/drm/i915_pciids.h | 8 ++++++-- 4 files changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index f50394a00fca..d8419d310091 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -533,8 +533,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_I965GM_IDS(&gen3_early_ops), INTEL_GM45_IDS(&gen3_early_ops), INTEL_G45_IDS(&gen3_early_ops), - INTEL_IRONLAKE_D_IDS(&gen3_early_ops), - INTEL_IRONLAKE_M_IDS(&gen3_early_ops), + INTEL_ILK_IDS(&gen3_early_ops), INTEL_SNB_D_IDS(&gen6_early_ops), INTEL_SNB_M_IDS(&gen6_early_ops), INTEL_IVB_M_IDS(&gen6_early_ops), diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 0e0f5a36507d..052fd1c290c3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -816,8 +816,8 @@ static const struct { INTEL_GM45_IDS(&gm45_display), INTEL_G45_IDS(&g45_display), INTEL_PNV_IDS(&pnv_display), - INTEL_IRONLAKE_D_IDS(&ilk_d_display), - INTEL_IRONLAKE_M_IDS(&ilk_m_display), + INTEL_ILK_D_IDS(&ilk_d_display), + INTEL_ILK_M_IDS(&ilk_m_display), INTEL_SNB_D_IDS(&snb_display), INTEL_SNB_M_IDS(&snb_display), INTEL_IVB_M_IDS(&ivb_display), diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 406e675c532a..651b027e3701 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -812,8 +812,8 @@ static const struct pci_device_id pciidlist[] = { INTEL_G45_IDS(&g45_info), INTEL_PNV_G_IDS(&pnv_g_info), INTEL_PNV_M_IDS(&pnv_m_info), - INTEL_IRONLAKE_D_IDS(&ilk_d_info), - INTEL_IRONLAKE_M_IDS(&ilk_m_info), + INTEL_ILK_D_IDS(&ilk_d_info), + INTEL_ILK_M_IDS(&ilk_m_info), INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 21942a3c823b..05f466ca8ce2 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -118,12 +118,16 @@ INTEL_PNV_G_IDS(info), \ INTEL_PNV_M_IDS(info) -#define INTEL_IRONLAKE_D_IDS(info) \ +#define INTEL_ILK_D_IDS(info) \ INTEL_VGA_DEVICE(0x0042, info) -#define INTEL_IRONLAKE_M_IDS(info) \ +#define INTEL_ILK_M_IDS(info) \ INTEL_VGA_DEVICE(0x0046, info) +#define INTEL_ILK_IDS(info) \ + INTEL_ILK_D_IDS(info), \ + INTEL_ILK_M_IDS(info) + #define INTEL_SNB_D_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x0102, info), \ INTEL_VGA_DEVICE(0x010A, info) -- cgit From 7b43a37348b7a3f07d2d7996539eb85f89e8acac Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 May 2024 14:22:16 +0300 Subject: drm/i915/pciids: add INTEL_SNB_IDS() Add INTEL_SNB_IDS() to identify all SNBs. Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Reviewed-by: Rodrigo Vivi Acked-by: Bjorn Helgaas Link: https://patchwork.freedesktop.org/patch/msgid/ffcb2d954ad9bca78ccd39836dc0a3dc7c6c0253.1715340032.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- arch/x86/kernel/early-quirks.c | 3 +-- drivers/gpu/drm/i915/display/intel_display_device.c | 3 +-- include/drm/i915_pciids.h | 4 ++++ 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index d8419d310091..23ded9260302 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -534,8 +534,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_GM45_IDS(&gen3_early_ops), INTEL_G45_IDS(&gen3_early_ops), INTEL_ILK_IDS(&gen3_early_ops), - INTEL_SNB_D_IDS(&gen6_early_ops), - INTEL_SNB_M_IDS(&gen6_early_ops), + INTEL_SNB_IDS(&gen6_early_ops), INTEL_IVB_M_IDS(&gen6_early_ops), INTEL_IVB_D_IDS(&gen6_early_ops), INTEL_HSW_IDS(&gen6_early_ops), diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 052fd1c290c3..c40d12ca386a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -818,8 +818,7 @@ static const struct { INTEL_PNV_IDS(&pnv_display), INTEL_ILK_D_IDS(&ilk_d_display), INTEL_ILK_M_IDS(&ilk_m_display), - INTEL_SNB_D_IDS(&snb_display), - INTEL_SNB_M_IDS(&snb_display), + INTEL_SNB_IDS(&snb_display), INTEL_IVB_M_IDS(&ivb_display), INTEL_IVB_D_IDS(&ivb_display), INTEL_HSW_IDS(&hsw_display), diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 05f466ca8ce2..0d48c493dcce 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -151,6 +151,10 @@ INTEL_SNB_M_GT1_IDS(info), \ INTEL_SNB_M_GT2_IDS(info) +#define INTEL_SNB_IDS(info) \ + INTEL_SNB_D_IDS(info), \ + INTEL_SNB_M_IDS(info) + #define INTEL_IVB_M_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */ -- cgit From 5c8c22adc802b2abe6fc7933087d5a029545fdff Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 May 2024 14:22:17 +0300 Subject: drm/i915/pciids: add INTEL_IVB_IDS() Add INTEL_IVB_IDS() to identify all IVBs except IVB Q transcode. Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Reviewed-by: Rodrigo Vivi Acked-by: Bjorn Helgaas Link: https://patchwork.freedesktop.org/patch/msgid/ed89a25b2c6bce318fe59e883d18b62d9453196b.1715340032.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- arch/x86/kernel/early-quirks.c | 3 +-- drivers/gpu/drm/i915/display/intel_display_device.c | 3 +-- include/drm/i915_pciids.h | 4 ++++ 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 23ded9260302..6549507003ec 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -535,8 +535,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_G45_IDS(&gen3_early_ops), INTEL_ILK_IDS(&gen3_early_ops), INTEL_SNB_IDS(&gen6_early_ops), - INTEL_IVB_M_IDS(&gen6_early_ops), - INTEL_IVB_D_IDS(&gen6_early_ops), + INTEL_IVB_IDS(&gen6_early_ops), INTEL_HSW_IDS(&gen6_early_ops), INTEL_BDW_IDS(&gen8_early_ops), INTEL_CHV_IDS(&chv_early_ops), diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index c40d12ca386a..bb681c8ed8a0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -819,8 +819,7 @@ static const struct { INTEL_ILK_D_IDS(&ilk_d_display), INTEL_ILK_M_IDS(&ilk_m_display), INTEL_SNB_IDS(&snb_display), - INTEL_IVB_M_IDS(&ivb_display), - INTEL_IVB_D_IDS(&ivb_display), + INTEL_IVB_IDS(&ivb_display), INTEL_HSW_IDS(&hsw_display), INTEL_VLV_IDS(&vlv_display), INTEL_BDW_IDS(&bdw_display), diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 0d48c493dcce..16778d92346b 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -177,6 +177,10 @@ INTEL_IVB_D_GT1_IDS(info), \ INTEL_IVB_D_GT2_IDS(info) +#define INTEL_IVB_IDS(info) \ + INTEL_IVB_M_IDS(info), \ + INTEL_IVB_D_IDS(info) + #define INTEL_IVB_Q_IDS(info) \ INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ -- cgit From aa3d586e16242ada8e865f79249e4b6ac0c7704c Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 May 2024 14:22:18 +0300 Subject: drm/i915/pciids: don't include WHL/CML PCI IDs in CFL It's confusing for INTEL_CFL_IDS() to include all WHL and CML PCI IDs. Even if we treat them the same in a lot of places, CML is a platform of its own, and the lists of PCI IDs should not conflate them. Largely go by the idea that if a platform has a name, group its PCI IDs together. That said, AML is special, having both KBL and CFL variants. Leave that alone. v2: Also split out WHL not just CML (Rodrigo) Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Reviewed-by: Rodrigo Vivi Acked-by: Bjorn Helgaas Link: https://patchwork.freedesktop.org/patch/msgid/7cca91dc78ed2b5982f14e400f03a1704645e475.1715340032.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- arch/x86/kernel/early-quirks.c | 2 ++ .../gpu/drm/i915/display/intel_display_device.c | 2 ++ include/drm/i915_pciids.h | 30 ++++++++++++---------- 3 files changed, 21 insertions(+), 13 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 6549507003ec..2b698a3f56ef 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -543,6 +543,8 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_BXT_IDS(&gen9_early_ops), INTEL_KBL_IDS(&gen9_early_ops), INTEL_CFL_IDS(&gen9_early_ops), + INTEL_WHL_IDS(&gen9_early_ops), + INTEL_CML_IDS(&gen9_early_ops), INTEL_GLK_IDS(&gen9_early_ops), INTEL_CNL_IDS(&gen9_early_ops), INTEL_ICL_11_IDS(&gen11_early_ops), diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index bb681c8ed8a0..23909a8e2dc8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -829,6 +829,8 @@ static const struct { INTEL_GLK_IDS(&glk_display), INTEL_KBL_IDS(&skl_display), INTEL_CFL_IDS(&skl_display), + INTEL_WHL_IDS(&skl_display), + INTEL_CML_IDS(&skl_display), INTEL_ICL_11_IDS(&icl_display), INTEL_EHL_IDS(&jsl_ehl_display), INTEL_JSL_IDS(&jsl_ehl_display), diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 16778d92346b..0c5a20d59801 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -488,6 +488,12 @@ INTEL_VGA_DEVICE(0x9BCA, info), \ INTEL_VGA_DEVICE(0x9BCC, info) +#define INTEL_CML_IDS(info) \ + INTEL_CML_GT1_IDS(info), \ + INTEL_CML_GT2_IDS(info), \ + INTEL_CML_U_GT1_IDS(info), \ + INTEL_CML_U_GT2_IDS(info) + #define INTEL_KBL_IDS(info) \ INTEL_KBL_GT1_IDS(info), \ INTEL_KBL_GT2_IDS(info), \ @@ -527,6 +533,15 @@ INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */ +#define INTEL_CFL_IDS(info) \ + INTEL_CFL_S_GT1_IDS(info), \ + INTEL_CFL_S_GT2_IDS(info), \ + INTEL_CFL_H_GT1_IDS(info), \ + INTEL_CFL_H_GT2_IDS(info), \ + INTEL_CFL_U_GT2_IDS(info), \ + INTEL_CFL_U_GT3_IDS(info), \ + INTEL_AML_CFL_GT2_IDS(info) + /* WHL/CFL U GT1 */ #define INTEL_WHL_U_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x3EA1, info), \ @@ -541,21 +556,10 @@ #define INTEL_WHL_U_GT3_IDS(info) \ INTEL_VGA_DEVICE(0x3EA2, info) -#define INTEL_CFL_IDS(info) \ - INTEL_CFL_S_GT1_IDS(info), \ - INTEL_CFL_S_GT2_IDS(info), \ - INTEL_CFL_H_GT1_IDS(info), \ - INTEL_CFL_H_GT2_IDS(info), \ - INTEL_CFL_U_GT2_IDS(info), \ - INTEL_CFL_U_GT3_IDS(info), \ +#define INTEL_WHL_IDS(info) \ INTEL_WHL_U_GT1_IDS(info), \ INTEL_WHL_U_GT2_IDS(info), \ - INTEL_WHL_U_GT3_IDS(info), \ - INTEL_AML_CFL_GT2_IDS(info), \ - INTEL_CML_GT1_IDS(info), \ - INTEL_CML_GT2_IDS(info), \ - INTEL_CML_U_GT1_IDS(info), \ - INTEL_CML_U_GT2_IDS(info) + INTEL_WHL_U_GT3_IDS(info) /* CNL */ #define INTEL_CNL_PORT_F_IDS(info) \ -- cgit From bfbda472276704d7b7f065a646a67b30b7a89730 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 May 2024 14:22:19 +0300 Subject: drm/i915/pciids: remove 11 from INTEL_ICL_IDS() Most other PCI ID macros do not encode the gen in the name. Follow suit for ICL. Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Reviewed-by: Rodrigo Vivi Acked-by: Bjorn Helgaas Link: https://patchwork.freedesktop.org/patch/msgid/36973674bf333dfdd7cd32ae656754bfa150022b.1715340032.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- arch/x86/kernel/early-quirks.c | 2 +- drivers/gpu/drm/i915/display/intel_display_device.c | 2 +- drivers/gpu/drm/i915/i915_pci.c | 2 +- include/drm/i915_pciids.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 2b698a3f56ef..c150bb6f1a39 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -547,7 +547,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_CML_IDS(&gen9_early_ops), INTEL_GLK_IDS(&gen9_early_ops), INTEL_CNL_IDS(&gen9_early_ops), - INTEL_ICL_11_IDS(&gen11_early_ops), + INTEL_ICL_IDS(&gen11_early_ops), INTEL_EHL_IDS(&gen11_early_ops), INTEL_JSL_IDS(&gen11_early_ops), INTEL_TGL_12_IDS(&gen11_early_ops), diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 23909a8e2dc8..e47896002c13 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -831,7 +831,7 @@ static const struct { INTEL_CFL_IDS(&skl_display), INTEL_WHL_IDS(&skl_display), INTEL_CML_IDS(&skl_display), - INTEL_ICL_11_IDS(&icl_display), + INTEL_ICL_IDS(&icl_display), INTEL_EHL_IDS(&jsl_ehl_display), INTEL_JSL_IDS(&jsl_ehl_display), INTEL_TGL_12_IDS(&tgl_display), diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 651b027e3701..9e6d9072de35 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -857,7 +857,7 @@ static const struct pci_device_id pciidlist[] = { INTEL_CML_GT2_IDS(&cml_gt2_info), INTEL_CML_U_GT1_IDS(&cml_gt1_info), INTEL_CML_U_GT2_IDS(&cml_gt2_info), - INTEL_ICL_11_IDS(&icl_info), + INTEL_ICL_IDS(&icl_info), INTEL_EHL_IDS(&ehl_info), INTEL_JSL_IDS(&jsl_info), INTEL_TGL_12_IDS(&tgl_info), diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 0c5a20d59801..ecfd7f71e2e7 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -597,7 +597,7 @@ INTEL_VGA_DEVICE(0x8A70, info), \ INTEL_VGA_DEVICE(0x8A71, info) -#define INTEL_ICL_11_IDS(info) \ +#define INTEL_ICL_IDS(info) \ INTEL_ICL_PORT_F_IDS(info), \ INTEL_VGA_DEVICE(0x8A51, info), \ INTEL_VGA_DEVICE(0x8A5D, info) -- cgit From 7858cc0b55e3d44cb0a5a033207c78fc2d5f4df9 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 May 2024 14:22:20 +0300 Subject: drm/i915/pciids: remove 12 from INTEL_TGL_IDS() Most other PCI ID macros do not encode the gen in the name. Follow suit for TGL. Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Reviewed-by: Rodrigo Vivi Acked-by: Bjorn Helgaas Link: https://patchwork.freedesktop.org/patch/msgid/044a5c553dc4564431bbef197d5e2dd085624fc2.1715340032.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- arch/x86/kernel/early-quirks.c | 2 +- drivers/gpu/drm/i915/display/intel_display_device.c | 2 +- drivers/gpu/drm/i915/i915_pci.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 2 +- include/drm/i915_pciids.h | 10 +++++----- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index c150bb6f1a39..b2b9cc3b9545 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -550,7 +550,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_ICL_IDS(&gen11_early_ops), INTEL_EHL_IDS(&gen11_early_ops), INTEL_JSL_IDS(&gen11_early_ops), - INTEL_TGL_12_IDS(&gen11_early_ops), + INTEL_TGL_IDS(&gen11_early_ops), INTEL_RKL_IDS(&gen11_early_ops), INTEL_ADLS_IDS(&gen11_early_ops), INTEL_ADLP_IDS(&gen11_early_ops), diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index e47896002c13..fb4c4054207e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -834,7 +834,7 @@ static const struct { INTEL_ICL_IDS(&icl_display), INTEL_EHL_IDS(&jsl_ehl_display), INTEL_JSL_IDS(&jsl_ehl_display), - INTEL_TGL_12_IDS(&tgl_display), + INTEL_TGL_IDS(&tgl_display), INTEL_DG1_IDS(&dg1_display), INTEL_RKL_IDS(&rkl_display), INTEL_ADLS_IDS(&adl_s_display), diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 9e6d9072de35..fe5cb3fcfe73 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -860,7 +860,7 @@ static const struct pci_device_id pciidlist[] = { INTEL_ICL_IDS(&icl_info), INTEL_EHL_IDS(&ehl_info), INTEL_JSL_IDS(&jsl_info), - INTEL_TGL_12_IDS(&tgl_info), + INTEL_TGL_IDS(&tgl_info), INTEL_RKL_IDS(&rkl_info), INTEL_ADLS_IDS(&adl_s_info), INTEL_ADLP_IDS(&adl_p_info), diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index a0a43ea07f11..64651a54a245 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -173,7 +173,7 @@ static const u16 subplatform_portf_ids[] = { }; static const u16 subplatform_uy_ids[] = { - INTEL_TGL_12_GT2_IDS(0), + INTEL_TGL_GT2_IDS(0), }; static const u16 subplatform_n_ids[] = { diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index ecfd7f71e2e7..42913d2eb655 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -620,12 +620,12 @@ INTEL_VGA_DEVICE(0x4E71, info) /* TGL */ -#define INTEL_TGL_12_GT1_IDS(info) \ +#define INTEL_TGL_GT1_IDS(info) \ INTEL_VGA_DEVICE(0x9A60, info), \ INTEL_VGA_DEVICE(0x9A68, info), \ INTEL_VGA_DEVICE(0x9A70, info) -#define INTEL_TGL_12_GT2_IDS(info) \ +#define INTEL_TGL_GT2_IDS(info) \ INTEL_VGA_DEVICE(0x9A40, info), \ INTEL_VGA_DEVICE(0x9A49, info), \ INTEL_VGA_DEVICE(0x9A59, info), \ @@ -635,9 +635,9 @@ INTEL_VGA_DEVICE(0x9AD9, info), \ INTEL_VGA_DEVICE(0x9AF8, info) -#define INTEL_TGL_12_IDS(info) \ - INTEL_TGL_12_GT1_IDS(info), \ - INTEL_TGL_12_GT2_IDS(info) +#define INTEL_TGL_IDS(info) \ + INTEL_TGL_GT1_IDS(info), \ + INTEL_TGL_GT2_IDS(info) /* RKL */ #define INTEL_RKL_IDS(info) \ -- cgit From d2c4b1db1c4f9e59ccb2d65aa1840420a059bf46 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 10 May 2024 14:22:21 +0300 Subject: drm/i915/pciids: don't include RPL-U PCI IDs in RPL-P It's confusing for INTEL_RPLP_IDS() to include INTEL_RPLU_IDS(). Even if we treat them the same elsewhere, the lists of PCI IDs should not. Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Reviewed-by: Rodrigo Vivi Acked-by: Bjorn Helgaas Link: https://patchwork.freedesktop.org/patch/msgid/28fe0910efb93a28c400728af14beff015667f42.1715340032.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- arch/x86/kernel/early-quirks.c | 1 + drivers/gpu/drm/i915/display/intel_display_device.c | 1 + drivers/gpu/drm/i915/i915_pci.c | 1 + drivers/gpu/drm/i915/intel_device_info.c | 1 + include/drm/i915_pciids.h | 1 - 5 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index b2b9cc3b9545..fd74d7f26f01 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -556,6 +556,7 @@ static const struct pci_device_id intel_early_ids[] __initconst = { INTEL_ADLP_IDS(&gen11_early_ops), INTEL_ADLN_IDS(&gen11_early_ops), INTEL_RPLS_IDS(&gen11_early_ops), + INTEL_RPLU_IDS(&gen11_early_ops), INTEL_RPLP_IDS(&gen11_early_ops), }; diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index fb4c4054207e..89069cff06b4 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -841,6 +841,7 @@ static const struct { INTEL_RPLS_IDS(&adl_s_display), INTEL_ADLP_IDS(&xe_lpd_display), INTEL_ADLN_IDS(&xe_lpd_display), + INTEL_RPLU_IDS(&xe_lpd_display), INTEL_RPLP_IDS(&xe_lpd_display), INTEL_DG2_IDS(&xe_hpd_display), diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index fe5cb3fcfe73..0edd550d8555 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -867,6 +867,7 @@ static const struct pci_device_id pciidlist[] = { INTEL_ADLN_IDS(&adl_p_info), INTEL_DG1_IDS(&dg1_info), INTEL_RPLS_IDS(&adl_s_info), + INTEL_RPLU_IDS(&adl_p_info), INTEL_RPLP_IDS(&adl_p_info), INTEL_DG2_IDS(&dg2_info), INTEL_ATS_M_IDS(&ats_m_info), diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 64651a54a245..a39497971994 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -182,6 +182,7 @@ static const u16 subplatform_n_ids[] = { static const u16 subplatform_rpl_ids[] = { INTEL_RPLS_IDS(0), + INTEL_RPLU_IDS(0), INTEL_RPLP_IDS(0), }; diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 42913d2eb655..04f6ca3dc5c1 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -717,7 +717,6 @@ /* RPL-P */ #define INTEL_RPLP_IDS(info) \ - INTEL_RPLU_IDS(info), \ INTEL_VGA_DEVICE(0xA720, info), \ INTEL_VGA_DEVICE(0xA7A0, info), \ INTEL_VGA_DEVICE(0xA7A8, info), \ -- cgit From 93160b2d1747500b5610569b549c8d7b7e9d0f21 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 May 2024 14:56:41 +0300 Subject: drm/i915: pass dev_priv explicitly to CURCNTR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURCNTR register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/06bc681558c86f351ae596e9600133bb10ae4bdd.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 10 +++++----- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/gvt/display.c | 8 ++++---- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 6 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 3ecab15d1431..31cb614b6ba8 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -295,11 +295,11 @@ static void i845_cursor_update_arm(struct intel_plane *plane, if (plane->cursor.base != base || plane->cursor.size != size || plane->cursor.cntl != cntl) { - intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0); + intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0); intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); - intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl); + intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl); plane->cursor.base = base; plane->cursor.size = size; @@ -328,7 +328,7 @@ static bool i845_cursor_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE; + ret = intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & CURSOR_ENABLE; *pipe = PIPE_A; @@ -646,7 +646,7 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane, if (HAS_CUR_FBC(dev_priv)) intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), fbc_ctl); - intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl); + intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl); intel_de_write_fw(dev_priv, CURPOS(pipe), pos); intel_de_write_fw(dev_priv, CURBASE(pipe), base); @@ -684,7 +684,7 @@ static bool i9xx_cursor_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - val = intel_de_read(dev_priv, CURCNTR(plane->pipe)); + val = intel_de_read(dev_priv, CURCNTR(dev_priv, plane->pipe)); ret = val & MCURSOR_MODE_MASK; diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index a478ef5787c5..5f522a4ecc2e 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -66,7 +66,7 @@ #define _CURBBASE_IVB 0x71084 #define _CURBPOS_IVB 0x71088 -#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) +#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) #define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) #define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) #define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e29073b90860..cce1420fb541 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8238,9 +8238,9 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) drm_WARN_ON(&dev_priv->drm, intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK); + intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK); drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK); + intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK); intel_de_write(dev_priv, TRANSCONF(pipe), 0); intel_de_posting_read(dev_priv, TRANSCONF(pipe)); diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 527e0bb2b15e..73ea8be0f80b 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -194,8 +194,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; - vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; - vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; + vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; + vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; } for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { @@ -505,8 +505,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) for_each_pipe(dev_priv, pipe) { vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; - vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE_MASK; - vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE; + vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; + vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; } vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index ac3ec9d1ef5f..6e226ea1afa2 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -347,7 +347,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, if (pipe >= I915_MAX_PIPES) return -ENODEV; - val = vgpu_vreg_t(vgpu, CURCNTR(pipe)); + val = vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)); mode = val & MCURSOR_MODE_MASK; plane->enabled = (mode != MCURSOR_MODE_DISABLE); if (!plane->enabled) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 843bdb46d49c..18deaf416b7e 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -145,9 +145,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B)); MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C)); MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP)); - MMIO_D(CURCNTR(PIPE_A)); - MMIO_D(CURCNTR(PIPE_B)); - MMIO_D(CURCNTR(PIPE_C)); + MMIO_D(CURCNTR(dev_priv, PIPE_A)); + MMIO_D(CURCNTR(dev_priv, PIPE_B)); + MMIO_D(CURCNTR(dev_priv, PIPE_C)); MMIO_D(CURPOS(PIPE_A)); MMIO_D(CURPOS(PIPE_B)); MMIO_D(CURPOS(PIPE_C)); -- cgit From 0edd2d251b7bdbf33f45924bb3c3cace38a00c42 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 May 2024 14:56:42 +0300 Subject: drm/i915: pass dev_priv explicitly to CURBASE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURBASE register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/e552df69a4e6a3dbd562ba8c442d0219cda3bfd0.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++--- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 31cb614b6ba8..573bbdec3e3d 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -296,7 +296,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane, plane->cursor.size != size || plane->cursor.cntl != cntl) { intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0); - intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base); + intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base); intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl); @@ -648,14 +648,14 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane, fbc_ctl); intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl); intel_de_write_fw(dev_priv, CURPOS(pipe), pos); - intel_de_write_fw(dev_priv, CURBASE(pipe), base); + intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base); plane->cursor.base = base; plane->cursor.size = fbc_ctl; plane->cursor.cntl = cntl; } else { intel_de_write_fw(dev_priv, CURPOS(pipe), pos); - intel_de_write_fw(dev_priv, CURBASE(pipe), base); + intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base); } } diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 5f522a4ecc2e..4a7e27f0c3c1 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -67,7 +67,7 @@ #define _CURBPOS_IVB 0x71088 #define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) -#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) +#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) #define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) #define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) #define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 6e226ea1afa2..60f368affb6c 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -373,7 +373,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n", alpha_plane, alpha_force); - plane->base = vgpu_vreg_t(vgpu, CURBASE(pipe)) & I915_GTT_PAGE_MASK; + plane->base = vgpu_vreg_t(vgpu, CURBASE(dev_priv, pipe)) & I915_GTT_PAGE_MASK; if (!vgpu_gmadr_is_valid(vgpu, plane->base)) return -EINVAL; diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 18deaf416b7e..f562172995a6 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -151,9 +151,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(CURPOS(PIPE_A)); MMIO_D(CURPOS(PIPE_B)); MMIO_D(CURPOS(PIPE_C)); - MMIO_D(CURBASE(PIPE_A)); - MMIO_D(CURBASE(PIPE_B)); - MMIO_D(CURBASE(PIPE_C)); + MMIO_D(CURBASE(dev_priv, PIPE_A)); + MMIO_D(CURBASE(dev_priv, PIPE_B)); + MMIO_D(CURBASE(dev_priv, PIPE_C)); MMIO_D(CUR_FBC_CTL(PIPE_A)); MMIO_D(CUR_FBC_CTL(PIPE_B)); MMIO_D(CUR_FBC_CTL(PIPE_C)); -- cgit From 99ab1a29dafe1a091ed57e82b74581b4bbad0c96 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 May 2024 14:56:43 +0300 Subject: drm/i915: pass dev_priv explicitly to CURPOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURPOS register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/ca229a123cb8a5d6a2970649a47236b3da1b02ad.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 573bbdec3e3d..17039d37dc91 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -298,14 +298,14 @@ static void i845_cursor_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0); intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base); intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); - intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); + intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl); plane->cursor.base = base; plane->cursor.size = size; plane->cursor.cntl = cntl; } else { - intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos); + intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); } } @@ -647,14 +647,14 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), fbc_ctl); intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl); - intel_de_write_fw(dev_priv, CURPOS(pipe), pos); + intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos); intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base); plane->cursor.base = base; plane->cursor.size = fbc_ctl; plane->cursor.cntl = cntl; } else { - intel_de_write_fw(dev_priv, CURPOS(pipe), pos); + intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos); intel_de_write_fw(dev_priv, CURBASE(dev_priv, pipe), base); } } diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 4a7e27f0c3c1..d0fa251ae8c4 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -68,7 +68,7 @@ #define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) #define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) -#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) +#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) #define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) #define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 60f368affb6c..e78de423a6c7 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -384,7 +384,7 @@ int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu, return -EINVAL; } - val = vgpu_vreg_t(vgpu, CURPOS(pipe)); + val = vgpu_vreg_t(vgpu, CURPOS(dev_priv, pipe)); plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT; plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT; plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT; diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index f562172995a6..5ea1fbc2e981 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -148,9 +148,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(CURCNTR(dev_priv, PIPE_A)); MMIO_D(CURCNTR(dev_priv, PIPE_B)); MMIO_D(CURCNTR(dev_priv, PIPE_C)); - MMIO_D(CURPOS(PIPE_A)); - MMIO_D(CURPOS(PIPE_B)); - MMIO_D(CURPOS(PIPE_C)); + MMIO_D(CURPOS(dev_priv, PIPE_A)); + MMIO_D(CURPOS(dev_priv, PIPE_B)); + MMIO_D(CURPOS(dev_priv, PIPE_C)); MMIO_D(CURBASE(dev_priv, PIPE_A)); MMIO_D(CURBASE(dev_priv, PIPE_B)); MMIO_D(CURBASE(dev_priv, PIPE_C)); -- cgit From 224689e14a2223320aeeabea273fe5207b2e196a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 May 2024 14:56:44 +0300 Subject: drm/i915: pass dev_priv explicitly to CURPOS_ERLY_TPT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURPOS_ERLY_TPT register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/2263b6412e983026990f7f6730b0b1141be4fd0f.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 4 +++- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 17039d37dc91..f8baf25c4a4f 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -543,7 +543,9 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane, if (crtc_state->enable_psr2_su_region_et) { u32 val = intel_cursor_position(crtc_state, plane_state, true); - intel_de_write_fw(dev_priv, CURPOS_ERLY_TPT(pipe), val); + intel_de_write_fw(dev_priv, + CURPOS_ERLY_TPT(dev_priv, pipe), + val); } intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index d0fa251ae8c4..0d1ee13ec066 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -69,7 +69,7 @@ #define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) #define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) #define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) -#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) +#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) #define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) -- cgit From 2f757b4c401fbeffcd6d92e4a8b4b9b25f0070c7 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 May 2024 14:56:45 +0300 Subject: drm/i915: pass dev_priv explicitly to CURSIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURSIZE register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/521ca44416eb95dcfcf4bfbc32ac7f9371aeaf5d.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index f8baf25c4a4f..8553f6164760 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -297,7 +297,7 @@ static void i845_cursor_update_arm(struct intel_plane *plane, plane->cursor.cntl != cntl) { intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), 0); intel_de_write_fw(dev_priv, CURBASE(dev_priv, PIPE_A), base); - intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size); + intel_de_write_fw(dev_priv, CURSIZE(dev_priv, PIPE_A), size); intel_de_write_fw(dev_priv, CURPOS(dev_priv, PIPE_A), pos); intel_de_write_fw(dev_priv, CURCNTR(dev_priv, PIPE_A), cntl); diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 0d1ee13ec066..7c3a76f5151d 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -70,7 +70,7 @@ #define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) #define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) #define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) -#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) +#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) #define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) -- cgit From 3de9076e9f823ec8418c053c734d6e0fff30a635 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 May 2024 14:56:46 +0300 Subject: drm/i915: pass dev_priv explicitly to CUR_FBC_CTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CUR_FBC_CTL register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/f5e76f916ccf02aaf6016ffd476e9544817ac179.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 3 ++- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 8553f6164760..c780ce146131 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -646,7 +646,8 @@ static void i9xx_cursor_update_arm(struct intel_plane *plane, plane->cursor.size != fbc_ctl || plane->cursor.cntl != cntl) { if (HAS_CUR_FBC(dev_priv)) - intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe), + intel_de_write_fw(dev_priv, + CUR_FBC_CTL(dev_priv, pipe), fbc_ctl); intel_de_write_fw(dev_priv, CURCNTR(dev_priv, pipe), cntl); intel_de_write_fw(dev_priv, CURPOS(dev_priv, pipe), pos); diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 7c3a76f5151d..40b01205e247 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -71,7 +71,7 @@ #define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) #define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) #define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) -#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) +#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) #define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 5ea1fbc2e981..b485976976db 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -154,9 +154,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(CURBASE(dev_priv, PIPE_A)); MMIO_D(CURBASE(dev_priv, PIPE_B)); MMIO_D(CURBASE(dev_priv, PIPE_C)); - MMIO_D(CUR_FBC_CTL(PIPE_A)); - MMIO_D(CUR_FBC_CTL(PIPE_B)); - MMIO_D(CUR_FBC_CTL(PIPE_C)); + MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_A)); + MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_B)); + MMIO_D(CUR_FBC_CTL(dev_priv, PIPE_C)); MMIO_D(_MMIO(0x700ac)); MMIO_D(_MMIO(0x710ac)); MMIO_D(_MMIO(0x720ac)); -- cgit From 79a0bcadb4ca1bd9af126faecf22999bef859b2d Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 May 2024 14:56:47 +0300 Subject: drm/i915: pass dev_priv explicitly to CUR_CHICKEN MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CUR_CHICKEN register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/0bd1fa8ab346ba2bb40f435136b975b472ad2bc8.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 40b01205e247..3e948526e9ab 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -72,7 +72,7 @@ #define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) #define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) #define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) -#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) +#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) #define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) /* skl+ */ -- cgit From 11abdbc22b1ad8fd0d41ca0742c79a153b2ade97 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 May 2024 14:56:48 +0300 Subject: drm/i915: pass dev_priv explicitly to CURSURFLIVE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CURSURFLIVE register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/86aa98ad9f883681f5c2e3aba839d02d8591bfbf.1715774156.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 13 +++++++++---- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 3e948526e9ab..c2190af1e9f5 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -73,7 +73,7 @@ #define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) #define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) #define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) -#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) +#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) /* skl+ */ #define _CUR_WM_A_0 0x70140 diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 98dfd537070c..df0d14a5023f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2352,7 +2352,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp) * but testing proved that it works for up display 13, for newer * than that testing will be needed. */ - intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); + intel_de_write(dev_priv, CURSURFLIVE(dev_priv, intel_dp->psr.pipe), 0); } void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state) @@ -3100,7 +3100,9 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp) if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { /* Send one update otherwise lag is observed in screen */ - intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); + intel_de_write(dev_priv, + CURSURFLIVE(dev_priv, intel_dp->psr.pipe), + 0); return; } @@ -3110,7 +3112,8 @@ static void _psr_invalidate_handle(struct intel_dp *intel_dp) intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), val); - intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); + intel_de_write(dev_priv, + CURSURFLIVE(dev_priv, intel_dp->psr.pipe), 0); intel_dp->psr.psr2_sel_fetch_cff_enabled = true; } else { intel_psr_exit(intel_dp); @@ -3210,7 +3213,9 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), val); - intel_de_write(dev_priv, CURSURFLIVE(intel_dp->psr.pipe), 0); + intel_de_write(dev_priv, + CURSURFLIVE(dev_priv, intel_dp->psr.pipe), + 0); intel_dp->psr.psr2_sel_fetch_cff_enabled = false; } } else { -- cgit From 007ed70831426d4cc108d879d688de6b8e3e6d45 Mon Sep 17 00:00:00 2001 From: Nirmoy Das Date: Thu, 16 May 2024 17:14:03 +0200 Subject: drm/i915/selftests: Set always_coherent to false when reading from CPU Commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick correct caching mode.") was not complete as for non LLC sharing platforms cpu read can happen from LLC which probably doesn't have the latest changes made by GPU. Cc: Andi Shyti Cc: Janusz Krzysztofik Cc: Jonathan Cavitt Fixes: 8d4ba9fc1c6c ("drm/i915/selftests: Pick correct caching mode.") Reviewed-by: Jonathan Cavitt Reviewed-by: Andi Shyti Link: https://patchwork.freedesktop.org/patch/msgid/20240516151403.2875-1-nirmoy.das@intel.com Signed-off-by: Nirmoy Das --- drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c index 65a931ea80e9..3527b8f446fe 100644 --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c @@ -196,7 +196,7 @@ static int verify_access(struct drm_i915_private *i915, if (err) goto out_file; - mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true); + mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, false); vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode); if (IS_ERR(vaddr)) { err = PTR_ERR(vaddr); -- cgit From 45430e7b7c8de9ed910d99cc8906db3db5a1334d Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 17 May 2024 10:30:03 +0300 Subject: drm/i915/psr: LunarLake IO and Fast Wake time line count maximums are 68 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On LunarLake maximum for IO and Fast Wake time line counts are 68: 6 bits + 5 lines added by the HW. Take this into account in calculation and when writing the IO Wake lines. v2: maximum line count is 68 (6 bits + 5 lines added by HW) Signed-off-by: Jouni Högander Reviewed-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-2-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index df0d14a5023f..f5d3eb776833 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1421,8 +1421,9 @@ static bool _compute_alpm_params(struct intel_dp *intel_dp, fast_wake_time = precharge + preamble + phy_wake + tfw_exit_latency; - if (DISPLAY_VER(i915) >= 12) - /* TODO: Check how we can use ALPM_CTL fast wake extended field */ + if (DISPLAY_VER(i915) >= 20) + max_wake_lines = 68; + else if (DISPLAY_VER(i915) >= 12) max_wake_lines = 12; else max_wake_lines = 8; -- cgit From 30dee753ca0a1b565da5eec8d0686315f595d171 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 17 May 2024 10:30:04 +0300 Subject: drm/i915/psr: LunarLake PSR2_CTL[IO Wake Lines] is 6 bits wide MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On LunarLake PSR2_CTL[IO Wake Lines] contains now bit 13:18. Take this into account when enabling PSR2_CTL. Bspec: 69885 Signed-off-by: Jouni Högander Reviewed-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-3-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 2 ++ drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f5d3eb776833..d2f6488b8fc7 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -958,6 +958,8 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) tmp = map[psr->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); + } else if (DISPLAY_VER(dev_priv) >= 20) { + val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines); } else if (DISPLAY_VER(dev_priv) >= 12) { val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines); val |= TGL_EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines); diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index e14cb48f2614..b6a39926ccb6 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -172,6 +172,10 @@ #define TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 #define TGL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(TGL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \ (lines) - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) +#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK REG_GENMASK(18, 13) +#define LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES 5 +#define LNL_EDP_PSR2_IO_BUFFER_WAKE(lines) REG_FIELD_PREP(LNL_EDP_PSR2_IO_BUFFER_WAKE_MASK, \ + (lines) - LNL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES) #define EDP_PSR2_FAST_WAKE_MASK REG_GENMASK(12, 11) #define EDP_PSR2_FAST_WAKE_MAX_LINES 8 #define EDP_PSR2_FAST_WAKE(lines) REG_FIELD_PREP(EDP_PSR2_FAST_WAKE_MASK, \ -- cgit From d370a9dba5c4a9bc1b6bc0643037700a03fceae1 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 17 May 2024 10:30:05 +0300 Subject: drm/i915/psr: PSR2_CTL[Block Count Number] not needed for LunarLake MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PSR2_CTL[Block Count Number] is not used by LunarLake do not configure it. Bspec: 69885 Signed-off-by: Jouni Högander Reviewed-by: Uma Shankar Link: https://patchwork.freedesktop.org/patch/msgid/20240517073005.2414293-4-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d2f6488b8fc7..d18baeb971bb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -927,7 +927,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) val |= intel_psr2_get_tp_time(intel_dp); - if (DISPLAY_VER(dev_priv) >= 12) { + if (DISPLAY_VER(dev_priv) >= 12 && DISPLAY_VER(dev_priv) < 20) { if (psr2_block_count(intel_dp) > 2) val |= TGL_EDP_PSR2_BLOCK_COUNT_NUM_3; else -- cgit From a568ff8cd0feb9202d8bd7d572b170931b57248c Mon Sep 17 00:00:00 2001 From: Ryszard Knop Date: Wed, 24 Apr 2024 13:41:59 +0200 Subject: MAINTAINERS: Move the drm-intel repo location to fd.o GitLab The drm-intel repo is moving from the classic fd.o git host to GitLab. Update its location with a URL matching other fd.o GitLab kernel trees. Signed-off-by: Ryszard Knop Acked-by: Jani Nikula Acked-by: Tvrtko Ursulin Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20240424114159.38719-1-ryszard.knop@intel.com Signed-off-by: Lucas De Marchi --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index abd4dbe2c653..841de2af93f0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10853,7 +10853,7 @@ W: https://drm.pages.freedesktop.org/intel-docs/ Q: http://patchwork.freedesktop.org/project/intel-gfx/ B: https://drm.pages.freedesktop.org/intel-docs/how-to-file-i915-bugs.html C: irc://irc.oftc.net/intel-gfx -T: git git://anongit.freedesktop.org/drm-intel +T: git https://gitlab.freedesktop.org/drm/i915/kernel.git F: Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon F: Documentation/gpu/i915.rst F: drivers/gpu/drm/ci/xfails/i915* -- cgit From cfa7772880f845f5d6dbee69c441c6efbffa425b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 May 2024 19:56:50 +0300 Subject: drm/i915/pciids: switch to xe driver style PCI ID macros The PCI ID macros in xe_pciids.h allow passing in the macro to operate on each PCI ID, making it more flexible. Convert i915_pciids.h to the same pattern. INTEL_IVB_Q_IDS() for Quanta transcode remains a special case, and unconditionally uses INTEL_QUANTA_VGA_DEVICE(). Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Cc: Lucas De Marchi Cc: Rodrigo Vivi Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20240515165651.1230465-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- arch/x86/kernel/early-quirks.c | 80 +- .../gpu/drm/i915/display/intel_display_device.c | 86 +- drivers/gpu/drm/i915/i915_pci.c | 150 +-- drivers/gpu/drm/i915/intel_device_info.c | 88 +- include/drm/i915_pciids.h | 1348 ++++++++++---------- 5 files changed, 876 insertions(+), 876 deletions(-) diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index fd74d7f26f01..1c137771c5d2 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -518,46 +518,46 @@ static const struct intel_early_ops gen11_early_ops __initconst = { /* Intel integrated GPUs for which we need to reserve "stolen memory" */ static const struct pci_device_id intel_early_ids[] __initconst = { - INTEL_I830_IDS(&i830_early_ops), - INTEL_I845G_IDS(&i845_early_ops), - INTEL_I85X_IDS(&i85x_early_ops), - INTEL_I865G_IDS(&i865_early_ops), - INTEL_I915G_IDS(&gen3_early_ops), - INTEL_I915GM_IDS(&gen3_early_ops), - INTEL_I945G_IDS(&gen3_early_ops), - INTEL_I945GM_IDS(&gen3_early_ops), - INTEL_VLV_IDS(&gen6_early_ops), - INTEL_PNV_IDS(&gen3_early_ops), - INTEL_I965G_IDS(&gen3_early_ops), - INTEL_G33_IDS(&gen3_early_ops), - INTEL_I965GM_IDS(&gen3_early_ops), - INTEL_GM45_IDS(&gen3_early_ops), - INTEL_G45_IDS(&gen3_early_ops), - INTEL_ILK_IDS(&gen3_early_ops), - INTEL_SNB_IDS(&gen6_early_ops), - INTEL_IVB_IDS(&gen6_early_ops), - INTEL_HSW_IDS(&gen6_early_ops), - INTEL_BDW_IDS(&gen8_early_ops), - INTEL_CHV_IDS(&chv_early_ops), - INTEL_SKL_IDS(&gen9_early_ops), - INTEL_BXT_IDS(&gen9_early_ops), - INTEL_KBL_IDS(&gen9_early_ops), - INTEL_CFL_IDS(&gen9_early_ops), - INTEL_WHL_IDS(&gen9_early_ops), - INTEL_CML_IDS(&gen9_early_ops), - INTEL_GLK_IDS(&gen9_early_ops), - INTEL_CNL_IDS(&gen9_early_ops), - INTEL_ICL_IDS(&gen11_early_ops), - INTEL_EHL_IDS(&gen11_early_ops), - INTEL_JSL_IDS(&gen11_early_ops), - INTEL_TGL_IDS(&gen11_early_ops), - INTEL_RKL_IDS(&gen11_early_ops), - INTEL_ADLS_IDS(&gen11_early_ops), - INTEL_ADLP_IDS(&gen11_early_ops), - INTEL_ADLN_IDS(&gen11_early_ops), - INTEL_RPLS_IDS(&gen11_early_ops), - INTEL_RPLU_IDS(&gen11_early_ops), - INTEL_RPLP_IDS(&gen11_early_ops), + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_early_ops), + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_early_ops), + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_early_ops), + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865_early_ops), + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &gen6_early_ops), + INTEL_PNV_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_G33_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_G45_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_ILK_IDS(INTEL_VGA_DEVICE, &gen3_early_ops), + INTEL_SNB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops), + INTEL_IVB_IDS(INTEL_VGA_DEVICE, &gen6_early_ops), + INTEL_HSW_IDS(INTEL_VGA_DEVICE, &gen6_early_ops), + INTEL_BDW_IDS(INTEL_VGA_DEVICE, &gen8_early_ops), + INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_early_ops), + INTEL_SKL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), + INTEL_BXT_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), + INTEL_KBL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), + INTEL_CFL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), + INTEL_WHL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), + INTEL_CML_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), + INTEL_GLK_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), + INTEL_CNL_IDS(INTEL_VGA_DEVICE, &gen9_early_ops), + INTEL_ICL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), + INTEL_EHL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), + INTEL_JSL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), + INTEL_TGL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), + INTEL_RKL_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), + INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), + INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &gen11_early_ops), }; struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0); diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 89069cff06b4..950e66cdba0a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -788,7 +788,7 @@ __diag_pop(); static bool has_no_display(struct pci_dev *pdev) { static const struct pci_device_id ids[] = { - INTEL_IVB_Q_IDS(0), + INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, 0), {} }; @@ -802,48 +802,48 @@ static const struct { u32 devid; const struct intel_display_device_info *info; } intel_display_ids[] = { - INTEL_I830_IDS(&i830_display), - INTEL_I845G_IDS(&i845_display), - INTEL_I85X_IDS(&i85x_display), - INTEL_I865G_IDS(&i865g_display), - INTEL_I915G_IDS(&i915g_display), - INTEL_I915GM_IDS(&i915gm_display), - INTEL_I945G_IDS(&i945g_display), - INTEL_I945GM_IDS(&i945gm_display), - INTEL_I965G_IDS(&i965g_display), - INTEL_G33_IDS(&g33_display), - INTEL_I965GM_IDS(&i965gm_display), - INTEL_GM45_IDS(&gm45_display), - INTEL_G45_IDS(&g45_display), - INTEL_PNV_IDS(&pnv_display), - INTEL_ILK_D_IDS(&ilk_d_display), - INTEL_ILK_M_IDS(&ilk_m_display), - INTEL_SNB_IDS(&snb_display), - INTEL_IVB_IDS(&ivb_display), - INTEL_HSW_IDS(&hsw_display), - INTEL_VLV_IDS(&vlv_display), - INTEL_BDW_IDS(&bdw_display), - INTEL_CHV_IDS(&chv_display), - INTEL_SKL_IDS(&skl_display), - INTEL_BXT_IDS(&bxt_display), - INTEL_GLK_IDS(&glk_display), - INTEL_KBL_IDS(&skl_display), - INTEL_CFL_IDS(&skl_display), - INTEL_WHL_IDS(&skl_display), - INTEL_CML_IDS(&skl_display), - INTEL_ICL_IDS(&icl_display), - INTEL_EHL_IDS(&jsl_ehl_display), - INTEL_JSL_IDS(&jsl_ehl_display), - INTEL_TGL_IDS(&tgl_display), - INTEL_DG1_IDS(&dg1_display), - INTEL_RKL_IDS(&rkl_display), - INTEL_ADLS_IDS(&adl_s_display), - INTEL_RPLS_IDS(&adl_s_display), - INTEL_ADLP_IDS(&xe_lpd_display), - INTEL_ADLN_IDS(&xe_lpd_display), - INTEL_RPLU_IDS(&xe_lpd_display), - INTEL_RPLP_IDS(&xe_lpd_display), - INTEL_DG2_IDS(&xe_hpd_display), + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_display), + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_display), + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_display), + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_display), + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_display), + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_display), + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_display), + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_display), + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_display), + INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_display), + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_display), + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_display), + INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_display), + INTEL_PNV_IDS(INTEL_VGA_DEVICE, &pnv_display), + INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_display), + INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_display), + INTEL_SNB_IDS(INTEL_VGA_DEVICE, &snb_display), + INTEL_IVB_IDS(INTEL_VGA_DEVICE, &ivb_display), + INTEL_HSW_IDS(INTEL_VGA_DEVICE, &hsw_display), + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_display), + INTEL_BDW_IDS(INTEL_VGA_DEVICE, &bdw_display), + INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_display), + INTEL_SKL_IDS(INTEL_VGA_DEVICE, &skl_display), + INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_display), + INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_display), + INTEL_KBL_IDS(INTEL_VGA_DEVICE, &skl_display), + INTEL_CFL_IDS(INTEL_VGA_DEVICE, &skl_display), + INTEL_WHL_IDS(INTEL_VGA_DEVICE, &skl_display), + INTEL_CML_IDS(INTEL_VGA_DEVICE, &skl_display), + INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_display), + INTEL_EHL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display), + INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display), + INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_display), + INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_display), + INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_display), + INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_display), + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_display), + INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display), + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &xe_lpd_display), + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &xe_lpd_display), + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display), + INTEL_DG2_IDS(INTEL_VGA_DEVICE, &xe_hpd_display), /* * Do not add any GMD_ID-based platforms to this list. They will diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 0edd550d8555..2e33b56e1cc6 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -797,81 +797,81 @@ __diag_pop(); * PCI ID matches, otherwise we'll use the wrong info struct above. */ static const struct pci_device_id pciidlist[] = { - INTEL_I830_IDS(&i830_info), - INTEL_I845G_IDS(&i845g_info), - INTEL_I85X_IDS(&i85x_info), - INTEL_I865G_IDS(&i865g_info), - INTEL_I915G_IDS(&i915g_info), - INTEL_I915GM_IDS(&i915gm_info), - INTEL_I945G_IDS(&i945g_info), - INTEL_I945GM_IDS(&i945gm_info), - INTEL_I965G_IDS(&i965g_info), - INTEL_G33_IDS(&g33_info), - INTEL_I965GM_IDS(&i965gm_info), - INTEL_GM45_IDS(&gm45_info), - INTEL_G45_IDS(&g45_info), - INTEL_PNV_G_IDS(&pnv_g_info), - INTEL_PNV_M_IDS(&pnv_m_info), - INTEL_ILK_D_IDS(&ilk_d_info), - INTEL_ILK_M_IDS(&ilk_m_info), - INTEL_SNB_D_GT1_IDS(&snb_d_gt1_info), - INTEL_SNB_D_GT2_IDS(&snb_d_gt2_info), - INTEL_SNB_M_GT1_IDS(&snb_m_gt1_info), - INTEL_SNB_M_GT2_IDS(&snb_m_gt2_info), - INTEL_IVB_Q_IDS(&ivb_q_info), /* must be first IVB */ - INTEL_IVB_M_GT1_IDS(&ivb_m_gt1_info), - INTEL_IVB_M_GT2_IDS(&ivb_m_gt2_info), - INTEL_IVB_D_GT1_IDS(&ivb_d_gt1_info), - INTEL_IVB_D_GT2_IDS(&ivb_d_gt2_info), - INTEL_HSW_GT1_IDS(&hsw_gt1_info), - INTEL_HSW_GT2_IDS(&hsw_gt2_info), - INTEL_HSW_GT3_IDS(&hsw_gt3_info), - INTEL_VLV_IDS(&vlv_info), - INTEL_BDW_GT1_IDS(&bdw_gt1_info), - INTEL_BDW_GT2_IDS(&bdw_gt2_info), - INTEL_BDW_GT3_IDS(&bdw_gt3_info), - INTEL_BDW_RSVD_IDS(&bdw_rsvd_info), - INTEL_CHV_IDS(&chv_info), - INTEL_SKL_GT1_IDS(&skl_gt1_info), - INTEL_SKL_GT2_IDS(&skl_gt2_info), - INTEL_SKL_GT3_IDS(&skl_gt3_info), - INTEL_SKL_GT4_IDS(&skl_gt4_info), - INTEL_BXT_IDS(&bxt_info), - INTEL_GLK_IDS(&glk_info), - INTEL_KBL_GT1_IDS(&kbl_gt1_info), - INTEL_KBL_GT2_IDS(&kbl_gt2_info), - INTEL_KBL_GT3_IDS(&kbl_gt3_info), - INTEL_KBL_GT4_IDS(&kbl_gt3_info), - INTEL_AML_KBL_GT2_IDS(&kbl_gt2_info), - INTEL_CFL_S_GT1_IDS(&cfl_gt1_info), - INTEL_CFL_S_GT2_IDS(&cfl_gt2_info), - INTEL_CFL_H_GT1_IDS(&cfl_gt1_info), - INTEL_CFL_H_GT2_IDS(&cfl_gt2_info), - INTEL_CFL_U_GT2_IDS(&cfl_gt2_info), - INTEL_CFL_U_GT3_IDS(&cfl_gt3_info), - INTEL_WHL_U_GT1_IDS(&cfl_gt1_info), - INTEL_WHL_U_GT2_IDS(&cfl_gt2_info), - INTEL_AML_CFL_GT2_IDS(&cfl_gt2_info), - INTEL_WHL_U_GT3_IDS(&cfl_gt3_info), - INTEL_CML_GT1_IDS(&cml_gt1_info), - INTEL_CML_GT2_IDS(&cml_gt2_info), - INTEL_CML_U_GT1_IDS(&cml_gt1_info), - INTEL_CML_U_GT2_IDS(&cml_gt2_info), - INTEL_ICL_IDS(&icl_info), - INTEL_EHL_IDS(&ehl_info), - INTEL_JSL_IDS(&jsl_info), - INTEL_TGL_IDS(&tgl_info), - INTEL_RKL_IDS(&rkl_info), - INTEL_ADLS_IDS(&adl_s_info), - INTEL_ADLP_IDS(&adl_p_info), - INTEL_ADLN_IDS(&adl_p_info), - INTEL_DG1_IDS(&dg1_info), - INTEL_RPLS_IDS(&adl_s_info), - INTEL_RPLU_IDS(&adl_p_info), - INTEL_RPLP_IDS(&adl_p_info), - INTEL_DG2_IDS(&dg2_info), - INTEL_ATS_M_IDS(&ats_m_info), - INTEL_MTL_IDS(&mtl_info), + INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_info), + INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845g_info), + INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_info), + INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_info), + INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_info), + INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_info), + INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_info), + INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_info), + INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_info), + INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_info), + INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_info), + INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_info), + INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_info), + INTEL_PNV_G_IDS(INTEL_VGA_DEVICE, &pnv_g_info), + INTEL_PNV_M_IDS(INTEL_VGA_DEVICE, &pnv_m_info), + INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_info), + INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_info), + INTEL_SNB_D_GT1_IDS(INTEL_VGA_DEVICE, &snb_d_gt1_info), + INTEL_SNB_D_GT2_IDS(INTEL_VGA_DEVICE, &snb_d_gt2_info), + INTEL_SNB_M_GT1_IDS(INTEL_VGA_DEVICE, &snb_m_gt1_info), + INTEL_SNB_M_GT2_IDS(INTEL_VGA_DEVICE, &snb_m_gt2_info), + INTEL_IVB_Q_IDS(INTEL_VGA_DEVICE, &ivb_q_info), /* must be first IVB */ + INTEL_IVB_M_GT1_IDS(INTEL_VGA_DEVICE, &ivb_m_gt1_info), + INTEL_IVB_M_GT2_IDS(INTEL_VGA_DEVICE, &ivb_m_gt2_info), + INTEL_IVB_D_GT1_IDS(INTEL_VGA_DEVICE, &ivb_d_gt1_info), + INTEL_IVB_D_GT2_IDS(INTEL_VGA_DEVICE, &ivb_d_gt2_info), + INTEL_HSW_GT1_IDS(INTEL_VGA_DEVICE, &hsw_gt1_info), + INTEL_HSW_GT2_IDS(INTEL_VGA_DEVICE, &hsw_gt2_info), + INTEL_HSW_GT3_IDS(INTEL_VGA_DEVICE, &hsw_gt3_info), + INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_info), + INTEL_BDW_GT1_IDS(INTEL_VGA_DEVICE, &bdw_gt1_info), + INTEL_BDW_GT2_IDS(INTEL_VGA_DEVICE, &bdw_gt2_info), + INTEL_BDW_GT3_IDS(INTEL_VGA_DEVICE, &bdw_gt3_info), + INTEL_BDW_RSVD_IDS(INTEL_VGA_DEVICE, &bdw_rsvd_info), + INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_info), + INTEL_SKL_GT1_IDS(INTEL_VGA_DEVICE, &skl_gt1_info), + INTEL_SKL_GT2_IDS(INTEL_VGA_DEVICE, &skl_gt2_info), + INTEL_SKL_GT3_IDS(INTEL_VGA_DEVICE, &skl_gt3_info), + INTEL_SKL_GT4_IDS(INTEL_VGA_DEVICE, &skl_gt4_info), + INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_info), + INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_info), + INTEL_KBL_GT1_IDS(INTEL_VGA_DEVICE, &kbl_gt1_info), + INTEL_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info), + INTEL_KBL_GT3_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info), + INTEL_KBL_GT4_IDS(INTEL_VGA_DEVICE, &kbl_gt3_info), + INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, &kbl_gt2_info), + INTEL_CFL_S_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info), + INTEL_CFL_S_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), + INTEL_CFL_H_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info), + INTEL_CFL_H_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), + INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), + INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info), + INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, &cfl_gt1_info), + INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), + INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, &cfl_gt2_info), + INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, &cfl_gt3_info), + INTEL_CML_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info), + INTEL_CML_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info), + INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, &cml_gt1_info), + INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, &cml_gt2_info), + INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_info), + INTEL_EHL_IDS(INTEL_VGA_DEVICE, &ehl_info), + INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_info), + INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_info), + INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_info), + INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_info), + INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_info), + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &adl_p_info), + INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_info), + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_info), + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &adl_p_info), + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_info), + INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_info), + INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_info), + INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_info), {} }; MODULE_DEVICE_TABLE(pci, pciidlist); diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index a39497971994..82bb34416fb1 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -131,77 +131,77 @@ void intel_device_info_print(const struct intel_device_info *info, #define INTEL_VGA_DEVICE(id, info) (id) static const u16 subplatform_ult_ids[] = { - INTEL_HSW_ULT_GT1_IDS(0), - INTEL_HSW_ULT_GT2_IDS(0), - INTEL_HSW_ULT_GT3_IDS(0), - INTEL_BDW_ULT_GT1_IDS(0), - INTEL_BDW_ULT_GT2_IDS(0), - INTEL_BDW_ULT_GT3_IDS(0), - INTEL_BDW_ULT_RSVD_IDS(0), - INTEL_SKL_ULT_GT1_IDS(0), - INTEL_SKL_ULT_GT2_IDS(0), - INTEL_SKL_ULT_GT3_IDS(0), - INTEL_KBL_ULT_GT1_IDS(0), - INTEL_KBL_ULT_GT2_IDS(0), - INTEL_KBL_ULT_GT3_IDS(0), - INTEL_CFL_U_GT2_IDS(0), - INTEL_CFL_U_GT3_IDS(0), - INTEL_WHL_U_GT1_IDS(0), - INTEL_WHL_U_GT2_IDS(0), - INTEL_WHL_U_GT3_IDS(0), - INTEL_CML_U_GT1_IDS(0), - INTEL_CML_U_GT2_IDS(0), + INTEL_HSW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0), + INTEL_HSW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_HSW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0), + INTEL_BDW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0), + INTEL_BDW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_BDW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0), + INTEL_BDW_ULT_RSVD_IDS(INTEL_VGA_DEVICE, 0), + INTEL_SKL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0), + INTEL_SKL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_SKL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0), + INTEL_KBL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0), + INTEL_KBL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_KBL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0), + INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, 0), + INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, 0), + INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, 0), + INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, 0), + INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, 0), }; static const u16 subplatform_ulx_ids[] = { - INTEL_HSW_ULX_GT1_IDS(0), - INTEL_HSW_ULX_GT2_IDS(0), - INTEL_BDW_ULX_GT1_IDS(0), - INTEL_BDW_ULX_GT2_IDS(0), - INTEL_BDW_ULX_GT3_IDS(0), - INTEL_BDW_ULX_RSVD_IDS(0), - INTEL_SKL_ULX_GT1_IDS(0), - INTEL_SKL_ULX_GT2_IDS(0), - INTEL_KBL_ULX_GT1_IDS(0), - INTEL_KBL_ULX_GT2_IDS(0), - INTEL_AML_KBL_GT2_IDS(0), - INTEL_AML_CFL_GT2_IDS(0), + INTEL_HSW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0), + INTEL_HSW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_BDW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0), + INTEL_BDW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_BDW_ULX_GT3_IDS(INTEL_VGA_DEVICE, 0), + INTEL_BDW_ULX_RSVD_IDS(INTEL_VGA_DEVICE, 0), + INTEL_SKL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0), + INTEL_SKL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_KBL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0), + INTEL_KBL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, 0), }; static const u16 subplatform_portf_ids[] = { - INTEL_ICL_PORT_F_IDS(0), + INTEL_ICL_PORT_F_IDS(INTEL_VGA_DEVICE, 0), }; static const u16 subplatform_uy_ids[] = { - INTEL_TGL_GT2_IDS(0), + INTEL_TGL_GT2_IDS(INTEL_VGA_DEVICE, 0), }; static const u16 subplatform_n_ids[] = { - INTEL_ADLN_IDS(0), + INTEL_ADLN_IDS(INTEL_VGA_DEVICE, 0), }; static const u16 subplatform_rpl_ids[] = { - INTEL_RPLS_IDS(0), - INTEL_RPLU_IDS(0), - INTEL_RPLP_IDS(0), + INTEL_RPLS_IDS(INTEL_VGA_DEVICE, 0), + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0), + INTEL_RPLP_IDS(INTEL_VGA_DEVICE, 0), }; static const u16 subplatform_rplu_ids[] = { - INTEL_RPLU_IDS(0), + INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0), }; static const u16 subplatform_g10_ids[] = { - INTEL_DG2_G10_IDS(0), - INTEL_ATS_M150_IDS(0), + INTEL_DG2_G10_IDS(INTEL_VGA_DEVICE, 0), + INTEL_ATS_M150_IDS(INTEL_VGA_DEVICE, 0), }; static const u16 subplatform_g11_ids[] = { - INTEL_DG2_G11_IDS(0), - INTEL_ATS_M75_IDS(0), + INTEL_DG2_G11_IDS(INTEL_VGA_DEVICE, 0), + INTEL_ATS_M75_IDS(INTEL_VGA_DEVICE, 0), }; static const u16 subplatform_g12_ids[] = { - INTEL_DG2_G12_IDS(0), + INTEL_DG2_G12_IDS(INTEL_VGA_DEVICE, 0), }; static bool find_devid(u16 id, const u16 *p, unsigned int num) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 04f6ca3dc5c1..3e39d644ebaa 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -35,752 +35,752 @@ * Don't use C99 here because "class" is reserved and we want to * give userspace flexibility. */ -#define INTEL_VGA_DEVICE(id, info) { \ - 0x8086, id, \ - ~0, ~0, \ - 0x030000, 0xff0000, \ +#define INTEL_VGA_DEVICE(id, info) { \ + 0x8086, id, \ + ~0, ~0, \ + 0x030000, 0xff0000, \ (unsigned long) info } -#define INTEL_QUANTA_VGA_DEVICE(info) { \ - 0x8086, 0x16a, \ - 0x152d, 0x8990, \ - 0x030000, 0xff0000, \ +#define INTEL_QUANTA_VGA_DEVICE(info) { \ + 0x8086, 0x16a, \ + 0x152d, 0x8990, \ + 0x030000, 0xff0000, \ (unsigned long) info } -#define INTEL_I810_IDS(info) \ - INTEL_VGA_DEVICE(0x7121, info), /* I810 */ \ - INTEL_VGA_DEVICE(0x7123, info), /* I810_DC100 */ \ - INTEL_VGA_DEVICE(0x7125, info) /* I810_E */ +#define INTEL_I810_IDS(MACRO__, ...) \ + MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \ + MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \ + MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */ -#define INTEL_I815_IDS(info) \ - INTEL_VGA_DEVICE(0x1132, info) /* I815*/ +#define INTEL_I815_IDS(MACRO__, ...) \ + MACRO__(0x1132, ## __VA_ARGS__) /* I815*/ -#define INTEL_I830_IDS(info) \ - INTEL_VGA_DEVICE(0x3577, info) +#define INTEL_I830_IDS(MACRO__, ...) \ + MACRO__(0x3577, ## __VA_ARGS__) -#define INTEL_I845G_IDS(info) \ - INTEL_VGA_DEVICE(0x2562, info) +#define INTEL_I845G_IDS(MACRO__, ...) \ + MACRO__(0x2562, ## __VA_ARGS__) -#define INTEL_I85X_IDS(info) \ - INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \ - INTEL_VGA_DEVICE(0x358e, info) +#define INTEL_I85X_IDS(MACRO__, ...) \ + MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \ + MACRO__(0x358e, ## __VA_ARGS__) -#define INTEL_I865G_IDS(info) \ - INTEL_VGA_DEVICE(0x2572, info) /* I865_G */ +#define INTEL_I865G_IDS(MACRO__, ...) \ + MACRO__(0x2572, ## __VA_ARGS__) /* I865_G */ -#define INTEL_I915G_IDS(info) \ - INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \ - INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */ +#define INTEL_I915G_IDS(MACRO__, ...) \ + MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \ + MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */ -#define INTEL_I915GM_IDS(info) \ - INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */ +#define INTEL_I915GM_IDS(MACRO__, ...) \ + MACRO__(0x2592, ## __VA_ARGS__) /* I915_GM */ -#define INTEL_I945G_IDS(info) \ - INTEL_VGA_DEVICE(0x2772, info) /* I945_G */ +#define INTEL_I945G_IDS(MACRO__, ...) \ + MACRO__(0x2772, ## __VA_ARGS__) /* I945_G */ -#define INTEL_I945GM_IDS(info) \ - INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \ - INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */ +#define INTEL_I945GM_IDS(MACRO__, ...) \ + MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \ + MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */ -#define INTEL_I965G_IDS(info) \ - INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \ - INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \ - INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \ - INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */ +#define INTEL_I965G_IDS(MACRO__, ...) \ + MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \ + MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \ + MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \ + MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */ -#define INTEL_G33_IDS(info) \ - INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \ - INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \ - INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */ +#define INTEL_G33_IDS(MACRO__, ...) \ + MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \ + MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \ + MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */ -#define INTEL_I965GM_IDS(info) \ - INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \ - INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */ +#define INTEL_I965GM_IDS(MACRO__, ...) \ + MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \ + MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */ -#define INTEL_GM45_IDS(info) \ - INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */ +#define INTEL_GM45_IDS(MACRO__, ...) \ + MACRO__(0x2a42, ## __VA_ARGS__) /* GM45_G */ -#define INTEL_G45_IDS(info) \ - INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \ - INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \ - INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \ - INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \ - INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \ - INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */ - -#define INTEL_PNV_G_IDS(info) \ - INTEL_VGA_DEVICE(0xa001, info) - -#define INTEL_PNV_M_IDS(info) \ - INTEL_VGA_DEVICE(0xa011, info) - -#define INTEL_PNV_IDS(info) \ - INTEL_PNV_G_IDS(info), \ - INTEL_PNV_M_IDS(info) - -#define INTEL_ILK_D_IDS(info) \ - INTEL_VGA_DEVICE(0x0042, info) - -#define INTEL_ILK_M_IDS(info) \ - INTEL_VGA_DEVICE(0x0046, info) - -#define INTEL_ILK_IDS(info) \ - INTEL_ILK_D_IDS(info), \ - INTEL_ILK_M_IDS(info) - -#define INTEL_SNB_D_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x0102, info), \ - INTEL_VGA_DEVICE(0x010A, info) - -#define INTEL_SNB_D_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x0112, info), \ - INTEL_VGA_DEVICE(0x0122, info) - -#define INTEL_SNB_D_IDS(info) \ - INTEL_SNB_D_GT1_IDS(info), \ - INTEL_SNB_D_GT2_IDS(info) - -#define INTEL_SNB_M_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x0106, info) - -#define INTEL_SNB_M_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x0116, info), \ - INTEL_VGA_DEVICE(0x0126, info) - -#define INTEL_SNB_M_IDS(info) \ - INTEL_SNB_M_GT1_IDS(info), \ - INTEL_SNB_M_GT2_IDS(info) - -#define INTEL_SNB_IDS(info) \ - INTEL_SNB_D_IDS(info), \ - INTEL_SNB_M_IDS(info) - -#define INTEL_IVB_M_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x0156, info) /* GT1 mobile */ - -#define INTEL_IVB_M_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */ - -#define INTEL_IVB_M_IDS(info) \ - INTEL_IVB_M_GT1_IDS(info), \ - INTEL_IVB_M_GT2_IDS(info) - -#define INTEL_IVB_D_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \ - INTEL_VGA_DEVICE(0x015a, info) /* GT1 server */ - -#define INTEL_IVB_D_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \ - INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */ - -#define INTEL_IVB_D_IDS(info) \ - INTEL_IVB_D_GT1_IDS(info), \ - INTEL_IVB_D_GT2_IDS(info) - -#define INTEL_IVB_IDS(info) \ - INTEL_IVB_M_IDS(info), \ - INTEL_IVB_D_IDS(info) - -#define INTEL_IVB_Q_IDS(info) \ - INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */ - -#define INTEL_HSW_ULT_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \ - INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \ - INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \ - INTEL_VGA_DEVICE(0x0A0B, info) /* ULT GT1 reserved */ - -#define INTEL_HSW_ULX_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x0A0E, info) /* ULX GT1 mobile */ - -#define INTEL_HSW_GT1_IDS(info) \ - INTEL_HSW_ULT_GT1_IDS(info), \ - INTEL_HSW_ULX_GT1_IDS(info), \ - INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \ - INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \ - INTEL_VGA_DEVICE(0x040A, info), /* GT1 server */ \ - INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \ - INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \ - INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \ - INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \ - INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \ - INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \ - INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \ - INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \ - INTEL_VGA_DEVICE(0x0D0E, info) /* CRW GT1 reserved */ - -#define INTEL_HSW_ULT_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \ - INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \ - INTEL_VGA_DEVICE(0x0A1B, info) /* ULT GT2 reserved */ \ - -#define INTEL_HSW_ULX_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x0A1E, info) /* ULX GT2 mobile */ \ - -#define INTEL_HSW_GT2_IDS(info) \ - INTEL_HSW_ULT_GT2_IDS(info), \ - INTEL_HSW_ULX_GT2_IDS(info), \ - INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \ - INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \ - INTEL_VGA_DEVICE(0x041A, info), /* GT2 server */ \ - INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \ - INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \ - INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \ - INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \ - INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \ - INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \ - INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \ - INTEL_VGA_DEVICE(0x0D1E, info) /* CRW GT2 reserved */ - -#define INTEL_HSW_ULT_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \ - INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \ - INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \ - INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0A2E, info) /* ULT GT3 reserved */ - -#define INTEL_HSW_GT3_IDS(info) \ - INTEL_HSW_ULT_GT3_IDS(info), \ - INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \ - INTEL_VGA_DEVICE(0x0426, info), /* GT3 mobile */ \ - INTEL_VGA_DEVICE(0x042A, info), /* GT3 server */ \ - INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \ - INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \ - INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \ - INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \ - INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \ - INTEL_VGA_DEVICE(0x0D26, info), /* CRW GT3 mobile */ \ - INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \ - INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \ - INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ - -#define INTEL_HSW_IDS(info) \ - INTEL_HSW_GT1_IDS(info), \ - INTEL_HSW_GT2_IDS(info), \ - INTEL_HSW_GT3_IDS(info) - -#define INTEL_VLV_IDS(info) \ - INTEL_VGA_DEVICE(0x0f30, info), \ - INTEL_VGA_DEVICE(0x0f31, info), \ - INTEL_VGA_DEVICE(0x0f32, info), \ - INTEL_VGA_DEVICE(0x0f33, info) - -#define INTEL_BDW_ULT_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x1606, info), /* GT1 ULT */ \ - INTEL_VGA_DEVICE(0x160B, info) /* GT1 Iris */ - -#define INTEL_BDW_ULX_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x160E, info) /* GT1 ULX */ - -#define INTEL_BDW_GT1_IDS(info) \ - INTEL_BDW_ULT_GT1_IDS(info), \ - INTEL_BDW_ULX_GT1_IDS(info), \ - INTEL_VGA_DEVICE(0x1602, info), /* GT1 ULT */ \ - INTEL_VGA_DEVICE(0x160A, info), /* GT1 Server */ \ - INTEL_VGA_DEVICE(0x160D, info) /* GT1 Workstation */ - -#define INTEL_BDW_ULT_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x1616, info), /* GT2 ULT */ \ - INTEL_VGA_DEVICE(0x161B, info) /* GT2 ULT */ - -#define INTEL_BDW_ULX_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x161E, info) /* GT2 ULX */ - -#define INTEL_BDW_GT2_IDS(info) \ - INTEL_BDW_ULT_GT2_IDS(info), \ - INTEL_BDW_ULX_GT2_IDS(info), \ - INTEL_VGA_DEVICE(0x1612, info), /* GT2 Halo */ \ - INTEL_VGA_DEVICE(0x161A, info), /* GT2 Server */ \ - INTEL_VGA_DEVICE(0x161D, info) /* GT2 Workstation */ - -#define INTEL_BDW_ULT_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x1626, info), /* ULT */ \ - INTEL_VGA_DEVICE(0x162B, info) /* Iris */ \ - -#define INTEL_BDW_ULX_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x162E, info) /* ULX */ - -#define INTEL_BDW_GT3_IDS(info) \ - INTEL_BDW_ULT_GT3_IDS(info), \ - INTEL_BDW_ULX_GT3_IDS(info), \ - INTEL_VGA_DEVICE(0x1622, info), /* ULT */ \ - INTEL_VGA_DEVICE(0x162A, info), /* Server */ \ - INTEL_VGA_DEVICE(0x162D, info) /* Workstation */ - -#define INTEL_BDW_ULT_RSVD_IDS(info) \ - INTEL_VGA_DEVICE(0x1636, info), /* ULT */ \ - INTEL_VGA_DEVICE(0x163B, info) /* Iris */ - -#define INTEL_BDW_ULX_RSVD_IDS(info) \ - INTEL_VGA_DEVICE(0x163E, info) /* ULX */ - -#define INTEL_BDW_RSVD_IDS(info) \ - INTEL_BDW_ULT_RSVD_IDS(info), \ - INTEL_BDW_ULX_RSVD_IDS(info), \ - INTEL_VGA_DEVICE(0x1632, info), /* ULT */ \ - INTEL_VGA_DEVICE(0x163A, info), /* Server */ \ - INTEL_VGA_DEVICE(0x163D, info) /* Workstation */ - -#define INTEL_BDW_IDS(info) \ - INTEL_BDW_GT1_IDS(info), \ - INTEL_BDW_GT2_IDS(info), \ - INTEL_BDW_GT3_IDS(info), \ - INTEL_BDW_RSVD_IDS(info) - -#define INTEL_CHV_IDS(info) \ - INTEL_VGA_DEVICE(0x22b0, info), \ - INTEL_VGA_DEVICE(0x22b1, info), \ - INTEL_VGA_DEVICE(0x22b2, info), \ - INTEL_VGA_DEVICE(0x22b3, info) - -#define INTEL_SKL_ULT_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x1906, info), /* ULT GT1 */ \ - INTEL_VGA_DEVICE(0x1913, info) /* ULT GT1.5 */ - -#define INTEL_SKL_ULX_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x190E, info), /* ULX GT1 */ \ - INTEL_VGA_DEVICE(0x1915, info) /* ULX GT1.5 */ - -#define INTEL_SKL_GT1_IDS(info) \ - INTEL_SKL_ULT_GT1_IDS(info), \ - INTEL_SKL_ULX_GT1_IDS(info), \ - INTEL_VGA_DEVICE(0x1902, info), /* DT GT1 */ \ - INTEL_VGA_DEVICE(0x190A, info), /* SRV GT1 */ \ - INTEL_VGA_DEVICE(0x190B, info), /* Halo GT1 */ \ - INTEL_VGA_DEVICE(0x1917, info) /* DT GT1.5 */ - -#define INTEL_SKL_ULT_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x1916, info), /* ULT GT2 */ \ - INTEL_VGA_DEVICE(0x1921, info) /* ULT GT2F */ - -#define INTEL_SKL_ULX_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x191E, info) /* ULX GT2 */ - -#define INTEL_SKL_GT2_IDS(info) \ - INTEL_SKL_ULT_GT2_IDS(info), \ - INTEL_SKL_ULX_GT2_IDS(info), \ - INTEL_VGA_DEVICE(0x1912, info), /* DT GT2 */ \ - INTEL_VGA_DEVICE(0x191A, info), /* SRV GT2 */ \ - INTEL_VGA_DEVICE(0x191B, info), /* Halo GT2 */ \ - INTEL_VGA_DEVICE(0x191D, info) /* WKS GT2 */ - -#define INTEL_SKL_ULT_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x1923, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x1926, info), /* ULT GT3e */ \ - INTEL_VGA_DEVICE(0x1927, info) /* ULT GT3e */ - -#define INTEL_SKL_GT3_IDS(info) \ - INTEL_SKL_ULT_GT3_IDS(info), \ - INTEL_VGA_DEVICE(0x192A, info), /* SRV GT3 */ \ - INTEL_VGA_DEVICE(0x192B, info), /* Halo GT3e */ \ - INTEL_VGA_DEVICE(0x192D, info) /* SRV GT3e */ - -#define INTEL_SKL_GT4_IDS(info) \ - INTEL_VGA_DEVICE(0x1932, info), /* DT GT4 */ \ - INTEL_VGA_DEVICE(0x193A, info), /* SRV GT4e */ \ - INTEL_VGA_DEVICE(0x193B, info), /* Halo GT4e */ \ - INTEL_VGA_DEVICE(0x193D, info) /* WKS GT4e */ - -#define INTEL_SKL_IDS(info) \ - INTEL_SKL_GT1_IDS(info), \ - INTEL_SKL_GT2_IDS(info), \ - INTEL_SKL_GT3_IDS(info), \ - INTEL_SKL_GT4_IDS(info) - -#define INTEL_BXT_IDS(info) \ - INTEL_VGA_DEVICE(0x0A84, info), \ - INTEL_VGA_DEVICE(0x1A84, info), \ - INTEL_VGA_DEVICE(0x1A85, info), \ - INTEL_VGA_DEVICE(0x5A84, info), /* APL HD Graphics 505 */ \ - INTEL_VGA_DEVICE(0x5A85, info) /* APL HD Graphics 500 */ - -#define INTEL_GLK_IDS(info) \ - INTEL_VGA_DEVICE(0x3184, info), \ - INTEL_VGA_DEVICE(0x3185, info) - -#define INTEL_KBL_ULT_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x5906, info), /* ULT GT1 */ \ - INTEL_VGA_DEVICE(0x5913, info) /* ULT GT1.5 */ - -#define INTEL_KBL_ULX_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x590E, info), /* ULX GT1 */ \ - INTEL_VGA_DEVICE(0x5915, info) /* ULX GT1.5 */ - -#define INTEL_KBL_GT1_IDS(info) \ - INTEL_KBL_ULT_GT1_IDS(info), \ - INTEL_KBL_ULX_GT1_IDS(info), \ - INTEL_VGA_DEVICE(0x5902, info), /* DT GT1 */ \ - INTEL_VGA_DEVICE(0x5908, info), /* Halo GT1 */ \ - INTEL_VGA_DEVICE(0x590A, info), /* SRV GT1 */ \ - INTEL_VGA_DEVICE(0x590B, info) /* Halo GT1 */ - -#define INTEL_KBL_ULT_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x5916, info), /* ULT GT2 */ \ - INTEL_VGA_DEVICE(0x5921, info) /* ULT GT2F */ - -#define INTEL_KBL_ULX_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x591E, info) /* ULX GT2 */ - -#define INTEL_KBL_GT2_IDS(info) \ - INTEL_KBL_ULT_GT2_IDS(info), \ - INTEL_KBL_ULX_GT2_IDS(info), \ - INTEL_VGA_DEVICE(0x5912, info), /* DT GT2 */ \ - INTEL_VGA_DEVICE(0x5917, info), /* Mobile GT2 */ \ - INTEL_VGA_DEVICE(0x591A, info), /* SRV GT2 */ \ - INTEL_VGA_DEVICE(0x591B, info), /* Halo GT2 */ \ - INTEL_VGA_DEVICE(0x591D, info) /* WKS GT2 */ - -#define INTEL_KBL_ULT_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x5926, info) /* ULT GT3 */ - -#define INTEL_KBL_GT3_IDS(info) \ - INTEL_KBL_ULT_GT3_IDS(info), \ - INTEL_VGA_DEVICE(0x5923, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x5927, info) /* ULT GT3 */ - -#define INTEL_KBL_GT4_IDS(info) \ - INTEL_VGA_DEVICE(0x593B, info) /* Halo GT4 */ +#define INTEL_G45_IDS(MACRO__, ...) \ + MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \ + MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \ + MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \ + MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \ + MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \ + MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */ + +#define INTEL_PNV_G_IDS(MACRO__, ...) \ + MACRO__(0xa001, ## __VA_ARGS__) + +#define INTEL_PNV_M_IDS(MACRO__, ...) \ + MACRO__(0xa011, ## __VA_ARGS__) + +#define INTEL_PNV_IDS(MACRO__, ...) \ + INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_ILK_D_IDS(MACRO__, ...) \ + MACRO__(0x0042, ## __VA_ARGS__) + +#define INTEL_ILK_M_IDS(MACRO__, ...) \ + MACRO__(0x0046, ## __VA_ARGS__) + +#define INTEL_ILK_IDS(MACRO__, ...) \ + INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0102, ## __VA_ARGS__), \ + MACRO__(0x010A, ## __VA_ARGS__) + +#define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0112, ## __VA_ARGS__), \ + MACRO__(0x0122, ## __VA_ARGS__) + +#define INTEL_SNB_D_IDS(MACRO__, ...) \ + INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_SNB_M_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0106, ## __VA_ARGS__) + +#define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0116, ## __VA_ARGS__), \ + MACRO__(0x0126, ## __VA_ARGS__) + +#define INTEL_SNB_M_IDS(MACRO__, ...) \ + INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_SNB_IDS(MACRO__, ...) \ + INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_IVB_M_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0156, ## __VA_ARGS__) /* GT1 mobile */ + +#define INTEL_IVB_M_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0166, ## __VA_ARGS__) /* GT2 mobile */ + +#define INTEL_IVB_M_IDS(MACRO__, ...) \ + INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \ + MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */ + +#define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \ + MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */ + +#define INTEL_IVB_D_IDS(MACRO__, ...) \ + INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_IVB_IDS(MACRO__, ...) \ + INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_IVB_Q_IDS(MACRO__, ...) \ + INTEL_QUANTA_VGA_DEVICE(__VA_ARGS__) /* Quanta transcode */ + +#define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \ + MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \ + MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \ + MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */ + +#define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0A0E, ## __VA_ARGS__) /* ULX GT1 mobile */ + +#define INTEL_HSW_GT1_IDS(MACRO__, ...) \ + INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \ + MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \ + MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \ + MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \ + MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \ + MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \ + MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \ + MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \ + MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \ + MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \ + MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \ + MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \ + MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \ + MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \ + MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */ + +#define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \ + MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \ + MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \ + MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \ + +#define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0A1E, ## __VA_ARGS__) /* ULX GT2 mobile */ \ + +#define INTEL_HSW_GT2_IDS(MACRO__, ...) \ + INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \ + MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \ + MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \ + MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \ + MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \ + MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \ + MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \ + MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \ + MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \ + MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \ + MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \ + MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \ + MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \ + MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \ + MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */ + +#define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \ + MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \ + MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \ + MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \ + MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \ + MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */ + +#define INTEL_HSW_GT3_IDS(MACRO__, ...) \ + INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \ + MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \ + MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \ + MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \ + MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \ + MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \ + MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \ + MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \ + MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \ + MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \ + MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \ + MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \ + MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \ + MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \ + MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */ + +#define INTEL_HSW_IDS(MACRO__, ...) \ + INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_VLV_IDS(MACRO__, ...) \ + MACRO__(0x0f30, ## __VA_ARGS__), \ + MACRO__(0x0f31, ## __VA_ARGS__), \ + MACRO__(0x0f32, ## __VA_ARGS__), \ + MACRO__(0x0f33, ## __VA_ARGS__) + +#define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \ + MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \ + MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */ + +#define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) \ + MACRO__(0x160E, ## __VA_ARGS__) /* GT1 ULX */ + +#define INTEL_BDW_GT1_IDS(MACRO__, ...) \ + INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \ + MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \ + MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */ + +#define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \ + MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \ + MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */ + +#define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) \ + MACRO__(0x161E, ## __VA_ARGS__) /* GT2 ULX */ + +#define INTEL_BDW_GT2_IDS(MACRO__, ...) \ + INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \ + MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \ + MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */ + +#define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \ + MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \ + MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \ + +#define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) \ + MACRO__(0x162E, ## __VA_ARGS__) /* ULX */ + +#define INTEL_BDW_GT3_IDS(MACRO__, ...) \ + INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \ + MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \ + MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */ + +#define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \ + MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \ + MACRO__(0x163B, ## __VA_ARGS__) /* Iris */ + +#define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) \ + MACRO__(0x163E, ## __VA_ARGS__) /* ULX */ + +#define INTEL_BDW_RSVD_IDS(MACRO__, ...) \ + INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \ + MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \ + MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */ + +#define INTEL_BDW_IDS(MACRO__, ...) \ + INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_CHV_IDS(MACRO__, ...) \ + MACRO__(0x22b0, ## __VA_ARGS__), \ + MACRO__(0x22b1, ## __VA_ARGS__), \ + MACRO__(0x22b2, ## __VA_ARGS__), \ + MACRO__(0x22b3, ## __VA_ARGS__) + +#define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \ + MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \ + MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */ + +#define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \ + MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \ + MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */ + +#define INTEL_SKL_GT1_IDS(MACRO__, ...) \ + INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \ + MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \ + MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \ + MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */ + +#define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \ + MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \ + MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */ + +#define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) \ + MACRO__(0x191E, ## __VA_ARGS__) /* ULX GT2 */ + +#define INTEL_SKL_GT2_IDS(MACRO__, ...) \ + INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \ + MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \ + MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */ + +#define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \ + MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \ + MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \ + MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */ + +#define INTEL_SKL_GT3_IDS(MACRO__, ...) \ + INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \ + MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \ + MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */ + +#define INTEL_SKL_GT4_IDS(MACRO__, ...) \ + MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \ + MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \ + MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \ + MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */ + +#define INTEL_SKL_IDS(MACRO__, ...) \ + INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_BXT_IDS(MACRO__, ...) \ + MACRO__(0x0A84, ## __VA_ARGS__), \ + MACRO__(0x1A84, ## __VA_ARGS__), \ + MACRO__(0x1A85, ## __VA_ARGS__), \ + MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \ + MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */ + +#define INTEL_GLK_IDS(MACRO__, ...) \ + MACRO__(0x3184, ## __VA_ARGS__), \ + MACRO__(0x3185, ## __VA_ARGS__) + +#define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \ + MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \ + MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */ + +#define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \ + MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \ + MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */ + +#define INTEL_KBL_GT1_IDS(MACRO__, ...) \ + INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \ + MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \ + MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \ + MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */ + +#define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \ + MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \ + MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */ + +#define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) \ + MACRO__(0x591E, ## __VA_ARGS__) /* ULX GT2 */ + +#define INTEL_KBL_GT2_IDS(MACRO__, ...) \ + INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \ + MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \ + MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \ + MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */ + +#define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) \ + MACRO__(0x5926, ## __VA_ARGS__) /* ULT GT3 */ + +#define INTEL_KBL_GT3_IDS(MACRO__, ...) \ + INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \ + MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */ + +#define INTEL_KBL_GT4_IDS(MACRO__, ...) \ + MACRO__(0x593B, ## __VA_ARGS__) /* Halo GT4 */ /* AML/KBL Y GT2 */ -#define INTEL_AML_KBL_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x591C, info), /* ULX GT2 */ \ - INTEL_VGA_DEVICE(0x87C0, info) /* ULX GT2 */ +#define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \ + MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \ + MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */ /* AML/CFL Y GT2 */ -#define INTEL_AML_CFL_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x87CA, info) +#define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) \ + MACRO__(0x87CA, ## __VA_ARGS__) /* CML GT1 */ -#define INTEL_CML_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x9BA2, info), \ - INTEL_VGA_DEVICE(0x9BA4, info), \ - INTEL_VGA_DEVICE(0x9BA5, info), \ - INTEL_VGA_DEVICE(0x9BA8, info) +#define INTEL_CML_GT1_IDS(MACRO__, ...) \ + MACRO__(0x9BA2, ## __VA_ARGS__), \ + MACRO__(0x9BA4, ## __VA_ARGS__), \ + MACRO__(0x9BA5, ## __VA_ARGS__), \ + MACRO__(0x9BA8, ## __VA_ARGS__) -#define INTEL_CML_U_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x9B21, info), \ - INTEL_VGA_DEVICE(0x9BAA, info), \ - INTEL_VGA_DEVICE(0x9BAC, info) +#define INTEL_CML_U_GT1_IDS(MACRO__, ...) \ + MACRO__(0x9B21, ## __VA_ARGS__), \ + MACRO__(0x9BAA, ## __VA_ARGS__), \ + MACRO__(0x9BAC, ## __VA_ARGS__) /* CML GT2 */ -#define INTEL_CML_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x9BC2, info), \ - INTEL_VGA_DEVICE(0x9BC4, info), \ - INTEL_VGA_DEVICE(0x9BC5, info), \ - INTEL_VGA_DEVICE(0x9BC6, info), \ - INTEL_VGA_DEVICE(0x9BC8, info), \ - INTEL_VGA_DEVICE(0x9BE6, info), \ - INTEL_VGA_DEVICE(0x9BF6, info) - -#define INTEL_CML_U_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x9B41, info), \ - INTEL_VGA_DEVICE(0x9BCA, info), \ - INTEL_VGA_DEVICE(0x9BCC, info) - -#define INTEL_CML_IDS(info) \ - INTEL_CML_GT1_IDS(info), \ - INTEL_CML_GT2_IDS(info), \ - INTEL_CML_U_GT1_IDS(info), \ - INTEL_CML_U_GT2_IDS(info) - -#define INTEL_KBL_IDS(info) \ - INTEL_KBL_GT1_IDS(info), \ - INTEL_KBL_GT2_IDS(info), \ - INTEL_KBL_GT3_IDS(info), \ - INTEL_KBL_GT4_IDS(info), \ - INTEL_AML_KBL_GT2_IDS(info) +#define INTEL_CML_GT2_IDS(MACRO__, ...) \ + MACRO__(0x9BC2, ## __VA_ARGS__), \ + MACRO__(0x9BC4, ## __VA_ARGS__), \ + MACRO__(0x9BC5, ## __VA_ARGS__), \ + MACRO__(0x9BC6, ## __VA_ARGS__), \ + MACRO__(0x9BC8, ## __VA_ARGS__), \ + MACRO__(0x9BE6, ## __VA_ARGS__), \ + MACRO__(0x9BF6, ## __VA_ARGS__) + +#define INTEL_CML_U_GT2_IDS(MACRO__, ...) \ + MACRO__(0x9B41, ## __VA_ARGS__), \ + MACRO__(0x9BCA, ## __VA_ARGS__), \ + MACRO__(0x9BCC, ## __VA_ARGS__) + +#define INTEL_CML_IDS(MACRO__, ...) \ + INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_KBL_IDS(MACRO__, ...) \ + INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__) /* CFL S */ -#define INTEL_CFL_S_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \ - INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \ - INTEL_VGA_DEVICE(0x3E99, info) /* SRV GT1 */ - -#define INTEL_CFL_S_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \ - INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \ - INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \ - INTEL_VGA_DEVICE(0x3E98, info), /* SRV GT2 */ \ - INTEL_VGA_DEVICE(0x3E9A, info) /* SRV GT2 */ +#define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \ + MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \ + MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \ + MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */ + +#define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \ + MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */ /* CFL H */ -#define INTEL_CFL_H_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x3E9C, info) +#define INTEL_CFL_H_GT1_IDS(MACRO__, ...) \ + MACRO__(0x3E9C, ## __VA_ARGS__) -#define INTEL_CFL_H_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x3E94, info), /* Halo GT2 */ \ - INTEL_VGA_DEVICE(0x3E9B, info) /* Halo GT2 */ +#define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \ + MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \ + MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */ /* CFL U GT2 */ -#define INTEL_CFL_U_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x3EA9, info) +#define INTEL_CFL_U_GT2_IDS(MACRO__, ...) \ + MACRO__(0x3EA9, ## __VA_ARGS__) /* CFL U GT3 */ -#define INTEL_CFL_U_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \ - INTEL_VGA_DEVICE(0x3EA8, info) /* ULT GT3 */ - -#define INTEL_CFL_IDS(info) \ - INTEL_CFL_S_GT1_IDS(info), \ - INTEL_CFL_S_GT2_IDS(info), \ - INTEL_CFL_H_GT1_IDS(info), \ - INTEL_CFL_H_GT2_IDS(info), \ - INTEL_CFL_U_GT2_IDS(info), \ - INTEL_CFL_U_GT3_IDS(info), \ - INTEL_AML_CFL_GT2_IDS(info) +#define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \ + MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \ + MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \ + MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \ + MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */ + +#define INTEL_CFL_IDS(MACRO__, ...) \ + INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__) /* WHL/CFL U GT1 */ -#define INTEL_WHL_U_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x3EA1, info), \ - INTEL_VGA_DEVICE(0x3EA4, info) +#define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \ + MACRO__(0x3EA1, ## __VA_ARGS__), \ + MACRO__(0x3EA4, ## __VA_ARGS__) /* WHL/CFL U GT2 */ -#define INTEL_WHL_U_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x3EA0, info), \ - INTEL_VGA_DEVICE(0x3EA3, info) +#define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \ + MACRO__(0x3EA0, ## __VA_ARGS__), \ + MACRO__(0x3EA3, ## __VA_ARGS__) /* WHL/CFL U GT3 */ -#define INTEL_WHL_U_GT3_IDS(info) \ - INTEL_VGA_DEVICE(0x3EA2, info) +#define INTEL_WHL_U_GT3_IDS(MACRO__, ...) \ + MACRO__(0x3EA2, ## __VA_ARGS__) -#define INTEL_WHL_IDS(info) \ - INTEL_WHL_U_GT1_IDS(info), \ - INTEL_WHL_U_GT2_IDS(info), \ - INTEL_WHL_U_GT3_IDS(info) +#define INTEL_WHL_IDS(MACRO__, ...) \ + INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__) /* CNL */ -#define INTEL_CNL_PORT_F_IDS(info) \ - INTEL_VGA_DEVICE(0x5A44, info), \ - INTEL_VGA_DEVICE(0x5A4C, info), \ - INTEL_VGA_DEVICE(0x5A54, info), \ - INTEL_VGA_DEVICE(0x5A5C, info) - -#define INTEL_CNL_IDS(info) \ - INTEL_CNL_PORT_F_IDS(info), \ - INTEL_VGA_DEVICE(0x5A40, info), \ - INTEL_VGA_DEVICE(0x5A41, info), \ - INTEL_VGA_DEVICE(0x5A42, info), \ - INTEL_VGA_DEVICE(0x5A49, info), \ - INTEL_VGA_DEVICE(0x5A4A, info), \ - INTEL_VGA_DEVICE(0x5A50, info), \ - INTEL_VGA_DEVICE(0x5A51, info), \ - INTEL_VGA_DEVICE(0x5A52, info), \ - INTEL_VGA_DEVICE(0x5A59, info), \ - INTEL_VGA_DEVICE(0x5A5A, info) +#define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \ + MACRO__(0x5A44, ## __VA_ARGS__), \ + MACRO__(0x5A4C, ## __VA_ARGS__), \ + MACRO__(0x5A54, ## __VA_ARGS__), \ + MACRO__(0x5A5C, ## __VA_ARGS__) + +#define INTEL_CNL_IDS(MACRO__, ...) \ + INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x5A40, ## __VA_ARGS__), \ + MACRO__(0x5A41, ## __VA_ARGS__), \ + MACRO__(0x5A42, ## __VA_ARGS__), \ + MACRO__(0x5A49, ## __VA_ARGS__), \ + MACRO__(0x5A4A, ## __VA_ARGS__), \ + MACRO__(0x5A50, ## __VA_ARGS__), \ + MACRO__(0x5A51, ## __VA_ARGS__), \ + MACRO__(0x5A52, ## __VA_ARGS__), \ + MACRO__(0x5A59, ## __VA_ARGS__), \ + MACRO__(0x5A5A, ## __VA_ARGS__) /* ICL */ -#define INTEL_ICL_PORT_F_IDS(info) \ - INTEL_VGA_DEVICE(0x8A50, info), \ - INTEL_VGA_DEVICE(0x8A52, info), \ - INTEL_VGA_DEVICE(0x8A53, info), \ - INTEL_VGA_DEVICE(0x8A54, info), \ - INTEL_VGA_DEVICE(0x8A56, info), \ - INTEL_VGA_DEVICE(0x8A57, info), \ - INTEL_VGA_DEVICE(0x8A58, info), \ - INTEL_VGA_DEVICE(0x8A59, info), \ - INTEL_VGA_DEVICE(0x8A5A, info), \ - INTEL_VGA_DEVICE(0x8A5B, info), \ - INTEL_VGA_DEVICE(0x8A5C, info), \ - INTEL_VGA_DEVICE(0x8A70, info), \ - INTEL_VGA_DEVICE(0x8A71, info) - -#define INTEL_ICL_IDS(info) \ - INTEL_ICL_PORT_F_IDS(info), \ - INTEL_VGA_DEVICE(0x8A51, info), \ - INTEL_VGA_DEVICE(0x8A5D, info) +#define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \ + MACRO__(0x8A50, ## __VA_ARGS__), \ + MACRO__(0x8A52, ## __VA_ARGS__), \ + MACRO__(0x8A53, ## __VA_ARGS__), \ + MACRO__(0x8A54, ## __VA_ARGS__), \ + MACRO__(0x8A56, ## __VA_ARGS__), \ + MACRO__(0x8A57, ## __VA_ARGS__), \ + MACRO__(0x8A58, ## __VA_ARGS__), \ + MACRO__(0x8A59, ## __VA_ARGS__), \ + MACRO__(0x8A5A, ## __VA_ARGS__), \ + MACRO__(0x8A5B, ## __VA_ARGS__), \ + MACRO__(0x8A5C, ## __VA_ARGS__), \ + MACRO__(0x8A70, ## __VA_ARGS__), \ + MACRO__(0x8A71, ## __VA_ARGS__) + +#define INTEL_ICL_IDS(MACRO__, ...) \ + INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x8A51, ## __VA_ARGS__), \ + MACRO__(0x8A5D, ## __VA_ARGS__) /* EHL */ -#define INTEL_EHL_IDS(info) \ - INTEL_VGA_DEVICE(0x4541, info), \ - INTEL_VGA_DEVICE(0x4551, info), \ - INTEL_VGA_DEVICE(0x4555, info), \ - INTEL_VGA_DEVICE(0x4557, info), \ - INTEL_VGA_DEVICE(0x4570, info), \ - INTEL_VGA_DEVICE(0x4571, info) +#define INTEL_EHL_IDS(MACRO__, ...) \ + MACRO__(0x4541, ## __VA_ARGS__), \ + MACRO__(0x4551, ## __VA_ARGS__), \ + MACRO__(0x4555, ## __VA_ARGS__), \ + MACRO__(0x4557, ## __VA_ARGS__), \ + MACRO__(0x4570, ## __VA_ARGS__), \ + MACRO__(0x4571, ## __VA_ARGS__) /* JSL */ -#define INTEL_JSL_IDS(info) \ - INTEL_VGA_DEVICE(0x4E51, info), \ - INTEL_VGA_DEVICE(0x4E55, info), \ - INTEL_VGA_DEVICE(0x4E57, info), \ - INTEL_VGA_DEVICE(0x4E61, info), \ - INTEL_VGA_DEVICE(0x4E71, info) +#define INTEL_JSL_IDS(MACRO__, ...) \ + MACRO__(0x4E51, ## __VA_ARGS__), \ + MACRO__(0x4E55, ## __VA_ARGS__), \ + MACRO__(0x4E57, ## __VA_ARGS__), \ + MACRO__(0x4E61, ## __VA_ARGS__), \ + MACRO__(0x4E71, ## __VA_ARGS__) /* TGL */ -#define INTEL_TGL_GT1_IDS(info) \ - INTEL_VGA_DEVICE(0x9A60, info), \ - INTEL_VGA_DEVICE(0x9A68, info), \ - INTEL_VGA_DEVICE(0x9A70, info) - -#define INTEL_TGL_GT2_IDS(info) \ - INTEL_VGA_DEVICE(0x9A40, info), \ - INTEL_VGA_DEVICE(0x9A49, info), \ - INTEL_VGA_DEVICE(0x9A59, info), \ - INTEL_VGA_DEVICE(0x9A78, info), \ - INTEL_VGA_DEVICE(0x9AC0, info), \ - INTEL_VGA_DEVICE(0x9AC9, info), \ - INTEL_VGA_DEVICE(0x9AD9, info), \ - INTEL_VGA_DEVICE(0x9AF8, info) - -#define INTEL_TGL_IDS(info) \ - INTEL_TGL_GT1_IDS(info), \ - INTEL_TGL_GT2_IDS(info) +#define INTEL_TGL_GT1_IDS(MACRO__, ...) \ + MACRO__(0x9A60, ## __VA_ARGS__), \ + MACRO__(0x9A68, ## __VA_ARGS__), \ + MACRO__(0x9A70, ## __VA_ARGS__) + +#define INTEL_TGL_GT2_IDS(MACRO__, ...) \ + MACRO__(0x9A40, ## __VA_ARGS__), \ + MACRO__(0x9A49, ## __VA_ARGS__), \ + MACRO__(0x9A59, ## __VA_ARGS__), \ + MACRO__(0x9A78, ## __VA_ARGS__), \ + MACRO__(0x9AC0, ## __VA_ARGS__), \ + MACRO__(0x9AC9, ## __VA_ARGS__), \ + MACRO__(0x9AD9, ## __VA_ARGS__), \ + MACRO__(0x9AF8, ## __VA_ARGS__) + +#define INTEL_TGL_IDS(MACRO__, ...) \ + INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__) /* RKL */ -#define INTEL_RKL_IDS(info) \ - INTEL_VGA_DEVICE(0x4C80, info), \ - INTEL_VGA_DEVICE(0x4C8A, info), \ - INTEL_VGA_DEVICE(0x4C8B, info), \ - INTEL_VGA_DEVICE(0x4C8C, info), \ - INTEL_VGA_DEVICE(0x4C90, info), \ - INTEL_VGA_DEVICE(0x4C9A, info) +#define INTEL_RKL_IDS(MACRO__, ...) \ + MACRO__(0x4C80, ## __VA_ARGS__), \ + MACRO__(0x4C8A, ## __VA_ARGS__), \ + MACRO__(0x4C8B, ## __VA_ARGS__), \ + MACRO__(0x4C8C, ## __VA_ARGS__), \ + MACRO__(0x4C90, ## __VA_ARGS__), \ + MACRO__(0x4C9A, ## __VA_ARGS__) /* DG1 */ -#define INTEL_DG1_IDS(info) \ - INTEL_VGA_DEVICE(0x4905, info), \ - INTEL_VGA_DEVICE(0x4906, info), \ - INTEL_VGA_DEVICE(0x4907, info), \ - INTEL_VGA_DEVICE(0x4908, info), \ - INTEL_VGA_DEVICE(0x4909, info) +#define INTEL_DG1_IDS(MACRO__, ...) \ + MACRO__(0x4905, ## __VA_ARGS__), \ + MACRO__(0x4906, ## __VA_ARGS__), \ + MACRO__(0x4907, ## __VA_ARGS__), \ + MACRO__(0x4908, ## __VA_ARGS__), \ + MACRO__(0x4909, ## __VA_ARGS__) /* ADL-S */ -#define INTEL_ADLS_IDS(info) \ - INTEL_VGA_DEVICE(0x4680, info), \ - INTEL_VGA_DEVICE(0x4682, info), \ - INTEL_VGA_DEVICE(0x4688, info), \ - INTEL_VGA_DEVICE(0x468A, info), \ - INTEL_VGA_DEVICE(0x468B, info), \ - INTEL_VGA_DEVICE(0x4690, info), \ - INTEL_VGA_DEVICE(0x4692, info), \ - INTEL_VGA_DEVICE(0x4693, info) +#define INTEL_ADLS_IDS(MACRO__, ...) \ + MACRO__(0x4680, ## __VA_ARGS__), \ + MACRO__(0x4682, ## __VA_ARGS__), \ + MACRO__(0x4688, ## __VA_ARGS__), \ + MACRO__(0x468A, ## __VA_ARGS__), \ + MACRO__(0x468B, ## __VA_ARGS__), \ + MACRO__(0x4690, ## __VA_ARGS__), \ + MACRO__(0x4692, ## __VA_ARGS__), \ + MACRO__(0x4693, ## __VA_ARGS__) /* ADL-P */ -#define INTEL_ADLP_IDS(info) \ - INTEL_VGA_DEVICE(0x46A0, info), \ - INTEL_VGA_DEVICE(0x46A1, info), \ - INTEL_VGA_DEVICE(0x46A2, info), \ - INTEL_VGA_DEVICE(0x46A3, info), \ - INTEL_VGA_DEVICE(0x46A6, info), \ - INTEL_VGA_DEVICE(0x46A8, info), \ - INTEL_VGA_DEVICE(0x46AA, info), \ - INTEL_VGA_DEVICE(0x462A, info), \ - INTEL_VGA_DEVICE(0x4626, info), \ - INTEL_VGA_DEVICE(0x4628, info), \ - INTEL_VGA_DEVICE(0x46B0, info), \ - INTEL_VGA_DEVICE(0x46B1, info), \ - INTEL_VGA_DEVICE(0x46B2, info), \ - INTEL_VGA_DEVICE(0x46B3, info), \ - INTEL_VGA_DEVICE(0x46C0, info), \ - INTEL_VGA_DEVICE(0x46C1, info), \ - INTEL_VGA_DEVICE(0x46C2, info), \ - INTEL_VGA_DEVICE(0x46C3, info) +#define INTEL_ADLP_IDS(MACRO__, ...) \ + MACRO__(0x46A0, ## __VA_ARGS__), \ + MACRO__(0x46A1, ## __VA_ARGS__), \ + MACRO__(0x46A2, ## __VA_ARGS__), \ + MACRO__(0x46A3, ## __VA_ARGS__), \ + MACRO__(0x46A6, ## __VA_ARGS__), \ + MACRO__(0x46A8, ## __VA_ARGS__), \ + MACRO__(0x46AA, ## __VA_ARGS__), \ + MACRO__(0x462A, ## __VA_ARGS__), \ + MACRO__(0x4626, ## __VA_ARGS__), \ + MACRO__(0x4628, ## __VA_ARGS__), \ + MACRO__(0x46B0, ## __VA_ARGS__), \ + MACRO__(0x46B1, ## __VA_ARGS__), \ + MACRO__(0x46B2, ## __VA_ARGS__), \ + MACRO__(0x46B3, ## __VA_ARGS__), \ + MACRO__(0x46C0, ## __VA_ARGS__), \ + MACRO__(0x46C1, ## __VA_ARGS__), \ + MACRO__(0x46C2, ## __VA_ARGS__), \ + MACRO__(0x46C3, ## __VA_ARGS__) /* ADL-N */ -#define INTEL_ADLN_IDS(info) \ - INTEL_VGA_DEVICE(0x46D0, info), \ - INTEL_VGA_DEVICE(0x46D1, info), \ - INTEL_VGA_DEVICE(0x46D2, info), \ - INTEL_VGA_DEVICE(0x46D3, info), \ - INTEL_VGA_DEVICE(0x46D4, info) +#define INTEL_ADLN_IDS(MACRO__, ...) \ + MACRO__(0x46D0, ## __VA_ARGS__), \ + MACRO__(0x46D1, ## __VA_ARGS__), \ + MACRO__(0x46D2, ## __VA_ARGS__), \ + MACRO__(0x46D3, ## __VA_ARGS__), \ + MACRO__(0x46D4, ## __VA_ARGS__) /* RPL-S */ -#define INTEL_RPLS_IDS(info) \ - INTEL_VGA_DEVICE(0xA780, info), \ - INTEL_VGA_DEVICE(0xA781, info), \ - INTEL_VGA_DEVICE(0xA782, info), \ - INTEL_VGA_DEVICE(0xA783, info), \ - INTEL_VGA_DEVICE(0xA788, info), \ - INTEL_VGA_DEVICE(0xA789, info), \ - INTEL_VGA_DEVICE(0xA78A, info), \ - INTEL_VGA_DEVICE(0xA78B, info) +#define INTEL_RPLS_IDS(MACRO__, ...) \ + MACRO__(0xA780, ## __VA_ARGS__), \ + MACRO__(0xA781, ## __VA_ARGS__), \ + MACRO__(0xA782, ## __VA_ARGS__), \ + MACRO__(0xA783, ## __VA_ARGS__), \ + MACRO__(0xA788, ## __VA_ARGS__), \ + MACRO__(0xA789, ## __VA_ARGS__), \ + MACRO__(0xA78A, ## __VA_ARGS__), \ + MACRO__(0xA78B, ## __VA_ARGS__) /* RPL-U */ -#define INTEL_RPLU_IDS(info) \ - INTEL_VGA_DEVICE(0xA721, info), \ - INTEL_VGA_DEVICE(0xA7A1, info), \ - INTEL_VGA_DEVICE(0xA7A9, info), \ - INTEL_VGA_DEVICE(0xA7AC, info), \ - INTEL_VGA_DEVICE(0xA7AD, info) +#define INTEL_RPLU_IDS(MACRO__, ...) \ + MACRO__(0xA721, ## __VA_ARGS__), \ + MACRO__(0xA7A1, ## __VA_ARGS__), \ + MACRO__(0xA7A9, ## __VA_ARGS__), \ + MACRO__(0xA7AC, ## __VA_ARGS__), \ + MACRO__(0xA7AD, ## __VA_ARGS__) /* RPL-P */ -#define INTEL_RPLP_IDS(info) \ - INTEL_VGA_DEVICE(0xA720, info), \ - INTEL_VGA_DEVICE(0xA7A0, info), \ - INTEL_VGA_DEVICE(0xA7A8, info), \ - INTEL_VGA_DEVICE(0xA7AA, info), \ - INTEL_VGA_DEVICE(0xA7AB, info) +#define INTEL_RPLP_IDS(MACRO__, ...) \ + MACRO__(0xA720, ## __VA_ARGS__), \ + MACRO__(0xA7A0, ## __VA_ARGS__), \ + MACRO__(0xA7A8, ## __VA_ARGS__), \ + MACRO__(0xA7AA, ## __VA_ARGS__), \ + MACRO__(0xA7AB, ## __VA_ARGS__) /* DG2 */ -#define INTEL_DG2_G10_IDS(info) \ - INTEL_VGA_DEVICE(0x5690, info), \ - INTEL_VGA_DEVICE(0x5691, info), \ - INTEL_VGA_DEVICE(0x5692, info), \ - INTEL_VGA_DEVICE(0x56A0, info), \ - INTEL_VGA_DEVICE(0x56A1, info), \ - INTEL_VGA_DEVICE(0x56A2, info), \ - INTEL_VGA_DEVICE(0x56BE, info), \ - INTEL_VGA_DEVICE(0x56BF, info) - -#define INTEL_DG2_G11_IDS(info) \ - INTEL_VGA_DEVICE(0x5693, info), \ - INTEL_VGA_DEVICE(0x5694, info), \ - INTEL_VGA_DEVICE(0x5695, info), \ - INTEL_VGA_DEVICE(0x56A5, info), \ - INTEL_VGA_DEVICE(0x56A6, info), \ - INTEL_VGA_DEVICE(0x56B0, info), \ - INTEL_VGA_DEVICE(0x56B1, info), \ - INTEL_VGA_DEVICE(0x56BA, info), \ - INTEL_VGA_DEVICE(0x56BB, info), \ - INTEL_VGA_DEVICE(0x56BC, info), \ - INTEL_VGA_DEVICE(0x56BD, info) - -#define INTEL_DG2_G12_IDS(info) \ - INTEL_VGA_DEVICE(0x5696, info), \ - INTEL_VGA_DEVICE(0x5697, info), \ - INTEL_VGA_DEVICE(0x56A3, info), \ - INTEL_VGA_DEVICE(0x56A4, info), \ - INTEL_VGA_DEVICE(0x56B2, info), \ - INTEL_VGA_DEVICE(0x56B3, info) - -#define INTEL_DG2_IDS(info) \ - INTEL_DG2_G10_IDS(info), \ - INTEL_DG2_G11_IDS(info), \ - INTEL_DG2_G12_IDS(info) - -#define INTEL_ATS_M150_IDS(info) \ - INTEL_VGA_DEVICE(0x56C0, info), \ - INTEL_VGA_DEVICE(0x56C2, info) - -#define INTEL_ATS_M75_IDS(info) \ - INTEL_VGA_DEVICE(0x56C1, info) - -#define INTEL_ATS_M_IDS(info) \ - INTEL_ATS_M150_IDS(info), \ - INTEL_ATS_M75_IDS(info) +#define INTEL_DG2_G10_IDS(MACRO__, ...) \ + MACRO__(0x5690, ## __VA_ARGS__), \ + MACRO__(0x5691, ## __VA_ARGS__), \ + MACRO__(0x5692, ## __VA_ARGS__), \ + MACRO__(0x56A0, ## __VA_ARGS__), \ + MACRO__(0x56A1, ## __VA_ARGS__), \ + MACRO__(0x56A2, ## __VA_ARGS__), \ + MACRO__(0x56BE, ## __VA_ARGS__), \ + MACRO__(0x56BF, ## __VA_ARGS__) + +#define INTEL_DG2_G11_IDS(MACRO__, ...) \ + MACRO__(0x5693, ## __VA_ARGS__), \ + MACRO__(0x5694, ## __VA_ARGS__), \ + MACRO__(0x5695, ## __VA_ARGS__), \ + MACRO__(0x56A5, ## __VA_ARGS__), \ + MACRO__(0x56A6, ## __VA_ARGS__), \ + MACRO__(0x56B0, ## __VA_ARGS__), \ + MACRO__(0x56B1, ## __VA_ARGS__), \ + MACRO__(0x56BA, ## __VA_ARGS__), \ + MACRO__(0x56BB, ## __VA_ARGS__), \ + MACRO__(0x56BC, ## __VA_ARGS__), \ + MACRO__(0x56BD, ## __VA_ARGS__) + +#define INTEL_DG2_G12_IDS(MACRO__, ...) \ + MACRO__(0x5696, ## __VA_ARGS__), \ + MACRO__(0x5697, ## __VA_ARGS__), \ + MACRO__(0x56A3, ## __VA_ARGS__), \ + MACRO__(0x56A4, ## __VA_ARGS__), \ + MACRO__(0x56B2, ## __VA_ARGS__), \ + MACRO__(0x56B3, ## __VA_ARGS__) + +#define INTEL_DG2_IDS(MACRO__, ...) \ + INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_ATS_M150_IDS(MACRO__, ...) \ + MACRO__(0x56C0, ## __VA_ARGS__), \ + MACRO__(0x56C2, ## __VA_ARGS__) + +#define INTEL_ATS_M75_IDS(MACRO__, ...) \ + MACRO__(0x56C1, ## __VA_ARGS__) + +#define INTEL_ATS_M_IDS(MACRO__, ...) \ + INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) /* MTL */ -#define INTEL_MTL_IDS(info) \ - INTEL_VGA_DEVICE(0x7D40, info), \ - INTEL_VGA_DEVICE(0x7D41, info), \ - INTEL_VGA_DEVICE(0x7D45, info), \ - INTEL_VGA_DEVICE(0x7D51, info), \ - INTEL_VGA_DEVICE(0x7D55, info), \ - INTEL_VGA_DEVICE(0x7D60, info), \ - INTEL_VGA_DEVICE(0x7D67, info), \ - INTEL_VGA_DEVICE(0x7DD1, info), \ - INTEL_VGA_DEVICE(0x7DD5, info) +#define INTEL_MTL_IDS(MACRO__, ...) \ + MACRO__(0x7D40, ## __VA_ARGS__), \ + MACRO__(0x7D41, ## __VA_ARGS__), \ + MACRO__(0x7D45, ## __VA_ARGS__), \ + MACRO__(0x7D51, ## __VA_ARGS__), \ + MACRO__(0x7D55, ## __VA_ARGS__), \ + MACRO__(0x7D60, ## __VA_ARGS__), \ + MACRO__(0x7D67, ## __VA_ARGS__), \ + MACRO__(0x7DD1, ## __VA_ARGS__), \ + MACRO__(0x7DD5, ## __VA_ARGS__) #endif /* _I915_PCIIDS_H */ -- cgit From 3c7bbd4c9dc42e05218d489bd487580336d42fc7 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 15 May 2024 19:56:51 +0300 Subject: drm/i915: stop redefining INTEL_VGA_DEVICE Now that the PCI ID macros allow us to pass in the macro to use, stop redefining INTEL_VGA_DEVICE. Cc: Lucas De Marchi Cc: Rodrigo Vivi Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20240515165651.1230465-2-jani.nikula@intel.com Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_device.c | 87 ++++++++++----------- drivers/gpu/drm/i915/intel_device_info.c | 91 +++++++++++----------- 2 files changed, 88 insertions(+), 90 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 950e66cdba0a..cf093bc0cb28 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -795,55 +795,54 @@ static bool has_no_display(struct pci_dev *pdev) return pci_match_id(ids, pdev); } -#undef INTEL_VGA_DEVICE -#define INTEL_VGA_DEVICE(id, info) { id, info } +#define INTEL_DISPLAY_DEVICE(_id, _info) { .devid = (_id), .info = (_info) } static const struct { u32 devid; const struct intel_display_device_info *info; } intel_display_ids[] = { - INTEL_I830_IDS(INTEL_VGA_DEVICE, &i830_display), - INTEL_I845G_IDS(INTEL_VGA_DEVICE, &i845_display), - INTEL_I85X_IDS(INTEL_VGA_DEVICE, &i85x_display), - INTEL_I865G_IDS(INTEL_VGA_DEVICE, &i865g_display), - INTEL_I915G_IDS(INTEL_VGA_DEVICE, &i915g_display), - INTEL_I915GM_IDS(INTEL_VGA_DEVICE, &i915gm_display), - INTEL_I945G_IDS(INTEL_VGA_DEVICE, &i945g_display), - INTEL_I945GM_IDS(INTEL_VGA_DEVICE, &i945gm_display), - INTEL_I965G_IDS(INTEL_VGA_DEVICE, &i965g_display), - INTEL_G33_IDS(INTEL_VGA_DEVICE, &g33_display), - INTEL_I965GM_IDS(INTEL_VGA_DEVICE, &i965gm_display), - INTEL_GM45_IDS(INTEL_VGA_DEVICE, &gm45_display), - INTEL_G45_IDS(INTEL_VGA_DEVICE, &g45_display), - INTEL_PNV_IDS(INTEL_VGA_DEVICE, &pnv_display), - INTEL_ILK_D_IDS(INTEL_VGA_DEVICE, &ilk_d_display), - INTEL_ILK_M_IDS(INTEL_VGA_DEVICE, &ilk_m_display), - INTEL_SNB_IDS(INTEL_VGA_DEVICE, &snb_display), - INTEL_IVB_IDS(INTEL_VGA_DEVICE, &ivb_display), - INTEL_HSW_IDS(INTEL_VGA_DEVICE, &hsw_display), - INTEL_VLV_IDS(INTEL_VGA_DEVICE, &vlv_display), - INTEL_BDW_IDS(INTEL_VGA_DEVICE, &bdw_display), - INTEL_CHV_IDS(INTEL_VGA_DEVICE, &chv_display), - INTEL_SKL_IDS(INTEL_VGA_DEVICE, &skl_display), - INTEL_BXT_IDS(INTEL_VGA_DEVICE, &bxt_display), - INTEL_GLK_IDS(INTEL_VGA_DEVICE, &glk_display), - INTEL_KBL_IDS(INTEL_VGA_DEVICE, &skl_display), - INTEL_CFL_IDS(INTEL_VGA_DEVICE, &skl_display), - INTEL_WHL_IDS(INTEL_VGA_DEVICE, &skl_display), - INTEL_CML_IDS(INTEL_VGA_DEVICE, &skl_display), - INTEL_ICL_IDS(INTEL_VGA_DEVICE, &icl_display), - INTEL_EHL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display), - INTEL_JSL_IDS(INTEL_VGA_DEVICE, &jsl_ehl_display), - INTEL_TGL_IDS(INTEL_VGA_DEVICE, &tgl_display), - INTEL_DG1_IDS(INTEL_VGA_DEVICE, &dg1_display), - INTEL_RKL_IDS(INTEL_VGA_DEVICE, &rkl_display), - INTEL_ADLS_IDS(INTEL_VGA_DEVICE, &adl_s_display), - INTEL_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_display), - INTEL_ADLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display), - INTEL_ADLN_IDS(INTEL_VGA_DEVICE, &xe_lpd_display), - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, &xe_lpd_display), - INTEL_RPLP_IDS(INTEL_VGA_DEVICE, &xe_lpd_display), - INTEL_DG2_IDS(INTEL_VGA_DEVICE, &xe_hpd_display), + INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_display), + INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_display), + INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_display), + INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_display), + INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_display), + INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_display), + INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_display), + INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_display), + INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_display), + INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_display), + INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_display), + INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_display), + INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_display), + INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_display), + INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_display), + INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_display), + INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_display), + INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_display), + INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_display), + INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_display), + INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_display), + INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_display), + INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), + INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_display), + INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_display), + INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), + INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), + INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), + INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &skl_display), + INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_display), + INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display), + INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display), + INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_display), + INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_display), + INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_display), + INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display), + INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display), + INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), + INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), + INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), + INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), + INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &xe_hpd_display), /* * Do not add any GMD_ID-based platforms to this list. They will diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 82bb34416fb1..862f4b705227 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -127,81 +127,80 @@ void intel_device_info_print(const struct intel_device_info *info, drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq); } -#undef INTEL_VGA_DEVICE -#define INTEL_VGA_DEVICE(id, info) (id) +#define ID(id) (id) static const u16 subplatform_ult_ids[] = { - INTEL_HSW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0), - INTEL_HSW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_HSW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0), - INTEL_BDW_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0), - INTEL_BDW_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_BDW_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0), - INTEL_BDW_ULT_RSVD_IDS(INTEL_VGA_DEVICE, 0), - INTEL_SKL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0), - INTEL_SKL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_SKL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0), - INTEL_KBL_ULT_GT1_IDS(INTEL_VGA_DEVICE, 0), - INTEL_KBL_ULT_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_KBL_ULT_GT3_IDS(INTEL_VGA_DEVICE, 0), - INTEL_CFL_U_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_CFL_U_GT3_IDS(INTEL_VGA_DEVICE, 0), - INTEL_WHL_U_GT1_IDS(INTEL_VGA_DEVICE, 0), - INTEL_WHL_U_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_WHL_U_GT3_IDS(INTEL_VGA_DEVICE, 0), - INTEL_CML_U_GT1_IDS(INTEL_VGA_DEVICE, 0), - INTEL_CML_U_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_HSW_ULT_GT1_IDS(ID), + INTEL_HSW_ULT_GT2_IDS(ID), + INTEL_HSW_ULT_GT3_IDS(ID), + INTEL_BDW_ULT_GT1_IDS(ID), + INTEL_BDW_ULT_GT2_IDS(ID), + INTEL_BDW_ULT_GT3_IDS(ID), + INTEL_BDW_ULT_RSVD_IDS(ID), + INTEL_SKL_ULT_GT1_IDS(ID), + INTEL_SKL_ULT_GT2_IDS(ID), + INTEL_SKL_ULT_GT3_IDS(ID), + INTEL_KBL_ULT_GT1_IDS(ID), + INTEL_KBL_ULT_GT2_IDS(ID), + INTEL_KBL_ULT_GT3_IDS(ID), + INTEL_CFL_U_GT2_IDS(ID), + INTEL_CFL_U_GT3_IDS(ID), + INTEL_WHL_U_GT1_IDS(ID), + INTEL_WHL_U_GT2_IDS(ID), + INTEL_WHL_U_GT3_IDS(ID), + INTEL_CML_U_GT1_IDS(ID), + INTEL_CML_U_GT2_IDS(ID), }; static const u16 subplatform_ulx_ids[] = { - INTEL_HSW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0), - INTEL_HSW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_BDW_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0), - INTEL_BDW_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_BDW_ULX_GT3_IDS(INTEL_VGA_DEVICE, 0), - INTEL_BDW_ULX_RSVD_IDS(INTEL_VGA_DEVICE, 0), - INTEL_SKL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0), - INTEL_SKL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_KBL_ULX_GT1_IDS(INTEL_VGA_DEVICE, 0), - INTEL_KBL_ULX_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_AML_KBL_GT2_IDS(INTEL_VGA_DEVICE, 0), - INTEL_AML_CFL_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_HSW_ULX_GT1_IDS(ID), + INTEL_HSW_ULX_GT2_IDS(ID), + INTEL_BDW_ULX_GT1_IDS(ID), + INTEL_BDW_ULX_GT2_IDS(ID), + INTEL_BDW_ULX_GT3_IDS(ID), + INTEL_BDW_ULX_RSVD_IDS(ID), + INTEL_SKL_ULX_GT1_IDS(ID), + INTEL_SKL_ULX_GT2_IDS(ID), + INTEL_KBL_ULX_GT1_IDS(ID), + INTEL_KBL_ULX_GT2_IDS(ID), + INTEL_AML_KBL_GT2_IDS(ID), + INTEL_AML_CFL_GT2_IDS(ID), }; static const u16 subplatform_portf_ids[] = { - INTEL_ICL_PORT_F_IDS(INTEL_VGA_DEVICE, 0), + INTEL_ICL_PORT_F_IDS(ID), }; static const u16 subplatform_uy_ids[] = { - INTEL_TGL_GT2_IDS(INTEL_VGA_DEVICE, 0), + INTEL_TGL_GT2_IDS(ID), }; static const u16 subplatform_n_ids[] = { - INTEL_ADLN_IDS(INTEL_VGA_DEVICE, 0), + INTEL_ADLN_IDS(ID), }; static const u16 subplatform_rpl_ids[] = { - INTEL_RPLS_IDS(INTEL_VGA_DEVICE, 0), - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0), - INTEL_RPLP_IDS(INTEL_VGA_DEVICE, 0), + INTEL_RPLS_IDS(ID), + INTEL_RPLU_IDS(ID), + INTEL_RPLP_IDS(ID), }; static const u16 subplatform_rplu_ids[] = { - INTEL_RPLU_IDS(INTEL_VGA_DEVICE, 0), + INTEL_RPLU_IDS(ID), }; static const u16 subplatform_g10_ids[] = { - INTEL_DG2_G10_IDS(INTEL_VGA_DEVICE, 0), - INTEL_ATS_M150_IDS(INTEL_VGA_DEVICE, 0), + INTEL_DG2_G10_IDS(ID), + INTEL_ATS_M150_IDS(ID), }; static const u16 subplatform_g11_ids[] = { - INTEL_DG2_G11_IDS(INTEL_VGA_DEVICE, 0), - INTEL_ATS_M75_IDS(INTEL_VGA_DEVICE, 0), + INTEL_DG2_G11_IDS(ID), + INTEL_ATS_M75_IDS(ID), }; static const u16 subplatform_g12_ids[] = { - INTEL_DG2_G12_IDS(INTEL_VGA_DEVICE, 0), + INTEL_DG2_G12_IDS(ID), }; static bool find_devid(u16 id, const u16 *p, unsigned int num) -- cgit From 1155de965e6a4987e2897f78ea56f07c7140764e Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 21 May 2024 13:44:56 +0530 Subject: drm/i915/hdcp: Move aux assignment after connector type check Move assignment of aux after connector type check as port may not exist if connector is not DPMST. --v2 -Fix unwanted change in intel_encoder check [Jani] Signed-off-by: Suraj Kandpal Reviewed-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240521081458.1500327-2-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index 92b03073acdd..551c862ed7a6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -687,7 +687,7 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector, bool *hdcp2_capable) { struct drm_i915_private *i915 = to_i915(connector->base.dev); - struct drm_dp_aux *aux = &connector->port->aux; + struct drm_dp_aux *aux; u8 bcaps; int ret; @@ -696,6 +696,7 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector, if (!intel_encoder_is_mst(connector->encoder)) return -EINVAL; + aux = &connector->port->aux; ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable); if (ret) drm_dbg_kms(&i915->drm, -- cgit From 76e220d4d88266a1b9f44b409959079292e409ad Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Tue, 21 May 2024 13:44:57 +0530 Subject: drm/i915/hdcp: Check mst_port to determine connector type Check mst_port field in intel_connector to check connector type rather than rely on encoder as it may not be attached to connector at times. --v2 -Add closes tag [Imre] Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10898 Signed-off-by: Suraj Kandpal Reviewed-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240521081458.1500327-3-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c index 551c862ed7a6..2edffe62f360 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c @@ -693,7 +693,7 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector, *hdcp_capable = false; *hdcp2_capable = false; - if (!intel_encoder_is_mst(connector->encoder)) + if (!connector->mst_port) return -EINVAL; aux = &connector->port->aux; -- cgit From bb3c3e79d9a1331eb03696e9a4274293767af594 Mon Sep 17 00:00:00 2001 From: Gustavo Sousa Date: Fri, 10 May 2024 11:05:33 -0300 Subject: drm/i915/bmg: Load DMC Load Battlemage's DMC. We re-use XELPDP_DMC_MAX_FW_SIZE since BMG's display is a derivative of Xe_LPD+ and has the same MMIO offset limits. Reviewed-by: Dnyaneshwar Bhadane Link: https://patchwork.freedesktop.org/patch/msgid/20240510140532.112352-2-gustavo.sousa@intel.com Signed-off-by: Gustavo Sousa --- drivers/gpu/drm/i915/display/intel_dmc.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index cbd2ac5671b1..63fccdda56c0 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -115,6 +115,9 @@ static bool dmc_firmware_param_disabled(struct drm_i915_private *i915) #define XE2LPD_DMC_PATH DMC_PATH(xe2lpd) MODULE_FIRMWARE(XE2LPD_DMC_PATH); +#define BMG_DMC_PATH DMC_PATH(bmg) +MODULE_FIRMWARE(BMG_DMC_PATH); + #define MTL_DMC_PATH DMC_PATH(mtl) MODULE_FIRMWARE(MTL_DMC_PATH); @@ -166,6 +169,9 @@ static const char *dmc_firmware_default(struct drm_i915_private *i915, u32 *size if (DISPLAY_VER_FULL(i915) == IP_VER(20, 0)) { fw_path = XE2LPD_DMC_PATH; max_fw_size = XE2LPD_DMC_MAX_FW_SIZE; + } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1)) { + fw_path = BMG_DMC_PATH; + max_fw_size = XELPDP_DMC_MAX_FW_SIZE; } else if (DISPLAY_VER_FULL(i915) == IP_VER(14, 0)) { fw_path = MTL_DMC_PATH; max_fw_size = XELPDP_DMC_MAX_FW_SIZE; -- cgit From 2689390b4ecc27d6f0a97f24544d75bd168a21b8 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 20 May 2024 19:47:32 +0300 Subject: drm/i915: Bump max TMDS bitrate to 6 Gbps on ADL-S/ADL-P/DG2+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bspec lists the mas TMDS bitrate as 6 Gbps on ADL-S/ADL-P/DG2. Bump our limit to match. v2: Bump for ADL-S as well (Jani) Cc: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240520164732.3682-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 0faf2afa1c09..9ac670a40bc1 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1784,7 +1784,9 @@ static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int max_tmds_clock, vbt_max_tmds_clock; - if (DISPLAY_VER(dev_priv) >= 10) + if (DISPLAY_VER(dev_priv) >= 13 || IS_ALDERLAKE_S(dev_priv)) + max_tmds_clock = 600000; + else if (DISPLAY_VER(dev_priv) >= 10) max_tmds_clock = 594000; else if (DISPLAY_VER(dev_priv) >= 8 || IS_HASWELL(dev_priv)) max_tmds_clock = 300000; -- cgit From 51064d471c53dcc8eddd2333c3f1c1d9131ba36c Mon Sep 17 00:00:00 2001 From: Vidya Srinivas Date: Mon, 20 May 2024 22:26:34 +0530 Subject: drm/i915/dpt: Make DPT object unshrinkable MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In some scenarios, the DPT object gets shrunk but the actual framebuffer did not and thus its still there on the DPT's vm->bound_list. Then it tries to rewrite the PTEs via a stale CPU mapping. This causes panic. Cc: stable@vger.kernel.org Reported-by: Shawn Lee Fixes: 0dc987b699ce ("drm/i915/display: Add smem fallback allocation for dpt") Signed-off-by: Vidya Srinivas [vsyrjala: Add TODO comment] Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240520165634.1162470-1-vidya.srinivas@intel.com --- drivers/gpu/drm/i915/gem/i915_gem_object.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_object.h b/drivers/gpu/drm/i915/gem/i915_gem_object.h index 3560a062d287..5d7446a48ae7 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_object.h +++ b/drivers/gpu/drm/i915/gem/i915_gem_object.h @@ -284,7 +284,9 @@ bool i915_gem_object_has_iomem(const struct drm_i915_gem_object *obj); static inline bool i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj) { - return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE); + /* TODO: make DPT shrinkable when it has no bound vmas */ + return i915_gem_object_type_has(obj, I915_GEM_OBJECT_IS_SHRINKABLE) && + !obj->is_dpt; } static inline bool -- cgit From df798d43b35521f004c2f209dbb264c47488218f Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 17 May 2024 20:12:08 +0300 Subject: drm/i915: Add skl+ plane name aliases to enum plane_id MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch of unnecessary head scratching. Add aliases using the skl+ plane names. And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1 as we only ever have 0-2 sprites per pipe on those platforms. v2: Don't break icl_nv12_y_plane_mask() (Jani) Cc: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240517171208.21313-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crtc.c | 6 ++---- drivers/gpu/drm/i915/display/intel_display.c | 8 ++++---- drivers/gpu/drm/i915/display/intel_display_limits.h | 21 ++++++++++++++------- drivers/gpu/drm/i915/display/intel_sprite_uapi.c | 2 +- drivers/gpu/drm/i915/display/skl_universal_plane.c | 19 +++++++++---------- 5 files changed, 30 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 339010384b86..ca6dc1dc56c8 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -310,8 +310,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe]; if (DISPLAY_VER(dev_priv) >= 9) - primary = skl_universal_plane_create(dev_priv, pipe, - PLANE_PRIMARY); + primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1); else primary = intel_primary_plane_create(dev_priv, pipe); if (IS_ERR(primary)) { @@ -326,8 +325,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) struct intel_plane *plane; if (DISPLAY_VER(dev_priv) >= 9) - plane = skl_universal_plane_create(dev_priv, pipe, - PLANE_SPRITE0 + sprite); + plane = skl_universal_plane_create(dev_priv, pipe, PLANE_2 + sprite); else plane = intel_sprite_plane_create(dev_priv, pipe, sprite); if (IS_ERR(plane)) { diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index cce1420fb541..ee2df655b0ab 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4121,13 +4121,13 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) linked_state->uapi.dst = plane_state->uapi.dst; if (icl_is_hdr_plane(dev_priv, plane->id)) { - if (linked->id == PLANE_SPRITE5) + if (linked->id == PLANE_7) plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL; - else if (linked->id == PLANE_SPRITE4) + else if (linked->id == PLANE_6) plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL; - else if (linked->id == PLANE_SPRITE3) + else if (linked->id == PLANE_5) plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL; - else if (linked->id == PLANE_SPRITE2) + else if (linked->id == PLANE_4) plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL; else MISSING_CASE(linked->id); diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h index 5126d0b5ae5d..c4775c99dc83 100644 --- a/drivers/gpu/drm/i915/display/intel_display_limits.h +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h @@ -60,16 +60,23 @@ enum transcoder { * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care. */ enum plane_id { - PLANE_PRIMARY, - PLANE_SPRITE0, - PLANE_SPRITE1, - PLANE_SPRITE2, - PLANE_SPRITE3, - PLANE_SPRITE4, - PLANE_SPRITE5, + /* skl+ universal plane names */ + PLANE_1, + PLANE_2, + PLANE_3, + PLANE_4, + PLANE_5, + PLANE_6, + PLANE_7, + PLANE_CURSOR, I915_MAX_PLANES, + + /* pre-skl plane names */ + PLANE_PRIMARY = PLANE_1, + PLANE_SPRITE0, + PLANE_SPRITE1, }; enum port { diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c index a76b48ebc2d3..4853c4806004 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c +++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c @@ -74,7 +74,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data, * pipe simultaneously. */ if (DISPLAY_VER(dev_priv) >= 9 && - to_intel_plane(plane)->id >= PLANE_SPRITE1 && + to_intel_plane(plane)->id >= PLANE_3 && set->flags & I915_SET_COLORKEY_DESTINATION) return -EINVAL; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 32d10e62b2b9..d99fec8e5233 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -238,9 +238,9 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915) { if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915)) - return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3); + return BIT(PLANE_4) | BIT(PLANE_5); else - return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5); + return BIT(PLANE_6) | BIT(PLANE_7); } bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, @@ -252,7 +252,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, u8 icl_hdr_plane_mask(void) { - return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1); + return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3); } bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id) @@ -2099,7 +2099,7 @@ static bool skl_plane_has_fbc(struct drm_i915_private *i915, if (DISPLAY_VER(i915) >= 20) return icl_is_hdr_plane(i915, plane_id); else - return plane_id == PLANE_PRIMARY; + return plane_id == PLANE_1; } static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv, @@ -2123,7 +2123,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv, if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C) return false; - if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0) + if (plane_id != PLANE_1 && plane_id != PLANE_2) return false; return true; @@ -2331,8 +2331,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915, return pipe != PIPE_C; return pipe != PIPE_C && - (plane_id == PLANE_PRIMARY || - plane_id == PLANE_SPRITE0); + (plane_id == PLANE_1 || plane_id == PLANE_2); } static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, @@ -2350,7 +2349,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915, if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) return false; - return plane_id < PLANE_SPRITE4; + return plane_id < PLANE_6; } static u8 skl_get_plane_caps(struct drm_i915_private *i915, @@ -2439,7 +2438,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, plane->get_hw_state = skl_plane_get_hw_state; plane->check_plane = skl_plane_check; - if (plane_id == PLANE_PRIMARY) { + if (plane_id == PLANE_1) { plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10); plane->async_flip = skl_plane_async_flip; plane->enable_flip_done = skl_plane_enable_flip_done; @@ -2461,7 +2460,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv, else plane_funcs = &skl_plane_funcs; - if (plane_id == PLANE_PRIMARY) + if (plane_id == PLANE_1) plane_type = DRM_PLANE_TYPE_PRIMARY; else plane_type = DRM_PLANE_TYPE_OVERLAY; -- cgit From 9cad70a9401f4d962e1baa9d607a291bfdc8f010 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:11 +0300 Subject: drm/i915: Clean up the cursor register defines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group the cursor register defines such that everything to do with one register is in one place. Also, while we are touching these protect all the macro arguments for good measure. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 52 ++++++++++++------------ 1 file changed, 26 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index c2190af1e9f5..270c26c2e6df 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -9,6 +9,7 @@ #include "intel_display_reg_defs.h" #define _CURACNTR 0x70080 +#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR) /* Old style CUR*CNTR flags (desktop 8xx) */ #define CURSOR_ENABLE REG_BIT(31) #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30) @@ -38,61 +39,60 @@ #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX) #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX) #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX) + #define _CURABASE 0x70084 +#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURABASE) + #define _CURAPOS 0x70088 -#define _CURAPOS_ERLY_TPT 0x7008c +#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS) #define CURSOR_POS_Y_SIGN REG_BIT(31) #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16) #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y)) #define CURSOR_POS_X_SIGN REG_BIT(15) #define CURSOR_POS_X_MASK REG_GENMASK(14, 0) #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x)) + +#define _CURAPOS_ERLY_TPT 0x7008c +#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT) + #define _CURASIZE 0x700a0 /* 845/865 */ +#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE) #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12) #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h)) #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0) #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w)) + #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */ +#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A) #define CUR_FBC_EN REG_BIT(31) #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0) #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h)) + #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */ +#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A) + #define _CURASURFLIVE 0x700ac /* g4x+ */ -#define _CURBCNTR 0x700c0 -#define _CURBBASE 0x700c4 -#define _CURBPOS 0x700c8 - -#define _CURBCNTR_IVB 0x71080 -#define _CURBBASE_IVB 0x71084 -#define _CURBPOS_IVB 0x71088 - -#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) -#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) -#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) -#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) -#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) -#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) -#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) -#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) +#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE) /* skl+ */ #define _CUR_WM_A_0 0x70140 #define _CUR_WM_B_0 0x71140 +#define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4) + #define _CUR_WM_SAGV_A 0x70158 #define _CUR_WM_SAGV_B 0x71158 +#define CUR_WM_SAGV(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) + #define _CUR_WM_SAGV_TRANS_A 0x7015C #define _CUR_WM_SAGV_TRANS_B 0x7115C +#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) + #define _CUR_WM_TRANS_A 0x70168 #define _CUR_WM_TRANS_B 0x71168 -#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0) -#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level))) -#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B) -#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B) -#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) +#define CUR_WM_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_TRANS_A, _CUR_WM_TRANS_B) -/* skl+ */ -#define _CUR_BUF_CFG_A 0x7017c -#define _CUR_BUF_CFG_B 0x7117c -#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) +#define _CUR_BUF_CFG_A 0x7017c +#define _CUR_BUF_CFG_B 0x7117c +#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) #endif /* __INTEL_CURSOR_REGS_H__ */ -- cgit From 199bc8c175d712be1610dcad7f7240ad5c864281 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 20 May 2024 20:14:59 +0300 Subject: drm/i915: Add separate define for SEL_FETCH_CUR_CTL() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split the cursor stuff from the rest of the selective fetch plane registers so that we can collect all cursor registers in intel_cursor_regs.h. Also take the opportunity to rename the registers to match the spec. v2: Pass the correct register offset fpr pipe B (Jani) s/mtl+/tgl+/ as that's where this was introduced Drop the bogus SEL_FETCH_CUR_CTL_ENABLE bit, the contents actually match the normal CUR_CTL register Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240520171459.9661-1-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++--- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +++++ 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index c780ce146131..b44809899502 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane, if (!crtc_state->enable_psr2_sel_fetch) return; - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0); } static void wa_16021440873(struct intel_plane *plane, @@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane, ctl &= ~MCURSOR_MODE_MASK; ctl |= MCURSOR_MODE_64_2B; - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl); + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl); intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe), PIPESRC_HEIGHT(et_y_position)); @@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane, val); } - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), plane_state->ctl); } else { /* Wa_16021440873 */ diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index 270c26c2e6df..e58930ff32ea 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -95,4 +95,9 @@ #define _CUR_BUF_CFG_B 0x7117c #define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) +/* tgl+ */ +#define _SEL_FETCH_CUR_CTL_A 0x70880 +#define _SEL_FETCH_CUR_CTL_B 0x71880 +#define SEL_FETCH_CUR_CTL(pipe) _MMIO_PIPE((pipe), _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_B) + #endif /* __INTEL_CURSOR_REGS_H__ */ -- cgit From 04c09e4b879b225f3747606bcfc97d00d82d800f Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:13 +0300 Subject: drm/i915: Simplify PIPESRC_ERLY_TPT definition MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range. so using _MMIO_TRANS2() for it is not really correct. Also since this is a pipe register, and not present on CHV, the registers will be equally spaced out, so we can use the simpler _MMIO_PIPE() instead of _MMIO_PIPE2(). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 2 +- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index b44809899502..7983cbaf83f7 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -525,7 +525,7 @@ static void wa_16021440873(struct intel_plane *plane, intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl); - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe), + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe), PIPESRC_HEIGHT(et_y_position)); } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d18baeb971bb..f59238d3d484 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2384,7 +2384,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st if (!crtc_state->enable_psr2_su_region_et) return; - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe), + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe), crtc_state->pipe_srcsz_early_tpt); } diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index b6a39926ccb6..23851513054a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -252,8 +252,8 @@ /* PSR2 Early transport */ #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074 - -#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A) +#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 +#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 -- cgit From 0ff7639bb1a6299930b7d66214bc6b0a293d8833 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:14 +0300 Subject: drm/i915: Rename selective fetch plane registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rename the selective fetch plane registers to match the spec. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 +++++----- drivers/gpu/drm/i915/display/skl_universal_plane.c | 12 ++++++------ 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 23851513054a..2a8746bc18dc 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -280,23 +280,23 @@ _SEL_FETCH_PLANE_BASE_A(plane)) #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 -#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ +#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ _SEL_FETCH_PLANE_CTL_1_A - \ _SEL_FETCH_PLANE_BASE_1_A) -#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31) +#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) #define _SEL_FETCH_PLANE_POS_1_A 0x70894 -#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ +#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ _SEL_FETCH_PLANE_POS_1_A - \ _SEL_FETCH_PLANE_BASE_1_A) #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 -#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ +#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ _SEL_FETCH_PLANE_SIZE_1_A - \ _SEL_FETCH_PLANE_BASE_1_A) #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C -#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ +#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ _SEL_FETCH_PLANE_OFFSET_1_A - \ _SEL_FETCH_PLANE_BASE_1_A) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index d99fec8e5233..31127ce0b950 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -705,7 +705,7 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_plane *plane, if (!crtc_state->enable_psr2_sel_fetch) return; - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0); + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0); } static void @@ -1304,7 +1304,7 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane, val = (clip->y1 + plane_state->uapi.dst.y1) << 16; val |= plane_state->uapi.dst.x1; - intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val); + intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val); x = plane_state->view.color_plane[color_plane].x; @@ -1319,13 +1319,13 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane, val = y << 16 | x; - intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id), + intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id), val); /* Sizes are 0 based */ val = (drm_rect_height(clip) - 1) << 16; val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1; - intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val); + intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val); } static void @@ -1414,8 +1414,8 @@ static void icl_plane_update_sel_fetch_arm(struct intel_plane *plane, return; if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), - PLANE_SEL_FETCH_CTL_ENABLE); + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), + SEL_FETCH_PLANE_CTL_ENABLE); else icl_plane_disable_sel_fetch_arm(plane, crtc_state); } -- cgit From 9871927034d177aacc7054e30c74e11fcddf8ee1 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:16 +0300 Subject: drm/i915: Add separate defines for cursor WM/DDB register bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make a more thorough split between universal planes vs. cursors by defining the contents of the cursor WM/DDB registers separately. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cursor.c | 34 ++++++++++++++++++---- drivers/gpu/drm/i915/display/intel_cursor_regs.h | 9 ++++++ drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 +-- drivers/gpu/drm/i915/display/skl_universal_plane.h | 3 -- 4 files changed, 39 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 7983cbaf83f7..cea0cfed569d 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -24,7 +24,6 @@ #include "intel_psr.h" #include "intel_psr_regs.h" #include "intel_vblank.h" -#include "skl_universal_plane.h" #include "skl_watermark.h" #include "gem/i915_gem_object.h" @@ -559,6 +558,29 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane, } } +static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry) +{ + if (!entry->end) + return 0; + + return CUR_BUF_END(entry->end - 1) | + CUR_BUF_START(entry->start); +} + +static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level) +{ + u32 val = 0; + + if (level->enable) + val |= CUR_WM_EN; + if (level->ignore_lines) + val |= CUR_WM_IGNORE_LINES; + val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks); + val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines); + + return val; +} + static void skl_write_cursor_wm(struct intel_plane *plane, const struct intel_crtc_state *crtc_state) { @@ -572,22 +594,22 @@ static void skl_write_cursor_wm(struct intel_plane *plane, for (level = 0; level < i915->display.wm.num_levels; level++) intel_de_write_fw(i915, CUR_WM(pipe, level), - skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); + skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level))); intel_de_write_fw(i915, CUR_WM_TRANS(pipe), - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); + skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id))); if (HAS_HW_SAGV_WM(i915)) { const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id]; intel_de_write_fw(i915, CUR_WM_SAGV(pipe), - skl_plane_wm_reg_val(&wm->sagv.wm0)); + skl_cursor_wm_reg_val(&wm->sagv.wm0)); intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe), - skl_plane_wm_reg_val(&wm->sagv.trans_wm)); + skl_cursor_wm_reg_val(&wm->sagv.trans_wm)); } intel_de_write_fw(i915, CUR_BUF_CFG(pipe), - skl_plane_ddb_reg_val(ddb)); + skl_cursor_ddb_reg_val(ddb)); } /* TODO: split into noarm+arm pair */ diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h index e58930ff32ea..aaa66331063e 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h @@ -78,6 +78,10 @@ #define _CUR_WM_A_0 0x70140 #define _CUR_WM_B_0 0x71140 #define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4) +#define CUR_WM_EN REG_BIT(31) +#define CUR_WM_IGNORE_LINES REG_BIT(30) +#define CUR_WM_LINES_MASK REG_GENMASK(26, 14) +#define CUR_WM_BLOCKS_MASK REG_GENMASK(11, 0) #define _CUR_WM_SAGV_A 0x70158 #define _CUR_WM_SAGV_B 0x71158 @@ -94,6 +98,11 @@ #define _CUR_BUF_CFG_A 0x7017c #define _CUR_BUF_CFG_B 0x7117c #define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B) +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */ +#define CUR_BUF_END_MASK REG_GENMASK(27, 16) +#define CUR_BUF_END(end) REG_FIELD_PREP(CUR_BUF_END_MASK, (end)) +#define CUR_BUF_START_MASK REG_GENMASK(11, 0) +#define CUR_BUF_START(start) REG_FIELD_PREP(CUR_BUF_START_MASK, (start)) /* tgl+ */ #define _SEL_FETCH_CUR_CTL_A 0x70880 diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 31127ce0b950..b7678b8a7f3d 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -622,7 +622,7 @@ static u32 skl_plane_stride(const struct intel_plane_state *plane_state, return stride / skl_plane_stride_mult(fb, color_plane, rotation); } -u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry) +static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry) { if (!entry->end) return 0; @@ -631,7 +631,7 @@ u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry) PLANE_BUF_START(entry->start); } -u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) +static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level) { u32 val = 0; diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h index 8eb4521ee851..541489479135 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h @@ -37,7 +37,4 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv, u8 icl_hdr_plane_mask(void); bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id); -u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry); -u32 skl_plane_wm_reg_val(const struct skl_wm_level *level); - #endif -- cgit From 561608610bca0353b567298ce0e683b517fa872f Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:17 +0300 Subject: drm/i915: Move PIPEGCMAX to intel_color_regs.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PIPEGCMAX was left behind when all other gamma registers moved into intel_color_regs.h. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-9-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_color_regs.h | 5 +++++ drivers/gpu/drm/i915/i915_reg.h | 4 ---- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h index bb99ea533842..61c18b4a7fa5 100644 --- a/drivers/gpu/drm/i915/display/intel_color_regs.h +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h @@ -36,6 +36,11 @@ _CHV_PALETTE_C, _CHV_PALETTE_C) + \ (i) * 4) +/* i965/g4x/vlv/chv */ +#define _PIPEAGCMAX 0x70010 +#define _PIPEBGCMAX 0x71010 +#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ + /* ilk+ palette */ #define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_B 0x4a800 diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 52b029cd3981..f5e8833cc37e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1882,10 +1882,6 @@ #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) -#define _PIPEAGCMAX 0x70010 -#define _PIPEBGCMAX 0x71010 -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ - #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) -- cgit From 514ca6dffb2b76c1593b558527e2c84bd7faa249 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:18 +0300 Subject: drm/i915: Extract i9xx_plane_regs.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocate all pre-skl primary plane register definitions into their own declutter i915_reg.h. Cc: Zhenyu Wang Cc: Zhi Wang Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-10-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 1 + drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 98 +++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_atomic_plane.c | 1 + drivers/gpu/drm/i915/display/intel_color.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 1 + drivers/gpu/drm/i915/display/intel_fbc.c | 1 + drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 + drivers/gpu/drm/i915/gvt/display.c | 1 + drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 + drivers/gpu/drm/i915/gvt/handlers.c | 1 + drivers/gpu/drm/i915/i915_reg.h | 87 +------------------- drivers/gpu/drm/i915/intel_clock_gating.c | 1 + drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 + 13 files changed, 110 insertions(+), 87 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane_regs.h diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index ea4d8ba55ad8..1f05f9184cb2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -10,6 +10,7 @@ #include "i915_reg.h" #include "i9xx_plane.h" +#include "i9xx_plane_regs.h" #include "intel_atomic.h" #include "intel_atomic_plane.h" #include "intel_de.h" diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h new file mode 100644 index 000000000000..0bf2cd42bce7 --- /dev/null +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -0,0 +1,98 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __I9XX_PLANE_REGS_H__ +#define __I9XX_PLANE_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define _DSPAADDR_VLV 0x7017C /* vlv/chv */ +#define _DSPACNTR 0x70180 +#define DISP_ENABLE REG_BIT(31) +#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) +#define DISP_FORMAT_MASK REG_GENMASK(29, 26) +#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) +#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) +#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) +#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) +#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) +#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) +#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) +#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) +#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) +#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) +#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) +#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) +#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) +#define DISP_STEREO_ENABLE REG_BIT(25) +#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ +#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) +#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) +#define DISP_SRC_KEY_ENABLE REG_BIT(22) +#define DISP_LINE_DOUBLE REG_BIT(20) +#define DISP_STEREO_POLARITY_SECOND REG_BIT(18) +#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ +#define DISP_ROTATE_180 REG_BIT(15) +#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ +#define DISP_TILED REG_BIT(10) +#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ +#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ +#define _DSPAADDR 0x70184 +#define _DSPASTRIDE 0x70188 +#define _DSPAPOS 0x7018C /* reserved */ +#define DISP_POS_Y_MASK REG_GENMASK(31, 16) +#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) +#define DISP_POS_X_MASK REG_GENMASK(15, 0) +#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) +#define _DSPASIZE 0x70190 +#define DISP_HEIGHT_MASK REG_GENMASK(31, 16) +#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) +#define DISP_WIDTH_MASK REG_GENMASK(15, 0) +#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) +#define _DSPASURF 0x7019C /* 965+ only */ +#define DISP_ADDR_MASK REG_GENMASK(31, 12) +#define _DSPATILEOFF 0x701A4 /* 965+ only */ +#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) +#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) +#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) +#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) +#define _DSPAOFFSET 0x701A4 /* HSW */ +#define _DSPASURFLIVE 0x701AC +#define _DSPAGAMC 0x701E0 + +#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) +#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) +#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) +#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) +#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) +#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) +#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) +#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) +#define DSPLINOFF(plane) DSPADDR(plane) +#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) +#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) +#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ + +/* CHV pipe B primary plane */ +#define _PRIMPOS_A 0x60a08 +#define PRIM_POS_Y_MASK REG_GENMASK(31, 16) +#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) +#define PRIM_POS_X_MASK REG_GENMASK(15, 0) +#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) +#define _PRIMSIZE_A 0x60a0c +#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) +#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) +#define PRIM_WIDTH_MASK REG_GENMASK(15, 0) +#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) +#define _PRIMCNSTALPHA_A 0x60a10 +#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) +#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) +#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) + +#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) +#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) +#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) + +#endif /* __I9XX_PLANE_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 27224ecdc94c..a2a827070c33 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -40,6 +40,7 @@ #include "i915_config.h" #include "i915_reg.h" +#include "i9xx_plane_regs.h" #include "intel_atomic_plane.h" #include "intel_cdclk.h" #include "intel_display_rps.h" diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index d23163dc64d4..82b155708422 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -22,7 +22,7 @@ * */ -#include "i915_reg.h" +#include "i9xx_plane_regs.h" #include "intel_color.h" #include "intel_color_regs.h" #include "intel_de.h" diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index ee2df655b0ab..1e8e2fd52cf6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -54,6 +54,7 @@ #include "i915_reg.h" #include "i915_utils.h" #include "i9xx_plane.h" +#include "i9xx_plane_regs.h" #include "i9xx_wm.h" #include "intel_atomic.h" #include "intel_atomic_plane.h" diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 50dd8eb9012e..680d7fc39503 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -48,6 +48,7 @@ #include "i915_utils.h" #include "i915_vgpu.h" #include "i915_vma.h" +#include "i9xx_plane_regs.h" #include "intel_cdclk.h" #include "intel_de.h" #include "intel_display_device.h" diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 4be8cb65fb7e..2c315caf2414 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -49,6 +49,7 @@ #include "i915_pvinfo.h" #include "trace.h" +#include "display/i9xx_plane_regs.h" #include "display/intel_display.h" #include "display/intel_sprite_regs.h" #include "gem/i915_gem_context.h" diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 73ea8be0f80b..dafa13ac826b 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -37,6 +37,7 @@ #include "gvt.h" #include "display/bxt_dpio_phy_regs.h" +#include "display/i9xx_plane_regs.h" #include "display/intel_cursor_regs.h" #include "display/intel_display.h" #include "display/intel_dpio_phy.h" diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index e78de423a6c7..521dee39e5fb 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -40,6 +40,7 @@ #include "i915_pvinfo.h" #include "i915_reg.h" +#include "display/i9xx_plane_regs.h" #include "display/intel_cursor_regs.h" #include "display/intel_sprite_regs.h" #include "display/skl_universal_plane_regs.h" diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 6f633035618e..27ef6dfee641 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -42,6 +42,7 @@ #include "i915_pvinfo.h" #include "intel_mchbar_regs.h" #include "display/bxt_dpio_phy_regs.h" +#include "display/i9xx_plane_regs.h" #include "display/intel_cursor_regs.h" #include "display/intel_display_types.h" #include "display/intel_dmc_regs.h" diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f5e8833cc37e..29f69ad8f704 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2260,75 +2260,7 @@ #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) -/* Display A control */ -#define _DSPAADDR_VLV 0x7017C /* vlv/chv */ -#define _DSPACNTR 0x70180 -#define DISP_ENABLE REG_BIT(31) -#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) -#define DISP_FORMAT_MASK REG_GENMASK(29, 26) -#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2) -#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3) -#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4) -#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5) -#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6) -#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7) -#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8) -#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9) -#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10) -#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11) -#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12) -#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14) -#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15) -#define DISP_STEREO_ENABLE REG_BIT(25) -#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */ -#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24) -#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe)) -#define DISP_SRC_KEY_ENABLE REG_BIT(22) -#define DISP_LINE_DOUBLE REG_BIT(20) -#define DISP_STEREO_POLARITY_SECOND REG_BIT(18) -#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ -#define DISP_ROTATE_180 REG_BIT(15) -#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ -#define DISP_TILED REG_BIT(10) -#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ -#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ -#define _DSPAADDR 0x70184 -#define _DSPASTRIDE 0x70188 -#define _DSPAPOS 0x7018C /* reserved */ -#define DISP_POS_Y_MASK REG_GENMASK(31, 16) -#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) -#define DISP_POS_X_MASK REG_GENMASK(15, 0) -#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) -#define _DSPASIZE 0x70190 -#define DISP_HEIGHT_MASK REG_GENMASK(31, 16) -#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) -#define DISP_WIDTH_MASK REG_GENMASK(15, 0) -#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) -#define _DSPASURF 0x7019C /* 965+ only */ -#define DISP_ADDR_MASK REG_GENMASK(31, 12) -#define _DSPATILEOFF 0x701A4 /* 965+ only */ -#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) -#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) -#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) -#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) -#define _DSPAOFFSET 0x701A4 /* HSW */ -#define _DSPASURFLIVE 0x701AC -#define _DSPAGAMC 0x701E0 - -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) -#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) -#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) -#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) -#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) -#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) -#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) -#define DSPLINOFF(plane) DSPADDR(plane) -#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) -#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) -#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ - -/* CHV pipe B blender and primary plane */ +/* CHV pipe B blender */ #define _CHV_BLEND_A 0x60a00 #define CHV_BLEND_MASK REG_GENMASK(31, 30) #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0) @@ -2338,26 +2270,9 @@ #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20) #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) -#define _PRIMPOS_A 0x60a08 -#define PRIM_POS_Y_MASK REG_GENMASK(31, 16) -#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) -#define PRIM_POS_X_MASK REG_GENMASK(15, 0) -#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) -#define _PRIMSIZE_A 0x60a0c -#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) -#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) -#define PRIM_WIDTH_MASK REG_GENMASK(15, 0) -#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) -#define _PRIMCNSTALPHA_A 0x60a10 -#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) -#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) -#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) #define CHV_BLEND(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A) #define CHV_CANVAS(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A) -#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) -#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) -#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) /* Display/Sprite base address macros */ #define DISP_BASEADDR_MASK (0xfffff000) diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 1dc5281b2ade..5c5685ebd49e 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -25,6 +25,7 @@ * */ +#include "display/i9xx_plane_regs.h" #include "display/intel_de.h" #include "display/intel_display.h" #include "display/intel_display_trace.h" diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index b485976976db..2375292292b6 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -4,6 +4,7 @@ */ #include "display/bxt_dpio_phy_regs.h" +#include "display/i9xx_plane_regs.h" #include "display/intel_audio_regs.h" #include "display/intel_backlight_regs.h" #include "display/intel_color_regs.h" -- cgit From c0086b71441d8af3f65a065f582b5e73891c9910 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:19 +0300 Subject: drm/i915: Polish pre-skl primary plane registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group the pre-skl primary plane register definitions sensible, and toss in a few comments to indicate which platforms have what. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-11-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 46 ++++++++++++++++---------- 1 file changed, 29 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 0bf2cd42bce7..929b26faf31e 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -9,7 +9,10 @@ #include "intel_display_reg_defs.h" #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ +#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) + #define _DSPACNTR 0x70180 +#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) #define DISP_ENABLE REG_BIT(31) #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) #define DISP_FORMAT_MASK REG_GENMASK(29, 26) @@ -39,60 +42,69 @@ #define DISP_TILED REG_BIT(10) #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ + #define _DSPAADDR 0x70184 +#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) + +#define _DSPALINOFF 0x70184 +#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) + #define _DSPASTRIDE 0x70188 +#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) + #define _DSPAPOS 0x7018C /* reserved */ +#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) #define DISP_POS_Y_MASK REG_GENMASK(31, 16) #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) #define DISP_POS_X_MASK REG_GENMASK(15, 0) #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) + #define _DSPASIZE 0x70190 +#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) #define DISP_WIDTH_MASK REG_GENMASK(15, 0) #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) + #define _DSPASURF 0x7019C /* 965+ only */ +#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) #define DISP_ADDR_MASK REG_GENMASK(31, 12) + #define _DSPATILEOFF 0x701A4 /* 965+ only */ +#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) + #define _DSPAOFFSET 0x701A4 /* HSW */ +#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) + #define _DSPASURFLIVE 0x701AC -#define _DSPAGAMC 0x701E0 +#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) -#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) -#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) -#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) -#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) -#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) -#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) -#define DSPLINOFF(plane) DSPADDR(plane) -#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) -#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) -#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ +#define _DSPAGAMC 0x701E0 +#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ #define _PRIMPOS_A 0x60a08 +#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) #define PRIM_POS_X_MASK REG_GENMASK(15, 0) #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) + #define _PRIMSIZE_A 0x60a0c +#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) + #define _PRIMCNSTALPHA_A 0x60a10 +#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) -#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) -#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) -#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) - #endif /* __I9XX_PLANE_REGS_H__ */ -- cgit From 48dd4a5e81005d26fdd88fbff439cc91f9992830 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:20 +0300 Subject: drm/i915: Document a few pre-skl primary plane platform dependencies MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add some notes indicating which plane registers/bits are valid for which platforms. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-12-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 929b26faf31e..d74a74d1f29a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -37,53 +37,53 @@ #define DISP_LINE_DOUBLE REG_BIT(20) #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ -#define DISP_ROTATE_180 REG_BIT(15) +#define DISP_ROTATE_180 REG_BIT(15) /* i965+ */ #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ -#define DISP_TILED REG_BIT(10) +#define DISP_TILED REG_BIT(10) /* i965+ */ #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ -#define _DSPAADDR 0x70184 +#define _DSPAADDR 0x70184 /* pre-i965 */ #define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) -#define _DSPALINOFF 0x70184 +#define _DSPALINOFF 0x70184 /* i965+ */ #define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) #define _DSPASTRIDE 0x70188 #define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) -#define _DSPAPOS 0x7018C /* reserved */ +#define _DSPAPOS 0x7018C /* pre-g4x */ #define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) #define DISP_POS_Y_MASK REG_GENMASK(31, 16) #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) #define DISP_POS_X_MASK REG_GENMASK(15, 0) #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) -#define _DSPASIZE 0x70190 +#define _DSPASIZE 0x70190 /* pre-g4x */ #define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) #define DISP_WIDTH_MASK REG_GENMASK(15, 0) #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) -#define _DSPASURF 0x7019C /* 965+ only */ +#define _DSPASURF 0x7019C /* i965+ */ #define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) #define DISP_ADDR_MASK REG_GENMASK(31, 12) -#define _DSPATILEOFF 0x701A4 /* 965+ only */ +#define _DSPATILEOFF 0x701A4 /* i965+ */ #define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) -#define _DSPAOFFSET 0x701A4 /* HSW */ +#define _DSPAOFFSET 0x701A4 /* hsw+ */ #define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) -#define _DSPASURFLIVE 0x701AC +#define _DSPASURFLIVE 0x701AC /* g4x+ */ #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) -#define _DSPAGAMC 0x701E0 +#define _DSPAGAMC 0x701E0 /* pre-g4x */ #define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ -- cgit From ddb904d6d08730bd54bc842a2d85fcfcfa27aff5 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:21 +0300 Subject: drm/i915: Polish sprite plane register definitions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Group the sprite plane register definitions such that everything to do with the same register is in one place. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-13-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_sprite_regs.h | 231 +++++++++++++---------- 1 file changed, 134 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h index bb67705652b2..c27adbaf0f00 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h @@ -7,6 +7,8 @@ #include "intel_display_reg_defs.h" #define _DVSACNTR 0x72180 +#define _DVSBCNTR 0x73180 +#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) #define DVS_ENABLE REG_BIT(31) #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) @@ -28,31 +30,67 @@ #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) #define DVS_TILED REG_BIT(10) #define DVS_DEST_KEY REG_BIT(2) + #define _DVSALINOFF 0x72184 +#define _DVSBLINOFF 0x73184 +#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) + #define _DVSASTRIDE 0x72188 +#define _DVSBSTRIDE 0x73188 +#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) + #define _DVSAPOS 0x7218c +#define _DVSBPOS 0x7318c +#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) #define DVS_POS_Y_MASK REG_GENMASK(31, 16) #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) #define DVS_POS_X_MASK REG_GENMASK(15, 0) #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) + #define _DVSASIZE 0x72190 +#define _DVSBSIZE 0x73190 +#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) #define DVS_HEIGHT_MASK REG_GENMASK(31, 16) #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) #define DVS_WIDTH_MASK REG_GENMASK(15, 0) #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) + #define _DVSAKEYVAL 0x72194 +#define _DVSBKEYVAL 0x73194 +#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) + #define _DVSAKEYMSK 0x72198 +#define _DVSBKEYMSK 0x73198 +#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) + #define _DVSASURF 0x7219c +#define _DVSBSURF 0x7319c +#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) #define DVS_ADDR_MASK REG_GENMASK(31, 12) + #define _DVSAKEYMAXVAL 0x721a0 +#define _DVSBKEYMAXVAL 0x731a0 +#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) + #define _DVSATILEOFF 0x721a4 +#define _DVSBTILEOFF 0x731a4 +#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) + #define _DVSASURFLIVE 0x721ac +#define _DVSBSURFLIVE 0x731ac +#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) + #define _DVSAGAMC_G4X 0x721e0 /* g4x */ +#define _DVSBGAMC_G4X 0x731e0 /* g4x */ +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ + #define _DVSASCALE 0x72204 +#define _DVSBSCALE 0x73204 +#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) #define DVS_SCALE_ENABLE REG_BIT(31) #define DVS_FILTER_MASK REG_GENMASK(30, 29) #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) @@ -64,42 +102,18 @@ #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) -#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ -#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ -#define _DVSBCNTR 0x73180 -#define _DVSBLINOFF 0x73184 -#define _DVSBSTRIDE 0x73188 -#define _DVSBPOS 0x7318c -#define _DVSBSIZE 0x73190 -#define _DVSBKEYVAL 0x73194 -#define _DVSBKEYMSK 0x73198 -#define _DVSBSURF 0x7319c -#define _DVSBKEYMAXVAL 0x731a0 -#define _DVSBTILEOFF 0x731a4 -#define _DVSBSURFLIVE 0x731ac -#define _DVSBGAMC_G4X 0x731e0 /* g4x */ -#define _DVSBSCALE 0x73204 +#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ -#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ - -#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) -#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) -#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) -#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) -#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) -#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) -#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) -#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) -#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) -#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) -#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) -#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) -#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ + +#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ +#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ #define _SPRA_CTL 0x70280 +#define _SPRB_CTL 0x71280 +#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) #define SPRITE_ENABLE REG_BIT(31) #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) @@ -125,31 +139,67 @@ #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) #define SPRITE_TILED REG_BIT(10) #define SPRITE_DEST_KEY REG_BIT(2) + #define _SPRA_LINOFF 0x70284 +#define _SPRB_LINOFF 0x71284 +#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) + #define _SPRA_STRIDE 0x70288 +#define _SPRB_STRIDE 0x71288 +#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) + #define _SPRA_POS 0x7028c +#define _SPRB_POS 0x7128c +#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) #define SPRITE_POS_X_MASK REG_GENMASK(15, 0) #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) + #define _SPRA_SIZE 0x70290 +#define _SPRB_SIZE 0x71290 +#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) + #define _SPRA_KEYVAL 0x70294 +#define _SPRB_KEYVAL 0x71294 +#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) + #define _SPRA_KEYMSK 0x70298 +#define _SPRB_KEYMSK 0x71298 +#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) + #define _SPRA_SURF 0x7029c +#define _SPRB_SURF 0x7129c +#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) #define SPRITE_ADDR_MASK REG_GENMASK(31, 12) + #define _SPRA_KEYMAX 0x702a0 +#define _SPRB_KEYMAX 0x712a0 +#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) + #define _SPRA_TILEOFF 0x702a4 +#define _SPRB_TILEOFF 0x712a4 +#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) + #define _SPRA_OFFSET 0x702a4 +#define _SPRB_OFFSET 0x712a4 +#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) + #define _SPRA_SURFLIVE 0x702ac +#define _SPRB_SURFLIVE 0x712ac +#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) + #define _SPRA_SCALE 0x70304 +#define _SPRB_SCALE 0x71304 +#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) #define SPRITE_SCALE_ENABLE REG_BIT(31) #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) @@ -161,45 +211,27 @@ #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) -#define _SPRA_GAMC 0x70400 -#define _SPRA_GAMC16 0x70440 -#define _SPRA_GAMC17 0x7044c -#define _SPRB_CTL 0x71280 -#define _SPRB_LINOFF 0x71284 -#define _SPRB_STRIDE 0x71288 -#define _SPRB_POS 0x7128c -#define _SPRB_SIZE 0x71290 -#define _SPRB_KEYVAL 0x71294 -#define _SPRB_KEYMSK 0x71298 -#define _SPRB_SURF 0x7129c -#define _SPRB_KEYMAX 0x712a0 -#define _SPRB_TILEOFF 0x712a4 -#define _SPRB_OFFSET 0x712a4 -#define _SPRB_SURFLIVE 0x712ac -#define _SPRB_SCALE 0x71304 +#define _SPRA_GAMC 0x70400 #define _SPRB_GAMC 0x71400 -#define _SPRB_GAMC16 0x71440 -#define _SPRB_GAMC17 0x7144c - -#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) -#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) -#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) -#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) -#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) -#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) -#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) -#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) -#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) -#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) -#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) -#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ + +#define _SPRA_GAMC16 0x70440 +#define _SPRB_GAMC16 0x71440 #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ + +#define _SPRA_GAMC17 0x7044c +#define _SPRB_GAMC17 0x7144c #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ -#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) + +#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ + _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) +#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ + _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) +#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) +#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) #define SP_ENABLE REG_BIT(31) #define SP_PIPE_GAMMA_ENABLE REG_BIT(30) #define SP_FORMAT_MASK REG_GENMASK(29, 26) @@ -225,80 +257,85 @@ #define SP_ROTATE_180 REG_BIT(15) #define SP_TILED REG_BIT(10) #define SP_MIRROR REG_BIT(8) /* CHV pipe B */ + #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) +#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) +#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) + #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) +#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) +#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) + #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) +#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) +#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) #define SP_POS_Y_MASK REG_GENMASK(31, 16) #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) #define SP_POS_X_MASK REG_GENMASK(15, 0) #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) + #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) +#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) +#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) #define SP_HEIGHT_MASK REG_GENMASK(31, 16) #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) #define SP_WIDTH_MASK REG_GENMASK(15, 0) #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) + #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) +#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) +#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) + #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) +#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) +#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) + #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) +#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) +#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) #define SP_ADDR_MASK REG_GENMASK(31, 12) + #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) +#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) +#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) + #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) +#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) +#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) #define SP_OFFSET_X_MASK REG_GENMASK(15, 0) #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) + #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) +#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) +#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) #define SP_CONST_ALPHA_ENABLE REG_BIT(31) #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) + #define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac) +#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac) +#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE) + #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) +#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) +#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) #define SP_CONTRAST_MASK REG_GENMASK(26, 18) #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ + #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) +#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) +#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) #define SP_SH_SIN_MASK REG_GENMASK(26, 16) #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ #define SP_SH_COS_MASK REG_GENMASK(9, 0) #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ -#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) -#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) -#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) -#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) -#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) -#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) -#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) -#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) -#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) -#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) -#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) -#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) -#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac) -#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) -#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) +#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) - -#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ - _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) -#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ - _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) - -#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) -#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) -#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) -#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) -#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) -#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) -#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) -#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) -#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) -#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) -#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) -#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE) -#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) -#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ /* -- cgit From a9940ce97d1dc5fe8e6b2f607e9da62073d5bca2 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:22 +0300 Subject: drm/i915: Document which platforms use which sprite registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Note which sprite registers are valid for which platforms. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-14-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_sprite_regs.h | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h index c27adbaf0f00..73021e3ced6d 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h @@ -6,6 +6,7 @@ #include "intel_display_reg_defs.h" +/* g4x/ilk/snb video sprite */ #define _DVSACNTR 0x72180 #define _DVSBCNTR 0x73180 #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) @@ -111,6 +112,7 @@ #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ +/* ivb/hsw/bdw sprite */ #define _SPRA_CTL 0x70280 #define _SPRB_CTL 0x71280 #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) @@ -140,8 +142,8 @@ #define SPRITE_TILED REG_BIT(10) #define SPRITE_DEST_KEY REG_BIT(2) -#define _SPRA_LINOFF 0x70284 -#define _SPRB_LINOFF 0x71284 +#define _SPRA_LINOFF 0x70284 /* ivb */ +#define _SPRB_LINOFF 0x71284 /* ivb */ #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) #define _SPRA_STRIDE 0x70288 @@ -181,24 +183,24 @@ #define _SPRB_KEYMAX 0x712a0 #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) -#define _SPRA_TILEOFF 0x702a4 -#define _SPRB_TILEOFF 0x712a4 +#define _SPRA_TILEOFF 0x702a4 /* ivb */ +#define _SPRB_TILEOFF 0x712a4 /* ivb */ #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) -#define _SPRA_OFFSET 0x702a4 -#define _SPRB_OFFSET 0x712a4 +#define _SPRA_OFFSET 0x702a4 /* hsw/bdw */ +#define _SPRB_OFFSET 0x712a4 /* hsw/bdw */ #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) #define _SPRA_SURFLIVE 0x702ac #define _SPRB_SURFLIVE 0x712ac #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) -#define _SPRA_SCALE 0x70304 -#define _SPRB_SCALE 0x71304 +#define _SPRA_SCALE 0x70304 /* ivb */ +#define _SPRB_SCALE 0x71304 /* ivb */ #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) #define SPRITE_SCALE_ENABLE REG_BIT(31) #define SPRITE_FILTER_MASK REG_GENMASK(30, 29) @@ -224,6 +226,7 @@ #define _SPRB_GAMC17 0x7144c #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ +/* vlv/chv sprite */ #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ -- cgit From 4bfa8a140db33599e666400fe4007d27fbacc96f Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 16 May 2024 16:56:15 +0300 Subject: drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of that huge _PICK() let's use PICK_EVEN_2RANGES() for the SEL_FETCH_PLANE registers. A bit more tedious to have to define 8 raw register offsets for everything, but perhaps a bit easier to understand since we use a standard mechanism now instead of hand rolling the arithmetic. Also bloat-o-meter says: add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-326 (-326) Function old new delta icl_plane_update_arm 510 446 -64 icl_plane_disable_sel_fetch_arm.isra 158 54 -104 icl_plane_update_noarm 1898 1740 -158 Total: Before=2574502, After=2574176, chg -0.01% v2: s/mtl+/tgl+/ comments to reflect actual reality Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240516135622.3498-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr_regs.h | 45 -------------- .../drm/i915/display/skl_universal_plane_regs.h | 72 ++++++++++++++++++++++ 2 files changed, 72 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 2a8746bc18dc..1e503209da09 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -255,51 +255,6 @@ #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074 #define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B) -#define _SEL_FETCH_PLANE_BASE_1_A 0x70890 -#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 -#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0 -#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0 -#define _SEL_FETCH_PLANE_BASE_5_A 0x70920 -#define _SEL_FETCH_PLANE_BASE_6_A 0x70940 -#define _SEL_FETCH_PLANE_BASE_7_A 0x70960 -#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880 -#define _SEL_FETCH_PLANE_BASE_1_B 0x71890 - -#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \ - _SEL_FETCH_PLANE_BASE_1_A, \ - _SEL_FETCH_PLANE_BASE_2_A, \ - _SEL_FETCH_PLANE_BASE_3_A, \ - _SEL_FETCH_PLANE_BASE_4_A, \ - _SEL_FETCH_PLANE_BASE_5_A, \ - _SEL_FETCH_PLANE_BASE_6_A, \ - _SEL_FETCH_PLANE_BASE_7_A, \ - _SEL_FETCH_PLANE_BASE_CUR_A) -#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B) -#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \ - _SEL_FETCH_PLANE_BASE_1_A + \ - _SEL_FETCH_PLANE_BASE_A(plane)) - -#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 -#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ - _SEL_FETCH_PLANE_CTL_1_A - \ - _SEL_FETCH_PLANE_BASE_1_A) -#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) - -#define _SEL_FETCH_PLANE_POS_1_A 0x70894 -#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ - _SEL_FETCH_PLANE_POS_1_A - \ - _SEL_FETCH_PLANE_BASE_1_A) - -#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 -#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ - _SEL_FETCH_PLANE_SIZE_1_A - \ - _SEL_FETCH_PLANE_BASE_1_A) - -#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C -#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \ - _SEL_FETCH_PLANE_OFFSET_1_A - \ - _SEL_FETCH_PLANE_BASE_1_A) - #define _ALPM_CTL_A 0x60950 #define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A) #define ALPM_CTL_ALPM_ENABLE REG_BIT(31) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index cb3bdd71b6b2..9904ecc54128 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -17,6 +17,17 @@ #define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \ _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b))) +#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ + _PICK_EVEN_2RANGES((plane), PLANE_5, \ + _PIPE((pipe), (reg_1_a), (reg_1_b)), \ + _PIPE((pipe), (reg_2_a), (reg_2_b)), \ + _PIPE((pipe), (reg_5_a), (reg_5_b)), \ + _PIPE((pipe), (reg_6_a), (reg_6_b))) +#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \ + _MMIO(_SEL_FETCH((pipe), (plane), \ + (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b), \ + (reg_5_a), (reg_5_b), (reg_6_a), (reg_6_b))) + #define _PLANE_CTL_1_A 0x70180 #define _PLANE_CTL_2_A 0x70280 #define _PLANE_CTL_1_B 0x71180 @@ -367,4 +378,65 @@ #define PLANE_BUF_START_MASK REG_GENMASK(11, 0) #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start)) +/* tgl+ */ +#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 +#define _SEL_FETCH_PLANE_CTL_2_A 0x708b0 +#define _SEL_FETCH_PLANE_CTL_5_A 0x70920 +#define _SEL_FETCH_PLANE_CTL_6_A 0x70940 +#define _SEL_FETCH_PLANE_CTL_1_B 0x71890 +#define _SEL_FETCH_PLANE_CTL_2_B 0x718b0 +#define _SEL_FETCH_PLANE_CTL_5_B 0x71920 +#define _SEL_FETCH_PLANE_CTL_6_B 0x71940 +#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ + _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \ + _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \ + _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \ + _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B) +#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31) + +/* tgl+ */ +#define _SEL_FETCH_PLANE_POS_1_A 0x70894 +#define _SEL_FETCH_PLANE_POS_2_A 0x708b4 +#define _SEL_FETCH_PLANE_POS_5_A 0x70924 +#define _SEL_FETCH_PLANE_POS_6_A 0x70944 +#define _SEL_FETCH_PLANE_POS_1_B 0x71894 +#define _SEL_FETCH_PLANE_POS_2_B 0x718b4 +#define _SEL_FETCH_PLANE_POS_5_B 0x71924 +#define _SEL_FETCH_PLANE_POS_6_B 0x71944 +#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ + _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ + _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ + _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ + _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B) + +/* tgl+ */ +#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 +#define _SEL_FETCH_PLANE_SIZE_2_A 0x708b8 +#define _SEL_FETCH_PLANE_SIZE_5_A 0x70928 +#define _SEL_FETCH_PLANE_SIZE_6_A 0x70948 +#define _SEL_FETCH_PLANE_SIZE_1_B 0x71898 +#define _SEL_FETCH_PLANE_SIZE_2_B 0x718b8 +#define _SEL_FETCH_PLANE_SIZE_5_B 0x71928 +#define _SEL_FETCH_PLANE_SIZE_6_B 0x71948 +#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ + _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ + _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ + _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ + _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B) + +/* tgl+ */ +#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089c +#define _SEL_FETCH_PLANE_OFFSET_2_A 0x708bc +#define _SEL_FETCH_PLANE_OFFSET_5_A 0x7092c +#define _SEL_FETCH_PLANE_OFFSET_6_A 0x7094c +#define _SEL_FETCH_PLANE_OFFSET_1_B 0x7189c +#define _SEL_FETCH_PLANE_OFFSET_2_B 0x718bc +#define _SEL_FETCH_PLANE_OFFSET_5_B 0x7192c +#define _SEL_FETCH_PLANE_OFFSET_6_B 0x7194c +#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ + _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ + _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ + _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ + _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B) + #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */ -- cgit From ee6af5de1cf438cbf4f82d6d7c453daa47dcaff9 Mon Sep 17 00:00:00 2001 From: José Roberto de Souza Date: Wed, 22 May 2024 13:12:03 -0700 Subject: drm/xe: Add process name to devcoredump MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Process name help us track what application caused the gpug hang, this is crucial when running several applications at the same time. v2: - handle Xe KMD exec_queues without VM v3: - use get_pid_task() (suggested by Nirmoy) Cc: Rodrigo Vivi Cc: Nirmoy Das Reviewed-by: Nirmoy Das Signed-off-by: José Roberto de Souza Link: https://patchwork.freedesktop.org/patch/msgid/20240522201203.145403-1-jose.souza@intel.com --- drivers/gpu/drm/xe/xe_devcoredump.c | 13 +++++++++++++ drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 ++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c index 3d7980232be1..7602cc1399e7 100644 --- a/drivers/gpu/drm/xe/xe_devcoredump.c +++ b/drivers/gpu/drm/xe/xe_devcoredump.c @@ -110,6 +110,7 @@ static ssize_t xe_devcoredump_read(char *buffer, loff_t offset, drm_printf(&p, "Snapshot time: %lld.%09ld\n", ts.tv_sec, ts.tv_nsec); ts = ktime_to_timespec64(ss->boot_time); drm_printf(&p, "Uptime: %lld.%09ld\n", ts.tv_sec, ts.tv_nsec); + drm_printf(&p, "Process: %s\n", ss->process_name); xe_device_snapshot_print(xe, &p); drm_printf(&p, "\n**** GuC CT ****\n"); @@ -166,12 +167,24 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump, enum xe_hw_engine_id id; u32 adj_logical_mask = q->logical_mask; u32 width_mask = (0x1 << q->width) - 1; + const char *process_name = "no process"; + struct task_struct *task = NULL; + int i; bool cookie; ss->snapshot_time = ktime_get_real(); ss->boot_time = ktime_get_boottime(); + if (q->vm) { + task = get_pid_task(q->vm->xef->drm->pid, PIDTYPE_PID); + if (task) + process_name = task->comm; + } + snprintf(ss->process_name, sizeof(ss->process_name), process_name); + if (task) + put_task_struct(task); + ss->gt = q->gt; INIT_WORK(&ss->work, xe_devcoredump_deferred_snap_work); diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h index 6f654b63c7f1..923cdf72a816 100644 --- a/drivers/gpu/drm/xe/xe_devcoredump_types.h +++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h @@ -26,6 +26,8 @@ struct xe_devcoredump_snapshot { ktime_t snapshot_time; /** @boot_time: Relative boot time so the uptime can be calculated. */ ktime_t boot_time; + /** @process_name: Name of process that triggered this gpu hang */ + char process_name[TASK_COMM_LEN]; /** @gt: Affected GT, used by forcewake for delayed capture */ struct xe_gt *gt; -- cgit From 2468c0dd01d1b911b9d8ae6c13b8ba28d1e01bb6 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:29 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPADDR_VLV MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPADDR_VLV register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/1d9be6b1eedd9240468a89cd3a10e8513caa33b1.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 1f05f9184cb2..4636523d7948 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -577,7 +577,7 @@ vlv_primary_async_flip(struct intel_plane *plane, u32 dspaddr_offset = plane_state->view.color_plane[0].offset; enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPADDR_VLV(i9xx_plane), + intel_de_write_fw(dev_priv, DSPADDR_VLV(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index d74a74d1f29a..926da106f1a2 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -9,7 +9,7 @@ #include "intel_display_reg_defs.h" #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) +#define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) #define _DSPACNTR 0x70180 #define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) -- cgit From be30c827e16e5527644f3126ceb050cb60301a0f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:30 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPCNTR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPCNTR register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/d9434a718658d7dc6dba1e8a54f80cd1503d0b33.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 10 +++++----- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/display/intel_color.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/gvt/display.c | 4 ++-- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/intel_clock_gating.c | 3 ++- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 10 files changed, 21 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 4636523d7948..ceb0a969357f 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -496,7 +496,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, * disabled. Try to make the plane enable atomic by writing * the control register just before the surface register. */ - intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); if (DISPLAY_VER(dev_priv) >= 4) intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), @@ -539,7 +539,7 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane, */ dspcntr = i9xx_plane_ctl_crtc(crtc_state); - intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); if (DISPLAY_VER(dev_priv) >= 4) intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); @@ -561,7 +561,7 @@ g4x_primary_async_flip(struct intel_plane *plane, if (async_flip) dspcntr |= DISP_ASYNC_FLIP; - intel_de_write_fw(dev_priv, DSPCNTR(i9xx_plane), dspcntr); + intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); @@ -685,7 +685,7 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane, if (!wakeref) return false; - val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); + val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); ret = val & DISP_ENABLE; @@ -1012,7 +1012,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->dev = dev; - val = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); + val = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); if (DISPLAY_VER(dev_priv) >= 4) { if (val & DISP_TILED) { diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 926da106f1a2..d483569e4147 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -12,7 +12,7 @@ #define DSPADDR_VLV(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) #define _DSPACNTR 0x70180 -#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) +#define DSPCNTR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) #define DISP_ENABLE REG_BIT(31) #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30) #define DISP_FORMAT_MASK REG_GENMASK(29, 26) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 82b155708422..a83f41ee6834 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1038,7 +1038,7 @@ static void i9xx_get_config(struct intel_crtc_state *crtc_state) enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; u32 tmp; - tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane)); + tmp = intel_de_read(dev_priv, DSPCNTR(dev_priv, i9xx_plane)); if (tmp & DISP_PIPE_GAMMA_ENABLE) crtc_state->gamma_enable = true; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1e8e2fd52cf6..58a4060f90b4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -8233,11 +8233,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) pipe_name(pipe)); drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE); + intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_A)) & DISP_ENABLE); drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE); + intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_B)) & DISP_ENABLE); drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE); + intel_de_read(dev_priv, DSPCNTR(dev_priv, PLANE_C)) & DISP_ENABLE); drm_WARN_ON(&dev_priv->drm, intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_A)) & MCURSOR_MODE_MASK); drm_WARN_ON(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 2c315caf2414..3b6529a6501b 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1315,7 +1315,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); if (info->plane == PLANE_A) { - info->ctrl_reg = DSPCNTR(info->pipe); + info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); info->stride_reg = DSPSTRIDE(info->pipe); info->surf_reg = DSPSURF(info->pipe); } else if (info->plane == PLANE_B) { @@ -1381,7 +1381,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, info->surf_val = (dword2 & GENMASK(31, 12)) >> 12; info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); - info->ctrl_reg = DSPCNTR(info->pipe); + info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); info->stride_reg = DSPSTRIDE(info->pipe); info->surf_reg = DSPSURF(info->pipe); diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index dafa13ac826b..eaa92d392189 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -193,7 +193,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) for_each_pipe(dev_priv, pipe) { vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &= ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); - vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; + vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; @@ -504,7 +504,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) /* Disable Primary/Sprite/Cursor plane */ for_each_pipe(dev_priv, pipe) { - vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISP_ENABLE; + vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) &= ~MCURSOR_MODE_MASK; vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 521dee39e5fb..48e3b6d8ed98 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -217,7 +217,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, if (pipe >= I915_MAX_PIPES) return -ENODEV; - val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); + val = vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)); plane->enabled = !!(val & DISP_ENABLE); if (!plane->enabled) return -ENODEV; diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 27ef6dfee641..56fb606b4a3d 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1022,7 +1022,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; - if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) + if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP) intel_vgpu_trigger_virtual_event(vgpu, event); else set_bit(event, vgpu->irq.flip_done_event[pipe]); diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 5c5685ebd49e..59d50195c144 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -138,7 +138,8 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) enum pipe pipe; for_each_pipe(dev_priv, pipe) { - intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(pipe), 0, DISP_TRICKLE_FEED_DISABLE); + intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(dev_priv, pipe), + 0, DISP_TRICKLE_FEED_DISABLE); intel_uncore_rmw(&dev_priv->uncore, DSPSURF(pipe), 0, 0); intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe)); diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 2375292292b6..909823d7ed1b 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -165,7 +165,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(_MMIO(0x70094)); MMIO_D(_MMIO(0x70098)); MMIO_D(_MMIO(0x7009c)); - MMIO_D(DSPCNTR(PIPE_A)); + MMIO_D(DSPCNTR(dev_priv, PIPE_A)); MMIO_D(DSPADDR(PIPE_A)); MMIO_D(DSPSTRIDE(PIPE_A)); MMIO_D(DSPPOS(PIPE_A)); @@ -174,7 +174,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPOFFSET(PIPE_A)); MMIO_D(DSPSURFLIVE(PIPE_A)); MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); - MMIO_D(DSPCNTR(PIPE_B)); + MMIO_D(DSPCNTR(dev_priv, PIPE_B)); MMIO_D(DSPADDR(PIPE_B)); MMIO_D(DSPSTRIDE(PIPE_B)); MMIO_D(DSPPOS(PIPE_B)); @@ -183,7 +183,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPOFFSET(PIPE_B)); MMIO_D(DSPSURFLIVE(PIPE_B)); MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); - MMIO_D(DSPCNTR(PIPE_C)); + MMIO_D(DSPCNTR(dev_priv, PIPE_C)); MMIO_D(DSPADDR(PIPE_C)); MMIO_D(DSPSTRIDE(PIPE_C)); MMIO_D(DSPPOS(PIPE_C)); -- cgit From c09b5ddb6e21e839f27daac6ca45f27bb5f2f45d Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:31 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPADDR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPADDR register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/777d4189c18c16392015dd2770f5c56d94bb88a9.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 8 ++++---- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++-- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index ceb0a969357f..79280fe2662d 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -502,7 +502,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else - intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), + intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -544,7 +544,7 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane, if (DISPLAY_VER(dev_priv) >= 4) intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); else - intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0); } static void @@ -1045,7 +1045,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; } else { offset = 0; - base = intel_de_read(dev_priv, DSPADDR(i9xx_plane)); + base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane)); } plane_config->base = base; @@ -1096,7 +1096,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, if (DISPLAY_VER(dev_priv) >= 4) intel_de_write(dev_priv, DSPSURF(i9xx_plane), base); else - intel_de_write(dev_priv, DSPADDR(i9xx_plane), base); + intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base); return true; } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index d483569e4147..a68d7b228187 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -44,7 +44,7 @@ #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ #define _DSPAADDR 0x70184 /* pre-i965 */ -#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) +#define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) #define _DSPALINOFF 0x70184 /* i965+ */ #define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 680d7fc39503..f46e01cad053 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -327,8 +327,8 @@ static void i8xx_fbc_nuke(struct intel_fbc *fbc) enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; struct drm_i915_private *dev_priv = fbc->i915; - intel_de_write_fw(dev_priv, DSPADDR(i9xx_plane), - intel_de_read_fw(dev_priv, DSPADDR(i9xx_plane))); + intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), + intel_de_read_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane))); } static void i8xx_fbc_program_cfb(struct intel_fbc *fbc) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 909823d7ed1b..944765fe22e7 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -166,7 +166,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(_MMIO(0x70098)); MMIO_D(_MMIO(0x7009c)); MMIO_D(DSPCNTR(dev_priv, PIPE_A)); - MMIO_D(DSPADDR(PIPE_A)); + MMIO_D(DSPADDR(dev_priv, PIPE_A)); MMIO_D(DSPSTRIDE(PIPE_A)); MMIO_D(DSPPOS(PIPE_A)); MMIO_D(DSPSIZE(PIPE_A)); @@ -175,7 +175,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSURFLIVE(PIPE_A)); MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_B)); - MMIO_D(DSPADDR(PIPE_B)); + MMIO_D(DSPADDR(dev_priv, PIPE_B)); MMIO_D(DSPSTRIDE(PIPE_B)); MMIO_D(DSPPOS(PIPE_B)); MMIO_D(DSPSIZE(PIPE_B)); @@ -184,7 +184,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSURFLIVE(PIPE_B)); MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_C)); - MMIO_D(DSPADDR(PIPE_C)); + MMIO_D(DSPADDR(dev_priv, PIPE_C)); MMIO_D(DSPSTRIDE(PIPE_C)); MMIO_D(DSPPOS(PIPE_C)); MMIO_D(DSPSIZE(PIPE_C)); -- cgit From 26d0ecc758accce04baa844723be8935f9d516ee Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:32 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPLINOFF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPLINOFF register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/922b6b0795787b335bd3d5b0541bd30dc2c19dd5.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++-- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 79280fe2662d..ba76c952a656 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -485,7 +485,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); } else if (DISPLAY_VER(dev_priv) >= 4) { - intel_de_write_fw(dev_priv, DSPLINOFF(i9xx_plane), + intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane), linear_offset); intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); @@ -1041,7 +1041,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, DSPTILEOFF(i9xx_plane)); else offset = intel_de_read(dev_priv, - DSPLINOFF(i9xx_plane)); + DSPLINOFF(dev_priv, i9xx_plane)); base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; } else { offset = 0; diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index a68d7b228187..e222c0333d19 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -47,7 +47,7 @@ #define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) #define _DSPALINOFF 0x70184 /* i965+ */ -#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) +#define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) #define _DSPASTRIDE 0x70188 #define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) -- cgit From cd962cdb33a799a37d4ade1af023a9edf2a44a94 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:33 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPSTRIDE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSTRIDE register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/4067b3009076492d05e80ae994f9a7bd29b56b2e.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++-- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index ba76c952a656..34760ecd5d34 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -423,7 +423,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, struct drm_i915_private *dev_priv = to_i915(plane->base.dev); enum i9xx_plane_id i9xx_plane = plane->i9xx_plane; - intel_de_write_fw(dev_priv, DSPSTRIDE(i9xx_plane), + intel_de_write_fw(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane), plane_state->view.color_plane[0].mapping_stride); if (DISPLAY_VER(dev_priv) < 4) { @@ -1055,7 +1055,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; - val = intel_de_read(dev_priv, DSPSTRIDE(i9xx_plane)); + val = intel_de_read(dev_priv, DSPSTRIDE(dev_priv, i9xx_plane)); fb->pitches[0] = val & 0xffffffc0; aligned_height = intel_fb_align_height(fb, 0, fb->height); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index e222c0333d19..049114620d93 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -50,7 +50,7 @@ #define DSPLINOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF) #define _DSPASTRIDE 0x70188 -#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) +#define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) #define _DSPAPOS 0x7018C /* pre-g4x */ #define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 3b6529a6501b..7072d14d86cf 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1316,7 +1316,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, if (info->plane == PLANE_A) { info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); - info->stride_reg = DSPSTRIDE(info->pipe); + info->stride_reg = DSPSTRIDE(dev_priv, info->pipe); info->surf_reg = DSPSURF(info->pipe); } else if (info->plane == PLANE_B) { info->ctrl_reg = SPRCTL(info->pipe); @@ -1382,7 +1382,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, info->async_flip = ((dword2 & GENMASK(1, 0)) == 0x1); info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); - info->stride_reg = DSPSTRIDE(info->pipe); + info->stride_reg = DSPSTRIDE(dev_priv, info->pipe); info->surf_reg = DSPSURF(info->pipe); return 0; diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 48e3b6d8ed98..cf1cff3d1c4f 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -155,7 +155,7 @@ static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, { struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; - u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask; + u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(dev_priv, pipe)) & stride_mask; u32 stride = stride_reg; if (GRAPHICS_VER(dev_priv) >= 9) { diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 944765fe22e7..02c5dafc0c93 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -167,7 +167,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(_MMIO(0x7009c)); MMIO_D(DSPCNTR(dev_priv, PIPE_A)); MMIO_D(DSPADDR(dev_priv, PIPE_A)); - MMIO_D(DSPSTRIDE(PIPE_A)); + MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); MMIO_D(DSPPOS(PIPE_A)); MMIO_D(DSPSIZE(PIPE_A)); MMIO_D(DSPSURF(PIPE_A)); @@ -176,7 +176,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_B)); MMIO_D(DSPADDR(dev_priv, PIPE_B)); - MMIO_D(DSPSTRIDE(PIPE_B)); + MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); MMIO_D(DSPPOS(PIPE_B)); MMIO_D(DSPSIZE(PIPE_B)); MMIO_D(DSPSURF(PIPE_B)); @@ -185,7 +185,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_C)); MMIO_D(DSPADDR(dev_priv, PIPE_C)); - MMIO_D(DSPSTRIDE(PIPE_C)); + MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); MMIO_D(DSPPOS(PIPE_C)); MMIO_D(DSPSIZE(PIPE_C)); MMIO_D(DSPSURF(PIPE_C)); -- cgit From 3ebfafa75c1e1250bd1f735e4f48f3b20ece5b99 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:34 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPPOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPPOS register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/fbe6b94f03926175611b51c5054466dd27656d2a.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 34760ecd5d34..b23135ed1a38 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -437,7 +437,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, * generator but let's assume we still need to * program whatever is there. */ - intel_de_write_fw(dev_priv, DSPPOS(i9xx_plane), + intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 049114620d93..13a49550c456 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -53,7 +53,7 @@ #define DSPSTRIDE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) #define _DSPAPOS 0x7018C /* pre-g4x */ -#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) +#define DSPPOS(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) #define DISP_POS_Y_MASK REG_GENMASK(31, 16) #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y)) #define DISP_POS_X_MASK REG_GENMASK(15, 0) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 02c5dafc0c93..00dd2b647c83 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -168,7 +168,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_A)); MMIO_D(DSPADDR(dev_priv, PIPE_A)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); - MMIO_D(DSPPOS(PIPE_A)); + MMIO_D(DSPPOS(dev_priv, PIPE_A)); MMIO_D(DSPSIZE(PIPE_A)); MMIO_D(DSPSURF(PIPE_A)); MMIO_D(DSPOFFSET(PIPE_A)); @@ -177,7 +177,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_B)); MMIO_D(DSPADDR(dev_priv, PIPE_B)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); - MMIO_D(DSPPOS(PIPE_B)); + MMIO_D(DSPPOS(dev_priv, PIPE_B)); MMIO_D(DSPSIZE(PIPE_B)); MMIO_D(DSPSURF(PIPE_B)); MMIO_D(DSPOFFSET(PIPE_B)); @@ -186,7 +186,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPCNTR(dev_priv, PIPE_C)); MMIO_D(DSPADDR(dev_priv, PIPE_C)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); - MMIO_D(DSPPOS(PIPE_C)); + MMIO_D(DSPPOS(dev_priv, PIPE_C)); MMIO_D(DSPSIZE(PIPE_C)); MMIO_D(DSPSURF(PIPE_C)); MMIO_D(DSPOFFSET(PIPE_C)); -- cgit From a99b1e7f6395ec17266d790a5e9d6cab6cb33ba2 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:35 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPSIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSIZE register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/d24ee614cac29ccc3917f9cba1ce03ce54fb7d8b.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index b23135ed1a38..42175cb74d5d 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -439,7 +439,7 @@ static void i9xx_plane_update_noarm(struct intel_plane *plane, */ intel_de_write_fw(dev_priv, DSPPOS(dev_priv, i9xx_plane), DISP_POS_Y(crtc_y) | DISP_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, DSPSIZE(i9xx_plane), + intel_de_write_fw(dev_priv, DSPSIZE(dev_priv, i9xx_plane), DISP_HEIGHT(crtc_h - 1) | DISP_WIDTH(crtc_w - 1)); } } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 13a49550c456..5a1f45eceed4 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -60,7 +60,7 @@ #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x)) #define _DSPASIZE 0x70190 /* pre-g4x */ -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) +#define DSPSIZE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) #define DISP_HEIGHT_MASK REG_GENMASK(31, 16) #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h)) #define DISP_WIDTH_MASK REG_GENMASK(15, 0) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 00dd2b647c83..e047928c3ea0 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -169,7 +169,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_A)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); MMIO_D(DSPPOS(dev_priv, PIPE_A)); - MMIO_D(DSPSIZE(PIPE_A)); + MMIO_D(DSPSIZE(dev_priv, PIPE_A)); MMIO_D(DSPSURF(PIPE_A)); MMIO_D(DSPOFFSET(PIPE_A)); MMIO_D(DSPSURFLIVE(PIPE_A)); @@ -178,7 +178,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_B)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); MMIO_D(DSPPOS(dev_priv, PIPE_B)); - MMIO_D(DSPSIZE(PIPE_B)); + MMIO_D(DSPSIZE(dev_priv, PIPE_B)); MMIO_D(DSPSURF(PIPE_B)); MMIO_D(DSPOFFSET(PIPE_B)); MMIO_D(DSPSURFLIVE(PIPE_B)); @@ -187,7 +187,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPADDR(dev_priv, PIPE_C)); MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); MMIO_D(DSPPOS(dev_priv, PIPE_C)); - MMIO_D(DSPSIZE(PIPE_C)); + MMIO_D(DSPSIZE(dev_priv, PIPE_C)); MMIO_D(DSPSURF(PIPE_C)); MMIO_D(DSPOFFSET(PIPE_C)); MMIO_D(DSPSURFLIVE(PIPE_C)); -- cgit From 9e93147f121e9c333316c87ee6be29507c817186 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:36 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPSURF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSURF register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/fc2d7753aa6e8e25303a111bf4b120da6ce8c458.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 12 ++++++------ drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/display/intel_fbc.c | 4 ++-- drivers/gpu/drm/i915/gvt/cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 8 ++++---- drivers/gpu/drm/i915/intel_clock_gating.c | 6 ++++-- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 8 files changed, 23 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 42175cb74d5d..7adaf8cbd945 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -499,7 +499,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), + intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); else intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), @@ -542,7 +542,7 @@ static void i9xx_plane_disable_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), 0); + intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), 0); else intel_de_write_fw(dev_priv, DSPADDR(dev_priv, i9xx_plane), 0); } @@ -563,7 +563,7 @@ g4x_primary_async_flip(struct intel_plane *plane, intel_de_write_fw(dev_priv, DSPCNTR(dev_priv, i9xx_plane), dspcntr); - intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), + intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), intel_plane_ggtt_offset(plane_state) + dspaddr_offset); } @@ -1034,7 +1034,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); - base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; + base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; } else if (DISPLAY_VER(dev_priv) >= 4) { if (plane_config->tiling) offset = intel_de_read(dev_priv, @@ -1042,7 +1042,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, else offset = intel_de_read(dev_priv, DSPLINOFF(dev_priv, i9xx_plane)); - base = intel_de_read(dev_priv, DSPSURF(i9xx_plane)) & DISP_ADDR_MASK; + base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; } else { offset = 0; base = intel_de_read(dev_priv, DSPADDR(dev_priv, i9xx_plane)); @@ -1094,7 +1094,7 @@ bool i9xx_fixup_initial_plane_config(struct intel_crtc *crtc, return false; if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write(dev_priv, DSPSURF(i9xx_plane), base); + intel_de_write(dev_priv, DSPSURF(dev_priv, i9xx_plane), base); else intel_de_write(dev_priv, DSPADDR(dev_priv, i9xx_plane), base); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 5a1f45eceed4..2771f2a7645b 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -67,7 +67,7 @@ #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w)) #define _DSPASURF 0x7019C /* i965+ */ -#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) +#define DSPSURF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) #define DISP_ADDR_MASK REG_GENMASK(31, 12) #define _DSPATILEOFF 0x701A4 /* i965+ */ diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index f46e01cad053..e9189a864f69 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -364,8 +364,8 @@ static void i965_fbc_nuke(struct intel_fbc *fbc) enum i9xx_plane_id i9xx_plane = fbc_state->plane->i9xx_plane; struct drm_i915_private *dev_priv = fbc->i915; - intel_de_write_fw(dev_priv, DSPSURF(i9xx_plane), - intel_de_read_fw(dev_priv, DSPSURF(i9xx_plane))); + intel_de_write_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane), + intel_de_read_fw(dev_priv, DSPSURF(dev_priv, i9xx_plane))); } static const struct intel_fbc_funcs i965_fbc_funcs = { diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 7072d14d86cf..9cdb53015d16 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1317,7 +1317,7 @@ static int gen8_decode_mi_display_flip(struct parser_exec_state *s, if (info->plane == PLANE_A) { info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); info->stride_reg = DSPSTRIDE(dev_priv, info->pipe); - info->surf_reg = DSPSURF(info->pipe); + info->surf_reg = DSPSURF(dev_priv, info->pipe); } else if (info->plane == PLANE_B) { info->ctrl_reg = SPRCTL(info->pipe); info->stride_reg = SPRSTRIDE(info->pipe); @@ -1383,7 +1383,7 @@ static int skl_decode_mi_display_flip(struct parser_exec_state *s, info->ctrl_reg = DSPCNTR(dev_priv, info->pipe); info->stride_reg = DSPSTRIDE(dev_priv, info->pipe); - info->surf_reg = DSPSURF(info->pipe); + info->surf_reg = DSPSURF(dev_priv, info->pipe); return 0; } diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index cf1cff3d1c4f..6c3a0f160bea 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -251,7 +251,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, plane->hw_format = fmt; - plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; + plane->base = vgpu_vreg_t(vgpu, DSPSURF(dev_priv, pipe)) & I915_GTT_PAGE_MASK; if (!vgpu_gmadr_is_valid(vgpu, plane->base)) return -EINVAL; diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 56fb606b4a3d..abcb8f0825e0 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1008,7 +1008,7 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, } #define DSPSURF_TO_PIPE(offset) \ - calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C)) + calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(dev_priv, PIPE_C)) static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) @@ -2276,13 +2276,13 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write); MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write); MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write); - MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write); + MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write); MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, reg50080_mmio_write); - MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write); + MMIO_DH(DSPSURF(dev_priv, PIPE_B), D_ALL, NULL, pri_surf_mmio_write); MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, reg50080_mmio_write); - MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write); + MMIO_DH(DSPSURF(dev_priv, PIPE_C), D_ALL, NULL, pri_surf_mmio_write); MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, reg50080_mmio_write); MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write); diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 59d50195c144..db4fbb6a803d 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -141,8 +141,10 @@ static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) intel_uncore_rmw(&dev_priv->uncore, DSPCNTR(dev_priv, pipe), 0, DISP_TRICKLE_FEED_DISABLE); - intel_uncore_rmw(&dev_priv->uncore, DSPSURF(pipe), 0, 0); - intel_uncore_posting_read(&dev_priv->uncore, DSPSURF(pipe)); + intel_uncore_rmw(&dev_priv->uncore, DSPSURF(dev_priv, pipe), + 0, 0); + intel_uncore_posting_read(&dev_priv->uncore, + DSPSURF(dev_priv, pipe)); } } diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index e047928c3ea0..a8be80bde2e7 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -170,7 +170,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSTRIDE(dev_priv, PIPE_A)); MMIO_D(DSPPOS(dev_priv, PIPE_A)); MMIO_D(DSPSIZE(dev_priv, PIPE_A)); - MMIO_D(DSPSURF(PIPE_A)); + MMIO_D(DSPSURF(dev_priv, PIPE_A)); MMIO_D(DSPOFFSET(PIPE_A)); MMIO_D(DSPSURFLIVE(PIPE_A)); MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); @@ -179,7 +179,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSTRIDE(dev_priv, PIPE_B)); MMIO_D(DSPPOS(dev_priv, PIPE_B)); MMIO_D(DSPSIZE(dev_priv, PIPE_B)); - MMIO_D(DSPSURF(PIPE_B)); + MMIO_D(DSPSURF(dev_priv, PIPE_B)); MMIO_D(DSPOFFSET(PIPE_B)); MMIO_D(DSPSURFLIVE(PIPE_B)); MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); @@ -188,7 +188,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSTRIDE(dev_priv, PIPE_C)); MMIO_D(DSPPOS(dev_priv, PIPE_C)); MMIO_D(DSPSIZE(dev_priv, PIPE_C)); - MMIO_D(DSPSURF(PIPE_C)); + MMIO_D(DSPSURF(dev_priv, PIPE_C)); MMIO_D(DSPOFFSET(PIPE_C)); MMIO_D(DSPSURFLIVE(PIPE_C)); MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY)); -- cgit From d434ac6252768a5aecf7004fddb939a1d945085f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:37 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPTILEOFF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPTILEOFF register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/4736b2d65ca3be3e9eb5a835ddac801ba99e1e6b.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 4 ++-- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/gvt/fb_decoder.c | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 7adaf8cbd945..36225c2aa1c8 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -487,7 +487,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, } else if (DISPLAY_VER(dev_priv) >= 4) { intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane), linear_offset); - intel_de_write_fw(dev_priv, DSPTILEOFF(i9xx_plane), + intel_de_write_fw(dev_priv, DSPTILEOFF(dev_priv, i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); } @@ -1038,7 +1038,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, } else if (DISPLAY_VER(dev_priv) >= 4) { if (plane_config->tiling) offset = intel_de_read(dev_priv, - DSPTILEOFF(i9xx_plane)); + DSPTILEOFF(dev_priv, i9xx_plane)); else offset = intel_de_read(dev_priv, DSPLINOFF(dev_priv, i9xx_plane)); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 2771f2a7645b..baa3d348c77e 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -71,7 +71,7 @@ #define DISP_ADDR_MASK REG_GENMASK(31, 12) #define _DSPATILEOFF 0x701A4 /* i965+ */ -#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) +#define DSPTILEOFF(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16) #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y)) #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0) diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 6c3a0f160bea..0afde865a7de 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -274,7 +274,7 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; plane->height += 1; /* raw height is one minus the real value */ - val = vgpu_vreg_t(vgpu, DSPTILEOFF(pipe)); + val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe)); plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >> _PRI_PLANE_X_OFF_SHIFT; plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >> -- cgit From 495d6f77dfa79b26bfa95eca3215179659c2cf8e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:38 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPOFFSET MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPOFFSET register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/c1d487d2c753221144e8fb8f17e5eb2826dba5f2.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 5 +++-- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 36225c2aa1c8..2026323d88ac 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -482,7 +482,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, } if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - intel_de_write_fw(dev_priv, DSPOFFSET(i9xx_plane), + intel_de_write_fw(dev_priv, DSPOFFSET(dev_priv, i9xx_plane), DISP_OFFSET_Y(y) | DISP_OFFSET_X(x)); } else if (DISPLAY_VER(dev_priv) >= 4) { intel_de_write_fw(dev_priv, DSPLINOFF(dev_priv, i9xx_plane), @@ -1033,7 +1033,8 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, fb->format = drm_format_info(fourcc); if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { - offset = intel_de_read(dev_priv, DSPOFFSET(i9xx_plane)); + offset = intel_de_read(dev_priv, + DSPOFFSET(dev_priv, i9xx_plane)); base = intel_de_read(dev_priv, DSPSURF(dev_priv, i9xx_plane)) & DISP_ADDR_MASK; } else if (DISPLAY_VER(dev_priv) >= 4) { if (plane_config->tiling) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index baa3d348c77e..0930a76ccf3c 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -78,7 +78,7 @@ #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x)) #define _DSPAOFFSET 0x701A4 /* hsw+ */ -#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) +#define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) #define _DSPASURFLIVE 0x701AC /* g4x+ */ #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index a8be80bde2e7..50dfe1f81b99 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -171,7 +171,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPPOS(dev_priv, PIPE_A)); MMIO_D(DSPSIZE(dev_priv, PIPE_A)); MMIO_D(DSPSURF(dev_priv, PIPE_A)); - MMIO_D(DSPOFFSET(PIPE_A)); + MMIO_D(DSPOFFSET(dev_priv, PIPE_A)); MMIO_D(DSPSURFLIVE(PIPE_A)); MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_B)); @@ -180,7 +180,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPPOS(dev_priv, PIPE_B)); MMIO_D(DSPSIZE(dev_priv, PIPE_B)); MMIO_D(DSPSURF(dev_priv, PIPE_B)); - MMIO_D(DSPOFFSET(PIPE_B)); + MMIO_D(DSPOFFSET(dev_priv, PIPE_B)); MMIO_D(DSPSURFLIVE(PIPE_B)); MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_C)); @@ -189,7 +189,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPPOS(dev_priv, PIPE_C)); MMIO_D(DSPSIZE(dev_priv, PIPE_C)); MMIO_D(DSPSURF(dev_priv, PIPE_C)); - MMIO_D(DSPOFFSET(PIPE_C)); + MMIO_D(DSPOFFSET(dev_priv, PIPE_C)); MMIO_D(DSPSURFLIVE(PIPE_C)); MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY)); MMIO_D(SPRCTL(PIPE_A)); -- cgit From 89b85751b4fda1918cf314318d61a184218d3df3 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:39 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPSURFLIVE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPSURFLIVE register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/bc252dee67718f729883da7d542c6435384683ae.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 4 ++-- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 0930a76ccf3c..22a550c8b41a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -81,7 +81,7 @@ #define DSPOFFSET(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) #define _DSPASURFLIVE 0x701AC /* g4x+ */ -#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) +#define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) #define _DSPAGAMC 0x701E0 /* pre-g4x */ #define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index abcb8f0825e0..840fea160aa6 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1018,7 +1018,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); write_vreg(vgpu, offset, p_data, bytes); - vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); + vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; @@ -1061,7 +1061,7 @@ static int reg50080_mmio_write(struct intel_vgpu *vgpu, write_vreg(vgpu, offset, p_data, bytes); if (plane == PLANE_PRIMARY) { - vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); + vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; } else { vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 50dfe1f81b99..b4d5592b18df 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -172,7 +172,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSIZE(dev_priv, PIPE_A)); MMIO_D(DSPSURF(dev_priv, PIPE_A)); MMIO_D(DSPOFFSET(dev_priv, PIPE_A)); - MMIO_D(DSPSURFLIVE(PIPE_A)); + MMIO_D(DSPSURFLIVE(dev_priv, PIPE_A)); MMIO_D(REG_50080(PIPE_A, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_B)); MMIO_D(DSPADDR(dev_priv, PIPE_B)); @@ -181,7 +181,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSIZE(dev_priv, PIPE_B)); MMIO_D(DSPSURF(dev_priv, PIPE_B)); MMIO_D(DSPOFFSET(dev_priv, PIPE_B)); - MMIO_D(DSPSURFLIVE(PIPE_B)); + MMIO_D(DSPSURFLIVE(dev_priv, PIPE_B)); MMIO_D(REG_50080(PIPE_B, PLANE_PRIMARY)); MMIO_D(DSPCNTR(dev_priv, PIPE_C)); MMIO_D(DSPADDR(dev_priv, PIPE_C)); @@ -190,7 +190,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(DSPSIZE(dev_priv, PIPE_C)); MMIO_D(DSPSURF(dev_priv, PIPE_C)); MMIO_D(DSPOFFSET(dev_priv, PIPE_C)); - MMIO_D(DSPSURFLIVE(PIPE_C)); + MMIO_D(DSPSURFLIVE(dev_priv, PIPE_C)); MMIO_D(REG_50080(PIPE_C, PLANE_PRIMARY)); MMIO_D(SPRCTL(PIPE_A)); MMIO_D(SPRLINOFF(PIPE_A)); -- cgit From 17c99a03b7768f6ae8fa128e72c6a5d95b184eda Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:40 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPGAMC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPGAMC register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/542455204f62182a46fa2cb16ad6b0648c72f612.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 22a550c8b41a..f67c5a2bb6b9 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -84,7 +84,7 @@ #define DSPSURFLIVE(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) #define _DSPAGAMC 0x701E0 /* pre-g4x */ -#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ +#define DSPGAMC(dev_priv, plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ #define _PRIMPOS_A 0x60a08 -- cgit From 90fa6a4210b78b39091627f4bd10f28835c4c5c2 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:41 +0300 Subject: drm/i915: pass dev_priv explicitly to PRIMPOS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PRIMPOS register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/4bbb3218ac25b292bea46dcba3df8ec474d578e2.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 2026323d88ac..1cefcdd4f26a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -474,7 +474,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, int crtc_w = drm_rect_width(&plane_state->uapi.dst); int crtc_h = drm_rect_height(&plane_state->uapi.dst); - intel_de_write_fw(dev_priv, PRIMPOS(i9xx_plane), + intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index f67c5a2bb6b9..7f291b34f10a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -87,8 +87,8 @@ #define DSPGAMC(dev_priv, plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B primary plane */ -#define _PRIMPOS_A 0x60a08 -#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) +#define _PRIMPOS_A 0x60a08 +#define PRIMPOS(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) #define PRIM_POS_Y_MASK REG_GENMASK(31, 16) #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y)) #define PRIM_POS_X_MASK REG_GENMASK(15, 0) -- cgit From 491097568a55238017356dba341cf6726a35b6bc Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:42 +0300 Subject: drm/i915: pass dev_priv explicitly to PRIMSIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PRIMSIZE register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/b672f17b4c3d5ba7ac606798bb3799408c26f075.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 1cefcdd4f26a..82cb393a0a22 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -476,7 +476,7 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, intel_de_write_fw(dev_priv, PRIMPOS(dev_priv, i9xx_plane), PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); - intel_de_write_fw(dev_priv, PRIMSIZE(i9xx_plane), + intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); } diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 7f291b34f10a..8d45c879e74a 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -94,8 +94,8 @@ #define PRIM_POS_X_MASK REG_GENMASK(15, 0) #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x)) -#define _PRIMSIZE_A 0x60a0c -#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) +#define _PRIMSIZE_A 0x60a0c +#define PRIMSIZE(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16) #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h)) #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) -- cgit From 1572fc3162de89f484d544beac6ae1204440f3c7 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:43 +0300 Subject: drm/i915: pass dev_priv explicitly to PRIMCNSTALPHA MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PRIMCNSTALPHA register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/783477b86f4d53849775cbf690bb8b9042792a66.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 3 ++- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 82cb393a0a22..5c8778865156 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -478,7 +478,8 @@ static void i9xx_plane_update_arm(struct intel_plane *plane, PRIM_POS_Y(crtc_y) | PRIM_POS_X(crtc_x)); intel_de_write_fw(dev_priv, PRIMSIZE(dev_priv, i9xx_plane), PRIM_HEIGHT(crtc_h - 1) | PRIM_WIDTH(crtc_w - 1)); - intel_de_write_fw(dev_priv, PRIMCNSTALPHA(i9xx_plane), 0); + intel_de_write_fw(dev_priv, + PRIMCNSTALPHA(dev_priv, i9xx_plane), 0); } if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index 8d45c879e74a..a2ba55fa2b30 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -101,8 +101,8 @@ #define PRIM_WIDTH_MASK REG_GENMASK(15, 0) #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w)) -#define _PRIMCNSTALPHA_A 0x60a10 -#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) +#define _PRIMCNSTALPHA_A 0x60a10 +#define PRIMCNSTALPHA(dev_priv, plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31) #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) -- cgit From eff70dac16d1f87c262049783b3281b706448593 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 15:59:44 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPEGCMAX MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPEGCMAX register macro. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/5fdc8562fe7b8d26e1ec1bb8f9a221348246bbe1.1716469091.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_color.c | 12 ++++++------ drivers/gpu/drm/i915/display/intel_color_regs.h | 6 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index a83f41ee6834..5c278b97d069 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1284,9 +1284,9 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc, i965_lut_10p6_udw(&lut[i])); } - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 0), lut[i].red); - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 1), lut[i].green); - intel_de_write_fw(dev_priv, PIPEGCMAX(pipe, 2), lut[i].blue); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0), lut[i].red); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1), lut[i].green); + intel_de_write_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2), lut[i].blue); } static void i965_load_luts(const struct intel_crtc_state *crtc_state) @@ -3239,9 +3239,9 @@ static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) i965_lut_10p6_pack(&lut[i], ldw, udw); } - lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 0))); - lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 1))); - lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(pipe, 2))); + lut[i].red = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 0))); + lut[i].green = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 1))); + lut[i].blue = i965_lut_11p6_max_pack(intel_de_read_fw(dev_priv, PIPEGCMAX(dev_priv, pipe, 2))); return blob; } diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h index 61c18b4a7fa5..8eb643cfead7 100644 --- a/drivers/gpu/drm/i915/display/intel_color_regs.h +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h @@ -37,9 +37,9 @@ (i) * 4) /* i965/g4x/vlv/chv */ -#define _PIPEAGCMAX 0x70010 -#define _PIPEBGCMAX 0x71010 -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ +#define _PIPEAGCMAX 0x70010 +#define _PIPEBGCMAX 0x71010 +#define PIPEGCMAX(dev_priv, pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ /* ilk+ palette */ #define _LGC_PALETTE_A 0x4a000 -- cgit From fdd0b80172758ce284f19fa8a26d90c61e4371d2 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 21 May 2024 17:30:22 +0300 Subject: drm/i915: Fix audio component initialization After registering the audio component in i915_audio_component_init() the audio driver may call i915_audio_component_get_power() via the component ops. This could program AUD_FREQ_CNTRL with an uninitialized value if the latter function is called before display.audio.freq_cntrl gets initialized. The get_power() function also does a modeset which in the above case happens too early before the initialization step and triggers the "Reject display access from task" error message added by the Fixes: commit below. Fix the above issue by registering the audio component only after the initialization step. Fixes: 87c1694533c9 ("drm/i915: save AUD_FREQ_CNTRL state at audio domain suspend") Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10291 Cc: stable@vger.kernel.org # v5.5+ Signed-off-by: Imre Deak Reviewed-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/20240521143022.3784539-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_audio.c | 32 ++++++++++++++-------- drivers/gpu/drm/i915/display/intel_audio.h | 1 + .../gpu/drm/i915/display/intel_display_driver.c | 2 ++ 3 files changed, 24 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index adde87900557..4c031e97f9a5 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -1267,17 +1267,6 @@ static const struct component_ops i915_audio_component_bind_ops = { static void i915_audio_component_init(struct drm_i915_private *i915) { u32 aud_freq, aud_freq_init; - int ret; - - ret = component_add_typed(i915->drm.dev, - &i915_audio_component_bind_ops, - I915_COMPONENT_AUDIO); - if (ret < 0) { - drm_err(&i915->drm, - "failed to add audio component (%d)\n", ret); - /* continue with reduced functionality */ - return; - } if (DISPLAY_VER(i915) >= 9) { aud_freq_init = intel_de_read(i915, AUD_FREQ_CNTRL); @@ -1300,6 +1289,21 @@ static void i915_audio_component_init(struct drm_i915_private *i915) /* init with current cdclk */ intel_audio_cdclk_change_post(i915); +} + +static void i915_audio_component_register(struct drm_i915_private *i915) +{ + int ret; + + ret = component_add_typed(i915->drm.dev, + &i915_audio_component_bind_ops, + I915_COMPONENT_AUDIO); + if (ret < 0) { + drm_err(&i915->drm, + "failed to add audio component (%d)\n", ret); + /* continue with reduced functionality */ + return; + } i915->display.audio.component_registered = true; } @@ -1332,6 +1336,12 @@ void intel_audio_init(struct drm_i915_private *i915) i915_audio_component_init(i915); } +void intel_audio_register(struct drm_i915_private *i915) +{ + if (!i915->display.audio.lpe.platdev) + i915_audio_component_register(i915); +} + /** * intel_audio_deinit() - deinitialize the audio driver * @i915: the i915 drm device private data diff --git a/drivers/gpu/drm/i915/display/intel_audio.h b/drivers/gpu/drm/i915/display/intel_audio.h index 9327954b801e..576c061d72a4 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.h +++ b/drivers/gpu/drm/i915/display/intel_audio.h @@ -28,6 +28,7 @@ void intel_audio_codec_get_config(struct intel_encoder *encoder, void intel_audio_cdclk_change_pre(struct drm_i915_private *dev_priv); void intel_audio_cdclk_change_post(struct drm_i915_private *dev_priv); void intel_audio_init(struct drm_i915_private *dev_priv); +void intel_audio_register(struct drm_i915_private *i915); void intel_audio_deinit(struct drm_i915_private *dev_priv); void intel_audio_sdp_split_update(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 89bd032ed995..794b4af38055 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -540,6 +540,8 @@ void intel_display_driver_register(struct drm_i915_private *i915) intel_display_driver_enable_user_access(i915); + intel_audio_register(i915); + intel_display_debugfs_register(i915); /* -- cgit From fabdb275e5ed13271d8fa218a22616ba7ae5aeea Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 24 May 2024 18:50:00 +0300 Subject: drm/i915: Fix SEL_FETCH_{SIZE,OFFSET} registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix up the SEL_FETCH_{SIZE,OFFSET} registers. A classic copy-paste fail on my part. I even had a small test to confirm that the old and new register offsets match, but somehow I must have screwed things up when running it, and likely just ended up comparing the old defines against themselves :/ Cc: Jani Nikula Fixes: 4bfa8a140db3 ("drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()") Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240524155000.13358-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h index 9904ecc54128..4ddcd7d46bbd 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h @@ -419,10 +419,10 @@ #define _SEL_FETCH_PLANE_SIZE_5_B 0x71928 #define _SEL_FETCH_PLANE_SIZE_6_B 0x71948 #define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ - _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ - _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ - _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ - _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B) + _SEL_FETCH_PLANE_SIZE_1_A, _SEL_FETCH_PLANE_SIZE_1_B, \ + _SEL_FETCH_PLANE_SIZE_2_A, _SEL_FETCH_PLANE_SIZE_2_B, \ + _SEL_FETCH_PLANE_SIZE_5_A, _SEL_FETCH_PLANE_SIZE_5_B, \ + _SEL_FETCH_PLANE_SIZE_6_A, _SEL_FETCH_PLANE_SIZE_6_B) /* tgl+ */ #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089c @@ -434,9 +434,9 @@ #define _SEL_FETCH_PLANE_OFFSET_5_B 0x7192c #define _SEL_FETCH_PLANE_OFFSET_6_B 0x7194c #define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\ - _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \ - _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \ - _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \ - _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B) + _SEL_FETCH_PLANE_OFFSET_1_A, _SEL_FETCH_PLANE_OFFSET_1_B, \ + _SEL_FETCH_PLANE_OFFSET_2_A, _SEL_FETCH_PLANE_OFFSET_2_B, \ + _SEL_FETCH_PLANE_OFFSET_5_A, _SEL_FETCH_PLANE_OFFSET_5_B, \ + _SEL_FETCH_PLANE_OFFSET_6_A, _SEL_FETCH_PLANE_OFFSET_6_B) #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */ -- cgit From 5f128aa1052e7d28074ac9b5279d0a09232b699a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 23 May 2024 21:28:16 +0300 Subject: drm/i915: Plumb the entire atomic state into intel_color_check() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Bunch of stuff in intel_color_check() needs to look at both the old and new crtc states. Currently we do that by digging the full atomic state via the crtc_state->state pointer. That thing is a total footgun if I ever saw one, as it's only valid during specific parts of the atomic flow. A lot of people have been bitten by this thing in the past when trying to use it after it's no longer valid. Take a small step towards elimination of the footgun by not using it in the inte_color_check(). Instead we plumb in the entire atomic state all the way from the top. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240523182818.15382-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_color.c | 111 ++++++++++++++++----------- drivers/gpu/drm/i915/display/intel_color.h | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 2 +- 3 files changed, 69 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 5c278b97d069..dda7c268e289 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -30,7 +30,8 @@ #include "intel_dsb.h" struct intel_color_funcs { - int (*color_check)(struct intel_crtc_state *crtc_state); + int (*color_check)(struct intel_atomic_state *state, + struct intel_crtc *crtc); /* * Program non-arming double buffered color management registers * before vblank evasion. The registers should then latch after @@ -1942,11 +1943,9 @@ bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state) return crtc_state->dsb; } -static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state) +static bool intel_can_preload_luts(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); - struct intel_atomic_state *state = - to_intel_atomic_state(new_crtc_state->uapi.state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); @@ -1954,11 +1953,9 @@ static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state !old_crtc_state->pre_csc_lut; } -static bool vlv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) +static bool vlv_can_preload_luts(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); - struct intel_atomic_state *state = - to_intel_atomic_state(new_crtc_state->uapi.state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); @@ -1966,13 +1963,13 @@ static bool vlv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) !old_crtc_state->post_csc_lut; } -static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) +static bool chv_can_preload_luts(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); - struct intel_atomic_state *state = - to_intel_atomic_state(new_crtc_state->uapi.state); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); /* * CGM_PIPE_MODE is itself single buffered. We'd have to @@ -1982,14 +1979,15 @@ static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode) return false; - return vlv_can_preload_luts(new_crtc_state); + return vlv_can_preload_luts(state, crtc); } -int intel_color_check(struct intel_crtc_state *crtc_state) +int intel_color_check(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); - return i915->display.funcs.color->color_check(crtc_state); + return i915->display.funcs.color->color_check(state, crtc); } void intel_color_get_config(struct intel_crtc_state *crtc_state) @@ -2039,14 +2037,14 @@ static bool need_plane_update(struct intel_plane *plane, } static int -intel_color_add_affected_planes(struct intel_crtc_state *new_crtc_state) +intel_color_add_affected_planes(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - struct intel_atomic_state *state = - to_intel_atomic_state(new_crtc_state->uapi.state); + struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); + struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); struct intel_plane *plane; if (!new_crtc_state->hw.active || @@ -2240,9 +2238,12 @@ static void intel_assign_luts(struct intel_crtc_state *crtc_state) crtc_state->hw.gamma_lut); } -static int i9xx_color_check(struct intel_crtc_state *crtc_state) +static int i9xx_color_check(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); int ret; ret = check_luts(crtc_state); @@ -2262,13 +2263,13 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state) return ret; } - ret = intel_color_add_affected_planes(crtc_state); + ret = intel_color_add_affected_planes(state, crtc); if (ret) return ret; intel_assign_luts(crtc_state); - crtc_state->preload_luts = intel_can_preload_luts(crtc_state); + crtc_state->preload_luts = intel_can_preload_luts(state, crtc); return 0; } @@ -2277,8 +2278,11 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state) * VLV color pipeline: * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 */ -static int vlv_color_check(struct intel_crtc_state *crtc_state) +static int vlv_color_check(struct intel_atomic_state *state, + struct intel_crtc *crtc) { + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); int ret; ret = check_luts(crtc_state); @@ -2293,7 +2297,7 @@ static int vlv_color_check(struct intel_crtc_state *crtc_state) crtc_state->wgc_enable = crtc_state->hw.ctm; - ret = intel_color_add_affected_planes(crtc_state); + ret = intel_color_add_affected_planes(state, crtc); if (ret) return ret; @@ -2301,7 +2305,7 @@ static int vlv_color_check(struct intel_crtc_state *crtc_state) vlv_assign_csc(crtc_state); - crtc_state->preload_luts = vlv_can_preload_luts(crtc_state); + crtc_state->preload_luts = vlv_can_preload_luts(state, crtc); return 0; } @@ -2336,8 +2340,11 @@ static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) * We always bypass the WGC csc and use the CGM csc * instead since it has degamma and better precision. */ -static int chv_color_check(struct intel_crtc_state *crtc_state) +static int chv_color_check(struct intel_atomic_state *state, + struct intel_crtc *crtc) { + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); int ret; ret = check_luts(crtc_state); @@ -2362,7 +2369,7 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) */ crtc_state->wgc_enable = false; - ret = intel_color_add_affected_planes(crtc_state); + ret = intel_color_add_affected_planes(state, crtc); if (ret) return ret; @@ -2370,7 +2377,7 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) chv_assign_csc(crtc_state); - crtc_state->preload_luts = chv_can_preload_luts(crtc_state); + crtc_state->preload_luts = chv_can_preload_luts(state, crtc); return 0; } @@ -2454,9 +2461,12 @@ static int ilk_assign_luts(struct intel_crtc_state *crtc_state) return 0; } -static int ilk_color_check(struct intel_crtc_state *crtc_state) +static int ilk_color_check(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); int ret; ret = check_luts(crtc_state); @@ -2484,7 +2494,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state) crtc_state->csc_mode = ilk_csc_mode(crtc_state); - ret = intel_color_add_affected_planes(crtc_state); + ret = intel_color_add_affected_planes(state, crtc); if (ret) return ret; @@ -2494,7 +2504,7 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state) ilk_assign_csc(crtc_state); - crtc_state->preload_luts = intel_can_preload_luts(crtc_state); + crtc_state->preload_luts = intel_can_preload_luts(state, crtc); return 0; } @@ -2555,9 +2565,12 @@ static int ivb_assign_luts(struct intel_crtc_state *crtc_state) return 0; } -static int ivb_color_check(struct intel_crtc_state *crtc_state) +static int ivb_color_check(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); int ret; ret = check_luts(crtc_state); @@ -2592,7 +2605,7 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state) crtc_state->csc_mode = ivb_csc_mode(crtc_state); - ret = intel_color_add_affected_planes(crtc_state); + ret = intel_color_add_affected_planes(state, crtc); if (ret) return ret; @@ -2602,7 +2615,7 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state) ilk_assign_csc(crtc_state); - crtc_state->preload_luts = intel_can_preload_luts(crtc_state); + crtc_state->preload_luts = intel_can_preload_luts(state, crtc); return 0; } @@ -2686,9 +2699,12 @@ static int glk_check_luts(const struct intel_crtc_state *crtc_state) return _check_luts(crtc_state, degamma_tests, gamma_tests); } -static int glk_color_check(struct intel_crtc_state *crtc_state) +static int glk_color_check(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); int ret; ret = glk_check_luts(crtc_state); @@ -2725,7 +2741,7 @@ static int glk_color_check(struct intel_crtc_state *crtc_state) crtc_state->csc_mode = 0; - ret = intel_color_add_affected_planes(crtc_state); + ret = intel_color_add_affected_planes(state, crtc); if (ret) return ret; @@ -2735,7 +2751,7 @@ static int glk_color_check(struct intel_crtc_state *crtc_state) ilk_assign_csc(crtc_state); - crtc_state->preload_luts = intel_can_preload_luts(crtc_state); + crtc_state->preload_luts = intel_can_preload_luts(state, crtc); return 0; } @@ -2783,8 +2799,11 @@ static u32 icl_csc_mode(const struct intel_crtc_state *crtc_state) return csc_mode; } -static int icl_color_check(struct intel_crtc_state *crtc_state) +static int icl_color_check(struct intel_atomic_state *state, + struct intel_crtc *crtc) { + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); int ret; ret = check_luts(crtc_state); @@ -2799,7 +2818,7 @@ static int icl_color_check(struct intel_crtc_state *crtc_state) icl_assign_csc(crtc_state); - crtc_state->preload_luts = intel_can_preload_luts(crtc_state); + crtc_state->preload_luts = intel_can_preload_luts(state, crtc); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h index 8ecd36149def..21ba4aa02e7b 100644 --- a/drivers/gpu/drm/i915/display/intel_color.h +++ b/drivers/gpu/drm/i915/display/intel_color.h @@ -8,6 +8,7 @@ #include +struct intel_atomic_state; struct intel_crtc_state; struct intel_crtc; struct drm_i915_private; @@ -16,7 +17,8 @@ struct drm_property_blob; void intel_color_init_hooks(struct drm_i915_private *i915); int intel_color_init(struct drm_i915_private *i915); void intel_color_crtc_init(struct intel_crtc *crtc); -int intel_color_check(struct intel_crtc_state *crtc_state); +int intel_color_check(struct intel_atomic_state *state, + struct intel_crtc *crtc); void intel_color_prepare_commit(struct intel_crtc_state *crtc_state); void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state); bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 58a4060f90b4..61c073fc0a46 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4255,7 +4255,7 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, crtc_state->uapi.color_mgmt_changed = true; if (intel_crtc_needs_color_update(crtc_state)) { - ret = intel_color_check(crtc_state); + ret = intel_color_check(state, crtc); if (ret) return ret; } -- cgit From 325257f2e9cb753a1581f8ca50e84012010d2718 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 23 May 2024 21:28:17 +0300 Subject: drm/i915: Hide the intel_crtc_needs_color_update() inside intel_color_check() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the intel_crtc_needs_color_update() into intel_color_check() so that the caller doesn't have to care about this. This will also enable us to hide the c8_planes_changed() thing better. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240523182818.15382-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_color.c | 5 +++++ drivers/gpu/drm/i915/display/intel_display.c | 8 +++----- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index dda7c268e289..fab474499182 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1986,6 +1986,11 @@ int intel_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); + + if (!intel_crtc_needs_color_update(new_crtc_state)) + return 0; return i915->display.funcs.color->color_check(state, crtc); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 61c073fc0a46..d035a12cbeb0 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4254,11 +4254,9 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, if (c8_planes_changed(crtc_state)) crtc_state->uapi.color_mgmt_changed = true; - if (intel_crtc_needs_color_update(crtc_state)) { - ret = intel_color_check(state, crtc); - if (ret) - return ret; - } + ret = intel_color_check(state, crtc); + if (ret) + return ret; ret = intel_compute_pipe_wm(state, crtc); if (ret) { -- cgit From 454772c7f7ecf6c51fadb7f35bc3ee430bd86885 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 23 May 2024 21:28:18 +0300 Subject: drm/i915: Bury c8_planes_changed() in intel_color_check() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The c8_planes_changed() check in the high level atomic code is a bit of an eyesore. Push it inside intel_color_check() so the high level code doesn't have to care about this stuff. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240523182818.15382-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_color.c | 11 ++++++++++- drivers/gpu/drm/i915/display/intel_display.c | 18 ------------------ 2 files changed, 10 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index fab474499182..9173caba3f0f 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1986,9 +1986,18 @@ int intel_color_check(struct intel_atomic_state *state, struct intel_crtc *crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); - const struct intel_crtc_state *new_crtc_state = + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); + /* + * May need to update pipe gamma enable bits + * when C8 planes are getting enabled/disabled. + */ + if (!old_crtc_state->c8_planes != !new_crtc_state->c8_planes) + new_crtc_state->uapi.color_mgmt_changed = true; + if (!intel_crtc_needs_color_update(new_crtc_state)) return 0; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index d035a12cbeb0..071ba95a1472 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4138,17 +4138,6 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) return 0; } -static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state) -{ - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); - struct intel_atomic_state *state = - to_intel_atomic_state(new_crtc_state->uapi.state); - const struct intel_crtc_state *old_crtc_state = - intel_atomic_get_old_crtc_state(state, crtc); - - return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes; -} - static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state) { const struct drm_display_mode *pipe_mode = @@ -4247,13 +4236,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state, return ret; } - /* - * May need to update pipe gamma enable bits - * when C8 planes are getting enabled/disabled. - */ - if (c8_planes_changed(crtc_state)) - crtc_state->uapi.color_mgmt_changed = true; - ret = intel_color_check(state, crtc); if (ret) return ret; -- cgit From 92cd5d046a96870abb0e9ad9922891066b5e5fb9 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 13:41:57 +0300 Subject: drm/i915: pass dev_priv explicitly to _MMIO_PPS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the _MMIO_PPS register macro. While at it, use __to_intel_display() to allow passing in struct intel_display at a later time. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/1e9f3ef7eee65946c0e6bf06cc2547a38e8dab78.1716806471.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pps_regs.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pps_regs.h b/drivers/gpu/drm/i915/display/intel_pps_regs.h index 60edd2a27100..bdcdf6ae2747 100644 --- a/drivers/gpu/drm/i915/display/intel_pps_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pps_regs.h @@ -6,6 +6,7 @@ #ifndef __INTEL_PPS_REGS_H__ #define __INTEL_PPS_REGS_H__ +#include "intel_display_conversion.h" #include "intel_display_reg_defs.h" /* Panel power sequencing */ @@ -13,12 +14,11 @@ #define VLV_PPS_BASE (VLV_DISPLAY_BASE + PPS_BASE) #define PCH_PPS_BASE 0xC7200 -#define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->display.pps.mmio_base - \ - PPS_BASE + (reg) + \ - (pps_idx) * 0x100) +#define _MMIO_PPS(dev_priv, pps_idx, reg) \ + _MMIO(__to_intel_display(dev_priv)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100) #define _PP_STATUS 0x61200 -#define PP_STATUS(pps_idx) _MMIO_PPS(pps_idx, _PP_STATUS) +#define PP_STATUS(pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_STATUS) #define PP_ON REG_BIT(31) /* * Indicates that all dependencies of the panel are on: @@ -45,7 +45,7 @@ #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) #define _PP_CONTROL 0x61204 -#define PP_CONTROL(pps_idx) _MMIO_PPS(pps_idx, _PP_CONTROL) +#define PP_CONTROL(pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_CONTROL) #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) @@ -55,7 +55,7 @@ #define PANEL_POWER_ON REG_BIT(0) #define _PP_ON_DELAYS 0x61208 -#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_ON_DELAYS) +#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_ON_DELAYS) #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) @@ -66,12 +66,12 @@ #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) #define _PP_OFF_DELAYS 0x6120C -#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(pps_idx, _PP_OFF_DELAYS) +#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_OFF_DELAYS) #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) #define _PP_DIVISOR 0x61210 -#define PP_DIVISOR(pps_idx) _MMIO_PPS(pps_idx, _PP_DIVISOR) +#define PP_DIVISOR(pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_DIVISOR) #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) -- cgit From fdc97fdc0469583e7960a5b6acc4de9ed1f595e6 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 13:41:58 +0300 Subject: drm/i915: pass dev_priv explicitly to PP_STATUS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PP_STATUS register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/7b76be10723f36d6e1b45be76d112a4b178ef493.1716806471.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- drivers/gpu/drm/i915/display/intel_lvds.c | 6 +++--- drivers/gpu/drm/i915/display/intel_pps.c | 4 ++-- drivers/gpu/drm/i915/display/intel_pps_regs.h | 2 +- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index a860d88a65da..34b6d843bc9e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1207,7 +1207,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) intel_de_read(dev_priv, WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); I915_STATE_WARN(dev_priv, - intel_de_read(dev_priv, PP_STATUS(0)) & PP_ON, + intel_de_read(dev_priv, PP_STATUS(dev_priv, 0)) & PP_ON, "Panel power on\n"); I915_STATE_WARN(dev_priv, intel_de_read(dev_priv, BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 8b8959073466..eec0dab3c3b2 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -324,7 +324,7 @@ static void intel_enable_lvds(struct intel_atomic_state *state, intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON); intel_de_posting_read(dev_priv, lvds_encoder->reg); - if (intel_de_wait_for_set(dev_priv, PP_STATUS(0), PP_ON, 5000)) + if (intel_de_wait_for_set(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 5000)) drm_err(&dev_priv->drm, "timed out waiting for panel to power on\n"); @@ -340,7 +340,7 @@ static void intel_disable_lvds(struct intel_atomic_state *state, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0); - if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_ON, 1000)) + if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 1000)) drm_err(&dev_priv->drm, "timed out waiting for panel to power off\n"); @@ -379,7 +379,7 @@ static void intel_lvds_shutdown(struct intel_encoder *encoder) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - if (intel_de_wait_for_clear(dev_priv, PP_STATUS(0), PP_CYCLE_DELAY_ACTIVE, 5000)) + if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_CYCLE_DELAY_ACTIVE, 5000)) drm_err(&dev_priv->drm, "timed out waiting for panel power cycle delay\n"); } diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 0ccbf9a85914..9aa08b525810 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -272,7 +272,7 @@ typedef bool (*pps_check)(struct drm_i915_private *dev_priv, int pps_idx); static bool pps_has_pp_on(struct drm_i915_private *dev_priv, int pps_idx) { - return intel_de_read(dev_priv, PP_STATUS(pps_idx)) & PP_ON; + return intel_de_read(dev_priv, PP_STATUS(dev_priv, pps_idx)) & PP_ON; } static bool pps_has_vdd_on(struct drm_i915_private *dev_priv, int pps_idx) @@ -492,7 +492,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, pps_idx = intel_dp->pps.pps_idx; regs->pp_ctrl = PP_CONTROL(pps_idx); - regs->pp_stat = PP_STATUS(pps_idx); + regs->pp_stat = PP_STATUS(dev_priv, pps_idx); regs->pp_on = PP_ON_DELAYS(pps_idx); regs->pp_off = PP_OFF_DELAYS(pps_idx); diff --git a/drivers/gpu/drm/i915/display/intel_pps_regs.h b/drivers/gpu/drm/i915/display/intel_pps_regs.h index bdcdf6ae2747..06bdf766b749 100644 --- a/drivers/gpu/drm/i915/display/intel_pps_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pps_regs.h @@ -18,7 +18,7 @@ _MMIO(__to_intel_display(dev_priv)->pps.mmio_base - PPS_BASE + (reg) + (pps_idx) * 0x100) #define _PP_STATUS 0x61200 -#define PP_STATUS(pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_STATUS) +#define PP_STATUS(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_STATUS) #define PP_ON REG_BIT(31) /* * Indicates that all dependencies of the panel are on: -- cgit From de49b912d2adfe5447c978036aeed1ccb6fe1db0 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 13:41:59 +0300 Subject: drm/i915: pass dev_priv explicitly to PP_CONTROL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PP_CONTROL register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/01024887af682d4c9ddfb440af98284c44422df7.1716806471.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 4 ++-- drivers/gpu/drm/i915/display/intel_lvds.c | 11 ++++++----- drivers/gpu/drm/i915/display/intel_pps.c | 12 ++++++------ drivers/gpu/drm/i915/display/intel_pps_regs.h | 2 +- 4 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c index cdc9dadb578d..072ef1d62bda 100644 --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c @@ -353,14 +353,14 @@ static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv, case MIPI_AVDD_EN_2: index = gpio == MIPI_AVDD_EN_1 ? 0 : 1; - intel_de_rmw(dev_priv, PP_CONTROL(index), PANEL_POWER_ON, + intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, index), PANEL_POWER_ON, value ? PANEL_POWER_ON : 0); break; case MIPI_BKLT_EN_1: case MIPI_BKLT_EN_2: index = gpio == MIPI_BKLT_EN_1 ? 0 : 1; - intel_de_rmw(dev_priv, PP_CONTROL(index), EDP_BLC_ENABLE, + intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, index), EDP_BLC_ENABLE, value ? EDP_BLC_ENABLE : 0); break; case MIPI_AVEE_EN_1: diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index eec0dab3c3b2..367b3528e141 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -161,7 +161,8 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, { u32 val; - pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; + pps->powerdown_on_reset = intel_de_read(dev_priv, + PP_CONTROL(dev_priv, 0)) & PANEL_POWER_RESET; val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); @@ -209,12 +210,12 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, { u32 val; - val = intel_de_read(dev_priv, PP_CONTROL(0)); + val = intel_de_read(dev_priv, PP_CONTROL(dev_priv, 0)); drm_WARN_ON(&dev_priv->drm, (val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); if (pps->powerdown_on_reset) val |= PANEL_POWER_RESET; - intel_de_write(dev_priv, PP_CONTROL(0), val); + intel_de_write(dev_priv, PP_CONTROL(dev_priv, 0), val); intel_de_write(dev_priv, PP_ON_DELAYS(0), REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | @@ -321,7 +322,7 @@ static void intel_enable_lvds(struct intel_atomic_state *state, intel_de_rmw(dev_priv, lvds_encoder->reg, 0, LVDS_PORT_EN); - intel_de_rmw(dev_priv, PP_CONTROL(0), 0, PANEL_POWER_ON); + intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), 0, PANEL_POWER_ON); intel_de_posting_read(dev_priv, lvds_encoder->reg); if (intel_de_wait_for_set(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 5000)) @@ -339,7 +340,7 @@ static void intel_disable_lvds(struct intel_atomic_state *state, struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - intel_de_rmw(dev_priv, PP_CONTROL(0), PANEL_POWER_ON, 0); + intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, 0), PANEL_POWER_ON, 0); if (intel_de_wait_for_clear(dev_priv, PP_STATUS(dev_priv, 0), PP_ON, 1000)) drm_err(&dev_priv->drm, "timed out waiting for panel to power off\n"); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 9aa08b525810..6b185424271d 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -277,7 +277,7 @@ static bool pps_has_pp_on(struct drm_i915_private *dev_priv, int pps_idx) static bool pps_has_vdd_on(struct drm_i915_private *dev_priv, int pps_idx) { - return intel_de_read(dev_priv, PP_CONTROL(pps_idx)) & EDP_FORCE_VDD; + return intel_de_read(dev_priv, PP_CONTROL(dev_priv, pps_idx)) & EDP_FORCE_VDD; } static bool pps_any(struct drm_i915_private *dev_priv, int pps_idx) @@ -491,7 +491,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, else pps_idx = intel_dp->pps.pps_idx; - regs->pp_ctrl = PP_CONTROL(pps_idx); + regs->pp_ctrl = PP_CONTROL(dev_priv, pps_idx); regs->pp_stat = PP_STATUS(dev_priv, pps_idx); regs->pp_on = PP_ON_DELAYS(pps_idx); regs->pp_off = PP_OFF_DELAYS(pps_idx); @@ -1656,7 +1656,7 @@ void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) pps_num = intel_num_pps(dev_priv); for (pps_idx = 0; pps_idx < pps_num; pps_idx++) - intel_de_rmw(dev_priv, PP_CONTROL(pps_idx), + intel_de_rmw(dev_priv, PP_CONTROL(dev_priv, pps_idx), PANEL_UNLOCK_MASK, PANEL_UNLOCK_REGS); } @@ -1714,7 +1714,7 @@ void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) if (HAS_PCH_SPLIT(dev_priv)) { u32 port_sel; - pp_reg = PP_CONTROL(0); + pp_reg = PP_CONTROL(dev_priv, 0); port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; switch (port_sel) { @@ -1736,12 +1736,12 @@ void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) } } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { /* presumably write lock depends on pipe, not port select */ - pp_reg = PP_CONTROL(pipe); + pp_reg = PP_CONTROL(dev_priv, pipe); panel_pipe = pipe; } else { u32 port_sel; - pp_reg = PP_CONTROL(0); + pp_reg = PP_CONTROL(dev_priv, 0); port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; drm_WARN_ON(&dev_priv->drm, diff --git a/drivers/gpu/drm/i915/display/intel_pps_regs.h b/drivers/gpu/drm/i915/display/intel_pps_regs.h index 06bdf766b749..e52d87b9f0ad 100644 --- a/drivers/gpu/drm/i915/display/intel_pps_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pps_regs.h @@ -45,7 +45,7 @@ #define PP_SEQUENCE_STATE_RESET REG_FIELD_PREP(PP_SEQUENCE_STATE_MASK, 0xf) #define _PP_CONTROL 0x61204 -#define PP_CONTROL(pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_CONTROL) +#define PP_CONTROL(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_CONTROL) #define PANEL_UNLOCK_MASK REG_GENMASK(31, 16) #define PANEL_UNLOCK_REGS REG_FIELD_PREP(PANEL_UNLOCK_MASK, 0xabcd) #define BXT_POWER_CYCLE_DELAY_MASK REG_GENMASK(8, 4) -- cgit From dc368a87457abf53178af774852b5a839efabf4a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 13:42:00 +0300 Subject: drm/i915: pass dev_priv explicitly to PP_ON_DELAYS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PP_ON_DELAYS register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/0fc707fde15bc11893b6e1d5038162368e3a2b8d.1716806471.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_lvds.c | 4 ++-- drivers/gpu/drm/i915/display/intel_pps.c | 10 +++++----- drivers/gpu/drm/i915/display/intel_pps_regs.h | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 367b3528e141..b7b4d78ec06a 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -164,7 +164,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(dev_priv, 0)) & PANEL_POWER_RESET; - val = intel_de_read(dev_priv, PP_ON_DELAYS(0)); + val = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0)); pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); @@ -217,7 +217,7 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, val |= PANEL_POWER_RESET; intel_de_write(dev_priv, PP_CONTROL(dev_priv, 0), val); - intel_de_write(dev_priv, PP_ON_DELAYS(0), + intel_de_write(dev_priv, PP_ON_DELAYS(dev_priv, 0), REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 6b185424271d..803a1e353c06 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -292,7 +292,7 @@ vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, enum pipe pipe; for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { - u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(pipe)) & + u32 port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, pipe)) & PANEL_PORT_SELECT_MASK; if (port_sel != PANEL_PORT_SELECT_VLV(port)) @@ -493,7 +493,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, regs->pp_ctrl = PP_CONTROL(dev_priv, pps_idx); regs->pp_stat = PP_STATUS(dev_priv, pps_idx); - regs->pp_on = PP_ON_DELAYS(pps_idx); + regs->pp_on = PP_ON_DELAYS(dev_priv, pps_idx); regs->pp_off = PP_OFF_DELAYS(pps_idx); /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ @@ -1111,7 +1111,7 @@ static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); enum pipe pipe = intel_dp->pps.pps_pipe; - i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); + i915_reg_t pp_on_reg = PP_ON_DELAYS(dev_priv, pipe); drm_WARN_ON(&dev_priv->drm, intel_dp->pps.active_pipe != INVALID_PIPE); @@ -1715,7 +1715,7 @@ void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) u32 port_sel; pp_reg = PP_CONTROL(dev_priv, 0); - port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; + port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0)) & PANEL_PORT_SELECT_MASK; switch (port_sel) { case PANEL_PORT_SELECT_LVDS: @@ -1742,7 +1742,7 @@ void assert_pps_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) u32 port_sel; pp_reg = PP_CONTROL(dev_priv, 0); - port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; + port_sel = intel_de_read(dev_priv, PP_ON_DELAYS(dev_priv, 0)) & PANEL_PORT_SELECT_MASK; drm_WARN_ON(&dev_priv->drm, port_sel != PANEL_PORT_SELECT_LVDS); diff --git a/drivers/gpu/drm/i915/display/intel_pps_regs.h b/drivers/gpu/drm/i915/display/intel_pps_regs.h index e52d87b9f0ad..8a6acefba7fe 100644 --- a/drivers/gpu/drm/i915/display/intel_pps_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pps_regs.h @@ -55,7 +55,7 @@ #define PANEL_POWER_ON REG_BIT(0) #define _PP_ON_DELAYS 0x61208 -#define PP_ON_DELAYS(pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_ON_DELAYS) +#define PP_ON_DELAYS(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_ON_DELAYS) #define PANEL_PORT_SELECT_MASK REG_GENMASK(31, 30) #define PANEL_PORT_SELECT_LVDS REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 0) #define PANEL_PORT_SELECT_DPA REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, 1) -- cgit From 07776fb3c8b37a45a106cc501423ff9e8521ace5 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 13:42:01 +0300 Subject: drm/i915: pass dev_priv explicitly to PP_OFF_DELAYS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PP_OFF_DELAYS register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/122e143ff6a1c1016534dae0ba28fde0b15e3e76.1716806471.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_lvds.c | 4 ++-- drivers/gpu/drm/i915/display/intel_pps.c | 2 +- drivers/gpu/drm/i915/display/intel_pps_regs.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index b7b4d78ec06a..3adfe93794ef 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -169,7 +169,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); - val = intel_de_read(dev_priv, PP_OFF_DELAYS(0)); + val = intel_de_read(dev_priv, PP_OFF_DELAYS(dev_priv, 0)); pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); @@ -222,7 +222,7 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); - intel_de_write(dev_priv, PP_OFF_DELAYS(0), + intel_de_write(dev_priv, PP_OFF_DELAYS(dev_priv, 0), REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 803a1e353c06..2cc6d5f209e6 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -494,7 +494,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, regs->pp_ctrl = PP_CONTROL(dev_priv, pps_idx); regs->pp_stat = PP_STATUS(dev_priv, pps_idx); regs->pp_on = PP_ON_DELAYS(dev_priv, pps_idx); - regs->pp_off = PP_OFF_DELAYS(pps_idx); + regs->pp_off = PP_OFF_DELAYS(dev_priv, pps_idx); /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv) || diff --git a/drivers/gpu/drm/i915/display/intel_pps_regs.h b/drivers/gpu/drm/i915/display/intel_pps_regs.h index 8a6acefba7fe..b1ccc54410ce 100644 --- a/drivers/gpu/drm/i915/display/intel_pps_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pps_regs.h @@ -66,7 +66,7 @@ #define PANEL_LIGHT_ON_DELAY_MASK REG_GENMASK(12, 0) #define _PP_OFF_DELAYS 0x6120C -#define PP_OFF_DELAYS(pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_OFF_DELAYS) +#define PP_OFF_DELAYS(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_OFF_DELAYS) #define PANEL_POWER_DOWN_DELAY_MASK REG_GENMASK(28, 16) #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) -- cgit From b758cd8057e9f982498efd73b3176987e996e5de Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 13:42:02 +0300 Subject: drm/i915: pass dev_priv explicitly to PP_DIVISOR Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PP_DIVISOR register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/28e9f7e3570c15ac5c229048ec0def2e4a667ffc.1716806471.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_lvds.c | 4 ++-- drivers/gpu/drm/i915/display/intel_pps.c | 2 +- drivers/gpu/drm/i915/display/intel_pps_regs.h | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 3adfe93794ef..891777481dd9 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -173,7 +173,7 @@ static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); - val = intel_de_read(dev_priv, PP_DIVISOR(0)); + val = intel_de_read(dev_priv, PP_DIVISOR(dev_priv, 0)); pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); /* @@ -226,7 +226,7 @@ static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); - intel_de_write(dev_priv, PP_DIVISOR(0), + intel_de_write(dev_priv, PP_DIVISOR(dev_priv, 0), REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); } diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 2cc6d5f209e6..73046ef58d8e 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -501,7 +501,7 @@ static void intel_pps_get_registers(struct intel_dp *intel_dp, INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) regs->pp_div = INVALID_MMIO_REG; else - regs->pp_div = PP_DIVISOR(pps_idx); + regs->pp_div = PP_DIVISOR(dev_priv, pps_idx); } static i915_reg_t diff --git a/drivers/gpu/drm/i915/display/intel_pps_regs.h b/drivers/gpu/drm/i915/display/intel_pps_regs.h index b1ccc54410ce..8f9dbfab9523 100644 --- a/drivers/gpu/drm/i915/display/intel_pps_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pps_regs.h @@ -71,7 +71,7 @@ #define PANEL_LIGHT_OFF_DELAY_MASK REG_GENMASK(12, 0) #define _PP_DIVISOR 0x61210 -#define PP_DIVISOR(pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_DIVISOR) +#define PP_DIVISOR(dev_priv, pps_idx) _MMIO_PPS(dev_priv, pps_idx, _PP_DIVISOR) #define PP_REFERENCE_DIVIDER_MASK REG_GENMASK(31, 8) #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) -- cgit From cc13f2937725cf0c5fb67008959125d42da3fb80 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:43 +0300 Subject: drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the HSW_TVIDEO_DIP_CTL register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/7261777d02eeb94093ed3510989c6809c66d50da.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- drivers/gpu/drm/i915/display/intel_hdmi.c | 7 ++++--- drivers/gpu/drm/i915/display/intel_lspcon.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 5 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c0a3b6d50681..4fa977f1e6c4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4353,7 +4353,8 @@ void intel_dp_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); + i915_reg_t reg = HSW_TVIDEO_DIP_CTL(dev_priv, + crtc_state->cpu_transcoder); u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 9ac670a40bc1..4557acdd8b3c 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -507,7 +507,7 @@ void hsw_write_infoframe(struct intel_encoder *encoder, const u32 *data = frame; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder); + i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(dev_priv, cpu_transcoder); int data_size; int i; u32 val = intel_de_read(dev_priv, ctl_reg); @@ -562,7 +562,7 @@ static u32 hsw_infoframes_enabled(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); u32 val = intel_de_read(dev_priv, - HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); + HSW_TVIDEO_DIP_CTL(dev_priv, pipe_config->cpu_transcoder)); u32 mask; mask = (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW | @@ -1216,7 +1216,8 @@ static void hsw_set_infoframes(struct intel_encoder *encoder, const struct drm_connector_state *conn_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); + i915_reg_t reg = HSW_TVIDEO_DIP_CTL(dev_priv, + crtc_state->cpu_transcoder); u32 val = intel_de_read(dev_priv, reg); assert_hdmi_transcoder_func_disabled(dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_lspcon.c b/drivers/gpu/drm/i915/display/intel_lspcon.c index 1d048fa98561..8b26354d6e53 100644 --- a/drivers/gpu/drm/i915/display/intel_lspcon.c +++ b/drivers/gpu/drm/i915/display/intel_lspcon.c @@ -641,7 +641,7 @@ u32 lspcon_infoframes_enabled(struct intel_encoder *encoder, if (lspcon->hdr_supported) { tmp = intel_de_read(dev_priv, - HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder)); + HSW_TVIDEO_DIP_CTL(dev_priv, pipe_config->cpu_transcoder)); mask = VIDEO_DIP_ENABLE_GMP_HSW; if (tmp & mask) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 29f69ad8f704..0331fdd61f33 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3475,7 +3475,7 @@ #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 -#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) +#define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) #define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index b4d5592b18df..027cd273d775 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -509,9 +509,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_MULT(TRANSCODER_A)); MMIO_D(TRANS_MULT(TRANSCODER_B)); MMIO_D(TRANS_MULT(TRANSCODER_C)); - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A)); - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B)); - MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C)); + MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_A)); + MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_B)); + MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_C)); MMIO_D(SFUSE_STRAP); MMIO_D(SBI_ADDR); MMIO_D(SBI_DATA); -- cgit From 093acd131600ebf3d581a55ec0f20269abc8f588 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:44 +0300 Subject: drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_GCP Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the HSW_TVIDEO_DIP_GCP register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/36f0b90f07c7aa78e88fadb375359df39ecd0a77.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 4557acdd8b3c..18a95d7f2771 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -986,7 +986,7 @@ static bool intel_hdmi_set_gcp_infoframe(struct intel_encoder *encoder, return false; if (HAS_DDI(dev_priv)) - reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); + reg = HSW_TVIDEO_DIP_GCP(dev_priv, crtc_state->cpu_transcoder); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); else if (HAS_PCH_SPLIT(dev_priv)) @@ -1011,7 +1011,7 @@ void intel_hdmi_read_gcp_infoframe(struct intel_encoder *encoder, return; if (HAS_DDI(dev_priv)) - reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder); + reg = HSW_TVIDEO_DIP_GCP(dev_priv, crtc_state->cpu_transcoder); else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) reg = VLV_TVIDEO_DIP_GCP(crtc->pipe); else if (HAS_PCH_SPLIT(dev_priv)) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0331fdd61f33..ff520171ac16 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3476,7 +3476,7 @@ #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 #define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) -#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) +#define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) #define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 027cd273d775..349578cc0fc8 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -1235,9 +1235,9 @@ static int iterate_bxt_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(BXT_DSI_PLL_ENABLE); MMIO_D(GEN9_CLKGATE_DIS_0); MMIO_D(GEN9_CLKGATE_DIS_4); - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_A)); - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_B)); - MMIO_D(HSW_TVIDEO_DIP_GCP(TRANSCODER_C)); + MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_A)); + MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_B)); + MMIO_D(HSW_TVIDEO_DIP_GCP(dev_priv, TRANSCODER_C)); MMIO_D(RC6_CTX_BASE); MMIO_D(GEN8_PUSHBUS_CONTROL); MMIO_D(GEN8_PUSHBUS_ENABLE); -- cgit From 7e6e5519bb998acdf8bc755718ff4980a8e3be6d Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:45 +0300 Subject: drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_AVI_DATA Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the HSW_TVIDEO_DIP_AVI_DATA register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/113e40bf4d42a38c1be09a7ce0159dc828356ebc.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 18a95d7f2771..5f77d1cf5cef 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -173,7 +173,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, case DP_SDP_PPS: return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_AVI: - return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i); + return HSW_TVIDEO_DIP_AVI_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_SPD: return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_VENDOR: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ff520171ac16..707d47955673 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3477,7 +3477,7 @@ #define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) #define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) -#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) +#define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) -- cgit From 0f1fe26137f12f9208bf2e0bed6b84def1f9c82a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:46 +0300 Subject: drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_VS_DATA Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the HSW_TVIDEO_DIP_VS_DATA register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/6f676d9b2bce0d4911e888c5efeacaddef98579c.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 5f77d1cf5cef..a5287b651eb5 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -177,7 +177,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, case HDMI_INFOFRAME_TYPE_SPD: return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_VENDOR: - return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i); + return HSW_TVIDEO_DIP_VS_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_DRM: return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); default: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 707d47955673..afb0a0a0d322 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3478,7 +3478,7 @@ #define HSW_TVIDEO_DIP_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) #define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) #define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) -#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) +#define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) -- cgit From 16645d59b9074bed42cd9d2eef5e17e687258762 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:47 +0300 Subject: drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_SPD_DATA Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the HSW_TVIDEO_DIP_SPD_DATA register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/97412857f7580994ea9c9c0c8f5f778261f7e71b.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a5287b651eb5..cd54973621c3 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -175,7 +175,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, case HDMI_INFOFRAME_TYPE_AVI: return HSW_TVIDEO_DIP_AVI_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_SPD: - return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i); + return HSW_TVIDEO_DIP_SPD_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_VENDOR: return HSW_TVIDEO_DIP_VS_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_DRM: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index afb0a0a0d322..df4112a2c521 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3479,7 +3479,7 @@ #define HSW_TVIDEO_DIP_GCP(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) #define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) -#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) +#define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) -- cgit From 5c99db622a12ad915a0e4ce201de8aaac06ac3eb Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:48 +0300 Subject: drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_GMP_DATA Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the HSW_TVIDEO_DIP_GMP_DATA register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/fff766dca0e790a801fb7d1ad78980da69d3b9f7.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index cd54973621c3..17c038013b34 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -165,7 +165,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, { switch (type) { case HDMI_PACKET_TYPE_GAMUT_METADATA: - return HSW_TVIDEO_DIP_GMP_DATA(cpu_transcoder, i); + return HSW_TVIDEO_DIP_GMP_DATA(dev_priv, cpu_transcoder, i); case DP_SDP_VSC: return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); case DP_SDP_ADAPTIVE_SYNC: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index df4112a2c521..779691365125 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3480,7 +3480,7 @@ #define HSW_TVIDEO_DIP_AVI_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) -#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) +#define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) -- cgit From 5159e72a930ee647d5addd709d4a1592b74cf535 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:49 +0300 Subject: drm/i915: pass dev_priv explicitly to HSW_TVIDEO_DIP_VSC_DATA Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the HSW_TVIDEO_DIP_VSC_DATA register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/2f0ed82eb9c759feb3978e38f3b2835f359d6d1f.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 17c038013b34..f7605ff547a3 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -167,7 +167,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, case HDMI_PACKET_TYPE_GAMUT_METADATA: return HSW_TVIDEO_DIP_GMP_DATA(dev_priv, cpu_transcoder, i); case DP_SDP_VSC: - return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i); + return HSW_TVIDEO_DIP_VSC_DATA(dev_priv, cpu_transcoder, i); case DP_SDP_ADAPTIVE_SYNC: return ADL_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i); case DP_SDP_PPS: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 779691365125..1cb60a2ffa54 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3481,7 +3481,7 @@ #define HSW_TVIDEO_DIP_VS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) -#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) +#define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) #define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) -- cgit From cf8361def4f6c09063061da945ddf560c54ac693 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:50 +0300 Subject: drm/i915: pass dev_priv explicitly to GLK_TVIDEO_DIP_DRM_DATA Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the GLK_TVIDEO_DIP_DRM_DATA register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/bab2d0385b748c34bec262afaf491be881990033.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index f7605ff547a3..a26ce1e4befd 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -179,7 +179,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, case HDMI_INFOFRAME_TYPE_VENDOR: return HSW_TVIDEO_DIP_VS_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_DRM: - return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i); + return GLK_TVIDEO_DIP_DRM_DATA(dev_priv, cpu_transcoder, i); default: MISSING_CASE(type); return INVALID_MMIO_REG; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1cb60a2ffa54..4645476bb29e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3482,7 +3482,7 @@ #define HSW_TVIDEO_DIP_SPD_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) -#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) +#define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) /*ADLP and later: */ -- cgit From a154f9ae877751f4ba2c81a5fd0fa1dea500ba31 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:51 +0300 Subject: drm/i915: pass dev_priv explicitly to ICL_VIDEO_DIP_PPS_DATA Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ICL_VIDEO_DIP_PPS_DATA register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/fb7c308dd655d1bc4af44ab9c88b5f5245d8a5d6.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index a26ce1e4befd..184fec37211b 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -171,7 +171,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, case DP_SDP_ADAPTIVE_SYNC: return ADL_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i); case DP_SDP_PPS: - return ICL_VIDEO_DIP_PPS_DATA(cpu_transcoder, i); + return ICL_VIDEO_DIP_PPS_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_AVI: return HSW_TVIDEO_DIP_AVI_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_SPD: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4645476bb29e..5fe0a0c6514f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3483,7 +3483,7 @@ #define HSW_TVIDEO_DIP_GMP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) #define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) #define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) -#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) +#define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) /*ADLP and later: */ #define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans,\ -- cgit From b31a97af9f6c37fda9aceebeaf2ddb486479c6bb Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:52 +0300 Subject: drm/i915: pass dev_priv explicitly to ICL_VIDEO_DIP_PPS_ECC Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ICL_VIDEO_DIP_PPS_ECC register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/620fd2da6eea334bf9a5d1b93717ca1176c4203e.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5fe0a0c6514f..57e805dcf4c6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3484,7 +3484,7 @@ #define HSW_TVIDEO_DIP_VSC_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) #define GLK_TVIDEO_DIP_DRM_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) -#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) +#define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) /*ADLP and later: */ #define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans,\ _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) -- cgit From c34474b48cf12ee806132c269ccba1395b10f724 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 27 May 2024 14:10:53 +0300 Subject: drm/i915: pass dev_priv explicitly to ADL_TVIDEO_DIP_AS_SDP_DATA Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ADL_TVIDEO_DIP_AS_SDP_DATA register macro. Reviewed-by: Chaitanya Kumar Borah Link: https://patchwork.freedesktop.org/patch/msgid/75a4f817f7c73277b2b8021275ccb9a4f3716953.1716808214.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 184fec37211b..3767be0bdba8 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -169,7 +169,7 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv, case DP_SDP_VSC: return HSW_TVIDEO_DIP_VSC_DATA(dev_priv, cpu_transcoder, i); case DP_SDP_ADAPTIVE_SYNC: - return ADL_TVIDEO_DIP_AS_SDP_DATA(cpu_transcoder, i); + return ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, cpu_transcoder, i); case DP_SDP_PPS: return ICL_VIDEO_DIP_PPS_DATA(dev_priv, cpu_transcoder, i); case HDMI_INFOFRAME_TYPE_AVI: diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 57e805dcf4c6..be57812a6b07 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3486,7 +3486,7 @@ #define ICL_VIDEO_DIP_PPS_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) #define ICL_VIDEO_DIP_PPS_ECC(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) /*ADLP and later: */ -#define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans,\ +#define ADL_TVIDEO_DIP_AS_SDP_DATA(dev_priv, trans, i) _MMIO_TRANS2(dev_priv, trans,\ _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) #define _HSW_STEREO_3D_CTL_A 0x70020 -- cgit From 73baf72eb193c6a30d883a380f2f8d26fd6d5ff9 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 28 May 2024 14:44:51 +0300 Subject: drm/i915/psr: Store pr_dpcd in intel_dp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We need pr_dpcd contents for early transport validity check on eDP Panel Replay and in debugfs interface to dump out panel early transport capability. Also remove unnecessarily printing out "Panel replay is not supported by panel" v2: commit message modified Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-2-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 19 ++++++------------- 2 files changed, 7 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9678c2b157f6..6fbfe8a18f45 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1743,6 +1743,7 @@ struct intel_dp { bool use_max_params; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; + u8 pr_dpcd; u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f59238d3d484..08d3c8c81585 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -559,20 +559,10 @@ exit: static void _panel_replay_init_dpcd(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - u8 pr_dpcd = 0; - - intel_dp->psr.sink_panel_replay_support = false; - drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, &pr_dpcd); - - if (!(pr_dpcd & DP_PANEL_REPLAY_SUPPORT)) { - drm_dbg_kms(&i915->drm, - "Panel replay is not supported by panel\n"); - return; - } intel_dp->psr.sink_panel_replay_support = true; - if (pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT) + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SU_SUPPORT) intel_dp->psr.sink_panel_replay_su_support = true; drm_dbg_kms(&i915->drm, @@ -630,10 +620,13 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp) void intel_psr_init_dpcd(struct intel_dp *intel_dp) { - _panel_replay_init_dpcd(intel_dp); - drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT, intel_dp->psr_dpcd, sizeof(intel_dp->psr_dpcd)); + drm_dp_dpcd_readb(&intel_dp->aux, DP_PANEL_REPLAY_CAP, + &intel_dp->pr_dpcd); + + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_SUPPORT) + _panel_replay_init_dpcd(intel_dp); if (intel_dp->psr_dpcd[0]) _psr_init_dpcd(intel_dp); -- cgit From 2f602531db4c5b522073aff1b09d2d5408352a1c Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 28 May 2024 14:44:52 +0300 Subject: drm/panel replay: Add edp1.5 Panel Replay bits and register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add PANEL_REPLAY_CONFIGURATION_2 register and some missing Panel Replay bits. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Acked-by: Maxime Ripard Acked-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-3-jouni.hogander@intel.com --- include/drm/display/drm_dp.h | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 906949ca3cee..79bde372b152 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -544,9 +544,10 @@ /* DFP Capability Extension */ #define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0a3 /* 2.0 */ -#define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */ -# define DP_PANEL_REPLAY_SUPPORT (1 << 0) -# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) +#define DP_PANEL_REPLAY_CAP 0x0b0 /* DP 2.0 */ +# define DP_PANEL_REPLAY_SUPPORT (1 << 0) +# define DP_PANEL_REPLAY_SU_SUPPORT (1 << 1) +# define DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT (1 << 2) /* eDP 1.5 */ #define DP_PANEL_PANEL_REPLAY_CAPABILITY 0xb1 # define DP_PANEL_PANEL_REPLAY_SU_GRANULARITY_REQUIRED (1 << 5) @@ -734,11 +735,20 @@ #define PANEL_REPLAY_CONFIG 0x1b0 /* DP 2.0 */ # define DP_PANEL_REPLAY_ENABLE (1 << 0) +# define DP_PANEL_REPLAY_VSC_SDP_CRC_EN (1 << 1) /* eDP 1.5 */ # define DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN (1 << 3) # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) # define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) # define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) +#define PANEL_REPLAY_CONFIG2 0x1b1 /* eDP 1.5 */ +# define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED (1 << 0) +# define DP_PANEL_REPLAY_CRC_VERIFICATION (1 << 1) +# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_EN (1 << 2) +# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_SHIFT 3 +# define DP_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_VAL_SEL_MASK (0xf << 3) +# define DP_PANEL_REPLAY_SU_REGION_SCANLINE_CAPTURE (1 << 7) + #define DP_PAYLOAD_ALLOCATE_SET 0x1c0 #define DP_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1c1 #define DP_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1c2 -- cgit From 1566b50a439cb8f5b50c7f1e6543e38d1e1848f6 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 28 May 2024 14:44:53 +0300 Subject: drm/i915/psr: Move printing sink PSR support to own function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel_psr_status has grown and is about to grow even. Let's split it a bit and move printing sink psr support to an own function. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-4-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 08d3c8c81585..943de3ca39c2 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3590,15 +3590,10 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) seq_printf(m, "Source PSR/PanelReplay status: %s [0x%08x]\n", status, val); } -static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) +static void intel_psr_sink_capability(struct intel_dp *intel_dp, + struct seq_file *m) { - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - enum transcoder cpu_transcoder = intel_dp->psr.transcoder; struct intel_psr *psr = &intel_dp->psr; - intel_wakeref_t wakeref; - const char *status; - bool enabled; - u32 val; seq_printf(m, "Sink support: PSR = %s", str_yes_no(psr->sink_support)); @@ -3608,6 +3603,19 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); seq_printf(m, ", Panel Replay Selective Update = %s\n", str_yes_no(psr->sink_panel_replay_su_support)); +} + +static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + struct intel_psr *psr = &intel_dp->psr; + intel_wakeref_t wakeref; + const char *status; + bool enabled; + u32 val; + + intel_psr_sink_capability(intel_dp, m); if (!(psr->sink_support || psr->sink_panel_replay_support)) return 0; -- cgit From f0faeb2e701ca51115ff4f025152dfc685f9ca07 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 28 May 2024 14:44:54 +0300 Subject: drm/i915/psr: Move printing PSR mode to own function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel_psr_status has grown and is about to grow even. Let's split it a bit and move printing PSR mode to an own function. v2: s/intel_psr_psr_mode/intel_psr_print_mode/ Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-5-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 26 +++++++++++++++++--------- 1 file changed, 17 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 943de3ca39c2..dfd45f6d7edd 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3605,13 +3605,28 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp, str_yes_no(psr->sink_panel_replay_su_support)); } +static void intel_psr_print_mode(struct intel_dp *intel_dp, + struct seq_file *m) +{ + struct intel_psr *psr = &intel_dp->psr; + const char *status; + + if (psr->panel_replay_enabled) + status = psr->sel_update_enabled ? "Panel Replay Selective Update Enabled" : + "Panel Replay Enabled"; + else if (psr->enabled) + status = psr->sel_update_enabled ? "PSR2" : "PSR1"; + else + status = "disabled"; + seq_printf(m, "PSR mode: %s\n", status); +} + static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; struct intel_psr *psr = &intel_dp->psr; intel_wakeref_t wakeref; - const char *status; bool enabled; u32 val; @@ -3623,14 +3638,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm); mutex_lock(&psr->lock); - if (psr->panel_replay_enabled) - status = psr->sel_update_enabled ? "Panel Replay Selective Update Enabled" : - "Panel Replay Enabled"; - else if (psr->enabled) - status = psr->sel_update_enabled ? "PSR2" : "PSR1"; - else - status = "disabled"; - seq_printf(m, "PSR mode: %s\n", status); + intel_psr_print_mode(intel_dp, m); if (!psr->enabled) { seq_printf(m, "PSR sink not reliable: %s\n", -- cgit From fec7efe7bf2d7fd7824a5d0420e13d4a03bbfb47 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 28 May 2024 14:44:55 +0300 Subject: drm/i915/psr: modify psr status debugfs to support eDP Panel Replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some PSR2_CTL bits are applicable for eDP panel replay as well. Dump this register for eDP Panel Replay as well. Bspec: 68920 Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240528114455.175961-6-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index dfd45f6d7edd..19f8ac12f995 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3628,7 +3628,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) struct intel_psr *psr = &intel_dp->psr; intel_wakeref_t wakeref; bool enabled; - u32 val; + u32 val, psr2_ctl; intel_psr_sink_capability(intel_dp, m); @@ -3649,6 +3649,12 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) if (psr->panel_replay_enabled) { val = intel_de_read(dev_priv, TRANS_DP2_CTL(cpu_transcoder)); + + if (intel_dp_is_edp(intel_dp)) + psr2_ctl = intel_de_read(dev_priv, + EDP_PSR2_CTL(dev_priv, + cpu_transcoder)); + enabled = val & TRANS_DP2_PANEL_REPLAY_ENABLE; } else if (psr->sel_update_enabled) { val = intel_de_read(dev_priv, @@ -3660,6 +3666,9 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) } seq_printf(m, "Source PSR/PanelReplay ctl: %s [0x%08x]\n", str_enabled_disabled(enabled), val); + if (psr->panel_replay_enabled && intel_dp_is_edp(intel_dp)) + seq_printf(m, "PSR2_CTL: 0x%08x\n", + psr2_ctl); psr_source_status(intel_dp, m); seq_printf(m, "Busy frontbuffer bits: 0x%08x\n", psr->busy_frontbuffer_bits); -- cgit From f008baf08d3eb778c19890bff81869d6d3481bd1 Mon Sep 17 00:00:00 2001 From: Suraj Kandpal Date: Mon, 27 May 2024 10:51:19 +0530 Subject: drm/i915/hdcp: Fix IS_METEORLAKE usage for HDCP line rekeying Replace IS_METEORLAKE usage with a more appropriate macro. While we are at it also add the stepping restrictions for other platforms. Fixes: 6a3691ca4799 ("drm/i915/hdcp: Disable HDCP Line Rekeying for HDCP2.2 on HDMI") Signed-off-by: Suraj Kandpal Reviewed-by: Dnyaneshwar Bhadane Link: https://patchwork.freedesktop.org/patch/msgid/20240527052118.1624216-2-suraj.kandpal@intel.com --- drivers/gpu/drm/i915/display/intel_hdcp.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 02cbbbfd8e25..5767070248bb 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -42,10 +42,11 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, return; if (DISPLAY_VER(dev_priv) >= 14) { - if (IS_METEORLAKE(dev_priv)) + if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_D0, STEP_FOREVER)) intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(hdcp->cpu_transcoder), 0, HDCP_LINE_REKEY_DISABLE); - else + else if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) || + IS_DISPLAY_IP_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER)) intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder), 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE); } -- cgit From 5575d7b661887760f385e8c68913da5cf202a8cf Mon Sep 17 00:00:00 2001 From: Mika Kahola Date: Thu, 23 May 2024 16:46:48 +0300 Subject: drm/i915/display: Revert "drm/i915/display: Skip C10 state verification in case of fastset" This reverts commit a1d91c6e989d0e66b89aa911f2cd459d7bdebbe5. Reviewed-by: Jani Nikula Signed-off-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20240523134649.31452-2-mika.kahola@intel.com --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 1b1ebafa49e8..c9e5bb6ecfd7 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -3243,9 +3243,6 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state *state, const struct intel_c10pll_state *mpllb_sw_state = &state->dpll_hw_state.cx0pll.c10; int i; - if (intel_crtc_needs_fastset(state)) - return; - for (i = 0; i < ARRAY_SIZE(mpllb_sw_state->pll); i++) { u8 expected = mpllb_sw_state->pll[i]; -- cgit From 45fe957ae769b9122f4a40f2528c516132fe7e3d Mon Sep 17 00:00:00 2001 From: Mika Kahola Date: Thu, 23 May 2024 16:46:49 +0300 Subject: drm/i915/display: Add compare config for MTL+ platforms Currently, we may bump into pll mismatch errors during the state verification stage. This happens when we try to use fastset instead of full modeset. Hence, we would need to add a check for pipe configuration to ensure that the sw and the hw configuration will match. In case of hw and sw mismatch, we would need to disable fastset and use full modeset instead. v2: Fix C10 error on PLL comparison (BAT) Use memcmp instead of fixed loops for pll config comparison (Jani) Clean up and use intel_cx0pll_dump_hw_state() to dump pll information (Jani) Reviewed-by: Jani Nikula Signed-off-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20240523134649.31452-3-mika.kahola@intel.com --- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 77 ++++++++++++++++++++++++--- drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-- drivers/gpu/drm/i915/display/intel_display.c | 33 ++++++++++++ drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 1 + 4 files changed, 109 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index c9e5bb6ecfd7..41f684c970dc 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -2038,6 +2038,7 @@ static int intel_c10pll_calc_state(struct intel_crtc_state *crtc_state, if (crtc_state->port_clock == tables[i]->clock) { crtc_state->dpll_hw_state.cx0pll.c10 = *tables[i]; intel_c10pll_update_pll(crtc_state, encoder); + crtc_state->dpll_hw_state.cx0pll.use_c10 = true; return 0; } @@ -2105,8 +2106,8 @@ static void intel_c10_pll_program(struct drm_i915_private *i915, MB_WRITE_COMMITTED); } -void intel_c10pll_dump_hw_state(struct drm_i915_private *i915, - const struct intel_c10pll_state *hw_state) +static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915, + const struct intel_c10pll_state *hw_state) { bool fracen; int i; @@ -2277,6 +2278,7 @@ static int intel_c20pll_calc_state(struct intel_crtc_state *crtc_state, for (i = 0; tables[i]; i++) { if (crtc_state->port_clock == tables[i]->clock) { crtc_state->dpll_hw_state.cx0pll.c20 = *tables[i]; + crtc_state->dpll_hw_state.cx0pll.use_c10 = false; return 0; } } @@ -2410,8 +2412,8 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder, intel_cx0_phy_transaction_end(encoder, wakeref); } -void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, - const struct intel_c20pll_state *hw_state) +static void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, + const struct intel_c20pll_state *hw_state) { int i; @@ -2430,6 +2432,15 @@ void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, } } +void intel_cx0pll_dump_hw_state(struct drm_i915_private *i915, + const struct intel_cx0pll_state *hw_state) +{ + if (hw_state->use_c10) + intel_c10pll_dump_hw_state(i915, &hw_state->c10); + else + intel_c20pll_dump_hw_state(i915, &hw_state->c20); +} + static u8 intel_c20_get_dp_rate(u32 clock) { switch (clock) { @@ -3266,10 +3277,64 @@ static void intel_c10pll_state_verify(const struct intel_crtc_state *state, void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, struct intel_cx0pll_state *pll_state) { - if (intel_encoder_is_c10phy(encoder)) + pll_state->use_c10 = false; + + if (intel_encoder_is_c10phy(encoder)) { intel_c10pll_readout_hw_state(encoder, &pll_state->c10); - else + pll_state->use_c10 = true; + } else { intel_c20pll_readout_hw_state(encoder, &pll_state->c20); + } +} + +static bool mtl_compare_hw_state_c10(const struct intel_c10pll_state *a, + const struct intel_c10pll_state *b) +{ + if (a->tx != b->tx) + return false; + + if (a->cmn != b->cmn) + return false; + + if (memcmp(&a->pll, &b->pll, sizeof(a->pll)) != 0) + return false; + + return true; +} + +static bool mtl_compare_hw_state_c20(const struct intel_c20pll_state *a, + const struct intel_c20pll_state *b) +{ + if (memcmp(&a->tx, &b->tx, sizeof(a->tx)) != 0) + return false; + + if (memcmp(&a->cmn, &b->cmn, sizeof(a->cmn)) != 0) + return false; + + if (a->tx[0] & C20_PHY_USE_MPLLB) { + if (memcmp(&a->mpllb, &b->mpllb, sizeof(a->mpllb)) != 0) + return false; + } else { + if (memcmp(&a->mplla, &b->mplla, sizeof(a->mplla)) != 0) + return false; + } + + return true; +} + +bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, + const struct intel_cx0pll_state *b) +{ + + if (a->use_c10 != b->use_c10) + return false; + + if (a->use_c10) + return mtl_compare_hw_state_c10(&a->c10, + &b->c10); + else + return mtl_compare_hw_state_c20(&a->c20, + &b->c20); } int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h index 3e03af3e006c..9004b99bb51f 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h @@ -35,12 +35,12 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder, const struct intel_cx0pll_state *pll_state); -void intel_c10pll_dump_hw_state(struct drm_i915_private *dev_priv, - const struct intel_c10pll_state *hw_state); +void intel_cx0pll_dump_hw_state(struct drm_i915_private *dev_priv, + const struct intel_cx0pll_state *hw_state); void intel_cx0pll_state_verify(struct intel_atomic_state *state, struct intel_crtc *crtc); -void intel_c20pll_dump_hw_state(struct drm_i915_private *i915, - const struct intel_c20pll_state *hw_state); +bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a, + const struct intel_cx0pll_state *b); void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state); int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 071ba95a1472..765a7ab04a1c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -67,6 +67,7 @@ #include "intel_crtc.h" #include "intel_crtc_state_dump.h" #include "intel_cursor_regs.h" +#include "intel_cx0_phy.h" #include "intel_ddi.h" #include "intel_de.h" #include "intel_display_driver.h" @@ -4983,6 +4984,24 @@ pipe_config_pll_mismatch(struct drm_printer *p, bool fastset, intel_dpll_dump_hw_state(i915, p, b); } +static void +pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset, + const struct intel_crtc *crtc, + const char *name, + const struct intel_cx0pll_state *a, + const struct intel_cx0pll_state *b) +{ + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + char *chipname = a->use_c10 ? "C10" : "C20"; + + pipe_config_mismatch(p, fastset, crtc, name, chipname); + + drm_printf(p, "expected:\n"); + intel_cx0pll_dump_hw_state(i915, a); + drm_printf(p, "found:\n"); + intel_cx0pll_dump_hw_state(i915, b); +} + bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, const struct intel_crtc_state *pipe_config, @@ -5086,6 +5105,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } \ } while (0) +#define PIPE_CONF_CHECK_PLL_CX0(name) do { \ + if (!intel_cx0pll_compare_hw_state(¤t_config->name, \ + &pipe_config->name)) { \ + pipe_config_cx0pll_mismatch(&p, fastset, crtc, __stringify(name), \ + ¤t_config->name, \ + &pipe_config->name); \ + ret = false; \ + } \ +} while (0) + #define PIPE_CONF_CHECK_TIMINGS(name) do { \ PIPE_CONF_CHECK_I(name.crtc_hdisplay); \ PIPE_CONF_CHECK_I(name.crtc_htotal); \ @@ -5318,6 +5347,10 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, if (dev_priv->display.dpll.mgr || HAS_GMCH(dev_priv)) PIPE_CONF_CHECK_PLL(dpll_hw_state); + /* FIXME convert MTL+ platforms over to dpll_mgr */ + if (DISPLAY_VER(dev_priv) >= 14) + PIPE_CONF_CHECK_PLL_CX0(dpll_hw_state.cx0pll); + PIPE_CONF_CHECK_X(dsi_pll.ctrl); PIPE_CONF_CHECK_X(dsi_pll.div); diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h index f09e513ce05b..36baed75b89a 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.h @@ -264,6 +264,7 @@ struct intel_cx0pll_state { struct intel_c20pll_state c20; }; bool ssc_enabled; + bool use_c10; }; struct intel_dpll_hw_state { -- cgit From b2c2f2df6f01174eefc1ea2aa9aef8b1a6c69575 Mon Sep 17 00:00:00 2001 From: Luca Coelho Date: Tue, 28 May 2024 14:29:00 +0300 Subject: drm/i915/bios: double check array-boundary in parse_sdvo_lvds_data During static analysis, a concern was raised that we may access the dtd->dtd[] array out of bounds, because we are not checking whether the index we use is larger than the array. This should not be a problem as is, because the enumeration that is used for this index comes from "panel_type", which uses an enumeration with 4 items. But if this enumeration is ever changed, it can lead to hard-to-detect bugs, so better double-check it before using it as an index to the array. Signed-off-by: Luca Coelho Reviewed-by: Rodrigo Vivi Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240528112901.476068-2-luciano.coelho@intel.com --- drivers/gpu/drm/i915/display/intel_bios.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index b0a49b2f957f..128fe9250f40 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1120,6 +1120,18 @@ parse_sdvo_lvds_data(struct drm_i915_private *i915, if (!dtd) return; + /* + * This should not happen, as long as the panel_type + * enumeration doesn't grow over 4 items. But if it does, it + * could lead to hard-to-detect bugs, so better double-check + * it here to be sure. + */ + if (index >= ARRAY_SIZE(dtd->dtd)) { + drm_err(&i915->drm, "index %d is larger than dtd->dtd[4] array\n", + index); + return; + } + panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); if (!panel_fixed_mode) return; -- cgit From ed43c40e1f10e0ee1d49b841ee35b23a3a7113ee Mon Sep 17 00:00:00 2001 From: Luca Coelho Date: Tue, 28 May 2024 14:29:01 +0300 Subject: drm/i915: move uapi.event outside spinlock in intel_crtc_vblank_work In intel_crtc_vblank_work(), we access uapi.event before grabbing the event_lock spinlock, but modify it inside the spinlock block. This causes some static analyzers to get confused and issue a warning. The uapi.event value is not protected by the event_lock, so we can safely move it out of the protected block to prevent false positives. Signed-off-by: Luca Coelho Reviewed-by: Rodrigo Vivi Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240528112901.476068-3-luciano.coelho@intel.com --- drivers/gpu/drm/i915/display/intel_crtc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index ca6dc1dc56c8..bf6e74e99f5c 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -411,8 +411,8 @@ static void intel_crtc_vblank_work(struct kthread_work *base) if (crtc_state->uapi.event) { spin_lock_irq(&crtc->base.dev->event_lock); drm_crtc_send_vblank_event(&crtc->base, crtc_state->uapi.event); - crtc_state->uapi.event = NULL; spin_unlock_irq(&crtc->base.dev->event_lock); + crtc_state->uapi.event = NULL; } trace_intel_crtc_vblank_work_end(crtc); -- cgit From dd73925e3b84bcf2b29c20d6276843e7ed7cd771 Mon Sep 17 00:00:00 2001 From: Animesh Manna Date: Thu, 30 May 2024 01:37:37 +0530 Subject: drm/i915/alpm: Move alpm parameters from intel_psr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit ALPM can be enabled for non psr panel and currenly aplm-params are encapsulated under intel_psr struct, so moving out to intel_dp struct. Reviewed-by: Jouni Högander Signed-off-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-2-animesh.manna@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 21 +++++------ drivers/gpu/drm/i915/display/intel_psr.c | 44 +++++++++++----------- 2 files changed, 31 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 6fbfe8a18f45..f03b598638d7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1705,17 +1705,6 @@ struct intel_psr { bool psr2_sel_fetch_cff_enabled; bool req_psr2_sdp_prior_scanline; u8 sink_sync_latency; - - struct { - u8 io_wake_lines; - u8 fast_wake_lines; - - /* LNL and beyond */ - u8 check_entry_lines; - u8 silence_period_sym_clocks; - u8 lfps_half_cycle_num_of_syms; - } alpm_parameters; - ktime_t last_entry_attempt; ktime_t last_exit; bool sink_not_reliable; @@ -1847,6 +1836,16 @@ struct intel_dp { unsigned long last_oui_write; bool colorimetry_support; + + struct { + u8 io_wake_lines; + u8 fast_wake_lines; + + /* LNL and beyond */ + u8 check_entry_lines; + u8 silence_period_sym_clocks; + u8 lfps_half_cycle_num_of_syms; + } alpm_parameters; }; enum lspcon_vendor { diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 19f8ac12f995..977a7eaa0cde 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -864,8 +864,8 @@ static u32 intel_psr2_get_tp_time(struct intel_dp *intel_dp) static int psr2_block_count_lines(struct intel_dp *intel_dp) { - return intel_dp->psr.alpm_parameters.io_wake_lines < 9 && - intel_dp->psr.alpm_parameters.fast_wake_lines < 9 ? 8 : 12; + return intel_dp->alpm_parameters.io_wake_lines < 9 && + intel_dp->alpm_parameters.fast_wake_lines < 9 ? 8 : 12; } static int psr2_block_count(struct intel_dp *intel_dp) @@ -903,7 +903,6 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp) static void hsw_activate_psr2(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - struct intel_psr *psr = &intel_dp->psr; enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 val = EDP_PSR2_ENABLE; u32 psr_val = 0; @@ -945,20 +944,20 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) */ int tmp; - tmp = map[psr->alpm_parameters.io_wake_lines - + tmp = map[intel_dp->alpm_parameters.io_wake_lines - TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES]; val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(tmp + TGL_EDP_PSR2_IO_BUFFER_WAKE_MIN_LINES); - tmp = map[psr->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; + tmp = map[intel_dp->alpm_parameters.fast_wake_lines - TGL_EDP_PSR2_FAST_WAKE_MIN_LINES]; val |= TGL_EDP_PSR2_FAST_WAKE(tmp + TGL_EDP_PSR2_FAST_WAKE_MIN_LINES); } else if (DISPLAY_VER(dev_priv) >= 20) { - val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines); + val |= LNL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines); } else if (DISPLAY_VER(dev_priv) >= 12) { - val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines); - val |= TGL_EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines); + val |= TGL_EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines); + val |= TGL_EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines); } else if (DISPLAY_VER(dev_priv) >= 9) { - val |= EDP_PSR2_IO_BUFFER_WAKE(psr->alpm_parameters.io_wake_lines); - val |= EDP_PSR2_FAST_WAKE(psr->alpm_parameters.fast_wake_lines); + val |= EDP_PSR2_IO_BUFFER_WAKE(intel_dp->alpm_parameters.io_wake_lines); + val |= EDP_PSR2_FAST_WAKE(intel_dp->alpm_parameters.fast_wake_lines); } if (intel_dp->psr.req_psr2_sdp_prior_scanline) @@ -1341,9 +1340,9 @@ static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, if (i915->display.params.psr_safest_params) aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK; - intel_dp->psr.alpm_parameters.fast_wake_lines = aux_less_wake_lines; - intel_dp->psr.alpm_parameters.silence_period_sym_clocks = silence_period; - intel_dp->psr.alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle; + intel_dp->alpm_parameters.fast_wake_lines = aux_less_wake_lines; + intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period; + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle; return true; } @@ -1370,7 +1369,7 @@ static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, if (i915->display.params.psr_safest_params) check_entry_lines = 15; - intel_dp->psr.alpm_parameters.check_entry_lines = check_entry_lines; + intel_dp->alpm_parameters.check_entry_lines = check_entry_lines; return true; } @@ -1439,8 +1438,8 @@ static bool _compute_alpm_params(struct intel_dp *intel_dp, io_wake_lines = fast_wake_lines = max_wake_lines; /* According to Bspec lower limit should be set as 7 lines. */ - intel_dp->psr.alpm_parameters.io_wake_lines = max(io_wake_lines, 7); - intel_dp->psr.alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7); + intel_dp->alpm_parameters.io_wake_lines = max(io_wake_lines, 7); + intel_dp->alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7); return true; } @@ -1841,7 +1840,6 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - struct intel_psr *psr = &intel_dp->psr; u32 alpm_ctl; if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && @@ -1863,23 +1861,23 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | PORT_ALPM_CTL_SILENCE_PERIOD( - psr->alpm_parameters.silence_period_sym_clocks)); + intel_dp->alpm_parameters.silence_period_sym_clocks)); intel_de_write(dev_priv, PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder), PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( - psr->alpm_parameters.lfps_half_cycle_num_of_syms) | + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( - psr->alpm_parameters.lfps_half_cycle_num_of_syms) | + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION( - psr->alpm_parameters.lfps_half_cycle_num_of_syms)); + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms)); } else { alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE | - ALPM_CTL_EXTENDED_FAST_WAKE_TIME(psr->alpm_parameters.fast_wake_lines); + ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines); } - alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(psr->alpm_parameters.check_entry_lines); + alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines); intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl); } -- cgit From 8bdbde7c4c84286aff55c0af37bcf0a72828d98f Mon Sep 17 00:00:00 2001 From: Animesh Manna Date: Thu, 30 May 2024 01:37:38 +0530 Subject: drm/i915/alpm: Move alpm related code to a new file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move ALPM feature related code as it will be used for non-psr panel also thorugh LOBF feature. v1: Initial version. v2: Correct ordering in makefile. [Jani] Reviewed-by: Jouni Högander Signed-off-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-3-animesh.manna@intel.com --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/intel_alpm.c | 295 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_alpm.h | 18 ++ drivers/gpu/drm/i915/display/intel_psr.c | 283 +--------------------------- drivers/gpu/drm/xe/Makefile | 1 + 5 files changed, 318 insertions(+), 280 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_alpm.c create mode 100644 drivers/gpu/drm/i915/display/intel_alpm.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 7cad944b825c..9a3f910ce4fd 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -243,6 +243,7 @@ i915-y += \ display/hsw_ips.o \ display/i9xx_plane.o \ display/i9xx_wm.o \ + display/intel_alpm.o \ display/intel_atomic.o \ display/intel_atomic_plane.o \ display/intel_audio.o \ diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c new file mode 100644 index 000000000000..7307e02277d6 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -0,0 +1,295 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright 2024, Intel Corporation. + */ + +#include "intel_alpm.h" +#include "intel_crtc.h" +#include "intel_de.h" +#include "intel_display_types.h" +#include "intel_dp.h" +#include "intel_dp_aux.h" +#include "intel_psr_regs.h" + +/* + * See Bspec: 71632 for the table + * + * Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2) + * + * Half cycle duration: + * + * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns + * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) ) + * + * Link rates 5.4 - 8.1 + * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10 + * LFPS Period chosen is the mid-point of the min:max values from the table + * FLOOR( LFPS Period in Symbol clocks / + * (2 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ]) ) + */ +static bool _lnl_get_silence_period_and_lfps_half_cycle(int link_rate, + int *silence_period, + int *lfps_half_cycle) +{ + switch (link_rate) { + case 162000: + *silence_period = 20; + *lfps_half_cycle = 5; + break; + case 216000: + *silence_period = 27; + *lfps_half_cycle = 7; + break; + case 243000: + *silence_period = 31; + *lfps_half_cycle = 8; + break; + case 270000: + *silence_period = 34; + *lfps_half_cycle = 9; + break; + case 324000: + *silence_period = 41; + *lfps_half_cycle = 11; + break; + case 432000: + *silence_period = 56; + *lfps_half_cycle = 15; + break; + case 540000: + *silence_period = 69; + *lfps_half_cycle = 12; + break; + case 648000: + *silence_period = 84; + *lfps_half_cycle = 15; + break; + case 675000: + *silence_period = 87; + *lfps_half_cycle = 15; + break; + case 810000: + *silence_period = 104; + *lfps_half_cycle = 19; + break; + default: + *silence_period = *lfps_half_cycle = -1; + return false; + } + return true; +} + +/* + * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+ + * tSilence, Max+ tPHY Establishment + tCDS) / tline) + * For the "PHY P2 to P0" latency see the PHY Power Control page + * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965 + * : 12 us + * The tLFPS_Period, Max term is 800ns + * The tSilence, Max term is 180ns + * The tPHY Establishment (a.k.a. t1) term is 50us + * The tCDS term is 1 or 2 times t2 + * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK + * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1) + * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and + * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start + * within the CDS period complete within the CDS period regardless of + * entry into the period + * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) ) + * TPS4 Length = 252 Symbols + */ +static int _lnl_compute_aux_less_wake_time(int port_clock) +{ + int tphy2_p2_to_p0 = 12 * 1000; + int tlfps_period_max = 800; + int tsilence_max = 180; + int t1 = 50 * 1000; + int tps4 = 252; + int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock; + int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1; + int t2 = num_ml_phy_lock * tml_phy_lock; + int tcds = 1 * t2; + + return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max + tsilence_max + + t1 + tcds, 1000); +} + +static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int aux_less_wake_time, aux_less_wake_lines, silence_period, + lfps_half_cycle; + + aux_less_wake_time = + _lnl_compute_aux_less_wake_time(crtc_state->port_clock); + aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, + aux_less_wake_time); + + if (!_lnl_get_silence_period_and_lfps_half_cycle(crtc_state->port_clock, + &silence_period, + &lfps_half_cycle)) + return false; + + if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK || + silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK || + lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK) + return false; + + if (i915->display.params.psr_safest_params) + aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK; + + intel_dp->alpm_parameters.fast_wake_lines = aux_less_wake_lines; + intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period; + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle; + + return true; +} + +static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int check_entry_lines; + + if (DISPLAY_VER(i915) < 20) + return true; + + /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */ + check_entry_lines = 2 + + intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5); + + if (check_entry_lines > 15) + return false; + + if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state)) + return false; + + if (i915->display.params.psr_safest_params) + check_entry_lines = 15; + + intel_dp->alpm_parameters.check_entry_lines = check_entry_lines; + + return true; +} + +/* + * IO wake time for DISPLAY_VER < 12 is not directly mentioned in Bspec. There + * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are + * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us. + */ +static int skl_io_buffer_wake_time(void) +{ + return 18; +} + +static int tgl_io_buffer_wake_time(void) +{ + return 10; +} + +static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + if (DISPLAY_VER(i915) >= 12) + return tgl_io_buffer_wake_time(); + else + return skl_io_buffer_wake_time(); +} + +bool intel_alpm_compute_params(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time; + int tfw_exit_latency = 20; /* eDP spec */ + int phy_wake = 4; /* eDP spec */ + int preamble = 8; /* eDP spec */ + int precharge = intel_dp_aux_fw_sync_len() - preamble; + u8 max_wake_lines; + + io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) + + preamble + phy_wake + tfw_exit_latency; + fast_wake_time = precharge + preamble + phy_wake + + tfw_exit_latency; + + if (DISPLAY_VER(i915) >= 20) + max_wake_lines = 68; + else if (DISPLAY_VER(i915) >= 12) + max_wake_lines = 12; + else + max_wake_lines = 8; + + io_wake_lines = intel_usecs_to_scanlines( + &crtc_state->hw.adjusted_mode, io_wake_time); + fast_wake_lines = intel_usecs_to_scanlines( + &crtc_state->hw.adjusted_mode, fast_wake_time); + + if (io_wake_lines > max_wake_lines || + fast_wake_lines > max_wake_lines) + return false; + + if (!_lnl_compute_alpm_params(intel_dp, crtc_state)) + return false; + + if (i915->display.params.psr_safest_params) + io_wake_lines = fast_wake_lines = max_wake_lines; + + /* According to Bspec lower limit should be set as 7 lines. */ + intel_dp->alpm_parameters.io_wake_lines = max(io_wake_lines, 7); + intel_dp->alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7); + + return true; +} + +static void lnl_alpm_configure(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + u32 alpm_ctl; + + if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && + !intel_dp_is_edp(intel_dp))) + return; + + /* + * Panel Replay on eDP is always using ALPM aux less. I.e. no need to + * check panel support at this point. + */ + if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { + alpm_ctl = ALPM_CTL_ALPM_ENABLE | + ALPM_CTL_ALPM_AUX_LESS_ENABLE | + ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS; + + intel_de_write(dev_priv, + PORT_ALPM_CTL(dev_priv, cpu_transcoder), + PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | + PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | + PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | + PORT_ALPM_CTL_SILENCE_PERIOD( + intel_dp->alpm_parameters.silence_period_sym_clocks)); + + intel_de_write(dev_priv, + PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder), + PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | + PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | + PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | + PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION( + intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms)); + } else { + alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE | + ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines); + } + + alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines); + + intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl); +} + +void intel_alpm_configure(struct intel_dp *intel_dp) +{ + lnl_alpm_configure(intel_dp); +} diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h new file mode 100644 index 000000000000..c45d078e5a6b --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT + * + * Copyright © 2024 Intel Corporation + */ + +#ifndef _INTEL_ALPM_H +#define _INTEL_ALPM_H + +#include + +struct intel_dp; +struct intel_crtc_state; + +bool intel_alpm_compute_params(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state); +void intel_alpm_configure(struct intel_dp *intel_dp); + +#endif diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 977a7eaa0cde..7b22b66bda6a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -27,6 +27,7 @@ #include "i915_drv.h" #include "i915_reg.h" +#include "intel_alpm.h" #include "intel_atomic.h" #include "intel_crtc.h" #include "intel_cursor_regs.h" @@ -1212,238 +1213,6 @@ static bool _compute_psr2_sdp_prior_scanline_indication(struct intel_dp *intel_d return true; } -/* - * See Bspec: 71632 for the table - * - * Silence_period = tSilence,Min + ((tSilence,Max - tSilence,Min) / 2) - * - * Half cycle duration: - * - * Link rates 1.62 - 4.32 and tLFPS_Cycle = 70 ns - * FLOOR( (Link Rate * tLFPS_Cycle) / (2 * 10) ) - * - * Link rates 5.4 - 8.1 - * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ] = 10 - * LFPS Period chosen is the mid-point of the min:max values from the table - * FLOOR( LFPS Period in Symbol clocks / - * (2 * PORT_ALPM_LFPS_CTL[ LFPS Cycle Count ]) ) - */ -static bool _lnl_get_silence_period_and_lfps_half_cycle(int link_rate, - int *silence_period, - int *lfps_half_cycle) -{ - switch (link_rate) { - case 162000: - *silence_period = 20; - *lfps_half_cycle = 5; - break; - case 216000: - *silence_period = 27; - *lfps_half_cycle = 7; - break; - case 243000: - *silence_period = 31; - *lfps_half_cycle = 8; - break; - case 270000: - *silence_period = 34; - *lfps_half_cycle = 9; - break; - case 324000: - *silence_period = 41; - *lfps_half_cycle = 11; - break; - case 432000: - *silence_period = 56; - *lfps_half_cycle = 15; - break; - case 540000: - *silence_period = 69; - *lfps_half_cycle = 12; - break; - case 648000: - *silence_period = 84; - *lfps_half_cycle = 15; - break; - case 675000: - *silence_period = 87; - *lfps_half_cycle = 15; - break; - case 810000: - *silence_period = 104; - *lfps_half_cycle = 19; - break; - default: - *silence_period = *lfps_half_cycle = -1; - return false; - } - return true; -} - -/* - * AUX-Less Wake Time = CEILING( ((PHY P2 to P0) + tLFPS_Period, Max+ - * tSilence, Max+ tPHY Establishment + tCDS) / tline) - * For the "PHY P2 to P0" latency see the PHY Power Control page - * (PHY P2 to P0) : https://gfxspecs.intel.com/Predator/Home/Index/68965 - * : 12 us - * The tLFPS_Period, Max term is 800ns - * The tSilence, Max term is 180ns - * The tPHY Establishment (a.k.a. t1) term is 50us - * The tCDS term is 1 or 2 times t2 - * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK - * Number ML_PHY_LOCK = ( 7 + CEILING( 6.5us / tML_PHY_LOCK ) + 1) - * Rounding up the 6.5us padding to the next ML_PHY_LOCK boundary and - * adding the "+ 1" term ensures all ML_PHY_LOCK sequences that start - * within the CDS period complete within the CDS period regardless of - * entry into the period - * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) ) - * TPS4 Length = 252 Symbols - */ -static int _lnl_compute_aux_less_wake_time(int port_clock) -{ - int tphy2_p2_to_p0 = 12 * 1000; - int tlfps_period_max = 800; - int tsilence_max = 180; - int t1 = 50 * 1000; - int tps4 = 252; - int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock; - int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1; - int t2 = num_ml_phy_lock * tml_phy_lock; - int tcds = 1 * t2; - - return DIV_ROUND_UP(tphy2_p2_to_p0 + tlfps_period_max + tsilence_max + - t1 + tcds, 1000); -} - -static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int aux_less_wake_time, aux_less_wake_lines, silence_period, - lfps_half_cycle; - - aux_less_wake_time = - _lnl_compute_aux_less_wake_time(crtc_state->port_clock); - aux_less_wake_lines = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, - aux_less_wake_time); - - if (!_lnl_get_silence_period_and_lfps_half_cycle(crtc_state->port_clock, - &silence_period, - &lfps_half_cycle)) - return false; - - if (aux_less_wake_lines > ALPM_CTL_AUX_LESS_WAKE_TIME_MASK || - silence_period > PORT_ALPM_CTL_SILENCE_PERIOD_MASK || - lfps_half_cycle > PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION_MASK) - return false; - - if (i915->display.params.psr_safest_params) - aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK; - - intel_dp->alpm_parameters.fast_wake_lines = aux_less_wake_lines; - intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period; - intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle; - - return true; -} - -static bool _lnl_compute_alpm_params(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int check_entry_lines; - - if (DISPLAY_VER(i915) < 20) - return true; - - /* ALPM Entry Check = 2 + CEILING( 5us /tline ) */ - check_entry_lines = 2 + - intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 5); - - if (check_entry_lines > 15) - return false; - - if (!_lnl_compute_aux_less_alpm_params(intel_dp, crtc_state)) - return false; - - if (i915->display.params.psr_safest_params) - check_entry_lines = 15; - - intel_dp->alpm_parameters.check_entry_lines = check_entry_lines; - - return true; -} - -/* - * IO wake time for DISPLAY_VER < 12 is not directly mentioned in Bspec. There - * are 50 us io wake time and 32 us fast wake time. Clearly preharge pulses are - * not (improperly) included in 32 us fast wake time. 50 us - 32 us = 18 us. - */ -static int skl_io_buffer_wake_time(void) -{ - return 18; -} - -static int tgl_io_buffer_wake_time(void) -{ - return 10; -} - -static int io_buffer_wake_time(const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - - if (DISPLAY_VER(i915) >= 12) - return tgl_io_buffer_wake_time(); - else - return skl_io_buffer_wake_time(); -} - -static bool _compute_alpm_params(struct intel_dp *intel_dp, - struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int io_wake_lines, io_wake_time, fast_wake_lines, fast_wake_time; - int tfw_exit_latency = 20; /* eDP spec */ - int phy_wake = 4; /* eDP spec */ - int preamble = 8; /* eDP spec */ - int precharge = intel_dp_aux_fw_sync_len() - preamble; - u8 max_wake_lines; - - io_wake_time = max(precharge, io_buffer_wake_time(crtc_state)) + - preamble + phy_wake + tfw_exit_latency; - fast_wake_time = precharge + preamble + phy_wake + - tfw_exit_latency; - - if (DISPLAY_VER(i915) >= 20) - max_wake_lines = 68; - else if (DISPLAY_VER(i915) >= 12) - max_wake_lines = 12; - else - max_wake_lines = 8; - - io_wake_lines = intel_usecs_to_scanlines( - &crtc_state->hw.adjusted_mode, io_wake_time); - fast_wake_lines = intel_usecs_to_scanlines( - &crtc_state->hw.adjusted_mode, fast_wake_time); - - if (io_wake_lines > max_wake_lines || - fast_wake_lines > max_wake_lines) - return false; - - if (!_lnl_compute_alpm_params(intel_dp, crtc_state)) - return false; - - if (i915->display.params.psr_safest_params) - io_wake_lines = fast_wake_lines = max_wake_lines; - - /* According to Bspec lower limit should be set as 7 lines. */ - intel_dp->alpm_parameters.io_wake_lines = max(io_wake_lines, 7); - intel_dp->alpm_parameters.fast_wake_lines = max(fast_wake_lines, 7); - - return true; -} - static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, const struct drm_display_mode *adjusted_mode) { @@ -1560,7 +1329,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, return false; } - if (!_compute_alpm_params(intel_dp, crtc_state)) { + if (!intel_alpm_compute_params(intel_dp, crtc_state)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, Unable to use long enough wake times\n"); return false; @@ -1836,52 +1605,6 @@ static void wm_optimization_wa(struct intel_dp *intel_dp, wa_16013835468_bit_get(intel_dp), 0); } -static void lnl_alpm_configure(struct intel_dp *intel_dp) -{ - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - u32 alpm_ctl; - - if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && - !intel_dp_is_edp(intel_dp))) - return; - - /* - * Panel Replay on eDP is always using ALPM aux less. I.e. no need to - * check panel support at this point. - */ - if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { - alpm_ctl = ALPM_CTL_ALPM_ENABLE | - ALPM_CTL_ALPM_AUX_LESS_ENABLE | - ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS; - - intel_de_write(dev_priv, - PORT_ALPM_CTL(dev_priv, cpu_transcoder), - PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | - PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | - PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | - PORT_ALPM_CTL_SILENCE_PERIOD( - intel_dp->alpm_parameters.silence_period_sym_clocks)); - - intel_de_write(dev_priv, - PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder), - PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | - PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( - intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | - PORT_ALPM_LFPS_CTL_FIRST_LFPS_HALF_CYCLE_DURATION( - intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | - PORT_ALPM_LFPS_CTL_LAST_LFPS_HALF_CYCLE_DURATION( - intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms)); - } else { - alpm_ctl = ALPM_CTL_EXTENDED_FAST_WAKE_ENABLE | - ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines); - } - - alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines); - - intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl); -} - static void intel_psr_enable_source(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { @@ -1962,7 +1685,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, IGNORE_PSR2_HW_TRACKING : 0); if (intel_dp_is_edp(intel_dp)) - lnl_alpm_configure(intel_dp); + intel_alpm_configure(intel_dp); /* * Wa_16013835468 diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index ae579b6c8763..0132397a1a31 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -215,6 +215,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ # Display code shared with i915 xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/icl_dsi.o \ + i915-display/intel_alpm.o \ i915-display/intel_atomic.o \ i915-display/intel_atomic_plane.o \ i915-display/intel_audio.o \ -- cgit From b09469817812ed30c2fda685831a1779437c9c11 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Thu, 30 May 2024 01:37:39 +0530 Subject: drm/display: Add missing aux less alpm wake related bits MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit eDP1.5 adds some more bits into DP_RECEIVER_ALPM_CAP and DP_RECEIVER_ALPM_CONFIG registers. Add definitions for these. Acked-by: Maxime Ripard Reviewed-by: Ankit Nautiyal Signed-off-by: Jouni Högander Signed-off-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-4-animesh.manna@intel.com --- include/drm/display/drm_dp.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 79bde372b152..f246fa03a3cb 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -232,6 +232,8 @@ #define DP_RECEIVER_ALPM_CAP 0x02e /* eDP 1.4 */ # define DP_ALPM_CAP (1 << 0) +# define DP_ALPM_PM_STATE_2A_SUPPORT (1 << 1) /* eDP 1.5 */ +# define DP_ALPM_AUX_LESS_CAP (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP 0x02f /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_CAP (1 << 0) @@ -684,7 +686,8 @@ #define DP_RECEIVER_ALPM_CONFIG 0x116 /* eDP 1.4 */ # define DP_ALPM_ENABLE (1 << 0) -# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) +# define DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE (1 << 1) /* eDP 1.5 */ +# define DP_ALPM_MODE_AUX_LESS (1 << 2) /* eDP 1.5 */ #define DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF 0x117 /* eDP 1.4 */ # define DP_AUX_FRAME_SYNC_ENABLE (1 << 0) -- cgit From 15438b32598744cf207398dc3e02bf88db42cf9a Mon Sep 17 00:00:00 2001 From: Animesh Manna Date: Thu, 30 May 2024 01:37:40 +0530 Subject: drm/i915/alpm: Add compute config for lobf MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Link Off Between Active Frames, is a new feature for eDP that allows the panel to go to lower power state after transmission of data. This is a feature on top of ALPM, AS SDP. Add compute config during atomic-check phase. v1: RFC version. v2: Add separate flag for auxless-alpm. [Jani] v3: - intel_dp->lobf_supported replaced with crtc_state->has_lobf. [Jouni] - Add DISPLAY_VER() check. [Jouni] - Modify function name of get_aux_less_status. [Jani] v4: Add enum alpm_mode to hold the aux-wake/less capability. v5: Add alpm_dpcd to intel_dp and use aux_wake_supported()/ aux_less_wake_supported() instead of enum alpm_mode. [Jouni] Reviewed-by: Jouni Högander Signed-off-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-5-animesh.manna@intel.com --- drivers/gpu/drm/i915/display/intel_alpm.c | 61 ++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_alpm.h | 5 ++ drivers/gpu/drm/i915/display/intel_display_types.h | 5 ++ drivers/gpu/drm/i915/display/intel_dp.c | 4 ++ 4 files changed, 75 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 7307e02277d6..3ac5986b4ad9 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -11,6 +11,26 @@ #include "intel_dp_aux.h" #include "intel_psr_regs.h" +static bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp) +{ + return intel_dp->alpm_dpcd & DP_ALPM_CAP; +} + +static bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp) +{ + return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP; +} + +void intel_alpm_init_dpcd(struct intel_dp *intel_dp) +{ + u8 dpcd; + + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, &dpcd) < 0) + return; + + intel_dp->alpm_dpcd = dpcd; +} + /* * See Bspec: 71632 for the table * @@ -243,6 +263,47 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp, return true; } +void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + int waketime_in_lines, first_sdp_position; + int context_latency, guardband; + + if (!intel_dp_is_edp(intel_dp)) + return; + + if (DISPLAY_VER(i915) < 20) + return; + + if (!intel_dp_as_sdp_supported(intel_dp)) + return; + + if (crtc_state->has_psr) + return; + + if (!(intel_alpm_aux_wake_supported(intel_dp) || + intel_alpm_aux_less_wake_supported(intel_dp))) + return; + + if (!intel_alpm_compute_params(intel_dp, crtc_state)) + return; + + context_latency = adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; + guardband = adjusted_mode->crtc_vtotal - + adjusted_mode->crtc_vdisplay - context_latency; + first_sdp_position = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_start; + if (intel_alpm_aux_less_wake_supported(intel_dp)) + waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines; + else + waketime_in_lines = intel_dp->alpm_parameters.fast_wake_lines; + + crtc_state->has_lobf = (context_latency + guardband) > + (first_sdp_position + waketime_in_lines); +} + static void lnl_alpm_configure(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h index c45d078e5a6b..e586e8a01b10 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.h +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -10,9 +10,14 @@ struct intel_dp; struct intel_crtc_state; +struct drm_connector_state; +void intel_alpm_init_dpcd(struct intel_dp *intel_dp); bool intel_alpm_compute_params(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); +void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state); void intel_alpm_configure(struct intel_dp *intel_dp); #endif diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index f03b598638d7..012ff9e18b54 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1410,6 +1410,9 @@ struct intel_crtc_state { /* for loading single buffered registers during vblank */ struct drm_vblank_work vblank_work; + + /* LOBF flag */ + bool has_lobf; }; enum intel_pipe_crc_source { @@ -1846,6 +1849,8 @@ struct intel_dp { u8 silence_period_sym_clocks; u8 lfps_half_cycle_num_of_syms; } alpm_parameters; + + u8 alpm_dpcd; }; enum lspcon_vendor { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 4fa977f1e6c4..fd054e16850d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -48,6 +48,7 @@ #include "i915_drv.h" #include "i915_irq.h" #include "i915_reg.h" +#include "intel_alpm.h" #include "intel_atomic.h" #include "intel_audio.h" #include "intel_backlight.h" @@ -3000,6 +3001,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_vrr_compute_config(pipe_config, conn_state); intel_dp_compute_as_sdp(intel_dp, pipe_config); intel_psr_compute_config(intel_dp, pipe_config, conn_state); + intel_alpm_lobf_compute_config(intel_dp, pipe_config, conn_state); intel_dp_drrs_compute_config(connector, pipe_config, link_bpp_x16); intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); @@ -6513,6 +6515,8 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, */ intel_hpd_enable_detection(encoder); + intel_alpm_init_dpcd(intel_dp); + /* Cache DPCD and EDID for edp. */ has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector); -- cgit From 5a9b255fdb2b235502bcfc0951d71c0c3f6d030e Mon Sep 17 00:00:00 2001 From: Animesh Manna Date: Thu, 30 May 2024 01:37:41 +0530 Subject: drm/i915/alpm: Enable lobf from source in ALPM_CTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the Link Off Between Frames Enable bit in ALPM_CTL register. Note: Lobf need to be enabled adaptive sync fixed refresh mode where vmin = vmax = flipline, which will arise after cmmr feature enablement. Will add enabling sequence in a separate patch. v1: Initial version. v2: Condition check modified in alpm_configure(). [Jouni] Reviewed-by: Jouni Högander Signed-off-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-6-animesh.manna@intel.com --- drivers/gpu/drm/i915/display/intel_alpm.c | 16 +++++++++++----- drivers/gpu/drm/i915/display/intel_alpm.h | 4 ++-- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 3ac5986b4ad9..a8ae5f65a250 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -304,10 +304,11 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, (first_sdp_position + waketime_in_lines); } -static void lnl_alpm_configure(struct intel_dp *intel_dp) +static void lnl_alpm_configure(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 alpm_ctl; if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && @@ -318,7 +319,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) * Panel Replay on eDP is always using ALPM aux less. I.e. no need to * check panel support at this point. */ - if (intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) { + if ((intel_dp->psr.panel_replay_enabled && intel_dp_is_edp(intel_dp)) || + (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp))) { alpm_ctl = ALPM_CTL_ALPM_ENABLE | ALPM_CTL_ALPM_AUX_LESS_ENABLE | ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS; @@ -345,12 +347,16 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp) ALPM_CTL_EXTENDED_FAST_WAKE_TIME(intel_dp->alpm_parameters.fast_wake_lines); } + if (crtc_state->has_lobf) + alpm_ctl |= ALPM_CTL_LOBF_ENABLE; + alpm_ctl |= ALPM_CTL_ALPM_ENTRY_CHECK(intel_dp->alpm_parameters.check_entry_lines); intel_de_write(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder), alpm_ctl); } -void intel_alpm_configure(struct intel_dp *intel_dp) +void intel_alpm_configure(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { - lnl_alpm_configure(intel_dp); + lnl_alpm_configure(intel_dp, crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h index e586e8a01b10..80b9ca086a49 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.h +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -18,6 +18,6 @@ bool intel_alpm_compute_params(struct intel_dp *intel_dp, void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state); -void intel_alpm_configure(struct intel_dp *intel_dp); - +void intel_alpm_configure(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state); #endif diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7b22b66bda6a..4b337bcd9c90 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1685,7 +1685,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, IGNORE_PSR2_HW_TRACKING : 0); if (intel_dp_is_edp(intel_dp)) - intel_alpm_configure(intel_dp); + intel_alpm_configure(intel_dp, crtc_state); /* * Wa_16013835468 -- cgit From 42493f7cb2c96ef96cce5809878ee2fa0ce63b1f Mon Sep 17 00:00:00 2001 From: Animesh Manna Date: Thu, 30 May 2024 01:37:42 +0530 Subject: drm/i915/alpm: Add debugfs for LOBF MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For validation purpose add debugfs for LOBF. v1: Initial version. v2: Add aux-wake/less info along with lobf status. [Jouni] Reviewed-by: Jouni Högander Signed-off-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240529200742.1694401-7-animesh.manna@intel.com --- drivers/gpu/drm/i915/display/intel_alpm.c | 49 ++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_alpm.h | 2 + .../gpu/drm/i915/display/intel_display_debugfs.c | 2 + 3 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index a8ae5f65a250..a26716c14aa3 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -360,3 +360,52 @@ void intel_alpm_configure(struct intel_dp *intel_dp, { lnl_alpm_configure(intel_dp, crtc_state); } + +static int i915_edp_lobf_info_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = m->private; + struct drm_i915_private *dev_priv = to_i915(connector->base.dev); + struct drm_crtc *crtc; + struct intel_crtc_state *crtc_state; + enum transcoder cpu_transcoder; + u32 alpm_ctl; + int ret; + + ret = drm_modeset_lock_single_interruptible(&dev_priv->drm.mode_config.connection_mutex); + if (ret) + return ret; + + crtc = connector->base.state->crtc; + if (connector->base.status != connector_status_connected || !crtc) { + ret = -ENODEV; + goto out; + } + + crtc_state = to_intel_crtc_state(crtc->state); + cpu_transcoder = crtc_state->cpu_transcoder; + alpm_ctl = intel_de_read(dev_priv, ALPM_CTL(dev_priv, cpu_transcoder)); + seq_printf(m, "LOBF status: %s\n", str_enabled_disabled(alpm_ctl & ALPM_CTL_LOBF_ENABLE)); + seq_printf(m, "Aux-wake alpm status: %s\n", + str_enabled_disabled(!(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE))); + seq_printf(m, "Aux-less alpm status: %s\n", + str_enabled_disabled(alpm_ctl & ALPM_CTL_ALPM_AUX_LESS_ENABLE)); +out: + drm_modeset_unlock(&dev_priv->drm.mode_config.connection_mutex); + + return ret; +} + +DEFINE_SHOW_ATTRIBUTE(i915_edp_lobf_info); + +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct dentry *root = connector->base.debugfs_entry; + + if (DISPLAY_VER(i915) < 20 || + connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) + return; + + debugfs_create_file("i915_edp_lobf_info", 0444, root, + connector, &i915_edp_lobf_info_fops); +} diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h index 80b9ca086a49..c82ecc7b4001 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.h +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -11,6 +11,7 @@ struct intel_dp; struct intel_crtc_state; struct drm_connector_state; +struct intel_connector; void intel_alpm_init_dpcd(struct intel_dp *intel_dp); bool intel_alpm_compute_params(struct intel_dp *intel_dp, @@ -20,4 +21,5 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, struct drm_connector_state *conn_state); void intel_alpm_configure(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); +void intel_alpm_lobf_debugfs_add(struct intel_connector *connector); #endif diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 35f9f86ef70f..86d9900c40af 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -13,6 +13,7 @@ #include "i915_debugfs.h" #include "i915_irq.h" #include "i915_reg.h" +#include "intel_alpm.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_crtc_state_dump.h" @@ -1515,6 +1516,7 @@ void intel_connector_debugfs_add(struct intel_connector *connector) intel_drrs_connector_debugfs_add(connector); intel_pps_connector_debugfs_add(connector); intel_psr_connector_debugfs_add(connector); + intel_alpm_lobf_debugfs_add(connector); if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || connector_type == DRM_MODE_CONNECTOR_HDMIA || -- cgit From 54698865addac97faa8dea4e07be838219128186 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 22 May 2024 20:33:38 +0300 Subject: drm/i915/display: move params copy at probe earlier Copy the parameters earlier to make subsequent changes easier. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/a0c3e74d824d8a7c02fa1461c3d5518a71171256.1716399081.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_device.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index cf093bc0cb28..9edadc7270f6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -936,6 +936,8 @@ void intel_display_device_probe(struct drm_i915_private *i915) /* Add drm device backpointer as early as possible. */ i915->display.drm = &i915->drm; + intel_display_params_copy(&i915->display.params); + if (HAS_GMD_ID(i915)) info = probe_gmdid_display(i915, &ver, &rel, &step); else @@ -952,8 +954,6 @@ void intel_display_device_probe(struct drm_i915_private *i915) DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; DISPLAY_RUNTIME_INFO(i915)->ip.step = step; } - - intel_display_params_copy(&i915->display.params); } void intel_display_device_remove(struct drm_i915_private *i915) -- cgit From ae6daede02d2a31171fd20887363e59f4aec3768 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 22 May 2024 20:33:39 +0300 Subject: drm/i915/display: change probe for no display case Return NULL for errors, and handle the no display case in one location. This will make subsequent changes easier. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/8dfac3532a72ca6494c9955987166d9c6e0919bd.1716399081.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_device.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 9edadc7270f6..03181bb79d21 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -881,7 +881,7 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); if (!addr) { drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); - return &no_display; + return NULL; } val = ioread32(addr); @@ -889,7 +889,7 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step if (val == 0) { drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); - return &no_display; + return NULL; } *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); @@ -903,7 +903,7 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", *ver, *rel); - return &no_display; + return NULL; } static const struct intel_display_device_info * @@ -914,7 +914,7 @@ probe_display(struct drm_i915_private *i915) if (has_no_display(pdev)) { drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); - return &no_display; + return NULL; } for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { @@ -925,7 +925,7 @@ probe_display(struct drm_i915_private *i915) drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n", pdev->device); - return &no_display; + return NULL; } void intel_display_device_probe(struct drm_i915_private *i915) @@ -943,6 +943,9 @@ void intel_display_device_probe(struct drm_i915_private *i915) else info = probe_display(i915); + if (!info) + goto no_display; + DISPLAY_INFO(i915) = info; memcpy(DISPLAY_RUNTIME_INFO(i915), @@ -954,6 +957,11 @@ void intel_display_device_probe(struct drm_i915_private *i915) DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; DISPLAY_RUNTIME_INFO(i915)->ip.step = step; } + + return; + +no_display: + DISPLAY_INFO(i915) = &no_display; } void intel_display_device_remove(struct drm_i915_private *i915) -- cgit From cb9d05b9c2696431db1501160dab9f81a23ab0e3 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 22 May 2024 20:33:40 +0300 Subject: drm/i915/display: check platforms without display one level higher The main change here is that the check for platforms without display is now also done for GMD ID based platforms. However, without matches, the end result is the same. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/78d5d326c4c89f1942f120655c279c9274e96bfb.1716399081.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_device.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 03181bb79d21..f548a7b0ec23 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -912,11 +912,6 @@ probe_display(struct drm_i915_private *i915) struct pci_dev *pdev = to_pci_dev(i915->drm.dev); int i; - if (has_no_display(pdev)) { - drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); - return NULL; - } - for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { if (intel_display_ids[i].devid == pdev->device) return intel_display_ids[i].info; @@ -930,6 +925,7 @@ probe_display(struct drm_i915_private *i915) void intel_display_device_probe(struct drm_i915_private *i915) { + struct pci_dev *pdev = to_pci_dev(i915->drm.dev); const struct intel_display_device_info *info; u16 ver, rel, step; @@ -938,6 +934,11 @@ void intel_display_device_probe(struct drm_i915_private *i915) intel_display_params_copy(&i915->display.params); + if (has_no_display(pdev)) { + drm_dbg_kms(&i915->drm, "Device doesn't have display\n"); + goto no_display; + } + if (HAS_GMD_ID(i915)) info = probe_gmdid_display(i915, &ver, &rel, &step); else -- cgit From fdf531b80345aa0ffb15dd6b3c3db52f1f194abe Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 22 May 2024 20:33:41 +0300 Subject: drm/i915/display: change GMD ID display ip ver propagation at probe Add a name to the display ip version structure, and pass that around instead of a triplet of u16's. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1610e9f5675b4d0d4f16ecd10a86486ce309a283.1716399081.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_device.c | 40 +++++++++------------- .../gpu/drm/i915/display/intel_display_device.h | 2 +- 2 files changed, 17 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index f548a7b0ec23..56b27546d1b3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -862,22 +862,14 @@ static const struct { }; static const struct intel_display_device_info * -probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step) +probe_gmdid_display(struct drm_i915_private *i915, struct intel_display_ip_ver *ip_ver) { struct pci_dev *pdev = to_pci_dev(i915->drm.dev); + struct intel_display_ip_ver gmd_id; void __iomem *addr; u32 val; int i; - /* The caller expects to ver, rel and step to be initialized - * here, and there's no good way to check when there was a - * failure and no_display was returned. So initialize all these - * values here zero, to be sure. - */ - *ver = 0; - *rel = 0; - *step = 0; - addr = pci_iomap_range(pdev, 0, i915_mmio_reg_offset(GMD_ID_DISPLAY), sizeof(u32)); if (!addr) { drm_err(&i915->drm, "Cannot map MMIO BAR to read display GMD_ID\n"); @@ -892,17 +884,20 @@ probe_gmdid_display(struct drm_i915_private *i915, u16 *ver, u16 *rel, u16 *step return NULL; } - *ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); - *rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); - *step = REG_FIELD_GET(GMD_ID_STEP, val); + gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); + gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); + gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val); - for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) - if (*ver == gmdid_display_map[i].ver && - *rel == gmdid_display_map[i].rel) + for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) { + if (gmd_id.ver == gmdid_display_map[i].ver && + gmd_id.rel == gmdid_display_map[i].rel) { + *ip_ver = gmd_id; return gmdid_display_map[i].display; + } + } drm_err(&i915->drm, "Unrecognized display IP version %d.%02d; disabling display.\n", - *ver, *rel); + gmd_id.ver, gmd_id.rel); return NULL; } @@ -927,7 +922,7 @@ void intel_display_device_probe(struct drm_i915_private *i915) { struct pci_dev *pdev = to_pci_dev(i915->drm.dev); const struct intel_display_device_info *info; - u16 ver, rel, step; + struct intel_display_ip_ver ip_ver = {}; /* Add drm device backpointer as early as possible. */ i915->display.drm = &i915->drm; @@ -940,7 +935,7 @@ void intel_display_device_probe(struct drm_i915_private *i915) } if (HAS_GMD_ID(i915)) - info = probe_gmdid_display(i915, &ver, &rel, &step); + info = probe_gmdid_display(i915, &ip_ver); else info = probe_display(i915); @@ -953,11 +948,8 @@ void intel_display_device_probe(struct drm_i915_private *i915) &DISPLAY_INFO(i915)->__runtime_defaults, sizeof(*DISPLAY_RUNTIME_INFO(i915))); - if (HAS_GMD_ID(i915)) { - DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver; - DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel; - DISPLAY_RUNTIME_INFO(i915)->ip.step = step; - } + if (ip_ver.ver || ip_ver.rel || ip_ver.step) + DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; return; diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 17ddf82f0b6e..fd2d03bfe8a6 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -111,7 +111,7 @@ struct drm_printer; (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) struct intel_display_runtime_info { - struct { + struct intel_display_ip_ver { u16 ver; u16 rel; u16 step; -- cgit From 785778ce21cf50cbd3ce6cad0bf4e6c0ba3a3b41 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 22 May 2024 20:33:42 +0300 Subject: drm/i915/display: add platform descriptors We'll need to start identifying the platforms independently in display code in order to break free from the i915 and xe IS_() macros. This is fairly straightforward, as we already identify most platforms by PCI ID in display probe anyway. As the first step, add platform descriptors with pointers to display info. We'll have more platforms than display info, so minimize duplication: - Add separate skl/kbl/cfl/cml descriptors while they share the display info. - Add separate jsl/ehl descriptors while they share the display info. Identify ADL-P (and derivatives) and DG2 descriptors by their names even though their display info is Xe LPD or HPD. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/45425c155608403efc149d4a022c0b443aa71200.1716399081.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_device.c | 558 ++++++++++++--------- 1 file changed, 326 insertions(+), 232 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 56b27546d1b3..d1e03437abb3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -20,6 +20,10 @@ __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); +struct platform_desc { + const struct intel_display_device_info *info; +}; + static const struct intel_display_device_info no_display = {}; #define PIPE_A_OFFSET 0x70000 @@ -200,33 +204,41 @@ static const struct intel_display_device_info no_display = {}; .__runtime_defaults.pipe_mask = BIT(PIPE_A), \ .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) -static const struct intel_display_device_info i830_display = { - I830_DISPLAY, +static const struct platform_desc i830_desc = { + .info = &(const struct intel_display_device_info) { + I830_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */ + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */ + }, }; -static const struct intel_display_device_info i845_display = { - I845_DISPLAY, +static const struct platform_desc i845_desc = { + .info = &(const struct intel_display_device_info) { + I845_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ + }, }; -static const struct intel_display_device_info i85x_display = { - I830_DISPLAY, +static const struct platform_desc i85x_desc = { + .info = &(const struct intel_display_device_info) { + I830_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info i865g_display = { - I845_DISPLAY, +static const struct platform_desc i865g_desc = { + .info = &(const struct intel_display_device_info) { + I845_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -#define GEN3_DISPLAY \ +#define GEN3_DISPLAY \ .has_gmch = 1, \ .has_overlay = 1, \ I9XX_PIPE_OFFSETS, \ @@ -238,52 +250,64 @@ static const struct intel_display_device_info i865g_display = { BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */ -static const struct intel_display_device_info i915g_display = { - GEN3_DISPLAY, - I845_COLORS, - .cursor_needs_physical = 1, - .overlay_needs_physical = 1, +static const struct platform_desc i915g_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I845_COLORS, + .cursor_needs_physical = 1, + .overlay_needs_physical = 1, + }, }; -static const struct intel_display_device_info i915gm_display = { - GEN3_DISPLAY, - I9XX_COLORS, - .cursor_needs_physical = 1, - .overlay_needs_physical = 1, - .supports_tv = 1, +static const struct platform_desc i915gm_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I9XX_COLORS, + .cursor_needs_physical = 1, + .overlay_needs_physical = 1, + .supports_tv = 1, - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info i945g_display = { - GEN3_DISPLAY, - I845_COLORS, - .has_hotplug = 1, - .cursor_needs_physical = 1, - .overlay_needs_physical = 1, +static const struct platform_desc i945g_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I845_COLORS, + .has_hotplug = 1, + .cursor_needs_physical = 1, + .overlay_needs_physical = 1, + }, }; -static const struct intel_display_device_info i945gm_display = { - GEN3_DISPLAY, - I9XX_COLORS, - .has_hotplug = 1, - .cursor_needs_physical = 1, - .overlay_needs_physical = 1, - .supports_tv = 1, - - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), +static const struct platform_desc i945gm_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I9XX_COLORS, + .has_hotplug = 1, + .cursor_needs_physical = 1, + .overlay_needs_physical = 1, + .supports_tv = 1, + + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info g33_display = { - GEN3_DISPLAY, - I845_COLORS, - .has_hotplug = 1, +static const struct platform_desc g33_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I845_COLORS, + .has_hotplug = 1, + }, }; -static const struct intel_display_device_info pnv_display = { - GEN3_DISPLAY, - I9XX_COLORS, - .has_hotplug = 1, +static const struct platform_desc pnv_desc = { + .info = &(const struct intel_display_device_info) { + GEN3_DISPLAY, + I9XX_COLORS, + .has_hotplug = 1, + }, }; #define GEN4_DISPLAY \ @@ -298,34 +322,42 @@ static const struct intel_display_device_info pnv_display = { .__runtime_defaults.cpu_transcoder_mask = \ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) -static const struct intel_display_device_info i965g_display = { - GEN4_DISPLAY, - .has_overlay = 1, +static const struct platform_desc i965g_desc = { + .info = &(const struct intel_display_device_info) { + GEN4_DISPLAY, + .has_overlay = 1, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ + }, }; -static const struct intel_display_device_info i965gm_display = { - GEN4_DISPLAY, - .has_overlay = 1, - .supports_tv = 1, +static const struct platform_desc i965gm_desc = { + .info = &(const struct intel_display_device_info) { + GEN4_DISPLAY, + .has_overlay = 1, + .supports_tv = 1, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info g45_display = { - GEN4_DISPLAY, +static const struct platform_desc g45_desc = { + .info = &(const struct intel_display_device_info) { + GEN4_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ + }, }; -static const struct intel_display_device_info gm45_display = { - GEN4_DISPLAY, - .supports_tv = 1, +static const struct platform_desc gm45_desc = { + .info = &(const struct intel_display_device_info) { + GEN4_DISPLAY, + .supports_tv = 1, - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* SDVO/HDMI/DP B/C, DP D */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; #define ILK_DISPLAY \ @@ -340,112 +372,128 @@ static const struct intel_display_device_info gm45_display = { BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \ .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ -static const struct intel_display_device_info ilk_d_display = { - ILK_DISPLAY, +static const struct platform_desc ilk_d_desc = { + .info = &(const struct intel_display_device_info) { + ILK_DISPLAY, + }, }; -static const struct intel_display_device_info ilk_m_display = { - ILK_DISPLAY, +static const struct platform_desc ilk_m_desc = { + .info = &(const struct intel_display_device_info) { + ILK_DISPLAY, - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info snb_display = { - .has_hotplug = 1, - I9XX_PIPE_OFFSETS, - I9XX_CURSOR_OFFSETS, - ILK_COLORS, +static const struct platform_desc snb_desc = { + .info = &(const struct intel_display_device_info) { + .has_hotplug = 1, + I9XX_PIPE_OFFSETS, + I9XX_CURSOR_OFFSETS, + ILK_COLORS, - .__runtime_defaults.ip.ver = 6, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), - .__runtime_defaults.cpu_transcoder_mask = + .__runtime_defaults.ip.ver = 6, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info ivb_display = { - .has_hotplug = 1, - IVB_PIPE_OFFSETS, - IVB_CURSOR_OFFSETS, - IVB_COLORS, +static const struct platform_desc ivb_desc = { + .info = &(const struct intel_display_device_info) { + .has_hotplug = 1, + IVB_PIPE_OFFSETS, + IVB_CURSOR_OFFSETS, + IVB_COLORS, - .__runtime_defaults.ip.ver = 7, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), - .__runtime_defaults.cpu_transcoder_mask = + .__runtime_defaults.ip.ver = 7, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info vlv_display = { - .has_gmch = 1, - .has_hotplug = 1, - .mmio_offset = VLV_DISPLAY_BASE, - I9XX_PIPE_OFFSETS, - I9XX_CURSOR_OFFSETS, - I9XX_COLORS, - - .__runtime_defaults.ip.ver = 7, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), - .__runtime_defaults.cpu_transcoder_mask = +static const struct platform_desc vlv_desc = { + .info = &(const struct intel_display_device_info) { + .has_gmch = 1, + .has_hotplug = 1, + .mmio_offset = VLV_DISPLAY_BASE, + I9XX_PIPE_OFFSETS, + I9XX_CURSOR_OFFSETS, + I9XX_COLORS, + + .__runtime_defaults.ip.ver = 7, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */ + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* HDMI/DP B/C */ + }, }; -static const struct intel_display_device_info hsw_display = { - .has_ddi = 1, - .has_dp_mst = 1, - .has_fpga_dbg = 1, - .has_hotplug = 1, - .has_psr = 1, - .has_psr_hw_tracking = 1, - HSW_PIPE_OFFSETS, - IVB_CURSOR_OFFSETS, - IVB_COLORS, - - .__runtime_defaults.ip.ver = 7, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), - .__runtime_defaults.cpu_transcoder_mask = +static const struct platform_desc hsw_desc = { + .info = &(const struct intel_display_device_info) { + .has_ddi = 1, + .has_dp_mst = 1, + .has_fpga_dbg = 1, + .has_hotplug = 1, + .has_psr = 1, + .has_psr_hw_tracking = 1, + HSW_PIPE_OFFSETS, + IVB_CURSOR_OFFSETS, + IVB_COLORS, + + .__runtime_defaults.ip.ver = 7, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info bdw_display = { - .has_ddi = 1, - .has_dp_mst = 1, - .has_fpga_dbg = 1, - .has_hotplug = 1, - .has_psr = 1, - .has_psr_hw_tracking = 1, - HSW_PIPE_OFFSETS, - IVB_CURSOR_OFFSETS, - IVB_COLORS, - - .__runtime_defaults.ip.ver = 8, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), - .__runtime_defaults.cpu_transcoder_mask = +static const struct platform_desc bdw_desc = { + .info = &(const struct intel_display_device_info) { + .has_ddi = 1, + .has_dp_mst = 1, + .has_fpga_dbg = 1, + .has_hotplug = 1, + .has_psr = 1, + .has_psr_hw_tracking = 1, + HSW_PIPE_OFFSETS, + IVB_CURSOR_OFFSETS, + IVB_COLORS, + + .__runtime_defaults.ip.ver = 8, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), - .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), + .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), + }, }; -static const struct intel_display_device_info chv_display = { - .has_hotplug = 1, - .has_gmch = 1, - .mmio_offset = VLV_DISPLAY_BASE, - CHV_PIPE_OFFSETS, - CHV_CURSOR_OFFSETS, - CHV_COLORS, - - .__runtime_defaults.ip.ver = 8, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), - .__runtime_defaults.cpu_transcoder_mask = +static const struct platform_desc chv_desc = { + .info = &(const struct intel_display_device_info) { + .has_hotplug = 1, + .has_gmch = 1, + .mmio_offset = VLV_DISPLAY_BASE, + CHV_PIPE_OFFSETS, + CHV_CURSOR_OFFSETS, + CHV_COLORS, + + .__runtime_defaults.ip.ver = 8, + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), - .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */ + .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), /* HDMI/DP B/C/D */ + }, }; static const struct intel_display_device_info skl_display = { @@ -467,13 +515,29 @@ static const struct intel_display_device_info skl_display = { .__runtime_defaults.has_hdcp = 1, .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), .__runtime_defaults.cpu_transcoder_mask = - BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | - BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), + BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | + BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), }; -#define GEN9_LP_DISPLAY \ +static const struct platform_desc skl_desc = { + .info = &skl_display, +}; + +static const struct platform_desc kbl_desc = { + .info = &skl_display, +}; + +static const struct platform_desc cfl_desc = { + .info = &skl_display, +}; + +static const struct platform_desc cml_desc = { + .info = &skl_display, +}; + +#define GEN9_LP_DISPLAY \ .dbuf.slice_mask = BIT(DBUF_S1), \ .has_dp_mst = 1, \ .has_ddi = 1, \ @@ -496,19 +560,23 @@ static const struct intel_display_device_info skl_display = { BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \ .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) -static const struct intel_display_device_info bxt_display = { - GEN9_LP_DISPLAY, - .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ +static const struct platform_desc bxt_desc = { + .info = &(const struct intel_display_device_info) { + GEN9_LP_DISPLAY, + .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ - .__runtime_defaults.ip.ver = 9, + .__runtime_defaults.ip.ver = 9, + }, }; -static const struct intel_display_device_info glk_display = { - GEN9_LP_DISPLAY, - .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ - GLK_COLORS, +static const struct platform_desc glk_desc = { + .info = &(const struct intel_display_device_info) { + GEN9_LP_DISPLAY, + .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ + GLK_COLORS, - .__runtime_defaults.ip.ver = 10, + .__runtime_defaults.ip.ver = 10, + }, }; #define ICL_DISPLAY \ @@ -552,10 +620,12 @@ static const struct intel_display_device_info glk_display = { BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) -static const struct intel_display_device_info icl_display = { - ICL_DISPLAY, +static const struct platform_desc icl_desc = { + .info = &(const struct intel_display_device_info) { + ICL_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E), + }, }; static const struct intel_display_device_info jsl_ehl_display = { @@ -564,6 +634,14 @@ static const struct intel_display_device_info jsl_ehl_display = { .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D), }; +static const struct platform_desc jsl_desc = { + .info = &jsl_ehl_display, +}; + +static const struct platform_desc ehl_desc = { + .info = &jsl_ehl_display, +}; + #define XE_D_DISPLAY \ .abox_mask = GENMASK(2, 1), \ .dbuf.size = 2048, \ @@ -607,44 +685,52 @@ static const struct intel_display_device_info jsl_ehl_display = { BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) -static const struct intel_display_device_info tgl_display = { - XE_D_DISPLAY, +static const struct platform_desc tgl_desc = { + .info = &(const struct intel_display_device_info) { + XE_D_DISPLAY, - /* - * FIXME DDI C/combo PHY C missing due to combo PHY - * code making a mess on SKUs where the PHY is missing. - */ - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | + /* + * FIXME DDI C/combo PHY C missing due to combo PHY + * code making a mess on SKUs where the PHY is missing. + */ + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4) | BIT(PORT_TC5) | BIT(PORT_TC6), + }, }; -static const struct intel_display_device_info dg1_display = { - XE_D_DISPLAY, +static const struct platform_desc dg1_desc = { + .info = &(const struct intel_display_device_info) { + XE_D_DISPLAY, - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2), + }, }; -static const struct intel_display_device_info rkl_display = { - XE_D_DISPLAY, - .abox_mask = BIT(0), - .has_hti = 1, - .has_psr_hw_tracking = 0, +static const struct platform_desc rkl_desc = { + .info = &(const struct intel_display_device_info) { + XE_D_DISPLAY, + .abox_mask = BIT(0), + .has_hti = 1, + .has_psr_hw_tracking = 0, - .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), - .__runtime_defaults.cpu_transcoder_mask = + .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), + .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), - .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_TC1) | BIT(PORT_TC2), + }, }; -static const struct intel_display_device_info adl_s_display = { - XE_D_DISPLAY, - .has_hti = 1, - .has_psr_hw_tracking = 0, +static const struct platform_desc adl_s_desc = { + .info = &(const struct intel_display_device_info) { + XE_D_DISPLAY, + .has_hti = 1, + .has_psr_hw_tracking = 0, - .__runtime_defaults.port_mask = BIT(PORT_A) | + .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), + }, }; #define XE_LPD_FEATURES \ @@ -703,6 +789,10 @@ static const struct intel_display_device_info xe_lpd_display = { BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), }; +static const struct platform_desc adl_p_desc = { + .info = &xe_lpd_display, +}; + static const struct intel_display_device_info xe_hpd_display = { XE_LPD_FEATURES, .has_cdclk_squash = 1, @@ -714,6 +804,10 @@ static const struct intel_display_device_info xe_hpd_display = { BIT(PORT_TC1), }; +static const struct platform_desc dg2_desc = { + .info = &xe_hpd_display, +}; + #define XE_LPDP_FEATURES \ .abox_mask = GENMASK(1, 0), \ .color = { \ @@ -795,54 +889,54 @@ static bool has_no_display(struct pci_dev *pdev) return pci_match_id(ids, pdev); } -#define INTEL_DISPLAY_DEVICE(_id, _info) { .devid = (_id), .info = (_info) } +#define INTEL_DISPLAY_DEVICE(_id, _desc) { .devid = (_id), .desc = (_desc) } static const struct { u32 devid; - const struct intel_display_device_info *info; + const struct platform_desc *desc; } intel_display_ids[] = { - INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_display), - INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_display), - INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_display), - INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_display), - INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_display), - INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_display), - INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_display), - INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_display), - INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_display), - INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_display), - INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_display), - INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_display), - INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_display), - INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_display), - INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_display), - INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_display), - INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_display), - INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_display), - INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_display), - INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_display), - INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_display), - INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_display), - INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), - INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_display), - INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_display), - INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), - INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), - INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &skl_display), - INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &skl_display), - INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_display), - INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display), - INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_ehl_display), - INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_display), - INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_display), - INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_display), - INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display), - INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_display), - INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), - INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), - INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), - INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &xe_lpd_display), - INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &xe_hpd_display), + INTEL_I830_IDS(INTEL_DISPLAY_DEVICE, &i830_desc), + INTEL_I845G_IDS(INTEL_DISPLAY_DEVICE, &i845_desc), + INTEL_I85X_IDS(INTEL_DISPLAY_DEVICE, &i85x_desc), + INTEL_I865G_IDS(INTEL_DISPLAY_DEVICE, &i865g_desc), + INTEL_I915G_IDS(INTEL_DISPLAY_DEVICE, &i915g_desc), + INTEL_I915GM_IDS(INTEL_DISPLAY_DEVICE, &i915gm_desc), + INTEL_I945G_IDS(INTEL_DISPLAY_DEVICE, &i945g_desc), + INTEL_I945GM_IDS(INTEL_DISPLAY_DEVICE, &i945gm_desc), + INTEL_I965G_IDS(INTEL_DISPLAY_DEVICE, &i965g_desc), + INTEL_G33_IDS(INTEL_DISPLAY_DEVICE, &g33_desc), + INTEL_I965GM_IDS(INTEL_DISPLAY_DEVICE, &i965gm_desc), + INTEL_GM45_IDS(INTEL_DISPLAY_DEVICE, &gm45_desc), + INTEL_G45_IDS(INTEL_DISPLAY_DEVICE, &g45_desc), + INTEL_PNV_IDS(INTEL_DISPLAY_DEVICE, &pnv_desc), + INTEL_ILK_D_IDS(INTEL_DISPLAY_DEVICE, &ilk_d_desc), + INTEL_ILK_M_IDS(INTEL_DISPLAY_DEVICE, &ilk_m_desc), + INTEL_SNB_IDS(INTEL_DISPLAY_DEVICE, &snb_desc), + INTEL_IVB_IDS(INTEL_DISPLAY_DEVICE, &ivb_desc), + INTEL_HSW_IDS(INTEL_DISPLAY_DEVICE, &hsw_desc), + INTEL_VLV_IDS(INTEL_DISPLAY_DEVICE, &vlv_desc), + INTEL_BDW_IDS(INTEL_DISPLAY_DEVICE, &bdw_desc), + INTEL_CHV_IDS(INTEL_DISPLAY_DEVICE, &chv_desc), + INTEL_SKL_IDS(INTEL_DISPLAY_DEVICE, &skl_desc), + INTEL_BXT_IDS(INTEL_DISPLAY_DEVICE, &bxt_desc), + INTEL_GLK_IDS(INTEL_DISPLAY_DEVICE, &glk_desc), + INTEL_KBL_IDS(INTEL_DISPLAY_DEVICE, &kbl_desc), + INTEL_CFL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc), + INTEL_WHL_IDS(INTEL_DISPLAY_DEVICE, &cfl_desc), + INTEL_CML_IDS(INTEL_DISPLAY_DEVICE, &cml_desc), + INTEL_ICL_IDS(INTEL_DISPLAY_DEVICE, &icl_desc), + INTEL_EHL_IDS(INTEL_DISPLAY_DEVICE, &ehl_desc), + INTEL_JSL_IDS(INTEL_DISPLAY_DEVICE, &jsl_desc), + INTEL_TGL_IDS(INTEL_DISPLAY_DEVICE, &tgl_desc), + INTEL_DG1_IDS(INTEL_DISPLAY_DEVICE, &dg1_desc), + INTEL_RKL_IDS(INTEL_DISPLAY_DEVICE, &rkl_desc), + INTEL_ADLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc), + INTEL_RPLS_IDS(INTEL_DISPLAY_DEVICE, &adl_s_desc), + INTEL_ADLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), + INTEL_ADLN_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), + INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), + INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), + INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &dg2_desc), /* * Do not add any GMD_ID-based platforms to this list. They will @@ -909,7 +1003,7 @@ probe_display(struct drm_i915_private *i915) for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { if (intel_display_ids[i].devid == pdev->device) - return intel_display_ids[i].info; + return intel_display_ids[i].desc->info; } drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n", -- cgit From f498d28977ab76ede14d4a78047e54a215c0a9d9 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 22 May 2024 20:33:43 +0300 Subject: drm/i915: add LNL PCI IDs Although not supported by i915 core, the display code needs to know the LNL PCI IDs. Long term, xe and i915 should probably share the file defining PCI IDs. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/d2baf7f89ed4df63674dac3d59982de69a7b14d4.1716399081.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- include/drm/i915_pciids.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 3e39d644ebaa..7ae7ee11ef38 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -783,4 +783,10 @@ MACRO__(0x7DD1, ## __VA_ARGS__), \ MACRO__(0x7DD5, ## __VA_ARGS__) +/* LNL */ +#define INTEL_LNL_IDS(MACRO__, ...) \ + MACRO__(0x6420, ## __VA_ARGS__), \ + MACRO__(0x64A0, ## __VA_ARGS__), \ + MACRO__(0x64B0, ## __VA_ARGS__) + #endif /* _I915_PCIIDS_H */ -- cgit From 54836ee194f9be651d5efde0037d51b700e6b3e9 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 22 May 2024 20:33:44 +0300 Subject: drm/i915/display: change display probe to identify GMD ID based platforms We'll need to identify all platforms, including the ones that have display defined by GMD ID. Add MTL and LNL. Their display info will still be probed via GMD ID. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/e26f6a1a0aa2b051f49d76242194f819be3d83fd.1716399081.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_device.c | 44 +++++++++++++--------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index d1e03437abb3..aec69b573dd3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -21,7 +21,7 @@ __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); struct platform_desc { - const struct intel_display_device_info *info; + const struct intel_display_device_info *info; /* NULL for GMD ID */ }; static const struct intel_display_device_info no_display = {}; @@ -871,6 +871,17 @@ static const struct intel_display_device_info xe2_hpd_display = { BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), }; +/* + * Do not initialize the .info member of the platform desc for GMD ID based + * platforms. Their display will be probed automatically based on the IP version + * reported by the hardware. + */ +static const struct platform_desc mtl_desc = { +}; + +static const struct platform_desc lnl_desc = { +}; + __diag_pop(); /* @@ -937,12 +948,8 @@ static const struct { INTEL_RPLU_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), INTEL_RPLP_IDS(INTEL_DISPLAY_DEVICE, &adl_p_desc), INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &dg2_desc), - - /* - * Do not add any GMD_ID-based platforms to this list. They will - * be probed automatically based on the IP version reported by - * the hardware. - */ + INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc), + INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc), }; static const struct { @@ -995,20 +1002,15 @@ probe_gmdid_display(struct drm_i915_private *i915, struct intel_display_ip_ver * return NULL; } -static const struct intel_display_device_info * -probe_display(struct drm_i915_private *i915) +static const struct platform_desc *find_platform_desc(struct pci_dev *pdev) { - struct pci_dev *pdev = to_pci_dev(i915->drm.dev); int i; for (i = 0; i < ARRAY_SIZE(intel_display_ids); i++) { if (intel_display_ids[i].devid == pdev->device) - return intel_display_ids[i].desc->info; + return intel_display_ids[i].desc; } - drm_dbg(&i915->drm, "No display ID found for device ID %04x; disabling display.\n", - pdev->device); - return NULL; } @@ -1017,6 +1019,7 @@ void intel_display_device_probe(struct drm_i915_private *i915) struct pci_dev *pdev = to_pci_dev(i915->drm.dev); const struct intel_display_device_info *info; struct intel_display_ip_ver ip_ver = {}; + const struct platform_desc *desc; /* Add drm device backpointer as early as possible. */ i915->display.drm = &i915->drm; @@ -1028,11 +1031,16 @@ void intel_display_device_probe(struct drm_i915_private *i915) goto no_display; } - if (HAS_GMD_ID(i915)) - info = probe_gmdid_display(i915, &ip_ver); - else - info = probe_display(i915); + desc = find_platform_desc(pdev); + if (!desc) { + drm_dbg_kms(&i915->drm, "Unknown device ID %04x; disabling display.\n", + pdev->device); + goto no_display; + } + info = desc->info; + if (!info) + info = probe_gmdid_display(i915, &ip_ver); if (!info) goto no_display; -- cgit From b27259626a4f7f83ef0addf84e068e298ef7a231 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 22 May 2024 20:33:45 +0300 Subject: drm/i915/display: identify platforms with enum and name Add enum intel_display_platform and add that and name to all platform descriptors. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/5dec70931217cd93e3ef34f7a57f949f6683f048.1716399081.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_device.c | 48 ++++++++++++++++++ .../gpu/drm/i915/display/intel_display_device.h | 58 ++++++++++++++++++++++ 2 files changed, 106 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index aec69b573dd3..4f286173fb59 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -21,9 +21,15 @@ __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); struct platform_desc { + enum intel_display_platform platform; + const char *name; const struct intel_display_device_info *info; /* NULL for GMD ID */ }; +#define PLATFORM(_platform) \ + .platform = (INTEL_DISPLAY_##_platform), \ + .name = #_platform + static const struct intel_display_device_info no_display = {}; #define PIPE_A_OFFSET 0x70000 @@ -205,6 +211,7 @@ static const struct intel_display_device_info no_display = {}; .__runtime_defaults.cpu_transcoder_mask = BIT(TRANSCODER_A) static const struct platform_desc i830_desc = { + PLATFORM(I830), .info = &(const struct intel_display_device_info) { I830_DISPLAY, @@ -213,6 +220,7 @@ static const struct platform_desc i830_desc = { }; static const struct platform_desc i845_desc = { + PLATFORM(I845G), .info = &(const struct intel_display_device_info) { I845_DISPLAY, @@ -221,6 +229,7 @@ static const struct platform_desc i845_desc = { }; static const struct platform_desc i85x_desc = { + PLATFORM(I85X), .info = &(const struct intel_display_device_info) { I830_DISPLAY, @@ -230,6 +239,7 @@ static const struct platform_desc i85x_desc = { }; static const struct platform_desc i865g_desc = { + PLATFORM(I865G), .info = &(const struct intel_display_device_info) { I845_DISPLAY, @@ -251,6 +261,7 @@ static const struct platform_desc i865g_desc = { .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */ static const struct platform_desc i915g_desc = { + PLATFORM(I915G), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I845_COLORS, @@ -260,6 +271,7 @@ static const struct platform_desc i915g_desc = { }; static const struct platform_desc i915gm_desc = { + PLATFORM(I915GM), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I9XX_COLORS, @@ -272,6 +284,7 @@ static const struct platform_desc i915gm_desc = { }; static const struct platform_desc i945g_desc = { + PLATFORM(I945G), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I845_COLORS, @@ -282,6 +295,7 @@ static const struct platform_desc i945g_desc = { }; static const struct platform_desc i945gm_desc = { + PLATFORM(I915GM), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I9XX_COLORS, @@ -295,6 +309,7 @@ static const struct platform_desc i945gm_desc = { }; static const struct platform_desc g33_desc = { + PLATFORM(G33), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I845_COLORS, @@ -303,6 +318,7 @@ static const struct platform_desc g33_desc = { }; static const struct platform_desc pnv_desc = { + PLATFORM(PINEVIEW), .info = &(const struct intel_display_device_info) { GEN3_DISPLAY, I9XX_COLORS, @@ -323,6 +339,7 @@ static const struct platform_desc pnv_desc = { BIT(TRANSCODER_A) | BIT(TRANSCODER_B) static const struct platform_desc i965g_desc = { + PLATFORM(I965G), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, .has_overlay = 1, @@ -332,6 +349,7 @@ static const struct platform_desc i965g_desc = { }; static const struct platform_desc i965gm_desc = { + PLATFORM(I965GM), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, .has_overlay = 1, @@ -343,6 +361,7 @@ static const struct platform_desc i965gm_desc = { }; static const struct platform_desc g45_desc = { + PLATFORM(G45), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, @@ -351,6 +370,7 @@ static const struct platform_desc g45_desc = { }; static const struct platform_desc gm45_desc = { + PLATFORM(GM45), .info = &(const struct intel_display_device_info) { GEN4_DISPLAY, .supports_tv = 1, @@ -373,12 +393,14 @@ static const struct platform_desc gm45_desc = { .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) /* DP A, SDVO/HDMI/DP B, HDMI/DP C/D */ static const struct platform_desc ilk_d_desc = { + PLATFORM(IRONLAKE), .info = &(const struct intel_display_device_info) { ILK_DISPLAY, }, }; static const struct platform_desc ilk_m_desc = { + PLATFORM(IRONLAKE), .info = &(const struct intel_display_device_info) { ILK_DISPLAY, @@ -387,6 +409,7 @@ static const struct platform_desc ilk_m_desc = { }; static const struct platform_desc snb_desc = { + PLATFORM(SANDYBRIDGE), .info = &(const struct intel_display_device_info) { .has_hotplug = 1, I9XX_PIPE_OFFSETS, @@ -403,6 +426,7 @@ static const struct platform_desc snb_desc = { }; static const struct platform_desc ivb_desc = { + PLATFORM(IVYBRIDGE), .info = &(const struct intel_display_device_info) { .has_hotplug = 1, IVB_PIPE_OFFSETS, @@ -419,6 +443,7 @@ static const struct platform_desc ivb_desc = { }; static const struct platform_desc vlv_desc = { + PLATFORM(VALLEYVIEW), .info = &(const struct intel_display_device_info) { .has_gmch = 1, .has_hotplug = 1, @@ -436,6 +461,7 @@ static const struct platform_desc vlv_desc = { }; static const struct platform_desc hsw_desc = { + PLATFORM(HASWELL), .info = &(const struct intel_display_device_info) { .has_ddi = 1, .has_dp_mst = 1, @@ -458,6 +484,7 @@ static const struct platform_desc hsw_desc = { }; static const struct platform_desc bdw_desc = { + PLATFORM(BROADWELL), .info = &(const struct intel_display_device_info) { .has_ddi = 1, .has_dp_mst = 1, @@ -480,6 +507,7 @@ static const struct platform_desc bdw_desc = { }; static const struct platform_desc chv_desc = { + PLATFORM(CHERRYVIEW), .info = &(const struct intel_display_device_info) { .has_hotplug = 1, .has_gmch = 1, @@ -522,18 +550,22 @@ static const struct intel_display_device_info skl_display = { }; static const struct platform_desc skl_desc = { + PLATFORM(SKYLAKE), .info = &skl_display, }; static const struct platform_desc kbl_desc = { + PLATFORM(KABYLAKE), .info = &skl_display, }; static const struct platform_desc cfl_desc = { + PLATFORM(COFFEELAKE), .info = &skl_display, }; static const struct platform_desc cml_desc = { + PLATFORM(COMETLAKE), .info = &skl_display, }; @@ -561,6 +593,7 @@ static const struct platform_desc cml_desc = { .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) static const struct platform_desc bxt_desc = { + PLATFORM(BROXTON), .info = &(const struct intel_display_device_info) { GEN9_LP_DISPLAY, .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */ @@ -570,6 +603,7 @@ static const struct platform_desc bxt_desc = { }; static const struct platform_desc glk_desc = { + PLATFORM(GEMINILAKE), .info = &(const struct intel_display_device_info) { GEN9_LP_DISPLAY, .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ @@ -621,6 +655,7 @@ static const struct platform_desc glk_desc = { .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) static const struct platform_desc icl_desc = { + PLATFORM(ICELAKE), .info = &(const struct intel_display_device_info) { ICL_DISPLAY, @@ -635,10 +670,12 @@ static const struct intel_display_device_info jsl_ehl_display = { }; static const struct platform_desc jsl_desc = { + PLATFORM(JASPERLAKE), .info = &jsl_ehl_display, }; static const struct platform_desc ehl_desc = { + PLATFORM(ELKHARTLAKE), .info = &jsl_ehl_display, }; @@ -686,6 +723,7 @@ static const struct platform_desc ehl_desc = { .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) static const struct platform_desc tgl_desc = { + PLATFORM(TIGERLAKE), .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, @@ -699,6 +737,7 @@ static const struct platform_desc tgl_desc = { }; static const struct platform_desc dg1_desc = { + PLATFORM(DG1), .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, @@ -708,6 +747,7 @@ static const struct platform_desc dg1_desc = { }; static const struct platform_desc rkl_desc = { + PLATFORM(ROCKETLAKE), .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, .abox_mask = BIT(0), @@ -723,6 +763,7 @@ static const struct platform_desc rkl_desc = { }; static const struct platform_desc adl_s_desc = { + PLATFORM(ALDERLAKE_S), .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, .has_hti = 1, @@ -790,6 +831,7 @@ static const struct intel_display_device_info xe_lpd_display = { }; static const struct platform_desc adl_p_desc = { + PLATFORM(ALDERLAKE_P), .info = &xe_lpd_display, }; @@ -805,6 +847,7 @@ static const struct intel_display_device_info xe_hpd_display = { }; static const struct platform_desc dg2_desc = { + PLATFORM(DG2), .info = &xe_hpd_display, }; @@ -877,9 +920,11 @@ static const struct intel_display_device_info xe2_hpd_display = { * reported by the hardware. */ static const struct platform_desc mtl_desc = { + PLATFORM(METEORLAKE), }; static const struct platform_desc lnl_desc = { + PLATFORM(LUNARLAKE), }; __diag_pop(); @@ -1050,6 +1095,9 @@ void intel_display_device_probe(struct drm_i915_private *i915) &DISPLAY_INFO(i915)->__runtime_defaults, sizeof(*DISPLAY_RUNTIME_INFO(i915))); + drm_WARN_ON(&i915->drm, !desc->platform || !desc->name); + DISPLAY_RUNTIME_INFO(i915)->platform = desc->platform; + if (ip_ver.ver || ip_ver.rel || ip_ver.step) DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index fd2d03bfe8a6..8accd680a61e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -14,6 +14,62 @@ struct drm_i915_private; struct drm_printer; +/* Keep in gen based order, and chronological order within a gen */ +enum intel_display_platform { + INTEL_DISPLAY_PLATFORM_UNINITIALIZED = 0, + /* Display ver 2 */ + INTEL_DISPLAY_I830, + INTEL_DISPLAY_I845G, + INTEL_DISPLAY_I85X, + INTEL_DISPLAY_I865G, + /* Display ver 3 */ + INTEL_DISPLAY_I915G, + INTEL_DISPLAY_I915GM, + INTEL_DISPLAY_I945G, + INTEL_DISPLAY_I945GM, + INTEL_DISPLAY_G33, + INTEL_DISPLAY_PINEVIEW, + /* Display ver 4 */ + INTEL_DISPLAY_I965G, + INTEL_DISPLAY_I965GM, + INTEL_DISPLAY_G45, + INTEL_DISPLAY_GM45, + /* Display ver 5 */ + INTEL_DISPLAY_IRONLAKE, + /* Display ver 6 */ + INTEL_DISPLAY_SANDYBRIDGE, + /* Display ver 7 */ + INTEL_DISPLAY_IVYBRIDGE, + INTEL_DISPLAY_VALLEYVIEW, + INTEL_DISPLAY_HASWELL, + /* Display ver 8 */ + INTEL_DISPLAY_BROADWELL, + INTEL_DISPLAY_CHERRYVIEW, + /* Display ver 9 */ + INTEL_DISPLAY_SKYLAKE, + INTEL_DISPLAY_BROXTON, + INTEL_DISPLAY_KABYLAKE, + INTEL_DISPLAY_GEMINILAKE, + INTEL_DISPLAY_COFFEELAKE, + INTEL_DISPLAY_COMETLAKE, + /* Display ver 11 */ + INTEL_DISPLAY_ICELAKE, + INTEL_DISPLAY_JASPERLAKE, + INTEL_DISPLAY_ELKHARTLAKE, + /* Display ver 12 */ + INTEL_DISPLAY_TIGERLAKE, + INTEL_DISPLAY_ROCKETLAKE, + INTEL_DISPLAY_DG1, + INTEL_DISPLAY_ALDERLAKE_S, + /* Display ver 13 */ + INTEL_DISPLAY_ALDERLAKE_P, + INTEL_DISPLAY_DG2, + /* Display ver 14 (based on GMD ID) */ + INTEL_DISPLAY_METEORLAKE, + /* Display ver 20 (based on GMD ID) */ + INTEL_DISPLAY_LUNARLAKE, +}; + #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ /* Keep in alphabetical order */ \ func(cursor_needs_physical); \ @@ -111,6 +167,8 @@ struct drm_printer; (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) struct intel_display_runtime_info { + enum intel_display_platform platform; + struct intel_display_ip_ver { u16 ver; u16 rel; -- cgit From 16b79b3397a314bfc7f08d8e5d52e9b09c6a0481 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 22 May 2024 20:33:46 +0300 Subject: drm/i915/display: add support for subplatforms Add support for subplatforms. This is similar to what the xe driver is doing. The subplatform is an enum and it's exclusive, i.e. only one subplatform can match, and it completely identifies the platform and subplatform. This is different from i915 core, and is notable in the handling of ULT/ULX and RPL/RPL-U. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/8c04e32648395c0b745bc31a1edd4ef6f574bb70.1716399081.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- .../gpu/drm/i915/display/intel_display_device.c | 204 +++++++++++++++++++++ .../gpu/drm/i915/display/intel_display_device.h | 26 +++ 2 files changed, 230 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 4f286173fb59..34ae02ca4ad2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -20,9 +20,16 @@ __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info"); +struct subplatform_desc { + enum intel_display_subplatform subplatform; + const char *name; + const u16 *pciidlist; +}; + struct platform_desc { enum intel_display_platform platform; const char *name; + const struct subplatform_desc *subplatforms; const struct intel_display_device_info *info; /* NULL for GMD ID */ }; @@ -30,6 +37,8 @@ struct platform_desc { .platform = (INTEL_DISPLAY_##_platform), \ .name = #_platform +#define ID(id) (id) + static const struct intel_display_device_info no_display = {}; #define PIPE_A_OFFSET 0x70000 @@ -460,8 +469,26 @@ static const struct platform_desc vlv_desc = { }, }; +static const u16 hsw_ult_ids[] = { + INTEL_HSW_ULT_GT1_IDS(ID), + INTEL_HSW_ULT_GT2_IDS(ID), + INTEL_HSW_ULT_GT3_IDS(ID), + 0 +}; + +static const u16 hsw_ulx_ids[] = { + INTEL_HSW_ULX_GT1_IDS(ID), + INTEL_HSW_ULX_GT2_IDS(ID), + 0 +}; + static const struct platform_desc hsw_desc = { PLATFORM(HASWELL), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_HASWELL_ULT, "ULT", hsw_ult_ids }, + { INTEL_DISPLAY_HASWELL_ULX, "ULX", hsw_ulx_ids }, + {}, + }, .info = &(const struct intel_display_device_info) { .has_ddi = 1, .has_dp_mst = 1, @@ -483,8 +510,29 @@ static const struct platform_desc hsw_desc = { }, }; +static const u16 bdw_ult_ids[] = { + INTEL_BDW_ULT_GT1_IDS(ID), + INTEL_BDW_ULT_GT2_IDS(ID), + INTEL_BDW_ULT_GT3_IDS(ID), + INTEL_BDW_ULT_RSVD_IDS(ID), + 0 +}; + +static const u16 bdw_ulx_ids[] = { + INTEL_BDW_ULX_GT1_IDS(ID), + INTEL_BDW_ULX_GT2_IDS(ID), + INTEL_BDW_ULX_GT3_IDS(ID), + INTEL_BDW_ULX_RSVD_IDS(ID), + 0 +}; + static const struct platform_desc bdw_desc = { PLATFORM(BROADWELL), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_BROADWELL_ULT, "ULT", bdw_ult_ids }, + { INTEL_DISPLAY_BROADWELL_ULX, "ULX", bdw_ulx_ids }, + {}, + }, .info = &(const struct intel_display_device_info) { .has_ddi = 1, .has_dp_mst = 1, @@ -549,23 +597,89 @@ static const struct intel_display_device_info skl_display = { .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A), }; +static const u16 skl_ult_ids[] = { + INTEL_SKL_ULT_GT1_IDS(ID), + INTEL_SKL_ULT_GT2_IDS(ID), + INTEL_SKL_ULT_GT3_IDS(ID), + 0 +}; + +static const u16 skl_ulx_ids[] = { + INTEL_SKL_ULX_GT1_IDS(ID), + INTEL_SKL_ULX_GT2_IDS(ID), + 0 +}; + static const struct platform_desc skl_desc = { PLATFORM(SKYLAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_SKYLAKE_ULT, "ULT", skl_ult_ids }, + { INTEL_DISPLAY_SKYLAKE_ULX, "ULX", skl_ulx_ids }, + {}, + }, .info = &skl_display, }; +static const u16 kbl_ult_ids[] = { + INTEL_KBL_ULT_GT1_IDS(ID), + INTEL_KBL_ULT_GT2_IDS(ID), + INTEL_KBL_ULT_GT3_IDS(ID), + 0 +}; + +static const u16 kbl_ulx_ids[] = { + INTEL_KBL_ULX_GT1_IDS(ID), + INTEL_KBL_ULX_GT2_IDS(ID), + INTEL_AML_KBL_GT2_IDS(ID), + 0 +}; + static const struct platform_desc kbl_desc = { PLATFORM(KABYLAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_KABYLAKE_ULT, "ULT", kbl_ult_ids }, + { INTEL_DISPLAY_KABYLAKE_ULX, "ULX", kbl_ulx_ids }, + {}, + }, .info = &skl_display, }; +static const u16 cfl_ult_ids[] = { + INTEL_CFL_U_GT2_IDS(ID), + INTEL_CFL_U_GT3_IDS(ID), + INTEL_WHL_U_GT1_IDS(ID), + INTEL_WHL_U_GT2_IDS(ID), + INTEL_WHL_U_GT3_IDS(ID), + 0 +}; + +static const u16 cfl_ulx_ids[] = { + INTEL_AML_CFL_GT2_IDS(ID), + 0 +}; + static const struct platform_desc cfl_desc = { PLATFORM(COFFEELAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_COFFEELAKE_ULT, "ULT", cfl_ult_ids }, + { INTEL_DISPLAY_COFFEELAKE_ULX, "ULX", cfl_ulx_ids }, + {}, + }, .info = &skl_display, }; +static const u16 cml_ult_ids[] = { + INTEL_CML_U_GT1_IDS(ID), + INTEL_CML_U_GT2_IDS(ID), + 0 +}; + static const struct platform_desc cml_desc = { PLATFORM(COMETLAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_COMETLAKE_ULT, "ULT", cml_ult_ids }, + {}, + }, .info = &skl_display, }; @@ -654,8 +768,17 @@ static const struct platform_desc glk_desc = { BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) +static const u16 icl_port_f_ids[] = { + INTEL_ICL_PORT_F_IDS(ID), + 0 +}; + static const struct platform_desc icl_desc = { PLATFORM(ICELAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_ICELAKE_PORT_F, "Port F", icl_port_f_ids }, + {}, + }, .info = &(const struct intel_display_device_info) { ICL_DISPLAY, @@ -722,8 +845,17 @@ static const struct platform_desc ehl_desc = { BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) +static const u16 tgl_uy_ids[] = { + INTEL_TGL_GT2_IDS(ID), + 0 +}; + static const struct platform_desc tgl_desc = { PLATFORM(TIGERLAKE), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_TIGERLAKE_UY, "UY", tgl_uy_ids }, + {}, + }, .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, @@ -762,8 +894,17 @@ static const struct platform_desc rkl_desc = { }, }; +static const u16 adls_rpls_ids[] = { + INTEL_RPLS_IDS(ID), + 0 +}; + static const struct platform_desc adl_s_desc = { PLATFORM(ALDERLAKE_S), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, "RPL-S", adls_rpls_ids }, + {}, + }, .info = &(const struct intel_display_device_info) { XE_D_DISPLAY, .has_hti = 1, @@ -830,8 +971,29 @@ static const struct intel_display_device_info xe_lpd_display = { BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4), }; +static const u16 adlp_adln_ids[] = { + INTEL_ADLN_IDS(ID), + 0 +}; + +static const u16 adlp_rplu_ids[] = { + INTEL_RPLU_IDS(ID), + 0 +}; + +static const u16 adlp_rplp_ids[] = { + INTEL_RPLP_IDS(ID), + 0 +}; + static const struct platform_desc adl_p_desc = { PLATFORM(ALDERLAKE_P), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, "ADL-N", adlp_adln_ids }, + { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, "RPL-U", adlp_rplu_ids }, + { INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, "RPL-P", adlp_rplp_ids }, + {}, + }, .info = &xe_lpd_display, }; @@ -846,8 +1008,29 @@ static const struct intel_display_device_info xe_hpd_display = { BIT(PORT_TC1), }; +static const u16 dg2_g10_ids[] = { + INTEL_DG2_G10_IDS(ID), + 0 +}; + +static const u16 dg2_g11_ids[] = { + INTEL_DG2_G11_IDS(ID), + 0 +}; + +static const u16 dg2_g12_ids[] = { + INTEL_DG2_G12_IDS(ID), + 0 +}; + static const struct platform_desc dg2_desc = { PLATFORM(DG2), + .subplatforms = (const struct subplatform_desc[]) { + { INTEL_DISPLAY_DG2_G10, "G10", dg2_g10_ids }, + { INTEL_DISPLAY_DG2_G11, "G11", dg2_g11_ids }, + { INTEL_DISPLAY_DG2_G12, "G12", dg2_g12_ids }, + {}, + }, .info = &xe_hpd_display, }; @@ -1059,12 +1242,27 @@ static const struct platform_desc *find_platform_desc(struct pci_dev *pdev) return NULL; } +static const struct subplatform_desc * +find_subplatform_desc(struct pci_dev *pdev, const struct platform_desc *desc) +{ + const struct subplatform_desc *sp; + const u16 *id; + + for (sp = desc->subplatforms; sp && sp->subplatform; sp++) + for (id = sp->pciidlist; *id; id++) + if (*id == pdev->device) + return sp; + + return NULL; +} + void intel_display_device_probe(struct drm_i915_private *i915) { struct pci_dev *pdev = to_pci_dev(i915->drm.dev); const struct intel_display_device_info *info; struct intel_display_ip_ver ip_ver = {}; const struct platform_desc *desc; + const struct subplatform_desc *subdesc; /* Add drm device backpointer as early as possible. */ i915->display.drm = &i915->drm; @@ -1098,6 +1296,12 @@ void intel_display_device_probe(struct drm_i915_private *i915) drm_WARN_ON(&i915->drm, !desc->platform || !desc->name); DISPLAY_RUNTIME_INFO(i915)->platform = desc->platform; + subdesc = find_subplatform_desc(pdev, desc); + if (subdesc) { + drm_WARN_ON(&i915->drm, !subdesc->subplatform || !subdesc->name); + DISPLAY_RUNTIME_INFO(i915)->subplatform = subdesc->subplatform; + } + if (ip_ver.ver || ip_ver.rel || ip_ver.step) DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 8accd680a61e..e1d9947394dc 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -70,6 +70,31 @@ enum intel_display_platform { INTEL_DISPLAY_LUNARLAKE, }; +enum intel_display_subplatform { + INTEL_DISPLAY_SUBPLATFORM_UNINITIALIZED = 0, + INTEL_DISPLAY_HASWELL_ULT, + INTEL_DISPLAY_HASWELL_ULX, + INTEL_DISPLAY_BROADWELL_ULT, + INTEL_DISPLAY_BROADWELL_ULX, + INTEL_DISPLAY_SKYLAKE_ULT, + INTEL_DISPLAY_SKYLAKE_ULX, + INTEL_DISPLAY_KABYLAKE_ULT, + INTEL_DISPLAY_KABYLAKE_ULX, + INTEL_DISPLAY_COFFEELAKE_ULT, + INTEL_DISPLAY_COFFEELAKE_ULX, + INTEL_DISPLAY_COMETLAKE_ULT, + INTEL_DISPLAY_COMETLAKE_ULX, + INTEL_DISPLAY_ICELAKE_PORT_F, + INTEL_DISPLAY_TIGERLAKE_UY, + INTEL_DISPLAY_ALDERLAKE_S_RAPTORLAKE_S, + INTEL_DISPLAY_ALDERLAKE_P_ALDERLAKE_N, + INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_P, + INTEL_DISPLAY_ALDERLAKE_P_RAPTORLAKE_U, + INTEL_DISPLAY_DG2_G10, + INTEL_DISPLAY_DG2_G11, + INTEL_DISPLAY_DG2_G12, +}; + #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ /* Keep in alphabetical order */ \ func(cursor_needs_physical); \ @@ -168,6 +193,7 @@ enum intel_display_platform { struct intel_display_runtime_info { enum intel_display_platform platform; + enum intel_display_subplatform subplatform; struct intel_display_ip_ver { u16 ver; -- cgit From 53d916d9a425fb10e974318991b9748a05efaaea Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 22 May 2024 20:33:47 +0300 Subject: drm/i915/display: add probe message Add an info message about which display device was probed. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/f9a4d015a2981ace2ef5b40b189efeaf6b18fb29.1716399081.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index 34ae02ca4ad2..b8b56ace7583 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1305,6 +1305,11 @@ void intel_display_device_probe(struct drm_i915_private *i915) if (ip_ver.ver || ip_ver.rel || ip_ver.step) DISPLAY_RUNTIME_INFO(i915)->ip = ip_ver; + drm_info(&i915->drm, "Found %s%s%s (device ID %04x) display version %u.%02u\n", + desc->name, subdesc ? "/" : "", subdesc ? subdesc->name : "", + pdev->device, DISPLAY_RUNTIME_INFO(i915)->ip.ver, + DISPLAY_RUNTIME_INFO(i915)->ip.rel); + return; no_display: -- cgit From 4fab6b8b3033c02f11837a26d24297cce9a5b6ae Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 28 May 2024 21:49:43 +0300 Subject: drm/i915/cdclk: Plumb the full atomic state deeper MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Various parts of the cdclk code need access the full atomic state. Currently it's being dug out via the cdclk_state->base.state pointer, which is not great as that pointer isn't always valid. Instead plumb the full atomic state from the top so that it's clear that it is in fact valid. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240528184945.24083-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cdclk.c | 60 +++++++++++++++++------------- 1 file changed, 35 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index b78154c82a71..7ef8dcb1601a 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -113,7 +113,7 @@ struct intel_cdclk_funcs { void (*set_cdclk)(struct drm_i915_private *i915, const struct intel_cdclk_config *cdclk_config, enum pipe pipe); - int (*modeset_calc_cdclk)(struct intel_cdclk_state *state); + int (*modeset_calc_cdclk)(struct intel_atomic_state *state); u8 (*calc_voltage_level)(int cdclk); }; @@ -130,10 +130,11 @@ static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv, dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe); } -static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv, - struct intel_cdclk_state *cdclk_config) +static int intel_cdclk_modeset_calc_cdclk(struct intel_atomic_state *state) { - return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config); + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + + return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(state); } static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv, @@ -2834,10 +2835,11 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) return min_cdclk; } -static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) +static int intel_compute_min_cdclk(struct intel_atomic_state *state) { - struct intel_atomic_state *state = cdclk_state->base.state; struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_cdclk_state *cdclk_state = + intel_atomic_get_new_cdclk_state(state); const struct intel_bw_state *bw_state; struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; @@ -2916,10 +2918,11 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state) * future platforms this code will need to be * adjusted. */ -static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) +static int bxt_compute_min_voltage_level(struct intel_atomic_state *state) { - struct intel_atomic_state *state = cdclk_state->base.state; struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_cdclk_state *cdclk_state = + intel_atomic_get_new_cdclk_state(state); struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; u8 min_voltage_level; @@ -2952,13 +2955,14 @@ static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state) return min_voltage_level; } -static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) +static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state) { - struct intel_atomic_state *state = cdclk_state->base.state; struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_cdclk_state *cdclk_state = + intel_atomic_get_new_cdclk_state(state); int min_cdclk, cdclk; - min_cdclk = intel_compute_min_cdclk(cdclk_state); + min_cdclk = intel_compute_min_cdclk(state); if (min_cdclk < 0) return min_cdclk; @@ -2981,11 +2985,13 @@ static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) return 0; } -static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) +static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state) { + struct intel_cdclk_state *cdclk_state = + intel_atomic_get_new_cdclk_state(state); int min_cdclk, cdclk; - min_cdclk = intel_compute_min_cdclk(cdclk_state); + min_cdclk = intel_compute_min_cdclk(state); if (min_cdclk < 0) return min_cdclk; @@ -3008,10 +3014,11 @@ static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) return 0; } -static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) +static int skl_dpll0_vco(struct intel_atomic_state *state) { - struct intel_atomic_state *state = cdclk_state->base.state; struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_cdclk_state *cdclk_state = + intel_atomic_get_new_cdclk_state(state); struct intel_crtc *crtc; struct intel_crtc_state *crtc_state; int vco, i; @@ -3045,15 +3052,17 @@ static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state) return vco; } -static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) +static int skl_modeset_calc_cdclk(struct intel_atomic_state *state) { + struct intel_cdclk_state *cdclk_state = + intel_atomic_get_new_cdclk_state(state); int min_cdclk, cdclk, vco; - min_cdclk = intel_compute_min_cdclk(cdclk_state); + min_cdclk = intel_compute_min_cdclk(state); if (min_cdclk < 0) return min_cdclk; - vco = skl_dpll0_vco(cdclk_state); + vco = skl_dpll0_vco(state); cdclk = skl_calc_cdclk(min_cdclk, vco); @@ -3076,17 +3085,18 @@ static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) return 0; } -static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) +static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state) { - struct intel_atomic_state *state = cdclk_state->base.state; struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_cdclk_state *cdclk_state = + intel_atomic_get_new_cdclk_state(state); int min_cdclk, min_voltage_level, cdclk, vco; - min_cdclk = intel_compute_min_cdclk(cdclk_state); + min_cdclk = intel_compute_min_cdclk(state); if (min_cdclk < 0) return min_cdclk; - min_voltage_level = bxt_compute_min_voltage_level(cdclk_state); + min_voltage_level = bxt_compute_min_voltage_level(state); if (min_voltage_level < 0) return min_voltage_level; @@ -3114,7 +3124,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) return 0; } -static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) +static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state) { int min_cdclk; @@ -3123,7 +3133,7 @@ static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) * check that the required minimum frequency doesn't exceed * the actual cdclk frequency. */ - min_cdclk = intel_compute_min_cdclk(cdclk_state); + min_cdclk = intel_compute_min_cdclk(state); if (min_cdclk < 0) return min_cdclk; @@ -3263,7 +3273,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) new_cdclk_state->active_pipes = intel_calc_active_pipes(state, old_cdclk_state->active_pipes); - ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state); + ret = intel_cdclk_modeset_calc_cdclk(state); if (ret) return ret; -- cgit From 5010375afab51fe80867ac15900f49bdb2908b9e Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 28 May 2024 21:49:44 +0300 Subject: drm/i915: Plumb the full atomic state into icl_check_nv12_planes() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit icl_check_nv12_planes() needs the full atomic state. Instead of digging that out from dubious sources plumb it in explicitly. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240528184945.24083-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 765a7ab04a1c..7370acdd6b8b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -4034,11 +4034,12 @@ static int icl_add_linked_planes(struct intel_atomic_state *state) return 0; } -static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state) +static int icl_check_nv12_planes(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state); + struct drm_i915_private *dev_priv = to_i915(state->base.dev); + struct intel_crtc_state *crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); struct intel_plane *plane, *linked; struct intel_plane_state *plane_state; int i; @@ -5819,7 +5820,7 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) new_crtc_state, i) { u8 old_active_planes, new_active_planes; - ret = icl_check_nv12_planes(new_crtc_state); + ret = icl_check_nv12_planes(state, crtc); if (ret) return ret; -- cgit From b84641c0a1742b79084ddc4124e2010f3f09888a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 28 May 2024 21:49:45 +0300 Subject: drm/i915: Plumb the full atomic state into skl_ddb_add_affected_planes() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit skl_ddb_add_affected_planes() needs the full atomic state. Instead of digging that out from dubious sources plumb it in explicitly. The wm counterpart (skl_wm_add_affected_planes()) already does things in the proper way. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240528184945.24083-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/skl_watermark.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 2064f72da675..a2726364b34d 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -2429,12 +2429,14 @@ bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry *ddb, } static int -skl_ddb_add_affected_planes(const struct intel_crtc_state *old_crtc_state, - struct intel_crtc_state *new_crtc_state) +skl_ddb_add_affected_planes(struct intel_atomic_state *state, + struct intel_crtc *crtc) { - struct intel_atomic_state *state = to_intel_atomic_state(new_crtc_state->uapi.state); - struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); - struct drm_i915_private *i915 = to_i915(crtc->base.dev); + struct drm_i915_private *i915 = to_i915(state->base.dev); + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + struct intel_crtc_state *new_crtc_state = + intel_atomic_get_new_crtc_state(state, crtc); struct intel_plane *plane; for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { @@ -2489,7 +2491,6 @@ skl_compute_ddb(struct intel_atomic_state *state) struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_dbuf_state *old_dbuf_state; struct intel_dbuf_state *new_dbuf_state = NULL; - const struct intel_crtc_state *old_crtc_state; struct intel_crtc_state *new_crtc_state; struct intel_crtc *crtc; int ret, i; @@ -2577,14 +2578,12 @@ skl_compute_ddb(struct intel_atomic_state *state) return ret; } - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, - new_crtc_state, i) { + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { ret = skl_crtc_allocate_plane_ddb(state, crtc); if (ret) return ret; - ret = skl_ddb_add_affected_planes(old_crtc_state, - new_crtc_state); + ret = skl_ddb_add_affected_planes(state, crtc); if (ret) return ret; } -- cgit From edd27f8ee89d66a42dbd691567ca01909f33138d Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 28 May 2024 21:56:41 +0300 Subject: drm/i915: Reuse intel_mode_vblank_start() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Replace a few hand rolled copies of intel_mode_vblank_start() with the real thing. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dsb.c | 10 +++------- drivers/gpu/drm/i915/display/intel_vblank.c | 9 +++------ drivers/gpu/drm/i915/display/intel_vblank.h | 3 +++ 3 files changed, 9 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 4baaa92ceaec..319fbebd7008 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -328,14 +328,10 @@ static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state) unsigned int latency = skl_watermark_max_latency(i915, 0); int vblank_start; - if (crtc_state->vrr.enable) { + if (crtc_state->vrr.enable) vblank_start = intel_vrr_vmin_vblank_start(crtc_state); - } else { - vblank_start = adjusted_mode->crtc_vblank_start; - - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) - vblank_start = DIV_ROUND_UP(vblank_start, 2); - } + else + vblank_start = intel_mode_vblank_start(adjusted_mode); return max(0, vblank_start - intel_usecs_to_scanlines(adjusted_mode, latency)); } diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 951190bcbc50..1f57596f8208 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -89,9 +89,7 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc) htotal = mode->crtc_htotal; hsync_start = mode->crtc_hsync_start; - vbl_start = mode->crtc_vblank_start; - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - vbl_start = DIV_ROUND_UP(vbl_start, 2); + vbl_start = intel_mode_vblank_start(mode); /* Convert to pixel count */ vbl_start *= htotal; @@ -313,11 +311,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, htotal = mode->crtc_htotal; hsync_start = mode->crtc_hsync_start; vtotal = mode->crtc_vtotal; - vbl_start = mode->crtc_vblank_start; + vbl_start = intel_mode_vblank_start(mode); vbl_end = mode->crtc_vblank_end; if (mode->flags & DRM_MODE_FLAG_INTERLACE) { - vbl_start = DIV_ROUND_UP(vbl_start, 2); vbl_end /= 2; vtotal /= 2; } @@ -577,7 +574,7 @@ void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, spin_unlock_irqrestore(&i915->drm.vblank_time_lock, irqflags); } -static int intel_mode_vblank_start(const struct drm_display_mode *mode) +int intel_mode_vblank_start(const struct drm_display_mode *mode) { int vblank_start = mode->crtc_vblank_start; diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h index ec6c3da3eeac..08825a4d8fb7 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.h +++ b/drivers/gpu/drm/i915/display/intel_vblank.h @@ -10,6 +10,7 @@ #include struct drm_crtc; +struct drm_display_mode; struct intel_crtc; struct intel_crtc_state; @@ -19,6 +20,8 @@ struct intel_vblank_evade_ctx { bool need_vlv_dsi_wa; }; +int intel_mode_vblank_start(const struct drm_display_mode *mode); + void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state, struct intel_vblank_evade_ctx *evade); -- cgit From 1fea297844413e3e775332faa61229be8ff3679e Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 28 May 2024 21:56:42 +0300 Subject: drm/i915: Extract intel_mode_vblank_end() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extract intel_mode_vblank_end() in the same vein as intel_mode_vblank_start(). While we have only one use of this it seems nicer to unify the approach. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vblank.c | 16 ++++++++++++---- drivers/gpu/drm/i915/display/intel_vblank.h | 1 + 2 files changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 1f57596f8208..ba56015f2c40 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -312,12 +312,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, hsync_start = mode->crtc_hsync_start; vtotal = mode->crtc_vtotal; vbl_start = intel_mode_vblank_start(mode); - vbl_end = mode->crtc_vblank_end; + vbl_end = intel_mode_vblank_end(mode); - if (mode->flags & DRM_MODE_FLAG_INTERLACE) { - vbl_end /= 2; + if (mode->flags & DRM_MODE_FLAG_INTERLACE) vtotal /= 2; - } /* * Enter vblank critical section, as we will do multiple @@ -584,6 +582,16 @@ int intel_mode_vblank_start(const struct drm_display_mode *mode) return vblank_start; } +int intel_mode_vblank_end(const struct drm_display_mode *mode) +{ + int vblank_end = mode->crtc_vblank_end; + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + vblank_end /= 2; + + return vblank_end; +} + void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state, struct intel_vblank_evade_ctx *evade) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h index 08825a4d8fb7..6f11fd070f19 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.h +++ b/drivers/gpu/drm/i915/display/intel_vblank.h @@ -21,6 +21,7 @@ struct intel_vblank_evade_ctx { }; int intel_mode_vblank_start(const struct drm_display_mode *mode); +int intel_mode_vblank_end(const struct drm_display_mode *mode); void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state, -- cgit From 9677dd01ca1ada359f22cd129ccaeab9cd383567 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 28 May 2024 21:56:43 +0300 Subject: drm/i915: Extract intel_mode_vtotal() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We have several copies of code calculating the hardware's idea of vtotal. Pull that to a helper, similar to intel_mode_vblank_{start,end}(). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vblank.c | 40 ++++++++++++----------------- drivers/gpu/drm/i915/display/intel_vblank.h | 1 + 2 files changed, 18 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index ba56015f2c40..31fa5867e1a7 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -207,9 +207,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) if (crtc->mode_flags & I915_MODE_FLAG_GET_SCANLINE_FROM_TIMESTAMP) return __intel_get_crtc_scanline_from_timestamp(crtc); - vtotal = mode->crtc_vtotal; - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - vtotal /= 2; + vtotal = intel_mode_vtotal(mode); position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK; @@ -249,11 +247,7 @@ int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline) { const struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base); const struct drm_display_mode *mode = &vblank->hwmode; - int vtotal; - - vtotal = mode->crtc_vtotal; - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - vtotal /= 2; + int vtotal = intel_mode_vtotal(mode); return (scanline + vtotal - crtc->scanline_offset) % vtotal; } @@ -310,13 +304,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, htotal = mode->crtc_htotal; hsync_start = mode->crtc_hsync_start; - vtotal = mode->crtc_vtotal; + vtotal = intel_mode_vtotal(mode); vbl_start = intel_mode_vblank_start(mode); vbl_end = intel_mode_vblank_end(mode); - if (mode->flags & DRM_MODE_FLAG_INTERLACE) - vtotal /= 2; - /* * Enter vblank critical section, as we will do multiple * timing critical raw register reads, potentially with @@ -508,19 +499,12 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) * However if queried just before the start of vblank we'll get an * answer that's slightly in the future. */ - if (DISPLAY_VER(i915) == 2) { - int vtotal; - - vtotal = adjusted_mode->crtc_vtotal; - if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) - vtotal /= 2; - - return vtotal - 1; - } else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { + if (DISPLAY_VER(i915) == 2) + return intel_mode_vtotal(adjusted_mode) - 1; + else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return 2; - } else { + else return 1; - } } void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, @@ -592,6 +576,16 @@ int intel_mode_vblank_end(const struct drm_display_mode *mode) return vblank_end; } +int intel_mode_vtotal(const struct drm_display_mode *mode) +{ + int vtotal = mode->crtc_vtotal; + + if (mode->flags & DRM_MODE_FLAG_INTERLACE) + vtotal /= 2; + + return vtotal; +} + void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state, struct intel_vblank_evade_ctx *evade) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h index 6f11fd070f19..b51ae2c1039e 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.h +++ b/drivers/gpu/drm/i915/display/intel_vblank.h @@ -22,6 +22,7 @@ struct intel_vblank_evade_ctx { int intel_mode_vblank_start(const struct drm_display_mode *mode); int intel_mode_vblank_end(const struct drm_display_mode *mode); +int intel_mode_vtotal(const struct drm_display_mode *mode); void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state, -- cgit From 5316dd0d617bb98956f75cb33982efe1b26d8f19 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 28 May 2024 21:56:44 +0300 Subject: drm/i915: Simplify scanline_offset handling for gen2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently intel_crtc_scanline_offset() is careful to always return a positive offset. That is not actually necessary as long as we take care of negative values when applying the offset in __intel_get_crtc_scanline(). This simplifies intel_crtc_scanline_offset(), and makes the scanline_offfset arithmetic more symmetric between the forward (__intel_get_crtc_scanline()) and reverse (intel_crtc_scanline_to_hw()) directions. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vblank.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 31fa5867e1a7..b0e95a4c680d 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -240,7 +240,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) * See update_scanline_offset() for the details on the * scanline_offset adjustment. */ - return (position + crtc->scanline_offset) % vtotal; + return (position + vtotal + crtc->scanline_offset) % vtotal; } int intel_crtc_scanline_to_hw(struct intel_crtc *crtc, int scanline) @@ -470,7 +470,6 @@ void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; /* * The scanline counter increments at the leading edge of hsync. @@ -482,8 +481,7 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) * last active line), the scanline counter will read vblank_start-1. * * On gen2 the scanline counter starts counting from 1 instead - * of vtotal-1, so we have to subtract one (or rather add vtotal-1 - * to keep the value positive), instead of adding one. + * of vtotal-1, so we have to subtract one. * * On HSW+ the behaviour of the scanline counter depends on the output * type. For DP ports it behaves like most other platforms, but on HDMI @@ -500,7 +498,7 @@ static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) * answer that's slightly in the future. */ if (DISPLAY_VER(i915) == 2) - return intel_mode_vtotal(adjusted_mode) - 1; + return -1; else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) return 2; else -- cgit From 5b7f65acf1b083868e0fa9bf0617168794c201ff Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 28 May 2024 21:56:45 +0300 Subject: drm/i915: Move intel_crtc_scanline_offset() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I want to use intel_crtc_scanline_offset() in intel_crtc_scanline_to_hw(). Relocate intel_crtc_scanline_offset() a bit to avoid a forward declaration. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vblank.c | 76 ++++++++++++++--------------- 1 file changed, 38 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index b0e95a4c680d..eb80952b0cfd 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -188,6 +188,44 @@ static u32 __intel_get_crtc_scanline_from_timestamp(struct intel_crtc *crtc) return scanline; } +static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + /* + * The scanline counter increments at the leading edge of hsync. + * + * On most platforms it starts counting from vtotal-1 on the + * first active line. That means the scanline counter value is + * always one less than what we would expect. Ie. just after + * start of vblank, which also occurs at start of hsync (on the + * last active line), the scanline counter will read vblank_start-1. + * + * On gen2 the scanline counter starts counting from 1 instead + * of vtotal-1, so we have to subtract one. + * + * On HSW+ the behaviour of the scanline counter depends on the output + * type. For DP ports it behaves like most other platforms, but on HDMI + * there's an extra 1 line difference. So we need to add two instead of + * one to the value. + * + * On VLV/CHV DSI the scanline counter would appear to increment + * approx. 1/3 of a scanline before start of vblank. Unfortunately + * that means we can't tell whether we're in vblank or not while + * we're on that particular line. We must still set scanline_offset + * to 1 so that the vblank timestamps come out correct when we query + * the scanline counter from within the vblank interrupt handler. + * However if queried just before the start of vblank we'll get an + * answer that's slightly in the future. + */ + if (DISPLAY_VER(i915) == 2) + return -1; + else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) + return 2; + else + return 1; +} + /* * intel_de_read_fw(), only for fast reads of display block, no need for * forcewake etc. @@ -467,44 +505,6 @@ void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc) wait_for_pipe_scanline_moving(crtc, true); } -static int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - - /* - * The scanline counter increments at the leading edge of hsync. - * - * On most platforms it starts counting from vtotal-1 on the - * first active line. That means the scanline counter value is - * always one less than what we would expect. Ie. just after - * start of vblank, which also occurs at start of hsync (on the - * last active line), the scanline counter will read vblank_start-1. - * - * On gen2 the scanline counter starts counting from 1 instead - * of vtotal-1, so we have to subtract one. - * - * On HSW+ the behaviour of the scanline counter depends on the output - * type. For DP ports it behaves like most other platforms, but on HDMI - * there's an extra 1 line difference. So we need to add two instead of - * one to the value. - * - * On VLV/CHV DSI the scanline counter would appear to increment - * approx. 1/3 of a scanline before start of vblank. Unfortunately - * that means we can't tell whether we're in vblank or not while - * we're on that particular line. We must still set scanline_offset - * to 1 so that the vblank timestamps come out correct when we query - * the scanline counter from within the vblank interrupt handler. - * However if queried just before the start of vblank we'll get an - * answer that's slightly in the future. - */ - if (DISPLAY_VER(i915) == 2) - return -1; - else if (HAS_DDI(i915) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - return 2; - else - return 1; -} - void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state, bool vrr_enable) { -- cgit From d3e80f2dcf8c2aae09eca6b394eb253505e37dda Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Tue, 28 May 2024 21:56:46 +0300 Subject: drm/i915: Switch intel_usecs_to_scanlines() to 64bit maths MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Dotclocks can reach ~1GHz these days, so intel_usecs_to_scanlines(), with its 32bit maths, is currently limited to a few milliseconds. I want bigger numbers in DSB selftests, so switch over to 64bit maths. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240528185647.7765-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crtc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index bf6e74e99f5c..54b529bfc935 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -454,8 +454,8 @@ int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode, if (!adjusted_mode->crtc_htotal) return 1; - return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock, - 1000 * adjusted_mode->crtc_htotal); + return DIV_ROUND_UP_ULL(mul_u32_u32(usecs, adjusted_mode->crtc_clock), + 1000 * adjusted_mode->crtc_htotal); } /** -- cgit From 68cc33f6137071cf634bfb3869f69accfa13eaef Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 28 May 2024 14:15:38 +0300 Subject: drm/i915/gvt: use proper macros for DP AUX CH CTL registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the proper helpers for DP AUX CH CTL registers, instead of reinventing the wheels. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/f30d35f28ef106d6fb2faf100fe1c5e3a42dfa20.1716894909.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/handlers.c | 35 +++++++++++++---------------- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 +++---- 2 files changed, 20 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 840fea160aa6..06393b77a9e8 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1083,13 +1083,13 @@ static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu, if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) event = AUX_CHANNEL_A; - else if (reg == _PCH_DPB_AUX_CH_CTL || + else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_B)) || reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) event = AUX_CHANNEL_B; - else if (reg == _PCH_DPC_AUX_CH_CTL || + else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_C)) || reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) event = AUX_CHANNEL_C; - else if (reg == _PCH_DPD_AUX_CH_CTL || + else if (reg == i915_mmio_reg_offset(PCH_DP_AUX_CH_CTL(AUX_CH_D)) || reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) event = AUX_CHANNEL_D; else { @@ -1153,11 +1153,6 @@ static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd, } } -#define _REG_HSW_DP_AUX_CH_CTL(dp) \ - ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010) - -#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100) - #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8) #define dpy_is_valid_port(port) \ @@ -1181,12 +1176,14 @@ static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu, write_vreg(vgpu, offset, p_data, bytes); data = vgpu_vreg(vgpu, offset); - if ((GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9) - && offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) { + if (GRAPHICS_VER(vgpu->gvt->gt->i915) >= 9 && + offset != i915_mmio_reg_offset(DP_AUX_CH_CTL(port_index))) { /* SKL DPB/C/D aux ctl register changed */ return 0; } else if (IS_BROADWELL(vgpu->gvt->gt->i915) && - offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) { + offset != i915_mmio_reg_offset(port_index ? + PCH_DP_AUX_CH_CTL(port_index) : + DP_AUX_CH_CTL(port_index))) { /* write to the data registers */ return 0; } @@ -2299,12 +2296,12 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) gmbus_mmio_write); MMIO_F(PCH_GPIO_BASE, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL); - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, - dp_aux_ch_ctl_mmio_write); - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, - dp_aux_ch_ctl_mmio_write); - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, - dp_aux_ch_ctl_mmio_write); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, + dp_aux_ch_ctl_mmio_write); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, + dp_aux_ch_ctl_mmio_write); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL, + dp_aux_ch_ctl_mmio_write); MMIO_DH(PCH_ADPA, D_PRE_SKL, NULL, pch_adpa_mmio_write); @@ -2341,8 +2338,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL); MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write); - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_ALL, NULL, - dp_aux_ch_ctl_mmio_write); + MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4, 0, 0, 0, D_ALL, NULL, + dp_aux_ch_ctl_mmio_write); MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 349578cc0fc8..f5c4e4e2f11f 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -517,7 +517,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(SBI_DATA); MMIO_D(SBI_CTL_STAT); MMIO_D(PIXCLK_GATE); - MMIO_F(_MMIO(_DPA_AUX_CH_CTL), 6 * 4); + MMIO_F(DP_AUX_CH_CTL(AUX_CH_A), 6 * 4); MMIO_D(DDI_BUF_CTL(PORT_A)); MMIO_D(DDI_BUF_CTL(PORT_B)); MMIO_D(DDI_BUF_CTL(PORT_C)); @@ -888,9 +888,9 @@ static int iterate_pre_skl_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(FORCEWAKE_MT); MMIO_D(PCH_ADPA); - MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4); - MMIO_F(_MMIO(_PCH_DPC_AUX_CH_CTL), 6 * 4); - MMIO_F(_MMIO(_PCH_DPD_AUX_CH_CTL), 6 * 4); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_B), 6 * 4); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_C), 6 * 4); + MMIO_F(PCH_DP_AUX_CH_CTL(AUX_CH_D), 6 * 4); MMIO_F(_MMIO(0x70440), 0xc); MMIO_F(_MMIO(0x71440), 0xc); -- cgit From eccd1dbc49946e7621ec6545c4b31dd557375ee6 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 28 May 2024 14:15:39 +0300 Subject: drm/i915: remove unused DP AUX CH register macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The intermediate macros are no longer needed. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/c97134b22d802ae82b19c299b79807ee60d9fae5.1716894909.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index be57812a6b07..989cc5691490 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3603,28 +3603,14 @@ #define PCH_DP_B _MMIO(_PCH_DP_B) #define _PCH_DPB_AUX_CH_CTL 0xe4110 #define _PCH_DPB_AUX_CH_DATA1 0xe4114 -#define _PCH_DPB_AUX_CH_DATA2 0xe4118 -#define _PCH_DPB_AUX_CH_DATA3 0xe411c -#define _PCH_DPB_AUX_CH_DATA4 0xe4120 -#define _PCH_DPB_AUX_CH_DATA5 0xe4124 #define _PCH_DP_C 0xe4200 #define PCH_DP_C _MMIO(_PCH_DP_C) #define _PCH_DPC_AUX_CH_CTL 0xe4210 #define _PCH_DPC_AUX_CH_DATA1 0xe4214 -#define _PCH_DPC_AUX_CH_DATA2 0xe4218 -#define _PCH_DPC_AUX_CH_DATA3 0xe421c -#define _PCH_DPC_AUX_CH_DATA4 0xe4220 -#define _PCH_DPC_AUX_CH_DATA5 0xe4224 #define _PCH_DP_D 0xe4300 #define PCH_DP_D _MMIO(_PCH_DP_D) -#define _PCH_DPD_AUX_CH_CTL 0xe4310 -#define _PCH_DPD_AUX_CH_DATA1 0xe4314 -#define _PCH_DPD_AUX_CH_DATA2 0xe4318 -#define _PCH_DPD_AUX_CH_DATA3 0xe431c -#define _PCH_DPD_AUX_CH_DATA4 0xe4320 -#define _PCH_DPD_AUX_CH_DATA5 0xe4324 #define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) #define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ -- cgit From dd7d72c9a45c8d0a6544970846378aecbec4d35e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 28 May 2024 14:15:40 +0300 Subject: drm/i915: rearrange DP AUX register macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Follow the recommended style for grouping register macros. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/8ace710d8a1edac7e1af1ed12122fb6bc68114e9.1716894910.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp_aux_regs.h | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h index e642445364d2..a438f6003ce4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h @@ -23,12 +23,13 @@ #define _DPA_AUX_CH_CTL 0x64010 #define _DPB_AUX_CH_CTL 0x64110 -#define _XELPDP_USBC1_AUX_CH_CTL 0x16f210 -#define _XELPDP_USBC2_AUX_CH_CTL 0x16f410 #define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, \ _DPB_AUX_CH_CTL) #define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \ _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)) + +#define _XELPDP_USBC1_AUX_CH_CTL 0x16f210 +#define _XELPDP_USBC2_AUX_CH_CTL 0x16f410 #define _XELPDP_DP_AUX_CH_CTL(aux_ch) \ _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \ _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL, \ @@ -72,12 +73,13 @@ #define _DPA_AUX_CH_DATA1 0x64014 #define _DPB_AUX_CH_DATA1 0x64114 -#define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214 -#define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414 #define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \ _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ #define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \ _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ + +#define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214 +#define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414 #define _XELPDP_DP_AUX_CH_DATA(aux_ch, i) \ _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \ _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1, \ -- cgit From 4adb24f7341a972ac013fc523d33482e34dcbe71 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 28 May 2024 14:15:41 +0300 Subject: drm/i915: move PCH DP AUX CH regs to intel_dp_aux_regs.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the macros where they belong. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/9bc3a7bb34edc5dc17ffcb2a9e64edcef8c7a7b8.1716894910.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp_aux_regs.h | 8 ++++++++ drivers/gpu/drm/i915/i915_reg.h | 7 ------- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h index a438f6003ce4..4e109e81409b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h @@ -28,6 +28,10 @@ #define VLV_DP_AUX_CH_CTL(aux_ch) _MMIO(VLV_DISPLAY_BASE + \ _PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)) +#define _PCH_DPB_AUX_CH_CTL 0xe4110 +#define _PCH_DPC_AUX_CH_CTL 0xe4210 +#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) + #define _XELPDP_USBC1_AUX_CH_CTL 0x16f210 #define _XELPDP_USBC2_AUX_CH_CTL 0x16f410 #define _XELPDP_DP_AUX_CH_CTL(aux_ch) \ @@ -78,6 +82,10 @@ #define VLV_DP_AUX_CH_DATA(aux_ch, i) _MMIO(VLV_DISPLAY_BASE + _PORT(aux_ch, _DPA_AUX_CH_DATA1, \ _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ +#define _PCH_DPB_AUX_CH_DATA1 0xe4114 +#define _PCH_DPC_AUX_CH_DATA1 0xe4214 +#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ + #define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214 #define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414 #define _XELPDP_DP_AUX_CH_DATA(aux_ch, i) \ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 989cc5691490..06e41afd5c4e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3601,20 +3601,13 @@ #define _PCH_DP_B 0xe4100 #define PCH_DP_B _MMIO(_PCH_DP_B) -#define _PCH_DPB_AUX_CH_CTL 0xe4110 -#define _PCH_DPB_AUX_CH_DATA1 0xe4114 #define _PCH_DP_C 0xe4200 #define PCH_DP_C _MMIO(_PCH_DP_C) -#define _PCH_DPC_AUX_CH_CTL 0xe4210 -#define _PCH_DPC_AUX_CH_DATA1 0xe4214 #define _PCH_DP_D 0xe4300 #define PCH_DP_D _MMIO(_PCH_DP_D) -#define PCH_DP_AUX_CH_CTL(aux_ch) _MMIO_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_CTL, _PCH_DPC_AUX_CH_CTL) -#define PCH_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT((aux_ch) - AUX_CH_B, _PCH_DPB_AUX_CH_DATA1, _PCH_DPC_AUX_CH_DATA1) + (i) * 4) /* 5 registers */ - /* CPT */ #define _TRANS_DP_CTL_A 0xe0300 #define _TRANS_DP_CTL_B 0xe1300 -- cgit From f8e1c8f5b05fd2f11e8c611bede20cb738bc34cf Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 28 May 2024 14:15:42 +0300 Subject: drm/i915: remove intermediate _PCH_DP_* macros MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The intermediate macros are unused. Remove them. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/0145043ff9767de93cc3dc5119f0e7152965ebe6.1716894910.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 06e41afd5c4e..6877e2f0fbc3 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3599,14 +3599,9 @@ #define CNP_PWM_CGE_GATING_DISABLE (1 << 13) #define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12) -#define _PCH_DP_B 0xe4100 -#define PCH_DP_B _MMIO(_PCH_DP_B) - -#define _PCH_DP_C 0xe4200 -#define PCH_DP_C _MMIO(_PCH_DP_C) - -#define _PCH_DP_D 0xe4300 -#define PCH_DP_D _MMIO(_PCH_DP_D) +#define PCH_DP_B _MMIO(0xe4100) +#define PCH_DP_C _MMIO(0xe4200) +#define PCH_DP_D _MMIO(0xe4300) /* CPT */ #define _TRANS_DP_CTL_A 0xe0300 -- cgit From b156a3e9bf4fdb6bc3bf4152f70b56573ff1350d Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 13:07:46 +0300 Subject: drm/i915: drop unnecessary i915_reg.h includes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the register header refactoring, some of the includes of i915_reg.h have become unnecessary. Remove. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240530100747.328631-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/dvo_ns2501.c | 1 - drivers/gpu/drm/i915/display/intel_atomic.c | 1 - drivers/gpu/drm/i915/display/intel_atomic_plane.c | 1 - drivers/gpu/drm/i915/display/intel_dkl_phy.c | 1 - drivers/gpu/drm/i915/display/intel_dsb.c | 1 - drivers/gpu/drm/i915/display/intel_sprite.c | 1 - drivers/gpu/drm/i915/display/intel_vdsc.c | 1 - 7 files changed, 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/dvo_ns2501.c b/drivers/gpu/drm/i915/display/dvo_ns2501.c index 1df212fb000e..21486008dae9 100644 --- a/drivers/gpu/drm/i915/display/dvo_ns2501.c +++ b/drivers/gpu/drm/i915/display/dvo_ns2501.c @@ -27,7 +27,6 @@ */ #include "i915_drv.h" -#include "i915_reg.h" #include "intel_display_types.h" #include "intel_dvo_dev.h" diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 7a77ae3dc394..76aa10b6f647 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -35,7 +35,6 @@ #include #include "i915_drv.h" -#include "i915_reg.h" #include "intel_atomic.h" #include "intel_cdclk.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index a2a827070c33..a4ce39a7f265 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -39,7 +39,6 @@ #include #include "i915_config.h" -#include "i915_reg.h" #include "i9xx_plane_regs.h" #include "intel_atomic_plane.h" #include "intel_cdclk.h" diff --git a/drivers/gpu/drm/i915/display/intel_dkl_phy.c b/drivers/gpu/drm/i915/display/intel_dkl_phy.c index a001232ad445..b146b4c46943 100644 --- a/drivers/gpu/drm/i915/display/intel_dkl_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dkl_phy.c @@ -4,7 +4,6 @@ */ #include "i915_drv.h" -#include "i915_reg.h" #include "intel_de.h" #include "intel_display.h" diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 319fbebd7008..bdc53b7ad592 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -6,7 +6,6 @@ #include "i915_drv.h" #include "i915_irq.h" -#include "i915_reg.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index 36a253a19c74..e1c907f601da 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -39,7 +39,6 @@ #include #include "i915_drv.h" -#include "i915_reg.h" #include "i9xx_plane.h" #include "intel_atomic_plane.h" #include "intel_de.h" diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 17d6572f9d0a..d76e70846a8c 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -10,7 +10,6 @@ #include #include "i915_drv.h" -#include "i915_reg.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_types.h" -- cgit From b95702e275a78d0b65b4877fa83ab817a18df855 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 13:07:47 +0300 Subject: drm/i915: reduce includes in intel_clock_gating.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With the refactoring in the file, some excessive includes were left behind and are now unnecessary. Remove. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240530100747.328631-2-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/intel_clock_gating.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index db4fbb6a803d..26c4dbda076e 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -26,11 +26,7 @@ */ #include "display/i9xx_plane_regs.h" -#include "display/intel_de.h" #include "display/intel_display.h" -#include "display/intel_display_trace.h" -#include "display/intel_fbc_regs.h" -#include "display/skl_watermark.h" #include "gt/intel_engine_regs.h" #include "gt/intel_gt.h" -- cgit From 05255ccbf172cb3e4c18200e077b46cc109698f5 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 16:19:02 +0300 Subject: drm: move intel-gtt.h under include/drm/intel Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter Cc: Dave Airlie Cc: Lucas De Marchi Reviewed-by: Andi Shyti Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/ae224504d99cc6428da6dced9dcde2b7953624ef.1717075103.git.jani.nikula@intel.com --- drivers/char/agp/intel-agp.c | 2 +- drivers/char/agp/intel-gtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c | 2 +- drivers/gpu/drm/i915/gt/intel_gt.c | 2 +- include/drm/intel-gtt.h | 39 ------------------------------- include/drm/intel/intel-gtt.h | 39 +++++++++++++++++++++++++++++++ 7 files changed, 44 insertions(+), 44 deletions(-) delete mode 100644 include/drm/intel-gtt.h create mode 100644 include/drm/intel/intel-gtt.h diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c index c518b3a9db04..eec80db6402d 100644 --- a/drivers/char/agp/intel-agp.c +++ b/drivers/char/agp/intel-agp.c @@ -12,7 +12,7 @@ #include #include "agp.h" #include "intel-agp.h" -#include +#include static int intel_fetch_size(void) { diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c index bf6716ff863b..11f5cf853c46 100644 --- a/drivers/char/agp/intel-gtt.c +++ b/drivers/char/agp/intel-gtt.c @@ -25,7 +25,7 @@ #include #include "agp.h" #include "intel-agp.h" -#include +#include #include /* diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 0d0a0dc9f610..2717699c6591 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include "display/intel_display.h" #include "gem/i915_gem_lmem.h" diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c index 866c416afb73..59eed0a0ce90 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt_gmch.c @@ -5,7 +5,7 @@ #include "intel_ggtt_gmch.h" -#include +#include #include diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c index 626b166e67ef..a6c69a706fd7 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt.c +++ b/drivers/gpu/drm/i915/gt/intel_gt.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include "gem/i915_gem_internal.h" #include "gem/i915_gem_lmem.h" diff --git a/include/drm/intel-gtt.h b/include/drm/intel-gtt.h deleted file mode 100644 index cb0d5b7200c7..000000000000 --- a/include/drm/intel-gtt.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* Common header for intel-gtt.ko and i915.ko */ - -#ifndef _DRM_INTEL_GTT_H -#define _DRM_INTEL_GTT_H - -#include - -struct agp_bridge_data; -struct pci_dev; -struct sg_table; - -void intel_gmch_gtt_get(u64 *gtt_total, - phys_addr_t *mappable_base, - resource_size_t *mappable_end); - -int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, - struct agp_bridge_data *bridge); -void intel_gmch_remove(void); - -bool intel_gmch_enable_gtt(void); - -void intel_gmch_gtt_flush(void); -void intel_gmch_gtt_insert_page(dma_addr_t addr, - unsigned int pg, - unsigned int flags); -void intel_gmch_gtt_insert_sg_entries(struct sg_table *st, - unsigned int pg_start, - unsigned int flags); -void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); - -/* Special gtt memory types */ -#define AGP_DCACHE_MEMORY 1 -#define AGP_PHYS_MEMORY 2 - -/* flag for GFDT type */ -#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) - -#endif diff --git a/include/drm/intel/intel-gtt.h b/include/drm/intel/intel-gtt.h new file mode 100644 index 000000000000..cb0d5b7200c7 --- /dev/null +++ b/include/drm/intel/intel-gtt.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Common header for intel-gtt.ko and i915.ko */ + +#ifndef _DRM_INTEL_GTT_H +#define _DRM_INTEL_GTT_H + +#include + +struct agp_bridge_data; +struct pci_dev; +struct sg_table; + +void intel_gmch_gtt_get(u64 *gtt_total, + phys_addr_t *mappable_base, + resource_size_t *mappable_end); + +int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, + struct agp_bridge_data *bridge); +void intel_gmch_remove(void); + +bool intel_gmch_enable_gtt(void); + +void intel_gmch_gtt_flush(void); +void intel_gmch_gtt_insert_page(dma_addr_t addr, + unsigned int pg, + unsigned int flags); +void intel_gmch_gtt_insert_sg_entries(struct sg_table *st, + unsigned int pg_start, + unsigned int flags); +void intel_gmch_gtt_clear_range(unsigned int first_entry, unsigned int num_entries); + +/* Special gtt memory types */ +#define AGP_DCACHE_MEMORY 1 +#define AGP_PHYS_MEMORY 2 + +/* flag for GFDT type */ +#define AGP_USER_CACHED_MEMORY_GFDT (1 << 3) + +#endif -- cgit From 0706d57100fd0b2b34d50855726f648b8bfa7d2b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 16:19:03 +0300 Subject: drm: move i915_gsc_proxy_mei_interface.h under include/drm/intel Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter Cc: Dave Airlie Cc: Lucas De Marchi Cc: Tomas Winkler Reviewed-by: Andi Shyti Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/461662d528c3f327c81b764b7c883cd4519d8729.1717075103.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 2 +- drivers/gpu/drm/xe/xe_gsc_proxy.c | 2 +- drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c | 2 +- include/drm/i915_gsc_proxy_mei_interface.h | 53 ------------------------ include/drm/intel/i915_gsc_proxy_mei_interface.h | 53 ++++++++++++++++++++++++ 5 files changed, 56 insertions(+), 56 deletions(-) delete mode 100644 include/drm/i915_gsc_proxy_mei_interface.h create mode 100644 include/drm/intel/i915_gsc_proxy_mei_interface.h diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c index a7d5465655f9..e7619d81353c 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include "gt/intel_gt.h" #include "gt/intel_gt_print.h" diff --git a/drivers/gpu/drm/xe/xe_gsc_proxy.c b/drivers/gpu/drm/xe/xe_gsc_proxy.c index 1b908d238bd1..bd5d2f656441 100644 --- a/drivers/gpu/drm/xe/xe_gsc_proxy.c +++ b/drivers/gpu/drm/xe/xe_gsc_proxy.c @@ -10,7 +10,7 @@ #include #include -#include +#include #include "abi/gsc_proxy_commands_abi.h" #include "regs/xe_gsc_regs.h" diff --git a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c index 89364bdbb129..d5fbaf5d0c8e 100644 --- a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c +++ b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include /** * mei_gsc_proxy_send - Sends a proxy message to ME FW. diff --git a/include/drm/i915_gsc_proxy_mei_interface.h b/include/drm/i915_gsc_proxy_mei_interface.h deleted file mode 100644 index 850dfbf40607..000000000000 --- a/include/drm/i915_gsc_proxy_mei_interface.h +++ /dev/null @@ -1,53 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright (c) 2022-2023 Intel Corporation - */ - -#ifndef _I915_GSC_PROXY_MEI_INTERFACE_H_ -#define _I915_GSC_PROXY_MEI_INTERFACE_H_ - -#include - -struct device; -struct module; - -/** - * struct i915_gsc_proxy_component_ops - ops for GSC Proxy services. - * @owner: Module providing the ops - * @send: sends a proxy message from GSC FW to ME FW - * @recv: receives a proxy message for GSC FW from ME FW - */ -struct i915_gsc_proxy_component_ops { - struct module *owner; - - /** - * @send: Sends a proxy message to ME FW. - * @dev: device struct corresponding to the mei device - * @buf: message buffer to send - * @size: size of the message - * Return: bytes sent on success, negative errno value on failure - */ - int (*send)(struct device *dev, const void *buf, size_t size); - - /** - * @recv: Receives a proxy message from ME FW. - * @dev: device struct corresponding to the mei device - * @buf: message buffer to contain the received message - * @size: size of the buffer - * Return: bytes received on success, negative errno value on failure - */ - int (*recv)(struct device *dev, void *buf, size_t size); -}; - -/** - * struct i915_gsc_proxy_component - Used for communication between i915 and - * MEI drivers for GSC proxy services - * @mei_dev: device that provide the GSC proxy service. - * @ops: Ops implemented by GSC proxy driver, used by i915 driver. - */ -struct i915_gsc_proxy_component { - struct device *mei_dev; - const struct i915_gsc_proxy_component_ops *ops; -}; - -#endif /* _I915_GSC_PROXY_MEI_INTERFACE_H_ */ diff --git a/include/drm/intel/i915_gsc_proxy_mei_interface.h b/include/drm/intel/i915_gsc_proxy_mei_interface.h new file mode 100644 index 000000000000..850dfbf40607 --- /dev/null +++ b/include/drm/intel/i915_gsc_proxy_mei_interface.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2022-2023 Intel Corporation + */ + +#ifndef _I915_GSC_PROXY_MEI_INTERFACE_H_ +#define _I915_GSC_PROXY_MEI_INTERFACE_H_ + +#include + +struct device; +struct module; + +/** + * struct i915_gsc_proxy_component_ops - ops for GSC Proxy services. + * @owner: Module providing the ops + * @send: sends a proxy message from GSC FW to ME FW + * @recv: receives a proxy message for GSC FW from ME FW + */ +struct i915_gsc_proxy_component_ops { + struct module *owner; + + /** + * @send: Sends a proxy message to ME FW. + * @dev: device struct corresponding to the mei device + * @buf: message buffer to send + * @size: size of the message + * Return: bytes sent on success, negative errno value on failure + */ + int (*send)(struct device *dev, const void *buf, size_t size); + + /** + * @recv: Receives a proxy message from ME FW. + * @dev: device struct corresponding to the mei device + * @buf: message buffer to contain the received message + * @size: size of the buffer + * Return: bytes received on success, negative errno value on failure + */ + int (*recv)(struct device *dev, void *buf, size_t size); +}; + +/** + * struct i915_gsc_proxy_component - Used for communication between i915 and + * MEI drivers for GSC proxy services + * @mei_dev: device that provide the GSC proxy service. + * @ops: Ops implemented by GSC proxy driver, used by i915 driver. + */ +struct i915_gsc_proxy_component { + struct device *mei_dev; + const struct i915_gsc_proxy_component_ops *ops; +}; + +#endif /* _I915_GSC_PROXY_MEI_INTERFACE_H_ */ -- cgit From 1bb01bdab03f43e324dcc3a4f0cfc15c5a2e215e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 16:19:04 +0300 Subject: drm: move i915_component.h under include/drm/intel Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. v2: Also change Documentation/gpu/i915.rst (Andi) Cc: Daniel Vetter Cc: Dave Airlie Cc: Lucas De Marchi Cc: Tomas Winkler Cc: Jaroslav Kysela Cc: Takashi Iwai Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/a8c07233a8234858eb6711140482ef8db4c91cf4.1717075103.git.jani.nikula@intel.com --- Documentation/gpu/i915.rst | 2 +- drivers/gpu/drm/i915/display/intel_audio.c | 2 +- drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +- drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c | 2 +- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 2 +- drivers/gpu/drm/xe/xe_gsc_proxy.c | 2 +- drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c | 2 +- drivers/misc/mei/hdcp/mei_hdcp.c | 2 +- drivers/misc/mei/pxp/mei_pxp.c | 2 +- include/drm/i915_component.h | 56 ---------------------------- include/drm/intel/i915_component.h | 56 ++++++++++++++++++++++++++++ include/sound/hdaudio.h | 2 +- 12 files changed, 66 insertions(+), 66 deletions(-) delete mode 100644 include/drm/i915_component.h create mode 100644 include/drm/intel/i915_component.h diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 3113e36f14cf..ad59ae579237 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -150,7 +150,7 @@ High Definition Audio .. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c :internal: -.. kernel-doc:: include/drm/i915_component.h +.. kernel-doc:: include/drm/intel/i915_component.h :internal: Intel HDMI LPE Audio Support diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c index 4c031e97f9a5..b9bafec06fb8 100644 --- a/drivers/gpu/drm/i915/display/intel_audio.c +++ b/drivers/gpu/drm/i915/display/intel_audio.c @@ -26,7 +26,7 @@ #include #include -#include +#include #include "i915_drv.h" #include "intel_atomic.h" diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index 5767070248bb..ba3eca919900 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -13,7 +13,7 @@ #include #include -#include +#include #include "i915_drv.h" #include "i915_reg.h" diff --git a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c index e7619d81353c..d8edd7c054c8 100644 --- a/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c +++ b/drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.c @@ -5,7 +5,7 @@ #include -#include +#include #include #include "gt/intel_gt.h" diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index b00d6c280159..051b6cdcf721 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include "gem/i915_gem_lmem.h" #include "gt/intel_gt_print.h" diff --git a/drivers/gpu/drm/xe/xe_gsc_proxy.c b/drivers/gpu/drm/xe/xe_gsc_proxy.c index bd5d2f656441..8665ca7a727d 100644 --- a/drivers/gpu/drm/xe/xe_gsc_proxy.c +++ b/drivers/gpu/drm/xe/xe_gsc_proxy.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include #include "abi/gsc_proxy_commands_abi.h" diff --git a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c index d5fbaf5d0c8e..f52fe23a6c0b 100644 --- a/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c +++ b/drivers/misc/mei/gsc_proxy/mei_gsc_proxy.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include /** diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c index f8759a6c9ed3..e43ea536c947 100644 --- a/drivers/misc/mei/hdcp/mei_hdcp.c +++ b/drivers/misc/mei/hdcp/mei_hdcp.c @@ -23,7 +23,7 @@ #include #include #include -#include +#include #include #include "mei_hdcp.h" diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c index b1e4c23b31a3..5a7a4d8b0e23 100644 --- a/drivers/misc/mei/pxp/mei_pxp.c +++ b/drivers/misc/mei/pxp/mei_pxp.c @@ -19,7 +19,7 @@ #include #include #include -#include +#include #include #include "mei_pxp.h" diff --git a/include/drm/i915_component.h b/include/drm/i915_component.h deleted file mode 100644 index 4ea3b17aa143..000000000000 --- a/include/drm/i915_component.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright © 2014 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef _I915_COMPONENT_H_ -#define _I915_COMPONENT_H_ - -#include - -enum i915_component_type { - I915_COMPONENT_AUDIO = 1, - I915_COMPONENT_HDCP, - I915_COMPONENT_PXP, - I915_COMPONENT_GSC_PROXY, -}; - -/* MAX_PORT is the number of port - * It must be sync with I915_MAX_PORTS defined i915_drv.h - */ -#define MAX_PORTS 9 - -/** - * struct i915_audio_component - Used for direct communication between i915 and hda drivers - */ -struct i915_audio_component { - /** - * @base: the drm_audio_component base class - */ - struct drm_audio_component base; - - /** - * @aud_sample_rate: the array of audio sample rate per port - */ - int aud_sample_rate[MAX_PORTS]; -}; - -#endif /* _I915_COMPONENT_H_ */ diff --git a/include/drm/intel/i915_component.h b/include/drm/intel/i915_component.h new file mode 100644 index 000000000000..4ea3b17aa143 --- /dev/null +++ b/include/drm/intel/i915_component.h @@ -0,0 +1,56 @@ +/* + * Copyright © 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef _I915_COMPONENT_H_ +#define _I915_COMPONENT_H_ + +#include + +enum i915_component_type { + I915_COMPONENT_AUDIO = 1, + I915_COMPONENT_HDCP, + I915_COMPONENT_PXP, + I915_COMPONENT_GSC_PROXY, +}; + +/* MAX_PORT is the number of port + * It must be sync with I915_MAX_PORTS defined i915_drv.h + */ +#define MAX_PORTS 9 + +/** + * struct i915_audio_component - Used for direct communication between i915 and hda drivers + */ +struct i915_audio_component { + /** + * @base: the drm_audio_component base class + */ + struct drm_audio_component base; + + /** + * @aud_sample_rate: the array of audio sample rate per port + */ + int aud_sample_rate[MAX_PORTS]; +}; + +#endif /* _I915_COMPONENT_H_ */ diff --git a/include/sound/hdaudio.h b/include/sound/hdaudio.h index a73d7f34f4e5..00d1ab6936dd 100644 --- a/include/sound/hdaudio.h +++ b/include/sound/hdaudio.h @@ -18,7 +18,7 @@ #include #include #include -#include +#include /* codec node id */ typedef u16 hda_nid_t; -- cgit From a1ed6865df70d0b022f510691059219d0b715d84 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 16:19:05 +0300 Subject: drm: move intel_lpe_audio.h under include/drm/intel Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter Cc: Dave Airlie Cc: Lucas De Marchi Cc: Jaroslav Kysela Cc: Takashi Iwai Reviewed-by: Andi Shyti Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/2d645970a65cfd13e01fd8195b35bf9483ae9c2f.1717075103.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +- include/drm/intel/intel_lpe_audio.h | 51 ++++++++++++++++++++++++++ include/drm/intel_lpe_audio.h | 51 -------------------------- sound/x86/intel_hdmi_audio.c | 2 +- 5 files changed, 54 insertions(+), 54 deletions(-) create mode 100644 include/drm/intel/intel_lpe_audio.h delete mode 100644 include/drm/intel_lpe_audio.h diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 3767be0bdba8..06ec9ce7fe1c 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -38,7 +38,7 @@ #include #include #include -#include +#include #include "g4x_hdmi.h" #include "i915_drv.h" diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index 93e6cac9a4ed..f11626176fe2 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -68,7 +68,7 @@ #include #include -#include +#include #include "i915_drv.h" #include "i915_irq.h" diff --git a/include/drm/intel/intel_lpe_audio.h b/include/drm/intel/intel_lpe_audio.h new file mode 100644 index 000000000000..b6121c8fe539 --- /dev/null +++ b/include/drm/intel/intel_lpe_audio.h @@ -0,0 +1,51 @@ +/* + * Copyright © 2016 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef _INTEL_LPE_AUDIO_H_ +#define _INTEL_LPE_AUDIO_H_ + +#include +#include + +struct platform_device; + +#define HDMI_MAX_ELD_BYTES 128 + +struct intel_hdmi_lpe_audio_port_pdata { + u8 eld[HDMI_MAX_ELD_BYTES]; + int port; + int pipe; + int ls_clock; + bool dp_output; +}; + +struct intel_hdmi_lpe_audio_pdata { + struct intel_hdmi_lpe_audio_port_pdata port[3]; /* for ports B,C,D */ + int num_ports; + int num_pipes; + + void (*notify_audio_lpe)(struct platform_device *pdev, int port); /* port: 0==B,1==C,2==D */ + spinlock_t lpe_audio_slock; +}; + +#endif /* _I915_LPE_AUDIO_H_ */ diff --git a/include/drm/intel_lpe_audio.h b/include/drm/intel_lpe_audio.h deleted file mode 100644 index b6121c8fe539..000000000000 --- a/include/drm/intel_lpe_audio.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright © 2016 Intel Corporation - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS - * IN THE SOFTWARE. - */ - -#ifndef _INTEL_LPE_AUDIO_H_ -#define _INTEL_LPE_AUDIO_H_ - -#include -#include - -struct platform_device; - -#define HDMI_MAX_ELD_BYTES 128 - -struct intel_hdmi_lpe_audio_port_pdata { - u8 eld[HDMI_MAX_ELD_BYTES]; - int port; - int pipe; - int ls_clock; - bool dp_output; -}; - -struct intel_hdmi_lpe_audio_pdata { - struct intel_hdmi_lpe_audio_port_pdata port[3]; /* for ports B,C,D */ - int num_ports; - int num_pipes; - - void (*notify_audio_lpe)(struct platform_device *pdev, int port); /* port: 0==B,1==C,2==D */ - spinlock_t lpe_audio_slock; -}; - -#endif /* _I915_LPE_AUDIO_H_ */ diff --git a/sound/x86/intel_hdmi_audio.c b/sound/x86/intel_hdmi_audio.c index 02f5a7f9b728..d41ea09ffbe5 100644 --- a/sound/x86/intel_hdmi_audio.c +++ b/sound/x86/intel_hdmi_audio.c @@ -31,7 +31,7 @@ #include #include #include -#include +#include #include "intel_hdmi_audio.h" #define INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS 5000 -- cgit From 03c7918d0d52378d215712ff66c06a980a2119ab Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 16:19:06 +0300 Subject: drm: move i915_drm.h under include/drm/intel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. v2: Also fix comment in intel_pci_config.h (Ilpo) Cc: Daniel Vetter Cc: Dave Airlie Cc: Lucas De Marchi Cc: Bjorn Helgaas Cc: Hans de Goede Cc: Ilpo Järvinen Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/0e344a72e9be596ac2b8b55a26fd674a96f03cdc.1717075103.git.jani.nikula@intel.com --- arch/x86/kernel/early-quirks.c | 2 +- drivers/gpu/drm/i915/gem/i915_gem_stolen.c | 2 +- drivers/gpu/drm/i915/gt/intel_ggtt.c | 2 +- drivers/gpu/drm/i915/gt/intel_rps.c | 2 +- drivers/gpu/drm/i915/intel_pci_config.h | 2 +- drivers/gpu/drm/i915/soc/intel_gmch.c | 2 +- drivers/gpu/drm/xe/xe_ggtt.c | 2 +- drivers/platform/x86/intel_ips.c | 2 +- include/drm/i915_drm.h | 102 ----------------------------- include/drm/intel/i915_drm.h | 102 +++++++++++++++++++++++++++++ 10 files changed, 110 insertions(+), 110 deletions(-) delete mode 100644 include/drm/i915_drm.h create mode 100644 include/drm/intel/i915_drm.h diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index 1c137771c5d2..ec1a7943c228 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c index ad6dd7f3259b..30595b2b63e1 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_stolen.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_stolen.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include "gem/i915_gem_lmem.h" #include "gem/i915_gem_region.h" diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c index 2717699c6591..206a5e0fedf1 100644 --- a/drivers/gpu/drm/i915/gt/intel_ggtt.c +++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include #include "display/intel_display.h" diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index c9cb2a391942..70176be269d3 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -5,7 +5,7 @@ #include -#include +#include #include "display/intel_display.h" #include "display/intel_display_irq.h" diff --git a/drivers/gpu/drm/i915/intel_pci_config.h b/drivers/gpu/drm/i915/intel_pci_config.h index 23b8e519f333..ebe040828e20 100644 --- a/drivers/gpu/drm/i915/intel_pci_config.h +++ b/drivers/gpu/drm/i915/intel_pci_config.h @@ -31,7 +31,7 @@ static inline int intel_mmio_bar(int graphics_ver) } } -/* BSM in include/drm/i915_drm.h */ +/* BSM in include/drm/intel/i915_drm.h */ #define MCHBAR_I915 0x44 #define MCHBAR_I965 0x48 diff --git a/drivers/gpu/drm/i915/soc/intel_gmch.c b/drivers/gpu/drm/i915/soc/intel_gmch.c index 40874ebfb64c..734e9f2801ea 100644 --- a/drivers/gpu/drm/i915/soc/intel_gmch.c +++ b/drivers/gpu/drm/i915/soc/intel_gmch.c @@ -8,7 +8,7 @@ #include #include -#include +#include #include "i915_drv.h" #include "intel_gmch.h" diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c index 0d541f55b4fc..96fd8190ab7e 100644 --- a/drivers/gpu/drm/xe/xe_ggtt.c +++ b/drivers/gpu/drm/xe/xe_ggtt.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include "regs/xe_gt_regs.h" #include "regs/xe_gtt_defs.h" diff --git a/drivers/platform/x86/intel_ips.c b/drivers/platform/x86/intel_ips.c index ba38649cc142..2a88012958eb 100644 --- a/drivers/platform/x86/intel_ips.c +++ b/drivers/platform/x86/intel_ips.c @@ -59,7 +59,7 @@ #include #include #include -#include +#include #include #include #include "intel_ips.h" diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h deleted file mode 100644 index adff68538484..000000000000 --- a/include/drm/i915_drm.h +++ /dev/null @@ -1,102 +0,0 @@ -/* - * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. - * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR - * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, - * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE - * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - */ -#ifndef _I915_DRM_H_ -#define _I915_DRM_H_ - -#include - -/* For use by IPS driver */ -unsigned long i915_read_mch_val(void); -bool i915_gpu_raise(void); -bool i915_gpu_lower(void); -bool i915_gpu_busy(void); -bool i915_gpu_turbo_disable(void); - -/* Exported from arch/x86/kernel/early-quirks.c */ -extern struct resource intel_graphics_stolen_res; - -/* - * The Bridge device's PCI config space has information about the - * fb aperture size and the amount of pre-reserved memory. - * This is all handled in the intel-gtt.ko module. i915.ko only - * cares about the vga bit for the vga arbiter. - */ -#define INTEL_GMCH_CTRL 0x52 -#define INTEL_GMCH_VGA_DISABLE (1 << 1) -#define SNB_GMCH_CTRL 0x50 -#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ -#define SNB_GMCH_GGMS_MASK 0x3 -#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ -#define SNB_GMCH_GMS_MASK 0x1f -#define BDW_GMCH_GGMS_SHIFT 6 -#define BDW_GMCH_GGMS_MASK 0x3 -#define BDW_GMCH_GMS_SHIFT 8 -#define BDW_GMCH_GMS_MASK 0xff - -#define I830_GMCH_CTRL 0x52 - -#define I830_GMCH_GMS_MASK 0x70 -#define I830_GMCH_GMS_LOCAL 0x10 -#define I830_GMCH_GMS_STOLEN_512 0x20 -#define I830_GMCH_GMS_STOLEN_1024 0x30 -#define I830_GMCH_GMS_STOLEN_8192 0x40 - -#define I855_GMCH_GMS_MASK 0xF0 -#define I855_GMCH_GMS_STOLEN_0M 0x0 -#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) -#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) -#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) -#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) -#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) -#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) -#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) -#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) -#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) -#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) -#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) -#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) -#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) - -#define I830_DRB3 0x63 -#define I85X_DRB3 0x43 -#define I865_TOUD 0xc4 - -#define I830_ESMRAMC 0x91 -#define I845_ESMRAMC 0x9e -#define I85X_ESMRAMC 0x61 -#define TSEG_ENABLE (1 << 0) -#define I830_TSEG_SIZE_512K (0 << 1) -#define I830_TSEG_SIZE_1M (1 << 1) -#define I845_TSEG_SIZE_MASK (3 << 1) -#define I845_TSEG_SIZE_512K (2 << 1) -#define I845_TSEG_SIZE_1M (3 << 1) - -#define INTEL_BSM 0x5c -#define INTEL_GEN11_BSM_DW0 0xc0 -#define INTEL_GEN11_BSM_DW1 0xc4 -#define INTEL_BSM_MASK (-(1u << 20)) - -#endif /* _I915_DRM_H_ */ diff --git a/include/drm/intel/i915_drm.h b/include/drm/intel/i915_drm.h new file mode 100644 index 000000000000..adff68538484 --- /dev/null +++ b/include/drm/intel/i915_drm.h @@ -0,0 +1,102 @@ +/* + * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef _I915_DRM_H_ +#define _I915_DRM_H_ + +#include + +/* For use by IPS driver */ +unsigned long i915_read_mch_val(void); +bool i915_gpu_raise(void); +bool i915_gpu_lower(void); +bool i915_gpu_busy(void); +bool i915_gpu_turbo_disable(void); + +/* Exported from arch/x86/kernel/early-quirks.c */ +extern struct resource intel_graphics_stolen_res; + +/* + * The Bridge device's PCI config space has information about the + * fb aperture size and the amount of pre-reserved memory. + * This is all handled in the intel-gtt.ko module. i915.ko only + * cares about the vga bit for the vga arbiter. + */ +#define INTEL_GMCH_CTRL 0x52 +#define INTEL_GMCH_VGA_DISABLE (1 << 1) +#define SNB_GMCH_CTRL 0x50 +#define SNB_GMCH_GGMS_SHIFT 8 /* GTT Graphics Memory Size */ +#define SNB_GMCH_GGMS_MASK 0x3 +#define SNB_GMCH_GMS_SHIFT 3 /* Graphics Mode Select */ +#define SNB_GMCH_GMS_MASK 0x1f +#define BDW_GMCH_GGMS_SHIFT 6 +#define BDW_GMCH_GGMS_MASK 0x3 +#define BDW_GMCH_GMS_SHIFT 8 +#define BDW_GMCH_GMS_MASK 0xff + +#define I830_GMCH_CTRL 0x52 + +#define I830_GMCH_GMS_MASK 0x70 +#define I830_GMCH_GMS_LOCAL 0x10 +#define I830_GMCH_GMS_STOLEN_512 0x20 +#define I830_GMCH_GMS_STOLEN_1024 0x30 +#define I830_GMCH_GMS_STOLEN_8192 0x40 + +#define I855_GMCH_GMS_MASK 0xF0 +#define I855_GMCH_GMS_STOLEN_0M 0x0 +#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4) +#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4) +#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4) +#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4) +#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4) +#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4) +#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4) +#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4) +#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4) +#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4) +#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4) +#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4) +#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4) + +#define I830_DRB3 0x63 +#define I85X_DRB3 0x43 +#define I865_TOUD 0xc4 + +#define I830_ESMRAMC 0x91 +#define I845_ESMRAMC 0x9e +#define I85X_ESMRAMC 0x61 +#define TSEG_ENABLE (1 << 0) +#define I830_TSEG_SIZE_512K (0 << 1) +#define I830_TSEG_SIZE_1M (1 << 1) +#define I845_TSEG_SIZE_MASK (3 << 1) +#define I845_TSEG_SIZE_512K (2 << 1) +#define I845_TSEG_SIZE_1M (3 << 1) + +#define INTEL_BSM 0x5c +#define INTEL_GEN11_BSM_DW0 0xc0 +#define INTEL_GEN11_BSM_DW1 0xc4 +#define INTEL_BSM_MASK (-(1u << 20)) + +#endif /* _I915_DRM_H_ */ -- cgit From cce3819a5f5a55e08e5a3c9dcd1f46a3c5276ea8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 16:19:07 +0300 Subject: drm: move i915_pxp_tee_interface.h under include/drm/intel Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter Cc: Dave Airlie Cc: Lucas De Marchi Cc: Tomas Winkler Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/5c1626978d2552ef5732dcf9427c903046afb9c1.1717075103.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/pxp/intel_pxp_tee.c | 2 +- drivers/misc/mei/pxp/mei_pxp.c | 2 +- include/drm/i915_pxp_tee_interface.h | 62 ------------------------------ include/drm/intel/i915_pxp_tee_interface.h | 62 ++++++++++++++++++++++++++++++ 4 files changed, 64 insertions(+), 64 deletions(-) delete mode 100644 include/drm/i915_pxp_tee_interface.h create mode 100644 include/drm/intel/i915_pxp_tee_interface.h diff --git a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c index 051b6cdcf721..1784153f0cf8 100644 --- a/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_tee.c @@ -5,7 +5,7 @@ #include -#include +#include #include #include "gem/i915_gem_lmem.h" diff --git a/drivers/misc/mei/pxp/mei_pxp.c b/drivers/misc/mei/pxp/mei_pxp.c index 5a7a4d8b0e23..4268a868255f 100644 --- a/drivers/misc/mei/pxp/mei_pxp.c +++ b/drivers/misc/mei/pxp/mei_pxp.c @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include "mei_pxp.h" diff --git a/include/drm/i915_pxp_tee_interface.h b/include/drm/i915_pxp_tee_interface.h deleted file mode 100644 index a532d32f58f3..000000000000 --- a/include/drm/i915_pxp_tee_interface.h +++ /dev/null @@ -1,62 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2020 Intel Corporation - */ - -#ifndef _I915_PXP_TEE_INTERFACE_H_ -#define _I915_PXP_TEE_INTERFACE_H_ - -#include -#include -struct scatterlist; - -/** - * struct i915_pxp_component_ops - ops for PXP services. - */ -struct i915_pxp_component_ops { - /** - * @owner: Module providing the ops. - */ - struct module *owner; - - /** - * @send: Send a PXP message. - */ - int (*send)(struct device *dev, const void *message, size_t size, - unsigned long timeout_ms); - /** - * @recv: Receive a PXP message. - */ - int (*recv)(struct device *dev, void *buffer, size_t size, - unsigned long timeout_ms); - /** - * @gsc_command: Send a GSC command. - */ - ssize_t (*gsc_command)(struct device *dev, u8 client_id, u32 fence_id, - struct scatterlist *sg_in, size_t total_in_len, - struct scatterlist *sg_out); - -}; - -/** - * struct i915_pxp_component - Used for communication between i915 and TEE - * drivers for the PXP services - */ -struct i915_pxp_component { - /** - * @tee_dev: device that provide the PXP service from TEE Bus. - */ - struct device *tee_dev; - - /** - * @ops: Ops implemented by TEE driver, used by i915 driver. - */ - const struct i915_pxp_component_ops *ops; - - /** - * @mutex: To protect the above members. - */ - struct mutex mutex; -}; - -#endif /* _I915_TEE_PXP_INTERFACE_H_ */ diff --git a/include/drm/intel/i915_pxp_tee_interface.h b/include/drm/intel/i915_pxp_tee_interface.h new file mode 100644 index 000000000000..a532d32f58f3 --- /dev/null +++ b/include/drm/intel/i915_pxp_tee_interface.h @@ -0,0 +1,62 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2020 Intel Corporation + */ + +#ifndef _I915_PXP_TEE_INTERFACE_H_ +#define _I915_PXP_TEE_INTERFACE_H_ + +#include +#include +struct scatterlist; + +/** + * struct i915_pxp_component_ops - ops for PXP services. + */ +struct i915_pxp_component_ops { + /** + * @owner: Module providing the ops. + */ + struct module *owner; + + /** + * @send: Send a PXP message. + */ + int (*send)(struct device *dev, const void *message, size_t size, + unsigned long timeout_ms); + /** + * @recv: Receive a PXP message. + */ + int (*recv)(struct device *dev, void *buffer, size_t size, + unsigned long timeout_ms); + /** + * @gsc_command: Send a GSC command. + */ + ssize_t (*gsc_command)(struct device *dev, u8 client_id, u32 fence_id, + struct scatterlist *sg_in, size_t total_in_len, + struct scatterlist *sg_out); + +}; + +/** + * struct i915_pxp_component - Used for communication between i915 and TEE + * drivers for the PXP services + */ +struct i915_pxp_component { + /** + * @tee_dev: device that provide the PXP service from TEE Bus. + */ + struct device *tee_dev; + + /** + * @ops: Ops implemented by TEE driver, used by i915 driver. + */ + const struct i915_pxp_component_ops *ops; + + /** + * @mutex: To protect the above members. + */ + struct mutex mutex; +}; + +#endif /* _I915_TEE_PXP_INTERFACE_H_ */ -- cgit From aef8dc4398c6c6fde0d4c746e8343a33c683cc33 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 16:19:08 +0300 Subject: drm: move i915_pciids.h under include/drm/intel Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter Cc: Dave Airlie Cc: Lucas De Marchi Cc: Bjorn Helgaas Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/a19cebc0f03588b9627dcaaebe69a9fef28c27f0.1717075103.git.jani.nikula@intel.com --- arch/x86/kernel/early-quirks.c | 2 +- .../gpu/drm/i915/display/intel_display_device.c | 2 +- drivers/gpu/drm/i915/i915_pci.c | 2 +- drivers/gpu/drm/i915/intel_device_info.c | 2 +- include/drm/i915_pciids.h | 792 --------------------- include/drm/intel/i915_pciids.h | 792 +++++++++++++++++++++ 6 files changed, 796 insertions(+), 796 deletions(-) delete mode 100644 include/drm/i915_pciids.h create mode 100644 include/drm/intel/i915_pciids.h diff --git a/arch/x86/kernel/early-quirks.c b/arch/x86/kernel/early-quirks.c index ec1a7943c228..29d1f9104e94 100644 --- a/arch/x86/kernel/early-quirks.c +++ b/arch/x86/kernel/early-quirks.c @@ -18,7 +18,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index b8b56ace7583..b35422da7f6c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -3,7 +3,7 @@ * Copyright © 2023 Intel Corporation */ -#include +#include #include #include diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 2e33b56e1cc6..7058efa75324 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -24,7 +24,7 @@ #include #include -#include +#include #include "display/intel_display.h" #include "display/intel_display_driver.h" diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 862f4b705227..d26de37719a7 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -25,7 +25,7 @@ #include #include -#include +#include #include "gt/intel_gt_regs.h" #include "i915_drv.h" diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h deleted file mode 100644 index 7ae7ee11ef38..000000000000 --- a/include/drm/i915_pciids.h +++ /dev/null @@ -1,792 +0,0 @@ -/* - * Copyright 2013 Intel Corporation - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef _I915_PCIIDS_H -#define _I915_PCIIDS_H - -/* - * A pci_device_id struct { - * __u32 vendor, device; - * __u32 subvendor, subdevice; - * __u32 class, class_mask; - * kernel_ulong_t driver_data; - * }; - * Don't use C99 here because "class" is reserved and we want to - * give userspace flexibility. - */ -#define INTEL_VGA_DEVICE(id, info) { \ - 0x8086, id, \ - ~0, ~0, \ - 0x030000, 0xff0000, \ - (unsigned long) info } - -#define INTEL_QUANTA_VGA_DEVICE(info) { \ - 0x8086, 0x16a, \ - 0x152d, 0x8990, \ - 0x030000, 0xff0000, \ - (unsigned long) info } - -#define INTEL_I810_IDS(MACRO__, ...) \ - MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \ - MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \ - MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */ - -#define INTEL_I815_IDS(MACRO__, ...) \ - MACRO__(0x1132, ## __VA_ARGS__) /* I815*/ - -#define INTEL_I830_IDS(MACRO__, ...) \ - MACRO__(0x3577, ## __VA_ARGS__) - -#define INTEL_I845G_IDS(MACRO__, ...) \ - MACRO__(0x2562, ## __VA_ARGS__) - -#define INTEL_I85X_IDS(MACRO__, ...) \ - MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \ - MACRO__(0x358e, ## __VA_ARGS__) - -#define INTEL_I865G_IDS(MACRO__, ...) \ - MACRO__(0x2572, ## __VA_ARGS__) /* I865_G */ - -#define INTEL_I915G_IDS(MACRO__, ...) \ - MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \ - MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */ - -#define INTEL_I915GM_IDS(MACRO__, ...) \ - MACRO__(0x2592, ## __VA_ARGS__) /* I915_GM */ - -#define INTEL_I945G_IDS(MACRO__, ...) \ - MACRO__(0x2772, ## __VA_ARGS__) /* I945_G */ - -#define INTEL_I945GM_IDS(MACRO__, ...) \ - MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \ - MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */ - -#define INTEL_I965G_IDS(MACRO__, ...) \ - MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \ - MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \ - MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \ - MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */ - -#define INTEL_G33_IDS(MACRO__, ...) \ - MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \ - MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \ - MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */ - -#define INTEL_I965GM_IDS(MACRO__, ...) \ - MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \ - MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */ - -#define INTEL_GM45_IDS(MACRO__, ...) \ - MACRO__(0x2a42, ## __VA_ARGS__) /* GM45_G */ - -#define INTEL_G45_IDS(MACRO__, ...) \ - MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \ - MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \ - MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \ - MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \ - MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \ - MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */ - -#define INTEL_PNV_G_IDS(MACRO__, ...) \ - MACRO__(0xa001, ## __VA_ARGS__) - -#define INTEL_PNV_M_IDS(MACRO__, ...) \ - MACRO__(0xa011, ## __VA_ARGS__) - -#define INTEL_PNV_IDS(MACRO__, ...) \ - INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_ILK_D_IDS(MACRO__, ...) \ - MACRO__(0x0042, ## __VA_ARGS__) - -#define INTEL_ILK_M_IDS(MACRO__, ...) \ - MACRO__(0x0046, ## __VA_ARGS__) - -#define INTEL_ILK_IDS(MACRO__, ...) \ - INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \ - MACRO__(0x0102, ## __VA_ARGS__), \ - MACRO__(0x010A, ## __VA_ARGS__) - -#define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \ - MACRO__(0x0112, ## __VA_ARGS__), \ - MACRO__(0x0122, ## __VA_ARGS__) - -#define INTEL_SNB_D_IDS(MACRO__, ...) \ - INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_SNB_M_GT1_IDS(MACRO__, ...) \ - MACRO__(0x0106, ## __VA_ARGS__) - -#define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \ - MACRO__(0x0116, ## __VA_ARGS__), \ - MACRO__(0x0126, ## __VA_ARGS__) - -#define INTEL_SNB_M_IDS(MACRO__, ...) \ - INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_SNB_IDS(MACRO__, ...) \ - INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_IVB_M_GT1_IDS(MACRO__, ...) \ - MACRO__(0x0156, ## __VA_ARGS__) /* GT1 mobile */ - -#define INTEL_IVB_M_GT2_IDS(MACRO__, ...) \ - MACRO__(0x0166, ## __VA_ARGS__) /* GT2 mobile */ - -#define INTEL_IVB_M_IDS(MACRO__, ...) \ - INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \ - MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \ - MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */ - -#define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \ - MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \ - MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */ - -#define INTEL_IVB_D_IDS(MACRO__, ...) \ - INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_IVB_IDS(MACRO__, ...) \ - INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_IVB_Q_IDS(MACRO__, ...) \ - INTEL_QUANTA_VGA_DEVICE(__VA_ARGS__) /* Quanta transcode */ - -#define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \ - MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \ - MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \ - MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \ - MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */ - -#define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) \ - MACRO__(0x0A0E, ## __VA_ARGS__) /* ULX GT1 mobile */ - -#define INTEL_HSW_GT1_IDS(MACRO__, ...) \ - INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \ - MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \ - MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \ - MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \ - MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \ - MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \ - MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \ - MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \ - MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \ - MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \ - MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \ - MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \ - MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \ - MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \ - MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */ - -#define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \ - MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \ - MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \ - MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \ - MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \ - -#define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) \ - MACRO__(0x0A1E, ## __VA_ARGS__) /* ULX GT2 mobile */ \ - -#define INTEL_HSW_GT2_IDS(MACRO__, ...) \ - INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \ - MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \ - MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \ - MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \ - MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \ - MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \ - MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \ - MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \ - MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \ - MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \ - MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \ - MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \ - MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \ - MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \ - MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */ - -#define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \ - MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \ - MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \ - MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \ - MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \ - MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */ - -#define INTEL_HSW_GT3_IDS(MACRO__, ...) \ - INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \ - MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \ - MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \ - MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \ - MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \ - MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \ - MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \ - MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \ - MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \ - MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \ - MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \ - MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \ - MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \ - MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \ - MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */ - -#define INTEL_HSW_IDS(MACRO__, ...) \ - INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_VLV_IDS(MACRO__, ...) \ - MACRO__(0x0f30, ## __VA_ARGS__), \ - MACRO__(0x0f31, ## __VA_ARGS__), \ - MACRO__(0x0f32, ## __VA_ARGS__), \ - MACRO__(0x0f33, ## __VA_ARGS__) - -#define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \ - MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \ - MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */ - -#define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) \ - MACRO__(0x160E, ## __VA_ARGS__) /* GT1 ULX */ - -#define INTEL_BDW_GT1_IDS(MACRO__, ...) \ - INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \ - MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \ - MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */ - -#define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \ - MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \ - MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */ - -#define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) \ - MACRO__(0x161E, ## __VA_ARGS__) /* GT2 ULX */ - -#define INTEL_BDW_GT2_IDS(MACRO__, ...) \ - INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \ - MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \ - MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */ - -#define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \ - MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \ - MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \ - -#define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) \ - MACRO__(0x162E, ## __VA_ARGS__) /* ULX */ - -#define INTEL_BDW_GT3_IDS(MACRO__, ...) \ - INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \ - MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \ - MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */ - -#define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \ - MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \ - MACRO__(0x163B, ## __VA_ARGS__) /* Iris */ - -#define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) \ - MACRO__(0x163E, ## __VA_ARGS__) /* ULX */ - -#define INTEL_BDW_RSVD_IDS(MACRO__, ...) \ - INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \ - MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \ - MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */ - -#define INTEL_BDW_IDS(MACRO__, ...) \ - INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_CHV_IDS(MACRO__, ...) \ - MACRO__(0x22b0, ## __VA_ARGS__), \ - MACRO__(0x22b1, ## __VA_ARGS__), \ - MACRO__(0x22b2, ## __VA_ARGS__), \ - MACRO__(0x22b3, ## __VA_ARGS__) - -#define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \ - MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \ - MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */ - -#define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \ - MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \ - MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */ - -#define INTEL_SKL_GT1_IDS(MACRO__, ...) \ - INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \ - MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \ - MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \ - MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */ - -#define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \ - MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \ - MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */ - -#define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) \ - MACRO__(0x191E, ## __VA_ARGS__) /* ULX GT2 */ - -#define INTEL_SKL_GT2_IDS(MACRO__, ...) \ - INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \ - MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \ - MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \ - MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */ - -#define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \ - MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \ - MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \ - MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */ - -#define INTEL_SKL_GT3_IDS(MACRO__, ...) \ - INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \ - MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \ - MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */ - -#define INTEL_SKL_GT4_IDS(MACRO__, ...) \ - MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \ - MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \ - MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \ - MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */ - -#define INTEL_SKL_IDS(MACRO__, ...) \ - INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_BXT_IDS(MACRO__, ...) \ - MACRO__(0x0A84, ## __VA_ARGS__), \ - MACRO__(0x1A84, ## __VA_ARGS__), \ - MACRO__(0x1A85, ## __VA_ARGS__), \ - MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \ - MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */ - -#define INTEL_GLK_IDS(MACRO__, ...) \ - MACRO__(0x3184, ## __VA_ARGS__), \ - MACRO__(0x3185, ## __VA_ARGS__) - -#define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \ - MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \ - MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */ - -#define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \ - MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \ - MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */ - -#define INTEL_KBL_GT1_IDS(MACRO__, ...) \ - INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \ - MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \ - MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \ - MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */ - -#define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \ - MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \ - MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */ - -#define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) \ - MACRO__(0x591E, ## __VA_ARGS__) /* ULX GT2 */ - -#define INTEL_KBL_GT2_IDS(MACRO__, ...) \ - INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \ - MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \ - MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \ - MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \ - MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */ - -#define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) \ - MACRO__(0x5926, ## __VA_ARGS__) /* ULT GT3 */ - -#define INTEL_KBL_GT3_IDS(MACRO__, ...) \ - INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \ - MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */ - -#define INTEL_KBL_GT4_IDS(MACRO__, ...) \ - MACRO__(0x593B, ## __VA_ARGS__) /* Halo GT4 */ - -/* AML/KBL Y GT2 */ -#define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \ - MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \ - MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */ - -/* AML/CFL Y GT2 */ -#define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) \ - MACRO__(0x87CA, ## __VA_ARGS__) - -/* CML GT1 */ -#define INTEL_CML_GT1_IDS(MACRO__, ...) \ - MACRO__(0x9BA2, ## __VA_ARGS__), \ - MACRO__(0x9BA4, ## __VA_ARGS__), \ - MACRO__(0x9BA5, ## __VA_ARGS__), \ - MACRO__(0x9BA8, ## __VA_ARGS__) - -#define INTEL_CML_U_GT1_IDS(MACRO__, ...) \ - MACRO__(0x9B21, ## __VA_ARGS__), \ - MACRO__(0x9BAA, ## __VA_ARGS__), \ - MACRO__(0x9BAC, ## __VA_ARGS__) - -/* CML GT2 */ -#define INTEL_CML_GT2_IDS(MACRO__, ...) \ - MACRO__(0x9BC2, ## __VA_ARGS__), \ - MACRO__(0x9BC4, ## __VA_ARGS__), \ - MACRO__(0x9BC5, ## __VA_ARGS__), \ - MACRO__(0x9BC6, ## __VA_ARGS__), \ - MACRO__(0x9BC8, ## __VA_ARGS__), \ - MACRO__(0x9BE6, ## __VA_ARGS__), \ - MACRO__(0x9BF6, ## __VA_ARGS__) - -#define INTEL_CML_U_GT2_IDS(MACRO__, ...) \ - MACRO__(0x9B41, ## __VA_ARGS__), \ - MACRO__(0x9BCA, ## __VA_ARGS__), \ - MACRO__(0x9BCC, ## __VA_ARGS__) - -#define INTEL_CML_IDS(MACRO__, ...) \ - INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_KBL_IDS(MACRO__, ...) \ - INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__) - -/* CFL S */ -#define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \ - MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \ - MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \ - MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */ - -#define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \ - MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \ - MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \ - MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \ - MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \ - MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */ - -/* CFL H */ -#define INTEL_CFL_H_GT1_IDS(MACRO__, ...) \ - MACRO__(0x3E9C, ## __VA_ARGS__) - -#define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \ - MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \ - MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */ - -/* CFL U GT2 */ -#define INTEL_CFL_U_GT2_IDS(MACRO__, ...) \ - MACRO__(0x3EA9, ## __VA_ARGS__) - -/* CFL U GT3 */ -#define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \ - MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \ - MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \ - MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \ - MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */ - -#define INTEL_CFL_IDS(MACRO__, ...) \ - INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__) - -/* WHL/CFL U GT1 */ -#define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \ - MACRO__(0x3EA1, ## __VA_ARGS__), \ - MACRO__(0x3EA4, ## __VA_ARGS__) - -/* WHL/CFL U GT2 */ -#define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \ - MACRO__(0x3EA0, ## __VA_ARGS__), \ - MACRO__(0x3EA3, ## __VA_ARGS__) - -/* WHL/CFL U GT3 */ -#define INTEL_WHL_U_GT3_IDS(MACRO__, ...) \ - MACRO__(0x3EA2, ## __VA_ARGS__) - -#define INTEL_WHL_IDS(MACRO__, ...) \ - INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__) - -/* CNL */ -#define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \ - MACRO__(0x5A44, ## __VA_ARGS__), \ - MACRO__(0x5A4C, ## __VA_ARGS__), \ - MACRO__(0x5A54, ## __VA_ARGS__), \ - MACRO__(0x5A5C, ## __VA_ARGS__) - -#define INTEL_CNL_IDS(MACRO__, ...) \ - INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x5A40, ## __VA_ARGS__), \ - MACRO__(0x5A41, ## __VA_ARGS__), \ - MACRO__(0x5A42, ## __VA_ARGS__), \ - MACRO__(0x5A49, ## __VA_ARGS__), \ - MACRO__(0x5A4A, ## __VA_ARGS__), \ - MACRO__(0x5A50, ## __VA_ARGS__), \ - MACRO__(0x5A51, ## __VA_ARGS__), \ - MACRO__(0x5A52, ## __VA_ARGS__), \ - MACRO__(0x5A59, ## __VA_ARGS__), \ - MACRO__(0x5A5A, ## __VA_ARGS__) - -/* ICL */ -#define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \ - MACRO__(0x8A50, ## __VA_ARGS__), \ - MACRO__(0x8A52, ## __VA_ARGS__), \ - MACRO__(0x8A53, ## __VA_ARGS__), \ - MACRO__(0x8A54, ## __VA_ARGS__), \ - MACRO__(0x8A56, ## __VA_ARGS__), \ - MACRO__(0x8A57, ## __VA_ARGS__), \ - MACRO__(0x8A58, ## __VA_ARGS__), \ - MACRO__(0x8A59, ## __VA_ARGS__), \ - MACRO__(0x8A5A, ## __VA_ARGS__), \ - MACRO__(0x8A5B, ## __VA_ARGS__), \ - MACRO__(0x8A5C, ## __VA_ARGS__), \ - MACRO__(0x8A70, ## __VA_ARGS__), \ - MACRO__(0x8A71, ## __VA_ARGS__) - -#define INTEL_ICL_IDS(MACRO__, ...) \ - INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0x8A51, ## __VA_ARGS__), \ - MACRO__(0x8A5D, ## __VA_ARGS__) - -/* EHL */ -#define INTEL_EHL_IDS(MACRO__, ...) \ - MACRO__(0x4541, ## __VA_ARGS__), \ - MACRO__(0x4551, ## __VA_ARGS__), \ - MACRO__(0x4555, ## __VA_ARGS__), \ - MACRO__(0x4557, ## __VA_ARGS__), \ - MACRO__(0x4570, ## __VA_ARGS__), \ - MACRO__(0x4571, ## __VA_ARGS__) - -/* JSL */ -#define INTEL_JSL_IDS(MACRO__, ...) \ - MACRO__(0x4E51, ## __VA_ARGS__), \ - MACRO__(0x4E55, ## __VA_ARGS__), \ - MACRO__(0x4E57, ## __VA_ARGS__), \ - MACRO__(0x4E61, ## __VA_ARGS__), \ - MACRO__(0x4E71, ## __VA_ARGS__) - -/* TGL */ -#define INTEL_TGL_GT1_IDS(MACRO__, ...) \ - MACRO__(0x9A60, ## __VA_ARGS__), \ - MACRO__(0x9A68, ## __VA_ARGS__), \ - MACRO__(0x9A70, ## __VA_ARGS__) - -#define INTEL_TGL_GT2_IDS(MACRO__, ...) \ - MACRO__(0x9A40, ## __VA_ARGS__), \ - MACRO__(0x9A49, ## __VA_ARGS__), \ - MACRO__(0x9A59, ## __VA_ARGS__), \ - MACRO__(0x9A78, ## __VA_ARGS__), \ - MACRO__(0x9AC0, ## __VA_ARGS__), \ - MACRO__(0x9AC9, ## __VA_ARGS__), \ - MACRO__(0x9AD9, ## __VA_ARGS__), \ - MACRO__(0x9AF8, ## __VA_ARGS__) - -#define INTEL_TGL_IDS(MACRO__, ...) \ - INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__) - -/* RKL */ -#define INTEL_RKL_IDS(MACRO__, ...) \ - MACRO__(0x4C80, ## __VA_ARGS__), \ - MACRO__(0x4C8A, ## __VA_ARGS__), \ - MACRO__(0x4C8B, ## __VA_ARGS__), \ - MACRO__(0x4C8C, ## __VA_ARGS__), \ - MACRO__(0x4C90, ## __VA_ARGS__), \ - MACRO__(0x4C9A, ## __VA_ARGS__) - -/* DG1 */ -#define INTEL_DG1_IDS(MACRO__, ...) \ - MACRO__(0x4905, ## __VA_ARGS__), \ - MACRO__(0x4906, ## __VA_ARGS__), \ - MACRO__(0x4907, ## __VA_ARGS__), \ - MACRO__(0x4908, ## __VA_ARGS__), \ - MACRO__(0x4909, ## __VA_ARGS__) - -/* ADL-S */ -#define INTEL_ADLS_IDS(MACRO__, ...) \ - MACRO__(0x4680, ## __VA_ARGS__), \ - MACRO__(0x4682, ## __VA_ARGS__), \ - MACRO__(0x4688, ## __VA_ARGS__), \ - MACRO__(0x468A, ## __VA_ARGS__), \ - MACRO__(0x468B, ## __VA_ARGS__), \ - MACRO__(0x4690, ## __VA_ARGS__), \ - MACRO__(0x4692, ## __VA_ARGS__), \ - MACRO__(0x4693, ## __VA_ARGS__) - -/* ADL-P */ -#define INTEL_ADLP_IDS(MACRO__, ...) \ - MACRO__(0x46A0, ## __VA_ARGS__), \ - MACRO__(0x46A1, ## __VA_ARGS__), \ - MACRO__(0x46A2, ## __VA_ARGS__), \ - MACRO__(0x46A3, ## __VA_ARGS__), \ - MACRO__(0x46A6, ## __VA_ARGS__), \ - MACRO__(0x46A8, ## __VA_ARGS__), \ - MACRO__(0x46AA, ## __VA_ARGS__), \ - MACRO__(0x462A, ## __VA_ARGS__), \ - MACRO__(0x4626, ## __VA_ARGS__), \ - MACRO__(0x4628, ## __VA_ARGS__), \ - MACRO__(0x46B0, ## __VA_ARGS__), \ - MACRO__(0x46B1, ## __VA_ARGS__), \ - MACRO__(0x46B2, ## __VA_ARGS__), \ - MACRO__(0x46B3, ## __VA_ARGS__), \ - MACRO__(0x46C0, ## __VA_ARGS__), \ - MACRO__(0x46C1, ## __VA_ARGS__), \ - MACRO__(0x46C2, ## __VA_ARGS__), \ - MACRO__(0x46C3, ## __VA_ARGS__) - -/* ADL-N */ -#define INTEL_ADLN_IDS(MACRO__, ...) \ - MACRO__(0x46D0, ## __VA_ARGS__), \ - MACRO__(0x46D1, ## __VA_ARGS__), \ - MACRO__(0x46D2, ## __VA_ARGS__), \ - MACRO__(0x46D3, ## __VA_ARGS__), \ - MACRO__(0x46D4, ## __VA_ARGS__) - -/* RPL-S */ -#define INTEL_RPLS_IDS(MACRO__, ...) \ - MACRO__(0xA780, ## __VA_ARGS__), \ - MACRO__(0xA781, ## __VA_ARGS__), \ - MACRO__(0xA782, ## __VA_ARGS__), \ - MACRO__(0xA783, ## __VA_ARGS__), \ - MACRO__(0xA788, ## __VA_ARGS__), \ - MACRO__(0xA789, ## __VA_ARGS__), \ - MACRO__(0xA78A, ## __VA_ARGS__), \ - MACRO__(0xA78B, ## __VA_ARGS__) - -/* RPL-U */ -#define INTEL_RPLU_IDS(MACRO__, ...) \ - MACRO__(0xA721, ## __VA_ARGS__), \ - MACRO__(0xA7A1, ## __VA_ARGS__), \ - MACRO__(0xA7A9, ## __VA_ARGS__), \ - MACRO__(0xA7AC, ## __VA_ARGS__), \ - MACRO__(0xA7AD, ## __VA_ARGS__) - -/* RPL-P */ -#define INTEL_RPLP_IDS(MACRO__, ...) \ - MACRO__(0xA720, ## __VA_ARGS__), \ - MACRO__(0xA7A0, ## __VA_ARGS__), \ - MACRO__(0xA7A8, ## __VA_ARGS__), \ - MACRO__(0xA7AA, ## __VA_ARGS__), \ - MACRO__(0xA7AB, ## __VA_ARGS__) - -/* DG2 */ -#define INTEL_DG2_G10_IDS(MACRO__, ...) \ - MACRO__(0x5690, ## __VA_ARGS__), \ - MACRO__(0x5691, ## __VA_ARGS__), \ - MACRO__(0x5692, ## __VA_ARGS__), \ - MACRO__(0x56A0, ## __VA_ARGS__), \ - MACRO__(0x56A1, ## __VA_ARGS__), \ - MACRO__(0x56A2, ## __VA_ARGS__), \ - MACRO__(0x56BE, ## __VA_ARGS__), \ - MACRO__(0x56BF, ## __VA_ARGS__) - -#define INTEL_DG2_G11_IDS(MACRO__, ...) \ - MACRO__(0x5693, ## __VA_ARGS__), \ - MACRO__(0x5694, ## __VA_ARGS__), \ - MACRO__(0x5695, ## __VA_ARGS__), \ - MACRO__(0x56A5, ## __VA_ARGS__), \ - MACRO__(0x56A6, ## __VA_ARGS__), \ - MACRO__(0x56B0, ## __VA_ARGS__), \ - MACRO__(0x56B1, ## __VA_ARGS__), \ - MACRO__(0x56BA, ## __VA_ARGS__), \ - MACRO__(0x56BB, ## __VA_ARGS__), \ - MACRO__(0x56BC, ## __VA_ARGS__), \ - MACRO__(0x56BD, ## __VA_ARGS__) - -#define INTEL_DG2_G12_IDS(MACRO__, ...) \ - MACRO__(0x5696, ## __VA_ARGS__), \ - MACRO__(0x5697, ## __VA_ARGS__), \ - MACRO__(0x56A3, ## __VA_ARGS__), \ - MACRO__(0x56A4, ## __VA_ARGS__), \ - MACRO__(0x56B2, ## __VA_ARGS__), \ - MACRO__(0x56B3, ## __VA_ARGS__) - -#define INTEL_DG2_IDS(MACRO__, ...) \ - INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__) - -#define INTEL_ATS_M150_IDS(MACRO__, ...) \ - MACRO__(0x56C0, ## __VA_ARGS__), \ - MACRO__(0x56C2, ## __VA_ARGS__) - -#define INTEL_ATS_M75_IDS(MACRO__, ...) \ - MACRO__(0x56C1, ## __VA_ARGS__) - -#define INTEL_ATS_M_IDS(MACRO__, ...) \ - INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \ - INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) - -/* MTL */ -#define INTEL_MTL_IDS(MACRO__, ...) \ - MACRO__(0x7D40, ## __VA_ARGS__), \ - MACRO__(0x7D41, ## __VA_ARGS__), \ - MACRO__(0x7D45, ## __VA_ARGS__), \ - MACRO__(0x7D51, ## __VA_ARGS__), \ - MACRO__(0x7D55, ## __VA_ARGS__), \ - MACRO__(0x7D60, ## __VA_ARGS__), \ - MACRO__(0x7D67, ## __VA_ARGS__), \ - MACRO__(0x7DD1, ## __VA_ARGS__), \ - MACRO__(0x7DD5, ## __VA_ARGS__) - -/* LNL */ -#define INTEL_LNL_IDS(MACRO__, ...) \ - MACRO__(0x6420, ## __VA_ARGS__), \ - MACRO__(0x64A0, ## __VA_ARGS__), \ - MACRO__(0x64B0, ## __VA_ARGS__) - -#endif /* _I915_PCIIDS_H */ diff --git a/include/drm/intel/i915_pciids.h b/include/drm/intel/i915_pciids.h new file mode 100644 index 000000000000..7ae7ee11ef38 --- /dev/null +++ b/include/drm/intel/i915_pciids.h @@ -0,0 +1,792 @@ +/* + * Copyright 2013 Intel Corporation + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef _I915_PCIIDS_H +#define _I915_PCIIDS_H + +/* + * A pci_device_id struct { + * __u32 vendor, device; + * __u32 subvendor, subdevice; + * __u32 class, class_mask; + * kernel_ulong_t driver_data; + * }; + * Don't use C99 here because "class" is reserved and we want to + * give userspace flexibility. + */ +#define INTEL_VGA_DEVICE(id, info) { \ + 0x8086, id, \ + ~0, ~0, \ + 0x030000, 0xff0000, \ + (unsigned long) info } + +#define INTEL_QUANTA_VGA_DEVICE(info) { \ + 0x8086, 0x16a, \ + 0x152d, 0x8990, \ + 0x030000, 0xff0000, \ + (unsigned long) info } + +#define INTEL_I810_IDS(MACRO__, ...) \ + MACRO__(0x7121, ## __VA_ARGS__), /* I810 */ \ + MACRO__(0x7123, ## __VA_ARGS__), /* I810_DC100 */ \ + MACRO__(0x7125, ## __VA_ARGS__) /* I810_E */ + +#define INTEL_I815_IDS(MACRO__, ...) \ + MACRO__(0x1132, ## __VA_ARGS__) /* I815*/ + +#define INTEL_I830_IDS(MACRO__, ...) \ + MACRO__(0x3577, ## __VA_ARGS__) + +#define INTEL_I845G_IDS(MACRO__, ...) \ + MACRO__(0x2562, ## __VA_ARGS__) + +#define INTEL_I85X_IDS(MACRO__, ...) \ + MACRO__(0x3582, ## __VA_ARGS__), /* I855_GM */ \ + MACRO__(0x358e, ## __VA_ARGS__) + +#define INTEL_I865G_IDS(MACRO__, ...) \ + MACRO__(0x2572, ## __VA_ARGS__) /* I865_G */ + +#define INTEL_I915G_IDS(MACRO__, ...) \ + MACRO__(0x2582, ## __VA_ARGS__), /* I915_G */ \ + MACRO__(0x258a, ## __VA_ARGS__) /* E7221_G */ + +#define INTEL_I915GM_IDS(MACRO__, ...) \ + MACRO__(0x2592, ## __VA_ARGS__) /* I915_GM */ + +#define INTEL_I945G_IDS(MACRO__, ...) \ + MACRO__(0x2772, ## __VA_ARGS__) /* I945_G */ + +#define INTEL_I945GM_IDS(MACRO__, ...) \ + MACRO__(0x27a2, ## __VA_ARGS__), /* I945_GM */ \ + MACRO__(0x27ae, ## __VA_ARGS__) /* I945_GME */ + +#define INTEL_I965G_IDS(MACRO__, ...) \ + MACRO__(0x2972, ## __VA_ARGS__), /* I946_GZ */ \ + MACRO__(0x2982, ## __VA_ARGS__), /* G35_G */ \ + MACRO__(0x2992, ## __VA_ARGS__), /* I965_Q */ \ + MACRO__(0x29a2, ## __VA_ARGS__) /* I965_G */ + +#define INTEL_G33_IDS(MACRO__, ...) \ + MACRO__(0x29b2, ## __VA_ARGS__), /* Q35_G */ \ + MACRO__(0x29c2, ## __VA_ARGS__), /* G33_G */ \ + MACRO__(0x29d2, ## __VA_ARGS__) /* Q33_G */ + +#define INTEL_I965GM_IDS(MACRO__, ...) \ + MACRO__(0x2a02, ## __VA_ARGS__), /* I965_GM */ \ + MACRO__(0x2a12, ## __VA_ARGS__) /* I965_GME */ + +#define INTEL_GM45_IDS(MACRO__, ...) \ + MACRO__(0x2a42, ## __VA_ARGS__) /* GM45_G */ + +#define INTEL_G45_IDS(MACRO__, ...) \ + MACRO__(0x2e02, ## __VA_ARGS__), /* IGD_E_G */ \ + MACRO__(0x2e12, ## __VA_ARGS__), /* Q45_G */ \ + MACRO__(0x2e22, ## __VA_ARGS__), /* G45_G */ \ + MACRO__(0x2e32, ## __VA_ARGS__), /* G41_G */ \ + MACRO__(0x2e42, ## __VA_ARGS__), /* B43_G */ \ + MACRO__(0x2e92, ## __VA_ARGS__) /* B43_G.1 */ + +#define INTEL_PNV_G_IDS(MACRO__, ...) \ + MACRO__(0xa001, ## __VA_ARGS__) + +#define INTEL_PNV_M_IDS(MACRO__, ...) \ + MACRO__(0xa011, ## __VA_ARGS__) + +#define INTEL_PNV_IDS(MACRO__, ...) \ + INTEL_PNV_G_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_PNV_M_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_ILK_D_IDS(MACRO__, ...) \ + MACRO__(0x0042, ## __VA_ARGS__) + +#define INTEL_ILK_M_IDS(MACRO__, ...) \ + MACRO__(0x0046, ## __VA_ARGS__) + +#define INTEL_ILK_IDS(MACRO__, ...) \ + INTEL_ILK_D_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_ILK_M_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_SNB_D_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0102, ## __VA_ARGS__), \ + MACRO__(0x010A, ## __VA_ARGS__) + +#define INTEL_SNB_D_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0112, ## __VA_ARGS__), \ + MACRO__(0x0122, ## __VA_ARGS__) + +#define INTEL_SNB_D_IDS(MACRO__, ...) \ + INTEL_SNB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SNB_D_GT2_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_SNB_M_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0106, ## __VA_ARGS__) + +#define INTEL_SNB_M_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0116, ## __VA_ARGS__), \ + MACRO__(0x0126, ## __VA_ARGS__) + +#define INTEL_SNB_M_IDS(MACRO__, ...) \ + INTEL_SNB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SNB_M_GT2_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_SNB_IDS(MACRO__, ...) \ + INTEL_SNB_D_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SNB_M_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_IVB_M_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0156, ## __VA_ARGS__) /* GT1 mobile */ + +#define INTEL_IVB_M_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0166, ## __VA_ARGS__) /* GT2 mobile */ + +#define INTEL_IVB_M_IDS(MACRO__, ...) \ + INTEL_IVB_M_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_IVB_M_GT2_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_IVB_D_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0152, ## __VA_ARGS__), /* GT1 desktop */ \ + MACRO__(0x015a, ## __VA_ARGS__) /* GT1 server */ + +#define INTEL_IVB_D_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0162, ## __VA_ARGS__), /* GT2 desktop */ \ + MACRO__(0x016a, ## __VA_ARGS__) /* GT2 server */ + +#define INTEL_IVB_D_IDS(MACRO__, ...) \ + INTEL_IVB_D_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_IVB_D_GT2_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_IVB_IDS(MACRO__, ...) \ + INTEL_IVB_M_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_IVB_D_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_IVB_Q_IDS(MACRO__, ...) \ + INTEL_QUANTA_VGA_DEVICE(__VA_ARGS__) /* Quanta transcode */ + +#define INTEL_HSW_ULT_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0A02, ## __VA_ARGS__), /* ULT GT1 desktop */ \ + MACRO__(0x0A06, ## __VA_ARGS__), /* ULT GT1 mobile */ \ + MACRO__(0x0A0A, ## __VA_ARGS__), /* ULT GT1 server */ \ + MACRO__(0x0A0B, ## __VA_ARGS__) /* ULT GT1 reserved */ + +#define INTEL_HSW_ULX_GT1_IDS(MACRO__, ...) \ + MACRO__(0x0A0E, ## __VA_ARGS__) /* ULX GT1 mobile */ + +#define INTEL_HSW_GT1_IDS(MACRO__, ...) \ + INTEL_HSW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_HSW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x0402, ## __VA_ARGS__), /* GT1 desktop */ \ + MACRO__(0x0406, ## __VA_ARGS__), /* GT1 mobile */ \ + MACRO__(0x040A, ## __VA_ARGS__), /* GT1 server */ \ + MACRO__(0x040B, ## __VA_ARGS__), /* GT1 reserved */ \ + MACRO__(0x040E, ## __VA_ARGS__), /* GT1 reserved */ \ + MACRO__(0x0C02, ## __VA_ARGS__), /* SDV GT1 desktop */ \ + MACRO__(0x0C06, ## __VA_ARGS__), /* SDV GT1 mobile */ \ + MACRO__(0x0C0A, ## __VA_ARGS__), /* SDV GT1 server */ \ + MACRO__(0x0C0B, ## __VA_ARGS__), /* SDV GT1 reserved */ \ + MACRO__(0x0C0E, ## __VA_ARGS__), /* SDV GT1 reserved */ \ + MACRO__(0x0D02, ## __VA_ARGS__), /* CRW GT1 desktop */ \ + MACRO__(0x0D06, ## __VA_ARGS__), /* CRW GT1 mobile */ \ + MACRO__(0x0D0A, ## __VA_ARGS__), /* CRW GT1 server */ \ + MACRO__(0x0D0B, ## __VA_ARGS__), /* CRW GT1 reserved */ \ + MACRO__(0x0D0E, ## __VA_ARGS__) /* CRW GT1 reserved */ + +#define INTEL_HSW_ULT_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0A12, ## __VA_ARGS__), /* ULT GT2 desktop */ \ + MACRO__(0x0A16, ## __VA_ARGS__), /* ULT GT2 mobile */ \ + MACRO__(0x0A1A, ## __VA_ARGS__), /* ULT GT2 server */ \ + MACRO__(0x0A1B, ## __VA_ARGS__) /* ULT GT2 reserved */ \ + +#define INTEL_HSW_ULX_GT2_IDS(MACRO__, ...) \ + MACRO__(0x0A1E, ## __VA_ARGS__) /* ULX GT2 mobile */ \ + +#define INTEL_HSW_GT2_IDS(MACRO__, ...) \ + INTEL_HSW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_HSW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x0412, ## __VA_ARGS__), /* GT2 desktop */ \ + MACRO__(0x0416, ## __VA_ARGS__), /* GT2 mobile */ \ + MACRO__(0x041A, ## __VA_ARGS__), /* GT2 server */ \ + MACRO__(0x041B, ## __VA_ARGS__), /* GT2 reserved */ \ + MACRO__(0x041E, ## __VA_ARGS__), /* GT2 reserved */ \ + MACRO__(0x0C12, ## __VA_ARGS__), /* SDV GT2 desktop */ \ + MACRO__(0x0C16, ## __VA_ARGS__), /* SDV GT2 mobile */ \ + MACRO__(0x0C1A, ## __VA_ARGS__), /* SDV GT2 server */ \ + MACRO__(0x0C1B, ## __VA_ARGS__), /* SDV GT2 reserved */ \ + MACRO__(0x0C1E, ## __VA_ARGS__), /* SDV GT2 reserved */ \ + MACRO__(0x0D12, ## __VA_ARGS__), /* CRW GT2 desktop */ \ + MACRO__(0x0D16, ## __VA_ARGS__), /* CRW GT2 mobile */ \ + MACRO__(0x0D1A, ## __VA_ARGS__), /* CRW GT2 server */ \ + MACRO__(0x0D1B, ## __VA_ARGS__), /* CRW GT2 reserved */ \ + MACRO__(0x0D1E, ## __VA_ARGS__) /* CRW GT2 reserved */ + +#define INTEL_HSW_ULT_GT3_IDS(MACRO__, ...) \ + MACRO__(0x0A22, ## __VA_ARGS__), /* ULT GT3 desktop */ \ + MACRO__(0x0A26, ## __VA_ARGS__), /* ULT GT3 mobile */ \ + MACRO__(0x0A2A, ## __VA_ARGS__), /* ULT GT3 server */ \ + MACRO__(0x0A2B, ## __VA_ARGS__), /* ULT GT3 reserved */ \ + MACRO__(0x0A2E, ## __VA_ARGS__) /* ULT GT3 reserved */ + +#define INTEL_HSW_GT3_IDS(MACRO__, ...) \ + INTEL_HSW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x0422, ## __VA_ARGS__), /* GT3 desktop */ \ + MACRO__(0x0426, ## __VA_ARGS__), /* GT3 mobile */ \ + MACRO__(0x042A, ## __VA_ARGS__), /* GT3 server */ \ + MACRO__(0x042B, ## __VA_ARGS__), /* GT3 reserved */ \ + MACRO__(0x042E, ## __VA_ARGS__), /* GT3 reserved */ \ + MACRO__(0x0C22, ## __VA_ARGS__), /* SDV GT3 desktop */ \ + MACRO__(0x0C26, ## __VA_ARGS__), /* SDV GT3 mobile */ \ + MACRO__(0x0C2A, ## __VA_ARGS__), /* SDV GT3 server */ \ + MACRO__(0x0C2B, ## __VA_ARGS__), /* SDV GT3 reserved */ \ + MACRO__(0x0C2E, ## __VA_ARGS__), /* SDV GT3 reserved */ \ + MACRO__(0x0D22, ## __VA_ARGS__), /* CRW GT3 desktop */ \ + MACRO__(0x0D26, ## __VA_ARGS__), /* CRW GT3 mobile */ \ + MACRO__(0x0D2A, ## __VA_ARGS__), /* CRW GT3 server */ \ + MACRO__(0x0D2B, ## __VA_ARGS__), /* CRW GT3 reserved */ \ + MACRO__(0x0D2E, ## __VA_ARGS__) /* CRW GT3 reserved */ + +#define INTEL_HSW_IDS(MACRO__, ...) \ + INTEL_HSW_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_HSW_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_HSW_GT3_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_VLV_IDS(MACRO__, ...) \ + MACRO__(0x0f30, ## __VA_ARGS__), \ + MACRO__(0x0f31, ## __VA_ARGS__), \ + MACRO__(0x0f32, ## __VA_ARGS__), \ + MACRO__(0x0f33, ## __VA_ARGS__) + +#define INTEL_BDW_ULT_GT1_IDS(MACRO__, ...) \ + MACRO__(0x1606, ## __VA_ARGS__), /* GT1 ULT */ \ + MACRO__(0x160B, ## __VA_ARGS__) /* GT1 Iris */ + +#define INTEL_BDW_ULX_GT1_IDS(MACRO__, ...) \ + MACRO__(0x160E, ## __VA_ARGS__) /* GT1 ULX */ + +#define INTEL_BDW_GT1_IDS(MACRO__, ...) \ + INTEL_BDW_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1602, ## __VA_ARGS__), /* GT1 ULT */ \ + MACRO__(0x160A, ## __VA_ARGS__), /* GT1 Server */ \ + MACRO__(0x160D, ## __VA_ARGS__) /* GT1 Workstation */ + +#define INTEL_BDW_ULT_GT2_IDS(MACRO__, ...) \ + MACRO__(0x1616, ## __VA_ARGS__), /* GT2 ULT */ \ + MACRO__(0x161B, ## __VA_ARGS__) /* GT2 ULT */ + +#define INTEL_BDW_ULX_GT2_IDS(MACRO__, ...) \ + MACRO__(0x161E, ## __VA_ARGS__) /* GT2 ULX */ + +#define INTEL_BDW_GT2_IDS(MACRO__, ...) \ + INTEL_BDW_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1612, ## __VA_ARGS__), /* GT2 Halo */ \ + MACRO__(0x161A, ## __VA_ARGS__), /* GT2 Server */ \ + MACRO__(0x161D, ## __VA_ARGS__) /* GT2 Workstation */ + +#define INTEL_BDW_ULT_GT3_IDS(MACRO__, ...) \ + MACRO__(0x1626, ## __VA_ARGS__), /* ULT */ \ + MACRO__(0x162B, ## __VA_ARGS__) /* Iris */ \ + +#define INTEL_BDW_ULX_GT3_IDS(MACRO__, ...) \ + MACRO__(0x162E, ## __VA_ARGS__) /* ULX */ + +#define INTEL_BDW_GT3_IDS(MACRO__, ...) \ + INTEL_BDW_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_ULX_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1622, ## __VA_ARGS__), /* ULT */ \ + MACRO__(0x162A, ## __VA_ARGS__), /* Server */ \ + MACRO__(0x162D, ## __VA_ARGS__) /* Workstation */ + +#define INTEL_BDW_ULT_RSVD_IDS(MACRO__, ...) \ + MACRO__(0x1636, ## __VA_ARGS__), /* ULT */ \ + MACRO__(0x163B, ## __VA_ARGS__) /* Iris */ + +#define INTEL_BDW_ULX_RSVD_IDS(MACRO__, ...) \ + MACRO__(0x163E, ## __VA_ARGS__) /* ULX */ + +#define INTEL_BDW_RSVD_IDS(MACRO__, ...) \ + INTEL_BDW_ULT_RSVD_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_ULX_RSVD_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1632, ## __VA_ARGS__), /* ULT */ \ + MACRO__(0x163A, ## __VA_ARGS__), /* Server */ \ + MACRO__(0x163D, ## __VA_ARGS__) /* Workstation */ + +#define INTEL_BDW_IDS(MACRO__, ...) \ + INTEL_BDW_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_BDW_RSVD_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_CHV_IDS(MACRO__, ...) \ + MACRO__(0x22b0, ## __VA_ARGS__), \ + MACRO__(0x22b1, ## __VA_ARGS__), \ + MACRO__(0x22b2, ## __VA_ARGS__), \ + MACRO__(0x22b3, ## __VA_ARGS__) + +#define INTEL_SKL_ULT_GT1_IDS(MACRO__, ...) \ + MACRO__(0x1906, ## __VA_ARGS__), /* ULT GT1 */ \ + MACRO__(0x1913, ## __VA_ARGS__) /* ULT GT1.5 */ + +#define INTEL_SKL_ULX_GT1_IDS(MACRO__, ...) \ + MACRO__(0x190E, ## __VA_ARGS__), /* ULX GT1 */ \ + MACRO__(0x1915, ## __VA_ARGS__) /* ULX GT1.5 */ + +#define INTEL_SKL_GT1_IDS(MACRO__, ...) \ + INTEL_SKL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SKL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1902, ## __VA_ARGS__), /* DT GT1 */ \ + MACRO__(0x190A, ## __VA_ARGS__), /* SRV GT1 */ \ + MACRO__(0x190B, ## __VA_ARGS__), /* Halo GT1 */ \ + MACRO__(0x1917, ## __VA_ARGS__) /* DT GT1.5 */ + +#define INTEL_SKL_ULT_GT2_IDS(MACRO__, ...) \ + MACRO__(0x1916, ## __VA_ARGS__), /* ULT GT2 */ \ + MACRO__(0x1921, ## __VA_ARGS__) /* ULT GT2F */ + +#define INTEL_SKL_ULX_GT2_IDS(MACRO__, ...) \ + MACRO__(0x191E, ## __VA_ARGS__) /* ULX GT2 */ + +#define INTEL_SKL_GT2_IDS(MACRO__, ...) \ + INTEL_SKL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SKL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x1912, ## __VA_ARGS__), /* DT GT2 */ \ + MACRO__(0x191A, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x191B, ## __VA_ARGS__), /* Halo GT2 */ \ + MACRO__(0x191D, ## __VA_ARGS__) /* WKS GT2 */ + +#define INTEL_SKL_ULT_GT3_IDS(MACRO__, ...) \ + MACRO__(0x1923, ## __VA_ARGS__), /* ULT GT3 */ \ + MACRO__(0x1926, ## __VA_ARGS__), /* ULT GT3e */ \ + MACRO__(0x1927, ## __VA_ARGS__) /* ULT GT3e */ + +#define INTEL_SKL_GT3_IDS(MACRO__, ...) \ + INTEL_SKL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x192A, ## __VA_ARGS__), /* SRV GT3 */ \ + MACRO__(0x192B, ## __VA_ARGS__), /* Halo GT3e */ \ + MACRO__(0x192D, ## __VA_ARGS__) /* SRV GT3e */ + +#define INTEL_SKL_GT4_IDS(MACRO__, ...) \ + MACRO__(0x1932, ## __VA_ARGS__), /* DT GT4 */ \ + MACRO__(0x193A, ## __VA_ARGS__), /* SRV GT4e */ \ + MACRO__(0x193B, ## __VA_ARGS__), /* Halo GT4e */ \ + MACRO__(0x193D, ## __VA_ARGS__) /* WKS GT4e */ + +#define INTEL_SKL_IDS(MACRO__, ...) \ + INTEL_SKL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SKL_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SKL_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_SKL_GT4_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_BXT_IDS(MACRO__, ...) \ + MACRO__(0x0A84, ## __VA_ARGS__), \ + MACRO__(0x1A84, ## __VA_ARGS__), \ + MACRO__(0x1A85, ## __VA_ARGS__), \ + MACRO__(0x5A84, ## __VA_ARGS__), /* APL HD Graphics 505 */ \ + MACRO__(0x5A85, ## __VA_ARGS__) /* APL HD Graphics 500 */ + +#define INTEL_GLK_IDS(MACRO__, ...) \ + MACRO__(0x3184, ## __VA_ARGS__), \ + MACRO__(0x3185, ## __VA_ARGS__) + +#define INTEL_KBL_ULT_GT1_IDS(MACRO__, ...) \ + MACRO__(0x5906, ## __VA_ARGS__), /* ULT GT1 */ \ + MACRO__(0x5913, ## __VA_ARGS__) /* ULT GT1.5 */ + +#define INTEL_KBL_ULX_GT1_IDS(MACRO__, ...) \ + MACRO__(0x590E, ## __VA_ARGS__), /* ULX GT1 */ \ + MACRO__(0x5915, ## __VA_ARGS__) /* ULX GT1.5 */ + +#define INTEL_KBL_GT1_IDS(MACRO__, ...) \ + INTEL_KBL_ULT_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_KBL_ULX_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x5902, ## __VA_ARGS__), /* DT GT1 */ \ + MACRO__(0x5908, ## __VA_ARGS__), /* Halo GT1 */ \ + MACRO__(0x590A, ## __VA_ARGS__), /* SRV GT1 */ \ + MACRO__(0x590B, ## __VA_ARGS__) /* Halo GT1 */ + +#define INTEL_KBL_ULT_GT2_IDS(MACRO__, ...) \ + MACRO__(0x5916, ## __VA_ARGS__), /* ULT GT2 */ \ + MACRO__(0x5921, ## __VA_ARGS__) /* ULT GT2F */ + +#define INTEL_KBL_ULX_GT2_IDS(MACRO__, ...) \ + MACRO__(0x591E, ## __VA_ARGS__) /* ULX GT2 */ + +#define INTEL_KBL_GT2_IDS(MACRO__, ...) \ + INTEL_KBL_ULT_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_KBL_ULX_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x5912, ## __VA_ARGS__), /* DT GT2 */ \ + MACRO__(0x5917, ## __VA_ARGS__), /* Mobile GT2 */ \ + MACRO__(0x591A, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x591B, ## __VA_ARGS__), /* Halo GT2 */ \ + MACRO__(0x591D, ## __VA_ARGS__) /* WKS GT2 */ + +#define INTEL_KBL_ULT_GT3_IDS(MACRO__, ...) \ + MACRO__(0x5926, ## __VA_ARGS__) /* ULT GT3 */ + +#define INTEL_KBL_GT3_IDS(MACRO__, ...) \ + INTEL_KBL_ULT_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x5923, ## __VA_ARGS__), /* ULT GT3 */ \ + MACRO__(0x5927, ## __VA_ARGS__) /* ULT GT3 */ + +#define INTEL_KBL_GT4_IDS(MACRO__, ...) \ + MACRO__(0x593B, ## __VA_ARGS__) /* Halo GT4 */ + +/* AML/KBL Y GT2 */ +#define INTEL_AML_KBL_GT2_IDS(MACRO__, ...) \ + MACRO__(0x591C, ## __VA_ARGS__), /* ULX GT2 */ \ + MACRO__(0x87C0, ## __VA_ARGS__) /* ULX GT2 */ + +/* AML/CFL Y GT2 */ +#define INTEL_AML_CFL_GT2_IDS(MACRO__, ...) \ + MACRO__(0x87CA, ## __VA_ARGS__) + +/* CML GT1 */ +#define INTEL_CML_GT1_IDS(MACRO__, ...) \ + MACRO__(0x9BA2, ## __VA_ARGS__), \ + MACRO__(0x9BA4, ## __VA_ARGS__), \ + MACRO__(0x9BA5, ## __VA_ARGS__), \ + MACRO__(0x9BA8, ## __VA_ARGS__) + +#define INTEL_CML_U_GT1_IDS(MACRO__, ...) \ + MACRO__(0x9B21, ## __VA_ARGS__), \ + MACRO__(0x9BAA, ## __VA_ARGS__), \ + MACRO__(0x9BAC, ## __VA_ARGS__) + +/* CML GT2 */ +#define INTEL_CML_GT2_IDS(MACRO__, ...) \ + MACRO__(0x9BC2, ## __VA_ARGS__), \ + MACRO__(0x9BC4, ## __VA_ARGS__), \ + MACRO__(0x9BC5, ## __VA_ARGS__), \ + MACRO__(0x9BC6, ## __VA_ARGS__), \ + MACRO__(0x9BC8, ## __VA_ARGS__), \ + MACRO__(0x9BE6, ## __VA_ARGS__), \ + MACRO__(0x9BF6, ## __VA_ARGS__) + +#define INTEL_CML_U_GT2_IDS(MACRO__, ...) \ + MACRO__(0x9B41, ## __VA_ARGS__), \ + MACRO__(0x9BCA, ## __VA_ARGS__), \ + MACRO__(0x9BCC, ## __VA_ARGS__) + +#define INTEL_CML_IDS(MACRO__, ...) \ + INTEL_CML_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CML_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CML_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CML_U_GT2_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_KBL_IDS(MACRO__, ...) \ + INTEL_KBL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_KBL_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_KBL_GT4_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_AML_KBL_GT2_IDS(MACRO__, ## __VA_ARGS__) + +/* CFL S */ +#define INTEL_CFL_S_GT1_IDS(MACRO__, ...) \ + MACRO__(0x3E90, ## __VA_ARGS__), /* SRV GT1 */ \ + MACRO__(0x3E93, ## __VA_ARGS__), /* SRV GT1 */ \ + MACRO__(0x3E99, ## __VA_ARGS__) /* SRV GT1 */ + +#define INTEL_CFL_S_GT2_IDS(MACRO__, ...) \ + MACRO__(0x3E91, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x3E92, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x3E96, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x3E98, ## __VA_ARGS__), /* SRV GT2 */ \ + MACRO__(0x3E9A, ## __VA_ARGS__) /* SRV GT2 */ + +/* CFL H */ +#define INTEL_CFL_H_GT1_IDS(MACRO__, ...) \ + MACRO__(0x3E9C, ## __VA_ARGS__) + +#define INTEL_CFL_H_GT2_IDS(MACRO__, ...) \ + MACRO__(0x3E94, ## __VA_ARGS__), /* Halo GT2 */ \ + MACRO__(0x3E9B, ## __VA_ARGS__) /* Halo GT2 */ + +/* CFL U GT2 */ +#define INTEL_CFL_U_GT2_IDS(MACRO__, ...) \ + MACRO__(0x3EA9, ## __VA_ARGS__) + +/* CFL U GT3 */ +#define INTEL_CFL_U_GT3_IDS(MACRO__, ...) \ + MACRO__(0x3EA5, ## __VA_ARGS__), /* ULT GT3 */ \ + MACRO__(0x3EA6, ## __VA_ARGS__), /* ULT GT3 */ \ + MACRO__(0x3EA7, ## __VA_ARGS__), /* ULT GT3 */ \ + MACRO__(0x3EA8, ## __VA_ARGS__) /* ULT GT3 */ + +#define INTEL_CFL_IDS(MACRO__, ...) \ + INTEL_CFL_S_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CFL_S_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CFL_H_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CFL_H_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CFL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_CFL_U_GT3_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_AML_CFL_GT2_IDS(MACRO__, ## __VA_ARGS__) + +/* WHL/CFL U GT1 */ +#define INTEL_WHL_U_GT1_IDS(MACRO__, ...) \ + MACRO__(0x3EA1, ## __VA_ARGS__), \ + MACRO__(0x3EA4, ## __VA_ARGS__) + +/* WHL/CFL U GT2 */ +#define INTEL_WHL_U_GT2_IDS(MACRO__, ...) \ + MACRO__(0x3EA0, ## __VA_ARGS__), \ + MACRO__(0x3EA3, ## __VA_ARGS__) + +/* WHL/CFL U GT3 */ +#define INTEL_WHL_U_GT3_IDS(MACRO__, ...) \ + MACRO__(0x3EA2, ## __VA_ARGS__) + +#define INTEL_WHL_IDS(MACRO__, ...) \ + INTEL_WHL_U_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_WHL_U_GT2_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_WHL_U_GT3_IDS(MACRO__, ## __VA_ARGS__) + +/* CNL */ +#define INTEL_CNL_PORT_F_IDS(MACRO__, ...) \ + MACRO__(0x5A44, ## __VA_ARGS__), \ + MACRO__(0x5A4C, ## __VA_ARGS__), \ + MACRO__(0x5A54, ## __VA_ARGS__), \ + MACRO__(0x5A5C, ## __VA_ARGS__) + +#define INTEL_CNL_IDS(MACRO__, ...) \ + INTEL_CNL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x5A40, ## __VA_ARGS__), \ + MACRO__(0x5A41, ## __VA_ARGS__), \ + MACRO__(0x5A42, ## __VA_ARGS__), \ + MACRO__(0x5A49, ## __VA_ARGS__), \ + MACRO__(0x5A4A, ## __VA_ARGS__), \ + MACRO__(0x5A50, ## __VA_ARGS__), \ + MACRO__(0x5A51, ## __VA_ARGS__), \ + MACRO__(0x5A52, ## __VA_ARGS__), \ + MACRO__(0x5A59, ## __VA_ARGS__), \ + MACRO__(0x5A5A, ## __VA_ARGS__) + +/* ICL */ +#define INTEL_ICL_PORT_F_IDS(MACRO__, ...) \ + MACRO__(0x8A50, ## __VA_ARGS__), \ + MACRO__(0x8A52, ## __VA_ARGS__), \ + MACRO__(0x8A53, ## __VA_ARGS__), \ + MACRO__(0x8A54, ## __VA_ARGS__), \ + MACRO__(0x8A56, ## __VA_ARGS__), \ + MACRO__(0x8A57, ## __VA_ARGS__), \ + MACRO__(0x8A58, ## __VA_ARGS__), \ + MACRO__(0x8A59, ## __VA_ARGS__), \ + MACRO__(0x8A5A, ## __VA_ARGS__), \ + MACRO__(0x8A5B, ## __VA_ARGS__), \ + MACRO__(0x8A5C, ## __VA_ARGS__), \ + MACRO__(0x8A70, ## __VA_ARGS__), \ + MACRO__(0x8A71, ## __VA_ARGS__) + +#define INTEL_ICL_IDS(MACRO__, ...) \ + INTEL_ICL_PORT_F_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0x8A51, ## __VA_ARGS__), \ + MACRO__(0x8A5D, ## __VA_ARGS__) + +/* EHL */ +#define INTEL_EHL_IDS(MACRO__, ...) \ + MACRO__(0x4541, ## __VA_ARGS__), \ + MACRO__(0x4551, ## __VA_ARGS__), \ + MACRO__(0x4555, ## __VA_ARGS__), \ + MACRO__(0x4557, ## __VA_ARGS__), \ + MACRO__(0x4570, ## __VA_ARGS__), \ + MACRO__(0x4571, ## __VA_ARGS__) + +/* JSL */ +#define INTEL_JSL_IDS(MACRO__, ...) \ + MACRO__(0x4E51, ## __VA_ARGS__), \ + MACRO__(0x4E55, ## __VA_ARGS__), \ + MACRO__(0x4E57, ## __VA_ARGS__), \ + MACRO__(0x4E61, ## __VA_ARGS__), \ + MACRO__(0x4E71, ## __VA_ARGS__) + +/* TGL */ +#define INTEL_TGL_GT1_IDS(MACRO__, ...) \ + MACRO__(0x9A60, ## __VA_ARGS__), \ + MACRO__(0x9A68, ## __VA_ARGS__), \ + MACRO__(0x9A70, ## __VA_ARGS__) + +#define INTEL_TGL_GT2_IDS(MACRO__, ...) \ + MACRO__(0x9A40, ## __VA_ARGS__), \ + MACRO__(0x9A49, ## __VA_ARGS__), \ + MACRO__(0x9A59, ## __VA_ARGS__), \ + MACRO__(0x9A78, ## __VA_ARGS__), \ + MACRO__(0x9AC0, ## __VA_ARGS__), \ + MACRO__(0x9AC9, ## __VA_ARGS__), \ + MACRO__(0x9AD9, ## __VA_ARGS__), \ + MACRO__(0x9AF8, ## __VA_ARGS__) + +#define INTEL_TGL_IDS(MACRO__, ...) \ + INTEL_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__) + +/* RKL */ +#define INTEL_RKL_IDS(MACRO__, ...) \ + MACRO__(0x4C80, ## __VA_ARGS__), \ + MACRO__(0x4C8A, ## __VA_ARGS__), \ + MACRO__(0x4C8B, ## __VA_ARGS__), \ + MACRO__(0x4C8C, ## __VA_ARGS__), \ + MACRO__(0x4C90, ## __VA_ARGS__), \ + MACRO__(0x4C9A, ## __VA_ARGS__) + +/* DG1 */ +#define INTEL_DG1_IDS(MACRO__, ...) \ + MACRO__(0x4905, ## __VA_ARGS__), \ + MACRO__(0x4906, ## __VA_ARGS__), \ + MACRO__(0x4907, ## __VA_ARGS__), \ + MACRO__(0x4908, ## __VA_ARGS__), \ + MACRO__(0x4909, ## __VA_ARGS__) + +/* ADL-S */ +#define INTEL_ADLS_IDS(MACRO__, ...) \ + MACRO__(0x4680, ## __VA_ARGS__), \ + MACRO__(0x4682, ## __VA_ARGS__), \ + MACRO__(0x4688, ## __VA_ARGS__), \ + MACRO__(0x468A, ## __VA_ARGS__), \ + MACRO__(0x468B, ## __VA_ARGS__), \ + MACRO__(0x4690, ## __VA_ARGS__), \ + MACRO__(0x4692, ## __VA_ARGS__), \ + MACRO__(0x4693, ## __VA_ARGS__) + +/* ADL-P */ +#define INTEL_ADLP_IDS(MACRO__, ...) \ + MACRO__(0x46A0, ## __VA_ARGS__), \ + MACRO__(0x46A1, ## __VA_ARGS__), \ + MACRO__(0x46A2, ## __VA_ARGS__), \ + MACRO__(0x46A3, ## __VA_ARGS__), \ + MACRO__(0x46A6, ## __VA_ARGS__), \ + MACRO__(0x46A8, ## __VA_ARGS__), \ + MACRO__(0x46AA, ## __VA_ARGS__), \ + MACRO__(0x462A, ## __VA_ARGS__), \ + MACRO__(0x4626, ## __VA_ARGS__), \ + MACRO__(0x4628, ## __VA_ARGS__), \ + MACRO__(0x46B0, ## __VA_ARGS__), \ + MACRO__(0x46B1, ## __VA_ARGS__), \ + MACRO__(0x46B2, ## __VA_ARGS__), \ + MACRO__(0x46B3, ## __VA_ARGS__), \ + MACRO__(0x46C0, ## __VA_ARGS__), \ + MACRO__(0x46C1, ## __VA_ARGS__), \ + MACRO__(0x46C2, ## __VA_ARGS__), \ + MACRO__(0x46C3, ## __VA_ARGS__) + +/* ADL-N */ +#define INTEL_ADLN_IDS(MACRO__, ...) \ + MACRO__(0x46D0, ## __VA_ARGS__), \ + MACRO__(0x46D1, ## __VA_ARGS__), \ + MACRO__(0x46D2, ## __VA_ARGS__), \ + MACRO__(0x46D3, ## __VA_ARGS__), \ + MACRO__(0x46D4, ## __VA_ARGS__) + +/* RPL-S */ +#define INTEL_RPLS_IDS(MACRO__, ...) \ + MACRO__(0xA780, ## __VA_ARGS__), \ + MACRO__(0xA781, ## __VA_ARGS__), \ + MACRO__(0xA782, ## __VA_ARGS__), \ + MACRO__(0xA783, ## __VA_ARGS__), \ + MACRO__(0xA788, ## __VA_ARGS__), \ + MACRO__(0xA789, ## __VA_ARGS__), \ + MACRO__(0xA78A, ## __VA_ARGS__), \ + MACRO__(0xA78B, ## __VA_ARGS__) + +/* RPL-U */ +#define INTEL_RPLU_IDS(MACRO__, ...) \ + MACRO__(0xA721, ## __VA_ARGS__), \ + MACRO__(0xA7A1, ## __VA_ARGS__), \ + MACRO__(0xA7A9, ## __VA_ARGS__), \ + MACRO__(0xA7AC, ## __VA_ARGS__), \ + MACRO__(0xA7AD, ## __VA_ARGS__) + +/* RPL-P */ +#define INTEL_RPLP_IDS(MACRO__, ...) \ + MACRO__(0xA720, ## __VA_ARGS__), \ + MACRO__(0xA7A0, ## __VA_ARGS__), \ + MACRO__(0xA7A8, ## __VA_ARGS__), \ + MACRO__(0xA7AA, ## __VA_ARGS__), \ + MACRO__(0xA7AB, ## __VA_ARGS__) + +/* DG2 */ +#define INTEL_DG2_G10_IDS(MACRO__, ...) \ + MACRO__(0x5690, ## __VA_ARGS__), \ + MACRO__(0x5691, ## __VA_ARGS__), \ + MACRO__(0x5692, ## __VA_ARGS__), \ + MACRO__(0x56A0, ## __VA_ARGS__), \ + MACRO__(0x56A1, ## __VA_ARGS__), \ + MACRO__(0x56A2, ## __VA_ARGS__), \ + MACRO__(0x56BE, ## __VA_ARGS__), \ + MACRO__(0x56BF, ## __VA_ARGS__) + +#define INTEL_DG2_G11_IDS(MACRO__, ...) \ + MACRO__(0x5693, ## __VA_ARGS__), \ + MACRO__(0x5694, ## __VA_ARGS__), \ + MACRO__(0x5695, ## __VA_ARGS__), \ + MACRO__(0x56A5, ## __VA_ARGS__), \ + MACRO__(0x56A6, ## __VA_ARGS__), \ + MACRO__(0x56B0, ## __VA_ARGS__), \ + MACRO__(0x56B1, ## __VA_ARGS__), \ + MACRO__(0x56BA, ## __VA_ARGS__), \ + MACRO__(0x56BB, ## __VA_ARGS__), \ + MACRO__(0x56BC, ## __VA_ARGS__), \ + MACRO__(0x56BD, ## __VA_ARGS__) + +#define INTEL_DG2_G12_IDS(MACRO__, ...) \ + MACRO__(0x5696, ## __VA_ARGS__), \ + MACRO__(0x5697, ## __VA_ARGS__), \ + MACRO__(0x56A3, ## __VA_ARGS__), \ + MACRO__(0x56A4, ## __VA_ARGS__), \ + MACRO__(0x56B2, ## __VA_ARGS__), \ + MACRO__(0x56B3, ## __VA_ARGS__) + +#define INTEL_DG2_IDS(MACRO__, ...) \ + INTEL_DG2_G10_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G11_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_DG2_G12_IDS(MACRO__, ## __VA_ARGS__) + +#define INTEL_ATS_M150_IDS(MACRO__, ...) \ + MACRO__(0x56C0, ## __VA_ARGS__), \ + MACRO__(0x56C2, ## __VA_ARGS__) + +#define INTEL_ATS_M75_IDS(MACRO__, ...) \ + MACRO__(0x56C1, ## __VA_ARGS__) + +#define INTEL_ATS_M_IDS(MACRO__, ...) \ + INTEL_ATS_M150_IDS(MACRO__, ## __VA_ARGS__), \ + INTEL_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) + +/* MTL */ +#define INTEL_MTL_IDS(MACRO__, ...) \ + MACRO__(0x7D40, ## __VA_ARGS__), \ + MACRO__(0x7D41, ## __VA_ARGS__), \ + MACRO__(0x7D45, ## __VA_ARGS__), \ + MACRO__(0x7D51, ## __VA_ARGS__), \ + MACRO__(0x7D55, ## __VA_ARGS__), \ + MACRO__(0x7D60, ## __VA_ARGS__), \ + MACRO__(0x7D67, ## __VA_ARGS__), \ + MACRO__(0x7DD1, ## __VA_ARGS__), \ + MACRO__(0x7DD5, ## __VA_ARGS__) + +/* LNL */ +#define INTEL_LNL_IDS(MACRO__, ...) \ + MACRO__(0x6420, ## __VA_ARGS__), \ + MACRO__(0x64A0, ## __VA_ARGS__), \ + MACRO__(0x64B0, ## __VA_ARGS__) + +#endif /* _I915_PCIIDS_H */ -- cgit From e051d64b0a8f5fba923ffbe2003d691ef03f0607 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 16:19:09 +0300 Subject: drm: move xe_pciids.h under include/drm/intel Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter Cc: Dave Airlie Cc: Lucas De Marchi Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/e19543f2ae978678c2ff814454f07c96ccd02175.1717075103.git.jani.nikula@intel.com --- drivers/gpu/drm/xe/xe_pci.c | 2 +- include/drm/intel/xe_pciids.h | 195 ++++++++++++++++++++++++++++++++++++++++++ include/drm/xe_pciids.h | 195 ------------------------------------------ 3 files changed, 196 insertions(+), 196 deletions(-) create mode 100644 include/drm/intel/xe_pciids.h delete mode 100644 include/drm/xe_pciids.h diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index d6859108cc69..0dd21e0da94e 100644 --- a/drivers/gpu/drm/xe/xe_pci.c +++ b/drivers/gpu/drm/xe/xe_pci.c @@ -13,7 +13,7 @@ #include #include -#include +#include #include "display/xe_display.h" #include "regs/xe_gt_regs.h" diff --git a/include/drm/intel/xe_pciids.h b/include/drm/intel/xe_pciids.h new file mode 100644 index 000000000000..adb37bc541e4 --- /dev/null +++ b/include/drm/intel/xe_pciids.h @@ -0,0 +1,195 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2022 Intel Corporation + */ + +#ifndef _XE_PCIIDS_H_ +#define _XE_PCIIDS_H_ + +/* + * Lists below can be turned into initializers for a struct pci_device_id + * by defining INTEL_VGA_DEVICE: + * + * #define INTEL_VGA_DEVICE(id, info) { \ + * 0x8086, id, \ + * ~0, ~0, \ + * 0x030000, 0xff0000, \ + * (unsigned long) info } + * + * And then calling like: + * + * XE_TGL_12_GT1_IDS(INTEL_VGA_DEVICE, ## __VA_ARGS__) + * + * To turn them into something else, just provide a different macro passed as + * first argument. + */ + +/* TGL */ +#define XE_TGL_GT1_IDS(MACRO__, ...) \ + MACRO__(0x9A60, ## __VA_ARGS__), \ + MACRO__(0x9A68, ## __VA_ARGS__), \ + MACRO__(0x9A70, ## __VA_ARGS__) + +#define XE_TGL_GT2_IDS(MACRO__, ...) \ + MACRO__(0x9A40, ## __VA_ARGS__), \ + MACRO__(0x9A49, ## __VA_ARGS__), \ + MACRO__(0x9A59, ## __VA_ARGS__), \ + MACRO__(0x9A78, ## __VA_ARGS__), \ + MACRO__(0x9AC0, ## __VA_ARGS__), \ + MACRO__(0x9AC9, ## __VA_ARGS__), \ + MACRO__(0x9AD9, ## __VA_ARGS__), \ + MACRO__(0x9AF8, ## __VA_ARGS__) + +#define XE_TGL_IDS(MACRO__, ...) \ + XE_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__),\ + XE_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__) + +/* RKL */ +#define XE_RKL_IDS(MACRO__, ...) \ + MACRO__(0x4C80, ## __VA_ARGS__), \ + MACRO__(0x4C8A, ## __VA_ARGS__), \ + MACRO__(0x4C8B, ## __VA_ARGS__), \ + MACRO__(0x4C8C, ## __VA_ARGS__), \ + MACRO__(0x4C90, ## __VA_ARGS__), \ + MACRO__(0x4C9A, ## __VA_ARGS__) + +/* DG1 */ +#define XE_DG1_IDS(MACRO__, ...) \ + MACRO__(0x4905, ## __VA_ARGS__), \ + MACRO__(0x4906, ## __VA_ARGS__), \ + MACRO__(0x4907, ## __VA_ARGS__), \ + MACRO__(0x4908, ## __VA_ARGS__), \ + MACRO__(0x4909, ## __VA_ARGS__) + +/* ADL-S */ +#define XE_ADLS_IDS(MACRO__, ...) \ + MACRO__(0x4680, ## __VA_ARGS__), \ + MACRO__(0x4682, ## __VA_ARGS__), \ + MACRO__(0x4688, ## __VA_ARGS__), \ + MACRO__(0x468A, ## __VA_ARGS__), \ + MACRO__(0x468B, ## __VA_ARGS__), \ + MACRO__(0x4690, ## __VA_ARGS__), \ + MACRO__(0x4692, ## __VA_ARGS__), \ + MACRO__(0x4693, ## __VA_ARGS__) + +/* ADL-P */ +#define XE_ADLP_IDS(MACRO__, ...) \ + MACRO__(0x46A0, ## __VA_ARGS__), \ + MACRO__(0x46A1, ## __VA_ARGS__), \ + MACRO__(0x46A2, ## __VA_ARGS__), \ + MACRO__(0x46A3, ## __VA_ARGS__), \ + MACRO__(0x46A6, ## __VA_ARGS__), \ + MACRO__(0x46A8, ## __VA_ARGS__), \ + MACRO__(0x46AA, ## __VA_ARGS__), \ + MACRO__(0x462A, ## __VA_ARGS__), \ + MACRO__(0x4626, ## __VA_ARGS__), \ + MACRO__(0x4628, ## __VA_ARGS__), \ + MACRO__(0x46B0, ## __VA_ARGS__), \ + MACRO__(0x46B1, ## __VA_ARGS__), \ + MACRO__(0x46B2, ## __VA_ARGS__), \ + MACRO__(0x46B3, ## __VA_ARGS__), \ + MACRO__(0x46C0, ## __VA_ARGS__), \ + MACRO__(0x46C1, ## __VA_ARGS__), \ + MACRO__(0x46C2, ## __VA_ARGS__), \ + MACRO__(0x46C3, ## __VA_ARGS__) + +/* ADL-N */ +#define XE_ADLN_IDS(MACRO__, ...) \ + MACRO__(0x46D0, ## __VA_ARGS__), \ + MACRO__(0x46D1, ## __VA_ARGS__), \ + MACRO__(0x46D2, ## __VA_ARGS__) + +/* RPL-S */ +#define XE_RPLS_IDS(MACRO__, ...) \ + MACRO__(0xA780, ## __VA_ARGS__), \ + MACRO__(0xA781, ## __VA_ARGS__), \ + MACRO__(0xA782, ## __VA_ARGS__), \ + MACRO__(0xA783, ## __VA_ARGS__), \ + MACRO__(0xA788, ## __VA_ARGS__), \ + MACRO__(0xA789, ## __VA_ARGS__), \ + MACRO__(0xA78A, ## __VA_ARGS__), \ + MACRO__(0xA78B, ## __VA_ARGS__) + +/* RPL-U */ +#define XE_RPLU_IDS(MACRO__, ...) \ + MACRO__(0xA721, ## __VA_ARGS__), \ + MACRO__(0xA7A1, ## __VA_ARGS__), \ + MACRO__(0xA7A9, ## __VA_ARGS__), \ + MACRO__(0xA7AC, ## __VA_ARGS__), \ + MACRO__(0xA7AD, ## __VA_ARGS__) + +/* RPL-P */ +#define XE_RPLP_IDS(MACRO__, ...) \ + XE_RPLU_IDS(MACRO__, ## __VA_ARGS__), \ + MACRO__(0xA720, ## __VA_ARGS__), \ + MACRO__(0xA7A0, ## __VA_ARGS__), \ + MACRO__(0xA7A8, ## __VA_ARGS__), \ + MACRO__(0xA7AA, ## __VA_ARGS__), \ + MACRO__(0xA7AB, ## __VA_ARGS__) + +/* DG2 */ +#define XE_DG2_G10_IDS(MACRO__, ...) \ + MACRO__(0x5690, ## __VA_ARGS__), \ + MACRO__(0x5691, ## __VA_ARGS__), \ + MACRO__(0x5692, ## __VA_ARGS__), \ + MACRO__(0x56A0, ## __VA_ARGS__), \ + MACRO__(0x56A1, ## __VA_ARGS__), \ + MACRO__(0x56A2, ## __VA_ARGS__), \ + MACRO__(0x56BE, ## __VA_ARGS__), \ + MACRO__(0x56BF, ## __VA_ARGS__) + +#define XE_DG2_G11_IDS(MACRO__, ...) \ + MACRO__(0x5693, ## __VA_ARGS__), \ + MACRO__(0x5694, ## __VA_ARGS__), \ + MACRO__(0x5695, ## __VA_ARGS__), \ + MACRO__(0x56A5, ## __VA_ARGS__), \ + MACRO__(0x56A6, ## __VA_ARGS__), \ + MACRO__(0x56B0, ## __VA_ARGS__), \ + MACRO__(0x56B1, ## __VA_ARGS__), \ + MACRO__(0x56BA, ## __VA_ARGS__), \ + MACRO__(0x56BB, ## __VA_ARGS__), \ + MACRO__(0x56BC, ## __VA_ARGS__), \ + MACRO__(0x56BD, ## __VA_ARGS__) + +#define XE_DG2_G12_IDS(MACRO__, ...) \ + MACRO__(0x5696, ## __VA_ARGS__), \ + MACRO__(0x5697, ## __VA_ARGS__), \ + MACRO__(0x56A3, ## __VA_ARGS__), \ + MACRO__(0x56A4, ## __VA_ARGS__), \ + MACRO__(0x56B2, ## __VA_ARGS__), \ + MACRO__(0x56B3, ## __VA_ARGS__) + +#define XE_DG2_IDS(MACRO__, ...) \ + XE_DG2_G10_IDS(MACRO__, ## __VA_ARGS__),\ + XE_DG2_G11_IDS(MACRO__, ## __VA_ARGS__),\ + XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__) + +#define XE_ATS_M150_IDS(MACRO__, ...) \ + MACRO__(0x56C0, ## __VA_ARGS__), \ + MACRO__(0x56C2, ## __VA_ARGS__) + +#define XE_ATS_M75_IDS(MACRO__, ...) \ + MACRO__(0x56C1, ## __VA_ARGS__) + +#define XE_ATS_M_IDS(MACRO__, ...) \ + XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\ + XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) + +/* MTL / ARL */ +#define XE_MTL_IDS(MACRO__, ...) \ + MACRO__(0x7D40, ## __VA_ARGS__), \ + MACRO__(0x7D41, ## __VA_ARGS__), \ + MACRO__(0x7D45, ## __VA_ARGS__), \ + MACRO__(0x7D51, ## __VA_ARGS__), \ + MACRO__(0x7D55, ## __VA_ARGS__), \ + MACRO__(0x7D60, ## __VA_ARGS__), \ + MACRO__(0x7D67, ## __VA_ARGS__), \ + MACRO__(0x7DD1, ## __VA_ARGS__), \ + MACRO__(0x7DD5, ## __VA_ARGS__) + +#define XE_LNL_IDS(MACRO__, ...) \ + MACRO__(0x6420, ## __VA_ARGS__), \ + MACRO__(0x64A0, ## __VA_ARGS__), \ + MACRO__(0x64B0, ## __VA_ARGS__) + +#endif diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h deleted file mode 100644 index adb37bc541e4..000000000000 --- a/include/drm/xe_pciids.h +++ /dev/null @@ -1,195 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2022 Intel Corporation - */ - -#ifndef _XE_PCIIDS_H_ -#define _XE_PCIIDS_H_ - -/* - * Lists below can be turned into initializers for a struct pci_device_id - * by defining INTEL_VGA_DEVICE: - * - * #define INTEL_VGA_DEVICE(id, info) { \ - * 0x8086, id, \ - * ~0, ~0, \ - * 0x030000, 0xff0000, \ - * (unsigned long) info } - * - * And then calling like: - * - * XE_TGL_12_GT1_IDS(INTEL_VGA_DEVICE, ## __VA_ARGS__) - * - * To turn them into something else, just provide a different macro passed as - * first argument. - */ - -/* TGL */ -#define XE_TGL_GT1_IDS(MACRO__, ...) \ - MACRO__(0x9A60, ## __VA_ARGS__), \ - MACRO__(0x9A68, ## __VA_ARGS__), \ - MACRO__(0x9A70, ## __VA_ARGS__) - -#define XE_TGL_GT2_IDS(MACRO__, ...) \ - MACRO__(0x9A40, ## __VA_ARGS__), \ - MACRO__(0x9A49, ## __VA_ARGS__), \ - MACRO__(0x9A59, ## __VA_ARGS__), \ - MACRO__(0x9A78, ## __VA_ARGS__), \ - MACRO__(0x9AC0, ## __VA_ARGS__), \ - MACRO__(0x9AC9, ## __VA_ARGS__), \ - MACRO__(0x9AD9, ## __VA_ARGS__), \ - MACRO__(0x9AF8, ## __VA_ARGS__) - -#define XE_TGL_IDS(MACRO__, ...) \ - XE_TGL_GT1_IDS(MACRO__, ## __VA_ARGS__),\ - XE_TGL_GT2_IDS(MACRO__, ## __VA_ARGS__) - -/* RKL */ -#define XE_RKL_IDS(MACRO__, ...) \ - MACRO__(0x4C80, ## __VA_ARGS__), \ - MACRO__(0x4C8A, ## __VA_ARGS__), \ - MACRO__(0x4C8B, ## __VA_ARGS__), \ - MACRO__(0x4C8C, ## __VA_ARGS__), \ - MACRO__(0x4C90, ## __VA_ARGS__), \ - MACRO__(0x4C9A, ## __VA_ARGS__) - -/* DG1 */ -#define XE_DG1_IDS(MACRO__, ...) \ - MACRO__(0x4905, ## __VA_ARGS__), \ - MACRO__(0x4906, ## __VA_ARGS__), \ - MACRO__(0x4907, ## __VA_ARGS__), \ - MACRO__(0x4908, ## __VA_ARGS__), \ - MACRO__(0x4909, ## __VA_ARGS__) - -/* ADL-S */ -#define XE_ADLS_IDS(MACRO__, ...) \ - MACRO__(0x4680, ## __VA_ARGS__), \ - MACRO__(0x4682, ## __VA_ARGS__), \ - MACRO__(0x4688, ## __VA_ARGS__), \ - MACRO__(0x468A, ## __VA_ARGS__), \ - MACRO__(0x468B, ## __VA_ARGS__), \ - MACRO__(0x4690, ## __VA_ARGS__), \ - MACRO__(0x4692, ## __VA_ARGS__), \ - MACRO__(0x4693, ## __VA_ARGS__) - -/* ADL-P */ -#define XE_ADLP_IDS(MACRO__, ...) \ - MACRO__(0x46A0, ## __VA_ARGS__), \ - MACRO__(0x46A1, ## __VA_ARGS__), \ - MACRO__(0x46A2, ## __VA_ARGS__), \ - MACRO__(0x46A3, ## __VA_ARGS__), \ - MACRO__(0x46A6, ## __VA_ARGS__), \ - MACRO__(0x46A8, ## __VA_ARGS__), \ - MACRO__(0x46AA, ## __VA_ARGS__), \ - MACRO__(0x462A, ## __VA_ARGS__), \ - MACRO__(0x4626, ## __VA_ARGS__), \ - MACRO__(0x4628, ## __VA_ARGS__), \ - MACRO__(0x46B0, ## __VA_ARGS__), \ - MACRO__(0x46B1, ## __VA_ARGS__), \ - MACRO__(0x46B2, ## __VA_ARGS__), \ - MACRO__(0x46B3, ## __VA_ARGS__), \ - MACRO__(0x46C0, ## __VA_ARGS__), \ - MACRO__(0x46C1, ## __VA_ARGS__), \ - MACRO__(0x46C2, ## __VA_ARGS__), \ - MACRO__(0x46C3, ## __VA_ARGS__) - -/* ADL-N */ -#define XE_ADLN_IDS(MACRO__, ...) \ - MACRO__(0x46D0, ## __VA_ARGS__), \ - MACRO__(0x46D1, ## __VA_ARGS__), \ - MACRO__(0x46D2, ## __VA_ARGS__) - -/* RPL-S */ -#define XE_RPLS_IDS(MACRO__, ...) \ - MACRO__(0xA780, ## __VA_ARGS__), \ - MACRO__(0xA781, ## __VA_ARGS__), \ - MACRO__(0xA782, ## __VA_ARGS__), \ - MACRO__(0xA783, ## __VA_ARGS__), \ - MACRO__(0xA788, ## __VA_ARGS__), \ - MACRO__(0xA789, ## __VA_ARGS__), \ - MACRO__(0xA78A, ## __VA_ARGS__), \ - MACRO__(0xA78B, ## __VA_ARGS__) - -/* RPL-U */ -#define XE_RPLU_IDS(MACRO__, ...) \ - MACRO__(0xA721, ## __VA_ARGS__), \ - MACRO__(0xA7A1, ## __VA_ARGS__), \ - MACRO__(0xA7A9, ## __VA_ARGS__), \ - MACRO__(0xA7AC, ## __VA_ARGS__), \ - MACRO__(0xA7AD, ## __VA_ARGS__) - -/* RPL-P */ -#define XE_RPLP_IDS(MACRO__, ...) \ - XE_RPLU_IDS(MACRO__, ## __VA_ARGS__), \ - MACRO__(0xA720, ## __VA_ARGS__), \ - MACRO__(0xA7A0, ## __VA_ARGS__), \ - MACRO__(0xA7A8, ## __VA_ARGS__), \ - MACRO__(0xA7AA, ## __VA_ARGS__), \ - MACRO__(0xA7AB, ## __VA_ARGS__) - -/* DG2 */ -#define XE_DG2_G10_IDS(MACRO__, ...) \ - MACRO__(0x5690, ## __VA_ARGS__), \ - MACRO__(0x5691, ## __VA_ARGS__), \ - MACRO__(0x5692, ## __VA_ARGS__), \ - MACRO__(0x56A0, ## __VA_ARGS__), \ - MACRO__(0x56A1, ## __VA_ARGS__), \ - MACRO__(0x56A2, ## __VA_ARGS__), \ - MACRO__(0x56BE, ## __VA_ARGS__), \ - MACRO__(0x56BF, ## __VA_ARGS__) - -#define XE_DG2_G11_IDS(MACRO__, ...) \ - MACRO__(0x5693, ## __VA_ARGS__), \ - MACRO__(0x5694, ## __VA_ARGS__), \ - MACRO__(0x5695, ## __VA_ARGS__), \ - MACRO__(0x56A5, ## __VA_ARGS__), \ - MACRO__(0x56A6, ## __VA_ARGS__), \ - MACRO__(0x56B0, ## __VA_ARGS__), \ - MACRO__(0x56B1, ## __VA_ARGS__), \ - MACRO__(0x56BA, ## __VA_ARGS__), \ - MACRO__(0x56BB, ## __VA_ARGS__), \ - MACRO__(0x56BC, ## __VA_ARGS__), \ - MACRO__(0x56BD, ## __VA_ARGS__) - -#define XE_DG2_G12_IDS(MACRO__, ...) \ - MACRO__(0x5696, ## __VA_ARGS__), \ - MACRO__(0x5697, ## __VA_ARGS__), \ - MACRO__(0x56A3, ## __VA_ARGS__), \ - MACRO__(0x56A4, ## __VA_ARGS__), \ - MACRO__(0x56B2, ## __VA_ARGS__), \ - MACRO__(0x56B3, ## __VA_ARGS__) - -#define XE_DG2_IDS(MACRO__, ...) \ - XE_DG2_G10_IDS(MACRO__, ## __VA_ARGS__),\ - XE_DG2_G11_IDS(MACRO__, ## __VA_ARGS__),\ - XE_DG2_G12_IDS(MACRO__, ## __VA_ARGS__) - -#define XE_ATS_M150_IDS(MACRO__, ...) \ - MACRO__(0x56C0, ## __VA_ARGS__), \ - MACRO__(0x56C2, ## __VA_ARGS__) - -#define XE_ATS_M75_IDS(MACRO__, ...) \ - MACRO__(0x56C1, ## __VA_ARGS__) - -#define XE_ATS_M_IDS(MACRO__, ...) \ - XE_ATS_M150_IDS(MACRO__, ## __VA_ARGS__),\ - XE_ATS_M75_IDS(MACRO__, ## __VA_ARGS__) - -/* MTL / ARL */ -#define XE_MTL_IDS(MACRO__, ...) \ - MACRO__(0x7D40, ## __VA_ARGS__), \ - MACRO__(0x7D41, ## __VA_ARGS__), \ - MACRO__(0x7D45, ## __VA_ARGS__), \ - MACRO__(0x7D51, ## __VA_ARGS__), \ - MACRO__(0x7D55, ## __VA_ARGS__), \ - MACRO__(0x7D60, ## __VA_ARGS__), \ - MACRO__(0x7D67, ## __VA_ARGS__), \ - MACRO__(0x7DD1, ## __VA_ARGS__), \ - MACRO__(0x7DD5, ## __VA_ARGS__) - -#define XE_LNL_IDS(MACRO__, ...) \ - MACRO__(0x6420, ## __VA_ARGS__), \ - MACRO__(0x64A0, ## __VA_ARGS__), \ - MACRO__(0x64B0, ## __VA_ARGS__) - -#endif -- cgit From 3acbde3e9ef941fe6c847a007f72aefee0746226 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 30 May 2024 16:19:10 +0300 Subject: drm: move i915_hdcp_interface.h under include/drm/intel Clean up the top level include/drm directory by grouping all the Intel specific files under a common subdirectory. Cc: Daniel Vetter Cc: Dave Airlie Cc: Lucas De Marchi Cc: Tomas Winkler Acked-by: Lucas De Marchi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/5f53384118e33123d3c87b94cc8835360237698b.1717075103.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 2 +- drivers/gpu/drm/i915/display/intel_hdcp_gsc.c | 2 +- .../gpu/drm/i915/display/intel_hdcp_gsc_message.c | 2 +- drivers/gpu/drm/xe/display/xe_hdcp_gsc.c | 2 +- drivers/misc/mei/hdcp/mei_hdcp.c | 2 +- include/drm/i915_hdcp_interface.h | 547 --------------------- include/drm/intel/i915_hdcp_interface.h | 547 +++++++++++++++++++++ 7 files changed, 552 insertions(+), 552 deletions(-) delete mode 100644 include/drm/i915_hdcp_interface.h create mode 100644 include/drm/intel/i915_hdcp_interface.h diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 012ff9e18b54..52d0fd2bdc82 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -44,7 +44,7 @@ #include #include #include -#include +#include #include #include "i915_vma.h" diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c index 35823e1f65d6..16afeb8a3a8d 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc.c @@ -3,7 +3,7 @@ * Copyright 2023, Intel Corporation. */ -#include +#include #include "gem/i915_gem_region.h" #include "gt/intel_gt.h" diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c index 240b00849f3d..6548e71b4c49 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include "i915_drv.h" #include "intel_hdcp_gsc_message.h" diff --git a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c index d46f87a039f2..e44adbccf694 100644 --- a/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c +++ b/drivers/gpu/drm/xe/display/xe_hdcp_gsc.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include "abi/gsc_command_header_abi.h" diff --git a/drivers/misc/mei/hdcp/mei_hdcp.c b/drivers/misc/mei/hdcp/mei_hdcp.c index e43ea536c947..323f10620d90 100644 --- a/drivers/misc/mei/hdcp/mei_hdcp.c +++ b/drivers/misc/mei/hdcp/mei_hdcp.c @@ -24,7 +24,7 @@ #include #include #include -#include +#include #include "mei_hdcp.h" diff --git a/include/drm/i915_hdcp_interface.h b/include/drm/i915_hdcp_interface.h deleted file mode 100644 index d776ed7dcd00..000000000000 --- a/include/drm/i915_hdcp_interface.h +++ /dev/null @@ -1,547 +0,0 @@ -/* SPDX-License-Identifier: (GPL-2.0+) */ -/* - * Copyright © 2017-2019 Intel Corporation - * - * Authors: - * Ramalingam C - */ - -#ifndef _I915_HDCP_INTERFACE_H_ -#define _I915_HDCP_INTERFACE_H_ - -#include -#include -#include - -/** - * enum hdcp_port_type - HDCP port implementation type defined by ME/GSC FW - * @HDCP_PORT_TYPE_INVALID: Invalid hdcp port type - * @HDCP_PORT_TYPE_INTEGRATED: In-Host HDCP2.x port - * @HDCP_PORT_TYPE_LSPCON: HDCP2.2 discrete wired Tx port with LSPCON - * (HDMI 2.0) solution - * @HDCP_PORT_TYPE_CPDP: HDCP2.2 discrete wired Tx port using the CPDP (DP 1.3) - * solution - */ -enum hdcp_port_type { - HDCP_PORT_TYPE_INVALID, - HDCP_PORT_TYPE_INTEGRATED, - HDCP_PORT_TYPE_LSPCON, - HDCP_PORT_TYPE_CPDP -}; - -/** - * enum hdcp_wired_protocol - HDCP adaptation used on the port - * @HDCP_PROTOCOL_INVALID: Invalid HDCP adaptation protocol - * @HDCP_PROTOCOL_HDMI: HDMI adaptation of HDCP used on the port - * @HDCP_PROTOCOL_DP: DP adaptation of HDCP used on the port - */ -enum hdcp_wired_protocol { - HDCP_PROTOCOL_INVALID, - HDCP_PROTOCOL_HDMI, - HDCP_PROTOCOL_DP -}; - -enum hdcp_ddi { - HDCP_DDI_INVALID_PORT = 0x0, - - HDCP_DDI_B = 1, - HDCP_DDI_C, - HDCP_DDI_D, - HDCP_DDI_E, - HDCP_DDI_F, - HDCP_DDI_A = 7, - HDCP_DDI_RANGE_END = HDCP_DDI_A, -}; - -/** - * enum hdcp_transcoder - ME/GSC Firmware defined index for transcoders - * @HDCP_INVALID_TRANSCODER: Index for Invalid transcoder - * @HDCP_TRANSCODER_EDP: Index for EDP Transcoder - * @HDCP_TRANSCODER_DSI0: Index for DSI0 Transcoder - * @HDCP_TRANSCODER_DSI1: Index for DSI1 Transcoder - * @HDCP_TRANSCODER_A: Index for Transcoder A - * @HDCP_TRANSCODER_B: Index for Transcoder B - * @HDCP_TRANSCODER_C: Index for Transcoder C - * @HDCP_TRANSCODER_D: Index for Transcoder D - */ -enum hdcp_transcoder { - HDCP_INVALID_TRANSCODER = 0x00, - HDCP_TRANSCODER_EDP, - HDCP_TRANSCODER_DSI0, - HDCP_TRANSCODER_DSI1, - HDCP_TRANSCODER_A = 0x10, - HDCP_TRANSCODER_B, - HDCP_TRANSCODER_C, - HDCP_TRANSCODER_D -}; - -/** - * struct hdcp_port_data - intel specific HDCP port data - * @hdcp_ddi: ddi index as per ME/GSC FW - * @hdcp_transcoder: transcoder index as per ME/GSC FW - * @port_type: HDCP port type as per ME/GSC FW classification - * @protocol: HDCP adaptation as per ME/GSC FW - * @k: No of streams transmitted on a port. Only on DP MST this is != 1 - * @seq_num_m: Count of RepeaterAuth_Stream_Manage msg propagated. - * Initialized to 0 on AKE_INIT. Incremented after every successful - * transmission of RepeaterAuth_Stream_Manage message. When it rolls - * over re-Auth has to be triggered. - * @streams: struct hdcp2_streamid_type[k]. Defines the type and id for the - * streams - */ -struct hdcp_port_data { - enum hdcp_ddi hdcp_ddi; - enum hdcp_transcoder hdcp_transcoder; - u8 port_type; - u8 protocol; - u16 k; - u32 seq_num_m; - struct hdcp2_streamid_type *streams; -}; - -/** - * struct i915_hdcp_ops- ops for HDCP2.2 services. - * @owner: Module providing the ops - * @initiate_hdcp2_session: Initiate a Wired HDCP2.2 Tx Session. - * And Prepare AKE_Init. - * @verify_receiver_cert_prepare_km: Verify the Receiver Certificate - * AKE_Send_Cert and prepare - * AKE_Stored_Km/AKE_No_Stored_Km - * @verify_hprime: Verify AKE_Send_H_prime - * @store_pairing_info: Store pairing info received - * @initiate_locality_check: Prepare LC_Init - * @verify_lprime: Verify lprime - * @get_session_key: Prepare SKE_Send_Eks - * @repeater_check_flow_prepare_ack: Validate the Downstream topology - * and prepare rep_ack - * @verify_mprime: Verify mprime - * @enable_hdcp_authentication: Mark a port as authenticated. - * @close_hdcp_session: Close the Wired HDCP Tx session per port. - * This also disables the authenticated state of the port. - */ -struct i915_hdcp_ops { - /** - * @owner: hdcp module - */ - struct module *owner; - - int (*initiate_hdcp2_session)(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_ake_init *ake_data); - int (*verify_receiver_cert_prepare_km)(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_ake_send_cert - *rx_cert, - bool *km_stored, - struct hdcp2_ake_no_stored_km - *ek_pub_km, - size_t *msg_sz); - int (*verify_hprime)(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_ake_send_hprime *rx_hprime); - int (*store_pairing_info)(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_ake_send_pairing_info - *pairing_info); - int (*initiate_locality_check)(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_lc_init *lc_init_data); - int (*verify_lprime)(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_lc_send_lprime *rx_lprime); - int (*get_session_key)(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_ske_send_eks *ske_data); - int (*repeater_check_flow_prepare_ack)(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_rep_send_receiverid_list - *rep_topology, - struct hdcp2_rep_send_ack - *rep_send_ack); - int (*verify_mprime)(struct device *dev, - struct hdcp_port_data *data, - struct hdcp2_rep_stream_ready *stream_ready); - int (*enable_hdcp_authentication)(struct device *dev, - struct hdcp_port_data *data); - int (*close_hdcp_session)(struct device *dev, - struct hdcp_port_data *data); -}; - -/** - * struct i915_hdcp_arbiter - Used for communication between i915 - * and hdcp drivers for the HDCP2.2 services - */ -struct i915_hdcp_arbiter { - /** - * @hdcp_dev: device that provides the HDCP2.2 service from MEI Bus. - */ - struct device *hdcp_dev; - - /** - * @ops: Ops implemented by hdcp driver or intel_hdcp_gsc, used by i915 - * driver. - */ - const struct i915_hdcp_ops *ops; - - /** - * @mutex: To protect the above members. - */ - struct mutex mutex; -}; - -/* fw_hdcp_status: Enumeration of all HDCP Status Codes */ -enum fw_hdcp_status { - FW_HDCP_STATUS_SUCCESS = 0x0000, - - /* WiDi Generic Status Codes */ - FW_HDCP_STATUS_INTERNAL_ERROR = 0x1000, - FW_HDCP_STATUS_UNKNOWN_ERROR = 0x1001, - FW_HDCP_STATUS_INCORRECT_API_VERSION = 0x1002, - FW_HDCP_STATUS_INVALID_FUNCTION = 0x1003, - FW_HDCP_STATUS_INVALID_BUFFER_LENGTH = 0x1004, - FW_HDCP_STATUS_INVALID_PARAMS = 0x1005, - FW_HDCP_STATUS_AUTHENTICATION_FAILED = 0x1006, - - /* WiDi Status Codes */ - FW_HDCP_INVALID_SESSION_STATE = 0x6000, - FW_HDCP_SRM_FRAGMENT_UNEXPECTED = 0x6001, - FW_HDCP_SRM_INVALID_LENGTH = 0x6002, - FW_HDCP_SRM_FRAGMENT_OFFSET_INVALID = 0x6003, - FW_HDCP_SRM_VERIFICATION_FAILED = 0x6004, - FW_HDCP_SRM_VERSION_TOO_OLD = 0x6005, - FW_HDCP_RX_CERT_VERIFICATION_FAILED = 0x6006, - FW_HDCP_RX_REVOKED = 0x6007, - FW_HDCP_H_VERIFICATION_FAILED = 0x6008, - FW_HDCP_REPEATER_CHECK_UNEXPECTED = 0x6009, - FW_HDCP_TOPOLOGY_MAX_EXCEEDED = 0x600A, - FW_HDCP_V_VERIFICATION_FAILED = 0x600B, - FW_HDCP_L_VERIFICATION_FAILED = 0x600C, - FW_HDCP_STREAM_KEY_ALLOC_FAILED = 0x600D, - FW_HDCP_BASE_KEY_RESET_FAILED = 0x600E, - FW_HDCP_NONCE_GENERATION_FAILED = 0x600F, - FW_HDCP_STATUS_INVALID_E_KEY_STATE = 0x6010, - FW_HDCP_STATUS_INVALID_CS_ICV = 0x6011, - FW_HDCP_STATUS_INVALID_KB_KEY_STATE = 0x6012, - FW_HDCP_STATUS_INVALID_PAVP_MODE_ICV = 0x6013, - FW_HDCP_STATUS_INVALID_PAVP_MODE = 0x6014, - FW_HDCP_STATUS_LC_MAX_ATTEMPTS = 0x6015, - - /* New status for HDCP 2.1 */ - FW_HDCP_STATUS_MISMATCH_IN_M = 0x6016, - - /* New status code for HDCP 2.2 Rx */ - FW_HDCP_STATUS_RX_PROV_NOT_ALLOWED = 0x6017, - FW_HDCP_STATUS_RX_PROV_WRONG_SUBJECT = 0x6018, - FW_HDCP_RX_NEEDS_PROVISIONING = 0x6019, - FW_HDCP_BKSV_ICV_AUTH_FAILED = 0x6020, - FW_HDCP_STATUS_INVALID_STREAM_ID = 0x6021, - FW_HDCP_STATUS_CHAIN_NOT_INITIALIZED = 0x6022, - FW_HDCP_FAIL_NOT_EXPECTED = 0x6023, - FW_HDCP_FAIL_HDCP_OFF = 0x6024, - FW_HDCP_FAIL_INVALID_PAVP_MEMORY_MODE = 0x6025, - FW_HDCP_FAIL_AES_ECB_FAILURE = 0x6026, - FW_HDCP_FEATURE_NOT_SUPPORTED = 0x6027, - FW_HDCP_DMA_READ_ERROR = 0x6028, - FW_HDCP_DMA_WRITE_ERROR = 0x6029, - FW_HDCP_FAIL_INVALID_PACKET_SIZE = 0x6030, - FW_HDCP_H264_PARSING_ERROR = 0x6031, - FW_HDCP_HDCP2_ERRATA_VIDEO_VIOLATION = 0x6032, - FW_HDCP_HDCP2_ERRATA_AUDIO_VIOLATION = 0x6033, - FW_HDCP_TX_ACTIVE_ERROR = 0x6034, - FW_HDCP_MODE_CHANGE_ERROR = 0x6035, - FW_HDCP_STREAM_TYPE_ERROR = 0x6036, - FW_HDCP_STREAM_MANAGE_NOT_POSSIBLE = 0x6037, - - FW_HDCP_STATUS_PORT_INVALID_COMMAND = 0x6038, - FW_HDCP_STATUS_UNSUPPORTED_PROTOCOL = 0x6039, - FW_HDCP_STATUS_INVALID_PORT_INDEX = 0x603a, - FW_HDCP_STATUS_TX_AUTH_NEEDED = 0x603b, - FW_HDCP_STATUS_NOT_INTEGRATED_PORT = 0x603c, - FW_HDCP_STATUS_SESSION_MAX_REACHED = 0x603d, - - /* hdcp capable bit is not set in rx_caps(error is unique to DP) */ - FW_HDCP_STATUS_NOT_HDCP_CAPABLE = 0x6041, - - FW_HDCP_STATUS_INVALID_STREAM_COUNT = 0x6042, -}; - -#define HDCP_API_VERSION 0x00010000 - -#define HDCP_M_LEN 16 -#define HDCP_KH_LEN 16 - -/* Payload Buffer size(Excluding Header) for CMDs and corresponding response */ -/* Wired_Tx_AKE */ -#define WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN (4 + 1) -#define WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_OUT (4 + 8 + 3) - -#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN (4 + 522 + 8 + 3) -#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_MIN_OUT (4 + 1 + 3 + 16 + 16) -#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_MAX_OUT (4 + 1 + 3 + 128) - -#define WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN (4 + 32) -#define WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_OUT (4) - -#define WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN (4 + 16) -#define WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_OUT (4) - -#define WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN (4) -#define WIRED_CMD_BUF_LEN_CLOSE_SESSION_OUT (4) - -/* Wired_Tx_LC */ -#define WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN (4) -#define WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_OUT (4 + 8) - -#define WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN (4 + 32) -#define WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_OUT (4) - -/* Wired_Tx_SKE */ -#define WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN (4) -#define WIRED_CMD_BUF_LEN_GET_SESSION_KEY_OUT (4 + 16 + 8) - -/* Wired_Tx_SKE */ -#define WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN (4 + 1) -#define WIRED_CMD_BUF_LEN_ENABLE_AUTH_OUT (4) - -/* Wired_Tx_Repeater */ -#define WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN (4 + 2 + 3 + 16 + 155) -#define WIRED_CMD_BUF_LEN_VERIFY_REPEATER_OUT (4 + 1 + 16) - -#define WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN (4 + 3 + \ - 32 + 2 + 2) - -#define WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_OUT (4) - -/* hdcp_command_id: Enumeration of all WIRED HDCP Command IDs */ -enum hdcp_command_id { - _WIDI_COMMAND_BASE = 0x00030000, - WIDI_INITIATE_HDCP2_SESSION = _WIDI_COMMAND_BASE, - HDCP_GET_SRM_STATUS, - HDCP_SEND_SRM_FRAGMENT, - - /* The wired HDCP Tx commands */ - _WIRED_COMMAND_BASE = 0x00031000, - WIRED_INITIATE_HDCP2_SESSION = _WIRED_COMMAND_BASE, - WIRED_VERIFY_RECEIVER_CERT, - WIRED_AKE_SEND_HPRIME, - WIRED_AKE_SEND_PAIRING_INFO, - WIRED_INIT_LOCALITY_CHECK, - WIRED_VALIDATE_LOCALITY, - WIRED_GET_SESSION_KEY, - WIRED_ENABLE_AUTH, - WIRED_VERIFY_REPEATER, - WIRED_REPEATER_AUTH_STREAM_REQ, - WIRED_CLOSE_SESSION, - - _WIRED_COMMANDS_COUNT, -}; - -union encrypted_buff { - u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN]; - u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN]; - struct { - u8 e_kh_km[HDCP_KH_LEN]; - u8 m[HDCP_M_LEN]; - } __packed; -}; - -/* HDCP HECI message header. All header values are little endian. */ -struct hdcp_cmd_header { - u32 api_version; - u32 command_id; - enum fw_hdcp_status status; - /* Length of the HECI message (excluding the header) */ - u32 buffer_len; -} __packed; - -/* Empty command request or response. No data follows the header. */ -struct hdcp_cmd_no_data { - struct hdcp_cmd_header header; -} __packed; - -/* Uniquely identifies the hdcp port being addressed for a given command. */ -struct hdcp_port_id { - u8 integrated_port_type; - /* physical_port is used until Gen11.5. Must be zero for Gen11.5+ */ - u8 physical_port; - /* attached_transcoder is for Gen11.5+. Set to zero for + */ + +#ifndef _I915_HDCP_INTERFACE_H_ +#define _I915_HDCP_INTERFACE_H_ + +#include +#include +#include + +/** + * enum hdcp_port_type - HDCP port implementation type defined by ME/GSC FW + * @HDCP_PORT_TYPE_INVALID: Invalid hdcp port type + * @HDCP_PORT_TYPE_INTEGRATED: In-Host HDCP2.x port + * @HDCP_PORT_TYPE_LSPCON: HDCP2.2 discrete wired Tx port with LSPCON + * (HDMI 2.0) solution + * @HDCP_PORT_TYPE_CPDP: HDCP2.2 discrete wired Tx port using the CPDP (DP 1.3) + * solution + */ +enum hdcp_port_type { + HDCP_PORT_TYPE_INVALID, + HDCP_PORT_TYPE_INTEGRATED, + HDCP_PORT_TYPE_LSPCON, + HDCP_PORT_TYPE_CPDP +}; + +/** + * enum hdcp_wired_protocol - HDCP adaptation used on the port + * @HDCP_PROTOCOL_INVALID: Invalid HDCP adaptation protocol + * @HDCP_PROTOCOL_HDMI: HDMI adaptation of HDCP used on the port + * @HDCP_PROTOCOL_DP: DP adaptation of HDCP used on the port + */ +enum hdcp_wired_protocol { + HDCP_PROTOCOL_INVALID, + HDCP_PROTOCOL_HDMI, + HDCP_PROTOCOL_DP +}; + +enum hdcp_ddi { + HDCP_DDI_INVALID_PORT = 0x0, + + HDCP_DDI_B = 1, + HDCP_DDI_C, + HDCP_DDI_D, + HDCP_DDI_E, + HDCP_DDI_F, + HDCP_DDI_A = 7, + HDCP_DDI_RANGE_END = HDCP_DDI_A, +}; + +/** + * enum hdcp_transcoder - ME/GSC Firmware defined index for transcoders + * @HDCP_INVALID_TRANSCODER: Index for Invalid transcoder + * @HDCP_TRANSCODER_EDP: Index for EDP Transcoder + * @HDCP_TRANSCODER_DSI0: Index for DSI0 Transcoder + * @HDCP_TRANSCODER_DSI1: Index for DSI1 Transcoder + * @HDCP_TRANSCODER_A: Index for Transcoder A + * @HDCP_TRANSCODER_B: Index for Transcoder B + * @HDCP_TRANSCODER_C: Index for Transcoder C + * @HDCP_TRANSCODER_D: Index for Transcoder D + */ +enum hdcp_transcoder { + HDCP_INVALID_TRANSCODER = 0x00, + HDCP_TRANSCODER_EDP, + HDCP_TRANSCODER_DSI0, + HDCP_TRANSCODER_DSI1, + HDCP_TRANSCODER_A = 0x10, + HDCP_TRANSCODER_B, + HDCP_TRANSCODER_C, + HDCP_TRANSCODER_D +}; + +/** + * struct hdcp_port_data - intel specific HDCP port data + * @hdcp_ddi: ddi index as per ME/GSC FW + * @hdcp_transcoder: transcoder index as per ME/GSC FW + * @port_type: HDCP port type as per ME/GSC FW classification + * @protocol: HDCP adaptation as per ME/GSC FW + * @k: No of streams transmitted on a port. Only on DP MST this is != 1 + * @seq_num_m: Count of RepeaterAuth_Stream_Manage msg propagated. + * Initialized to 0 on AKE_INIT. Incremented after every successful + * transmission of RepeaterAuth_Stream_Manage message. When it rolls + * over re-Auth has to be triggered. + * @streams: struct hdcp2_streamid_type[k]. Defines the type and id for the + * streams + */ +struct hdcp_port_data { + enum hdcp_ddi hdcp_ddi; + enum hdcp_transcoder hdcp_transcoder; + u8 port_type; + u8 protocol; + u16 k; + u32 seq_num_m; + struct hdcp2_streamid_type *streams; +}; + +/** + * struct i915_hdcp_ops- ops for HDCP2.2 services. + * @owner: Module providing the ops + * @initiate_hdcp2_session: Initiate a Wired HDCP2.2 Tx Session. + * And Prepare AKE_Init. + * @verify_receiver_cert_prepare_km: Verify the Receiver Certificate + * AKE_Send_Cert and prepare + * AKE_Stored_Km/AKE_No_Stored_Km + * @verify_hprime: Verify AKE_Send_H_prime + * @store_pairing_info: Store pairing info received + * @initiate_locality_check: Prepare LC_Init + * @verify_lprime: Verify lprime + * @get_session_key: Prepare SKE_Send_Eks + * @repeater_check_flow_prepare_ack: Validate the Downstream topology + * and prepare rep_ack + * @verify_mprime: Verify mprime + * @enable_hdcp_authentication: Mark a port as authenticated. + * @close_hdcp_session: Close the Wired HDCP Tx session per port. + * This also disables the authenticated state of the port. + */ +struct i915_hdcp_ops { + /** + * @owner: hdcp module + */ + struct module *owner; + + int (*initiate_hdcp2_session)(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_ake_init *ake_data); + int (*verify_receiver_cert_prepare_km)(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_ake_send_cert + *rx_cert, + bool *km_stored, + struct hdcp2_ake_no_stored_km + *ek_pub_km, + size_t *msg_sz); + int (*verify_hprime)(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_ake_send_hprime *rx_hprime); + int (*store_pairing_info)(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_ake_send_pairing_info + *pairing_info); + int (*initiate_locality_check)(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_lc_init *lc_init_data); + int (*verify_lprime)(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_lc_send_lprime *rx_lprime); + int (*get_session_key)(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_ske_send_eks *ske_data); + int (*repeater_check_flow_prepare_ack)(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_rep_send_receiverid_list + *rep_topology, + struct hdcp2_rep_send_ack + *rep_send_ack); + int (*verify_mprime)(struct device *dev, + struct hdcp_port_data *data, + struct hdcp2_rep_stream_ready *stream_ready); + int (*enable_hdcp_authentication)(struct device *dev, + struct hdcp_port_data *data); + int (*close_hdcp_session)(struct device *dev, + struct hdcp_port_data *data); +}; + +/** + * struct i915_hdcp_arbiter - Used for communication between i915 + * and hdcp drivers for the HDCP2.2 services + */ +struct i915_hdcp_arbiter { + /** + * @hdcp_dev: device that provides the HDCP2.2 service from MEI Bus. + */ + struct device *hdcp_dev; + + /** + * @ops: Ops implemented by hdcp driver or intel_hdcp_gsc, used by i915 + * driver. + */ + const struct i915_hdcp_ops *ops; + + /** + * @mutex: To protect the above members. + */ + struct mutex mutex; +}; + +/* fw_hdcp_status: Enumeration of all HDCP Status Codes */ +enum fw_hdcp_status { + FW_HDCP_STATUS_SUCCESS = 0x0000, + + /* WiDi Generic Status Codes */ + FW_HDCP_STATUS_INTERNAL_ERROR = 0x1000, + FW_HDCP_STATUS_UNKNOWN_ERROR = 0x1001, + FW_HDCP_STATUS_INCORRECT_API_VERSION = 0x1002, + FW_HDCP_STATUS_INVALID_FUNCTION = 0x1003, + FW_HDCP_STATUS_INVALID_BUFFER_LENGTH = 0x1004, + FW_HDCP_STATUS_INVALID_PARAMS = 0x1005, + FW_HDCP_STATUS_AUTHENTICATION_FAILED = 0x1006, + + /* WiDi Status Codes */ + FW_HDCP_INVALID_SESSION_STATE = 0x6000, + FW_HDCP_SRM_FRAGMENT_UNEXPECTED = 0x6001, + FW_HDCP_SRM_INVALID_LENGTH = 0x6002, + FW_HDCP_SRM_FRAGMENT_OFFSET_INVALID = 0x6003, + FW_HDCP_SRM_VERIFICATION_FAILED = 0x6004, + FW_HDCP_SRM_VERSION_TOO_OLD = 0x6005, + FW_HDCP_RX_CERT_VERIFICATION_FAILED = 0x6006, + FW_HDCP_RX_REVOKED = 0x6007, + FW_HDCP_H_VERIFICATION_FAILED = 0x6008, + FW_HDCP_REPEATER_CHECK_UNEXPECTED = 0x6009, + FW_HDCP_TOPOLOGY_MAX_EXCEEDED = 0x600A, + FW_HDCP_V_VERIFICATION_FAILED = 0x600B, + FW_HDCP_L_VERIFICATION_FAILED = 0x600C, + FW_HDCP_STREAM_KEY_ALLOC_FAILED = 0x600D, + FW_HDCP_BASE_KEY_RESET_FAILED = 0x600E, + FW_HDCP_NONCE_GENERATION_FAILED = 0x600F, + FW_HDCP_STATUS_INVALID_E_KEY_STATE = 0x6010, + FW_HDCP_STATUS_INVALID_CS_ICV = 0x6011, + FW_HDCP_STATUS_INVALID_KB_KEY_STATE = 0x6012, + FW_HDCP_STATUS_INVALID_PAVP_MODE_ICV = 0x6013, + FW_HDCP_STATUS_INVALID_PAVP_MODE = 0x6014, + FW_HDCP_STATUS_LC_MAX_ATTEMPTS = 0x6015, + + /* New status for HDCP 2.1 */ + FW_HDCP_STATUS_MISMATCH_IN_M = 0x6016, + + /* New status code for HDCP 2.2 Rx */ + FW_HDCP_STATUS_RX_PROV_NOT_ALLOWED = 0x6017, + FW_HDCP_STATUS_RX_PROV_WRONG_SUBJECT = 0x6018, + FW_HDCP_RX_NEEDS_PROVISIONING = 0x6019, + FW_HDCP_BKSV_ICV_AUTH_FAILED = 0x6020, + FW_HDCP_STATUS_INVALID_STREAM_ID = 0x6021, + FW_HDCP_STATUS_CHAIN_NOT_INITIALIZED = 0x6022, + FW_HDCP_FAIL_NOT_EXPECTED = 0x6023, + FW_HDCP_FAIL_HDCP_OFF = 0x6024, + FW_HDCP_FAIL_INVALID_PAVP_MEMORY_MODE = 0x6025, + FW_HDCP_FAIL_AES_ECB_FAILURE = 0x6026, + FW_HDCP_FEATURE_NOT_SUPPORTED = 0x6027, + FW_HDCP_DMA_READ_ERROR = 0x6028, + FW_HDCP_DMA_WRITE_ERROR = 0x6029, + FW_HDCP_FAIL_INVALID_PACKET_SIZE = 0x6030, + FW_HDCP_H264_PARSING_ERROR = 0x6031, + FW_HDCP_HDCP2_ERRATA_VIDEO_VIOLATION = 0x6032, + FW_HDCP_HDCP2_ERRATA_AUDIO_VIOLATION = 0x6033, + FW_HDCP_TX_ACTIVE_ERROR = 0x6034, + FW_HDCP_MODE_CHANGE_ERROR = 0x6035, + FW_HDCP_STREAM_TYPE_ERROR = 0x6036, + FW_HDCP_STREAM_MANAGE_NOT_POSSIBLE = 0x6037, + + FW_HDCP_STATUS_PORT_INVALID_COMMAND = 0x6038, + FW_HDCP_STATUS_UNSUPPORTED_PROTOCOL = 0x6039, + FW_HDCP_STATUS_INVALID_PORT_INDEX = 0x603a, + FW_HDCP_STATUS_TX_AUTH_NEEDED = 0x603b, + FW_HDCP_STATUS_NOT_INTEGRATED_PORT = 0x603c, + FW_HDCP_STATUS_SESSION_MAX_REACHED = 0x603d, + + /* hdcp capable bit is not set in rx_caps(error is unique to DP) */ + FW_HDCP_STATUS_NOT_HDCP_CAPABLE = 0x6041, + + FW_HDCP_STATUS_INVALID_STREAM_COUNT = 0x6042, +}; + +#define HDCP_API_VERSION 0x00010000 + +#define HDCP_M_LEN 16 +#define HDCP_KH_LEN 16 + +/* Payload Buffer size(Excluding Header) for CMDs and corresponding response */ +/* Wired_Tx_AKE */ +#define WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_IN (4 + 1) +#define WIRED_CMD_BUF_LEN_INITIATE_HDCP2_SESSION_OUT (4 + 8 + 3) + +#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_IN (4 + 522 + 8 + 3) +#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_MIN_OUT (4 + 1 + 3 + 16 + 16) +#define WIRED_CMD_BUF_LEN_VERIFY_RECEIVER_CERT_MAX_OUT (4 + 1 + 3 + 128) + +#define WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_IN (4 + 32) +#define WIRED_CMD_BUF_LEN_AKE_SEND_HPRIME_OUT (4) + +#define WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_IN (4 + 16) +#define WIRED_CMD_BUF_LEN_SEND_PAIRING_INFO_OUT (4) + +#define WIRED_CMD_BUF_LEN_CLOSE_SESSION_IN (4) +#define WIRED_CMD_BUF_LEN_CLOSE_SESSION_OUT (4) + +/* Wired_Tx_LC */ +#define WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_IN (4) +#define WIRED_CMD_BUF_LEN_INIT_LOCALITY_CHECK_OUT (4 + 8) + +#define WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_IN (4 + 32) +#define WIRED_CMD_BUF_LEN_VALIDATE_LOCALITY_OUT (4) + +/* Wired_Tx_SKE */ +#define WIRED_CMD_BUF_LEN_GET_SESSION_KEY_IN (4) +#define WIRED_CMD_BUF_LEN_GET_SESSION_KEY_OUT (4 + 16 + 8) + +/* Wired_Tx_SKE */ +#define WIRED_CMD_BUF_LEN_ENABLE_AUTH_IN (4 + 1) +#define WIRED_CMD_BUF_LEN_ENABLE_AUTH_OUT (4) + +/* Wired_Tx_Repeater */ +#define WIRED_CMD_BUF_LEN_VERIFY_REPEATER_IN (4 + 2 + 3 + 16 + 155) +#define WIRED_CMD_BUF_LEN_VERIFY_REPEATER_OUT (4 + 1 + 16) + +#define WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_MIN_IN (4 + 3 + \ + 32 + 2 + 2) + +#define WIRED_CMD_BUF_LEN_REPEATER_AUTH_STREAM_REQ_OUT (4) + +/* hdcp_command_id: Enumeration of all WIRED HDCP Command IDs */ +enum hdcp_command_id { + _WIDI_COMMAND_BASE = 0x00030000, + WIDI_INITIATE_HDCP2_SESSION = _WIDI_COMMAND_BASE, + HDCP_GET_SRM_STATUS, + HDCP_SEND_SRM_FRAGMENT, + + /* The wired HDCP Tx commands */ + _WIRED_COMMAND_BASE = 0x00031000, + WIRED_INITIATE_HDCP2_SESSION = _WIRED_COMMAND_BASE, + WIRED_VERIFY_RECEIVER_CERT, + WIRED_AKE_SEND_HPRIME, + WIRED_AKE_SEND_PAIRING_INFO, + WIRED_INIT_LOCALITY_CHECK, + WIRED_VALIDATE_LOCALITY, + WIRED_GET_SESSION_KEY, + WIRED_ENABLE_AUTH, + WIRED_VERIFY_REPEATER, + WIRED_REPEATER_AUTH_STREAM_REQ, + WIRED_CLOSE_SESSION, + + _WIRED_COMMANDS_COUNT, +}; + +union encrypted_buff { + u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN]; + u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN]; + struct { + u8 e_kh_km[HDCP_KH_LEN]; + u8 m[HDCP_M_LEN]; + } __packed; +}; + +/* HDCP HECI message header. All header values are little endian. */ +struct hdcp_cmd_header { + u32 api_version; + u32 command_id; + enum fw_hdcp_status status; + /* Length of the HECI message (excluding the header) */ + u32 buffer_len; +} __packed; + +/* Empty command request or response. No data follows the header. */ +struct hdcp_cmd_no_data { + struct hdcp_cmd_header header; +} __packed; + +/* Uniquely identifies the hdcp port being addressed for a given command. */ +struct hdcp_port_id { + u8 integrated_port_type; + /* physical_port is used until Gen11.5. Must be zero for Gen11.5+ */ + u8 physical_port; + /* attached_transcoder is for Gen11.5+. Set to zero for Date: Thu, 30 May 2024 16:19:11 +0300 Subject: MAINTAINERS: update i915 and xe entries for include/drm/intel MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With all the Intel specific drm files under include/drm/intel, update the i915, xe, and the shared display entries. Do not discriminate based on file name pattern, just add the entire directory for all three entries. Cc: Joonas Lahtinen Cc: Lucas De Marchi Cc: Oded Gabbay Cc: Rodrigo Vivi Cc: Thomas Hellström Cc: Tvrtko Ursulin Reviewed-by: Andi Shyti Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/e0fdf28307bb3e457d8c67966c09c44cf7ff5783.1717075103.git.jani.nikula@intel.com --- MAINTAINERS | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 841de2af93f0..dafb1d5b4499 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -10841,6 +10841,7 @@ S: Supported F: drivers/gpu/drm/i915/display/ F: drivers/gpu/drm/xe/display/ F: drivers/gpu/drm/xe/compat-i915-headers +F: include/drm/intel/ INTEL DRM I915 DRIVER (Meteor Lake, DG2 and older excluding Poulsbo, Moorestown and derivative) M: Jani Nikula @@ -10858,7 +10859,7 @@ F: Documentation/ABI/testing/sysfs-driver-intel-i915-hwmon F: Documentation/gpu/i915.rst F: drivers/gpu/drm/ci/xfails/i915* F: drivers/gpu/drm/i915/ -F: include/drm/i915* +F: include/drm/intel/ F: include/uapi/drm/i915_drm.h INTEL DRM XE DRIVER (Lunar Lake and newer) @@ -10875,7 +10876,7 @@ T: git https://gitlab.freedesktop.org/drm/xe/kernel.git F: Documentation/ABI/testing/sysfs-driver-intel-xe-hwmon F: Documentation/gpu/xe/ F: drivers/gpu/drm/xe/ -F: include/drm/xe* +F: include/drm/intel/ F: include/uapi/drm/xe_drm.h INTEL ETHERNET DRIVERS -- cgit From 0e3771f459ad84a286802ee22896f7a64a744f21 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 29 May 2024 12:38:44 +0300 Subject: drm/i915/psr: Add Early Transport status boolean into intel_psr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently we are purely relying on psr2_su_region_et_valid. Add new boolean value into intel_psr struct indicating whether Early Transport is enabled or not and use it instead of psr2_su_region_et_valid for getting Early Transport status information. Reviewed-by: Animesh Manna Signed-off-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-2-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 52d0fd2bdc82..77609656317b 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1706,6 +1706,7 @@ struct intel_psr { bool sel_update_enabled; bool psr2_sel_fetch_enabled; bool psr2_sel_fetch_cff_enabled; + bool su_region_et_enabled; bool req_psr2_sdp_prior_scanline; u8 sink_sync_latency; ktime_t last_entry_attempt; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4b337bcd9c90..410b51f38d48 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -978,7 +978,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) PSR2_MAN_TRK_CTL(dev_priv, cpu_transcoder), 0); } - if (psr2_su_region_et_valid(intel_dp)) + if (intel_dp->psr.su_region_et_enabled) val |= LNL_EDP_PSR2_SU_REGION_ET_ENABLE; /* @@ -1771,6 +1771,7 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp, intel_dp->psr.dc3co_exit_delay = val; intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline; intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch; + intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; intel_dp->psr.req_psr2_sdp_prior_scanline = crtc_state->req_psr2_sdp_prior_scanline; @@ -1927,6 +1928,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) intel_dp->psr.panel_replay_enabled = false; intel_dp->psr.sel_update_enabled = false; intel_dp->psr.psr2_sel_fetch_enabled = false; + intel_dp->psr.su_region_et_enabled = false; intel_dp->psr.psr2_sel_fetch_cff_enabled = false; } -- cgit From 13d1359d67485c220832594fa044436992597823 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 29 May 2024 12:38:45 +0300 Subject: drm/i915/psr: Get Early Transport status in intel_psr_pipe_get_config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are currently not getting Early Transport status information in intel_psr_pipe_get_config. Fix this. Reviewed-by: Animesh Manna Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") Signed-off-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-3-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 410b51f38d48..73966d011f7b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1525,6 +1525,8 @@ void intel_psr_get_config(struct intel_encoder *encoder, pipe_config->enable_psr2_sel_fetch = true; } + pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled; + if (DISPLAY_VER(dev_priv) >= 12) { val = intel_de_read(dev_priv, TRANS_EXITLINE(dev_priv, cpu_transcoder)); -- cgit From 0a8c581ce01c84214b8221fcc5d52b45c09d0007 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 29 May 2024 12:38:46 +0300 Subject: drm/i915/psr: Use enable boolean from intel_crtc_state for Early Transport MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When enabling Early Transport use intel_crtc_state->enable_psr2_su_region_et instead of psr2_su_region_et_valid. Reviewed-by: Animesh Manna Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible") Signed-off-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-4-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 73966d011f7b..c9c657fca048 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -710,7 +710,7 @@ void intel_psr_enable_sink(struct intel_dp *intel_dp, DP_ALPM_ENABLE | DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); - if (psr2_su_region_et_valid(intel_dp)) + if (crtc_state->enable_psr2_su_region_et) dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET; } -- cgit From 16b65af8b746ca6af74fd45156e755f2c8fa2379 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 29 May 2024 12:38:47 +0300 Subject: drm/i915/display: Selective fetch Y position on Region Early Transport MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Selective fetch Y position differs when Region Early Transport is used. Use formula from Bspec for this. Bspec: 68927 Reviewed-by: Animesh Manna Signed-off-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-5-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/skl_universal_plane.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index b7678b8a7f3d..1aa70fc35b9d 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -1302,7 +1302,11 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane, clip = &plane_state->psr2_sel_fetch_area; - val = (clip->y1 + plane_state->uapi.dst.y1) << 16; + if (crtc_state->enable_psr2_su_region_et) + y = max(0, plane_state->uapi.dst.y1 - crtc_state->psr2_su_area.y1); + else + y = (clip->y1 + plane_state->uapi.dst.y1); + val = y << 16; val |= plane_state->uapi.dst.x1; intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val); -- cgit From 04d0aed08206a235470ca82c08f46aa7b73e97fc Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 29 May 2024 12:38:48 +0300 Subject: drm/i915/psr: Allow setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE via debugfs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently setting I915_PSR_DEBUG_SU_REGION_ET_DISABLE (0x20) via psr_debug debugfs interface is not allowed. This patch allows it. v3: - ensure psr is disabled/enabled if enable_psr2_su_region_et changes - remove extra space v2: ensure that fastset is performed when the bit changes Reviewed-by: Animesh Manna Signed-off-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-6-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c9c657fca048..b6162a8b2db6 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2494,12 +2494,15 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, * - PSR disabled in new state * - All planes will go inactive * - Changing between PSR versions + * - Region Early Transport changing * - Display WA #1136: skl, bxt */ needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); needs_to_disable |= !new_crtc_state->has_psr; needs_to_disable |= !new_crtc_state->active_planes; needs_to_disable |= new_crtc_state->has_sel_update != psr->sel_update_enabled; + needs_to_disable |= new_crtc_state->enable_psr2_su_region_et != + psr->su_region_et_enabled; needs_to_disable |= DISPLAY_VER(i915) < 11 && new_crtc_state->wm_level_disabled; @@ -2735,10 +2738,12 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; - u32 old_mode; + const u32 disable_bits = val & I915_PSR_DEBUG_SU_REGION_ET_DISABLE; + u32 old_mode, old_disable_bits; int ret; - if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_MODE_MASK) || + if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | + I915_PSR_DEBUG_MODE_MASK) || mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); return -EINVAL; @@ -2749,6 +2754,8 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) return ret; old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; + old_disable_bits = intel_dp->psr.debug & + I915_PSR_DEBUG_SU_REGION_ET_DISABLE; intel_dp->psr.debug = val; /* @@ -2760,7 +2767,7 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) mutex_unlock(&intel_dp->psr.lock); - if (old_mode != mode) + if (old_mode != mode || old_disable_bits != disable_bits) ret = intel_psr_fastset_force(dev_priv); return ret; -- cgit From b330568f0c51b0b80e463841b0062206011a4746 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Wed, 29 May 2024 12:38:49 +0300 Subject: drm/i915/psr: Add Early Transport into psr debugfs interface MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We want to have sink Early Transport capability and usage in our psr debugfs status interface. v4: use su_region_et_enabled instead of psr2_su_region_et_valid v3: remove extra space from "PSR mode: disabled" v2: printout "Selective Update enabled (Early Transport)" instead of "Selective Update Early Transport enabled" Reviewed-by: Animesh Manna Signed-off-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240529093849.1016172-7-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 35 ++++++++++++++++++++++++-------- 1 file changed, 27 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b6162a8b2db6..4a4124a92a0d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3332,25 +3332,44 @@ static void intel_psr_sink_capability(struct intel_dp *intel_dp, if (psr->sink_support) seq_printf(m, " [0x%02x]", intel_dp->psr_dpcd[0]); + if (intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED) + seq_printf(m, " (Early Transport)"); seq_printf(m, ", Panel Replay = %s", str_yes_no(psr->sink_panel_replay_support)); - seq_printf(m, ", Panel Replay Selective Update = %s\n", + seq_printf(m, ", Panel Replay Selective Update = %s", str_yes_no(psr->sink_panel_replay_su_support)); + if (intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT) + seq_printf(m, " (Early Transport)"); + seq_printf(m, "\n"); } static void intel_psr_print_mode(struct intel_dp *intel_dp, struct seq_file *m) { struct intel_psr *psr = &intel_dp->psr; - const char *status; + const char *status, *mode, *region_et; - if (psr->panel_replay_enabled) - status = psr->sel_update_enabled ? "Panel Replay Selective Update Enabled" : - "Panel Replay Enabled"; - else if (psr->enabled) - status = psr->sel_update_enabled ? "PSR2" : "PSR1"; + if (psr->enabled) + status = " enabled"; else status = "disabled"; - seq_printf(m, "PSR mode: %s\n", status); + + if (psr->panel_replay_enabled && psr->sel_update_enabled) + mode = "Panel Replay Selective Update"; + else if (psr->panel_replay_enabled) + mode = "Panel Replay"; + else if (psr->sel_update_enabled) + mode = "PSR2"; + else if (psr->enabled) + mode = "PSR1"; + else + mode = ""; + + if (psr->su_region_et_enabled) + region_et = " (Early Transport)"; + else + region_et = ""; + + seq_printf(m, "PSR mode: %s%s%s\n", mode, status, region_et); } static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) -- cgit From 30ca6365bb4200f55e59bf1ab2a24e65406e9eac Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Thu, 30 May 2024 13:53:12 +0300 Subject: drm/i915: Fix assert on pending async-put power domain work when it requeues itself MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit dd839aa857eb ("drm/i915: Fix incorrect assert about pending power domain async-put work") fixed the assert about a pending work dropping a display power reference asynchronously, leading to the drm_WARN_ON(!queue_delayed_work(&power_domains->async_put_work)); warn next time around a power reference was put asynchronously, due to a stale instance of the work still being pending. However the fix didn't consider the case where multiple power reference was acquired and put, requiring the work to requeue itself. Extend the fix for this case as well canceling the pending instance of the work before it requeues itself. Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10915 Signed-off-by: Imre Deak Reviewed-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240530105312.1016485-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display_power.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 34b6d843bc9e..8c49ac053dfb 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -675,6 +675,12 @@ intel_display_power_put_async_work(struct work_struct *work) release_async_put_domains(power_domains, &power_domains->async_put_domains[0]); + /* + * Cancel the work that got queued after this one got dequeued, + * since here we released the corresponding async-put reference. + */ + cancel_async_put_work(power_domains, false); + /* Requeue the work if more domains were async put meanwhile. */ if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) { bitmap_copy(power_domains->async_put_domains[0].bits, @@ -686,12 +692,6 @@ intel_display_power_put_async_work(struct work_struct *work) fetch_and_zero(&new_work_wakeref), power_domains->async_put_next_delay); power_domains->async_put_next_delay = 0; - } else { - /* - * Cancel the work that got queued after this one got dequeued, - * since here we released the corresponding async-put reference. - */ - cancel_async_put_work(power_domains, false); } out_verify: -- cgit From 7f57f21510de2c76596af7a51804e6f1abc0be00 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:40:58 +0300 Subject: drm/i915/dsb: Polish the DSB ID enum MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Namespace the DSB ID enum properly, and make the naming match other such enums in general. Also make the names 0 based as that's what Bspec uses for DSB (unlike eg. planes where it uses 1 based indexing). We'll throw out INVALID_DSB while at it since we have no use for it at the moment. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531114101.19994-2-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/intel_dsb.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index bdc53b7ad592..2be46f4ffc27 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -18,16 +18,16 @@ #define CACHELINE_BYTES 64 -enum dsb_id { - INVALID_DSB = -1, - DSB1, - DSB2, - DSB3, - MAX_DSB_PER_PIPE +enum intel_dsb_id { + INTEL_DSB_0, + INTEL_DSB_1, + INTEL_DSB_2, + + I915_MAX_DSBS, }; struct intel_dsb { - enum dsb_id id; + enum intel_dsb_id id; struct intel_dsb_buffer dsb_buf; struct intel_crtc *crtc; @@ -120,9 +120,9 @@ static void intel_dsb_dump(struct intel_dsb *dsb) } static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, - enum dsb_id id) + enum intel_dsb_id dsb_id) { - return intel_de_read_fw(i915, DSB_CTRL(pipe, id)) & DSB_STATUS_BUSY; + return intel_de_read_fw(i915, DSB_CTRL(pipe, dsb_id)) & DSB_STATUS_BUSY; } static void intel_dsb_emit(struct intel_dsb *dsb, u32 ldw, u32 udw) @@ -481,7 +481,7 @@ struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, intel_runtime_pm_put(&i915->runtime_pm, wakeref); - dsb->id = DSB1; + dsb->id = INTEL_DSB_0; dsb->crtc = crtc; dsb->size = size / 4; /* in dwords */ dsb->free_pos = 0; @@ -496,7 +496,7 @@ out_put_rpm: out: drm_info_once(&i915->drm, "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to MMIO for display HW programming\n", - crtc->base.base.id, crtc->base.name, DSB1); + crtc->base.base.id, crtc->base.name, INTEL_DSB_0); return NULL; } -- cgit From 738f3d86182ed5f6d09205db6f0ba3c498c20d69 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:40:59 +0300 Subject: drm/i915/dsb: Move DSB ID definition to the header MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We're going to need to make the DSB ID visible outside the DSB code, so that we eg. can use multiple DSB engines in parallel. to that end move the definition to intel_dsb.h. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531114101.19994-3-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/intel_dsb.c | 8 -------- drivers/gpu/drm/i915/display/intel_dsb.h | 8 ++++++++ 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 2be46f4ffc27..75ac780d66bf 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -18,14 +18,6 @@ #define CACHELINE_BYTES 64 -enum intel_dsb_id { - INTEL_DSB_0, - INTEL_DSB_1, - INTEL_DSB_2, - - I915_MAX_DSBS, -}; - struct intel_dsb { enum intel_dsb_id id; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 16d80f434356..5d7561ea65fa 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -14,6 +14,14 @@ struct intel_crtc; struct intel_crtc_state; struct intel_dsb; +enum intel_dsb_id { + INTEL_DSB_0, + INTEL_DSB_1, + INTEL_DSB_2, + + I915_MAX_DSBS, +}; + struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, unsigned int max_cmds); void intel_dsb_finish(struct intel_dsb *dsb); -- cgit From 81d604f44b1880a278197a4d076bddc83e763af5 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:41:00 +0300 Subject: drm/i915/dsb: Pass DSB engine ID to intel_dsb_prepare() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Allow the caller of intel_dsb_prepare() to determine which DSB engine (out of the three possible per pipe) to use. This will let us utilize multiple DSB engines during the same commit. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531114101.19994-4-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/intel_color.c | 2 +- drivers/gpu/drm/i915/display/intel_dsb.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_dsb.h | 1 + 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 9173caba3f0f..98553e8a5149 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1914,7 +1914,7 @@ void intel_color_prepare_commit(struct intel_crtc_state *crtc_state) if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut) return; - crtc_state->dsb = intel_dsb_prepare(crtc_state, 1024); + crtc_state->dsb = intel_dsb_prepare(crtc_state, INTEL_DSB_0, 1024); if (!crtc_state->dsb) return; diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 75ac780d66bf..5180b9722046 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -435,6 +435,7 @@ void intel_dsb_wait(struct intel_dsb *dsb) /** * intel_dsb_prepare() - Allocate, pin and map the DSB command buffer. * @crtc_state: the CRTC state + * @dsb_id: the DSB engine to use * @max_cmds: number of commands we need to fit into command buffer * * This function prepare the command buffer which is used to store dsb @@ -444,6 +445,7 @@ void intel_dsb_wait(struct intel_dsb *dsb) * DSB context, NULL on failure */ struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, + enum intel_dsb_id dsb_id, unsigned int max_cmds) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); @@ -473,7 +475,7 @@ struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, intel_runtime_pm_put(&i915->runtime_pm, wakeref); - dsb->id = INTEL_DSB_0; + dsb->id = dsb_id; dsb->crtc = crtc; dsb->size = size / 4; /* in dwords */ dsb->free_pos = 0; @@ -488,7 +490,7 @@ out_put_rpm: out: drm_info_once(&i915->drm, "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to MMIO for display HW programming\n", - crtc->base.base.id, crtc->base.name, INTEL_DSB_0); + crtc->base.base.id, crtc->base.name, dsb_id); return NULL; } diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h index 5d7561ea65fa..36fdb130af6e 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.h +++ b/drivers/gpu/drm/i915/display/intel_dsb.h @@ -23,6 +23,7 @@ enum intel_dsb_id { }; struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, + enum intel_dsb_id dsb_id, unsigned int max_cmds); void intel_dsb_finish(struct intel_dsb *dsb); void intel_dsb_cleanup(struct intel_dsb *dsb); -- cgit From 8b329d74fb6dbc920c17185a36089b3b7f4f64e1 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:41:01 +0300 Subject: drm/i915/dsb: Use intel_color_uses_dsb() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use intel_color_uses_dsb() instead of open coding it in intel_vblank_evade_init(). Make the logic around DSB a bit more isolated from the rest of the code. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531114101.19994-5-ville.syrjala@linux.intel.com Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/intel_vblank.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index eb80952b0cfd..789b2db4d95e 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -5,6 +5,7 @@ #include "i915_drv.h" #include "i915_reg.h" +#include "intel_color.h" #include "intel_crtc.h" #include "intel_de.h" #include "intel_display_types.h" @@ -637,7 +638,8 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, * DSB execution waits for the transcoder's undelayed vblank, * hence we must kick off the commit before that. */ - if (new_crtc_state->dsb || new_crtc_state->update_m_n || new_crtc_state->update_lrr) + if (intel_color_uses_dsb(new_crtc_state) || + new_crtc_state->update_m_n || new_crtc_state->update_lrr) evade->min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay; } -- cgit From ccb6ba9eba6f267e4ca3689152ddedb6351f673b Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:53:36 +0300 Subject: drm/i915: Extract intel_pipe_crc_regs.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The CRC registers are a pretty self contained bunch. Extract them to a separate header to declutter i915_reg.h. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 1 + drivers/gpu/drm/i915/display/intel_pipe_crc.c | 1 + drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 92 ++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 81 ------------------- 4 files changed, 94 insertions(+), 81 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 1674570dff1e..9c12cc0f2ed0 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -18,6 +18,7 @@ #include "intel_fifo_underrun.h" #include "intel_gmbus.h" #include "intel_hotplug_irq.h" +#include "intel_pipe_crc_regs.h" #include "intel_pmdemand.h" #include "intel_psr.h" #include "intel_psr_regs.h" diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc.c b/drivers/gpu/drm/i915/display/intel_pipe_crc.c index b3dcfee6ec0e..82ceede0b2b1 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc.c +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc.c @@ -34,6 +34,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_pipe_crc.h" +#include "intel_pipe_crc_regs.h" static const char * const pipe_crc_sources[] = { [INTEL_PIPE_CRC_SOURCE_NONE] = "none", diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h new file mode 100644 index 000000000000..e684bc9ae1c0 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_PIPE_CRC_REGS_H__ +#define __INTEL_PIPE_CRC_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* Pipe A CRC regs */ +#define _PIPE_CRC_CTL_A 0x60050 +#define PIPE_CRC_ENABLE REG_BIT(31) +/* skl+ source selection */ +#define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) +#define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) +#define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) +#define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) +#define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) +#define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) +#define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) +#define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) +#define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) +/* ivb+ source selection */ +#define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) +#define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) +#define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) +#define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) +/* ilk+ source selection */ +#define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) +#define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) +#define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) +#define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) +/* embedded DP port on the north display block */ +#define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) +#define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) +/* vlv source selection */ +#define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) +#define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) +#define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) +#define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) +/* with DP port the pipe source is invalid */ +#define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) +#define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) +#define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) +/* gen3+ source selection */ +#define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) +#define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) +#define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) +#define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) +/* with DP/TV port the pipe source is invalid */ +#define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) +#define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) +#define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) +#define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) +#define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) +/* gen2 doesn't have source selection bits */ +#define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) + +#define _PIPE_CRC_RES_1_A_IVB 0x60064 +#define _PIPE_CRC_RES_2_A_IVB 0x60068 +#define _PIPE_CRC_RES_3_A_IVB 0x6006c +#define _PIPE_CRC_RES_4_A_IVB 0x60070 +#define _PIPE_CRC_RES_5_A_IVB 0x60074 + +#define _PIPE_CRC_RES_RED_A 0x60060 +#define _PIPE_CRC_RES_GREEN_A 0x60064 +#define _PIPE_CRC_RES_BLUE_A 0x60068 +#define _PIPE_CRC_RES_RES1_A_I915 0x6006c +#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 + +/* Pipe B CRC regs */ +#define _PIPE_CRC_RES_1_B_IVB 0x61064 +#define _PIPE_CRC_RES_2_B_IVB 0x61068 +#define _PIPE_CRC_RES_3_B_IVB 0x6106c +#define _PIPE_CRC_RES_4_B_IVB 0x61070 +#define _PIPE_CRC_RES_5_B_IVB 0x61074 + +#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) +#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) +#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) +#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) +#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) +#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) + +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) +#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) + +#endif /* __INTEL_PIPE_CRC_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6877e2f0fbc3..0569a23b83b2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1069,87 +1069,6 @@ * Display engine regs */ -/* Pipe A CRC regs */ -#define _PIPE_CRC_CTL_A 0x60050 -#define PIPE_CRC_ENABLE REG_BIT(31) -/* skl+ source selection */ -#define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) -#define PIPE_CRC_SOURCE_PLANE_1_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 0) -#define PIPE_CRC_SOURCE_PLANE_2_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 2) -#define PIPE_CRC_SOURCE_DMUX_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 4) -#define PIPE_CRC_SOURCE_PLANE_3_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 6) -#define PIPE_CRC_SOURCE_PLANE_4_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 7) -#define PIPE_CRC_SOURCE_PLANE_5_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 5) -#define PIPE_CRC_SOURCE_PLANE_6_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 3) -#define PIPE_CRC_SOURCE_PLANE_7_SKL REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_SKL, 1) -/* ivb+ source selection */ -#define PIPE_CRC_SOURCE_MASK_IVB REG_GENMASK(30, 29) -#define PIPE_CRC_SOURCE_PRIMARY_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 0) -#define PIPE_CRC_SOURCE_SPRITE_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 1) -#define PIPE_CRC_SOURCE_PF_IVB REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_IVB, 2) -/* ilk+ source selection */ -#define PIPE_CRC_SOURCE_MASK_ILK REG_GENMASK(30, 28) -#define PIPE_CRC_SOURCE_PRIMARY_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 0) -#define PIPE_CRC_SOURCE_SPRITE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 1) -#define PIPE_CRC_SOURCE_PIPE_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 2) -/* embedded DP port on the north display block */ -#define PIPE_CRC_SOURCE_PORT_A_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 4) -#define PIPE_CRC_SOURCE_FDI_ILK REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_ILK, 5) -/* vlv source selection */ -#define PIPE_CRC_SOURCE_MASK_VLV REG_GENMASK(30, 27) -#define PIPE_CRC_SOURCE_PIPE_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 0) -#define PIPE_CRC_SOURCE_HDMIB_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 1) -#define PIPE_CRC_SOURCE_HDMIC_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 2) -/* with DP port the pipe source is invalid */ -#define PIPE_CRC_SOURCE_DP_D_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 3) -#define PIPE_CRC_SOURCE_DP_B_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 6) -#define PIPE_CRC_SOURCE_DP_C_VLV REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_VLV, 7) -/* gen3+ source selection */ -#define PIPE_CRC_SOURCE_MASK_I9XX REG_GENMASK(30, 28) -#define PIPE_CRC_SOURCE_PIPE_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 0) -#define PIPE_CRC_SOURCE_SDVOB_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 1) -#define PIPE_CRC_SOURCE_SDVOC_I9XX REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 2) -/* with DP/TV port the pipe source is invalid */ -#define PIPE_CRC_SOURCE_DP_D_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 3) -#define PIPE_CRC_SOURCE_TV_PRE REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 4) -#define PIPE_CRC_SOURCE_TV_POST REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 5) -#define PIPE_CRC_SOURCE_DP_B_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 6) -#define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) -/* gen2 doesn't have source selection bits */ -#define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) - -#define _PIPE_CRC_RES_1_A_IVB 0x60064 -#define _PIPE_CRC_RES_2_A_IVB 0x60068 -#define _PIPE_CRC_RES_3_A_IVB 0x6006c -#define _PIPE_CRC_RES_4_A_IVB 0x60070 -#define _PIPE_CRC_RES_5_A_IVB 0x60074 - -#define _PIPE_CRC_RES_RED_A 0x60060 -#define _PIPE_CRC_RES_GREEN_A 0x60064 -#define _PIPE_CRC_RES_BLUE_A 0x60068 -#define _PIPE_CRC_RES_RES1_A_I915 0x6006c -#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 - -/* Pipe B CRC regs */ -#define _PIPE_CRC_RES_1_B_IVB 0x61064 -#define _PIPE_CRC_RES_2_B_IVB 0x61068 -#define _PIPE_CRC_RES_3_B_IVB 0x6106c -#define _PIPE_CRC_RES_4_B_IVB 0x61070 -#define _PIPE_CRC_RES_5_B_IVB 0x61074 - -#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) -#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) -#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) -#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) -#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) -#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) - -#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) -#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) -#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) -#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) -#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) - /* Pipe/transcoder A timing regs */ #define _TRANS_HTOTAL_A 0x60000 #define HTOTAL_MASK REG_GENMASK(31, 16) -- cgit From 1c1bfd8b0b7ccf1d82b531875f13e35d7f96e086 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:53:37 +0300 Subject: drm/i915: Switch PIPE_CRC_RES_*_IVB to _MMIO_PIPE() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PIPE_CRC_RES_*_IVB are proper pipe registers, and only valid for IVB+ where pipe register blocks are equally spaced, so we can switch from _MMIO_TRANS2() to the simpler _MMIO_PIPE() for these. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 12 ++++++------ drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 10 +++++----- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 9c12cc0f2ed0..7db87dfcb12a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -357,7 +357,7 @@ static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), 0, 0, 0, 0); } @@ -365,11 +365,11 @@ static void ivb_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(dev_priv, pipe)), - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(dev_priv, pipe))); + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_2_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_3_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_4_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_5_IVB(pipe))); } static void i9xx_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index e684bc9ae1c0..66520c97bf1e 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -77,11 +77,11 @@ #define _PIPE_CRC_RES_5_B_IVB 0x61074 #define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) -#define PIPE_CRC_RES_1_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) -#define PIPE_CRC_RES_2_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) -#define PIPE_CRC_RES_3_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) -#define PIPE_CRC_RES_4_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) -#define PIPE_CRC_RES_5_IVB(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) +#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) +#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) +#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) +#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) +#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) #define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) -- cgit From 1ec6defe71ee8ecab72399a29f258c12f826c8df Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:53:38 +0300 Subject: drm/i915: Regroup pipe CRC regs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Put all the definitions related to a single pipe CRC register in one place, instead of the current approach where things are spread all over the place. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 43 ++++++++++++---------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index 66520c97bf1e..a1217a4d6f2e 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -8,8 +8,8 @@ #include "intel_display_reg_defs.h" -/* Pipe A CRC regs */ #define _PIPE_CRC_CTL_A 0x60050 +#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) #define PIPE_CRC_ENABLE REG_BIT(31) /* skl+ source selection */ #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) @@ -57,36 +57,39 @@ /* gen2 doesn't have source selection bits */ #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) -#define _PIPE_CRC_RES_1_A_IVB 0x60064 -#define _PIPE_CRC_RES_2_A_IVB 0x60068 -#define _PIPE_CRC_RES_3_A_IVB 0x6006c -#define _PIPE_CRC_RES_4_A_IVB 0x60070 -#define _PIPE_CRC_RES_5_A_IVB 0x60074 - #define _PIPE_CRC_RES_RED_A 0x60060 +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) + #define _PIPE_CRC_RES_GREEN_A 0x60064 +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) + #define _PIPE_CRC_RES_BLUE_A 0x60068 +#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) + #define _PIPE_CRC_RES_RES1_A_I915 0x6006c +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) + #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) -/* Pipe B CRC regs */ +#define _PIPE_CRC_RES_1_A_IVB 0x60064 #define _PIPE_CRC_RES_1_B_IVB 0x61064 -#define _PIPE_CRC_RES_2_B_IVB 0x61068 -#define _PIPE_CRC_RES_3_B_IVB 0x6106c -#define _PIPE_CRC_RES_4_B_IVB 0x61070 -#define _PIPE_CRC_RES_5_B_IVB 0x61074 - -#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) + +#define _PIPE_CRC_RES_2_A_IVB 0x60068 +#define _PIPE_CRC_RES_2_B_IVB 0x61068 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) + +#define _PIPE_CRC_RES_3_A_IVB 0x6006c +#define _PIPE_CRC_RES_3_B_IVB 0x6106c #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) + +#define _PIPE_CRC_RES_4_A_IVB 0x60070 +#define _PIPE_CRC_RES_4_B_IVB 0x61070 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) -#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) -#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) -#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) -#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) -#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) -#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) +#define _PIPE_CRC_RES_5_A_IVB 0x60074 +#define _PIPE_CRC_RES_5_B_IVB 0x61074 +#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) #endif /* __INTEL_PIPE_CRC_REGS_H__ */ -- cgit From 7bd7cfa83359d7204b5c479f91f03bc153d69832 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:53:39 +0300 Subject: drm/i915: Add a separate definition for PIPE_CRC_RES_HSW MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On hsw+ we only have one CRC result register, instead of the five we have on ivb, and some of the others have been repurposed to serve other CRC related purposes. Since the hsw+ vs. pre-hsw register operate quite differently let's add a separate definition for the hsw+ variant to make the situation a bit more clear. Also since we only use this from a hsw+ codepath there is no real benefit to be had with reusing the ivb register definition. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 7db87dfcb12a..d2d70b81aef9 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -357,7 +357,7 @@ static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv, enum pipe pipe) { display_pipe_crc_irq_handler(dev_priv, pipe, - intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_1_IVB(pipe)), + intel_uncore_read(&dev_priv->uncore, PIPE_CRC_RES_HSW(pipe)), 0, 0, 0, 0); } diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index a1217a4d6f2e..d06ff3516dbc 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -92,4 +92,9 @@ #define _PIPE_CRC_RES_5_B_IVB 0x61074 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) +/* hsw+ */ +#define _PIPE_CRC_RES_A_HSW 0x60064 +#define _PIPE_CRC_RES_B_HSW 0x61064 +#define PIPE_CRC_RES_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW) + #endif /* __INTEL_PIPE_CRC_REGS_H__ */ -- cgit From 31951bbe3e9f9399bf903cc68a2c0c7eedbb26b7 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:53:40 +0300 Subject: drm/i915: Document which platforms have which CRC registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sprinkle some comments around to indicate which CRC registers are valid for which platforms. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index d06ff3516dbc..4f4bf51e1940 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -66,28 +66,33 @@ #define _PIPE_CRC_RES_BLUE_A 0x60068 #define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) -#define _PIPE_CRC_RES_RES1_A_I915 0x6006c +#define _PIPE_CRC_RES_RES1_A_I915 0x6006c /* i915+ */ #define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) -#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 +#define _PIPE_CRC_RES_RES2_A_G4X 0x60080 /* g4x+ */ #define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) +/* ivb */ #define _PIPE_CRC_RES_1_A_IVB 0x60064 #define _PIPE_CRC_RES_1_B_IVB 0x61064 #define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) +/* ivb */ #define _PIPE_CRC_RES_2_A_IVB 0x60068 #define _PIPE_CRC_RES_2_B_IVB 0x61068 #define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) +/* ivb */ #define _PIPE_CRC_RES_3_A_IVB 0x6006c #define _PIPE_CRC_RES_3_B_IVB 0x6106c #define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) +/* ivb */ #define _PIPE_CRC_RES_4_A_IVB 0x60070 #define _PIPE_CRC_RES_4_B_IVB 0x61070 #define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) +/* ivb */ #define _PIPE_CRC_RES_5_A_IVB 0x60074 #define _PIPE_CRC_RES_5_B_IVB 0x61074 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) -- cgit From fddb9fa961a1ba5ddf0e076df3374137906ca48a Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:53:41 +0300 Subject: drm/i915: Define the PIPE_CRC_EXP registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit I need a scratch register which fill the following requirements: - can be accessed via DSB - all the bits can be read/written - no serious side effects So far the only thing I could think of is the "expected CRC" register. Add the definition so I can use it. While I only need the hsw+ variant currently, let's define the older variants as well for completeness. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-7-ville.syrjala@linux.intel.com Acked-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index 4f4bf51e1940..383910a785f6 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -56,6 +56,24 @@ #define PIPE_CRC_SOURCE_DP_C_G4X REG_FIELD_PREP(PIPE_CRC_SOURCE_MASK_I9XX, 7) /* gen2 doesn't have source selection bits */ #define PIPE_CRC_INCLUDE_BORDER_I8XX REG_BIT(30) +#define PIPE_CRC_EXP_RED_MASK REG_BIT(22, 0) /* pre-ivb */ +#define PIPE_CRC_EXP_1_MASK_IVB REG_BIT(22, 0) /* ivb */ + +#define _PIPE_CRC_EXP_GREEN_A 0x60054 +#define PIPE_CRC_EXP_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_GREEN_A) +#define PIPE_CRC_EXP_GREEN_MASK REG_BIT(22, 0) /* pre-ivb */ + +#define _PIPE_CRC_EXP_BLUE_A 0x60058 +#define PIPE_CRC_EXP_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_BLUE_A) +#define PIPE_CRC_EXP_BLUE_MASK REG_BIT(22, 0) /* pre-ivb */ + +#define _PIPE_CRC_EXP_RES1_A_I915 0x6005c /* i915+ */ +#define PIPE_CRC_EXP_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES1_A_I915) +#define PIPE_CRC_EXP_RES1_MASK REG_BIT(22, 0) /* pre-ivb */ + +#define _PIPE_CRC_EXP_RES2_A_G4X 0x60080 /* g4x+ */ +#define PIPE_CRC_EXP_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_EXP_RES2_A_G4X) +#define PIPE_CRC_EXP_RES2_MASK REG_BIT(22, 0) /* pre-ivb */ #define _PIPE_CRC_RES_RED_A 0x60060 #define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) @@ -72,6 +90,30 @@ #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 /* g4x+ */ #define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) +/* ivb */ +#define _PIPE_CRC_EXP_2_A_IVB 0x60054 +#define _PIPE_CRC_EXP_2_B_IVB 0x61054 +#define PIPE_CRC_EXP_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB) +#define PIPE_CRC_EXP_2_MASK_IVB REG_BIT(22, 0) /* ivb */ + +/* ivb */ +#define _PIPE_CRC_EXP_3_A_IVB 0x60058 +#define _PIPE_CRC_EXP_3_B_IVB 0x61058 +#define PIPE_CRC_EXP_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_3_A_IVB, _PIPE_CRC_EXP_3_B_IVB) +#define PIPE_CRC_EXP_3_MASK_IVB REG_BIT(22, 0) /* ivb */ + +/* ivb */ +#define _PIPE_CRC_EXP_4_A_IVB 0x6005c +#define _PIPE_CRC_EXP_4_B_IVB 0x6105c +#define PIPE_CRC_EXP_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB) +#define PIPE_CRC_EXP_4_MASK_IVB REG_BIT(22, 0) /* ivb */ + +/* ivb */ +#define _PIPE_CRC_EXP_5_A_IVB 0x60060 +#define _PIPE_CRC_EXP_5_B_IVB 0x61060 +#define PIPE_CRC_EXP_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_2_A_IVB, _PIPE_CRC_EXP_2_B_IVB) +#define PIPE_CRC_EXP_5_MASK_IVB REG_BIT(22, 0) /* ivb */ + /* ivb */ #define _PIPE_CRC_RES_1_A_IVB 0x60064 #define _PIPE_CRC_RES_1_B_IVB 0x61064 @@ -97,6 +139,11 @@ #define _PIPE_CRC_RES_5_B_IVB 0x61074 #define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) +/* hsw+ */ +#define _PIPE_CRC_EXP_A_HSW 0x60054 +#define _PIPE_CRC_EXP_B_HSW 0x61054 +#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW) + /* hsw+ */ #define _PIPE_CRC_RES_A_HSW 0x60064 #define _PIPE_CRC_RES_B_HSW 0x61064 -- cgit From 17419f5c6d409bcce5d094279a6fed5d5dbdba12 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 31 May 2024 14:53:42 +0300 Subject: drm/i915: Protect CRC reg macro arguments for consistency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's probably a good idea to start protecting all macro arguments to avoid any cargo-cult mistakes when people go looking for examples of how to define these things. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h | 26 +++++++++++----------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h index 383910a785f6..4e65f51d34e6 100644 --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h @@ -9,7 +9,7 @@ #include "intel_display_reg_defs.h" #define _PIPE_CRC_CTL_A 0x60050 -#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) +#define PIPE_CRC_CTL(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A) #define PIPE_CRC_ENABLE REG_BIT(31) /* skl+ source selection */ #define PIPE_CRC_SOURCE_MASK_SKL REG_GENMASK(30, 28) @@ -76,19 +76,19 @@ #define PIPE_CRC_EXP_RES2_MASK REG_BIT(22, 0) /* pre-ivb */ #define _PIPE_CRC_RES_RED_A 0x60060 -#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) +#define PIPE_CRC_RES_RED(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A) #define _PIPE_CRC_RES_GREEN_A 0x60064 -#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) +#define PIPE_CRC_RES_GREEN(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A) #define _PIPE_CRC_RES_BLUE_A 0x60068 -#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) +#define PIPE_CRC_RES_BLUE(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A) #define _PIPE_CRC_RES_RES1_A_I915 0x6006c /* i915+ */ -#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915) #define _PIPE_CRC_RES_RES2_A_G4X 0x60080 /* g4x+ */ -#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe) _MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X) /* ivb */ #define _PIPE_CRC_EXP_2_A_IVB 0x60054 @@ -117,36 +117,36 @@ /* ivb */ #define _PIPE_CRC_RES_1_A_IVB 0x60064 #define _PIPE_CRC_RES_1_B_IVB 0x61064 -#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) +#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB) /* ivb */ #define _PIPE_CRC_RES_2_A_IVB 0x60068 #define _PIPE_CRC_RES_2_B_IVB 0x61068 -#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) +#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB) /* ivb */ #define _PIPE_CRC_RES_3_A_IVB 0x6006c #define _PIPE_CRC_RES_3_B_IVB 0x6106c -#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) +#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB) /* ivb */ #define _PIPE_CRC_RES_4_A_IVB 0x60070 #define _PIPE_CRC_RES_4_B_IVB 0x61070 -#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) +#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB) /* ivb */ #define _PIPE_CRC_RES_5_A_IVB 0x60074 #define _PIPE_CRC_RES_5_B_IVB 0x61074 -#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) +#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB) /* hsw+ */ #define _PIPE_CRC_EXP_A_HSW 0x60054 #define _PIPE_CRC_EXP_B_HSW 0x61054 -#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW) +#define PIPE_CRC_EXP_HSW(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW) /* hsw+ */ #define _PIPE_CRC_RES_A_HSW 0x60064 #define _PIPE_CRC_RES_B_HSW 0x61064 -#define PIPE_CRC_RES_HSW(pipe) _MMIO_PIPE(pipe, _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW) +#define PIPE_CRC_RES_HSW(pipe) _MMIO_PIPE((pipe), _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW) #endif /* __INTEL_PIPE_CRC_REGS_H__ */ -- cgit From dd3cac0ac7ec4921dc93af884997a44c4e59b4e8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 16:37:05 +0300 Subject: drm/i915: drop redundant W=1 warnings from Makefile Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default across the subsystem"), most of the extra warnings in the driver Makefile are redundant. Remove them. Note that -Wmissing-declarations and -Wmissing-prototypes are always enabled by default in scripts/Makefile.extrawarn. Acked-by: Lucas De Marchi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/490931748fa9a1dbac2bceda0c4b778240b10b58.1716471145.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/Makefile | 25 +------------------------ 1 file changed, 1 insertion(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 9a3f910ce4fd..06e6486c07b5 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -3,31 +3,8 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -# Unconditionally enable W=1 warnings locally -# --- begin copy-paste W=1 warnings from scripts/Makefile.extrawarn -subdir-ccflags-y += -Wextra -Wunused -Wno-unused-parameter -subdir-ccflags-y += -Wmissing-declarations -subdir-ccflags-y += $(call cc-option, -Wrestrict) -subdir-ccflags-y += -Wmissing-format-attribute -subdir-ccflags-y += -Wmissing-prototypes -subdir-ccflags-y += -Wold-style-definition -subdir-ccflags-y += -Wmissing-include-dirs -subdir-ccflags-y += $(call cc-option, -Wunused-but-set-variable) -subdir-ccflags-y += $(call cc-option, -Wunused-const-variable) -subdir-ccflags-y += $(call cc-option, -Wpacked-not-aligned) -subdir-ccflags-y += $(call cc-option, -Wformat-overflow) +# Enable W=1 warnings not enabled in drm subsystem Makefile subdir-ccflags-y += $(call cc-option, -Wformat-truncation) -subdir-ccflags-y += $(call cc-option, -Wstringop-truncation) -# The following turn off the warnings enabled by -Wextra -ifeq ($(findstring 2, $(KBUILD_EXTRA_WARN)),) -subdir-ccflags-y += -Wno-missing-field-initializers -subdir-ccflags-y += -Wno-type-limits -subdir-ccflags-y += -Wno-shift-negative-value -endif -ifeq ($(findstring 3, $(KBUILD_EXTRA_WARN)),) -subdir-ccflags-y += -Wno-sign-compare -endif -# --- end copy-paste # Enable -Werror in CI and development subdir-ccflags-$(CONFIG_DRM_I915_WERROR) += -Werror -- cgit From 27e3b4ee6320b466dec3f6f342ca4b372893b36b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 May 2024 20:48:05 +0300 Subject: drm/i915/display: include gem/i915_gem_stolen.h where needed Include what you use. We need to move the compat i915_gem_stolen.h under gem subdir. With this, we can drop the include from xe compat i915_drv.h. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/6ac3480a8689fda5aaf4007cb604e06e939a03f7.1717004739.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_fbc.c | 1 + .../xe/compat-i915-headers/gem/i915_gem_stolen.h | 87 ++++++++++++++++++++++ drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - .../drm/xe/compat-i915-headers/i915_gem_stolen.h | 87 ---------------------- 4 files changed, 88 insertions(+), 88 deletions(-) create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_stolen.h delete mode 100644 drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index e9189a864f69..6985abeb6102 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -43,6 +43,7 @@ #include #include +#include "gem/i915_gem_stolen.h" #include "i915_drv.h" #include "i915_reg.h" #include "i915_utils.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_stolen.h b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_stolen.h new file mode 100644 index 000000000000..cb6c7598824b --- /dev/null +++ b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_stolen.h @@ -0,0 +1,87 @@ +#ifndef _I915_GEM_STOLEN_H_ +#define _I915_GEM_STOLEN_H_ + +#include "xe_ttm_stolen_mgr.h" +#include "xe_res_cursor.h" + +struct xe_bo; + +struct i915_stolen_fb { + struct xe_bo *bo; +}; + +static inline int i915_gem_stolen_insert_node_in_range(struct xe_device *xe, + struct i915_stolen_fb *fb, + u32 size, u32 align, + u32 start, u32 end) +{ + struct xe_bo *bo; + int err; + u32 flags = XE_BO_FLAG_PINNED | XE_BO_FLAG_STOLEN; + + if (start < SZ_4K) + start = SZ_4K; + + if (align) { + size = ALIGN(size, align); + start = ALIGN(start, align); + } + + bo = xe_bo_create_locked_range(xe, xe_device_get_root_tile(xe), + NULL, size, start, end, + ttm_bo_type_kernel, flags); + if (IS_ERR(bo)) { + err = PTR_ERR(bo); + bo = NULL; + return err; + } + err = xe_bo_pin(bo); + xe_bo_unlock_vm_held(bo); + + if (err) { + xe_bo_put(fb->bo); + bo = NULL; + } + + fb->bo = bo; + + return err; +} + +static inline int i915_gem_stolen_insert_node(struct xe_device *xe, + struct i915_stolen_fb *fb, + u32 size, u32 align) +{ + /* Not used on xe */ + BUG_ON(1); + return -ENODEV; +} + +static inline void i915_gem_stolen_remove_node(struct xe_device *xe, + struct i915_stolen_fb *fb) +{ + xe_bo_unpin_map_no_vm(fb->bo); + fb->bo = NULL; +} + +#define i915_gem_stolen_initialized(xe) (!!ttm_manager_type(&(xe)->ttm, XE_PL_STOLEN)) +#define i915_gem_stolen_node_allocated(fb) (!!((fb)->bo)) + +static inline u32 i915_gem_stolen_node_offset(struct i915_stolen_fb *fb) +{ + struct xe_res_cursor res; + + xe_res_first(fb->bo->ttm.resource, 0, 4096, &res); + return res.start; +} + +/* Used for < gen4. These are not supported by Xe */ +#define i915_gem_stolen_area_address(xe) (!WARN_ON(1)) +/* Used for gen9 specific WA. Gen9 is not supported by Xe */ +#define i915_gem_stolen_area_size(xe) (!WARN_ON(1)) + +#define i915_gem_stolen_node_address(xe, fb) (xe_ttm_stolen_gpu_offset(xe) + \ + i915_gem_stolen_node_offset(fb)) +#define i915_gem_stolen_node_size(fb) ((u64)((fb)->bo->ttm.base.size)) + +#endif diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index ffaa4d2f1eed..0675c50edc6f 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -19,7 +19,6 @@ #include "xe_bo.h" #include "xe_pm.h" #include "xe_step.h" -#include "i915_gem_stolen.h" #include "i915_gpu_error.h" #include "i915_reg_defs.h" #include "i915_utils.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h deleted file mode 100644 index cb6c7598824b..000000000000 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_gem_stolen.h +++ /dev/null @@ -1,87 +0,0 @@ -#ifndef _I915_GEM_STOLEN_H_ -#define _I915_GEM_STOLEN_H_ - -#include "xe_ttm_stolen_mgr.h" -#include "xe_res_cursor.h" - -struct xe_bo; - -struct i915_stolen_fb { - struct xe_bo *bo; -}; - -static inline int i915_gem_stolen_insert_node_in_range(struct xe_device *xe, - struct i915_stolen_fb *fb, - u32 size, u32 align, - u32 start, u32 end) -{ - struct xe_bo *bo; - int err; - u32 flags = XE_BO_FLAG_PINNED | XE_BO_FLAG_STOLEN; - - if (start < SZ_4K) - start = SZ_4K; - - if (align) { - size = ALIGN(size, align); - start = ALIGN(start, align); - } - - bo = xe_bo_create_locked_range(xe, xe_device_get_root_tile(xe), - NULL, size, start, end, - ttm_bo_type_kernel, flags); - if (IS_ERR(bo)) { - err = PTR_ERR(bo); - bo = NULL; - return err; - } - err = xe_bo_pin(bo); - xe_bo_unlock_vm_held(bo); - - if (err) { - xe_bo_put(fb->bo); - bo = NULL; - } - - fb->bo = bo; - - return err; -} - -static inline int i915_gem_stolen_insert_node(struct xe_device *xe, - struct i915_stolen_fb *fb, - u32 size, u32 align) -{ - /* Not used on xe */ - BUG_ON(1); - return -ENODEV; -} - -static inline void i915_gem_stolen_remove_node(struct xe_device *xe, - struct i915_stolen_fb *fb) -{ - xe_bo_unpin_map_no_vm(fb->bo); - fb->bo = NULL; -} - -#define i915_gem_stolen_initialized(xe) (!!ttm_manager_type(&(xe)->ttm, XE_PL_STOLEN)) -#define i915_gem_stolen_node_allocated(fb) (!!((fb)->bo)) - -static inline u32 i915_gem_stolen_node_offset(struct i915_stolen_fb *fb) -{ - struct xe_res_cursor res; - - xe_res_first(fb->bo->ttm.resource, 0, 4096, &res); - return res.start; -} - -/* Used for < gen4. These are not supported by Xe */ -#define i915_gem_stolen_area_address(xe) (!WARN_ON(1)) -/* Used for gen9 specific WA. Gen9 is not supported by Xe */ -#define i915_gem_stolen_area_size(xe) (!WARN_ON(1)) - -#define i915_gem_stolen_node_address(xe, fb) (xe_ttm_stolen_gpu_offset(xe) + \ - i915_gem_stolen_node_offset(fb)) -#define i915_gem_stolen_node_size(fb) ((u64)((fb)->bo->ttm.base.size)) - -#endif -- cgit From 03f8db65ad8616ed8be67efc4379fdd60903235b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 May 2024 20:48:06 +0300 Subject: drm/i915/display: include gt/intel_gt_types.h where needed Include what you use. We need to move the compat intel_gt_types.h under gt subdir. With this, we can drop the include from xe compat i915_drv.h. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/df73c0934ad21f157714a41b33b81cebd2a523a6.1717004739.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_fbc.c | 1 + drivers/gpu/drm/xe/compat-i915-headers/gt/intel_gt_types.h | 11 +++++++++++ drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h | 11 ----------- 4 files changed, 12 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/gt/intel_gt_types.h delete mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 6985abeb6102..8e956e7a1964 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -44,6 +44,7 @@ #include #include "gem/i915_gem_stolen.h" +#include "gt/intel_gt_types.h" #include "i915_drv.h" #include "i915_reg.h" #include "i915_utils.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gt/intel_gt_types.h b/drivers/gpu/drm/xe/compat-i915-headers/gt/intel_gt_types.h new file mode 100644 index 000000000000..c15806d6c4f7 --- /dev/null +++ b/drivers/gpu/drm/xe/compat-i915-headers/gt/intel_gt_types.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + */ + +#ifndef __INTEL_GT_TYPES__ +#define __INTEL_GT_TYPES__ + +#define intel_gt_support_legacy_fencing(gt) 0 + +#endif diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index 0675c50edc6f..f976588ed628 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -22,7 +22,6 @@ #include "i915_gpu_error.h" #include "i915_reg_defs.h" #include "i915_utils.h" -#include "intel_gt_types.h" #include "intel_step.h" #include "intel_uncore.h" #include "intel_runtime_pm.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h deleted file mode 100644 index c15806d6c4f7..000000000000 --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_gt_types.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2023 Intel Corporation - */ - -#ifndef __INTEL_GT_TYPES__ -#define __INTEL_GT_TYPES__ - -#define intel_gt_support_legacy_fencing(gt) 0 - -#endif -- cgit From 8411aa0c5541a1f2f03938c83445e2a1e7ce84a5 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 May 2024 20:48:07 +0300 Subject: drm/i915/display: include i915_gpu_error.h where needed Include what you use. With this, we can drop the include from xe compat i915_drv.h. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/a5dbb8d46403761bd8518db45fa71dc55930d3cf.1717004739.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_dmc.c | 1 + drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 63fccdda56c0..b5ebb0f5b269 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -26,6 +26,7 @@ #include #include "i915_drv.h" +#include "i915_gpu_error.h" #include "i915_reg.h" #include "intel_de.h" #include "intel_dmc.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index f976588ed628..bf2f2efe7beb 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -19,7 +19,6 @@ #include "xe_bo.h" #include "xe_pm.h" #include "xe_step.h" -#include "i915_gpu_error.h" #include "i915_reg_defs.h" #include "i915_utils.h" #include "intel_step.h" -- cgit From 37310936c36bd3e4d2a6415f3ca0dc5e1eae899a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 May 2024 20:48:08 +0300 Subject: drm/i915/display: include intel_uncore.h where needed Include what you use. With this, we can drop the include from xe compat i915_drv.h. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/bc3a722413e20db905671e58627ba6d757f41c63.1717004739.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_bios.c | 1 + drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 128fe9250f40..def2ade61954 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -36,6 +36,7 @@ #include "intel_display.h" #include "intel_display_types.h" #include "intel_gmbus.h" +#include "intel_uncore.h" #define _INTEL_BIOS_PRIVATE #include "intel_vbt_defs.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index bf2f2efe7beb..3b3533ec07a4 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -22,7 +22,6 @@ #include "i915_reg_defs.h" #include "i915_utils.h" #include "intel_step.h" -#include "intel_uncore.h" #include "intel_runtime_pm.h" #include -- cgit From 61e22c77ded6dec109d1bfadaf0c4afd27095970 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 May 2024 20:48:09 +0300 Subject: drm/i915/display: include intel_step.h where needed Include what you use. With this, we can drop the include along with xe_step.h from xe compat i915_drv.h. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/abee71a6c6edbd1a3ddf0f97838977e53feaa5ff.1717004739.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_dmc.c | 1 + drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 2 -- 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index b5ebb0f5b269..852c11aa3205 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -31,6 +31,7 @@ #include "intel_de.h" #include "intel_dmc.h" #include "intel_dmc_regs.h" +#include "intel_step.h" /** * DOC: DMC Firmware Support diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index 3b3533ec07a4..ef04d965a574 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -18,10 +18,8 @@ #include "xe_device.h" #include "xe_bo.h" #include "xe_pm.h" -#include "xe_step.h" #include "i915_reg_defs.h" #include "i915_utils.h" -#include "intel_step.h" #include "intel_runtime_pm.h" #include -- cgit From 208f53102a0b66d5735868c717de32ef49a20050 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 May 2024 20:48:10 +0300 Subject: drm/i915/display: include xe_bo.h, gem_object_types etc. where needed Include what you use. The dependencies on the headers, and what they include, is a bit convoluted. Add xe compat gem/gem_object_types.h. Fix all the places needed. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/e9ca3d6127ea22f252d9dbf30cfde99e37538c99.1717004739.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 1 + drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_fb.c | 1 + drivers/gpu/drm/i915/display/intel_fbdev.c | 1 + .../drm/xe/compat-i915-headers/gem/i915_gem_object_types.h | 11 +++++++++++ drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 4 ---- drivers/gpu/drm/xe/display/intel_fb_bo.c | 2 ++ drivers/gpu/drm/xe/display/intel_fbdev_fb.c | 9 ++++----- drivers/gpu/drm/xe/display/xe_fb_pin.c | 5 +++-- drivers/gpu/drm/xe/display/xe_plane_initial.c | 1 + 10 files changed, 25 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_types.h diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index a4ce39a7f265..980c5dc70763 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -32,6 +32,7 @@ */ #include +#include #include #include diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 77609656317b..83d6a3d901fd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -47,6 +47,7 @@ #include #include +#include "gem/i915_gem_object_types.h" /* for to_intel_bo() */ #include "i915_vma.h" #include "i915_vma_types.h" #include "intel_bios.h" diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c index b6638726949d..8069abf91c5e 100644 --- a/drivers/gpu/drm/i915/display/intel_fb.c +++ b/drivers/gpu/drm/i915/display/intel_fb.c @@ -9,6 +9,7 @@ #include #include +#include "gem/i915_gem_object.h" #include "i915_drv.h" #include "intel_display.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 5ad0b4c8a0fd..37ae176bfeb0 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -44,6 +44,7 @@ #include #include "gem/i915_gem_mman.h" +#include "gem/i915_gem_object.h" #include "i915_drv.h" #include "intel_display_types.h" diff --git a/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_types.h b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_types.h new file mode 100644 index 000000000000..7d6bb1abab73 --- /dev/null +++ b/drivers/gpu/drm/xe/compat-i915-headers/gem/i915_gem_object_types.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2024 Intel Corporation */ + +#ifndef __I915_GEM_OBJECT_TYPES_H__ +#define __I915_GEM_OBJECT_TYPES_H__ + +#include "xe_bo.h" + +#define to_intel_bo(x) gem_to_xe_bo((x)) + +#endif diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index ef04d965a574..1da5e67cda29 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -12,11 +12,8 @@ #include -#include "gem/i915_gem_object.h" - #include "soc/intel_pch.h" #include "xe_device.h" -#include "xe_bo.h" #include "xe_pm.h" #include "i915_reg_defs.h" #include "i915_utils.h" @@ -112,7 +109,6 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) #define IS_RAPTORLAKE_U(xe) ((xe)->info.subplatform == XE_SUBPLATFORM_ALDERLAKE_P_RPLU) #define IS_ICL_WITH_PORT_F(xe) (xe && 0) #define HAS_FLAT_CCS(xe) (xe_device_has_flat_ccs(xe)) -#define to_intel_bo(x) gem_to_xe_bo((x)) #define HAS_128_BYTE_Y_TILING(xe) (xe || 1) diff --git a/drivers/gpu/drm/xe/display/intel_fb_bo.c b/drivers/gpu/drm/xe/display/intel_fb_bo.c index e18521acc516..b89cda053d2c 100644 --- a/drivers/gpu/drm/xe/display/intel_fb_bo.c +++ b/drivers/gpu/drm/xe/display/intel_fb_bo.c @@ -4,10 +4,12 @@ */ #include +#include #include "i915_drv.h" #include "intel_display_types.h" #include "intel_fb_bo.h" +#include "xe_bo.h" void intel_fb_bo_framebuffer_fini(struct xe_bo *bo) { diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c index f6bf5896ff1b..5ecc7d467934 100644 --- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c +++ b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c @@ -3,15 +3,14 @@ * Copyright © 2023 Intel Corporation */ -#include "intel_fbdev_fb.h" - #include -#include "xe_gt.h" -#include "xe_ttm_stolen_mgr.h" - #include "i915_drv.h" #include "intel_display_types.h" +#include "intel_fbdev_fb.h" +#include "xe_bo.h" +#include "xe_gt.h" +#include "xe_ttm_stolen_mgr.h" struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, struct drm_fb_helper_surface_size *sizes) diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 36e15c4961c1..0449cdb892f3 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -3,17 +3,18 @@ * Copyright © 2021 Intel Corporation */ +#include + #include "i915_drv.h" #include "intel_display_types.h" #include "intel_dpt.h" #include "intel_fb.h" #include "intel_fb_pin.h" +#include "xe_bo.h" #include "xe_ggtt.h" #include "xe_gt.h" #include "xe_pm.h" -#include - static void write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_ofs, u32 width, u32 height, u32 src_stride, u32 dst_stride) diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c index 9eaa29e733e1..7672a0cffbd8 100644 --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c @@ -18,6 +18,7 @@ #include "intel_fb_pin.h" #include "intel_frontbuffer.h" #include "intel_plane_initial.h" +#include "xe_bo.h" static bool intel_reuse_initial_plane_obj(struct intel_crtc *this, -- cgit From b67be58fafb21b6b75f792674ce8f9f5635694d1 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 May 2024 20:48:11 +0300 Subject: drm/xe/display: move compat uncore stubs to the correct file Move things that belong to intel_uncore.h to the correct place. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/3f3903c7c5e34aefac0f6d06e433710bc782c97e.1717004739.git.jani.nikula@intel.com --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 5 ----- drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h | 5 +++++ 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index 1da5e67cda29..0e9e833f945c 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -154,11 +154,6 @@ static inline void intel_runtime_pm_put(struct xe_runtime_pm *pm, intel_wakeref_ #define assert_rpm_wakelock_held(x) do { } while (0) #define assert_rpm_raw_wakeref_held(x) do { } while (0) -#define intel_uncore_forcewake_get(x, y) do { } while (0) -#define intel_uncore_forcewake_put(x, y) do { } while (0) - -#define intel_uncore_arm_unclaimed_mmio_detection(x) do { } while (0) - #define I915_PRIORITY_DISPLAY 0 struct i915_sched_attr { int priority; diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h index ef79793caa72..083c4da2ea41 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h @@ -172,4 +172,9 @@ static inline void __iomem *intel_uncore_regs(struct intel_uncore *uncore) #define raw_reg_write(base, reg, value) \ writel(value, base + i915_mmio_reg_offset(reg)) +#define intel_uncore_forcewake_get(x, y) do { } while (0) +#define intel_uncore_forcewake_put(x, y) do { } while (0) + +#define intel_uncore_arm_unclaimed_mmio_detection(x) do { } while (0) + #endif /* __INTEL_UNCORE_H__ */ -- cgit From d242f39dd10164d3d82e1922277c16c1f3704687 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 May 2024 20:48:12 +0300 Subject: drm/xe/display: move compat runtime pm stubs to the correct file Move things that belong to intel_runtime_pm.h to the correct place. Add missing header guards while at it. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/edefb6ef02920528eacdf01b828cfc45ce55e061.1717004739.git.jani.nikula@intel.com --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 48 -------------------- .../drm/xe/compat-i915-headers/intel_runtime_pm.h | 51 ++++++++++++++++++++++ 2 files changed, 51 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index 0e9e833f945c..c9554eeaf468 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -14,11 +14,9 @@ #include "soc/intel_pch.h" #include "xe_device.h" -#include "xe_pm.h" #include "i915_reg_defs.h" #include "i915_utils.h" #include "intel_runtime_pm.h" -#include static inline struct drm_i915_private *to_i915(const struct drm_device *dev) { @@ -112,58 +110,12 @@ static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) #define HAS_128_BYTE_Y_TILING(xe) (xe || 1) -#include "intel_wakeref.h" - -static inline intel_wakeref_t intel_runtime_pm_get(struct xe_runtime_pm *pm) -{ - struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); - - return xe_pm_runtime_resume_and_get(xe); -} - -static inline intel_wakeref_t intel_runtime_pm_get_if_in_use(struct xe_runtime_pm *pm) -{ - struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); - - return xe_pm_runtime_get_if_in_use(xe); -} - -static inline intel_wakeref_t intel_runtime_pm_get_noresume(struct xe_runtime_pm *pm) -{ - struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); - - xe_pm_runtime_get_noresume(xe); - return true; -} - -static inline void intel_runtime_pm_put_unchecked(struct xe_runtime_pm *pm) -{ - struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); - - xe_pm_runtime_put(xe); -} - -static inline void intel_runtime_pm_put(struct xe_runtime_pm *pm, intel_wakeref_t wakeref) -{ - if (wakeref) - intel_runtime_pm_put_unchecked(pm); -} - -#define intel_runtime_pm_get_raw intel_runtime_pm_get -#define intel_runtime_pm_put_raw intel_runtime_pm_put -#define assert_rpm_wakelock_held(x) do { } while (0) -#define assert_rpm_raw_wakeref_held(x) do { } while (0) - #define I915_PRIORITY_DISPLAY 0 struct i915_sched_attr { int priority; }; #define i915_gem_fence_wait_priority(fence, attr) do { (void) attr; } while (0) -#define with_intel_runtime_pm(rpm, wf) \ - for ((wf) = intel_runtime_pm_get(rpm); (wf); \ - intel_runtime_pm_put((rpm), (wf)), (wf) = 0) - #define pdev_to_i915 pdev_to_xe_device #define RUNTIME_INFO(xe) (&(xe)->info.i915_runtime) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h index 89da3cc62f39..8c7b315aa8ac 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h @@ -3,7 +3,12 @@ * Copyright © 2023 Intel Corporation */ +#ifndef __INTEL_RUNTIME_PM_H__ +#define __INTEL_RUNTIME_PM_H__ + #include "intel_wakeref.h" +#include "xe_device_types.h" +#include "xe_pm.h" #define intel_runtime_pm xe_runtime_pm @@ -14,3 +19,49 @@ static inline void disable_rpm_wakeref_asserts(void *rpm) static inline void enable_rpm_wakeref_asserts(void *rpm) { } + +static inline intel_wakeref_t intel_runtime_pm_get(struct xe_runtime_pm *pm) +{ + struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); + + return xe_pm_runtime_resume_and_get(xe); +} + +static inline intel_wakeref_t intel_runtime_pm_get_if_in_use(struct xe_runtime_pm *pm) +{ + struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); + + return xe_pm_runtime_get_if_in_use(xe); +} + +static inline intel_wakeref_t intel_runtime_pm_get_noresume(struct xe_runtime_pm *pm) +{ + struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); + + xe_pm_runtime_get_noresume(xe); + return true; +} + +static inline void intel_runtime_pm_put_unchecked(struct xe_runtime_pm *pm) +{ + struct xe_device *xe = container_of(pm, struct xe_device, runtime_pm); + + xe_pm_runtime_put(xe); +} + +static inline void intel_runtime_pm_put(struct xe_runtime_pm *pm, intel_wakeref_t wakeref) +{ + if (wakeref) + intel_runtime_pm_put_unchecked(pm); +} + +#define intel_runtime_pm_get_raw intel_runtime_pm_get +#define intel_runtime_pm_put_raw intel_runtime_pm_put +#define assert_rpm_wakelock_held(x) do { } while (0) +#define assert_rpm_raw_wakeref_held(x) do { } while (0) + +#define with_intel_runtime_pm(rpm, wf) \ + for ((wf) = intel_runtime_pm_get(rpm); (wf); \ + intel_runtime_pm_put((rpm), (wf)), (wf) = 0) + +#endif -- cgit From 3ddb4f80990407c3262bde7867d288967b8da6b8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 May 2024 20:48:13 +0300 Subject: drm/xe/display: reduce includes in compat i915_drv.h Remove some unnecessary includes, and replace xe_device.h with the sufficient xe_device_types.h. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/ada73d5e3565b1cc284405386a16cc74d79bbb05.1717004739.git.jani.nikula@intel.com --- drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h index c9554eeaf468..a5dbdaf283b2 100644 --- a/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h +++ b/drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h @@ -12,11 +12,9 @@ #include -#include "soc/intel_pch.h" -#include "xe_device.h" -#include "i915_reg_defs.h" #include "i915_utils.h" #include "intel_runtime_pm.h" +#include "xe_device_types.h" static inline struct drm_i915_private *to_i915(const struct drm_device *dev) { -- cgit From 8e712bd7966c0f9024b1b30ac4bd6b8988a592dc Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Wed, 29 May 2024 20:48:14 +0300 Subject: drm/xe/display: drop i915_drv.h include from xe code Drop i915_drv.h include from xe display code as much as possible, and switch to xe types where necessary. Reviewed-by: Rodrigo Vivi Acked-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/bb490f3e928fd8178277fde2435de80638fc5715.1717004739.git.jani.nikula@intel.com --- drivers/gpu/drm/xe/display/ext/i915_irq.c | 1 - drivers/gpu/drm/xe/display/intel_fb_bo.c | 5 ++--- drivers/gpu/drm/xe/display/intel_fbdev_fb.c | 21 ++++++++++----------- drivers/gpu/drm/xe/display/xe_dsb_buffer.c | 9 ++++----- drivers/gpu/drm/xe/display/xe_fb_pin.c | 1 - drivers/gpu/drm/xe/display/xe_plane_initial.c | 18 ++++++++---------- 6 files changed, 24 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/xe/display/ext/i915_irq.c b/drivers/gpu/drm/xe/display/ext/i915_irq.c index bee191a4a97d..eb40f1cb44f6 100644 --- a/drivers/gpu/drm/xe/display/ext/i915_irq.c +++ b/drivers/gpu/drm/xe/display/ext/i915_irq.c @@ -3,7 +3,6 @@ * Copyright © 2023 Intel Corporation */ -#include "i915_drv.h" #include "i915_irq.h" #include "i915_reg.h" #include "intel_uncore.h" diff --git a/drivers/gpu/drm/xe/display/intel_fb_bo.c b/drivers/gpu/drm/xe/display/intel_fb_bo.c index b89cda053d2c..f835492f73fb 100644 --- a/drivers/gpu/drm/xe/display/intel_fb_bo.c +++ b/drivers/gpu/drm/xe/display/intel_fb_bo.c @@ -6,7 +6,6 @@ #include #include -#include "i915_drv.h" #include "intel_display_types.h" #include "intel_fb_bo.h" #include "xe_bo.h" @@ -26,7 +25,7 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, struct xe_bo *bo, struct drm_mode_fb_cmd2 *mode_cmd) { - struct drm_i915_private *i915 = to_i915(bo->ttm.base.dev); + struct xe_device *xe = to_xe_device(bo->ttm.base.dev); int ret; xe_bo_get(bo); @@ -42,7 +41,7 @@ int intel_fb_bo_framebuffer_init(struct intel_framebuffer *intel_fb, * mode when the boect is VM_BINDed, so we can only set * coherency with display when unbound. */ - if (XE_IOCTL_DBG(i915, !list_empty(&bo->ttm.base.gpuva.list))) { + if (XE_IOCTL_DBG(xe, !list_empty(&bo->ttm.base.gpuva.list))) { ttm_bo_unreserve(&bo->ttm); ret = -EINVAL; goto err; diff --git a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c index 5ecc7d467934..816ad13821a8 100644 --- a/drivers/gpu/drm/xe/display/intel_fbdev_fb.c +++ b/drivers/gpu/drm/xe/display/intel_fbdev_fb.c @@ -5,7 +5,6 @@ #include -#include "i915_drv.h" #include "intel_display_types.h" #include "intel_fbdev_fb.h" #include "xe_bo.h" @@ -17,7 +16,7 @@ struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, { struct drm_framebuffer *fb; struct drm_device *dev = helper->dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct xe_device *xe = to_xe_device(dev); struct drm_mode_fb_cmd2 mode_cmd = {}; struct drm_i915_gem_object *obj; int size; @@ -38,26 +37,26 @@ struct intel_framebuffer *intel_fbdev_fb_alloc(struct drm_fb_helper *helper, size = PAGE_ALIGN(size); obj = ERR_PTR(-ENODEV); - if (!IS_DGFX(dev_priv)) { - obj = xe_bo_create_pin_map(dev_priv, xe_device_get_root_tile(dev_priv), + if (!IS_DGFX(xe)) { + obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe), NULL, size, ttm_bo_type_kernel, XE_BO_FLAG_SCANOUT | XE_BO_FLAG_STOLEN | XE_BO_FLAG_PINNED); if (!IS_ERR(obj)) - drm_info(&dev_priv->drm, "Allocated fbdev into stolen\n"); + drm_info(&xe->drm, "Allocated fbdev into stolen\n"); else - drm_info(&dev_priv->drm, "Allocated fbdev into stolen failed: %li\n", PTR_ERR(obj)); + drm_info(&xe->drm, "Allocated fbdev into stolen failed: %li\n", PTR_ERR(obj)); } if (IS_ERR(obj)) { - obj = xe_bo_create_pin_map(dev_priv, xe_device_get_root_tile(dev_priv), NULL, size, - ttm_bo_type_kernel, XE_BO_FLAG_SCANOUT | - XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(dev_priv)) | - XE_BO_FLAG_PINNED); + obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe), NULL, size, + ttm_bo_type_kernel, XE_BO_FLAG_SCANOUT | + XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) | + XE_BO_FLAG_PINNED); } if (IS_ERR(obj)) { - drm_err(&dev_priv->drm, "failed to allocate framebuffer (%pe)\n", obj); + drm_err(&xe->drm, "failed to allocate framebuffer (%pe)\n", obj); fb = ERR_PTR(-ENOMEM); goto err; } diff --git a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c index 44c9fd2143cc..9e860c61f4b3 100644 --- a/drivers/gpu/drm/xe/display/xe_dsb_buffer.c +++ b/drivers/gpu/drm/xe/display/xe_dsb_buffer.c @@ -3,7 +3,6 @@ * Copyright 2023, Intel Corporation. */ -#include "i915_drv.h" #include "i915_vma.h" #include "intel_display_types.h" #include "intel_dsb_buffer.h" @@ -34,18 +33,18 @@ void intel_dsb_buffer_memset(struct intel_dsb_buffer *dsb_buf, u32 idx, u32 val, bool intel_dsb_buffer_create(struct intel_crtc *crtc, struct intel_dsb_buffer *dsb_buf, size_t size) { - struct drm_i915_private *i915 = to_i915(crtc->base.dev); - struct drm_i915_gem_object *obj; + struct xe_device *xe = to_xe_device(crtc->base.dev); + struct xe_bo *obj; struct i915_vma *vma; vma = kzalloc(sizeof(*vma), GFP_KERNEL); if (!vma) return false; - obj = xe_bo_create_pin_map(i915, xe_device_get_root_tile(i915), + obj = xe_bo_create_pin_map(xe, xe_device_get_root_tile(xe), NULL, PAGE_ALIGN(size), ttm_bo_type_kernel, - XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(i915)) | + XE_BO_FLAG_VRAM_IF_DGFX(xe_device_get_root_tile(xe)) | XE_BO_FLAG_GGTT); if (IS_ERR(obj)) { kfree(vma); diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c index 0449cdb892f3..a2f417209124 100644 --- a/drivers/gpu/drm/xe/display/xe_fb_pin.c +++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c @@ -5,7 +5,6 @@ #include -#include "i915_drv.h" #include "intel_display_types.h" #include "intel_dpt.h" #include "intel_fb.h" diff --git a/drivers/gpu/drm/xe/display/xe_plane_initial.c b/drivers/gpu/drm/xe/display/xe_plane_initial.c index 7672a0cffbd8..e135b20962d9 100644 --- a/drivers/gpu/drm/xe/display/xe_plane_initial.c +++ b/drivers/gpu/drm/xe/display/xe_plane_initial.c @@ -9,7 +9,6 @@ #include "regs/xe_gtt_defs.h" #include "xe_ggtt.h" -#include "i915_drv.h" #include "intel_atomic_plane.h" #include "intel_crtc.h" #include "intel_display.h" @@ -25,10 +24,10 @@ intel_reuse_initial_plane_obj(struct intel_crtc *this, const struct intel_initial_plane_config plane_configs[], struct drm_framebuffer **fb) { - struct drm_i915_private *i915 = to_i915(this->base.dev); + struct xe_device *xe = to_xe_device(this->base.dev); struct intel_crtc *crtc; - for_each_intel_crtc(&i915->drm, crtc) { + for_each_intel_crtc(&xe->drm, crtc) { struct intel_plane *plane = to_intel_plane(crtc->base.primary); const struct intel_plane_state *plane_state = @@ -135,8 +134,7 @@ static bool intel_alloc_initial_plane_obj(struct intel_crtc *crtc, struct intel_initial_plane_config *plane_config) { - struct drm_device *dev = crtc->base.dev; - struct drm_i915_private *dev_priv = to_i915(dev); + struct xe_device *xe = to_xe_device(crtc->base.dev); struct drm_mode_fb_cmd2 mode_cmd = { 0 }; struct drm_framebuffer *fb = &plane_config->fb->base; struct xe_bo *bo; @@ -148,9 +146,9 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, case I915_FORMAT_MOD_4_TILED: break; default: - drm_dbg(&dev_priv->drm, - "Unsupported modifier for initial FB: 0x%llx\n", - fb->modifier); + drm_dbg_kms(&xe->drm, + "Unsupported modifier for initial FB: 0x%llx\n", + fb->modifier); return false; } @@ -161,13 +159,13 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, mode_cmd.modifier[0] = fb->modifier; mode_cmd.flags = DRM_MODE_FB_MODIFIERS; - bo = initial_plane_bo(dev_priv, plane_config); + bo = initial_plane_bo(xe, plane_config); if (!bo) return false; if (intel_framebuffer_init(to_intel_framebuffer(fb), bo, &mode_cmd)) { - drm_dbg_kms(&dev_priv->drm, "intel fb init failed\n"); + drm_dbg_kms(&xe->drm, "intel fb init failed\n"); goto err_bo; } /* Reference handed over to fb */ -- cgit From 92959898fdd6f398a799faf0bdcb1f7afc35d055 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 5 Jun 2024 14:33:36 +0300 Subject: drm/i915: Reduce DDI clock gating printk level from NOTICE to DEBUG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No idea why the DDI clock gating print is done with drm_notice(). Just use drm_dbg_kms() since no one is going to be interested in this under normal circumstances. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240605113336.11194-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 3c3fc53376ce..c76bbd13bb27 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2072,9 +2072,9 @@ void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder) !encoder->is_clock_enabled(encoder)) return; - drm_notice(&i915->drm, - "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", - encoder->base.base.id, encoder->base.name); + drm_dbg_kms(&i915->drm, + "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n", + encoder->base.base.id, encoder->base.name); encoder->disable_clock(encoder); } -- cgit From d6b933912df0daf23d88daa7f96f6a3a65a67894 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 6 Jun 2024 17:07:04 +0300 Subject: drm/i915/dmc: convert intel_dmc_print_error_state() to drm_printer Use the regular drm printer, so we can drop the i915_error_printf() usage. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20240606140705.3072987-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dmc.c | 15 +++++++-------- drivers/gpu/drm/i915/display/intel_dmc.h | 6 +++--- drivers/gpu/drm/i915/i915_gpu_error.c | 3 ++- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c index 852c11aa3205..73977b173898 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.c +++ b/drivers/gpu/drm/i915/display/intel_dmc.c @@ -26,7 +26,6 @@ #include #include "i915_drv.h" -#include "i915_gpu_error.h" #include "i915_reg.h" #include "intel_de.h" #include "intel_dmc.h" @@ -1185,7 +1184,7 @@ void intel_dmc_fini(struct drm_i915_private *i915) } } -void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, +void intel_dmc_print_error_state(struct drm_printer *p, struct drm_i915_private *i915) { struct intel_dmc *dmc = i915_to_dmc(i915); @@ -1193,13 +1192,13 @@ void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, if (!HAS_DMC(i915)) return; - i915_error_printf(m, "DMC initialized: %s\n", str_yes_no(dmc)); - i915_error_printf(m, "DMC loaded: %s\n", - str_yes_no(intel_dmc_has_payload(i915))); + drm_printf(p, "DMC initialized: %s\n", str_yes_no(dmc)); + drm_printf(p, "DMC loaded: %s\n", + str_yes_no(intel_dmc_has_payload(i915))); if (dmc) - i915_error_printf(m, "DMC fw version: %d.%d\n", - DMC_VERSION_MAJOR(dmc->version), - DMC_VERSION_MINOR(dmc->version)); + drm_printf(p, "DMC fw version: %d.%d\n", + DMC_VERSION_MAJOR(dmc->version), + DMC_VERSION_MINOR(dmc->version)); } static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h index fd607afff2ef..54cff6002e31 100644 --- a/drivers/gpu/drm/i915/display/intel_dmc.h +++ b/drivers/gpu/drm/i915/display/intel_dmc.h @@ -8,9 +8,9 @@ #include -struct drm_i915_error_state_buf; -struct drm_i915_private; enum pipe; +struct drm_i915_private; +struct drm_printer; void intel_dmc_init(struct drm_i915_private *i915); void intel_dmc_load_program(struct drm_i915_private *i915); @@ -22,7 +22,7 @@ void intel_dmc_suspend(struct drm_i915_private *i915); void intel_dmc_resume(struct drm_i915_private *i915); bool intel_dmc_has_payload(struct drm_i915_private *i915); void intel_dmc_debugfs_register(struct drm_i915_private *i915); -void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, +void intel_dmc_print_error_state(struct drm_printer *p, struct drm_i915_private *i915); void assert_dmc_loaded(struct drm_i915_private *i915); diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 625b3c024540..3fee7ad0ec51 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -836,6 +836,7 @@ static void err_print_gt_engines(struct drm_i915_error_state_buf *m, static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, struct i915_gpu_coredump *error) { + struct drm_printer p = i915_error_printer(m); const struct intel_engine_coredump *ee; struct timespec64 ts; @@ -873,7 +874,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, err_printf(m, "IOMMU enabled?: %d\n", error->iommu); - intel_dmc_print_error_state(m, m->i915); + intel_dmc_print_error_state(&p, m->i915); err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock)); err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended)); -- cgit From 349f4f1e6aaa313ee9e334b61bbeec83b847125c Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 6 Jun 2024 17:07:05 +0300 Subject: drm/i915/overlay: convert intel_overlay_print_error_state() to drm_printer Use the regular drm printer, so we can drop the i915_error_printf() usage. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/20240606140705.3072987-2-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_overlay.c | 11 +++++------ drivers/gpu/drm/i915/display/intel_overlay.h | 6 +++--- drivers/gpu/drm/i915/i915_gpu_error.c | 2 +- 3 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index 1c2099ed5514..b97087f8e311 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -1485,15 +1485,14 @@ intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) } void -intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, +intel_overlay_print_error_state(struct drm_printer *p, struct intel_overlay_error_state *error) { - i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", - error->dovsta, error->isr); - i915_error_printf(m, " Register file at 0x%08lx:\n", - error->base); + drm_printf(p, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", + error->dovsta, error->isr); + drm_printf(p, " Register file at 0x%08lx:\n", error->base); -#define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) +#define P(x) drm_printf(p, " " #x ": 0x%08x\n", error->regs.x) P(OBUF_0Y); P(OBUF_1Y); P(OBUF_0U); diff --git a/drivers/gpu/drm/i915/display/intel_overlay.h b/drivers/gpu/drm/i915/display/intel_overlay.h index c3f68fce6f08..f28a09c062d0 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.h +++ b/drivers/gpu/drm/i915/display/intel_overlay.h @@ -8,8 +8,8 @@ struct drm_device; struct drm_file; -struct drm_i915_error_state_buf; struct drm_i915_private; +struct drm_printer; struct intel_overlay; struct intel_overlay_error_state; @@ -24,7 +24,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data, void intel_overlay_reset(struct drm_i915_private *dev_priv); struct intel_overlay_error_state * intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); -void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, +void intel_overlay_print_error_state(struct drm_printer *p, struct intel_overlay_error_state *error); #else static inline void intel_overlay_setup(struct drm_i915_private *dev_priv) @@ -55,7 +55,7 @@ intel_overlay_capture_error_state(struct drm_i915_private *dev_priv) { return NULL; } -static inline void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, +static inline void intel_overlay_print_error_state(struct drm_printer *p, struct intel_overlay_error_state *error) { } diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 3fee7ad0ec51..96c6cafd5b9e 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -905,7 +905,7 @@ static void __err_print_to_sgl(struct drm_i915_error_state_buf *m, } if (error->overlay) - intel_overlay_print_error_state(m, error->overlay); + intel_overlay_print_error_state(&p, error->overlay); err_print_capabilities(m, error); err_print_params(m, &error->params); -- cgit From 9a875f958062950d5b7a862c9403a99adc1ff41b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:19 +0300 Subject: drm/i915: pass dev_priv explicitly to DPLL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DPLL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/7deea1d86c2706994450ec938f8f174a2ac54d27.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 21 +++++----- drivers/gpu/drm/i915/display/intel_display_power.c | 2 +- .../drm/i915/display/intel_display_power_well.c | 6 +-- drivers/gpu/drm/i915/display/intel_dpll.c | 45 +++++++++++----------- drivers/gpu/drm/i915/display/intel_dvo.c | 5 ++- drivers/gpu/drm/i915/display/intel_pps.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 7 files changed, 43 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7370acdd6b8b..42e2d884c98e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -382,11 +382,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv, fallthrough; case PORT_B: port_mask = DPLL_PORTB_READY_MASK; - dpll_reg = DPLL(0); + dpll_reg = DPLL(dev_priv, 0); break; case PORT_C: port_mask = DPLL_PORTC_READY_MASK; - dpll_reg = DPLL(0); + dpll_reg = DPLL(dev_priv, 0); expected_mask <<= 4; break; case PORT_D: @@ -8212,11 +8212,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) * the P1/P2 dividers. Otherwise the DPLL will keep using the old * dividers, even though the register value does change. */ - intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); - intel_de_write(dev_priv, DPLL(pipe), dpll); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), + dpll & ~DPLL_VGA_MODE_DIS); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); /* Wait for the clocks to stabilize. */ - intel_de_posting_read(dev_priv, DPLL(pipe)); + intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); udelay(150); /* The pixel multiplier can only be updated once the @@ -8224,12 +8225,12 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) * * So write it again. */ - intel_de_write(dev_priv, DPLL(pipe), dpll); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); /* We do this three times for luck */ for (i = 0; i < 3 ; i++) { - intel_de_write(dev_priv, DPLL(pipe), dpll); - intel_de_posting_read(dev_priv, DPLL(pipe)); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll); + intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); udelay(150); /* wait for warmup */ } @@ -8262,8 +8263,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) intel_wait_for_pipe_scanline_stopped(crtc); - intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); - intel_de_posting_read(dev_priv, DPLL(pipe)); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS); + intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); } void intel_hpd_poll_fini(struct drm_i915_private *i915) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 8c49ac053dfb..e288a1b21d7e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -1772,7 +1772,7 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv) * current lane status. */ if (intel_power_well_is_enabled(dev_priv, cmn_bc)) { - u32 status = intel_de_read(dev_priv, DPLL(PIPE_A)); + u32 status = intel_de_read(dev_priv, DPLL(dev_priv, PIPE_A)); unsigned int mask; mask = status & DPLL_PORTB_READY_MASK; diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 83f616097a29..3b6cb237d80a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1196,13 +1196,13 @@ static void vlv_display_power_well_init(struct drm_i915_private *dev_priv) * CHV DPLL B/C have some issues if VGA mode is enabled. */ for_each_pipe(dev_priv, pipe) { - u32 val = intel_de_read(dev_priv, DPLL(pipe)); + u32 val = intel_de_read(dev_priv, DPLL(dev_priv, pipe)); val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; - intel_de_write(dev_priv, DPLL(pipe), val); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); } vlv_init_display_clock_gating(dev_priv); @@ -1355,7 +1355,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv) */ if (BITS_SET(phy_control, PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) && - (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0) + (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0) phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1); if (BITS_SET(phy_control, diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index a981f45facb3..a007ca5208b8 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -403,7 +403,7 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc, hw_state->dpll_md = tmp; } - hw_state->dpll = intel_de_read(dev_priv, DPLL(crtc->pipe)); + hw_state->dpll = intel_de_read(dev_priv, DPLL(dev_priv, crtc->pipe)); if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { hw_state->fp0 = intel_de_read(dev_priv, FP0(crtc->pipe)); @@ -1842,11 +1842,12 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) * the P1/P2 dividers. Otherwise the DPLL will keep using the old * dividers, even though the register value does change. */ - intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll & ~DPLL_VGA_MODE_DIS); - intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), + hw_state->dpll & ~DPLL_VGA_MODE_DIS); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); /* Wait for the clocks to stabilize. */ - intel_de_posting_read(dev_priv, DPLL(pipe)); + intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); udelay(150); if (DISPLAY_VER(dev_priv) >= 4) { @@ -1857,13 +1858,13 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) * * So write it again. */ - intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); } /* We do this three times for luck */ for (i = 0; i < 3; i++) { - intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); - intel_de_posting_read(dev_priv, DPLL(pipe)); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); + intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); udelay(150); /* wait for warmup */ } } @@ -1991,11 +1992,11 @@ static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; enum pipe pipe = crtc->pipe; - intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); - intel_de_posting_read(dev_priv, DPLL(pipe)); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); + intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); udelay(150); - if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) + if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); } @@ -2012,7 +2013,7 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) assert_pps_unlocked(dev_priv, pipe); /* Enable Refclk */ - intel_de_write(dev_priv, DPLL(pipe), + intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); if (hw_state->dpll & DPLL_VCO_ENABLE) { @@ -2138,10 +2139,10 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) udelay(1); /* Enable PLL */ - intel_de_write(dev_priv, DPLL(pipe), hw_state->dpll); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll); /* Check PLL is locked */ - if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) + if (intel_de_wait_for_set(dev_priv, DPLL(dev_priv, pipe), DPLL_LOCK_VLV, 1)) drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); } @@ -2158,7 +2159,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) assert_pps_unlocked(dev_priv, pipe); /* Enable Refclk and SSC */ - intel_de_write(dev_priv, DPLL(pipe), + intel_de_write(dev_priv, DPLL(dev_priv, pipe), hw_state->dpll & ~DPLL_VCO_ENABLE); if (hw_state->dpll & DPLL_VCO_ENABLE) { @@ -2183,7 +2184,7 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) * We should always have it disabled. */ drm_WARN_ON(&dev_priv->drm, - (intel_de_read(dev_priv, DPLL(PIPE_B)) & + (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); } else { intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); @@ -2241,8 +2242,8 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; - intel_de_write(dev_priv, DPLL(pipe), val); - intel_de_posting_read(dev_priv, DPLL(pipe)); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); + intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); } void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) @@ -2259,8 +2260,8 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) if (pipe != PIPE_A) val |= DPLL_INTEGRATED_CRI_CLK_VLV; - intel_de_write(dev_priv, DPLL(pipe), val); - intel_de_posting_read(dev_priv, DPLL(pipe)); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), val); + intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); vlv_dpio_get(dev_priv); @@ -2285,8 +2286,8 @@ void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) /* Make sure the pipe isn't still relying on us */ assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); - intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); - intel_de_posting_read(dev_priv, DPLL(pipe)); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), DPLL_VGA_MODE_DIS); + intel_de_posting_read(dev_priv, DPLL(dev_priv, pipe)); } @@ -2312,7 +2313,7 @@ static void assert_pll(struct drm_i915_private *dev_priv, { bool cur_state; - cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; + cur_state = intel_de_read(dev_priv, DPLL(dev_priv, pipe)) & DPLL_VCO_ENABLE; I915_STATE_WARN(dev_priv, cur_state != state, "PLL state assertion failure (expected %s, current %s)\n", str_on_off(state), str_on_off(cur_state)); diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c index 1840f5b59229..091824334f26 100644 --- a/drivers/gpu/drm/i915/display/intel_dvo.c +++ b/drivers/gpu/drm/i915/display/intel_dvo.c @@ -456,13 +456,14 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv, * the device. */ for_each_pipe(dev_priv, pipe) - dpll[pipe] = intel_de_rmw(dev_priv, DPLL(pipe), 0, DPLL_DVO_2X_MODE); + dpll[pipe] = intel_de_rmw(dev_priv, DPLL(dev_priv, pipe), 0, + DPLL_DVO_2X_MODE); ret = dvo->dev_ops->init(&intel_dvo->dev, i2c); /* restore the DVO 2x clock state to original */ for_each_pipe(dev_priv, pipe) { - intel_de_write(dev_priv, DPLL(pipe), dpll[pipe]); + intel_de_write(dev_priv, DPLL(dev_priv, pipe), dpll[pipe]); } intel_gmbus_force_bit(i2c, false); diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c index 73046ef58d8e..42306bc4ba86 100644 --- a/drivers/gpu/drm/i915/display/intel_pps.c +++ b/drivers/gpu/drm/i915/display/intel_pps.c @@ -119,7 +119,7 @@ vlv_power_sequencer_kick(struct intel_dp *intel_dp) else DP |= DP_PIPE_SEL(pipe); - pll_enabled = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; + pll_enabled = intel_de_read(dev_priv, DPLL(dev_priv, pipe)) & DPLL_VCO_ENABLE; /* * The DPLL for the pipe must be enabled for this to work. diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0569a23b83b2..539c4e96d736 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -668,7 +668,7 @@ #define _DPLL_A 0x6014 #define _DPLL_B 0x6018 #define _CHV_DPLL_C 0x6030 -#define DPLL(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ +#define DPLL(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) #define VGA0 _MMIO(0x6000) -- cgit From 6ba1e81433e1a5b63394bfa38af9b5ede6aaae13 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:20 +0300 Subject: drm/i915: pass dev_priv explicitly to DPLL_MD Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DPLL_MD register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/98d24284d4ec435c3acae6445943204dfa96617d.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dpll.c | 18 +++++++++++------- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index a007ca5208b8..d67d5e2fd570 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -398,7 +398,8 @@ void i9xx_dpll_get_hw_state(struct intel_crtc *crtc, if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe]; else - tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe)); + tmp = intel_de_read(dev_priv, + DPLL_MD(dev_priv, crtc->pipe)); hw_state->dpll_md = tmp; } @@ -1851,7 +1852,8 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) udelay(150); if (DISPLAY_VER(dev_priv) >= 4) { - intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); + intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), + hw_state->dpll_md); } else { /* The pixel multiplier can only be updated once the * DPLL is enabled and the clocks are stable. @@ -2021,8 +2023,8 @@ void vlv_enable_pll(const struct intel_crtc_state *crtc_state) _vlv_enable_pll(crtc_state); } - intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); - intel_de_posting_read(dev_priv, DPLL_MD(pipe)); + intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), hw_state->dpll_md); + intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe)); } static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) @@ -2175,7 +2177,8 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) * the value from DPLLBMD to either pipe B or C. */ intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); - intel_de_write(dev_priv, DPLL_MD(PIPE_B), hw_state->dpll_md); + intel_de_write(dev_priv, DPLL_MD(dev_priv, PIPE_B), + hw_state->dpll_md); intel_de_write(dev_priv, CBR4_VLV, 0); dev_priv->display.state.chv_dpll_md[pipe] = hw_state->dpll_md; @@ -2187,8 +2190,9 @@ void chv_enable_pll(const struct intel_crtc_state *crtc_state) (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); } else { - intel_de_write(dev_priv, DPLL_MD(pipe), hw_state->dpll_md); - intel_de_posting_read(dev_priv, DPLL_MD(pipe)); + intel_de_write(dev_priv, DPLL_MD(dev_priv, pipe), + hw_state->dpll_md); + intel_de_posting_read(dev_priv, DPLL_MD(dev_priv, pipe)); } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 539c4e96d736..3166925b9881 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -768,7 +768,7 @@ #define _DPLL_A_MD 0x601c #define _DPLL_B_MD 0x6020 #define _CHV_DPLL_C_MD 0x603c -#define DPLL_MD(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ +#define DPLL_MD(dev_priv, pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) /* -- cgit From e5799743ee06f1733420ff87f96e800e6acf4f39 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:21 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_HTOTAL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_HTOTAL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/4bdba7417341782b74b89753b7db7fdc3edf932c.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 79ecfc339430..af0d3159369e 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -915,7 +915,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, /* program TRANS_HTOTAL register */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans), + intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, dsi_trans), HACTIVE(hactive - 1) | HTOTAL(htotal - 1)); } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 42e2d884c98e..481e076b17e6 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2710,7 +2710,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), vsyncshift); - intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), + intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder), HACTIVE(adjusted_mode->crtc_hdisplay - 1) | HTOTAL(adjusted_mode->crtc_htotal - 1)); intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), @@ -2811,7 +2811,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; u32 tmp; - tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder)); adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1; adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; @@ -8189,7 +8189,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) PLL_REF_INPUT_DREFCLK | DPLL_VCO_ENABLE; - intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder), + intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder), HACTIVE(640 - 1) | HTOTAL(800 - 1)); intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 826e38a9e6a4..2bf00d5336e3 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -224,7 +224,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), - intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder))); + intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 06393b77a9e8..0d972ef4871c 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -676,7 +676,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); /* Get H/V total from transcoder timing */ - htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); + htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); if (dp_br && link_n && htotal && vtotal) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3166925b9881..9832ece1d11a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1136,7 +1136,7 @@ #define _TRANS_VSYNC_DSI1 0x6b814 #define _TRANS_VSYNCSHIFT_DSI1 0x6b828 -#define TRANS_HTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) +#define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) #define TRANS_HBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) #define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) #define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index f5c4e4e2f11f..2bc90909d980 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -231,7 +231,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(SPRSCALE(PIPE_C)); MMIO_D(SPRSURFLIVE(PIPE_C)); MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0)); - MMIO_D(TRANS_HTOTAL(TRANSCODER_A)); + MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_HBLANK(TRANSCODER_A)); MMIO_D(TRANS_HSYNC(TRANSCODER_A)); MMIO_D(TRANS_VTOTAL(TRANSCODER_A)); @@ -240,7 +240,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(BCLRPAT(TRANSCODER_A)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A)); MMIO_D(PIPESRC(TRANSCODER_A)); - MMIO_D(TRANS_HTOTAL(TRANSCODER_B)); + MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_HBLANK(TRANSCODER_B)); MMIO_D(TRANS_HSYNC(TRANSCODER_B)); MMIO_D(TRANS_VTOTAL(TRANSCODER_B)); @@ -249,7 +249,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(BCLRPAT(TRANSCODER_B)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B)); MMIO_D(PIPESRC(TRANSCODER_B)); - MMIO_D(TRANS_HTOTAL(TRANSCODER_C)); + MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_HBLANK(TRANSCODER_C)); MMIO_D(TRANS_HSYNC(TRANSCODER_C)); MMIO_D(TRANS_VTOTAL(TRANSCODER_C)); @@ -258,7 +258,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(BCLRPAT(TRANSCODER_C)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C)); MMIO_D(PIPESRC(TRANSCODER_C)); - MMIO_D(TRANS_HTOTAL(TRANSCODER_EDP)); + MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_HBLANK(TRANSCODER_EDP)); MMIO_D(TRANS_HSYNC(TRANSCODER_EDP)); MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP)); -- cgit From 7d8ee788659968790786f69baeff3edce27bbfe7 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:22 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_HBLANK Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_HBLANK register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/19d3d11d522be1787db89bdc254ae826ca4fb50a.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 7 ++++--- drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 481e076b17e6..997418fb7310 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2713,7 +2713,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder), HACTIVE(adjusted_mode->crtc_hdisplay - 1) | HTOTAL(adjusted_mode->crtc_htotal - 1)); - intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), + intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder), HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), @@ -2816,7 +2816,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1; if (!transcoder_is_dsi(cpu_transcoder)) { - tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANS_HBLANK(dev_priv, cpu_transcoder)); adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1; adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; } @@ -8191,7 +8192,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder), HACTIVE(640 - 1) | HTOTAL(800 - 1)); - intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder), + intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder), HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 2bf00d5336e3..625b1fedd54c 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -226,7 +226,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s intel_de_write(dev_priv, PCH_TRANS_HTOTAL(pch_transcoder), intel_de_read(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), - intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder))); + intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder))); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9832ece1d11a..4d19ad8a50ad 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1137,7 +1137,7 @@ #define _TRANS_VSYNCSHIFT_DSI1 0x6b828 #define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) -#define TRANS_HBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) +#define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) #define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) #define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) #define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 2bc90909d980..47681fa69020 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -232,7 +232,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(SPRSURFLIVE(PIPE_C)); MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A)); - MMIO_D(TRANS_HBLANK(TRANSCODER_A)); + MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_HSYNC(TRANSCODER_A)); MMIO_D(TRANS_VTOTAL(TRANSCODER_A)); MMIO_D(TRANS_VBLANK(TRANSCODER_A)); @@ -241,7 +241,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A)); MMIO_D(PIPESRC(TRANSCODER_A)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B)); - MMIO_D(TRANS_HBLANK(TRANSCODER_B)); + MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_HSYNC(TRANSCODER_B)); MMIO_D(TRANS_VTOTAL(TRANSCODER_B)); MMIO_D(TRANS_VBLANK(TRANSCODER_B)); @@ -250,7 +250,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B)); MMIO_D(PIPESRC(TRANSCODER_B)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C)); - MMIO_D(TRANS_HBLANK(TRANSCODER_C)); + MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_HSYNC(TRANSCODER_C)); MMIO_D(TRANS_VTOTAL(TRANSCODER_C)); MMIO_D(TRANS_VBLANK(TRANSCODER_C)); @@ -259,7 +259,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C)); MMIO_D(PIPESRC(TRANSCODER_C)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP)); - MMIO_D(TRANS_HBLANK(TRANSCODER_EDP)); + MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_HSYNC(TRANSCODER_EDP)); MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP)); MMIO_D(TRANS_VBLANK(TRANSCODER_EDP)); -- cgit From 9b2db3bbc7b5d1033f5e4d108fa87814c1f633e0 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:23 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_HSYNC Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_HSYNC register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/d387281470c9b677adb659b80fa3385df2faca99.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 5 files changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index af0d3159369e..f87a2170ac91 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -938,7 +938,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans), + intel_de_write(dev_priv, + TRANS_HSYNC(dev_priv, dsi_trans), HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1)); } } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 997418fb7310..111f2c400ecd 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2716,7 +2716,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder), HBLANK_START(adjusted_mode->crtc_hblank_start - 1) | HBLANK_END(adjusted_mode->crtc_hblank_end - 1)); - intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), + intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder), HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); @@ -2822,7 +2822,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1; } - tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder)); + tmp = intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder)); adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; @@ -8194,7 +8194,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) HACTIVE(640 - 1) | HTOTAL(800 - 1)); intel_de_write(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder), HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); - intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder), + intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder), HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), VACTIVE(480 - 1) | VTOTAL(525 - 1)); diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 625b1fedd54c..480c0e09434d 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -228,7 +228,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s intel_de_write(dev_priv, PCH_TRANS_HBLANK(pch_transcoder), intel_de_read(dev_priv, TRANS_HBLANK(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_HSYNC(pch_transcoder), - intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder))); + intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder))); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4d19ad8a50ad..faee5ad2d5be 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1138,7 +1138,7 @@ #define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) #define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) -#define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) +#define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) #define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) #define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) #define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 47681fa69020..09d8960f7398 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -233,7 +233,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(REG_50080(PIPE_C, PLANE_SPRITE0)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A)); - MMIO_D(TRANS_HSYNC(TRANSCODER_A)); + MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VTOTAL(TRANSCODER_A)); MMIO_D(TRANS_VBLANK(TRANSCODER_A)); MMIO_D(TRANS_VSYNC(TRANSCODER_A)); @@ -242,7 +242,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPESRC(TRANSCODER_A)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B)); - MMIO_D(TRANS_HSYNC(TRANSCODER_B)); + MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VTOTAL(TRANSCODER_B)); MMIO_D(TRANS_VBLANK(TRANSCODER_B)); MMIO_D(TRANS_VSYNC(TRANSCODER_B)); @@ -251,7 +251,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPESRC(TRANSCODER_B)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C)); - MMIO_D(TRANS_HSYNC(TRANSCODER_C)); + MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VTOTAL(TRANSCODER_C)); MMIO_D(TRANS_VBLANK(TRANSCODER_C)); MMIO_D(TRANS_VSYNC(TRANSCODER_C)); @@ -260,7 +260,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPESRC(TRANSCODER_C)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP)); - MMIO_D(TRANS_HSYNC(TRANSCODER_EDP)); + MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP)); MMIO_D(TRANS_VBLANK(TRANSCODER_EDP)); MMIO_D(TRANS_VSYNC(TRANSCODER_EDP)); -- cgit From b3e773f6d5b131ca5a3a0ead2ec2a80fa9d4e05b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:24 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VTOTAL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VTOTAL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/751bc7046f5e2c5fc6a4fe5ade2e836c641abdb7.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 2 +- drivers/gpu/drm/i915/display/intel_crt.c | 3 ++- drivers/gpu/drm/i915/display/intel_display.c | 10 +++++----- drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 7 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index f87a2170ac91..f95709321ea6 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -953,7 +953,7 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, * struct drm_display_mode. * For interlace mode: program required pixel minus 2 */ - intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans), + intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, dsi_trans), VACTIVE(vactive - 1) | VTOTAL(vtotal - 1)); } diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 10e95dc425a6..29ab5b112b86 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -708,7 +708,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder)); - save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); + save_vtotal = intel_de_read(dev_priv, + TRANS_VTOTAL(dev_priv, cpu_transcoder)); vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 111f2c400ecd..c681a23be1eb 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2720,7 +2720,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta HSYNC_START(adjusted_mode->crtc_hsync_start - 1) | HSYNC_END(adjusted_mode->crtc_hsync_end - 1)); - intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), @@ -2736,7 +2736,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta * bits. */ if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && (pipe == PIPE_B || pipe == PIPE_C)) - intel_de_write(dev_priv, TRANS_VTOTAL(pipe), + intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, pipe), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); } @@ -2767,7 +2767,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc * The double buffer latch point for TRANS_VTOTAL * is the transcoder's undelayed vblank. */ - intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); } @@ -2826,7 +2826,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1; adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1; - tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)); adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1; adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1; @@ -8196,7 +8196,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) HBLANK_START(640 - 1) | HBLANK_END(800 - 1)); intel_de_write(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder), HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); - intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), VACTIVE(480 - 1) | VTOTAL(525 - 1)); intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 480c0e09434d..611a9cd2596f 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -231,7 +231,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s intel_de_read(dev_priv, TRANS_HSYNC(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), - intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder))); + intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 0d972ef4871c..45b1dbd5881a 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -677,7 +677,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) /* Get H/V total from transcoder timing */ htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); - vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); + vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); if (dp_br && link_n && htotal && vtotal) { u64 pixel_clk = 0; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index faee5ad2d5be..fe61cd0dae6e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1139,7 +1139,7 @@ #define TRANS_HTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) #define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) #define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) -#define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) +#define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) #define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) #define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) #define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 09d8960f7398..5dd85943e0a1 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -234,7 +234,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A)); - MMIO_D(TRANS_VTOTAL(TRANSCODER_A)); + MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VBLANK(TRANSCODER_A)); MMIO_D(TRANS_VSYNC(TRANSCODER_A)); MMIO_D(BCLRPAT(TRANSCODER_A)); @@ -243,7 +243,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B)); - MMIO_D(TRANS_VTOTAL(TRANSCODER_B)); + MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VBLANK(TRANSCODER_B)); MMIO_D(TRANS_VSYNC(TRANSCODER_B)); MMIO_D(BCLRPAT(TRANSCODER_B)); @@ -252,7 +252,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C)); - MMIO_D(TRANS_VTOTAL(TRANSCODER_C)); + MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VBLANK(TRANSCODER_C)); MMIO_D(TRANS_VSYNC(TRANSCODER_C)); MMIO_D(BCLRPAT(TRANSCODER_C)); @@ -261,7 +261,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP)); - MMIO_D(TRANS_VTOTAL(TRANSCODER_EDP)); + MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VBLANK(TRANSCODER_EDP)); MMIO_D(TRANS_VSYNC(TRANSCODER_EDP)); MMIO_D(BCLRPAT(TRANSCODER_EDP)); -- cgit From 45f1039335861705bdbf71aff4d890a692662980 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:25 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VBLANK Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VBLANK register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/c33739ac6f26105fd1ad79b0027b6626e241c7bc.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++- drivers/gpu/drm/i915/display/intel_crt.c | 10 +++++++--- drivers/gpu/drm/i915/display/intel_display.c | 9 +++++---- drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 6 files changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index f95709321ea6..0ee42954054f 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -995,7 +995,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, if (DISPLAY_VER(dev_priv) >= 12) { for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans), + intel_de_write(dev_priv, + TRANS_VBLANK(dev_priv, dsi_trans), VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1)); } } diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 29ab5b112b86..54549d2cfcff 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -710,7 +710,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder)); save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)); - vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); + vblank = intel_de_read(dev_priv, + TRANS_VBLANK(dev_priv, cpu_transcoder)); vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1; vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1; @@ -749,7 +750,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; vblank_start = vsync_start; - intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), + intel_de_write(dev_priv, + TRANS_VBLANK(dev_priv, cpu_transcoder), VBLANK_START(vblank_start - 1) | VBLANK_END(vblank_end - 1)); restore_vblank = true; @@ -782,7 +784,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) /* restore vblank if necessary */ if (restore_vblank) - intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank); + intel_de_write(dev_priv, + TRANS_VBLANK(dev_priv, cpu_transcoder), + vblank); /* * If more than 3/4 of the scanline detected a monitor, * then it is assumed to be present. This works even on i830, diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c681a23be1eb..87a690cf5808 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2723,7 +2723,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), VACTIVE(crtc_vdisplay - 1) | VTOTAL(crtc_vtotal - 1)); - intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), @@ -2760,7 +2760,7 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode. * But let's write it anyway to keep the state checker happy. */ - intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); /* @@ -2832,7 +2832,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, /* FIXME TGL+ DSI transcoders have this! */ if (!transcoder_is_dsi(cpu_transcoder)) { - tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANS_VBLANK(dev_priv, cpu_transcoder)); adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; } @@ -8198,7 +8199,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) HSYNC_START(656 - 1) | HSYNC_END(752 - 1)); intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder), VACTIVE(480 - 1) | VTOTAL(525 - 1)); - intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 611a9cd2596f..03a33ff2653a 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -233,7 +233,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s intel_de_write(dev_priv, PCH_TRANS_VTOTAL(pch_transcoder), intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), - intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder))); + intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fe61cd0dae6e..31b059acd56f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1140,7 +1140,7 @@ #define TRANS_HBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) #define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) #define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) -#define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) +#define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) #define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) #define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 5dd85943e0a1..baeedcdfdcab 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -235,7 +235,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A)); - MMIO_D(TRANS_VBLANK(TRANSCODER_A)); + MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VSYNC(TRANSCODER_A)); MMIO_D(BCLRPAT(TRANSCODER_A)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A)); @@ -244,7 +244,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B)); - MMIO_D(TRANS_VBLANK(TRANSCODER_B)); + MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VSYNC(TRANSCODER_B)); MMIO_D(BCLRPAT(TRANSCODER_B)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B)); @@ -253,7 +253,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C)); - MMIO_D(TRANS_VBLANK(TRANSCODER_C)); + MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VSYNC(TRANSCODER_C)); MMIO_D(BCLRPAT(TRANSCODER_C)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C)); @@ -262,7 +262,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP)); - MMIO_D(TRANS_VBLANK(TRANSCODER_EDP)); + MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VSYNC(TRANSCODER_EDP)); MMIO_D(BCLRPAT(TRANSCODER_EDP)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP)); -- cgit From 9cacbd237f51a9646da04c0cba08d542069b73b0 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:26 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VSYNC Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VSYNC register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/eed30cb59cc45955a88cdf951023b0e695095760.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++- drivers/gpu/drm/i915/display/intel_crt.c | 3 ++- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 6 files changed, 13 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 0ee42954054f..b267099fde8a 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -967,7 +967,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, if (is_vid_mode(intel_dsi)) { for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans), + intel_de_write(dev_priv, + TRANS_VSYNC(dev_priv, dsi_trans), VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1)); } } diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 54549d2cfcff..15569cf96c9c 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -746,7 +746,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) * Yes, this will flicker */ if (vblank_start <= vactive && vblank_end >= vtotal) { - u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); + u32 vsync = intel_de_read(dev_priv, + TRANS_VSYNC(dev_priv, cpu_transcoder)); u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1; vblank_start = vsync_start; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 87a690cf5808..776e4450e4af 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2726,7 +2726,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), VBLANK_START(crtc_vblank_start - 1) | VBLANK_END(crtc_vblank_end - 1)); - intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), VSYNC_START(adjusted_mode->crtc_vsync_start - 1) | VSYNC_END(adjusted_mode->crtc_vsync_end - 1)); @@ -2837,7 +2837,7 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1; adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1; } - tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder)); + tmp = intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder)); adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1; adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1; @@ -8201,7 +8201,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) VACTIVE(480 - 1) | VTOTAL(525 - 1)); intel_de_write(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder), VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); - intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder), + intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); intel_de_write(dev_priv, PIPESRC(pipe), PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 03a33ff2653a..9f8269705171 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -235,7 +235,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s intel_de_write(dev_priv, PCH_TRANS_VBLANK(pch_transcoder), intel_de_read(dev_priv, TRANS_VBLANK(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), - intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder))); + intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder))); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 31b059acd56f..2f87fb2d015e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1141,7 +1141,7 @@ #define TRANS_HSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) #define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) #define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) -#define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) +#define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) #define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) #define PIPESRC(pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index baeedcdfdcab..e618a16eafac 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -236,7 +236,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A)); - MMIO_D(TRANS_VSYNC(TRANSCODER_A)); + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A)); MMIO_D(BCLRPAT(TRANSCODER_A)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A)); MMIO_D(PIPESRC(TRANSCODER_A)); @@ -245,7 +245,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B)); - MMIO_D(TRANS_VSYNC(TRANSCODER_B)); + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B)); MMIO_D(BCLRPAT(TRANSCODER_B)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B)); MMIO_D(PIPESRC(TRANSCODER_B)); @@ -254,7 +254,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C)); - MMIO_D(TRANS_VSYNC(TRANSCODER_C)); + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C)); MMIO_D(BCLRPAT(TRANSCODER_C)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C)); MMIO_D(PIPESRC(TRANSCODER_C)); @@ -263,7 +263,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP)); - MMIO_D(TRANS_VSYNC(TRANSCODER_EDP)); + MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP)); MMIO_D(BCLRPAT(TRANSCODER_EDP)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M1(TRANSCODER_A)); -- cgit From d96fdbf04cece60b8c88d94b08095acafb0a2b27 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:27 +0300 Subject: drm/i915: pass dev_priv explicitly to BCLRPAT Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the BCLRPAT register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/f04d0313032d5820a14cc504af390b4b1006fae6.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crt.c | 10 ++++++---- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 4 files changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 15569cf96c9c..2660c4a53e6f 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -193,7 +193,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder, adpa |= ADPA_PIPE_SEL(crtc->pipe); if (!HAS_PCH_SPLIT(dev_priv)) - intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); + intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0); switch (mode) { case DRM_MODE_DPMS_ON: @@ -707,7 +707,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n"); - save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder)); + save_bclrpat = intel_de_read(dev_priv, + BCLRPAT(dev_priv, cpu_transcoder)); save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(dev_priv, cpu_transcoder)); vblank = intel_de_read(dev_priv, @@ -720,7 +721,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1; /* Set the border color to purple. */ - intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050); + intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050); if (DISPLAY_VER(dev_priv) != 2) { u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); @@ -800,7 +801,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) } /* Restore previous settings */ - intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat); + intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), + save_bclrpat); return status; } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 776e4450e4af..49f7ac0f7997 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1870,7 +1870,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) /* Border color in case we don't scale up to the full screen. Black by * default, change to something else for debugging. */ - intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0); + intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0); } /* Prefer intel_encoder_is_combo() */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 2f87fb2d015e..39f92739b822 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1142,7 +1142,7 @@ #define TRANS_VTOTAL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) #define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) #define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) -#define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) +#define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) #define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) #define PIPESRC(pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) #define TRANS_MULT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index e618a16eafac..5e1ef52922cc 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -237,7 +237,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A)); - MMIO_D(BCLRPAT(TRANSCODER_A)); + MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A)); MMIO_D(PIPESRC(TRANSCODER_A)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B)); @@ -246,7 +246,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B)); - MMIO_D(BCLRPAT(TRANSCODER_B)); + MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B)); MMIO_D(PIPESRC(TRANSCODER_B)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C)); @@ -255,7 +255,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C)); - MMIO_D(BCLRPAT(TRANSCODER_C)); + MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C)); MMIO_D(PIPESRC(TRANSCODER_C)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP)); @@ -264,7 +264,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP)); - MMIO_D(BCLRPAT(TRANSCODER_EDP)); + MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M1(TRANSCODER_A)); MMIO_D(PIPE_DATA_N1(TRANSCODER_A)); -- cgit From 8925350cd3514fdad88de6d94c79f4aa6b713564 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:28 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_VSYNCSHIFT Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_VSYNCSHIFT register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/8103a31fbf6da725e6aed3bb86c15bbd581164fb.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 3 ++- drivers/gpu/drm/i915/display/intel_display.c | 3 ++- drivers/gpu/drm/i915/display/intel_pch_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 5 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index b267099fde8a..0625c4d5ee0b 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -982,7 +982,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder, if (is_vid_mode(intel_dsi)) { for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans), + intel_de_write(dev_priv, + TRANS_VSYNCSHIFT(dev_priv, dsi_trans), vsync_shift); } } diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 49f7ac0f7997..993eb0935f6b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2707,7 +2707,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta } if (DISPLAY_VER(dev_priv) >= 4) - intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder), + intel_de_write(dev_priv, + TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder), vsyncshift); intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, cpu_transcoder), diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 9f8269705171..6a45bc1651c3 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -237,7 +237,7 @@ static void ilk_pch_transcoder_set_timings(const struct intel_crtc_state *crtc_s intel_de_write(dev_priv, PCH_TRANS_VSYNC(pch_transcoder), intel_de_read(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder))); intel_de_write(dev_priv, PCH_TRANS_VSYNCSHIFT(pch_transcoder), - intel_de_read(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder))); + intel_de_read(dev_priv, TRANS_VSYNCSHIFT(dev_priv, cpu_transcoder))); } static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 39f92739b822..5f6f2bb06f35 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1143,7 +1143,7 @@ #define TRANS_VBLANK(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) #define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) #define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) -#define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) +#define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) #define PIPESRC(pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) #define TRANS_MULT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 5e1ef52922cc..5abae7df0bfe 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -238,7 +238,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A)); MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A)); - MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_A)); + MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A)); MMIO_D(PIPESRC(TRANSCODER_A)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B)); @@ -247,7 +247,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B)); MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B)); - MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_B)); + MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B)); MMIO_D(PIPESRC(TRANSCODER_B)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C)); @@ -256,7 +256,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C)); MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C)); - MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_C)); + MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C)); MMIO_D(PIPESRC(TRANSCODER_C)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP)); @@ -265,7 +265,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP)); MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP)); - MMIO_D(TRANS_VSYNCSHIFT(TRANSCODER_EDP)); + MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M1(TRANSCODER_A)); MMIO_D(PIPE_DATA_N1(TRANSCODER_A)); MMIO_D(PIPE_DATA_M2(TRANSCODER_A)); -- cgit From 454a498978b113af11585a843b2f7920ac8e4449 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:29 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPESRC Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPESRC register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/ac1959b7038d6fedb4777dcf2b961de901fb8880.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane.c | 2 +- drivers/gpu/drm/i915/display/intel_display.c | 6 +++--- drivers/gpu/drm/i915/gvt/fb_decoder.c | 6 +++--- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c index 5c8778865156..864d94406894 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane.c +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c @@ -1053,7 +1053,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc, drm_WARN_ON(&dev_priv->drm, offset != 0); - val = intel_de_read(dev_priv, PIPESRC(pipe)); + val = intel_de_read(dev_priv, PIPESRC(dev_priv, pipe)); fb->width = REG_FIELD_GET(PIPESRC_WIDTH_MASK, val) + 1; fb->height = REG_FIELD_GET(PIPESRC_HEIGHT_MASK, val) + 1; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 993eb0935f6b..81ae72648e8e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2784,7 +2784,7 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state) /* pipesrc controls the size that is scaled from, which should * always be the user's requested size. */ - intel_de_write(dev_priv, PIPESRC(pipe), + intel_de_write(dev_priv, PIPESRC(dev_priv, pipe), PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1)); } @@ -2878,7 +2878,7 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(dev); u32 tmp; - tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe)); + tmp = intel_de_read(dev_priv, PIPESRC(dev_priv, crtc->pipe)); drm_rect_init(&pipe_config->pipe_src, 0, 0, REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, @@ -8204,7 +8204,7 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) VBLANK_START(480 - 1) | VBLANK_END(525 - 1)); intel_de_write(dev_priv, TRANS_VSYNC(dev_priv, cpu_transcoder), VSYNC_START(490 - 1) | VSYNC_END(492 - 1)); - intel_de_write(dev_priv, PIPESRC(pipe), + intel_de_write(dev_priv, PIPESRC(dev_priv, pipe), PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1)); intel_de_write(dev_priv, FP0(pipe), fp); diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 0afde865a7de..c454e25b2b0f 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -267,11 +267,11 @@ int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu, (_PRI_PLANE_STRIDE_MASK >> 6) : _PRI_PLANE_STRIDE_MASK, plane->bpp); - plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> + plane->width = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & _PIPE_H_SRCSZ_MASK) >> _PIPE_H_SRCSZ_SHIFT; plane->width += 1; - plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & - _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; + plane->height = (vgpu_vreg_t(vgpu, PIPESRC(dev_priv, pipe)) & + _PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT; plane->height += 1; /* raw height is one minus the real value */ val = vgpu_vreg_t(vgpu, DSPTILEOFF(dev_priv, pipe)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5f6f2bb06f35..8e312aa8ca71 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1144,7 +1144,7 @@ #define TRANS_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) #define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) #define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) -#define PIPESRC(pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) +#define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) #define TRANS_MULT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) /* VRR registers */ diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 5abae7df0bfe..ff561a1e0fd3 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -239,7 +239,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A)); MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_A)); - MMIO_D(PIPESRC(TRANSCODER_A)); + MMIO_D(PIPESRC(dev_priv, TRANSCODER_A)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_B)); @@ -248,7 +248,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_B)); MMIO_D(BCLRPAT(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_B)); - MMIO_D(PIPESRC(TRANSCODER_B)); + MMIO_D(PIPESRC(dev_priv, TRANSCODER_B)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_C)); @@ -257,7 +257,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_C)); MMIO_D(BCLRPAT(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_C)); - MMIO_D(PIPESRC(TRANSCODER_C)); + MMIO_D(PIPESRC(dev_priv, TRANSCODER_C)); MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_EDP)); -- cgit From 5734c976717d4d7027c387d167c19ba52d3498ed Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:30 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_MULT Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_MULT register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/7ea79208a81fd5c3b021bcd8e1f9f90607716d82.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 6 +++--- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 81ae72648e8e..e7ee4970e306 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1646,7 +1646,7 @@ static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_sta intel_vrr_set_transcoder_timings(crtc_state); if (cpu_transcoder != TRANSCODER_EDP) - intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder), + intel_de_write(dev_priv, TRANS_MULT(dev_priv, cpu_transcoder), crtc_state->pixel_multiplier - 1); hsw_set_frame_start_delay(crtc_state); @@ -3861,7 +3861,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, !transcoder_is_dsi(pipe_config->cpu_transcoder)) { pipe_config->pixel_multiplier = intel_de_read(dev_priv, - TRANS_MULT(pipe_config->cpu_transcoder)) + 1; + TRANS_MULT(dev_priv, pipe_config->cpu_transcoder)) + 1; } else { pipe_config->pixel_multiplier = 1; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8e312aa8ca71..e72be82445ca 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1145,7 +1145,7 @@ #define BCLRPAT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) #define TRANS_VSYNCSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) #define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) -#define TRANS_MULT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) +#define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) /* VRR registers */ #define _TRANS_VRR_CTL_A 0x60420 diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index ff561a1e0fd3..600e89148f77 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -506,9 +506,9 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(GAMMA_MODE(PIPE_A)); MMIO_D(GAMMA_MODE(PIPE_B)); MMIO_D(GAMMA_MODE(PIPE_C)); - MMIO_D(TRANS_MULT(TRANSCODER_A)); - MMIO_D(TRANS_MULT(TRANSCODER_B)); - MMIO_D(TRANS_MULT(TRANSCODER_C)); + MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_A)); + MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_B)); + MMIO_D(TRANS_MULT(dev_priv, TRANSCODER_C)); MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_A)); MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_B)); MMIO_D(HSW_TVIDEO_DIP_CTL(dev_priv, TRANSCODER_C)); -- cgit From 8232a3bfba3ea3ee41d49ee0353ae7db30ee798c Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:31 +0300 Subject: drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_EN Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_HOTPLUG_EN register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/3f4c3fb108f62db5d9b6bdabd0fbeb6650e14e82.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crt.c | 2 +- drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 2660c4a53e6f..b7eab52b64b6 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -603,7 +603,7 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) CRT_HOTPLUG_FORCE_DETECT, CRT_HOTPLUG_FORCE_DETECT); /* wait for FORCE_DETECT to go off */ - if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN, + if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN(dev_priv), CRT_HOTPLUG_FORCE_DETECT, 1000)) drm_dbg_kms(&dev_priv->drm, "timed out waiting for FORCE_DETECT to go off"); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c index d270bb7b9462..90fe5f8538e1 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c @@ -186,7 +186,8 @@ void i915_hotplug_interrupt_update_locked(struct drm_i915_private *dev_priv, lockdep_assert_held(&dev_priv->irq_lock); drm_WARN_ON(&dev_priv->drm, bits & ~mask); - intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN, mask, bits); + intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_EN(dev_priv), mask, + bits); } /** diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e72be82445ca..3b1fc58b95c2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1297,7 +1297,7 @@ /* Hotplug control (945+ only) */ -#define PORT_HOTPLUG_EN _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) +#define PORT_HOTPLUG_EN(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61110) #define PORTB_HOTPLUG_INT_EN (1 << 29) #define PORTC_HOTPLUG_INT_EN (1 << 28) #define PORTD_HOTPLUG_INT_EN (1 << 27) -- cgit From 201008c44fd745e44f1fc6d7bbc235012a8995af Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:32 +0300 Subject: drm/i915: pass dev_priv explicitly to PORT_HOTPLUG_STAT Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PORT_HOTPLUG_STAT register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/9a47bba4ab8fa4b1a8e8ceea2ba5301bed54805d.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/g4x_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_crt.c | 5 +++-- drivers/gpu/drm/i915/display/intel_display_irq.c | 2 +- drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 9 ++++++--- drivers/gpu/drm/i915/i915_irq.c | 5 +++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 6 files changed, 15 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 06ec04e667e3..40fee8380a81 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -1228,7 +1228,7 @@ static bool g4x_digital_port_connected(struct intel_encoder *encoder) return false; } - return intel_de_read(dev_priv, PORT_HOTPLUG_STAT) & bit; + return intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv)) & bit; } static bool ilk_digital_port_connected(struct intel_encoder *encoder) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index b7eab52b64b6..808fa8afb164 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -609,12 +609,13 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector) "timed out waiting for FORCE_DETECT to go off"); } - stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT); + stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv)); if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) ret = true; /* clear the interrupt we just generated, if any */ - intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); + intel_de_write(dev_priv, PORT_HOTPLUG_STAT(dev_priv), + CRT_HOTPLUG_INT_STATUS); i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0); diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index d2d70b81aef9..bb57fa65c7be 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1378,7 +1378,7 @@ void vlv_display_irq_reset(struct drm_i915_private *dev_priv) intel_uncore_write(uncore, DPINVGTT, DPINVGTT_STATUS_MASK_VLV); i915_hotplug_interrupt_update_locked(dev_priv, 0xffffffff, 0); - intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT, 0, 0); + intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT(dev_priv), 0, 0); i9xx_pipestat_irq_reset(dev_priv); diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c index 90fe5f8538e1..a1f07ee69a86 100644 --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c @@ -435,18 +435,21 @@ u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) * bits can itself generate a new hotplug interrupt :( */ for (i = 0; i < 10; i++) { - u32 tmp = intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT) & hotplug_status_mask; + u32 tmp = intel_uncore_read(&dev_priv->uncore, + PORT_HOTPLUG_STAT(dev_priv)) & hotplug_status_mask; if (tmp == 0) return hotplug_status; hotplug_status |= tmp; - intel_uncore_write(&dev_priv->uncore, PORT_HOTPLUG_STAT, hotplug_status); + intel_uncore_write(&dev_priv->uncore, + PORT_HOTPLUG_STAT(dev_priv), + hotplug_status); } drm_WARN_ONCE(&dev_priv->drm, 1, "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", - intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT)); + intel_uncore_read(&dev_priv->uncore, PORT_HOTPLUG_STAT(dev_priv))); return hotplug_status; } diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 678d632ed043..8059ac7e15fe 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1040,7 +1040,8 @@ static void i915_irq_reset(struct drm_i915_private *dev_priv) if (I915_HAS_HOTPLUG(dev_priv)) { i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); - intel_uncore_rmw(&dev_priv->uncore, PORT_HOTPLUG_STAT, 0, 0); + intel_uncore_rmw(&dev_priv->uncore, + PORT_HOTPLUG_STAT(dev_priv), 0, 0); } i9xx_pipestat_irq_reset(dev_priv); @@ -1149,7 +1150,7 @@ static void i965_irq_reset(struct drm_i915_private *dev_priv) struct intel_uncore *uncore = &dev_priv->uncore; i915_hotplug_interrupt_update(dev_priv, 0xffffffff, 0); - intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT, 0, 0); + intel_uncore_rmw(uncore, PORT_HOTPLUG_STAT(dev_priv), 0, 0); i9xx_pipestat_irq_reset(dev_priv); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3b1fc58b95c2..710078a6bf3f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1327,7 +1327,7 @@ #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2) #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2) -#define PORT_HOTPLUG_STAT _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) +#define PORT_HOTPLUG_STAT(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61114) /* HDMI/DP bits are g4x+ */ #define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 27) #define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28) -- cgit From 62148804b6e2ff49d19f58b34f247d2974061dc8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:33 +0300 Subject: drm/i915: pass dev_priv explicitly to PFIT_CONTROL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PFIT_CONTROL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/fad44d3d987d914c83844cdf172adaa19772e035.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 11 ++++++----- drivers/gpu/drm/i915/display/intel_lvds.c | 2 +- drivers/gpu/drm/i915/display/intel_overlay.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 4 files changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e7ee4970e306..49672694293f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1861,12 +1861,13 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) * according to register description and PRM. */ drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE); + intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE); assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); intel_de_write(dev_priv, PFIT_PGM_RATIOS, crtc_state->gmch_pfit.pgm_ratios); - intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control); + intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), + crtc_state->gmch_pfit.control); /* Border color in case we don't scale up to the full screen. Black by * default, change to something else for debugging. */ @@ -2195,8 +2196,8 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state) assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder); drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n", - intel_de_read(dev_priv, PFIT_CONTROL)); - intel_de_write(dev_priv, PFIT_CONTROL, 0); + intel_de_read(dev_priv, PFIT_CONTROL(dev_priv))); + intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), 0); } static void i9xx_crtc_disable(struct intel_atomic_state *state, @@ -2974,7 +2975,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) if (!i9xx_has_pfit(dev_priv)) return; - tmp = intel_de_read(dev_priv, PFIT_CONTROL); + tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)); if (!(tmp & PFIT_ENABLE)) return; diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c index 891777481dd9..9f018503d4fd 100644 --- a/drivers/gpu/drm/i915/display/intel_lvds.c +++ b/drivers/gpu/drm/i915/display/intel_lvds.c @@ -148,7 +148,7 @@ static void intel_lvds_get_config(struct intel_encoder *encoder, /* gen2/3 store dither state in pfit control, needs to match */ if (DISPLAY_VER(dev_priv) < 4) { - tmp = intel_de_read(dev_priv, PFIT_CONTROL); + tmp = intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)); crtc_state->gmch_pfit.control |= tmp & PFIT_PANEL_8TO6_DITHER_ENABLE; } diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index b97087f8e311..b81046a6d369 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -950,7 +950,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) } else { u32 tmp; - if (intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_VERT_AUTO_SCALE) + if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE) tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); else tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 710078a6bf3f..ca3d43e5061a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1507,7 +1507,7 @@ #define VIDEO_DIP_ENABLE_AS_ADL REG_BIT(23) /* Panel fitting */ -#define PFIT_CONTROL _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) +#define PFIT_CONTROL(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61230) #define PFIT_ENABLE REG_BIT(31) #define PFIT_PIPE_MASK REG_GENMASK(30, 29) /* 965+ */ #define PFIT_PIPE(pipe) REG_FIELD_PREP(PFIT_PIPE_MASK, (pipe)) -- cgit From 23501e567a71cd8fa2eba4ef0572c2e938abeb01 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:34 +0300 Subject: drm/i915: pass dev_priv explicitly to PFIT_PGM_RATIOS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PFIT_PGM_RATIOS register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/8453205c9619bb8453bf4904d0c5bb868f614fc4.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/display/intel_overlay.c | 5 +++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 49672694293f..1e2ddae5ba94 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1864,7 +1864,7 @@ static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state) intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_ENABLE); assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); - intel_de_write(dev_priv, PFIT_PGM_RATIOS, + intel_de_write(dev_priv, PFIT_PGM_RATIOS(dev_priv), crtc_state->gmch_pfit.pgm_ratios); intel_de_write(dev_priv, PFIT_CONTROL(dev_priv), crtc_state->gmch_pfit.control); @@ -2990,7 +2990,7 @@ static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state) crtc_state->gmch_pfit.control = tmp; crtc_state->gmch_pfit.pgm_ratios = - intel_de_read(dev_priv, PFIT_PGM_RATIOS); + intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv)); } static enum intel_output_format diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index b81046a6d369..28bf89b77e34 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -943,7 +943,7 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) * line with the intel documentation for the i965 */ if (DISPLAY_VER(dev_priv) >= 4) { - u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); + u32 tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv)); /* on i965 use the PGM reg to read out the autoscaler values */ ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK_965, tmp); @@ -953,7 +953,8 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE) tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); else - tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS); + tmp = intel_de_read(dev_priv, + PFIT_PGM_RATIOS(dev_priv)); ratio = REG_FIELD_GET(PFIT_VERT_SCALE_MASK, tmp); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ca3d43e5061a..48ef787c7349 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1528,7 +1528,7 @@ #define PFIT_HORIZ_AUTO_SCALE REG_BIT(5) /* pre-965 */ #define PFIT_PANEL_8TO6_DITHER_ENABLE REG_BIT(3) /* pre-965 */ -#define PFIT_PGM_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) +#define PFIT_PGM_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61234) #define PFIT_VERT_SCALE_MASK REG_GENMASK(31, 20) /* pre-965 */ #define PFIT_VERT_SCALE(x) REG_FIELD_PREP(PFIT_VERT_SCALE_MASK, (x)) #define PFIT_HORIZ_SCALE_MASK REG_GENMASK(15, 4) /* pre-965 */ -- cgit From 6d3a843b0efb4ddfc71b4c67053714e37b98b337 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:35 +0300 Subject: drm/i915: pass dev_priv explicitly to PFIT_AUTO_RATIOS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PFIT_AUTO_RATIOS register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/148e8c66d37b5eb3077eef44018591d8b6a57937.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_overlay.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c index 28bf89b77e34..06b1122ec13e 100644 --- a/drivers/gpu/drm/i915/display/intel_overlay.c +++ b/drivers/gpu/drm/i915/display/intel_overlay.c @@ -951,7 +951,8 @@ static void update_pfit_vscale_ratio(struct intel_overlay *overlay) u32 tmp; if (intel_de_read(dev_priv, PFIT_CONTROL(dev_priv)) & PFIT_VERT_AUTO_SCALE) - tmp = intel_de_read(dev_priv, PFIT_AUTO_RATIOS); + tmp = intel_de_read(dev_priv, + PFIT_AUTO_RATIOS(dev_priv)); else tmp = intel_de_read(dev_priv, PFIT_PGM_RATIOS(dev_priv)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 48ef787c7349..db41a6b88b63 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1536,7 +1536,7 @@ #define PFIT_VERT_SCALE_MASK_965 REG_GENMASK(28, 16) /* 965+ */ #define PFIT_HORIZ_SCALE_MASK_965 REG_GENMASK(12, 0) /* 965+ */ -#define PFIT_AUTO_RATIOS _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) +#define PFIT_AUTO_RATIOS(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x61238) #define PCH_GTC_CTL _MMIO(0xe7000) #define PCH_GTC_ENABLE (1 << 31) -- cgit From 984b61c35866fc0729801b74c3ce03812a121368 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:36 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANSCONF Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANSCONF register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/9afc96be1cbe4514cdca701ab434b4c7aa3a55ba.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 12 ++--- drivers/gpu/drm/i915/display/intel_crt.c | 11 +++-- drivers/gpu/drm/i915/display/intel_display.c | 52 ++++++++++++---------- .../drm/i915/display/intel_display_power_well.c | 8 ++-- drivers/gpu/drm/i915/display/intel_drrs.c | 2 +- drivers/gpu/drm/i915/display/intel_fdi.c | 6 +-- drivers/gpu/drm/i915/display/intel_pch_display.c | 7 +-- drivers/gpu/drm/i915/display/vlv_dsi.c | 3 +- drivers/gpu/drm/i915/gvt/display.c | 12 ++--- drivers/gpu/drm/i915/gvt/handlers.c | 12 +++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++-- 12 files changed, 76 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 0625c4d5ee0b..9beb94494b2b 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -1013,10 +1013,11 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder) for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE); + intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), 0, + TRANSCONF_ENABLE); /* wait for transcoder to be enabled */ - if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans), + if (intel_de_wait_for_set(dev_priv, TRANSCONF(dev_priv, dsi_trans), TRANSCONF_STATE_ENABLE, 10)) drm_err(&dev_priv->drm, "DSI transcoder not enabled\n"); @@ -1279,10 +1280,11 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder) dsi_trans = dsi_port_to_transcoder(port); /* disable transcoder */ - intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0); + intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), + TRANSCONF_ENABLE, 0); /* wait for transcoder to be disabled */ - if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans), + if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, dsi_trans), TRANSCONF_STATE_ENABLE, 50)) drm_err(&dev_priv->drm, "DSI trancoder not disabled\n"); @@ -1714,7 +1716,7 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, goto out; } - tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans)); + tmp = intel_de_read(dev_priv, TRANSCONF(dev_priv, dsi_trans)); ret = tmp & TRANSCONF_ENABLE; } out: diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index 808fa8afb164..d4f16d894eda 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -725,11 +725,13 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050); if (DISPLAY_VER(dev_priv) != 2) { - u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); + u32 transconf = intel_de_read(dev_priv, + TRANSCONF(dev_priv, cpu_transcoder)); - intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), + intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), transconf | TRANSCONF_FORCE_BORDER); - intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); + intel_de_posting_read(dev_priv, + TRANSCONF(dev_priv, cpu_transcoder)); /* Wait for next Vblank to substitue * border color for Color info */ intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe)); @@ -738,7 +740,8 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) connector_status_connected : connector_status_disconnected; - intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf); + intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), + transconf); } else { bool restore_vblank = false; int count, detect; diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 1e2ddae5ba94..9434eba91839 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -307,7 +307,7 @@ intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state) enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; /* Wait for the Pipe State to go off */ - if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder), + if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), TRANSCONF_STATE_ENABLE, 100)) drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n"); } else { @@ -329,7 +329,8 @@ void assert_transcoder(struct drm_i915_private *dev_priv, power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain); if (wakeref) { - u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); + u32 val = intel_de_read(dev_priv, + TRANSCONF(dev_priv, cpu_transcoder)); cur_state = !!(val & TRANSCONF_ENABLE); intel_display_power_put(dev_priv, power_domain, wakeref); @@ -453,7 +454,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) clear, set); } - val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); + val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); if (val & TRANSCONF_ENABLE) { /* we keep both pipes enabled on 830 */ drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv)); @@ -468,9 +469,9 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) TRANSCONF_PIXEL_COUNT_SCALING_X4); } - intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), + intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val | TRANSCONF_ENABLE); - intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); + intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); /* * Until the pipe starts PIPEDSL reads will return a stale value, @@ -499,7 +500,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) */ assert_planes_disabled(crtc); - val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); + val = intel_de_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); if ((val & TRANSCONF_ENABLE) == 0) return; @@ -519,7 +520,7 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state) old_crtc_state->dsc.compression_enable) val &= ~TRANSCONF_PIXEL_COUNT_SCALING_MASK; - intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); + intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); if (DISPLAY_VER(dev_priv) >= 12) intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, cpu_transcoder), @@ -2799,9 +2800,11 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) - return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; + return intel_de_read(dev_priv, + TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW; else - return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; + return intel_de_read(dev_priv, + TRANSCONF(dev_priv, cpu_transcoder)) & TRANSCONF_INTERLACE_MASK; } static void intel_get_transcoder_timings(struct intel_crtc *crtc, @@ -2952,8 +2955,8 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); - intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); - intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); + intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); + intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); } static bool i9xx_has_pfit(struct drm_i915_private *dev_priv) @@ -3035,7 +3038,8 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, ret = false; - tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); if (!(tmp & TRANSCONF_ENABLE)) goto out; @@ -3182,8 +3186,8 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state) val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay); - intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); - intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); + intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); + intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); } static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) @@ -3212,8 +3216,8 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state) crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW; - intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); - intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder)); + intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), val); + intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, cpu_transcoder)); } static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) @@ -3408,7 +3412,8 @@ static bool ilk_get_pipe_config(struct intel_crtc *crtc, pipe_config->shared_dpll = NULL; ret = false; - tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); if (!(tmp & TRANSCONF_ENABLE)) goto out; @@ -3721,7 +3726,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, pipe_config->pch_pfit.force_thru = true; } - tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); return tmp & TRANSCONF_ENABLE; } @@ -3827,7 +3833,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, if (IS_HASWELL(dev_priv)) { u32 tmp = intel_de_read(dev_priv, - TRANSCONF(pipe_config->cpu_transcoder)); + TRANSCONF(dev_priv, pipe_config->cpu_transcoder)); if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW) pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444; @@ -8238,8 +8244,8 @@ void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) udelay(150); /* wait for warmup */ } - intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE); - intel_de_posting_read(dev_priv, TRANSCONF(pipe)); + intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), TRANSCONF_ENABLE); + intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe)); intel_wait_for_pipe_scanline_moving(crtc); } @@ -8262,8 +8268,8 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) drm_WARN_ON(&dev_priv->drm, intel_de_read(dev_priv, CURCNTR(dev_priv, PIPE_B)) & MCURSOR_MODE_MASK); - intel_de_write(dev_priv, TRANSCONF(pipe), 0); - intel_de_posting_read(dev_priv, TRANSCONF(pipe)); + intel_de_write(dev_priv, TRANSCONF(dev_priv, pipe), 0); + intel_de_posting_read(dev_priv, TRANSCONF(dev_priv, pipe)); intel_wait_for_pipe_scanline_stopped(crtc); diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index 3b6cb237d80a..919f712fef13 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -1044,9 +1044,9 @@ static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - if ((intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE) == 0) + if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE) == 0) i830_enable_pipe(dev_priv, PIPE_A); - if ((intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE) == 0) + if ((intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE) == 0) i830_enable_pipe(dev_priv, PIPE_B); } @@ -1060,8 +1060,8 @@ static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv, static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv, struct i915_power_well *power_well) { - return intel_de_read(dev_priv, TRANSCONF(PIPE_A)) & TRANSCONF_ENABLE && - intel_de_read(dev_priv, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; + return intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_A)) & TRANSCONF_ENABLE && + intel_de_read(dev_priv, TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; } static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c index 597f8bd6aa1a..5250622f1479 100644 --- a/drivers/gpu/drm/i915/display/intel_drrs.c +++ b/drivers/gpu/drm/i915/display/intel_drrs.c @@ -85,7 +85,7 @@ intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc, else bit = TRANSCONF_REFRESH_RATE_ALT_ILK; - intel_de_rmw(dev_priv, TRANSCONF(cpu_transcoder), + intel_de_rmw(dev_priv, TRANSCONF(dev_priv, cpu_transcoder), bit, refresh_rate == DRRS_REFRESH_RATE_LOW ? bit : 0); } diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 295a0f24ebbf..8b17b8ad71c3 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -1034,7 +1034,7 @@ void ilk_fdi_pll_enable(const struct intel_crtc_state *crtc_state) temp = intel_de_read(dev_priv, reg); temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); - temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11; + temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; intel_de_write(dev_priv, reg, temp | FDI_RX_PLL_ENABLE); intel_de_posting_read(dev_priv, reg); @@ -1090,7 +1090,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc) reg = FDI_RX_CTL(pipe); temp = intel_de_read(dev_priv, reg); temp &= ~(0x7 << 16); - temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11; + temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; intel_de_write(dev_priv, reg, temp & ~FDI_RX_ENABLE); intel_de_posting_read(dev_priv, reg); @@ -1116,7 +1116,7 @@ void ilk_fdi_disable(struct intel_crtc *crtc) } /* BPC in FDI rx is consistent with that in TRANSCONF */ temp &= ~(0x07 << 16); - temp |= (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) << 11; + temp |= (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) << 11; intel_de_write(dev_priv, reg, temp); intel_de_posting_read(dev_priv, reg); diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c index 6a45bc1651c3..0d48b9bec29c 100644 --- a/drivers/gpu/drm/i915/display/intel_pch_display.c +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c @@ -271,7 +271,7 @@ static void ilk_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) reg = PCH_TRANSCONF(pipe); val = intel_de_read(dev_priv, reg); - pipeconf_val = intel_de_read(dev_priv, TRANSCONF(pipe)); + pipeconf_val = intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)); if (HAS_PCH_IBX(dev_priv)) { /* Configure frame start delay to match the CPU */ @@ -413,7 +413,7 @@ void ilk_pch_enable(struct intel_atomic_state *state, intel_crtc_has_dp_encoder(crtc_state)) { const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; - u32 bpc = (intel_de_read(dev_priv, TRANSCONF(pipe)) & TRANSCONF_BPC_MASK) >> 5; + u32 bpc = (intel_de_read(dev_priv, TRANSCONF(dev_priv, pipe)) & TRANSCONF_BPC_MASK) >> 5; i915_reg_t reg = TRANS_DP_CTL(pipe); enum port port; @@ -557,7 +557,8 @@ static void lpt_enable_pch_transcoder(const struct intel_crtc_state *crtc_state) intel_de_write(dev_priv, TRANS_CHICKEN2(PIPE_A), val); val = TRANS_ENABLE; - pipeconf_val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)); + pipeconf_val = intel_de_read(dev_priv, + TRANSCONF(dev_priv, cpu_transcoder)); if ((pipeconf_val & TRANSCONF_INTERLACE_MASK_HSW) == TRANSCONF_INTERLACE_IF_ID_ILK) val |= TRANS_INTERLACE_INTERLACED; diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c index ee9923c7b115..eae5b5e09aa8 100644 --- a/drivers/gpu/drm/i915/display/vlv_dsi.c +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c @@ -972,7 +972,8 @@ static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, */ if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && port == PORT_C) - enabled = intel_de_read(display, TRANSCONF(PIPE_B)) & TRANSCONF_ENABLE; + enabled = intel_de_read(display, + TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; /* Try command mode if video mode not enabled */ if (!enabled) { diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index eaa92d392189..ad21b8f65d6b 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu) { struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; - if (!(vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_EDP)) & TRANSCONF_ENABLE)) + if (!(vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_EDP)) & TRANSCONF_ENABLE)) return 0; if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE)) @@ -83,7 +83,7 @@ int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) pipe < PIPE_A || pipe >= I915_MAX_PIPES)) return -EINVAL; - if (vgpu_vreg_t(vgpu, TRANSCONF(pipe)) & TRANSCONF_ENABLE) + if (vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) & TRANSCONF_ENABLE) return 1; if (edp_pipe_is_enabled(vgpu) && @@ -191,7 +191,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) GEN8_DE_PORT_HOTPLUG(HPD_PORT_C)); for_each_pipe(dev_priv, pipe) { - vgpu_vreg_t(vgpu, TRANSCONF(pipe)) &= + vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, pipe)) &= ~(TRANSCONF_ENABLE | TRANSCONF_STATE_ENABLE); vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) &= ~DISP_ENABLE; vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE; @@ -252,8 +252,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) * TRANSCODER_A can be enabled. PORT_x depends on the input of * setup_virtual_dp_monitor. */ - vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; - vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; + vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE; + vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; /* * Golden M/N are calculated based on: @@ -510,7 +510,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, CURCNTR(dev_priv, pipe)) |= MCURSOR_MODE_DISABLE; } - vgpu_vreg_t(vgpu, TRANSCONF(TRANSCODER_A)) |= TRANSCONF_ENABLE; + vgpu_vreg_t(vgpu, TRANSCONF(dev_priv, TRANSCODER_A)) |= TRANSCONF_ENABLE; } static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 45b1dbd5881a..31ed96be91f3 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -2269,10 +2269,14 @@ static int init_generic_mmio_info(struct intel_gvt *gvt) MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL); /* display */ - MMIO_DH(TRANSCONF(TRANSCODER_A), D_ALL, NULL, pipeconf_mmio_write); - MMIO_DH(TRANSCONF(TRANSCODER_B), D_ALL, NULL, pipeconf_mmio_write); - MMIO_DH(TRANSCONF(TRANSCODER_C), D_ALL, NULL, pipeconf_mmio_write); - MMIO_DH(TRANSCONF(TRANSCODER_EDP), D_ALL, NULL, pipeconf_mmio_write); + MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_A), D_ALL, NULL, + pipeconf_mmio_write); + MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_B), D_ALL, NULL, + pipeconf_mmio_write); + MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_C), D_ALL, NULL, + pipeconf_mmio_write); + MMIO_DH(TRANSCONF(dev_priv, TRANSCODER_EDP), D_ALL, NULL, + pipeconf_mmio_write); MMIO_DH(DSPSURF(dev_priv, PIPE_A), D_ALL, NULL, pri_surf_mmio_write); MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, reg50080_mmio_write); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index db41a6b88b63..21cf16240070 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1795,7 +1795,7 @@ #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff -#define TRANSCONF(trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) +#define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) #define PIPEDSL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) #define PIPEFRAME(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 600e89148f77..436d4a2eccd7 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -130,10 +130,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPEDSL(PIPE_B)); MMIO_D(PIPEDSL(PIPE_C)); MMIO_D(PIPEDSL(_PIPE_EDP)); - MMIO_D(TRANSCONF(TRANSCODER_A)); - MMIO_D(TRANSCONF(TRANSCODER_B)); - MMIO_D(TRANSCONF(TRANSCODER_C)); - MMIO_D(TRANSCONF(TRANSCODER_EDP)); + MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A)); + MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B)); + MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C)); + MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPESTAT(PIPE_A)); MMIO_D(PIPESTAT(PIPE_B)); MMIO_D(PIPESTAT(PIPE_C)); -- cgit From 840e748285cbd5cdde32f9a4d1a075cdcafdc6a3 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:37 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPEDSL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPEDSL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/53b751f5a883318d44b690284d2e9d5a43fba860.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_crt.c | 6 +++--- drivers/gpu/drm/i915/display/intel_hdmi.c | 3 ++- drivers/gpu/drm/i915/display/intel_vblank.c | 7 ++++--- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 5 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index d4f16d894eda..835c8b844494 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -771,9 +771,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) /* * Wait for the border to be displayed */ - while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive) + while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive) ; - while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample) + while ((dsl = intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe))) <= vsample) ; /* * Watch ST00 for an entire scanline @@ -786,7 +786,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE); if (st00 & (1 << 4)) detect++; - } while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl)); + } while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl)); /* restore vblank if necessary */ if (restore_vblank) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 06ec9ce7fe1c..7704ead5002d 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -1476,7 +1476,8 @@ static int kbl_repositioning_enc_en_signal(struct intel_connector *connector, int ret; for (;;) { - scanline = intel_de_read(dev_priv, PIPEDSL(crtc->pipe)); + scanline = intel_de_read(dev_priv, + PIPEDSL(dev_priv, crtc->pipe)); if (scanline > 100 && scanline < 200) break; usleep_range(25, 50); diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 789b2db4d95e..12913bbdf123 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -248,7 +248,7 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) vtotal = intel_mode_vtotal(mode); - position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK; + position = intel_de_read_fw(dev_priv, PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK; /* * On HSW, the DSL reg (0x70000) appears to return 0 if we @@ -267,7 +267,8 @@ static int __intel_get_crtc_scanline(struct intel_crtc *crtc) for (i = 0; i < 100; i++) { udelay(1); - temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & PIPEDSL_LINE_MASK; + temp = intel_de_read_fw(dev_priv, + PIPEDSL(dev_priv, pipe)) & PIPEDSL_LINE_MASK; if (temp != position) { position = temp; break; @@ -474,7 +475,7 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc) static bool pipe_scanline_is_moving(struct drm_i915_private *dev_priv, enum pipe pipe) { - i915_reg_t reg = PIPEDSL(pipe); + i915_reg_t reg = PIPEDSL(dev_priv, pipe); u32 line1, line2; line1 = intel_de_read(dev_priv, reg) & PIPEDSL_LINE_MASK; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 21cf16240070..c19d9863db65 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1796,7 +1796,7 @@ #define PIPESTAT_INT_STATUS_MASK 0x0000ffff #define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) -#define PIPEDSL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) +#define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) #define PIPEFRAME(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 436d4a2eccd7..6a37f790c753 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -126,10 +126,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(_MMIO(0x650b4)); MMIO_D(_MMIO(0xc4040)); MMIO_D(DERRMR); - MMIO_D(PIPEDSL(PIPE_A)); - MMIO_D(PIPEDSL(PIPE_B)); - MMIO_D(PIPEDSL(PIPE_C)); - MMIO_D(PIPEDSL(_PIPE_EDP)); + MMIO_D(PIPEDSL(dev_priv, PIPE_A)); + MMIO_D(PIPEDSL(dev_priv, PIPE_B)); + MMIO_D(PIPEDSL(dev_priv, PIPE_C)); + MMIO_D(PIPEDSL(dev_priv, _PIPE_EDP)); MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A)); MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B)); MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C)); -- cgit From 849a7f0ea571c5b9e0c9a30832a6247262fa09ac Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:38 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPEFRAME Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPEFRAME register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/7e6d1a8d3ae2a42efa3a48884e0e37357e0108c1.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vblank.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 12913bbdf123..aa1cd8b6c547 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -103,7 +103,8 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc) * we get a low value that's stable across two reads of the high * register. */ - frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe), PIPEFRAME(pipe)); + frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe), + PIPEFRAME(dev_priv, pipe)); pixel = frame & PIPE_PIXEL_MASK; frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c19d9863db65..52e4d0b3cd0c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1797,7 +1797,7 @@ #define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) #define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) -#define PIPEFRAME(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) +#define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) -- cgit From eb3750ea338471b6e59b515d498fe2e3a5fbfd51 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:39 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPEFRAMEPIXEL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPEFRAMEPIXEL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/464d4536f90e9d463458cdd315b3ba650e12ada5.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vblank.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index aa1cd8b6c547..f2eb3bc65203 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -103,7 +103,7 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc) * we get a low value that's stable across two reads of the high * register. */ - frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(pipe), + frame = intel_de_read64_2x32(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe), PIPEFRAME(dev_priv, pipe)); pixel = frame & PIPE_PIXEL_MASK; @@ -387,7 +387,7 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, * We can split this into vertical and horizontal * scanout position. */ - position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; + position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(dev_priv, pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; /* convert to pixel counts */ vbl_start *= htotal; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 52e4d0b3cd0c..3b8b9ec273d7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1798,7 +1798,7 @@ #define TRANSCONF(dev_priv, trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) #define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) #define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) -#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) +#define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ -- cgit From 30d41e3fe153160714b01065320fde64639c3fd0 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:40 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPESTAT Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPESTAT register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/8b18a1e77ccfd451bbaee80b6ddb23bdbc479336.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display_irq.c | 9 +++++---- drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 4 files changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index bb57fa65c7be..0c0433aae26d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -225,7 +225,7 @@ out: void i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, u32 status_mask) { - i915_reg_t reg = PIPESTAT(pipe); + i915_reg_t reg = PIPESTAT(dev_priv, pipe); u32 enable_mask; drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, @@ -248,7 +248,7 @@ void i915_enable_pipestat(struct drm_i915_private *dev_priv, void i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, u32 status_mask) { - i915_reg_t reg = PIPESTAT(pipe); + i915_reg_t reg = PIPESTAT(dev_priv, pipe); u32 enable_mask; drm_WARN_ONCE(&dev_priv->drm, status_mask & ~PIPESTAT_INT_STATUS_MASK, @@ -401,7 +401,8 @@ void i9xx_pipestat_irq_reset(struct drm_i915_private *dev_priv) enum pipe pipe; for_each_pipe(dev_priv, pipe) { - intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe), + intel_uncore_write(&dev_priv->uncore, + PIPESTAT(dev_priv, pipe), PIPESTAT_INT_STATUS_MASK | PIPE_FIFO_UNDERRUN_STATUS); @@ -454,7 +455,7 @@ void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, if (!status_mask) continue; - reg = PIPESTAT(pipe); + reg = PIPESTAT(dev_priv, pipe); pipe_stats[pipe] = intel_uncore_read(&dev_priv->uncore, reg) & status_mask; enable_mask = i915_pipestat_enable_mask(dev_priv, pipe); diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index 09a7fa6c0c37..401726f466c0 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -94,7 +94,7 @@ static bool cpt_can_enable_serr_int(struct drm_device *dev) static void i9xx_check_fifo_underruns(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - i915_reg_t reg = PIPESTAT(crtc->pipe); + i915_reg_t reg = PIPESTAT(dev_priv, crtc->pipe); u32 enable_mask; lockdep_assert_held(&dev_priv->irq_lock); @@ -115,7 +115,7 @@ static void i9xx_set_fifo_underrun_reporting(struct drm_device *dev, bool enable, bool old) { struct drm_i915_private *dev_priv = to_i915(dev); - i915_reg_t reg = PIPESTAT(pipe); + i915_reg_t reg = PIPESTAT(dev_priv, pipe); lockdep_assert_held(&dev_priv->irq_lock); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3b8b9ec273d7..a94b050f09bf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1799,7 +1799,7 @@ #define PIPEDSL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) #define PIPEFRAME(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) #define PIPEFRAMEPIXEL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) -#define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) +#define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 6a37f790c753..00ee588fab39 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -134,10 +134,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANSCONF(dev_priv, TRANSCODER_B)); MMIO_D(TRANSCONF(dev_priv, TRANSCODER_C)); MMIO_D(TRANSCONF(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPESTAT(PIPE_A)); - MMIO_D(PIPESTAT(PIPE_B)); - MMIO_D(PIPESTAT(PIPE_C)); - MMIO_D(PIPESTAT(_PIPE_EDP)); + MMIO_D(PIPESTAT(dev_priv, PIPE_A)); + MMIO_D(PIPESTAT(dev_priv, PIPE_B)); + MMIO_D(PIPESTAT(dev_priv, PIPE_C)); + MMIO_D(PIPESTAT(dev_priv, _PIPE_EDP)); MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A)); MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B)); MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C)); -- cgit From 03de2e10cf948101eee7e9cb73d911341c7d3dee Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:41 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_ARB_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_ARB_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/e75e80bd96e05ece6b82c0bdb509527ab2dd0e6d.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9434eba91839..48ee8aee21be 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -439,7 +439,7 @@ void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state) /* Wa_22012358565:adl-p */ if (DISPLAY_VER(dev_priv) == 13) - intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe), + intel_de_rmw(dev_priv, PIPE_ARB_CTL(dev_priv, pipe), 0, PIPE_ARB_USE_PROG_SLOTS); if (DISPLAY_VER(dev_priv) >= 14) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index a94b050f09bf..0b699bcac759 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1802,7 +1802,7 @@ #define PIPESTAT(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ -#define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) +#define PIPE_ARB_CTL(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) #define _PIPE_MISC_A 0x70030 -- cgit From 58d18ae5655f7c2d122ccb23f35de83872fbb48b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:42 +0300 Subject: drm/i915: pass dev_priv explicitly to ICL_PIPESTATUS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the ICL_PIPESTATUS register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/d9a7ef1ff8e848cd10729f4ee033d1ef55ee78cc.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 9 ++++++--- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c index 401726f466c0..e5e4ca7cc499 100644 --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c @@ -209,7 +209,8 @@ static void bdw_set_fifo_underrun_reporting(struct drm_device *dev, if (enable) { if (DISPLAY_VER(dev_priv) >= 11) - intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), + intel_de_write(dev_priv, + ICL_PIPESTATUS(dev_priv, pipe), icl_pipe_status_underrun_mask(dev_priv)); bdw_enable_pipe_irq(dev_priv, pipe, mask); @@ -418,9 +419,11 @@ void intel_cpu_fifo_underrun_irq_handler(struct drm_i915_private *dev_priv, * the underrun was caused by the downstream port. */ if (DISPLAY_VER(dev_priv) >= 11) { - underruns = intel_de_read(dev_priv, ICL_PIPESTATUS(pipe)) & + underruns = intel_de_read(dev_priv, + ICL_PIPESTATUS(dev_priv, pipe)) & icl_pipe_status_underrun_mask(dev_priv); - intel_de_write(dev_priv, ICL_PIPESTATUS(pipe), underruns); + intel_de_write(dev_priv, ICL_PIPESTATUS(dev_priv, pipe), + underruns); } if (intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false)) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0b699bcac759..37796427511f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1846,7 +1846,7 @@ #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) #define _ICL_PIPE_A_STATUS 0x70058 -#define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS) +#define ICL_PIPESTATUS(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS) #define PIPE_STATUS_UNDERRUN REG_BIT(31) #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) -- cgit From f0fea981483220a9152e69bd0adfda8b1b2db907 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:43 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPARB Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPARB register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/9e8dc8978ce3122a0e9c53778be547875a9ae6d8.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_wm.c | 22 ++++++++++++---------- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/i915_suspend.c | 6 ++++-- 3 files changed, 17 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index 628e7192ebc9..fd14010b4cc3 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -269,13 +269,15 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) switch (pipe) { case PIPE_A: - dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); + dsparb = intel_uncore_read(&dev_priv->uncore, + DSPARB(dev_priv)); dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2); sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); break; case PIPE_B: - dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); + dsparb = intel_uncore_read(&dev_priv->uncore, + DSPARB(dev_priv)); dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2); sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); @@ -300,7 +302,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, enum i9xx_plane_id i9xx_plane) { - u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); + u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv)); int size; size = dsparb & 0x7f; @@ -316,7 +318,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, static int i830_get_fifo_size(struct drm_i915_private *dev_priv, enum i9xx_plane_id i9xx_plane) { - u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); + u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv)); int size; size = dsparb & 0x1ff; @@ -333,7 +335,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv, static int i845_get_fifo_size(struct drm_i915_private *dev_priv, enum i9xx_plane_id i9xx_plane) { - u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB); + u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv)); int size; size = dsparb & 0x7f; @@ -1787,7 +1789,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, switch (crtc->pipe) { case PIPE_A: - dsparb = intel_uncore_read_fw(uncore, DSPARB); + dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv)); dsparb2 = intel_uncore_read_fw(uncore, DSPARB2); dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | @@ -1800,11 +1802,11 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); - intel_uncore_write_fw(uncore, DSPARB, dsparb); + intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb); intel_uncore_write_fw(uncore, DSPARB2, dsparb2); break; case PIPE_B: - dsparb = intel_uncore_read_fw(uncore, DSPARB); + dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv)); dsparb2 = intel_uncore_read_fw(uncore, DSPARB2); dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | @@ -1817,7 +1819,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); - intel_uncore_write_fw(uncore, DSPARB, dsparb); + intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb); intel_uncore_write_fw(uncore, DSPARB2, dsparb2); break; case PIPE_C: @@ -1841,7 +1843,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state, break; } - intel_uncore_posting_read_fw(uncore, DSPARB); + intel_uncore_posting_read_fw(uncore, DSPARB(dev_priv)); spin_unlock(&uncore->lock); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 37796427511f..e206725adb15 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1903,7 +1903,7 @@ #define SPRITEA_INVALID_GTT_STATUS REG_BIT(1) #define PLANEA_INVALID_GTT_STATUS REG_BIT(0) -#define DSPARB _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) +#define DSPARB(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030) #define DSPARB_CSTART_MASK (0x7f << 7) #define DSPARB_CSTART_SHIFT 7 #define DSPARB_BSTART_MASK (0x7f) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 81def10eb58f..bc449613c848 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -92,7 +92,8 @@ void i915_save_display(struct drm_i915_private *dev_priv) /* Display arbitration control */ if (GRAPHICS_VER(dev_priv) <= 4) - dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB); + dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, + DSPARB(dev_priv)); if (GRAPHICS_VER(dev_priv) == 4) pci_read_config_word(pdev, GCDGMBUS, @@ -116,7 +117,8 @@ void i915_restore_display(struct drm_i915_private *dev_priv) /* Display arbitration */ if (GRAPHICS_VER(dev_priv) <= 4) - intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB); + intel_de_write(dev_priv, DSPARB(dev_priv), + dev_priv->regfile.saveDSPARB); intel_vga_redisable(dev_priv); -- cgit From 42879a65203f9a563c82114b916bb7e9a1f79dc2 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:44 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPFW1 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPFW1 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/4843726dff7d95e4127fb948073c9e4addc1e683.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_wm.c | 25 +++++++++++++------------ drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index fd14010b4cc3..99f3748209db 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -657,10 +657,10 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) &pnv_display_wm, pnv_display_wm.fifo_size, cpp, latency->display_sr); - reg = intel_uncore_read(&dev_priv->uncore, DSPFW1); + reg = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv)); reg &= ~DSPFW_SR_MASK; reg |= FW_WM(wm, SR); - intel_uncore_write(&dev_priv->uncore, DSPFW1, reg); + intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv), reg); drm_dbg_kms(&dev_priv->drm, "DSPFW1 register is %x\n", reg); /* cursor SR */ @@ -720,7 +720,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv, for_each_pipe(dev_priv, pipe) trace_g4x_wm(intel_crtc_for_pipe(dev_priv, pipe), wm); - intel_uncore_write(&dev_priv->uncore, DSPFW1, + intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv), FW_WM(wm->sr.plane, SR) | FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | @@ -738,7 +738,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv, FW_WM(wm->hpll.cursor, HPLL_CURSOR) | FW_WM(wm->hpll.plane, HPLL_SR)); - intel_uncore_posting_read(&dev_priv->uncore, DSPFW1); + intel_uncore_posting_read(&dev_priv->uncore, DSPFW1(dev_priv)); } #define FW_WM_VLV(value, plane) \ @@ -770,7 +770,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv, intel_uncore_write(&dev_priv->uncore, DSPFW5, 0); intel_uncore_write(&dev_priv->uncore, DSPFW6, 0); - intel_uncore_write(&dev_priv->uncore, DSPFW1, + intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv), FW_WM(wm->sr.plane, SR) | FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | @@ -817,7 +817,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv, FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); } - intel_uncore_posting_read(&dev_priv->uncore, DSPFW1); + intel_uncore_posting_read(&dev_priv->uncore, DSPFW1(dev_priv)); } #undef FW_WM_VLV @@ -2067,10 +2067,11 @@ static void i965_update_wm(struct drm_i915_private *dev_priv) srwm); /* 965 has limitations... */ - intel_uncore_write(&dev_priv->uncore, DSPFW1, FW_WM(srwm, SR) | - FW_WM(8, CURSORB) | - FW_WM(8, PLANEB) | - FW_WM(8, PLANEA)); + intel_uncore_write(&dev_priv->uncore, DSPFW1(dev_priv), + FW_WM(srwm, SR) | + FW_WM(8, CURSORB) | + FW_WM(8, PLANEB) | + FW_WM(8, PLANEA)); intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) | FW_WM(8, PLANEC_OLD)); /* update cursor SR watermark */ @@ -3521,7 +3522,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv, { u32 tmp; - tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1); + tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv)); wm->sr.plane = _FW_WM(tmp, SR); wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); @@ -3561,7 +3562,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv, (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); } - tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1); + tmp = intel_uncore_read(&dev_priv->uncore, DSPFW1(dev_priv)); wm->sr.plane = _FW_WM(tmp, SR); wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e206725adb15..8380cb1309ff 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1938,7 +1938,7 @@ #define DSPARB_SPRITEF_MASK_VLV (0xff << 8) /* pnv/gen4/g4x/vlv/chv */ -#define DSPFW1 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) +#define DSPFW1(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70034) #define DSPFW_SR_SHIFT 23 #define DSPFW_SR_MASK (0x1ff << 23) #define DSPFW_CURSORB_SHIFT 16 -- cgit From 51946d0c75fd4c047694d8e06b5d5b13f0d3c12b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 7 Jun 2024 11:26:36 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPFW2 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPFW2 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/ba349f90b6614605c52f58ae048961c7b4da4495.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_wm.c | 13 +++++++------ drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index 99f3748209db..2e24aed3d67c 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -725,7 +725,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv, FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); - intel_uncore_write(&dev_priv->uncore, DSPFW2, + intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv), (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) | FW_WM(wm->sr.fbc, FBC_SR) | FW_WM(wm->hpll.fbc, FBC_HPLL_SR) | @@ -775,7 +775,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv, FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); - intel_uncore_write(&dev_priv->uncore, DSPFW2, + intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv), FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); @@ -2072,8 +2072,9 @@ static void i965_update_wm(struct drm_i915_private *dev_priv) FW_WM(8, CURSORB) | FW_WM(8, PLANEB) | FW_WM(8, PLANEA)); - intel_uncore_write(&dev_priv->uncore, DSPFW2, FW_WM(8, CURSORA) | - FW_WM(8, PLANEC_OLD)); + intel_uncore_write(&dev_priv->uncore, DSPFW2(dev_priv), + FW_WM(8, CURSORA) | + FW_WM(8, PLANEC_OLD)); /* update cursor SR watermark */ intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); @@ -3528,7 +3529,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv, wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA); - tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2); + tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2(dev_priv)); wm->fbc_en = tmp & DSPFW_FBC_SR_EN; wm->sr.fbc = _FW_WM(tmp, FBC_SR); wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR); @@ -3568,7 +3569,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv, wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA); - tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2); + tmp = intel_uncore_read(&dev_priv->uncore, DSPFW2(dev_priv)); wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB); wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8380cb1309ff..fd0be33c1864 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1949,7 +1949,7 @@ #define DSPFW_PLANEA_SHIFT 0 #define DSPFW_PLANEA_MASK (0x7f << 0) #define DSPFW_PLANEA_MASK_VLV (0xff << 0) /* vlv/chv */ -#define DSPFW2 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) +#define DSPFW2(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70038) #define DSPFW_FBC_SR_EN (1 << 31) /* g4x */ #define DSPFW_FBC_SR_SHIFT 28 #define DSPFW_FBC_SR_MASK (0x7 << 28) /* g4x */ -- cgit From 446db74bd372bc0baaace57c01897d9ad71c8abc Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:46 +0300 Subject: drm/i915: pass dev_priv explicitly to DSPFW3 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the DSPFW3 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/856978ed413e537b7d46eed5e8d93bdfd7c80fc6.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_wm.c | 27 ++++++++++++---------- .../gpu/drm/i915/display/intel_display_debugfs.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 3 files changed, 17 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index 2e24aed3d67c..a12765d9e9e4 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -149,14 +149,14 @@ static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enabl intel_uncore_write(&dev_priv->uncore, FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); intel_uncore_posting_read(&dev_priv->uncore, FW_BLC_SELF); } else if (IS_PINEVIEW(dev_priv)) { - val = intel_uncore_read(&dev_priv->uncore, DSPFW3); + val = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv)); was_enabled = val & PINEVIEW_SELF_REFRESH_EN; if (enable) val |= PINEVIEW_SELF_REFRESH_EN; else val &= ~PINEVIEW_SELF_REFRESH_EN; - intel_uncore_write(&dev_priv->uncore, DSPFW3, val); - intel_uncore_posting_read(&dev_priv->uncore, DSPFW3); + intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), val); + intel_uncore_posting_read(&dev_priv->uncore, DSPFW3(dev_priv)); } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { was_enabled = intel_uncore_read(&dev_priv->uncore, FW_BLC_SELF) & FW_BLC_SELF_EN; val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : @@ -668,7 +668,8 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) &pnv_cursor_wm, pnv_display_wm.fifo_size, 4, latency->cursor_sr); - intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_CURSOR_SR_MASK, + intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv), + DSPFW_CURSOR_SR_MASK, FW_WM(wm, CURSOR_SR)); /* Display HPLL off SR */ @@ -676,17 +677,18 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) &pnv_display_hplloff_wm, pnv_display_hplloff_wm.fifo_size, cpp, latency->display_hpll_disable); - intel_uncore_rmw(&dev_priv->uncore, DSPFW3, DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR)); + intel_uncore_rmw(&dev_priv->uncore, DSPFW3(dev_priv), + DSPFW_HPLL_SR_MASK, FW_WM(wm, HPLL_SR)); /* cursor HPLL off SR */ wm = intel_calculate_wm(dev_priv, pixel_rate, &pnv_cursor_hplloff_wm, pnv_display_hplloff_wm.fifo_size, 4, latency->cursor_hpll_disable); - reg = intel_uncore_read(&dev_priv->uncore, DSPFW3); + reg = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv)); reg &= ~DSPFW_HPLL_CURSOR_MASK; reg |= FW_WM(wm, HPLL_CURSOR); - intel_uncore_write(&dev_priv->uncore, DSPFW3, reg); + intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), reg); drm_dbg_kms(&dev_priv->drm, "DSPFW3 register is %x\n", reg); intel_set_memory_cxsr(dev_priv, true); @@ -732,7 +734,7 @@ static void g4x_write_wm_values(struct drm_i915_private *dev_priv, FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); - intel_uncore_write(&dev_priv->uncore, DSPFW3, + intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) | FW_WM(wm->sr.cursor, CURSOR_SR) | FW_WM(wm->hpll.cursor, HPLL_CURSOR) | @@ -779,7 +781,7 @@ static void vlv_write_wm_values(struct drm_i915_private *dev_priv, FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); - intel_uncore_write(&dev_priv->uncore, DSPFW3, + intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), FW_WM(wm->sr.cursor, CURSOR_SR)); if (IS_CHERRYVIEW(dev_priv)) { @@ -2076,7 +2078,8 @@ static void i965_update_wm(struct drm_i915_private *dev_priv) FW_WM(8, CURSORA) | FW_WM(8, PLANEC_OLD)); /* update cursor SR watermark */ - intel_uncore_write(&dev_priv->uncore, DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); + intel_uncore_write(&dev_priv->uncore, DSPFW3(dev_priv), + FW_WM(cursor_sr, CURSOR_SR)); if (cxsr_enabled) intel_set_memory_cxsr(dev_priv, true); @@ -3537,7 +3540,7 @@ static void g4x_read_wm_values(struct drm_i915_private *dev_priv, wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA); - tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3); + tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv)); wm->hpll_en = tmp & DSPFW_HPLL_SR_EN; wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR); @@ -3574,7 +3577,7 @@ static void vlv_read_wm_values(struct drm_i915_private *dev_priv, wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); - tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3); + tmp = intel_uncore_read(&dev_priv->uncore, DSPFW3(dev_priv)); wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); if (IS_CHERRYVIEW(dev_priv)) { diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 86d9900c40af..b538a8204124 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -77,7 +77,7 @@ static int i915_sr_status(struct seq_file *m, void *unused) else if (IS_I915GM(dev_priv)) sr_enabled = intel_de_read(dev_priv, INSTPM) & INSTPM_SELF_EN; else if (IS_PINEVIEW(dev_priv)) - sr_enabled = intel_de_read(dev_priv, DSPFW3) & PINEVIEW_SELF_REFRESH_EN; + sr_enabled = intel_de_read(dev_priv, DSPFW3(dev_priv)) & PINEVIEW_SELF_REFRESH_EN; else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index fd0be33c1864..3a75fa5c8b5b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1965,7 +1965,7 @@ #define DSPFW_SPRITEA_SHIFT 0 #define DSPFW_SPRITEA_MASK (0x7f << 0) /* g4x */ #define DSPFW_SPRITEA_MASK_VLV (0xff << 0) /* vlv/chv */ -#define DSPFW3 _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) +#define DSPFW3(dev_priv) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x7003c) #define DSPFW_HPLL_SR_EN (1 << 31) #define PINEVIEW_SELF_REFRESH_EN (1 << 30) #define DSPFW_CURSOR_SR_SHIFT 24 -- cgit From 8edbb0ee171796cc96bb65fd85a8bc8e6d6ca2a3 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:47 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_FRMCOUNT_G4X Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_FRMCOUNT_G4X register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/747124e5eebdb58b06d70a0aae0af4dd7e6b7d86.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vblank.c | 2 +- drivers/gpu/drm/i915/gvt/display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 4 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index f2eb3bc65203..e5db54b1c632 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -126,7 +126,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc) if (!vblank->max_vblank_count) return 0; - return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(pipe)); + return intel_de_read(dev_priv, PIPE_FRMCOUNT_G4X(dev_priv, pipe)); } static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc) diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index ad21b8f65d6b..3681dca165c6 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -647,7 +647,7 @@ static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe) } if (pipe_is_enabled(vgpu, pipe)) { - vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++; + vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(dev_priv, pipe))++; intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]); } } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3a75fa5c8b5b..0ab8df446ea9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2176,7 +2176,7 @@ /* GM45+ just has to be different */ #define _PIPEA_FRMCOUNT_G4X 0x70040 #define _PIPEA_FLIPCOUNT_G4X 0x70044 -#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) +#define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) /* CHV pipe B blender */ diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 00ee588fab39..2e027f3ee750 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -142,10 +142,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B)); MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C)); MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP)); - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A)); - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B)); - MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C)); - MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP)); + MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A)); + MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_B)); + MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C)); + MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, _PIPE_EDP)); MMIO_D(CURCNTR(dev_priv, PIPE_A)); MMIO_D(CURCNTR(dev_priv, PIPE_B)); MMIO_D(CURCNTR(dev_priv, PIPE_C)); -- cgit From 2501a0b68e8e5989eb782c8ac42eb4bd26713b10 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:48 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_FLIPCOUNT_G4X Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_FLIPCOUNT_G4X register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/c53a6f5cd97976f43fbae442034074d2ea9aac42.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 +- drivers/gpu/drm/i915/gvt/handlers.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 9cdb53015d16..2f4c9c66b40b 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -1437,7 +1437,7 @@ static int gen8_update_plane_mmio_from_mi_display_flip( } if (info->plane == PLANE_PRIMARY) - vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(info->pipe))++; + vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, info->pipe))++; if (info->async_flip) intel_vgpu_trigger_virtual_event(vgpu, info->event); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 31ed96be91f3..bffbefe5fd31 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1020,7 +1020,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, write_vreg(vgpu, offset, p_data, bytes); vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); - vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; + vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++; if (vgpu_vreg_t(vgpu, DSPCNTR(dev_priv, pipe)) & PLANE_CTL_ASYNC_FLIP) intel_vgpu_trigger_virtual_event(vgpu, event); @@ -1062,7 +1062,7 @@ static int reg50080_mmio_write(struct intel_vgpu *vgpu, write_vreg(vgpu, offset, p_data, bytes); if (plane == PLANE_PRIMARY) { vgpu_vreg_t(vgpu, DSPSURFLIVE(dev_priv, pipe)) = vgpu_vreg(vgpu, offset); - vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++; + vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(dev_priv, pipe))++; } else { vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 0ab8df446ea9..064d14d1e8bb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2177,7 +2177,7 @@ #define _PIPEA_FRMCOUNT_G4X 0x70040 #define _PIPEA_FLIPCOUNT_G4X 0x70044 #define PIPE_FRMCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) -#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) +#define PIPE_FLIPCOUNT_G4X(dev_priv, pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) /* CHV pipe B blender */ #define _CHV_BLEND_A 0x60a00 diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 2e027f3ee750..ba3f734ced0b 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -138,10 +138,10 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPESTAT(dev_priv, PIPE_B)); MMIO_D(PIPESTAT(dev_priv, PIPE_C)); MMIO_D(PIPESTAT(dev_priv, _PIPE_EDP)); - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A)); - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B)); - MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C)); - MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP)); + MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_A)); + MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_B)); + MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, PIPE_C)); + MMIO_D(PIPE_FLIPCOUNT_G4X(dev_priv, _PIPE_EDP)); MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_A)); MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_B)); MMIO_D(PIPE_FRMCOUNT_G4X(dev_priv, PIPE_C)); -- cgit From 65313768a4e2da9e0abc104afa6d82ee193b01ed Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:49 +0300 Subject: drm/i915: pass dev_priv explicitly to CHV_BLEND Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CHV_BLEND register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/a2c5064ee3a985f7b7b5c7e672737df447d3af29.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 48ee8aee21be..a6d7928fbe37 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2108,7 +2108,8 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0); if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { - intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY); + intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe), + CHV_BLEND_LEGACY); intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 064d14d1e8bb..17422a41a51d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2190,7 +2190,7 @@ #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10) #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) -#define CHV_BLEND(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A) +#define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A) #define CHV_CANVAS(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A) /* Display/Sprite base address macros */ -- cgit From c8f1392f4849b4e92ea344da29c86834fd54b2cf Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:50 +0300 Subject: drm/i915: pass dev_priv explicitly to CHV_CANVAS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the CHV_CANVAS register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/a48c7984a14412ef74af250d5bc2ea9097aa2222.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a6d7928fbe37..241121b0b3ff 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2110,7 +2110,7 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { intel_de_write(dev_priv, CHV_BLEND(dev_priv, pipe), CHV_BLEND_LEGACY); - intel_de_write(dev_priv, CHV_CANVAS(pipe), 0); + intel_de_write(dev_priv, CHV_CANVAS(dev_priv, pipe), 0); } crtc->active = true; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 17422a41a51d..44e3f3bebfee 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2191,7 +2191,7 @@ #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0) #define CHV_BLEND(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A) -#define CHV_CANVAS(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A) +#define CHV_CANVAS(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A) /* Display/Sprite base address macros */ #define DISP_BASEADDR_MASK (0xfffff000) -- cgit From 3b24925e54daf6e2afbbdc7ec9c301da47f0504e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:51 +0300 Subject: drm/i915: pass dev_priv explicitly to SWF0 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the SWF0 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/df957a1dfeddc14e4b62d6e2a1bf8104d506be87.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/i915_suspend.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 44e3f3bebfee..574a171d29c9 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2209,7 +2209,7 @@ * [10:1f] all * [30:32] all */ -#define SWF0(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) +#define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) #define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index bc449613c848..ac8221ae97f3 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -40,7 +40,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv) /* Scratch space */ if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { for (i = 0; i < 7; i++) { - dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); + dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, + SWF0(dev_priv, i)); dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); } for (i = 0; i < 3; i++) @@ -50,7 +51,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv) dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); } else if (HAS_GMCH(dev_priv)) { for (i = 0; i < 16; i++) { - dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(i)); + dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, + SWF0(dev_priv, i)); dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); } for (i = 0; i < 3; i++) @@ -65,7 +67,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv) /* Scratch space */ if (GRAPHICS_VER(dev_priv) == 2 && IS_MOBILE(dev_priv)) { for (i = 0; i < 7; i++) { - intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]); + intel_de_write(dev_priv, SWF0(dev_priv, i), + dev_priv->regfile.saveSWF0[i]); intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); } for (i = 0; i < 3; i++) @@ -75,7 +78,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv) intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); } else if (HAS_GMCH(dev_priv)) { for (i = 0; i < 16; i++) { - intel_de_write(dev_priv, SWF0(i), dev_priv->regfile.saveSWF0[i]); + intel_de_write(dev_priv, SWF0(dev_priv, i), + dev_priv->regfile.saveSWF0[i]); intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); } for (i = 0; i < 3; i++) -- cgit From eefd93d8f632acb376eb06af67dddd515e6eb63a Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:52 +0300 Subject: drm/i915: pass dev_priv explicitly to SWF1 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the SWF1 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/cd31efc114325e61e357b0f8a1106f2eb7819fff.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/i915_suspend.c | 18 ++++++++++++------ 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 574a171d29c9..ebd01cc6eb16 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2210,7 +2210,7 @@ * [30:32] all */ #define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) -#define SWF1(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) +#define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) #define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index ac8221ae97f3..8a71c1f52cb4 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -42,18 +42,21 @@ static void intel_save_swf(struct drm_i915_private *dev_priv) for (i = 0; i < 7; i++) { dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(dev_priv, i)); - dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); + dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, + SWF1(dev_priv, i)); } for (i = 0; i < 3; i++) dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); } else if (GRAPHICS_VER(dev_priv) == 2) { for (i = 0; i < 7; i++) - dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); + dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, + SWF1(dev_priv, i)); } else if (HAS_GMCH(dev_priv)) { for (i = 0; i < 16; i++) { dev_priv->regfile.saveSWF0[i] = intel_de_read(dev_priv, SWF0(dev_priv, i)); - dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, SWF1(i)); + dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, + SWF1(dev_priv, i)); } for (i = 0; i < 3; i++) dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); @@ -69,18 +72,21 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv) for (i = 0; i < 7; i++) { intel_de_write(dev_priv, SWF0(dev_priv, i), dev_priv->regfile.saveSWF0[i]); - intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); + intel_de_write(dev_priv, SWF1(dev_priv, i), + dev_priv->regfile.saveSWF1[i]); } for (i = 0; i < 3; i++) intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]); } else if (GRAPHICS_VER(dev_priv) == 2) { for (i = 0; i < 7; i++) - intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); + intel_de_write(dev_priv, SWF1(dev_priv, i), + dev_priv->regfile.saveSWF1[i]); } else if (HAS_GMCH(dev_priv)) { for (i = 0; i < 16; i++) { intel_de_write(dev_priv, SWF0(dev_priv, i), dev_priv->regfile.saveSWF0[i]); - intel_de_write(dev_priv, SWF1(i), dev_priv->regfile.saveSWF1[i]); + intel_de_write(dev_priv, SWF1(dev_priv, i), + dev_priv->regfile.saveSWF1[i]); } for (i = 0; i < 3; i++) intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]); -- cgit From b9089184ba9f26dce6482d6afa200500b8c6bbb6 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:25:53 +0300 Subject: drm/i915: pass dev_priv explicitly to SWF3 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the SWF3 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/5ab27d6a4366617ba273e526a46a505c3d3c3295.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/i915_suspend.c | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ebd01cc6eb16..56c1b7d83c27 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2211,7 +2211,7 @@ */ #define SWF0(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70410 + (i) * 4) #define SWF1(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x71410 + (i) * 4) -#define SWF3(i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) +#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) /* Pipe B */ diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c index 8a71c1f52cb4..f8373a461f17 100644 --- a/drivers/gpu/drm/i915/i915_suspend.c +++ b/drivers/gpu/drm/i915/i915_suspend.c @@ -46,7 +46,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv) SWF1(dev_priv, i)); } for (i = 0; i < 3; i++) - dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); + dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, + SWF3(dev_priv, i)); } else if (GRAPHICS_VER(dev_priv) == 2) { for (i = 0; i < 7; i++) dev_priv->regfile.saveSWF1[i] = intel_de_read(dev_priv, @@ -59,7 +60,8 @@ static void intel_save_swf(struct drm_i915_private *dev_priv) SWF1(dev_priv, i)); } for (i = 0; i < 3; i++) - dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, SWF3(i)); + dev_priv->regfile.saveSWF3[i] = intel_de_read(dev_priv, + SWF3(dev_priv, i)); } } @@ -76,7 +78,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv) dev_priv->regfile.saveSWF1[i]); } for (i = 0; i < 3; i++) - intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]); + intel_de_write(dev_priv, SWF3(dev_priv, i), + dev_priv->regfile.saveSWF3[i]); } else if (GRAPHICS_VER(dev_priv) == 2) { for (i = 0; i < 7; i++) intel_de_write(dev_priv, SWF1(dev_priv, i), @@ -89,7 +92,8 @@ static void intel_restore_swf(struct drm_i915_private *dev_priv) dev_priv->regfile.saveSWF1[i]); } for (i = 0; i < 3; i++) - intel_de_write(dev_priv, SWF3(i), dev_priv->regfile.saveSWF3[i]); + intel_de_write(dev_priv, SWF3(dev_priv, i), + dev_priv->regfile.saveSWF3[i]); } } -- cgit From 5702d5d4125a03afcb1cf3c5746eb7704fe815ed Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:08 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_DATA_M1 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_DATA_M1 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/aa87444d7b2c0c695729c15730bb11aa922b7561.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_fdi.c | 6 +++--- drivers/gpu/drm/i915/gvt/display.c | 8 ++++---- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 5 files changed, 16 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 241121b0b3ff..7fd65e3b018d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2641,7 +2641,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, if (DISPLAY_VER(dev_priv) >= 5) intel_set_m_n(dev_priv, m_n, - PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), + PIPE_DATA_M1(dev_priv, transcoder), + PIPE_DATA_N1(transcoder), PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); else intel_set_m_n(dev_priv, m_n, @@ -3337,7 +3338,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, if (DISPLAY_VER(dev_priv) >= 5) intel_get_m_n(dev_priv, m_n, - PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder), + PIPE_DATA_M1(dev_priv, transcoder), + PIPE_DATA_N1(transcoder), PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); else intel_get_m_n(dev_priv, m_n, diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 8b17b8ad71c3..007e0f9e9304 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -514,7 +514,7 @@ static void ilk_fdi_link_train(struct intel_crtc *crtc, * detection works. */ intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), - intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); + intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); /* FDI needs bits from pipe first */ assert_transcoder_enabled(dev_priv, crtc_state->cpu_transcoder); @@ -616,7 +616,7 @@ static void gen6_fdi_link_train(struct intel_crtc *crtc, * detection works. */ intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), - intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); + intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ @@ -754,7 +754,7 @@ static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, * detection works. */ intel_de_write(dev_priv, FDI_RX_TUSIZE1(pipe), - intel_de_read(dev_priv, PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); + intel_de_read(dev_priv, PIPE_DATA_M1(dev_priv, pipe)) & TU_SIZE_MASK); /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit for train result */ diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 3681dca165c6..ce6f20b1dabc 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -261,8 +261,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) * DP link clk 1620 MHz and non-constant_n. * TODO: calculate DP link symbol clk and stream clk m/n. */ - vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); - vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; + vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); + vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; @@ -395,8 +395,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) * DP link clk 1620 MHz and non-constant_n. * TODO: calculate DP link symbol clk and stream clk m/n. */ - vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = TU_SIZE(64); - vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e; + vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); + vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 56c1b7d83c27..e7b7f8ac8ae2 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2298,7 +2298,7 @@ #define _PIPEB_LINK_M2 0x61048 #define _PIPEB_LINK_N2 0x6104c -#define PIPE_DATA_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) +#define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) #define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) #define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index ba3f734ced0b..977d695fbdff 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -266,7 +266,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_EDP)); MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPE_DATA_M1(TRANSCODER_A)); + MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_N1(TRANSCODER_A)); MMIO_D(PIPE_DATA_M2(TRANSCODER_A)); MMIO_D(PIPE_DATA_N2(TRANSCODER_A)); @@ -274,7 +274,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_N1(TRANSCODER_A)); MMIO_D(PIPE_LINK_M2(TRANSCODER_A)); MMIO_D(PIPE_LINK_N2(TRANSCODER_A)); - MMIO_D(PIPE_DATA_M1(TRANSCODER_B)); + MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_N1(TRANSCODER_B)); MMIO_D(PIPE_DATA_M2(TRANSCODER_B)); MMIO_D(PIPE_DATA_N2(TRANSCODER_B)); @@ -282,7 +282,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_N1(TRANSCODER_B)); MMIO_D(PIPE_LINK_M2(TRANSCODER_B)); MMIO_D(PIPE_LINK_N2(TRANSCODER_B)); - MMIO_D(PIPE_DATA_M1(TRANSCODER_C)); + MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_N1(TRANSCODER_C)); MMIO_D(PIPE_DATA_M2(TRANSCODER_C)); MMIO_D(PIPE_DATA_N2(TRANSCODER_C)); @@ -290,7 +290,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_N1(TRANSCODER_C)); MMIO_D(PIPE_LINK_M2(TRANSCODER_C)); MMIO_D(PIPE_LINK_N2(TRANSCODER_C)); - MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP)); + MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP)); -- cgit From 12967c4f21707269de2bd9cd525acf32d3e0a8ee Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:09 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_DATA_N1 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_DATA_N1 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/80759c6efdfdb59c4bd624af85b9db38ebe06f65.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/gvt/display.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 4 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7fd65e3b018d..5eb4ad261c21 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2642,7 +2642,7 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, if (DISPLAY_VER(dev_priv) >= 5) intel_set_m_n(dev_priv, m_n, PIPE_DATA_M1(dev_priv, transcoder), - PIPE_DATA_N1(transcoder), + PIPE_DATA_N1(dev_priv, transcoder), PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); else intel_set_m_n(dev_priv, m_n, @@ -3339,7 +3339,7 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, if (DISPLAY_VER(dev_priv) >= 5) intel_get_m_n(dev_priv, m_n, PIPE_DATA_M1(dev_priv, transcoder), - PIPE_DATA_N1(transcoder), + PIPE_DATA_N1(dev_priv, transcoder), PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); else intel_get_m_n(dev_priv, m_n, diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index ce6f20b1dabc..5f3ee57b5982 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -263,7 +263,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) */ vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; - vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; + vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; @@ -397,7 +397,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) */ vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; - vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000; + vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e7b7f8ac8ae2..762b2e43051c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2299,7 +2299,7 @@ #define _PIPEB_LINK_N2 0x6104c #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) -#define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) +#define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) #define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 977d695fbdff..b9ad4eec4740 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -267,7 +267,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(BCLRPAT(dev_priv, TRANSCODER_EDP)); MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A)); - MMIO_D(PIPE_DATA_N1(TRANSCODER_A)); + MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_M2(TRANSCODER_A)); MMIO_D(PIPE_DATA_N2(TRANSCODER_A)); MMIO_D(PIPE_LINK_M1(TRANSCODER_A)); @@ -275,7 +275,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M2(TRANSCODER_A)); MMIO_D(PIPE_LINK_N2(TRANSCODER_A)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B)); - MMIO_D(PIPE_DATA_N1(TRANSCODER_B)); + MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_M2(TRANSCODER_B)); MMIO_D(PIPE_DATA_N2(TRANSCODER_B)); MMIO_D(PIPE_LINK_M1(TRANSCODER_B)); @@ -283,7 +283,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M2(TRANSCODER_B)); MMIO_D(PIPE_LINK_N2(TRANSCODER_B)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C)); - MMIO_D(PIPE_DATA_N1(TRANSCODER_C)); + MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_M2(TRANSCODER_C)); MMIO_D(PIPE_DATA_N2(TRANSCODER_C)); MMIO_D(PIPE_LINK_M1(TRANSCODER_C)); @@ -291,7 +291,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M2(TRANSCODER_C)); MMIO_D(PIPE_LINK_N2(TRANSCODER_C)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP)); + MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP)); -- cgit From ddbdeb6c591ed52f104d1cfd862bae6e581df004 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:10 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_DATA_M2 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_DATA_M2 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1fda9b8cd446727845089844a1c8eeb5c8ae7b5a.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5eb4ad261c21..c2a2061a467d 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2660,7 +2660,8 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, return; intel_set_m_n(dev_priv, m_n, - PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), + PIPE_DATA_M2(dev_priv, transcoder), + PIPE_DATA_N2(transcoder), PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); } @@ -3357,7 +3358,8 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, return; intel_get_m_n(dev_priv, m_n, - PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder), + PIPE_DATA_M2(dev_priv, transcoder), + PIPE_DATA_N2(transcoder), PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 762b2e43051c..5e3e709d8f1a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2300,7 +2300,7 @@ #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) -#define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) +#define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) #define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index b9ad4eec4740..4199106f7202 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -268,7 +268,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(TRANS_VSYNCSHIFT(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A)); - MMIO_D(PIPE_DATA_M2(TRANSCODER_A)); + MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_N2(TRANSCODER_A)); MMIO_D(PIPE_LINK_M1(TRANSCODER_A)); MMIO_D(PIPE_LINK_N1(TRANSCODER_A)); @@ -276,7 +276,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_N2(TRANSCODER_A)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B)); - MMIO_D(PIPE_DATA_M2(TRANSCODER_B)); + MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_N2(TRANSCODER_B)); MMIO_D(PIPE_LINK_M1(TRANSCODER_B)); MMIO_D(PIPE_LINK_N1(TRANSCODER_B)); @@ -284,7 +284,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_N2(TRANSCODER_B)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C)); - MMIO_D(PIPE_DATA_M2(TRANSCODER_C)); + MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_N2(TRANSCODER_C)); MMIO_D(PIPE_LINK_M1(TRANSCODER_C)); MMIO_D(PIPE_LINK_N1(TRANSCODER_C)); @@ -292,7 +292,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_N2(TRANSCODER_C)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP)); + MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP)); -- cgit From 9ffd21103d064c382110bd0c4bdec0c2a4db9960 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:11 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_DATA_N2 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_DATA_N2 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/6eeb0c74d6e566f04a193b2a3f1272e58df66f20.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c2a2061a467d..7bf5b2559143 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2661,7 +2661,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, intel_set_m_n(dev_priv, m_n, PIPE_DATA_M2(dev_priv, transcoder), - PIPE_DATA_N2(transcoder), + PIPE_DATA_N2(dev_priv, transcoder), PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); } @@ -3359,7 +3359,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, intel_get_m_n(dev_priv, m_n, PIPE_DATA_M2(dev_priv, transcoder), - PIPE_DATA_N2(transcoder), + PIPE_DATA_N2(dev_priv, transcoder), PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5e3e709d8f1a..87c06eadf248 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2301,7 +2301,7 @@ #define PIPE_DATA_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) -#define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) +#define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) #define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 4199106f7202..829196c665c6 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -269,7 +269,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A)); - MMIO_D(PIPE_DATA_N2(TRANSCODER_A)); + MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_M1(TRANSCODER_A)); MMIO_D(PIPE_LINK_N1(TRANSCODER_A)); MMIO_D(PIPE_LINK_M2(TRANSCODER_A)); @@ -277,7 +277,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B)); - MMIO_D(PIPE_DATA_N2(TRANSCODER_B)); + MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_M1(TRANSCODER_B)); MMIO_D(PIPE_LINK_N1(TRANSCODER_B)); MMIO_D(PIPE_LINK_M2(TRANSCODER_B)); @@ -285,7 +285,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C)); - MMIO_D(PIPE_DATA_N2(TRANSCODER_C)); + MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_M1(TRANSCODER_C)); MMIO_D(PIPE_LINK_N1(TRANSCODER_C)); MMIO_D(PIPE_LINK_M2(TRANSCODER_C)); @@ -293,7 +293,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP)); + MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP)); -- cgit From 3c461986e8ab2bc126a2bb7868b4f9f3b125e965 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:12 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_LINK_M1 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_M1 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/bf25d447d98009f56f2c5b2205719ab2d9a70c93.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-- drivers/gpu/drm/i915/gvt/display.c | 4 ++-- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 5 files changed, 12 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 7bf5b2559143..a3249d782a8b 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2643,7 +2643,8 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, intel_set_m_n(dev_priv, m_n, PIPE_DATA_M1(dev_priv, transcoder), PIPE_DATA_N1(dev_priv, transcoder), - PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); + PIPE_LINK_M1(dev_priv, transcoder), + PIPE_LINK_N1(transcoder)); else intel_set_m_n(dev_priv, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), @@ -3341,7 +3342,8 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, intel_get_m_n(dev_priv, m_n, PIPE_DATA_M1(dev_priv, transcoder), PIPE_DATA_N1(dev_priv, transcoder), - PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder)); + PIPE_LINK_M1(dev_priv, transcoder), + PIPE_LINK_N1(transcoder)); else intel_get_m_n(dev_priv, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 5f3ee57b5982..eea956603cc8 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -264,7 +264,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; - vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; + vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; /* Enable per-DDI/PORT vreg */ @@ -398,7 +398,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) = TU_SIZE(64); vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; - vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e; + vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; } diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index bffbefe5fd31..d0c4e555435a 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -672,7 +672,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) dp_br = skl_vgpu_get_dp_bitrate(vgpu, port); /* Get DP link symbol clock M/N */ - link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)); + link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)); link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); /* Get H/V total from transcoder timing */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 87c06eadf248..f45bb6d5705b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2302,7 +2302,7 @@ #define PIPE_DATA_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) -#define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) +#define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) #define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 829196c665c6..c08b8e755377 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -270,7 +270,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A)); - MMIO_D(PIPE_LINK_M1(TRANSCODER_A)); + MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_N1(TRANSCODER_A)); MMIO_D(PIPE_LINK_M2(TRANSCODER_A)); MMIO_D(PIPE_LINK_N2(TRANSCODER_A)); @@ -278,7 +278,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B)); - MMIO_D(PIPE_LINK_M1(TRANSCODER_B)); + MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_N1(TRANSCODER_B)); MMIO_D(PIPE_LINK_M2(TRANSCODER_B)); MMIO_D(PIPE_LINK_N2(TRANSCODER_B)); @@ -286,7 +286,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C)); - MMIO_D(PIPE_LINK_M1(TRANSCODER_C)); + MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_N1(TRANSCODER_C)); MMIO_D(PIPE_LINK_M2(TRANSCODER_C)); MMIO_D(PIPE_LINK_N2(TRANSCODER_C)); @@ -294,7 +294,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP)); + MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP)); -- cgit From 0b406cc993297a0cd718e041a8456ffb7ee5445b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:13 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_LINK_N1 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_N1 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/0960c3726a36999b38084dce6c3824882921c475.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/gvt/display.c | 4 ++-- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index a3249d782a8b..eef317984564 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2644,7 +2644,7 @@ void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc, PIPE_DATA_M1(dev_priv, transcoder), PIPE_DATA_N1(dev_priv, transcoder), PIPE_LINK_M1(dev_priv, transcoder), - PIPE_LINK_N1(transcoder)); + PIPE_LINK_N1(dev_priv, transcoder)); else intel_set_m_n(dev_priv, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), @@ -3343,7 +3343,7 @@ void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc, PIPE_DATA_M1(dev_priv, transcoder), PIPE_DATA_N1(dev_priv, transcoder), PIPE_LINK_M1(dev_priv, transcoder), - PIPE_LINK_N1(transcoder)); + PIPE_LINK_N1(dev_priv, transcoder)); else intel_get_m_n(dev_priv, m_n, PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe), diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index eea956603cc8..95b4b76d3b45 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -265,7 +265,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; - vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; + vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000; /* Enable per-DDI/PORT vreg */ if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { @@ -399,7 +399,7 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, PIPE_DATA_M1(dev_priv, TRANSCODER_A)) |= 0x5b425e; vgpu_vreg_t(vgpu, PIPE_DATA_N1(dev_priv, TRANSCODER_A)) = 0x800000; vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)) = 0x3cd6e; - vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000; + vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)) = 0x80000; } if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) { diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index d0c4e555435a..7416068e7c82 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -673,7 +673,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) /* Get DP link symbol clock M/N */ link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(dev_priv, TRANSCODER_A)); - link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)); + link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(dev_priv, TRANSCODER_A)); /* Get H/V total from transcoder timing */ htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(dev_priv, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f45bb6d5705b..86ca2798fd2c 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2303,7 +2303,7 @@ #define PIPE_DATA_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) -#define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) +#define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) #define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index c08b8e755377..00ce7147a9b6 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -271,7 +271,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A)); - MMIO_D(PIPE_LINK_N1(TRANSCODER_A)); + MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_M2(TRANSCODER_A)); MMIO_D(PIPE_LINK_N2(TRANSCODER_A)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B)); @@ -279,7 +279,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B)); - MMIO_D(PIPE_LINK_N1(TRANSCODER_B)); + MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_M2(TRANSCODER_B)); MMIO_D(PIPE_LINK_N2(TRANSCODER_B)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C)); @@ -287,7 +287,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C)); - MMIO_D(PIPE_LINK_N1(TRANSCODER_C)); + MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_M2(TRANSCODER_C)); MMIO_D(PIPE_LINK_N2(TRANSCODER_C)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP)); @@ -295,7 +295,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP)); + MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP)); MMIO_D(PF_CTL(PIPE_A)); -- cgit From 04f657cf6677d7606c2ebcb6d8643cec0ec683c7 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:14 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_LINK_M2 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_M2 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/31337adcaca1333724600b0afe6e3880f0948d5e.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index eef317984564..9df8e486a86e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2663,7 +2663,8 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, intel_set_m_n(dev_priv, m_n, PIPE_DATA_M2(dev_priv, transcoder), PIPE_DATA_N2(dev_priv, transcoder), - PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); + PIPE_LINK_M2(dev_priv, transcoder), + PIPE_LINK_N2(transcoder)); } static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) @@ -3362,7 +3363,8 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, intel_get_m_n(dev_priv, m_n, PIPE_DATA_M2(dev_priv, transcoder), PIPE_DATA_N2(dev_priv, transcoder), - PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder)); + PIPE_LINK_M2(dev_priv, transcoder), + PIPE_LINK_N2(transcoder)); } static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 86ca2798fd2c..f0e9cc998143 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2304,7 +2304,7 @@ #define PIPE_DATA_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) -#define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) +#define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) #define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) /* CPU panel fitter */ diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index 00ce7147a9b6..d1a51ae042f1 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -272,7 +272,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A)); - MMIO_D(PIPE_LINK_M2(TRANSCODER_A)); + MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_N2(TRANSCODER_A)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B)); @@ -280,7 +280,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B)); - MMIO_D(PIPE_LINK_M2(TRANSCODER_B)); + MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_N2(TRANSCODER_B)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C)); @@ -288,7 +288,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C)); - MMIO_D(PIPE_LINK_M2(TRANSCODER_C)); + MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_N2(TRANSCODER_C)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP)); @@ -296,7 +296,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_DATA_N2(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP)); + MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP)); MMIO_D(PF_CTL(PIPE_A)); MMIO_D(PF_WIN_SZ(PIPE_A)); -- cgit From 2d557d3abafb92b813f8dff613c9fd54161cbbc8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:15 +0300 Subject: drm/i915: pass dev_priv explicitly to PIPE_LINK_N2 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the PIPE_LINK_N2 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/5267c167414fb46a25277c1c9a802f6ccf8de3c9.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 8 ++++---- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 9df8e486a86e..952780028630 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2664,7 +2664,7 @@ void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc, PIPE_DATA_M2(dev_priv, transcoder), PIPE_DATA_N2(dev_priv, transcoder), PIPE_LINK_M2(dev_priv, transcoder), - PIPE_LINK_N2(transcoder)); + PIPE_LINK_N2(dev_priv, transcoder)); } static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state) @@ -3364,7 +3364,7 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc, PIPE_DATA_M2(dev_priv, transcoder), PIPE_DATA_N2(dev_priv, transcoder), PIPE_LINK_M2(dev_priv, transcoder), - PIPE_LINK_N2(transcoder)); + PIPE_LINK_N2(dev_priv, transcoder)); } static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f0e9cc998143..5f822b8f1775 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2305,7 +2305,7 @@ #define PIPE_LINK_M1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) #define PIPE_LINK_N1(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) #define PIPE_LINK_M2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) -#define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) +#define PIPE_LINK_N2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) /* CPU panel fitter */ /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index d1a51ae042f1..955c9a33212a 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -273,7 +273,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_A)); - MMIO_D(PIPE_LINK_N2(TRANSCODER_A)); + MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_A)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_B)); @@ -281,7 +281,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_B)); - MMIO_D(PIPE_LINK_N2(TRANSCODER_B)); + MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_B)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_C)); @@ -289,7 +289,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_C)); - MMIO_D(PIPE_LINK_N2(TRANSCODER_C)); + MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_C)); MMIO_D(PIPE_DATA_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_N1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_DATA_M2(dev_priv, TRANSCODER_EDP)); @@ -297,7 +297,7 @@ static int iterate_generic_mmio(struct intel_gvt_mmio_table_iter *iter) MMIO_D(PIPE_LINK_M1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_N1(dev_priv, TRANSCODER_EDP)); MMIO_D(PIPE_LINK_M2(dev_priv, TRANSCODER_EDP)); - MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP)); + MMIO_D(PIPE_LINK_N2(dev_priv, TRANSCODER_EDP)); MMIO_D(PF_CTL(PIPE_A)); MMIO_D(PF_WIN_SZ(PIPE_A)); MMIO_D(PF_WIN_POS(PIPE_A)); -- cgit From b092d6ad277363eb5e8fe89b0b34070f3dc8f66b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:17 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_DDI_FUNC_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/4ccf75561aa0fb209fd71c85e9089b0350570fd6.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 12 ++++++---- drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++++++++++++++--------- drivers/gpu/drm/i915/display/intel_display.c | 9 +++++--- drivers/gpu/drm/i915/display/intel_display_irq.c | 3 ++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++-- drivers/gpu/drm/i915/display/intel_fdi.c | 3 ++- drivers/gpu/drm/i915/display/intel_hdcp.c | 3 ++- drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +- drivers/gpu/drm/i915/gvt/display.c | 25 +++++++++++--------- drivers/gpu/drm/i915/gvt/handlers.c | 2 +- drivers/gpu/drm/i915/i915_reg.h | 2 +- 11 files changed, 58 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index 9beb94494b2b..acc80d439352 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -796,7 +796,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, dsi_trans = dsi_port_to_transcoder(port); /* select data lane width */ - tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans)); tmp &= ~DDI_PORT_WIDTH_MASK; tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count); @@ -822,7 +823,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, /* enable DDI buffer */ tmp |= TRANS_DDI_FUNC_ENABLE; - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp); + intel_de_write(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans), tmp); } /* wait for link ready */ @@ -1333,7 +1335,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) /* disable ddi function */ for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), + intel_de_rmw(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans), TRANS_DDI_FUNC_ENABLE, 0); } @@ -1697,7 +1700,8 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans)); switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { case TRANS_DDI_EDP_INPUT_A_ON: *pipe = PIPE_A; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index c76bbd13bb27..4a55ef88c414 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -606,7 +606,7 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); } - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state)); } @@ -626,7 +626,8 @@ intel_ddi_config_transcoder_func(struct intel_encoder *encoder, ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state); ctl &= ~TRANS_DDI_FUNC_ENABLE; - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + ctl); } void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state) @@ -641,7 +642,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); - ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); + ctl = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING); @@ -660,7 +662,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK); } - intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl); + intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), + ctl); if (intel_has_quirk(display, QUIRK_INCREASE_DDI_DISABLED_TIME) && intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) { @@ -684,7 +687,7 @@ int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder, if (drm_WARN_ON(dev, !wakeref)) return -ENXIO; - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), + intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), hdcp_mask, enable ? hdcp_mask : 0); intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref); return ret; @@ -718,7 +721,8 @@ bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) else cpu_transcoder = (enum transcoder) pipe; - tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { case TRANS_DDI_MODE_SELECT_HDMI: @@ -782,7 +786,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) { tmp = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); + TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)); switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { default: @@ -823,7 +827,7 @@ static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder, } tmp = intel_de_read(dev_priv, - TRANS_DDI_FUNC_CTL(cpu_transcoder)); + TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder), trans_wakeref); @@ -3025,7 +3029,8 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state, if (is_mst) { enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), + intel_de_rmw(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), TGL_TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK, 0); } @@ -3759,7 +3764,8 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2); } else { - u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); + u32 ctl = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0) return INVALID_TRANSCODER; @@ -3815,7 +3821,8 @@ static void intel_ddi_read_func_ctl(struct intel_encoder *encoder, struct intel_digital_port *dig_port = enc_to_dig_port(encoder); u32 temp, flags = 0; - temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); + temp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); if (temp & TRANS_DDI_PHSYNC) flags |= DRM_MODE_FLAG_PHSYNC; else diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 952780028630..62f8300c73a5 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3507,7 +3507,8 @@ static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) - tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); return tmp & TRANS_DDI_FUNC_ENABLE; } @@ -3622,7 +3623,8 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) - tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); if (!(tmp & TRANS_DDI_FUNC_ENABLE)) continue; @@ -3729,7 +3731,8 @@ static bool hsw_get_transcoder_state(struct intel_crtc *crtc, return false; if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) { - tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); + tmp = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, pipe_config->cpu_transcoder)); if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF) pipe_config->pch_pfit.force_thru = true; diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 0c0433aae26d..176cfac74140 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -935,7 +935,8 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, } /* Get PIPE for handling VBLANK event */ - val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL(dsi_trans)); + val = intel_uncore_read(&dev_priv->uncore, + TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans)); switch (val & TRANS_DDI_EDP_INPUT_MASK) { case TRANS_DDI_EDP_INPUT_A_ON: pipe = PIPE_A; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c772ba19c547..aa633844f849 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1009,7 +1009,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state, clear_act_sent(encoder, old_crtc_state); - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), + intel_de_rmw(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, old_crtc_state->cpu_transcoder), TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); wait_for_act_sent(encoder, old_crtc_state); @@ -1230,7 +1231,7 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, clear_act_sent(encoder, pipe_config); - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, + intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, trans), 0, TRANS_DDI_DP_VC_PAYLOAD_ALLOC); drm_dbg_kms(&dev_priv->drm, "active links %d\n", diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 007e0f9e9304..d33befd7994d 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -34,7 +34,8 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv, * so pipe->transcoder cast is fine here. */ enum transcoder cpu_transcoder = (enum transcoder)pipe; - cur_state = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; + cur_state = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE; } else { cur_state = intel_de_read(dev_priv, FDI_TX_CTL(pipe)) & FDI_TX_ENABLE; } diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c index ba3eca919900..3ebe035f382e 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c @@ -47,7 +47,8 @@ intel_hdcp_disable_hdcp_line_rekeying(struct intel_encoder *encoder, 0, HDCP_LINE_REKEY_DISABLE); else if (IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 1), STEP_B0, STEP_FOREVER) || IS_DISPLAY_IP_STEP(dev_priv, IP_VER(20, 0), STEP_B0, STEP_FOREVER)) - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(hdcp->cpu_transcoder), + intel_de_rmw(dev_priv, + TRANS_DDI_FUNC_CTL(dev_priv, hdcp->cpu_transcoder), 0, TRANS_DDI_HDCP_LINE_REKEY_DISABLE); } } diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index 7704ead5002d..19498ee455fa 100644 --- a/drivers/gpu/drm/i915/display/intel_hdmi.c +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c @@ -83,7 +83,7 @@ assert_hdmi_transcoder_func_disabled(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { drm_WARN(&dev_priv->drm, - intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder)) & + intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)) & TRANS_DDI_FUNC_ENABLE, "HDMI transcoder function enabled, expecting disabled\n"); } diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index 95b4b76d3b45..c66d6d3177c8 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -200,11 +200,11 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) } for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &= + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, trans)) &= ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE); } - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | TRANS_DDI_PORT_MASK); @@ -287,7 +287,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) (DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED); vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= ~DDI_BUF_IS_IDLE; - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |= + vgpu_vreg_t(vgpu, + TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_EDP)) |= (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | TRANS_DDI_FUNC_ENABLE); vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |= @@ -316,7 +317,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) DDI_BUF_CTL_ENABLE; vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE; - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= + vgpu_vreg_t(vgpu, + TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | (PORT_B << TRANS_DDI_PORT_SHIFT) | TRANS_DDI_FUNC_ENABLE); @@ -346,7 +348,8 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) DDI_BUF_CTL_ENABLE; vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE; - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= + vgpu_vreg_t(vgpu, + TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | (PORT_B << TRANS_DDI_PORT_SHIFT) | TRANS_DDI_FUNC_ENABLE); @@ -410,10 +413,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, DPLL_CTRL2) |= DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED; - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | TRANS_DDI_PORT_MASK); - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | (PORT_B << TRANS_DDI_PORT_SHIFT) | TRANS_DDI_FUNC_ENABLE); @@ -436,10 +439,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, DPLL_CTRL2) |= DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_C); vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT; - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | TRANS_DDI_PORT_MASK); - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | (PORT_C << TRANS_DDI_PORT_SHIFT) | TRANS_DDI_FUNC_ENABLE); @@ -462,10 +465,10 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu) vgpu_vreg_t(vgpu, DPLL_CTRL2) |= DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_D); vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT; - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &= + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) &= ~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK | TRANS_DDI_PORT_MASK); - vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |= + vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) |= (TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST | (PORT_D << TRANS_DDI_PORT_SHIFT) | TRANS_DDI_FUNC_ENABLE); diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 7416068e7c82..073edabf24a5 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -656,7 +656,7 @@ static void vgpu_update_refresh_rate(struct intel_vgpu *vgpu) u32 dp_br, link_m, link_n, htotal, vtotal; /* Find DDI/PORT assigned to TRANSCODER_A, expect B or D */ - port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) & + port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(dev_priv, TRANSCODER_A)) & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; if (port != PORT_B && port != PORT_D) { gvt_dbg_dpy("vgpu-%d unsupported PORT_%c\n", vgpu->id, port_name(port)); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5f822b8f1775..195f4993fe02 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3872,7 +3872,7 @@ enum skl_power_gate { #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 -#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A) +#define TRANS_DDI_FUNC_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A) #define TRANS_DDI_FUNC_ENABLE (1 << 31) /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ -- cgit From 76f1b2b1a4481e31a6c9d10a933ebac5073e1e19 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:18 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_DDI_FUNC_CTL2 Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_DDI_FUNC_CTL2 register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/2b61bf9c1f74ae633c99aa34fbf1aa85735cc5b6.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/icl_dsi.c | 6 ++++-- drivers/gpu/drm/i915/display/intel_ddi.c | 9 ++++++--- drivers/gpu/drm/i915/display/intel_display_irq.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 4 files changed, 13 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c index acc80d439352..ae8f6617aa70 100644 --- a/drivers/gpu/drm/i915/display/icl_dsi.c +++ b/drivers/gpu/drm/i915/display/icl_dsi.c @@ -784,7 +784,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder, if (intel_dsi->dual_link) { for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans), + intel_de_rmw(dev_priv, + TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans), 0, PORT_SYNC_MODE_ENABLE); } @@ -1344,7 +1345,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder) if (intel_dsi->dual_link) { for_each_dsi_port(port, intel_dsi->ports) { dsi_trans = dsi_port_to_transcoder(port); - intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans), + intel_de_rmw(dev_priv, + TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans), PORT_SYNC_MODE_ENABLE, 0); } } diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 4a55ef88c414..97355a4a0a55 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -603,7 +603,8 @@ void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, } intel_de_write(dev_priv, - TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2); + TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), + ctl2); } intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder), @@ -640,7 +641,8 @@ void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state if (DISPLAY_VER(dev_priv) >= 11) intel_de_write(dev_priv, - TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0); + TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder), + 0); ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dev_priv, cpu_transcoder)); @@ -3757,7 +3759,8 @@ static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *de u32 master_select; if (DISPLAY_VER(dev_priv) >= 11) { - u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder)); + u32 ctl2 = intel_de_read(dev_priv, + TRANS_DDI_FUNC_CTL2(dev_priv, cpu_transcoder)); if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0) return INVALID_TRANSCODER; diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 176cfac74140..82e1369e5d76 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -914,7 +914,8 @@ static void gen11_dsi_te_interrupt_handler(struct drm_i915_private *dev_priv, * Incase of dual link, TE comes from DSI_1 * this is to check if dual link is enabled */ - val = intel_uncore_read(&dev_priv->uncore, TRANS_DDI_FUNC_CTL2(TRANSCODER_DSI_0)); + val = intel_uncore_read(&dev_priv->uncore, + TRANS_DDI_FUNC_CTL2(dev_priv, TRANSCODER_DSI_0)); val &= PORT_SYNC_MODE_ENABLE; /* diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 195f4993fe02..e7a627f5da4d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3928,7 +3928,7 @@ enum skl_power_gate { #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 -#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A) +#define TRANS_DDI_FUNC_CTL2(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A) #define PORT_SYNC_MODE_ENABLE REG_BIT(4) #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) -- cgit From 3cd5a36df1a9dd8c92fb5b15e2c2ec99e1031120 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:19 +0300 Subject: drm/i915: pass dev_priv explicitly to TGL_DP_TP_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TGL_DP_TP_CTL register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/3d3e2b732ec9372cf6b1ae44b25342179b028b1a.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 97355a4a0a55..9ec3b032affd 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2184,7 +2184,8 @@ i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (DISPLAY_VER(dev_priv) >= 12) - return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state)); + return TGL_DP_TP_CTL(dev_priv, + tgl_dp_tp_transcoder(crtc_state)); else return DP_TP_CTL(encoder->port); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e7a627f5da4d..22aa7dd6a183 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3941,7 +3941,7 @@ enum skl_power_gate { #define _DP_TP_CTL_B 0x64140 #define _TGL_DP_TP_CTL_A 0x60540 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) -#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A) +#define TGL_DP_TP_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A) #define DP_TP_CTL_ENABLE (1 << 31) #define DP_TP_CTL_FEC_ENABLE (1 << 30) #define DP_TP_CTL_MODE_SST (0 << 27) -- cgit From b11bf614f9ce4540593c4cf287a50ee2918c3163 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:20 +0300 Subject: drm/i915: pass dev_priv explicitly to TGL_DP_TP_STATUS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TGL_DP_TP_STATUS register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/c7aaf0e981324bfc5b3aec31f30a7b1a158ba568.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 9ec3b032affd..f8295f11bd60 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2196,7 +2196,8 @@ i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); if (DISPLAY_VER(dev_priv) >= 12) - return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state)); + return TGL_DP_TP_STATUS(dev_priv, + tgl_dp_tp_transcoder(crtc_state)); else return DP_TP_STATUS(encoder->port); } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 22aa7dd6a183..cb9b02b20acf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3967,7 +3967,7 @@ enum skl_power_gate { #define _DP_TP_STATUS_B 0x64144 #define _TGL_DP_TP_STATUS_A 0x60544 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) -#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A) +#define TGL_DP_TP_STATUS(dev_priv, tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A) #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) #define DP_TP_STATUS_IDLE_DONE (1 << 25) #define DP_TP_STATUS_ACT_SENT (1 << 24) -- cgit From 0623993cad61186856a83ef25312708c5079098e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:21 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_MSA_MISC Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_MSA_MISC register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/1a9c0a0f8c5bba31138f0c7aebdf839b9b30298c.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_ddi.c | 3 ++- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f8295f11bd60..f306e0d2d418 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -440,7 +440,8 @@ void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, if (intel_dp_needs_vsc_sdp(crtc_state, conn_state)) temp |= DP_MSA_MISC_COLOR_VSC_SDP; - intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp); + intel_de_write(dev_priv, TRANS_MSA_MISC(dev_priv, cpu_transcoder), + temp); } static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index cb9b02b20acf..637b446afb82 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4148,7 +4148,7 @@ enum skl_power_gate { #define _TRANSB_MSA_MISC 0x61410 #define _TRANSC_MSA_MISC 0x62410 #define _TRANS_EDP_MSA_MISC 0x6f410 -#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC) +#define TRANS_MSA_MISC(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC) /* See DP_MSA_MISC_* for the bit definitions */ #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C -- cgit From e4a4142bf31673faf153f39c666a01da6f0c42df Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:22 +0300 Subject: drm/i915: pass dev_priv explicitly to TRANS_SET_CONTEXT_LATENCY Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the TRANS_SET_CONTEXT_LATENCY register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/989f89994edae0829e3b6d5d6e3d8a521f0eda00.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 62f8300c73a5..c608329dac42 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2703,7 +2703,8 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start. */ if (DISPLAY_VER(dev_priv) >= 13) { - intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder), + intel_de_write(dev_priv, + TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder), crtc_vblank_start - crtc_vdisplay); /* @@ -2860,7 +2861,8 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder)) adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay + - intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder)); + intel_de_read(dev_priv, + TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder)); } static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 637b446afb82..7d68f6806e5b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4155,7 +4155,7 @@ enum skl_power_gate { #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C -#define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) +#define TRANS_SET_CONTEXT_LATENCY(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) -- cgit From d9abe5f9e575e7df0e245694c13a0aa4e787f009 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:23 +0300 Subject: drm/i915: pass dev_priv explicitly to MTL_CLKGATE_DIS_TRANS Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the MTL_CLKGATE_DIS_TRANS register macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/b330d86c5e3012513daa36dceffd2db45f0d7850.1717514638.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_psr.c | 5 +++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 4a4124a92a0d..21f6a4fa86a4 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1716,7 +1716,8 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, if (!intel_dp->psr.panel_replay_enabled && IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, - MTL_CLKGATE_DIS_TRANS(cpu_transcoder), 0, + MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder), + 0, MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS); else if (IS_ALDERLAKE_P(dev_priv)) intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, 0, @@ -1897,7 +1898,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) if (!intel_dp->psr.panel_replay_enabled && IS_DISPLAY_IP_STEP(dev_priv, IP_VER(14, 0), STEP_A0, STEP_B0)) intel_de_rmw(dev_priv, - MTL_CLKGATE_DIS_TRANS(cpu_transcoder), + MTL_CLKGATE_DIS_TRANS(dev_priv, cpu_transcoder), MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS, 0); else if (IS_ALDERLAKE_P(dev_priv)) intel_de_rmw(dev_priv, CLKGATE_DIS_MISC, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7d68f6806e5b..15ad35178f1a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4637,7 +4637,7 @@ enum skl_power_gate { #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 -#define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) +#define MTL_CLKGATE_DIS_TRANS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) -- cgit From 106fb076aa5ce24bfac3037aa655dbeb26cc8ff8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 7 Jun 2024 11:07:06 +0300 Subject: drm/i915: do not select ACPI_BUTTON MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We stopped using ACPI button in commit 05c72e77ccda ("drm/i915: Nuke the LVDS lid notifier"). Also stop force enabling the ACPI_BUTTON config. Cc: Ville Syrjälä Closes: https://lore.kernel.org/r/ZmGsJsXhHcPV48XJ@intel.com Reviewed-by: Ville Syrjälä Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/060d687c3a80cd94f065e637200dd10fea7b979f.1717747542.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig index 4f0d18a16b0f..e90ad3cd3f6d 100644 --- a/drivers/gpu/drm/i915/Kconfig +++ b/drivers/gpu/drm/i915/Kconfig @@ -29,7 +29,6 @@ config DRM_I915 select X86_PLATFORM_DEVICES if ACPI select ACPI_WMI if ACPI select ACPI_VIDEO if ACPI - select ACPI_BUTTON if ACPI select SYNC_FILE select IOSF_MBI if X86 select CRC32 -- cgit From 80c414772d93f2f21af2483497f424c6cc7b1132 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 5 Jun 2024 16:47:55 +0300 Subject: drm/i915/bios: Define block 46 chromaticity coordinates properly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The VBT spec does a very poor job of defining how the chromaticity coordinates in block 46 are laid out. After double checking the Windows implementation it turns out these more or less match the EDID definition, where the 10bit values are split into 2bit + 8bit chunks. Adjust our struct definition to reflect that. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240605134756.17099-1-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index 862c5923b83d..da8694771f69 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -1376,16 +1376,23 @@ struct chromaticity { u8 chromaticity_from_edid_base_block:1; u8 rsvd:6; - u8 red_green; - u8 blue_white; - u8 red_x; - u8 red_y; - u8 green_x; - u8 green_y; - u8 blue_x; - u8 blue_y; - u8 white_x; - u8 white_y; + u8 green_y_lo:2; + u8 green_x_lo:2; + u8 red_y_lo:2; + u8 red_x_lo:2; + u8 white_y_lo:2; + u8 white_x_lo:2; + u8 blue_y_lo:2; + u8 blue_x_lo:2; + + u8 red_x_hi; + u8 red_y_hi; + u8 green_x_hi; + u8 green_y_hi; + u8 blue_x_hi; + u8 blue_y_hi; + u8 white_x_hi; + u8 white_y_hi; } __packed; struct bdb_chromaticity { -- cgit From 3e8daf14c47d79a35a4ad69d12f5a9b6450e9ecd Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Wed, 5 Jun 2024 16:47:56 +0300 Subject: drm/i915/bios: Define the "luminance and gamma" sub-struct of block 46 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since BDB version 211 block 46 has included more luminance and gamma related information. Define it fully. The data is semi-based on DisplayID v2.0 apparently. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240605134756.17099-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h index da8694771f69..1af8407e2081 100644 --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h @@ -1395,8 +1395,20 @@ struct chromaticity { u8 white_y_hi; } __packed; +struct luminance_and_gamma { + u8 luminance_enable:1; /* 211+ */ + u8 gamma_enable:1; /* 211+ */ + u8 rsvd:6; + + u16 min_luminance; /* 211+ */ + u16 max_luminance; /* 211+ */ + u16 one_percent_max_luminance; /* 211+ */ + u8 gamma; /* 211+ */ +} __packed; + struct bdb_chromaticity { struct chromaticity chromaticity[16]; + struct luminance_and_gamma luminance_and_gamma[16]; /* 211+ */ } __packed; /* -- cgit From ba9bbbe1499a8f14858e89cd4a21bf2990cfb0de Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Tue, 4 Jun 2024 18:26:16 +0300 Subject: drm/i915: pass dev_priv explicitly to HSW_STEREO_3D_CTL Avoid the implicit dev_priv local variable use, and pass dev_priv explicitly to the HSW_STEREO_3D_CTL register macro. Reviewed-by: Rodrigo Vivi Signed-off-by: Jani Nikula Link: https://patchwork.freedesktop.org/patch/msgid/76f980f5ed3638746c6b58dec7d0bd8c43a37987.1717514638.git.jani.nikula@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 15ad35178f1a..7daf902772e4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3412,7 +3412,7 @@ #define S3D_ENABLE (1 << 31) #define _HSW_STEREO_3D_CTL_B 0x71020 -#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) +#define HSW_STEREO_3D_CTL(dev_priv, trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) #define _PCH_TRANS_HTOTAL_B 0xe1000 #define _PCH_TRANS_HBLANK_B 0xe1004 -- cgit From 76dbc41608167d531f9c45d60054fd1f76498785 Mon Sep 17 00:00:00 2001 From: Balasubramani Vivekanandan Date: Tue, 4 Jun 2024 19:30:21 +0530 Subject: drm/i915/display/bmg: Add platform descriptor Platform descriptor defined and PCI IDs added for Battlemage. Signed-off-by: Balasubramani Vivekanandan Reviewed-by: Radhakrishna Sripada Signed-off-by: Radhakrishna Sripada Link: https://patchwork.freedesktop.org/patch/msgid/20240604140021.1357502-1-balasubramani.vivekanandan@intel.com --- drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++ drivers/gpu/drm/i915/display/intel_display_device.h | 2 ++ include/drm/intel/i915_pciids.h | 8 ++++++++ 3 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c index b35422da7f6c..dd7dce4b0e7a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.c +++ b/drivers/gpu/drm/i915/display/intel_display_device.c @@ -1110,6 +1110,10 @@ static const struct platform_desc lnl_desc = { PLATFORM(LUNARLAKE), }; +static const struct platform_desc bmg_desc = { + PLATFORM(BATTLEMAGE), +}; + __diag_pop(); /* @@ -1178,6 +1182,7 @@ static const struct { INTEL_DG2_IDS(INTEL_DISPLAY_DEVICE, &dg2_desc), INTEL_MTL_IDS(INTEL_DISPLAY_DEVICE, &mtl_desc), INTEL_LNL_IDS(INTEL_DISPLAY_DEVICE, &lnl_desc), + INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc), }; static const struct { diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index e1d9947394dc..44cda6c3e4d8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -68,6 +68,8 @@ enum intel_display_platform { INTEL_DISPLAY_METEORLAKE, /* Display ver 20 (based on GMD ID) */ INTEL_DISPLAY_LUNARLAKE, + /* Display ver 14.1 (based on GMD ID) */ + INTEL_DISPLAY_BATTLEMAGE, }; enum intel_display_subplatform { diff --git a/include/drm/intel/i915_pciids.h b/include/drm/intel/i915_pciids.h index 7ae7ee11ef38..b21374f76df2 100644 --- a/include/drm/intel/i915_pciids.h +++ b/include/drm/intel/i915_pciids.h @@ -789,4 +789,12 @@ MACRO__(0x64A0, ## __VA_ARGS__), \ MACRO__(0x64B0, ## __VA_ARGS__) +/* BMG */ +#define INTEL_BMG_IDS(MACRO__, ...) \ + MACRO__(0xE202, ## __VA_ARGS__), \ + MACRO__(0xE20B, ## __VA_ARGS__), \ + MACRO__(0xE20C, ## __VA_ARGS__), \ + MACRO__(0xE20D, ## __VA_ARGS__), \ + MACRO__(0xE212, ## __VA_ARGS__) + #endif /* _I915_PCIIDS_H */ -- cgit From fc8fc81cb8302831146f806f96a50d6debf5aaf3 Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Mon, 10 Jun 2024 12:51:54 +0530 Subject: drm/i915: Update indentation for VRR registers and bits Update the indentation for the VRR register definition and its bits, and fix checkpatch issues to ensure smooth movement of registers and bits. --v2: - Keep XELPD_VRR_CTL_VRR_GUARDBAND(x) to avoid readability (Ankit). - Fix all indentation related VRR registers and bits instead of checkpatch one. Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-2-mitulkumar.ajitkumar.golani@intel.com --- drivers/gpu/drm/i915/i915_reg.h | 174 ++++++++++++++++++++-------------------- 1 file changed, 87 insertions(+), 87 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 7daf902772e4..3fbf639e6aa0 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1148,104 +1148,104 @@ #define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) /* VRR registers */ -#define _TRANS_VRR_CTL_A 0x60420 -#define _TRANS_VRR_CTL_B 0x61420 -#define _TRANS_VRR_CTL_C 0x62420 -#define _TRANS_VRR_CTL_D 0x63420 -#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) -#define VRR_CTL_VRR_ENABLE REG_BIT(31) -#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) -#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) -#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) -#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) -#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) -#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) - -#define _TRANS_VRR_VMAX_A 0x60424 -#define _TRANS_VRR_VMAX_B 0x61424 -#define _TRANS_VRR_VMAX_C 0x62424 -#define _TRANS_VRR_VMAX_D 0x63424 +#define _TRANS_VRR_CTL_A 0x60420 +#define _TRANS_VRR_CTL_B 0x61420 +#define _TRANS_VRR_CTL_C 0x62420 +#define _TRANS_VRR_CTL_D 0x63420 +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) +#define VRR_CTL_VRR_ENABLE REG_BIT(31) +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) +#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) +#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) +#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) + +#define _TRANS_VRR_VMAX_A 0x60424 +#define _TRANS_VRR_VMAX_B 0x61424 +#define _TRANS_VRR_VMAX_C 0x62424 +#define _TRANS_VRR_VMAX_D 0x63424 #define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) -#define VRR_VMAX_MASK REG_GENMASK(19, 0) +#define VRR_VMAX_MASK REG_GENMASK(19, 0) -#define _TRANS_VRR_VMIN_A 0x60434 -#define _TRANS_VRR_VMIN_B 0x61434 -#define _TRANS_VRR_VMIN_C 0x62434 -#define _TRANS_VRR_VMIN_D 0x63434 +#define _TRANS_VRR_VMIN_A 0x60434 +#define _TRANS_VRR_VMIN_B 0x61434 +#define _TRANS_VRR_VMIN_C 0x62434 +#define _TRANS_VRR_VMIN_D 0x63434 #define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) -#define VRR_VMIN_MASK REG_GENMASK(15, 0) +#define VRR_VMIN_MASK REG_GENMASK(15, 0) -#define _TRANS_VRR_VMAXSHIFT_A 0x60428 -#define _TRANS_VRR_VMAXSHIFT_B 0x61428 -#define _TRANS_VRR_VMAXSHIFT_C 0x62428 -#define _TRANS_VRR_VMAXSHIFT_D 0x63428 +#define _TRANS_VRR_VMAXSHIFT_A 0x60428 +#define _TRANS_VRR_VMAXSHIFT_B 0x61428 +#define _TRANS_VRR_VMAXSHIFT_C 0x62428 +#define _TRANS_VRR_VMAXSHIFT_D 0x63428 #define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ - _TRANS_VRR_VMAXSHIFT_A) -#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) -#define VRR_VMAXSHIFT_DEC REG_BIT(16) -#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) - -#define _TRANS_VRR_STATUS_A 0x6042C -#define _TRANS_VRR_STATUS_B 0x6142C -#define _TRANS_VRR_STATUS_C 0x6242C -#define _TRANS_VRR_STATUS_D 0x6342C -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) -#define VRR_STATUS_VMAX_REACHED REG_BIT(31) -#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) -#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) -#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) -#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) -#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) -#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) -#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) -#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) -#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) -#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) -#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) -#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) -#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) - -#define _TRANS_VRR_VTOTAL_PREV_A 0x60480 -#define _TRANS_VRR_VTOTAL_PREV_B 0x61480 -#define _TRANS_VRR_VTOTAL_PREV_C 0x62480 -#define _TRANS_VRR_VTOTAL_PREV_D 0x63480 + _TRANS_VRR_VMAXSHIFT_A) +#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) +#define VRR_VMAXSHIFT_DEC REG_BIT(16) +#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) + +#define _TRANS_VRR_STATUS_A 0x6042c +#define _TRANS_VRR_STATUS_B 0x6142c +#define _TRANS_VRR_STATUS_C 0x6242c +#define _TRANS_VRR_STATUS_D 0x6342c +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) +#define VRR_STATUS_VMAX_REACHED REG_BIT(31) +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) +#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) +#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) +#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) +#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) +#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) +#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) +#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) +#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) +#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) + +#define _TRANS_VRR_VTOTAL_PREV_A 0x60480 +#define _TRANS_VRR_VTOTAL_PREV_B 0x61480 +#define _TRANS_VRR_VTOTAL_PREV_C 0x62480 +#define _TRANS_VRR_VTOTAL_PREV_D 0x63480 #define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ - _TRANS_VRR_VTOTAL_PREV_A) -#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) -#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) -#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) -#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) - -#define _TRANS_VRR_FLIPLINE_A 0x60438 -#define _TRANS_VRR_FLIPLINE_B 0x61438 -#define _TRANS_VRR_FLIPLINE_C 0x62438 -#define _TRANS_VRR_FLIPLINE_D 0x63438 + _TRANS_VRR_VTOTAL_PREV_A) +#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) +#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) +#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) +#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_FLIPLINE_A 0x60438 +#define _TRANS_VRR_FLIPLINE_B 0x61438 +#define _TRANS_VRR_FLIPLINE_C 0x62438 +#define _TRANS_VRR_FLIPLINE_D 0x63438 #define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ - _TRANS_VRR_FLIPLINE_A) -#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) + _TRANS_VRR_FLIPLINE_A) +#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) -#define _TRANS_VRR_STATUS2_A 0x6043C -#define _TRANS_VRR_STATUS2_B 0x6143C -#define _TRANS_VRR_STATUS2_C 0x6243C -#define _TRANS_VRR_STATUS2_D 0x6343C +#define _TRANS_VRR_STATUS2_A 0x6043c +#define _TRANS_VRR_STATUS2_B 0x6143c +#define _TRANS_VRR_STATUS2_C 0x6243c +#define _TRANS_VRR_STATUS2_D 0x6343c #define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) -#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) +#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) -#define _TRANS_PUSH_A 0x60A70 -#define _TRANS_PUSH_B 0x61A70 -#define _TRANS_PUSH_C 0x62A70 -#define _TRANS_PUSH_D 0x63A70 +#define _TRANS_PUSH_A 0x60a70 +#define _TRANS_PUSH_B 0x61a70 +#define _TRANS_PUSH_C 0x62a70 +#define _TRANS_PUSH_D 0x63a70 #define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) -#define TRANS_PUSH_EN REG_BIT(31) -#define TRANS_PUSH_SEND REG_BIT(30) - -#define _TRANS_VRR_VSYNC_A 0x60078 -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) -#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) -#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) -#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) -#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) +#define TRANS_PUSH_EN REG_BIT(31) +#define TRANS_PUSH_SEND REG_BIT(30) + +#define _TRANS_VRR_VSYNC_A 0x60078 +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) /* VGA port control */ #define ADPA _MMIO(0x61100) -- cgit From 6eb82761887a6e031b6cb85d4491f434b9c7e73c Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Mon, 10 Jun 2024 12:51:55 +0530 Subject: drm/i915: Separate VRR related register definitions Move VRR related register definitions to a separate file called intel_vrr_regs.h. Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-3-mitulkumar.ajitkumar.golani@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 1 + drivers/gpu/drm/i915/display/intel_vrr_regs.h | 111 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 100 ----------------------- 3 files changed, 112 insertions(+), 100 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_vrr_regs.h diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 5f3657aa8313..871e6e6a184a 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -9,6 +9,7 @@ #include "intel_de.h" #include "intel_display_types.h" #include "intel_vrr.h" +#include "intel_vrr_regs.h" #include "intel_dp.h" bool intel_vrr_is_capable(struct intel_connector *connector) diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h new file mode 100644 index 000000000000..c3237d5c38df --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_VRR_REGS_H__ +#define __INTEL_VRR_REGS_H__ + +#include "intel_display_reg_defs.h" + +/* VRR registers */ +#define _TRANS_VRR_CTL_A 0x60420 +#define _TRANS_VRR_CTL_B 0x61420 +#define _TRANS_VRR_CTL_C 0x62420 +#define _TRANS_VRR_CTL_D 0x63420 +#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) +#define VRR_CTL_VRR_ENABLE REG_BIT(31) +#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) +#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) +#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) +#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) +#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) +#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) +#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) + +#define _TRANS_VRR_VMAX_A 0x60424 +#define _TRANS_VRR_VMAX_B 0x61424 +#define _TRANS_VRR_VMAX_C 0x62424 +#define _TRANS_VRR_VMAX_D 0x63424 +#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) +#define VRR_VMAX_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_VMIN_A 0x60434 +#define _TRANS_VRR_VMIN_B 0x61434 +#define _TRANS_VRR_VMIN_C 0x62434 +#define _TRANS_VRR_VMIN_D 0x63434 +#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) +#define VRR_VMIN_MASK REG_GENMASK(15, 0) + +#define _TRANS_VRR_VMAXSHIFT_A 0x60428 +#define _TRANS_VRR_VMAXSHIFT_B 0x61428 +#define _TRANS_VRR_VMAXSHIFT_C 0x62428 +#define _TRANS_VRR_VMAXSHIFT_D 0x63428 +#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ + _TRANS_VRR_VMAXSHIFT_A) +#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) +#define VRR_VMAXSHIFT_DEC REG_BIT(16) +#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) + +#define _TRANS_VRR_STATUS_A 0x6042c +#define _TRANS_VRR_STATUS_B 0x6142c +#define _TRANS_VRR_STATUS_C 0x6242c +#define _TRANS_VRR_STATUS_D 0x6342c +#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) +#define VRR_STATUS_VMAX_REACHED REG_BIT(31) +#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) +#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) +#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) +#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) +#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) +#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) +#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) +#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) +#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) +#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) +#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) +#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) +#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) + +#define _TRANS_VRR_VTOTAL_PREV_A 0x60480 +#define _TRANS_VRR_VTOTAL_PREV_B 0x61480 +#define _TRANS_VRR_VTOTAL_PREV_C 0x62480 +#define _TRANS_VRR_VTOTAL_PREV_D 0x63480 +#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ + _TRANS_VRR_VTOTAL_PREV_A) +#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) +#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) +#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) +#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_FLIPLINE_A 0x60438 +#define _TRANS_VRR_FLIPLINE_B 0x61438 +#define _TRANS_VRR_FLIPLINE_C 0x62438 +#define _TRANS_VRR_FLIPLINE_D 0x63438 +#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ + _TRANS_VRR_FLIPLINE_A) +#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) + +#define _TRANS_VRR_STATUS2_A 0x6043c +#define _TRANS_VRR_STATUS2_B 0x6143c +#define _TRANS_VRR_STATUS2_C 0x6243c +#define _TRANS_VRR_STATUS2_D 0x6343c +#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) +#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) + +#define _TRANS_PUSH_A 0x60a70 +#define _TRANS_PUSH_B 0x61a70 +#define _TRANS_PUSH_C 0x62a70 +#define _TRANS_PUSH_D 0x63a70 +#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) +#define TRANS_PUSH_EN REG_BIT(31) +#define TRANS_PUSH_SEND REG_BIT(30) + +#define _TRANS_VRR_VSYNC_A 0x60078 +#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) +#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) +#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) + +#endif /* __INTEL_VRR_REGS__ */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3fbf639e6aa0..df58cf38e144 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1147,106 +1147,6 @@ #define PIPESRC(dev_priv, pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) #define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) -/* VRR registers */ -#define _TRANS_VRR_CTL_A 0x60420 -#define _TRANS_VRR_CTL_B 0x61420 -#define _TRANS_VRR_CTL_C 0x62420 -#define _TRANS_VRR_CTL_D 0x63420 -#define TRANS_VRR_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) -#define VRR_CTL_VRR_ENABLE REG_BIT(31) -#define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) -#define VRR_CTL_FLIP_LINE_EN REG_BIT(29) -#define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3) -#define VRR_CTL_PIPELINE_FULL(x) REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x)) -#define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0) -#define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0) -#define XELPD_VRR_CTL_VRR_GUARDBAND(x) REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x)) - -#define _TRANS_VRR_VMAX_A 0x60424 -#define _TRANS_VRR_VMAX_B 0x61424 -#define _TRANS_VRR_VMAX_C 0x62424 -#define _TRANS_VRR_VMAX_D 0x63424 -#define TRANS_VRR_VMAX(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) -#define VRR_VMAX_MASK REG_GENMASK(19, 0) - -#define _TRANS_VRR_VMIN_A 0x60434 -#define _TRANS_VRR_VMIN_B 0x61434 -#define _TRANS_VRR_VMIN_C 0x62434 -#define _TRANS_VRR_VMIN_D 0x63434 -#define TRANS_VRR_VMIN(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) -#define VRR_VMIN_MASK REG_GENMASK(15, 0) - -#define _TRANS_VRR_VMAXSHIFT_A 0x60428 -#define _TRANS_VRR_VMAXSHIFT_B 0x61428 -#define _TRANS_VRR_VMAXSHIFT_C 0x62428 -#define _TRANS_VRR_VMAXSHIFT_D 0x63428 -#define TRANS_VRR_VMAXSHIFT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ - _TRANS_VRR_VMAXSHIFT_A) -#define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) -#define VRR_VMAXSHIFT_DEC REG_BIT(16) -#define VRR_VMAXSHIFT_INC_MASK REG_GENMASK(12, 0) - -#define _TRANS_VRR_STATUS_A 0x6042c -#define _TRANS_VRR_STATUS_B 0x6142c -#define _TRANS_VRR_STATUS_C 0x6242c -#define _TRANS_VRR_STATUS_D 0x6342c -#define TRANS_VRR_STATUS(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) -#define VRR_STATUS_VMAX_REACHED REG_BIT(31) -#define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) -#define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) -#define VRR_STATUS_NO_FLIP_FRAME REG_BIT(28) -#define VRR_STATUS_VRR_EN_LIVE REG_BIT(27) -#define VRR_STATUS_FLIPS_SERVICED REG_BIT(26) -#define VRR_STATUS_VBLANK_MASK REG_GENMASK(22, 20) -#define STATUS_FSM_IDLE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0) -#define STATUS_FSM_WAIT_TILL_FDB REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1) -#define STATUS_FSM_WAIT_TILL_FS REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2) -#define STATUS_FSM_WAIT_TILL_FLIP REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3) -#define STATUS_FSM_PIPELINE_FILL REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4) -#define STATUS_FSM_ACTIVE REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5) -#define STATUS_FSM_LEGACY_VBLANK REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6) - -#define _TRANS_VRR_VTOTAL_PREV_A 0x60480 -#define _TRANS_VRR_VTOTAL_PREV_B 0x61480 -#define _TRANS_VRR_VTOTAL_PREV_C 0x62480 -#define _TRANS_VRR_VTOTAL_PREV_D 0x63480 -#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ - _TRANS_VRR_VTOTAL_PREV_A) -#define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) -#define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) -#define VRR_VTOTAL_FLIP_AFTER_DBLBUF REG_BIT(29) -#define VRR_VTOTAL_PREV_FRAME_MASK REG_GENMASK(19, 0) - -#define _TRANS_VRR_FLIPLINE_A 0x60438 -#define _TRANS_VRR_FLIPLINE_B 0x61438 -#define _TRANS_VRR_FLIPLINE_C 0x62438 -#define _TRANS_VRR_FLIPLINE_D 0x63438 -#define TRANS_VRR_FLIPLINE(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, \ - _TRANS_VRR_FLIPLINE_A) -#define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) - -#define _TRANS_VRR_STATUS2_A 0x6043c -#define _TRANS_VRR_STATUS2_B 0x6143c -#define _TRANS_VRR_STATUS2_C 0x6243c -#define _TRANS_VRR_STATUS2_D 0x6343c -#define TRANS_VRR_STATUS2(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) -#define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) - -#define _TRANS_PUSH_A 0x60a70 -#define _TRANS_PUSH_B 0x61a70 -#define _TRANS_PUSH_C 0x62a70 -#define _TRANS_PUSH_D 0x63a70 -#define TRANS_PUSH(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) -#define TRANS_PUSH_EN REG_BIT(31) -#define TRANS_PUSH_SEND REG_BIT(30) - -#define _TRANS_VRR_VSYNC_A 0x60078 -#define TRANS_VRR_VSYNC(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) -#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) -#define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) -#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) -#define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) - /* VGA port control */ #define ADPA _MMIO(0x61100) #define PCH_ADPA _MMIO(0xe1100) -- cgit From 06173340336c8f21ed5151a93a5398a8725c4704 Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Mon, 10 Jun 2024 12:51:56 +0530 Subject: drm/i915: Define and compute Transcoder CMRR registers Add register definitions for Transcoder Fixed Average Vtotal mode/CMRR function, with the necessary bitfields. Compute these registers when CMRR is enabled, extending Adaptive refresh rate capabilities. --v2: - Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani] - Fix indent and order based on register offset. [Jani] --v3: - Removing RFC tag. --v4: - Update place holder for CMRR register definition. (Jani) --v5: - Add CMRR register definitions to a separate file intel_vrr_reg.h. --v6: - Fixed indentation. (Jani) - Add dependency header intel_display_reg_defs.h. (Jani) - Rename file name to intel_vrr_regs.h instead of reg.h (Jani) --v7: - Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing, as it is already being done during intel_vrr_enable. (Ankit) Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-4-mitulkumar.ajitkumar.golani@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 23 +++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_display_types.h | 6 ++++++ drivers/gpu/drm/i915/display/intel_vrr.c | 20 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_vrr_regs.h | 14 +++++++++++++ 4 files changed, 62 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index c608329dac42..33f5a3ef2e94 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -1006,6 +1006,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state, old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full; } +static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state, + const struct intel_crtc_state *new_crtc_state) +{ + return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m || + old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n; +} + static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state, const struct intel_crtc_state *new_crtc_state) { @@ -5078,6 +5085,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, } \ } while (0) +#define PIPE_CONF_CHECK_LLI(name) do { \ + if (current_config->name != pipe_config->name) { \ + pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \ + "(expected %lli, found %lli)", \ + current_config->name, \ + pipe_config->name); \ + ret = false; \ + } \ +} while (0) + #define PIPE_CONF_CHECK_BOOL(name) do { \ if (current_config->name != pipe_config->name) { \ BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \ @@ -5456,10 +5473,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.guardband); PIPE_CONF_CHECK_I(vrr.vsync_start); PIPE_CONF_CHECK_I(vrr.vsync_end); + PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); + PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); } #undef PIPE_CONF_CHECK_X #undef PIPE_CONF_CHECK_I +#undef PIPE_CONF_CHECK_LLI #undef PIPE_CONF_CHECK_BOOL #undef PIPE_CONF_CHECK_P #undef PIPE_CONF_CHECK_FLAGS @@ -6848,7 +6868,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state, intel_crtc_needs_fastset(new_crtc_state)) icl_set_pipe_chicken(new_crtc_state); - if (vrr_params_changed(old_crtc_state, new_crtc_state)) + if (vrr_params_changed(old_crtc_state, new_crtc_state) || + cmrr_params_changed(old_crtc_state, new_crtc_state)) intel_vrr_set_transcoder_timings(new_crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 83d6a3d901fd..098cabc15c7f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1402,6 +1402,12 @@ struct intel_crtc_state { u32 vsync_end, vsync_start; } vrr; + /* Content Match Refresh Rate state */ + struct { + bool enable; + u64 cmrr_n, cmrr_m; + } cmrr; + /* Stream Splitter for eDP MSO */ struct { bool enable; diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 871e6e6a184a..d2f854d9d18b 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -219,6 +219,17 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) return; } + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_m)); + intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder), + upper_32_bits(crtc_state->cmrr.cmrr_n)); + intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder), + lower_32_bits(crtc_state->cmrr.cmrr_n)); + } + intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder), crtc_state->vrr.vmin - 1); intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder), @@ -307,6 +318,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (crtc_state->cmrr.enable) { + crtc_state->cmrr.cmrr_n = + intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder), + TRANS_CMRR_N_HI(dev_priv, cpu_transcoder)); + crtc_state->cmrr.cmrr_m = + intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder), + TRANS_CMRR_M_HI(dev_priv, cpu_transcoder)); + } + if (DISPLAY_VER(dev_priv) >= 13) crtc_state->vrr.guardband = REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl); diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h index c3237d5c38df..20267ec12f5a 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -108,4 +108,18 @@ #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) #define VRR_VSYNC_START(vsync_start) REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) +/*CMRR Registers*/ + +#define _TRANS_CMRR_M_LO_A 0x604F0 +#define TRANS_CMRR_M_LO(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A) + +#define _TRANS_CMRR_M_HI_A 0x604F4 +#define TRANS_CMRR_M_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A) + +#define _TRANS_CMRR_N_LO_A 0x604F8 +#define TRANS_CMRR_N_LO(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A) + +#define _TRANS_CMRR_N_HI_A 0x604FC +#define TRANS_CMRR_N_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A) + #endif /* __INTEL_VRR_REGS__ */ -- cgit From de065ceeaa2f78c770d5dc586fbd4fa4f915c606 Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Mon, 10 Jun 2024 12:51:57 +0530 Subject: drm/i915: Update trans_vrr_ctl flag when cmrr is computed Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable is set, With this commit setting the stage for subsequent CMRR enablement. --v2: - Check pipe active state in cmrr enabling. [Jani] - Remove usage of bitwise OR on booleans. [Jani] - Revert unrelated changes. [Jani] - Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani] - Simplify whole if-ladder in intel_vrr_enable. [Jani] - Revert patch restructuring mistakes in intel_vrr_get_config. [Jani] --v3: - Check pipe active state in cmrr disabling.[Jani] - Correct messed up condition in intel_vrr_enable. [Jani] --v4: - Removing RFC tag. --v5: - CMRR handling in co-existatnce of LRR and DRRS. --v7: - Rebase on top of AS SDP merge. --v8: - Remove cmrr_enabling/disabling and update commit message. (Ankit) --v9: - Revert removed line(Ankit). Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-5-mitulkumar.ajitkumar.golani@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 10 ++++++++-- drivers/gpu/drm/i915/display/intel_vrr_regs.h | 2 ++ 2 files changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index d2f854d9d18b..19b364074de0 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -282,8 +282,14 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) VRR_VSYNC_END(crtc_state->vrr.vsync_end) | VRR_VSYNC_START(crtc_state->vrr.vsync_start)); - intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), - VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + if (crtc_state->cmrr.enable) { + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), + VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE | + trans_vrr_ctl(crtc_state)); + } else { + intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder), + VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); + } } void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h index 20267ec12f5a..6ed0e0dc97e7 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -122,4 +122,6 @@ #define _TRANS_CMRR_N_HI_A 0x604FC #define TRANS_CMRR_N_HI(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A) +#define VRR_CTL_CMRR_ENABLE REG_BIT(27) + #endif /* __INTEL_VRR_REGS__ */ -- cgit From a20c6d954d75b2e188618e36de43d13d413d4e06 Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Mon, 10 Jun 2024 12:51:58 +0530 Subject: drm/dp: Add refresh rate divider to struct representing AS SDP Add target_rr_divider to structure representing AS SDP. It is valid only in FAVT mode, sink device ignores the bit in AVT mode. --v2: - Update commit header and send patch to dri-devel. Signed-off-by: Mitul Golani Reviewed-by: Arun R Murthy Acked-by: Maxime Ripard Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-6-mitulkumar.ajitkumar.golani@intel.com --- include/drm/display/drm_dp_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h index 8bed890eec2c..393dbf8cf6ab 100644 --- a/include/drm/display/drm_dp_helper.h +++ b/include/drm/display/drm_dp_helper.h @@ -122,6 +122,7 @@ struct drm_dp_as_sdp { int target_rr; int duration_incr_ms; int duration_decr_ms; + bool target_rr_divider; enum operation_mode mode; }; -- cgit From eba88f28121507b14b328c6e61818c794f313b17 Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Mon, 10 Jun 2024 12:51:59 +0530 Subject: drm/i915/display: Add support for pack and unpack Add support of pack and unpack for target_rr_divider. --v2: - Set Target Refresh Rate Divider bit when related AS SDP bit is set (Ankit). --v3: - target_rr_divider is bools so set accordingly (Ankit). Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-7-mitulkumar.ajitkumar.golani@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index fd054e16850d..ac81b172b1ec 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4232,6 +4232,9 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp, sdp->db[3] = as_sdp->target_rr & 0xFF; sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3; + if (as_sdp->target_rr_divider) + sdp->db[4] |= 0x20; + return length; } @@ -4413,6 +4416,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp, as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE; as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1]; as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3); + as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false; return 0; } -- cgit From 0612514db728a28982759e62da3c76444ae15281 Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Mon, 10 Jun 2024 12:52:00 +0530 Subject: drm/i915/display: Compute Adaptive sync SDP params Compute params for Adaptive Sync SDP when Fixed Average Vtotal mode is enabled. --v2: Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit). --v3: - Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit). - check cmrr.enable when CMRR flags are set during intel_dp_compute_as_sdp. --v4: - Use drm_mode_vrefresh instead of manual calculation (Ankit). Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-8-mitulkumar.ajitkumar.golani@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index ac81b172b1ec..b5915c23302f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2637,11 +2637,19 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp, /* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */ as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC; as_sdp->length = 0x9; - as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; - as_sdp->vtotal = adjusted_mode->vtotal; - as_sdp->target_rr = 0; as_sdp->duration_incr_ms = 0; as_sdp->duration_incr_ms = 0; + + if (crtc_state->cmrr.enable) { + as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED; + as_sdp->vtotal = adjusted_mode->vtotal; + as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode); + as_sdp->target_rr_divider = true; + } else { + as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL; + as_sdp->vtotal = adjusted_mode->vtotal; + as_sdp->target_rr = 0; + } } static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, -- cgit From 5922f45329cd67e1c37c2c01513a59da82a65b96 Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Mon, 10 Jun 2024 12:52:01 +0530 Subject: drm/i915/display: Compute vrr vsync params Compute vrr vsync params in case of FAVT as well instead of only to AVT mode of operation. --v2: - Remove redundant computation for vrr_vsync_start and vrr_vsync_end(Ankit). --v3: - vrr.enable and cmrr.enable check together is not required as both will be true at the same point in time. (Ankit) - Replace vrr.enable flag to cmrr.enable, mistakenly added. (Ankit) Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-9-mitulkumar.ajitkumar.golani@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 19b364074de0..4ad99a54aa83 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -175,14 +175,15 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, if (crtc_state->uapi.vrr_enabled) { crtc_state->vrr.enable = true; crtc_state->mode_flags |= I915_MODE_FLAG_VRR; - if (intel_dp_as_sdp_supported(intel_dp)) { - crtc_state->vrr.vsync_start = - (crtc_state->hw.adjusted_mode.crtc_vtotal - - crtc_state->hw.adjusted_mode.vsync_start); - crtc_state->vrr.vsync_end = - (crtc_state->hw.adjusted_mode.crtc_vtotal - - crtc_state->hw.adjusted_mode.vsync_end); - } + } + + if (intel_dp_as_sdp_supported(intel_dp)) { + crtc_state->vrr.vsync_start = + (crtc_state->hw.adjusted_mode.crtc_vtotal - + crtc_state->hw.adjusted_mode.vsync_start); + crtc_state->vrr.vsync_end = + (crtc_state->hw.adjusted_mode.crtc_vtotal - + crtc_state->hw.adjusted_mode.vsync_end); } } -- cgit From 1676ecd303acca213852156fed0873c265d88512 Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Mon, 10 Jun 2024 12:52:02 +0530 Subject: drm/i915: Compute CMRR and calculate vtotal Compute Fixed Average Vtotal/CMRR with resepect to userspace VRR enablement. Also calculate required parameters in case of CMRR is enabled. During intel_vrr_compute_config, CMRR is getting enabled based on userspace has enabled Variable refresh mode with VRR timing generator or not. Make CMRR as small subset of FAVT mode, when Panel is running on Fixed refresh rate and on VRR framework then only enable CMRR to match with actual refresh rate. --v2: - Update is_cmrr_frac_required function return as bool, not int. [Jani] - Use signed int math instead of unsigned in cmrr_get_vtotal2. [Jani] - Fix typo and usage of camel case in cmrr_get_vtotal. [Jani] - Use do_div in cmrr_get_vtotalwhile calculating cmrr_m. [ Jani] - Simplify cmrr and vrr compute config in intel_vrr_compute_config. [Jani] - Correct valiable name usage in is_cmrr_frac_required. [Ville] --v3: - Removing RFC tag. --v4: - Added edp check to address edp usecase for now. (ville) - Updated is_cmrr_fraction_required to more simplified calculation. - on longterm goal to be worked upon uapi as suggestion from ville. --v5: - Correct vtotal paramas accuracy and add 2 digit precision. - Avoid using DIV_ROUND_UP and improve scanline precision. --v6: - Make CMRR a small subset of FAVT mode. --v7: - Update commit message to avoid confusion with Legacy VRR (Ankit). - Add cmrr.enable in last, so remove from this patch. --v8: - Set cmrr.enable in current patch instead of separate patch (Ankit). - Since vrr.enable and cmrr.enable are not mutually exclusive, handle accordingly (Ankit). - is_edp is not required inside is_cmrr_frac_required function (Ankit). - Add video_mode_required flag for future enhancement. - Correct cmrr_m/cmrr_n calculation. --v9: - Move patch to last and set other bits before computing cmrr.enable.(Ankit) - Add TODO: for to address target refresh rate precision as future enhancement. Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240610072203.24956-10-mitulkumar.ajitkumar.golani@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 1 + .../gpu/drm/i915/display/intel_display_device.h | 1 + drivers/gpu/drm/i915/display/intel_vrr.c | 92 +++++++++++++++++++--- 3 files changed, 83 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 33f5a3ef2e94..5a91f67a8c9f 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5475,6 +5475,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_I(vrr.vsync_end); PIPE_CONF_CHECK_LLI(cmrr.cmrr_m); PIPE_CONF_CHECK_LLI(cmrr.cmrr_n); + PIPE_CONF_CHECK_BOOL(cmrr.enable); } #undef PIPE_CONF_CHECK_X diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h index 44cda6c3e4d8..13453ea4daea 100644 --- a/drivers/gpu/drm/i915/display/intel_display_device.h +++ b/drivers/gpu/drm/i915/display/intel_display_device.h @@ -154,6 +154,7 @@ enum intel_display_subplatform { BIT(trans)) != 0) #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) #define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13) +#define HAS_CMRR(i915) (DISPLAY_VER(i915) >= 20) #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 4ad99a54aa83..05f67dc9d98d 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -12,6 +12,9 @@ #include "intel_vrr_regs.h" #include "intel_dp.h" +#define FIXED_POINT_PRECISION 100 +#define CMRR_PRECISION_TOLERANCE 10 + bool intel_vrr_is_capable(struct intel_connector *connector) { const struct drm_display_info *info = &connector->base.display_info; @@ -107,6 +110,52 @@ int intel_vrr_vmax_vblank_start(const struct intel_crtc_state *crtc_state) return crtc_state->vrr.vmax - intel_vrr_vblank_exit_length(crtc_state); } +static bool +is_cmrr_frac_required(struct intel_crtc_state *crtc_state) +{ + int calculated_refresh_k, actual_refresh_k, pixel_clock_per_line; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + if (!HAS_CMRR(i915)) + return false; + + actual_refresh_k = + drm_mode_vrefresh(adjusted_mode) * FIXED_POINT_PRECISION; + pixel_clock_per_line = + adjusted_mode->crtc_clock * 1000 / adjusted_mode->crtc_htotal; + calculated_refresh_k = + pixel_clock_per_line * FIXED_POINT_PRECISION / adjusted_mode->crtc_vtotal; + + if ((actual_refresh_k - calculated_refresh_k) < CMRR_PRECISION_TOLERANCE) + return false; + + return true; +} + +static unsigned int +cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) +{ + int multiplier_m = 1, multiplier_n = 1, vtotal, desired_refresh_rate; + long long adjusted_pixel_rate; + struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; + + desired_refresh_rate = drm_mode_vrefresh(adjusted_mode); + + if (video_mode_required) { + multiplier_m = 1001; + multiplier_n = 1000; + } + + crtc_state->cmrr.cmrr_n = + desired_refresh_rate * adjusted_mode->crtc_htotal * multiplier_n; + vtotal = (adjusted_mode->crtc_clock * 1000 * multiplier_n) / crtc_state->cmrr.cmrr_n; + adjusted_pixel_rate = adjusted_mode->crtc_clock * 1000 * multiplier_m; + crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); + + return vtotal; +} + void intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -116,6 +165,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, struct intel_connector *connector = to_intel_connector(conn_state->connector); struct intel_dp *intel_dp = intel_attached_dp(connector); + bool is_edp = intel_dp_is_edp(intel_dp); struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; const struct drm_display_info *info = &connector->base.display_info; int vmin, vmax; @@ -160,21 +210,26 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->vrr.flipline = crtc_state->vrr.vmin + 1; /* - * For XE_LPD+, we use guardband and pipeline override - * is deprecated. + * When panel is VRR capable and userspace has + * not enabled adaptive sync mode then Fixed Average + * Vtotal mode should be enabled. */ - if (DISPLAY_VER(i915) >= 13) { - crtc_state->vrr.guardband = - crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; - } else { - crtc_state->vrr.pipeline_full = - min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - - crtc_state->framestart_delay - 1); - } - if (crtc_state->uapi.vrr_enabled) { crtc_state->vrr.enable = true; crtc_state->mode_flags |= I915_MODE_FLAG_VRR; + } else if (is_cmrr_frac_required(crtc_state) && is_edp) { + crtc_state->vrr.enable = true; + crtc_state->cmrr.enable = true; + /* + * TODO: Compute precise target refresh rate to determine + * if video_mode_required should be true. Currently set to + * false due to uncertainty about the precise target + * refresh Rate. + */ + crtc_state->vrr.vmax = cmrr_get_vtotal(crtc_state, false); + crtc_state->vrr.vmin = crtc_state->vrr.vmax; + crtc_state->vrr.flipline = crtc_state->vrr.vmin; + crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } if (intel_dp_as_sdp_supported(intel_dp)) { @@ -185,6 +240,19 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, (crtc_state->hw.adjusted_mode.crtc_vtotal - crtc_state->hw.adjusted_mode.vsync_end); } + + /* + * For XE_LPD+, we use guardband and pipeline override + * is deprecated. + */ + if (DISPLAY_VER(i915) >= 13) { + crtc_state->vrr.guardband = + crtc_state->vrr.vmin + 1 - adjusted_mode->crtc_vblank_start; + } else { + crtc_state->vrr.pipeline_full = + min(255, crtc_state->vrr.vmin - adjusted_mode->crtc_vblank_start - + crtc_state->framestart_delay - 1); + } } static u32 trans_vrr_ctl(const struct intel_crtc_state *crtc_state) @@ -324,6 +392,8 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) TRANS_VRR_CTL(dev_priv, cpu_transcoder)); crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; + if (HAS_CMRR(dev_priv)) + crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); if (crtc_state->cmrr.enable) { crtc_state->cmrr.cmrr_n = -- cgit From 21925ee8e68fdb9e7b7d1898f34b5ad0b7c3f5c9 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:05 +0300 Subject: drm/i915/alpm: Do not use fast_wake_lines for aux less wake time MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We want to have own variables for fast wake lines and aux less wake time. It might be needed to choose if we can enable Panel Replay Selective Update or PSR2. Also currently aux less wake time is overwritten by calculated fast wake time. v2:use aux less wake time in intel_alpm_lobf_compute_config Fixes: da6a9836ac09 ("drm/i915/psr: Calculate aux less wake time") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-2-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_alpm.c | 4 ++-- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index a26716c14aa3..52a573367976 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -159,7 +159,7 @@ static int _lnl_compute_aux_less_alpm_params(struct intel_dp *intel_dp, if (i915->display.params.psr_safest_params) aux_less_wake_lines = ALPM_CTL_AUX_LESS_WAKE_TIME_MASK; - intel_dp->alpm_parameters.fast_wake_lines = aux_less_wake_lines; + intel_dp->alpm_parameters.aux_less_wake_lines = aux_less_wake_lines; intel_dp->alpm_parameters.silence_period_sym_clocks = silence_period; intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms = lfps_half_cycle; @@ -298,7 +298,7 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, if (intel_alpm_aux_less_wake_supported(intel_dp)) waketime_in_lines = intel_dp->alpm_parameters.io_wake_lines; else - waketime_in_lines = intel_dp->alpm_parameters.fast_wake_lines; + waketime_in_lines = intel_dp->alpm_parameters.aux_less_wake_lines; crtc_state->has_lobf = (context_latency + guardband) > (first_sdp_position + waketime_in_lines); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 098cabc15c7f..4ee760bd26f7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1854,6 +1854,7 @@ struct intel_dp { /* LNL and beyond */ u8 check_entry_lines; + u8 aux_less_wake_lines; u8 silence_period_sym_clocks; u8 lfps_half_cycle_num_of_syms; } alpm_parameters; -- cgit From 1fceeb85de3b76cfafa3c3649b56c864f04f49cd Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:06 +0300 Subject: drm/i915/alpm: Write also AUX Less Wake lines into ALPM_CTL MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently AUX Less Wake lines are not written into ALPM_CTL. Fix this. Fixes: 1ccbf135862b ("drm/i915/psr: Enable ALPM on source side for eDP Panel replay") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-3-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_alpm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 52a573367976..18c1c5803670 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -323,7 +323,8 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, (crtc_state->has_lobf && intel_alpm_aux_less_wake_supported(intel_dp))) { alpm_ctl = ALPM_CTL_ALPM_ENABLE | ALPM_CTL_ALPM_AUX_LESS_ENABLE | - ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS; + ALPM_CTL_AUX_LESS_SLEEP_HOLD_TIME_50_SYMBOLS | + ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines); intel_de_write(dev_priv, PORT_ALPM_CTL(dev_priv, cpu_transcoder), -- cgit From f36b4810f082d1d8c11362cde82b86390616a179 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:07 +0300 Subject: drm/i915/display: Take panel replay into account in vsc sdp unpacking MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently intel_dp_vsc_sdp_unpack is not taking into account Panel Replay vsc sdp. Fix this by adding vsc sdp revision 0x6 and length 0x10 into intel_dp_vsc_sdp_unpack Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-4-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b5915c23302f..653b20f9576c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4450,7 +4450,8 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, vsc->length = sdp->sdp_header.HB3; if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || - (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) { + (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe) || + (sdp->sdp_header.HB2 == 0x6 && sdp->sdp_header.HB3 == 0x10)) { /* * - HB2 = 0x2, HB3 = 0x8 * VSC SDP supporting 3D stereo + PSR @@ -4458,6 +4459,8 @@ static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of * first scan line of the SU region (applies to eDP v1.4b * and higher). + * - HB2 = 0x6, HB3 = 0x10 + * VSC SDP supporting 3D stereo + Panel Replay. */ return 0; } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { -- cgit From 955446ed6e822b86751993bd69022d347b43a99e Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:08 +0300 Subject: drm/i915/display: Skip Panel Replay on pipe comparison if no active planes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Panel Replay is not enabled if there are no active planes. Do not compare it on pipe comparison. Otherwise we get pipe mismatch. Fixes: ac9ef327327b ("drm/i915/psr: Panel replay has to be enabled before link training") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-5-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_display.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5a91f67a8c9f..5e0aa5a0b10c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5372,7 +5372,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, * Panel replay has to be enabled before link training. PSR doesn't have * this requirement -> check these only if using panel replay */ - if (current_config->has_panel_replay || pipe_config->has_panel_replay) { + if (current_config->active_planes && + (current_config->has_panel_replay || + pipe_config->has_panel_replay)) { PIPE_CONF_CHECK_BOOL(has_psr); PIPE_CONF_CHECK_BOOL(has_sel_update); PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch); -- cgit From 91930fc0394b3b54c6a8a3333b2b52c923cf6c52 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:09 +0300 Subject: drm/display: Add missing Panel Replay Enable SU Region ET bit MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing Panel Replay Enable SU Region ET bit defined in DP2.1 specification. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Acked-by: Maarten Lankhorst Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-6-jouni.hogander@intel.com --- include/drm/display/drm_dp.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index f246fa03a3cb..173548c6473a 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -743,6 +743,7 @@ # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) # define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) # define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) +# define DP_PANEL_REPLAY_ENABLE_SU_REGION_ET (1 << 7) /* DP 2.1 */ #define PANEL_REPLAY_CONFIG2 0x1b1 /* eDP 1.5 */ # define DP_PANEL_REPLAY_SINK_REFRESH_RATE_UNLOCK_GRANTED (1 << 0) -- cgit From 32f0045f905c3cc17e8c6ae81959b3db95bb0091 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:10 +0300 Subject: drm/i915/psr: Split enabling sink for PSR and Panel Replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Current intel_psr_enable_sink is a mess due to partly reusing PSR bit definitions for Panel Replay. Even thought PSR and Panel Replay enable registers do have common bits they still have also different bits and same bits with different meaning. For sake of clarity split enabling sink to PSR and Panel Replay specific parts. Also fix issue caused by using psr->panel_replay_enabled to early. Fixes: 88ae6c65ecdb ("drm/i915/psr: Unify panel replay enable/disable sink") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-7-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 81 +++++++++++++++++--------------- 1 file changed, 44 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 21f6a4fa86a4..320ea54df555 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -686,56 +686,62 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp) return false; } -static unsigned int intel_psr_get_enable_sink_offset(struct intel_dp *intel_dp) +static void _panel_replay_enable_sink(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { - return intel_dp->psr.panel_replay_enabled ? - PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG; + u8 val = DP_PANEL_REPLAY_ENABLE | + DP_PANEL_REPLAY_VSC_SDP_CRC_EN | + DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | + DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN | + DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN; + + if (crtc_state->has_sel_update) + val |= DP_PANEL_REPLAY_SU_ENABLE; + + if (crtc_state->enable_psr2_su_region_et) + val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; + + drm_dp_dpcd_writeb(&intel_dp->aux, PANEL_REPLAY_CONFIG, val); } -/* - * Note: Most of the bits are same in PANEL_REPLAY_CONFIG and DP_PSR_EN_CFG. We - * are relying on PSR definitions on these "common" bits. - */ -void intel_psr_enable_sink(struct intel_dp *intel_dp, - const struct intel_crtc_state *crtc_state) +static void _psr_enable_sink(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - u8 dpcd_val = DP_PSR_ENABLE; + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + u8 val = DP_PSR_ENABLE; if (crtc_state->has_sel_update) { - /* Enable ALPM at sink for psr2 */ - if (!crtc_state->has_panel_replay) { - drm_dp_dpcd_writeb(&intel_dp->aux, - DP_RECEIVER_ALPM_CONFIG, - DP_ALPM_ENABLE | - DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); - - if (crtc_state->enable_psr2_su_region_et) - dpcd_val |= DP_PSR_ENABLE_SU_REGION_ET; - } - - dpcd_val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; + val |= DP_PSR_ENABLE_PSR2 | DP_PSR_IRQ_HPD_WITH_CRC_ERRORS; } else { if (intel_dp->psr.link_standby) - dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; + val |= DP_PSR_MAIN_LINK_ACTIVE; - if (!crtc_state->has_panel_replay && DISPLAY_VER(dev_priv) >= 8) - dpcd_val |= DP_PSR_CRC_VERIFICATION; + if (DISPLAY_VER(i915) >= 8) + val |= DP_PSR_CRC_VERIFICATION; } - if (crtc_state->has_panel_replay) - dpcd_val |= DP_PANEL_REPLAY_UNRECOVERABLE_ERROR_EN | - DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN; - - if (crtc_state->req_psr2_sdp_prior_scanline) - dpcd_val |= DP_PSR_SU_REGION_SCANLINE_CAPTURE; + if (crtc_state->enable_psr2_su_region_et) + val |= DP_PANEL_REPLAY_ENABLE_SU_REGION_ET; if (intel_dp->psr.entry_setup_frames > 0) - dpcd_val |= DP_PSR_FRAME_CAPTURE; + val |= DP_PSR_FRAME_CAPTURE; - drm_dp_dpcd_writeb(&intel_dp->aux, - intel_psr_get_enable_sink_offset(intel_dp), - dpcd_val); + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); +} + +void intel_psr_enable_sink(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + /* Enable ALPM at sink for psr2 */ + if (!crtc_state->has_panel_replay && crtc_state->has_sel_update) + drm_dp_dpcd_writeb(&intel_dp->aux, + DP_RECEIVER_ALPM_CONFIG, + DP_ALPM_ENABLE | + DP_ALPM_LOCK_ERROR_IRQ_HPD_ENABLE); + + crtc_state->has_panel_replay ? + _panel_replay_enable_sink(intel_dp, crtc_state) : + _psr_enable_sink(intel_dp, crtc_state); if (intel_dp_is_edp(intel_dp)) drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); @@ -1921,7 +1927,8 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) /* Disable PSR on Sink */ drm_dp_dpcd_writeb(&intel_dp->aux, - intel_psr_get_enable_sink_offset(intel_dp), 0); + intel_dp->psr.panel_replay_enabled ? + PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG, 0); if (!intel_dp->psr.panel_replay_enabled && intel_dp->psr.sel_update_enabled) -- cgit From 92d03bdee41adaf5221b201fc7e67e8761888a71 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:11 +0300 Subject: drm/i915/alpm: Share alpm support checks with PSR code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert intel_alpm_aux_wake_supported and intel_alpm_aux_less_wake_supported as non-static. Use them in intel_psr.c instead of local variables. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-8-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_alpm.c | 4 ++-- drivers/gpu/drm/i915/display/intel_alpm.h | 2 ++ drivers/gpu/drm/i915/display/intel_psr.c | 14 ++------------ 3 files changed, 6 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 18c1c5803670..90072f6e3a33 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -11,12 +11,12 @@ #include "intel_dp_aux.h" #include "intel_psr_regs.h" -static bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp) +bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp) { return intel_dp->alpm_dpcd & DP_ALPM_CAP; } -static bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp) +bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp) { return intel_dp->alpm_dpcd & DP_ALPM_AUX_LESS_CAP; } diff --git a/drivers/gpu/drm/i915/display/intel_alpm.h b/drivers/gpu/drm/i915/display/intel_alpm.h index c82ecc7b4001..d4fb60393c91 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.h +++ b/drivers/gpu/drm/i915/display/intel_alpm.h @@ -22,4 +22,6 @@ void intel_alpm_lobf_compute_config(struct intel_dp *intel_dp, void intel_alpm_configure(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); void intel_alpm_lobf_debugfs_add(struct intel_connector *connector); +bool intel_alpm_aux_wake_supported(struct intel_dp *intel_dp); +bool intel_alpm_aux_less_wake_supported(struct intel_dp *intel_dp); #endif diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 320ea54df555..9e3081f9112e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -446,16 +446,6 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) } } -static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp) -{ - u8 alpm_caps = 0; - - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP, - &alpm_caps) != 1) - return false; - return alpm_caps & DP_ALPM_CAP; -} - static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -600,7 +590,6 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp) intel_dp->psr_dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) { bool y_req = intel_dp->psr_dpcd[1] & DP_PSR2_SU_Y_COORDINATE_REQUIRED; - bool alpm = intel_dp_get_alpm_status(intel_dp); /* * All panels that supports PSR version 03h (PSR2 + @@ -613,7 +602,8 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp) * Y-coordinate requirement panels we would need to enable * GTC first. */ - intel_dp->psr.sink_psr2_support = y_req && alpm; + intel_dp->psr.sink_psr2_support = y_req && + intel_alpm_aux_wake_supported(intel_dp); drm_dbg_kms(&i915->drm, "PSR2 %ssupported\n", intel_dp->psr.sink_psr2_support ? "" : "not "); } -- cgit From 672670b5dc6143601ca9cb457d82c8c98322d0f4 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:12 +0300 Subject: drm/i915/psr: Add Panel Replay support to intel_psr2_config_et_valid MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Early Transport is possible and in our HW mandatory on eDP Panel Replay. Add parameter to intel_psr2_config_et_valid to differentiate validity check for Panel Replay. v2: fix intel_dp->psr_dpcd[0] check Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-9-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 9e3081f9112e..a0b322dab025 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -664,16 +664,17 @@ static void hsw_psr_setup_aux(struct intel_dp *intel_dp) aux_ctl); } -static bool psr2_su_region_et_valid(struct intel_dp *intel_dp) +static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - if (DISPLAY_VER(i915) >= 20 && - intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED && - !(intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE)) - return true; + if (DISPLAY_VER(i915) < 20 || !intel_dp_is_edp(intel_dp) || + intel_dp->psr.debug & I915_PSR_DEBUG_SU_REGION_ET_DISABLE) + return false; - return false; + return panel_replay ? + intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : + intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; } static void _panel_replay_enable_sink(struct intel_dp *intel_dp, @@ -1351,7 +1352,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, tgl_dc3co_exitline_compute_config(intel_dp, crtc_state); - if (psr2_su_region_et_valid(intel_dp)) + if (psr2_su_region_et_valid(intel_dp, crtc_state->has_panel_replay)) crtc_state->enable_psr2_su_region_et = true; return true; -- cgit From 51ee1f29a9aceb8a52037ba4759d44c70e966fe5 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:13 +0300 Subject: drm/i915/psr: Print Panel Replay status instead of frame lock status MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently Panel Replay status printout is printing frame lock status. It should print Panel Replay status instead. Panel Replay status register field follows PSR status register field. Use existing PSR code for that. Fixes: ef75c25e8fed ("drm/i915/panelreplay: Debugfs support for panel replay") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-10-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index a0b322dab025..c3c576defc2b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3580,16 +3580,9 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data) "reserved", "sink internal error", }; - static const char * const panel_replay_status[] = { - "Sink device frame is locked to the Source device", - "Sink device is coasting, using the VTotal target", - "Sink device is governing the frame rate (frame rate unlock is granted)", - "Sink device in the process of re-locking with the Source device", - }; const char *str; int ret; u8 status, error_status; - u32 idx; if (!(CAN_PSR(intel_dp) || CAN_PANEL_REPLAY(intel_dp))) { seq_puts(m, "PSR/Panel-Replay Unsupported\n"); @@ -3603,16 +3596,11 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data) if (ret) return ret; - str = "unknown"; - if (intel_dp->psr.panel_replay_enabled) { - idx = (status & DP_SINK_FRAME_LOCKED_MASK) >> DP_SINK_FRAME_LOCKED_SHIFT; - if (idx < ARRAY_SIZE(panel_replay_status)) - str = panel_replay_status[idx]; - } else if (intel_dp->psr.enabled) { - idx = status & DP_PSR_SINK_STATE_MASK; - if (idx < ARRAY_SIZE(sink_status)) - str = sink_status[idx]; - } + status &= DP_PSR_SINK_STATE_MASK; + if (status < ARRAY_SIZE(sink_status)) + str = sink_status[status]; + else + str = "unknown"; seq_printf(m, "Sink %s status: 0x%x [%s]\n", psr_mode_str(intel_dp), status, str); -- cgit From 2e8938a1c56e60fcd6e52de254808615d0eccea4 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:14 +0300 Subject: drm/i915/psr: Move vblank length check to separate function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We are about to add more complexity to vblank length check. It makes sense to move it to separate function for sake of clarity. v2: change name to wake_lines_fit_into_vblank Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-11-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index c3c576defc2b..8f2b8b4620bd 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1243,6 +1243,20 @@ static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, return entry_setup_frames; } +static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, + const struct intel_crtc_state *crtc_state) +{ + int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - + crtc_state->hw.adjusted_mode.crtc_vblank_start; + int wake_lines = psr2_block_count_lines(intel_dp); + + /* Vblank >= PSR2_CTL Block Count Number maximum line count */ + if (vblank < wake_lines) + return false; + + return true; +} + static bool intel_psr2_config_valid(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state) { @@ -1333,9 +1347,7 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp, } /* Vblank >= PSR2_CTL Block Count Number maximum line count */ - if (crtc_state->hw.adjusted_mode.crtc_vblank_end - - crtc_state->hw.adjusted_mode.crtc_vblank_start < - psr2_block_count_lines(intel_dp)) { + if (!wake_lines_fit_into_vblank(intel_dp, crtc_state)) { drm_dbg_kms(&dev_priv->drm, "PSR2 not enabled, too short vblank time\n"); return false; -- cgit From aeafa46ee30c95dbad77db19b1400fb6fd78245f Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:15 +0300 Subject: drm/i915/psr: Take into account SU SDP scanline indication in vblank check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SU SDP scanline indication should be taken into account when checking vblank length. In Bspec we have: PSR2_CTL[ SU SDP scanline indication ] = 0: (TRANS_VBLANK Vertical Blank End- TRANS_VBLANK Vertical Blank Start) > PSR2_CTL Block Count Number value in lines PSR2_CTL[ SU SDP scanline indication ] = 1: (TRANS_VBLANK Vertical Blank End- TRANS_VBLANK Vertical Blank Start- 1) > PSR2_CTL Block Count Number value in lines Bspec: 49274 Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-12-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 8f2b8b4620bd..7ee03bf924c4 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1250,6 +1250,9 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, crtc_state->hw.adjusted_mode.crtc_vblank_start; int wake_lines = psr2_block_count_lines(intel_dp); + if (crtc_state->req_psr2_sdp_prior_scanline) + vblank -= 1; + /* Vblank >= PSR2_CTL Block Count Number maximum line count */ if (vblank < wake_lines) return false; -- cgit From 99fcf463903d5236e6e693230c142284a1e19164 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:16 +0300 Subject: drm/i915/psr: Check vblank against IO buffer wake time on Lunarlake MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As Lunarlake doesn't have block count configuration vblank should be checked against IO buffer wake time. Bspec: 68920 Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-13-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7ee03bf924c4..658216d50fdd 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1246,9 +1246,13 @@ static int intel_psr_entry_setup_frames(struct intel_dp *intel_dp, static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { + struct drm_i915_private *i915 = dp_to_i915(intel_dp); int vblank = crtc_state->hw.adjusted_mode.crtc_vblank_end - crtc_state->hw.adjusted_mode.crtc_vblank_start; - int wake_lines = psr2_block_count_lines(intel_dp); + int wake_lines; + + wake_lines = DISPLAY_VER(i915) < 20 ? psr2_block_count_lines(intel_dp) : + intel_dp->alpm_parameters.io_wake_lines; if (crtc_state->req_psr2_sdp_prior_scanline) vblank -= 1; -- cgit From ca8a170f73d93cca2be791162fcbf12941c47558 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Fri, 7 Jun 2024 16:49:17 +0300 Subject: drm/i915/psr: Wake time is aux less wake time for Panel Replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When checking vblank length used wake time is aux less wake time for eDP Panel Replay (vblank length is not checked for DP2.0 Panel Replay). Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240607134917.1327574-14-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 658216d50fdd..1cce9713a960 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1251,8 +1251,12 @@ static bool wake_lines_fit_into_vblank(struct intel_dp *intel_dp, crtc_state->hw.adjusted_mode.crtc_vblank_start; int wake_lines; - wake_lines = DISPLAY_VER(i915) < 20 ? psr2_block_count_lines(intel_dp) : - intel_dp->alpm_parameters.io_wake_lines; + if (crtc_state->has_panel_replay) + wake_lines = intel_dp->alpm_parameters.aux_less_wake_lines; + else + wake_lines = DISPLAY_VER(i915) < 20 ? + psr2_block_count_lines(intel_dp) : + intel_dp->alpm_parameters.io_wake_lines; if (crtc_state->req_psr2_sdp_prior_scanline) vblank -= 1; -- cgit From fb4943574f927b3140d9ce5aaabfb8730639096f Mon Sep 17 00:00:00 2001 From: Stanislav Lisovskiy Date: Fri, 7 Jun 2024 10:54:57 +0300 Subject: drm/i915: Rename all bigjoiner to joiner MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Lets unify both bigjoiner and ultrajoiner under simple "joiner" name, because in future we might have multiple configurations, involving multiple bigjoiners, ultrajoiner, however it is possible to use same api for handling both. v2: - Renamed back some bigjoiner specific parts for now(Ville) Signed-off-by: Stanislav Lisovskiy [vsyrjala: Catch a few more cases] Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240607075457.15700-1-stanislav.lisovskiy@intel.com --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 4 +- drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +- .../gpu/drm/i915/display/intel_crtc_state_dump.c | 8 +- drivers/gpu/drm/i915/display/intel_cursor.c | 4 +- drivers/gpu/drm/i915/display/intel_ddi.c | 4 +- drivers/gpu/drm/i915/display/intel_display.c | 232 ++++++++++----------- drivers/gpu/drm/i915/display/intel_display.h | 8 +- .../gpu/drm/i915/display/intel_display_debugfs.c | 6 +- drivers/gpu/drm/i915/display/intel_display_types.h | 6 +- drivers/gpu/drm/i915/display/intel_dp.c | 44 ++-- drivers/gpu/drm/i915/display/intel_dp.h | 8 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 28 +-- drivers/gpu/drm/i915/display/intel_drrs.c | 6 +- drivers/gpu/drm/i915/display/intel_modeset_setup.c | 42 ++-- drivers/gpu/drm/i915/display/intel_psr.c | 6 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 12 +- drivers/gpu/drm/i915/display/intel_vrr.c | 2 +- drivers/gpu/drm/i915/display/skl_universal_plane.c | 4 +- 18 files changed, 213 insertions(+), 213 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 980c5dc70763..8903bca2e6ab 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -336,7 +336,7 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, intel_plane_clear_hw_state(plane_state); /* - * For the bigjoiner slave uapi.crtc will point at + * For the joiner slave uapi.crtc will point at * the master crtc. So we explicitly assign the right * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates * the plane is logically enabled on the uapi level. @@ -721,7 +721,7 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - if (new_crtc_state && intel_crtc_is_bigjoiner_slave(new_crtc_state)) { + if (new_crtc_state && intel_crtc_is_joiner_slave(new_crtc_state)) { struct intel_crtc *master_crtc = intel_master_crtc(new_crtc_state); struct intel_plane *master_plane = diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 7ef8dcb1601a..c5bc49e48c88 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2732,7 +2732,7 @@ static int intel_vdsc_min_cdclk(const struct intel_crtc_state *crtc_state) min_cdclk = max_t(int, min_cdclk, DIV_ROUND_UP(crtc_state->pixel_rate, num_vdsc_instances)); - if (crtc_state->bigjoiner_pipes) { + if (crtc_state->joiner_pipes) { int pixel_clock = intel_dp_mode_to_fec_clock(crtc_state->hw.adjusted_mode.clock); /* diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index bddcc9edeab4..5d35c5537eaa 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -222,10 +222,10 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, transcoder_name(pipe_config->master_transcoder), pipe_config->sync_mode_slaves_mask); - drm_printf(&p, "bigjoiner: %s, pipes: 0x%x\n", - intel_crtc_is_bigjoiner_slave(pipe_config) ? "slave" : - intel_crtc_is_bigjoiner_master(pipe_config) ? "master" : "no", - pipe_config->bigjoiner_pipes); + drm_printf(&p, "joiner: %s, pipes: 0x%x\n", + intel_crtc_is_joiner_slave(pipe_config) ? "slave" : + intel_crtc_is_joiner_master(pipe_config) ? "master" : "no", + pipe_config->joiner_pipes); drm_printf(&p, "splitter: %s, link count %d, overlap %d\n", str_enabled_disabled(pipe_config->splitter.enable), diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index cea0cfed569d..7f7fc710350c 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -761,12 +761,12 @@ intel_legacy_cursor_update(struct drm_plane *_plane, * PSR2 plane and transcoder registers can only be updated during * vblank. * - * FIXME bigjoiner fastpath would be good + * FIXME joiner fastpath would be good */ if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state) || intel_crtc_needs_fastset(crtc_state) || - crtc_state->bigjoiner_pipes) + crtc_state->joiner_pipes) goto slow; /* diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index f306e0d2d418..eb265eac2ad7 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4277,10 +4277,10 @@ static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state { /* * FIXME the modeset sequence is currently wrong and - * can't deal with bigjoiner + port sync at the same time. + * can't deal with joiner + port sync at the same time. */ return crtc_state1->hw.active && crtc_state2->hw.active && - !crtc_state1->bigjoiner_pipes && !crtc_state2->bigjoiner_pipes && + !crtc_state1->joiner_pipes && !crtc_state2->joiner_pipes && crtc_state1->output_types == crtc_state2->output_types && crtc_state1->output_format == crtc_state2->output_format && crtc_state1->lane_count == crtc_state2->lane_count && diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 5e0aa5a0b10c..bea388d71b50 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -246,53 +246,53 @@ is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) is_trans_port_sync_slave(crtc_state); } -static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state) +static enum pipe joiner_master_pipe(const struct intel_crtc_state *crtc_state) { - return ffs(crtc_state->bigjoiner_pipes) - 1; + return ffs(crtc_state->joiner_pipes) - 1; } -u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state) +u8 intel_crtc_joiner_slave_pipes(const struct intel_crtc_state *crtc_state) { - if (crtc_state->bigjoiner_pipes) - return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state)); + if (crtc_state->joiner_pipes) + return crtc_state->joiner_pipes & ~BIT(joiner_master_pipe(crtc_state)); else return 0; } -bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state) +bool intel_crtc_is_joiner_slave(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - return crtc_state->bigjoiner_pipes && - crtc->pipe != bigjoiner_master_pipe(crtc_state); + return crtc_state->joiner_pipes && + crtc->pipe != joiner_master_pipe(crtc_state); } -bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state) +bool intel_crtc_is_joiner_master(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - return crtc_state->bigjoiner_pipes && - crtc->pipe == bigjoiner_master_pipe(crtc_state); + return crtc_state->joiner_pipes && + crtc->pipe == joiner_master_pipe(crtc_state); } -static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state) +static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state) { - return hweight8(crtc_state->bigjoiner_pipes); + return hweight8(crtc_state->joiner_pipes); } u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - return BIT(crtc->pipe) | crtc_state->bigjoiner_pipes; + return BIT(crtc->pipe) | crtc_state->joiner_pipes; } struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - if (intel_crtc_is_bigjoiner_slave(crtc_state)) - return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state)); + if (intel_crtc_is_joiner_slave(crtc_state)) + return intel_crtc_for_pipe(i915, joiner_master_pipe(crtc_state)); else return to_intel_crtc(crtc_state->uapi.crtc); } @@ -2328,10 +2328,10 @@ static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) ilk_pipe_pixel_rate(crtc_state); } -static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state, - struct drm_display_mode *mode) +static void intel_joiner_adjust_timings(const struct intel_crtc_state *crtc_state, + struct drm_display_mode *mode) { - int num_pipes = intel_bigjoiner_num_pipes(crtc_state); + int num_pipes = intel_joiner_num_pipes(crtc_state); if (num_pipes < 2) return; @@ -2395,11 +2395,11 @@ static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state drm_mode_copy(mode, pipe_mode); intel_mode_from_crtc_timings(mode, mode); mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) * - (intel_bigjoiner_num_pipes(crtc_state) ?: 1); + (intel_joiner_num_pipes(crtc_state) ?: 1); mode->vdisplay = drm_rect_height(&crtc_state->pipe_src); - /* Derive per-pipe timings in case bigjoiner is used */ - intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); + /* Derive per-pipe timings in case joiner is used */ + intel_joiner_adjust_timings(crtc_state, pipe_mode); intel_mode_from_crtc_timings(pipe_mode, pipe_mode); intel_crtc_compute_pixel_rate(crtc_state); @@ -2413,9 +2413,9 @@ void intel_encoder_get_config(struct intel_encoder *encoder, intel_crtc_readout_derived_state(crtc_state); } -static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state) +static void intel_joiner_compute_pipe_src(struct intel_crtc_state *crtc_state) { - int num_pipes = intel_bigjoiner_num_pipes(crtc_state); + int num_pipes = intel_joiner_num_pipes(crtc_state); int width, height; if (num_pipes < 2) @@ -2433,7 +2433,7 @@ static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - intel_bigjoiner_compute_pipe_src(crtc_state); + intel_joiner_compute_pipe_src(crtc_state); /* * Pipe horizontal size must be even in: @@ -2478,8 +2478,8 @@ static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state) /* Expand MSO per-segment transcoder timings to full */ intel_splitter_adjust_timings(crtc_state, pipe_mode); - /* Derive per-pipe timings in case bigjoiner is used */ - intel_bigjoiner_adjust_timings(crtc_state, pipe_mode); + /* Derive per-pipe timings in case joiner is used */ + intel_joiner_adjust_timings(crtc_state, pipe_mode); intel_mode_from_crtc_timings(pipe_mode, pipe_mode); if (DISPLAY_VER(i915) < 4) { @@ -2872,17 +2872,17 @@ static void intel_get_transcoder_timings(struct intel_crtc *crtc, TRANS_SET_CONTEXT_LATENCY(dev_priv, cpu_transcoder)); } -static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) +static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - int num_pipes = intel_bigjoiner_num_pipes(crtc_state); + int num_pipes = intel_joiner_num_pipes(crtc_state); enum pipe master_pipe, pipe = crtc->pipe; int width; if (num_pipes < 2) return; - master_pipe = bigjoiner_master_pipe(crtc_state); + master_pipe = joiner_master_pipe(crtc_state); width = drm_rect_width(&crtc_state->pipe_src); drm_rect_translate_to(&crtc_state->pipe_src, @@ -2902,7 +2902,7 @@ static void intel_get_pipe_src_size(struct intel_crtc *crtc, REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1, REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1); - intel_bigjoiner_adjust_pipe_src(pipe_config); + intel_joiner_adjust_pipe_src(pipe_config); } void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) @@ -3492,7 +3492,7 @@ out: return ret; } -static u8 bigjoiner_pipes(struct drm_i915_private *i915) +static u8 joiner_pipes(struct drm_i915_private *i915) { u8 pipes; @@ -3522,8 +3522,8 @@ static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, return tmp & TRANS_DDI_FUNC_ENABLE; } -static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, - u8 *master_pipes, u8 *slave_pipes) +static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, + u8 *master_pipes, u8 *slave_pipes) { struct intel_crtc *crtc; @@ -3531,7 +3531,7 @@ static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, *slave_pipes = 0; for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, - bigjoiner_pipes(dev_priv)) { + joiner_pipes(dev_priv)) { enum intel_display_power_domain power_domain; enum pipe pipe = crtc->pipe; intel_wakeref_t wakeref; @@ -3563,13 +3563,13 @@ static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv, } } - /* Bigjoiner pipes should always be consecutive master and slave */ + /* Joiner pipes should always be consecutive master and slave */ drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, - "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", + "Joiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", *master_pipes, *slave_pipes); } -static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) +static enum pipe get_joiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) { if ((slave_pipes & BIT(pipe)) == 0) return pipe; @@ -3581,11 +3581,11 @@ static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 s return fls(master_pipes) - 1; } -static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) +static u8 get_joiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) { enum pipe master_pipe, next_master_pipe; - master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes); + master_pipe = get_joiner_master_pipe(pipe, master_pipes, slave_pipes); if ((master_pipes & BIT(master_pipe)) == 0) return 0; @@ -3663,16 +3663,16 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) enabled_transcoders |= BIT(cpu_transcoder); } - /* single pipe or bigjoiner master */ + /* single pipe or joiner master */ cpu_transcoder = (enum transcoder) crtc->pipe; if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) enabled_transcoders |= BIT(cpu_transcoder); - /* bigjoiner slave -> consider the master pipe's transcoder as well */ - enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes); + /* joiner slave -> consider the master pipe's transcoder as well */ + enabled_joiner_pipes(dev_priv, &master_pipes, &slave_pipes); if (slave_pipes & BIT(crtc->pipe)) { cpu_transcoder = (enum transcoder) - get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); + get_joiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) enabled_transcoders |= BIT(cpu_transcoder); } @@ -3799,21 +3799,21 @@ static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, return transcoder_is_dsi(pipe_config->cpu_transcoder); } -static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state) +static void intel_joiner_get_config(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); u8 master_pipes, slave_pipes; enum pipe pipe = crtc->pipe; - enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes); + enabled_joiner_pipes(i915, &master_pipes, &slave_pipes); if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) return; - crtc_state->bigjoiner_pipes = - BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) | - get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes); + crtc_state->joiner_pipes = + BIT(get_joiner_master_pipe(pipe, master_pipes, slave_pipes)) | + get_joiner_slave_pipes(pipe, master_pipes, slave_pipes); } static bool hsw_get_pipe_config(struct intel_crtc *crtc, @@ -3840,7 +3840,7 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc, if (!active) goto out; - intel_bigjoiner_get_config(pipe_config); + intel_joiner_get_config(pipe_config); intel_dsc_get_config(pipe_config); if (!transcoder_is_dsi(pipe_config->cpu_transcoder) || @@ -4480,7 +4480,7 @@ intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); + WARN_ON(intel_crtc_is_joiner_slave(crtc_state)); drm_property_replace_blob(&crtc_state->hw.degamma_lut, crtc_state->uapi.degamma_lut); @@ -4497,7 +4497,7 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); + WARN_ON(intel_crtc_is_joiner_slave(crtc_state)); crtc_state->hw.enable = crtc_state->uapi.enable; crtc_state->hw.active = crtc_state->uapi.active; @@ -4511,8 +4511,8 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, } static void -copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, - struct intel_crtc *slave_crtc) +copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state, + struct intel_crtc *slave_crtc) { struct intel_crtc_state *slave_crtc_state = intel_atomic_get_new_crtc_state(state, slave_crtc); @@ -4531,8 +4531,8 @@ copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state, } static int -copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, - struct intel_crtc *slave_crtc) +copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, + struct intel_crtc *slave_crtc) { struct intel_crtc_state *slave_crtc_state = intel_atomic_get_new_crtc_state(state, slave_crtc); @@ -4541,8 +4541,8 @@ copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, intel_atomic_get_new_crtc_state(state, master_crtc); struct intel_crtc_state *saved_state; - WARN_ON(master_crtc_state->bigjoiner_pipes != - slave_crtc_state->bigjoiner_pipes); + WARN_ON(master_crtc_state->joiner_pipes != + slave_crtc_state->joiner_pipes); saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); if (!saved_state) @@ -4576,14 +4576,14 @@ copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state, drm_dp_tunnel_ref_get(master_crtc_state->dp_tunnel_ref.tunnel, &slave_crtc_state->dp_tunnel_ref); - copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc); + copy_joiner_crtc_state_nomodeset(state, slave_crtc); slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; - WARN_ON(master_crtc_state->bigjoiner_pipes != - slave_crtc_state->bigjoiner_pipes); + WARN_ON(master_crtc_state->joiner_pipes != + slave_crtc_state->joiner_pipes); return 0; } @@ -5425,7 +5425,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_X(sync_mode_slaves_mask); PIPE_CONF_CHECK_I(master_transcoder); - PIPE_CONF_CHECK_X(bigjoiner_pipes); + PIPE_CONF_CHECK_X(joiner_pipes); PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable); PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb); @@ -5793,9 +5793,9 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv) IS_IVYBRIDGE(dev_priv); } -static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, - struct intel_crtc *crtc, - struct intel_crtc *other) +static int intel_crtc_add_joiner_planes(struct intel_atomic_state *state, + struct intel_crtc *crtc, + struct intel_crtc *other) { const struct intel_plane_state __maybe_unused *plane_state; struct intel_plane *plane; @@ -5810,7 +5810,7 @@ static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state, return intel_crtc_add_planes_to_state(state, other, plane_ids); } -static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) +static int intel_joiner_add_affected_planes(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_crtc_state *crtc_state; @@ -5821,13 +5821,13 @@ static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state) struct intel_crtc *other; for_each_intel_crtc_in_pipe_mask(&i915->drm, other, - crtc_state->bigjoiner_pipes) { + crtc_state->joiner_pipes) { int ret; if (crtc == other) continue; - ret = intel_crtc_add_bigjoiner_planes(state, crtc, other); + ret = intel_crtc_add_joiner_planes(state, crtc, other); if (ret) return ret; } @@ -5849,7 +5849,7 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state) if (ret) return ret; - ret = intel_bigjoiner_add_affected_planes(state); + ret = intel_joiner_add_affected_planes(state); if (ret) return ret; @@ -5949,33 +5949,33 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state, return false; } -static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, - struct intel_crtc *master_crtc) +static int intel_atomic_check_joiner(struct intel_atomic_state *state, + struct intel_crtc *master_crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_crtc_state *master_crtc_state = intel_atomic_get_new_crtc_state(state, master_crtc); struct intel_crtc *slave_crtc; - if (!master_crtc_state->bigjoiner_pipes) + if (!master_crtc_state->joiner_pipes) return 0; /* sanity check */ if (drm_WARN_ON(&i915->drm, - master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state))) + master_crtc->pipe != joiner_master_pipe(master_crtc_state))) return -EINVAL; - if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) { + if (master_crtc_state->joiner_pipes & ~joiner_pipes(i915)) { drm_dbg_kms(&i915->drm, - "[CRTC:%d:%s] Cannot act as big joiner master " + "[CRTC:%d:%s] Cannot act as joiner master " "(need 0x%x as pipes, only 0x%x possible)\n", master_crtc->base.base.id, master_crtc->base.name, - master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915)); + master_crtc_state->joiner_pipes, joiner_pipes(i915)); return -EINVAL; } for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, - intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { + intel_crtc_joiner_slave_pipes(master_crtc_state)) { struct intel_crtc_state *slave_crtc_state; int ret; @@ -5987,7 +5987,7 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, if (slave_crtc_state->uapi.enable) { drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " - "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n", + "[CRTC:%d:%s] claiming this CRTC for joiner.\n", slave_crtc->base.base.id, slave_crtc->base.name, master_crtc->base.base.id, master_crtc->base.name); return -EINVAL; @@ -6005,14 +6005,14 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, return -EINVAL; drm_dbg_kms(&i915->drm, - "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n", + "[CRTC:%d:%s] Used as slave for joiner master [CRTC:%d:%s]\n", slave_crtc->base.base.id, slave_crtc->base.name, master_crtc->base.base.id, master_crtc->base.name); - slave_crtc_state->bigjoiner_pipes = - master_crtc_state->bigjoiner_pipes; + slave_crtc_state->joiner_pipes = + master_crtc_state->joiner_pipes; - ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc); + ret = copy_joiner_crtc_state_modeset(state, slave_crtc); if (ret) return ret; } @@ -6020,8 +6020,8 @@ static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state, return 0; } -static void kill_bigjoiner_slave(struct intel_atomic_state *state, - struct intel_crtc *master_crtc) +static void kill_joiner_slave(struct intel_atomic_state *state, + struct intel_crtc *master_crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_crtc_state *master_crtc_state = @@ -6029,16 +6029,16 @@ static void kill_bigjoiner_slave(struct intel_atomic_state *state, struct intel_crtc *slave_crtc; for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, - intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) { + intel_crtc_joiner_slave_pipes(master_crtc_state)) { struct intel_crtc_state *slave_crtc_state = intel_atomic_get_new_crtc_state(state, slave_crtc); - slave_crtc_state->bigjoiner_pipes = 0; + slave_crtc_state->joiner_pipes = 0; intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); } - master_crtc_state->bigjoiner_pipes = 0; + master_crtc_state->joiner_pipes = 0; } /** @@ -6088,12 +6088,12 @@ static int intel_async_flip_check_uapi(struct intel_atomic_state *state, } /* - * FIXME: Bigjoiner+async flip is busted currently. + * FIXME: joiner+async flip is busted currently. * Remove this check once the issues are fixed. */ - if (new_crtc_state->bigjoiner_pipes) { + if (new_crtc_state->joiner_pipes) { drm_dbg_kms(&i915->drm, - "[CRTC:%d:%s] async flip disallowed with bigjoiner\n", + "[CRTC:%d:%s] async flip disallowed with joiner\n", crtc->base.base.id, crtc->base.name); return -EINVAL; } @@ -6318,7 +6318,7 @@ static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct in return 0; } -static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) +static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state) { struct drm_i915_private *i915 = to_i915(state->base.dev); struct intel_crtc_state *crtc_state; @@ -6328,9 +6328,9 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) int i; for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - affected_pipes |= crtc_state->bigjoiner_pipes; + affected_pipes |= crtc_state->joiner_pipes; if (intel_crtc_needs_modeset(crtc_state)) - modeset_pipes |= crtc_state->bigjoiner_pipes; + modeset_pipes |= crtc_state->joiner_pipes; } for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) { @@ -6356,10 +6356,10 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state) } for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { - /* Kill old bigjoiner link, we may re-establish afterwards */ + /* Kill old joiner link, we may re-establish afterwards */ if (intel_crtc_needs_modeset(crtc_state) && - intel_crtc_is_bigjoiner_master(crtc_state)) - kill_bigjoiner_slave(state, crtc); + intel_crtc_is_joiner_master(crtc_state)) + kill_joiner_slave(state, crtc); } return 0; @@ -6377,7 +6377,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state, *failed_pipe = INVALID_PIPE; - ret = intel_bigjoiner_add_affected_crtcs(state); + ret = intel_joiner_add_affected_crtcs(state); if (ret) return ret; @@ -6387,14 +6387,14 @@ static int intel_atomic_check_config(struct intel_atomic_state *state, for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { if (!intel_crtc_needs_modeset(new_crtc_state)) { - if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) - copy_bigjoiner_crtc_state_nomodeset(state, crtc); + if (intel_crtc_is_joiner_slave(new_crtc_state)) + copy_joiner_crtc_state_nomodeset(state, crtc); else intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); continue; } - if (drm_WARN_ON(&i915->drm, intel_crtc_is_bigjoiner_slave(new_crtc_state))) + if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_slave(new_crtc_state))) continue; ret = intel_crtc_prepare_cleared_state(state, crtc); @@ -6413,7 +6413,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state, if (!intel_crtc_needs_modeset(new_crtc_state)) continue; - if (drm_WARN_ON(&i915->drm, intel_crtc_is_bigjoiner_slave(new_crtc_state))) + if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_slave(new_crtc_state))) continue; if (!new_crtc_state->hw.enable) @@ -6524,12 +6524,12 @@ int intel_atomic_check(struct drm_device *dev, if (!intel_crtc_needs_modeset(new_crtc_state)) continue; - if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) { + if (intel_crtc_is_joiner_slave(new_crtc_state)) { drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); continue; } - ret = intel_atomic_check_bigjoiner(state, crtc); + ret = intel_atomic_check_joiner(state, crtc); if (ret) goto fail; } @@ -6539,7 +6539,7 @@ int intel_atomic_check(struct drm_device *dev, if (!intel_crtc_needs_modeset(new_crtc_state)) continue; - intel_bigjoiner_adjust_pipe_src(new_crtc_state); + intel_joiner_adjust_pipe_src(new_crtc_state); intel_crtc_check_fastset(old_crtc_state, new_crtc_state); } @@ -6579,8 +6579,8 @@ int intel_atomic_check(struct drm_device *dev, intel_crtc_flag_modeset(new_crtc_state); } - if (new_crtc_state->bigjoiner_pipes) { - if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) + if (new_crtc_state->joiner_pipes) { + if (intel_pipes_need_modeset(state, new_crtc_state->joiner_pipes)) intel_crtc_flag_modeset(new_crtc_state); } } @@ -6995,7 +6995,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) if ((disable_pipes & BIT(crtc->pipe)) == 0) continue; - if (intel_crtc_is_bigjoiner_slave(old_crtc_state)) + if (intel_crtc_is_joiner_slave(old_crtc_state)) continue; /* In case of Transcoder port Sync master slave CRTCs can be @@ -7017,7 +7017,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) if ((disable_pipes & BIT(crtc->pipe)) == 0) continue; - if (intel_crtc_is_bigjoiner_slave(old_crtc_state)) + if (intel_crtc_is_joiner_slave(old_crtc_state)) continue; intel_old_crtc_state_disables(state, crtc); @@ -7096,7 +7096,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) while (update_pipes) { /* - * Commit in reverse order to make bigjoiner master + * Commit in reverse order to make joiner master * send the uapi events after slaves are done. */ for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state, @@ -7142,7 +7142,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((modeset_pipes & BIT(pipe)) == 0) continue; - if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) + if (intel_crtc_is_joiner_slave(new_crtc_state)) continue; if (intel_dp_mst_is_slave_trans(new_crtc_state) || @@ -7156,7 +7156,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) /* * Then we enable all remaining pipes that depend on other - * pipes: MST slaves and port sync masters, big joiner master + * pipes: MST slaves and port sync masters */ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { enum pipe pipe = crtc->pipe; @@ -7164,7 +7164,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((modeset_pipes & BIT(pipe)) == 0) continue; - if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) + if (intel_crtc_is_joiner_slave(new_crtc_state)) continue; modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); @@ -7185,7 +7185,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) } /* - * Commit in reverse order to make bigjoiner master + * Commit in reverse order to make joiner master * send the uapi events after slaves are done. */ for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) { @@ -7913,7 +7913,7 @@ static int max_dotclock(struct drm_i915_private *i915) { int max_dotclock = i915->display.cdclk.max_dotclk_freq; - /* icl+ might use bigjoiner */ + /* icl+ might use joiner */ if (DISPLAY_VER(i915) >= 11) max_dotclock *= 2; @@ -8038,7 +8038,7 @@ enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *de enum drm_mode_status intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, const struct drm_display_mode *mode, - bool bigjoiner) + bool joiner) { int plane_width_max, plane_height_max; @@ -8055,7 +8055,7 @@ intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, * too big for that. */ if (DISPLAY_VER(dev_priv) >= 11) { - plane_width_max = 5120 << bigjoiner; + plane_width_max = 5120 << joiner; plane_height_max = 4320; } else { plane_width_max = 5120; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 56d1c0e3e62c..a2ec5309113e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -415,7 +415,7 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv, enum drm_mode_status intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv, const struct drm_display_mode *mode, - bool bigjoiner); + bool joiner); enum drm_mode_status intel_cpu_transcoder_mode_valid(struct drm_i915_private *i915, const struct drm_display_mode *mode); @@ -423,9 +423,9 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); bool is_trans_port_sync_mode(const struct intel_crtc_state *state); bool is_trans_port_sync_master(const struct intel_crtc_state *state); u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state); -bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state); -bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state); -u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state); +bool intel_crtc_is_joiner_slave(const struct intel_crtc_state *crtc_state); +bool intel_crtc_is_joiner_master(const struct intel_crtc_state *crtc_state); +u8 intel_crtc_joiner_slave_pipes(const struct intel_crtc_state *crtc_state); struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state); bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index b538a8204124..7090f6dccd6c 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -575,10 +575,10 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) intel_scaler_info(m, crtc); - if (crtc_state->bigjoiner_pipes) + if (crtc_state->joiner_pipes) seq_printf(m, "\tLinked to 0x%x pipes as a %s\n", - crtc_state->bigjoiner_pipes, - intel_crtc_is_bigjoiner_slave(crtc_state) ? "slave" : "master"); + crtc_state->joiner_pipes, + intel_crtc_is_joiner_slave(crtc_state) ? "slave" : "master"); for_each_intel_encoder_mask(&dev_priv->drm, encoder, crtc_state->uapi.encoder_mask) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4ee760bd26f7..4fa785fd664e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1048,7 +1048,7 @@ struct intel_crtc_state { * * During initial hw readout, they need to be copied to uapi. * - * Bigjoiner will allow a transcoder mode that spans 2 pipes; + * Joiner will allow a transcoder mode that spans 2 pipes; * Use the pipe_mode for calculations like watermarks, pipe * scaler, and bandwidth. * @@ -1344,8 +1344,8 @@ struct intel_crtc_state { /* enable vlv/chv wgc csc? */ bool wgc_enable; - /* big joiner pipe bitmask */ - u8 bigjoiner_pipes; + /* joiner pipe bitmask */ + u8 joiner_pipes; /* Display Stream compression state */ struct { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 653b20f9576c..b56752873a68 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -437,7 +437,7 @@ int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, return max_rate; } -bool intel_dp_has_bigjoiner(struct intel_dp *intel_dp) +bool intel_dp_has_joiner(struct intel_dp *intel_dp) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &intel_dig_port->base; @@ -1208,13 +1208,13 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, return MODE_OK; } -bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, - struct intel_connector *connector, - int hdisplay, int clock) +bool intel_dp_need_joiner(struct intel_dp *intel_dp, + struct intel_connector *connector, + int hdisplay, int clock) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - if (!intel_dp_has_bigjoiner(intel_dp)) + if (!intel_dp_has_joiner(intel_dp)) return false; return clock > i915->display.cdclk.max_dotclk_freq || hdisplay > 5120 || @@ -1235,7 +1235,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, u16 dsc_max_compressed_bpp = 0; u8 dsc_slice_count = 0; enum drm_mode_status status; - bool dsc = false, bigjoiner = false; + bool dsc = false, joiner = false; status = intel_cpu_transcoder_mode_valid(dev_priv, mode); if (status != MODE_OK) @@ -1256,9 +1256,9 @@ intel_dp_mode_valid(struct drm_connector *_connector, target_clock = fixed_mode->clock; } - if (intel_dp_need_bigjoiner(intel_dp, connector, - mode->hdisplay, target_clock)) { - bigjoiner = true; + if (intel_dp_need_joiner(intel_dp, connector, + mode->hdisplay, target_clock)) { + joiner = true; max_dotclk *= 2; } if (target_clock > max_dotclk) @@ -1305,20 +1305,20 @@ intel_dp_mode_valid(struct drm_connector *_connector, max_lanes, target_clock, mode->hdisplay, - bigjoiner, + joiner, output_format, pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(connector, target_clock, mode->hdisplay, - bigjoiner); + joiner); } dsc = dsc_max_compressed_bpp && dsc_slice_count; } - if (intel_dp_joiner_needs_dsc(dev_priv, bigjoiner) && !dsc) + if (intel_dp_joiner_needs_dsc(dev_priv, joiner) && !dsc) return MODE_CLOCK_HIGH; if (mode_rate > max_rate && !dsc) @@ -1328,7 +1328,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (status != MODE_OK) return status; - return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner); + return intel_mode_valid_max_plane_size(dev_priv, mode, joiner); } bool intel_dp_source_supports_tps3(struct drm_i915_private *i915) @@ -2019,7 +2019,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock, adjusted_mode->hdisplay, - pipe_config->bigjoiner_pipes); + pipe_config->joiner_pipes); dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp); dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16)); @@ -2253,7 +2253,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, intel_dp_dsc_get_slice_count(connector, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, - pipe_config->bigjoiner_pipes); + pipe_config->joiner_pipes); if (!dsc_dp_slice_count) { drm_dbg_kms(&dev_priv->drm, "Compressed Slice Count not supported\n"); @@ -2267,7 +2267,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * is greater than the maximum Cdclock and if slice count is even * then we need to use 2 VDSC instances. */ - if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1) + if (pipe_config->joiner_pipes || pipe_config->dsc.slice_count > 1) pipe_config->dsc.dsc_split = true; ret = intel_dp_dsc_compute_params(connector, pipe_config); @@ -2433,12 +2433,12 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, !intel_dp_supports_fec(intel_dp, connector, pipe_config)) return -EINVAL; - if (intel_dp_need_bigjoiner(intel_dp, connector, - adjusted_mode->crtc_hdisplay, - adjusted_mode->crtc_clock)) - pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); + if (intel_dp_need_joiner(intel_dp, connector, + adjusted_mode->crtc_hdisplay, + adjusted_mode->crtc_clock)) + pipe_config->joiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); - joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, pipe_config->bigjoiner_pipes); + joiner_needs_dsc = intel_dp_joiner_needs_dsc(i915, pipe_config->joiner_pipes); dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || !intel_dp_compute_config_limits(intel_dp, pipe_config, @@ -2766,7 +2766,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, * FIXME all joined pipes share the same transcoder. * Need to account for that when updating M/N live. */ - if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes) + if (has_seamless_m_n(connector) && !pipe_config->joiner_pipes) pipe_config->update_m_n = true; if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index aad2223df2a3..f14506a63aa0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -121,7 +121,7 @@ int intel_dp_effective_data_rate(int pixel_clock, int bpp_x16, int intel_dp_max_link_data_rate(struct intel_dp *intel_dp, int max_dprx_rate, int max_dprx_lanes); bool intel_dp_joiner_needs_dsc(struct drm_i915_private *i915, bool use_joiner); -bool intel_dp_has_bigjoiner(struct intel_dp *intel_dp); +bool intel_dp_has_joiner(struct intel_dp *intel_dp); bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable, @@ -150,9 +150,9 @@ int intel_dp_dsc_sink_max_compressed_bpp(const struct intel_connector *connector u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, bool bigjoiner); -bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, - struct intel_connector *connector, - int hdisplay, int clock); +bool intel_dp_need_joiner(struct intel_dp *intel_dp, + struct intel_connector *connector, + int hdisplay, int clock); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index aa633844f849..c3c889a5b7ee 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -105,7 +105,7 @@ static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state, dsc_slice_count = intel_dp_dsc_get_slice_count(connector, adjusted_mode->clock, adjusted_mode->hdisplay, - crtc_state->bigjoiner_pipes); + crtc_state->joiner_pipes); } overhead = drm_dp_bw_overhead(crtc_state->lane_count, @@ -567,16 +567,16 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) return -EINVAL; - if (intel_dp_need_bigjoiner(intel_dp, connector, - adjusted_mode->crtc_hdisplay, - adjusted_mode->crtc_clock)) - pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); + if (intel_dp_need_joiner(intel_dp, connector, + adjusted_mode->crtc_hdisplay, + adjusted_mode->crtc_clock)) + pipe_config->joiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe); pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; pipe_config->has_pch_encoder = false; - joiner_needs_dsc = intel_dp_joiner_needs_dsc(dev_priv, pipe_config->bigjoiner_pipes); + joiner_needs_dsc = intel_dp_joiner_needs_dsc(dev_priv, pipe_config->joiner_pipes); dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en || !intel_dp_mst_compute_config_limits(intel_dp, @@ -1376,7 +1376,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; int ret; - bool dsc = false, bigjoiner = false; + bool dsc = false, joiner = false; u16 dsc_max_compressed_bpp = 0; u8 dsc_slice_count = 0; int target_clock = mode->clock; @@ -1419,9 +1419,9 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, * corresponding link capabilities of the sink) in case the * stream is uncompressed for it by the last branch device. */ - if (intel_dp_need_bigjoiner(intel_dp, intel_connector, - mode->hdisplay, target_clock)) { - bigjoiner = true; + if (intel_dp_need_joiner(intel_dp, intel_connector, + mode->hdisplay, target_clock)) { + joiner = true; max_dotclk *= 2; } @@ -1450,20 +1450,20 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, max_lanes, target_clock, mode->hdisplay, - bigjoiner, + joiner, INTEL_OUTPUT_FORMAT_RGB, pipe_bpp, 64); dsc_slice_count = intel_dp_dsc_get_slice_count(intel_connector, target_clock, mode->hdisplay, - bigjoiner); + joiner); } dsc = dsc_max_compressed_bpp && dsc_slice_count; } - if (intel_dp_joiner_needs_dsc(dev_priv, bigjoiner) && !dsc) { + if (intel_dp_joiner_needs_dsc(dev_priv, joiner) && !dsc) { *status = MODE_CLOCK_HIGH; return 0; } @@ -1473,7 +1473,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, return 0; } - *status = intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner); + *status = intel_mode_valid_max_plane_size(dev_priv, mode, joiner); return 0; } diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c index 5250622f1479..8af5ee434782 100644 --- a/drivers/gpu/drm/i915/display/intel_drrs.c +++ b/drivers/gpu/drm/i915/display/intel_drrs.c @@ -135,7 +135,7 @@ static unsigned int intel_drrs_frontbuffer_bits(const struct intel_crtc_state *c frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, - crtc_state->bigjoiner_pipes) + crtc_state->joiner_pipes) frontbuffer_bits |= INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); return frontbuffer_bits; @@ -157,7 +157,7 @@ void intel_drrs_activate(const struct intel_crtc_state *crtc_state) if (!crtc_state->hw.active) return; - if (intel_crtc_is_bigjoiner_slave(crtc_state)) + if (intel_crtc_is_joiner_slave(crtc_state)) return; mutex_lock(&crtc->drrs.mutex); @@ -189,7 +189,7 @@ void intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->hw.active) return; - if (intel_crtc_is_bigjoiner_slave(old_crtc_state)) + if (intel_crtc_is_joiner_slave(old_crtc_state)) return; mutex_lock(&crtc->drrs.mutex); diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index caeca3a8442c..066252c45e12 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -68,7 +68,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, /* Everything's already locked, -EDEADLK can't happen. */ for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, BIT(pipe) | - intel_crtc_bigjoiner_slave_pipes(crtc_state)) { + intel_crtc_joiner_slave_pipes(crtc_state)) { struct intel_crtc_state *temp_crtc_state = intel_atomic_get_crtc_state(state, temp_crtc); int ret; @@ -189,7 +189,7 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc) /* * Return all the pipes using a transcoder in @transcoder_mask. - * For bigjoiner configs return only the bigjoiner master. + * For joiner configs return only the joiner master. */ static u8 get_transcoder_pipes(struct drm_i915_private *i915, u8 transcoder_mask) @@ -204,7 +204,7 @@ static u8 get_transcoder_pipes(struct drm_i915_private *i915, if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER) continue; - if (intel_crtc_is_bigjoiner_slave(temp_crtc_state)) + if (intel_crtc_is_joiner_slave(temp_crtc_state)) continue; if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder)) @@ -216,7 +216,7 @@ static u8 get_transcoder_pipes(struct drm_i915_private *i915, /* * Return the port sync master and slave pipes linked to @crtc. - * For bigjoiner configs return only the bigjoiner master pipes. + * For joiner configs return only the joiner master pipes. */ static void get_portsync_pipes(struct intel_crtc *crtc, u8 *master_pipe_mask, u8 *slave_pipes_mask) @@ -248,7 +248,7 @@ static void get_portsync_pipes(struct intel_crtc *crtc, *slave_pipes_mask = get_transcoder_pipes(i915, master_crtc_state->sync_mode_slaves_mask); } -static u8 get_bigjoiner_slave_pipes(struct drm_i915_private *i915, u8 master_pipes_mask) +static u8 get_joiner_slave_pipes(struct drm_i915_private *i915, u8 master_pipes_mask) { struct intel_crtc *master_crtc; u8 pipes = 0; @@ -257,7 +257,7 @@ static u8 get_bigjoiner_slave_pipes(struct drm_i915_private *i915, u8 master_pip struct intel_crtc_state *master_crtc_state = to_intel_crtc_state(master_crtc->base.state); - pipes |= intel_crtc_bigjoiner_slave_pipes(master_crtc_state); + pipes |= intel_crtc_joiner_slave_pipes(master_crtc_state); } return pipes; @@ -269,21 +269,21 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, struct drm_i915_private *i915 = to_i915(crtc->base.dev); u8 portsync_master_mask; u8 portsync_slaves_mask; - u8 bigjoiner_slaves_mask; + u8 joiner_slaves_mask; struct intel_crtc *temp_crtc; /* TODO: Add support for MST */ get_portsync_pipes(crtc, &portsync_master_mask, &portsync_slaves_mask); - bigjoiner_slaves_mask = get_bigjoiner_slave_pipes(i915, - portsync_master_mask | - portsync_slaves_mask); + joiner_slaves_mask = get_joiner_slave_pipes(i915, + portsync_master_mask | + portsync_slaves_mask); drm_WARN_ON(&i915->drm, portsync_master_mask & portsync_slaves_mask || - portsync_master_mask & bigjoiner_slaves_mask || - portsync_slaves_mask & bigjoiner_slaves_mask); + portsync_master_mask & joiner_slaves_mask || + portsync_slaves_mask & joiner_slaves_mask); - for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, bigjoiner_slaves_mask) + for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, joiner_slaves_mask) intel_crtc_disable_noatomic_begin(temp_crtc, ctx); for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_slaves_mask) @@ -293,7 +293,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, intel_crtc_disable_noatomic_begin(temp_crtc, ctx); for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, - bigjoiner_slaves_mask | + joiner_slaves_mask | portsync_slaves_mask | portsync_master_mask) intel_crtc_disable_noatomic_complete(temp_crtc); @@ -326,7 +326,7 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) { - if (intel_crtc_is_bigjoiner_slave(crtc_state)) + if (intel_crtc_is_joiner_slave(crtc_state)) return; crtc_state->uapi.enable = crtc_state->hw.enable; @@ -474,7 +474,7 @@ static bool intel_sanitize_crtc(struct intel_crtc *crtc, } if (!crtc_state->hw.active || - intel_crtc_is_bigjoiner_slave(crtc_state)) + intel_crtc_is_joiner_slave(crtc_state)) return false; needs_link_reset = intel_crtc_needs_link_reset(crtc); @@ -728,15 +728,15 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) encoder->base.crtc = &crtc->base; intel_encoder_get_config(encoder, crtc_state); - /* read out to slave crtc as well for bigjoiner */ - if (crtc_state->bigjoiner_pipes) { + /* read out to slave crtc as well for joiner */ + if (crtc_state->joiner_pipes) { struct intel_crtc *slave_crtc; - /* encoder should read be linked to bigjoiner master */ - WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state)); + /* encoder should read be linked to joiner master */ + WARN_ON(intel_crtc_is_joiner_slave(crtc_state)); for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, - intel_crtc_bigjoiner_slave_pipes(crtc_state)) { + intel_crtc_joiner_slave_pipes(crtc_state)) { struct intel_crtc_state *slave_crtc_state; slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 1cce9713a960..920186c2264d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1480,13 +1480,13 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, } /* - * FIXME figure out what is wrong with PSR+bigjoiner and + * FIXME figure out what is wrong with PSR+joiner and * fix it. Presumably something related to the fact that * PSR is a transcoder level feature. */ - if (crtc_state->bigjoiner_pipes) { + if (crtc_state->joiner_pipes) { drm_dbg_kms(&dev_priv->drm, - "PSR disabled due to bigjoiner\n"); + "PSR disabled due to joiner\n"); return; } diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index d76e70846a8c..56827340982b 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -379,7 +379,7 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state) { int num_vdsc_instances = intel_dsc_get_vdsc_per_pipe(crtc_state); - if (crtc_state->bigjoiner_pipes) + if (crtc_state->joiner_pipes) num_vdsc_instances *= 2; return num_vdsc_instances; @@ -760,8 +760,8 @@ void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); u32 dss_ctl1_val = 0; - if (crtc_state->bigjoiner_pipes && !crtc_state->dsc.compression_enable) { - if (intel_crtc_is_bigjoiner_slave(crtc_state)) + if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) { + if (intel_crtc_is_joiner_slave(crtc_state)) dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE; else dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER; @@ -788,9 +788,9 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) dss_ctl2_val |= RIGHT_BRANCH_VDSC_ENABLE; dss_ctl1_val |= JOINER_ENABLE; } - if (crtc_state->bigjoiner_pipes) { + if (crtc_state->joiner_pipes) { dss_ctl1_val |= BIG_JOINER_ENABLE; - if (!intel_crtc_is_bigjoiner_slave(crtc_state)) + if (!intel_crtc_is_joiner_slave(crtc_state)) dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; } intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); @@ -804,7 +804,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) /* Disable only if either of them is enabled */ if (old_crtc_state->dsc.compression_enable || - old_crtc_state->bigjoiner_pipes) { + old_crtc_state->joiner_pipes) { intel_de_write(dev_priv, dss_ctl1_reg(crtc, old_crtc_state->cpu_transcoder), 0); intel_de_write(dev_priv, dss_ctl2_reg(crtc, old_crtc_state->cpu_transcoder), 0); } diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 05f67dc9d98d..1bef1f6f58ee 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -174,7 +174,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, * FIXME all joined pipes share the same transcoder. * Need to account for that during VRR toggle/push/etc. */ - if (crtc_state->bigjoiner_pipes) + if (crtc_state->joiner_pipes) return; if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c index 1aa70fc35b9d..8a66b1002a74 100644 --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c @@ -2558,9 +2558,9 @@ skl_get_initial_plane_config(struct intel_crtc *crtc, drm_WARN_ON(dev, pipe != crtc->pipe); - if (crtc_state->bigjoiner_pipes) { + if (crtc_state->joiner_pipes) { drm_dbg_kms(&dev_priv->drm, - "Unsupported bigjoiner configuration for initial FB\n"); + "Unsupported joiner configuration for initial FB\n"); return; } -- cgit From da8c3cdb016cca4e2c72c12bff4d6eeb0237e686 Mon Sep 17 00:00:00 2001 From: Stanislav Lisovskiy Date: Mon, 3 Jun 2024 14:25:50 +0300 Subject: drm/i915: Rename bigjoiner master/slave to bigjoiner primary/secondary MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to BSpec we now should call "master" pipes, "primary" pipes and "slave" pipes, should be "secondary" pipes. Signed-off-by: Stanislav Lisovskiy [vsyrjala: Don't rename port sync stuff, catch a few more things] Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240603112551.6481-3-stanislav.lisovskiy@intel.com --- drivers/gpu/drm/i915/display/intel_atomic_plane.c | 28 +- .../gpu/drm/i915/display/intel_crtc_state_dump.c | 4 +- drivers/gpu/drm/i915/display/intel_ddi.c | 5 +- drivers/gpu/drm/i915/display/intel_display.c | 342 ++++++++++----------- drivers/gpu/drm/i915/display/intel_display.h | 8 +- .../gpu/drm/i915/display/intel_display_debugfs.c | 2 +- drivers/gpu/drm/i915/display/intel_drrs.c | 4 +- drivers/gpu/drm/i915/display/intel_modeset_setup.c | 58 ++-- .../gpu/drm/i915/display/intel_modeset_verify.c | 8 +- drivers/gpu/drm/i915/display/intel_vdsc.c | 10 +- drivers/gpu/drm/i915/display/intel_vdsc_regs.h | 6 +- 11 files changed, 237 insertions(+), 238 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c index 8903bca2e6ab..8ec1bab1b15d 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -336,10 +336,10 @@ void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state, intel_plane_clear_hw_state(plane_state); /* - * For the joiner slave uapi.crtc will point at - * the master crtc. So we explicitly assign the right - * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates - * the plane is logically enabled on the uapi level. + * For the joiner secondary uapi.crtc will point at + * the primary crtc. So we explicitly assign the right + * secondary crtc to hw.crtc. uapi.crtc!=NULL simply + * indicates the plane is logically enabled on the uapi level. */ plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL; @@ -714,27 +714,27 @@ int intel_plane_atomic_check(struct intel_atomic_state *state, intel_atomic_get_new_plane_state(state, plane); const struct intel_plane_state *old_plane_state = intel_atomic_get_old_plane_state(state, plane); - const struct intel_plane_state *new_master_plane_state; + const struct intel_plane_state *new_primary_crtc_plane_state; struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe); const struct intel_crtc_state *old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - if (new_crtc_state && intel_crtc_is_joiner_slave(new_crtc_state)) { - struct intel_crtc *master_crtc = - intel_master_crtc(new_crtc_state); - struct intel_plane *master_plane = - intel_crtc_get_plane(master_crtc, plane->id); + if (new_crtc_state && intel_crtc_is_joiner_secondary(new_crtc_state)) { + struct intel_crtc *primary_crtc = + intel_primary_crtc(new_crtc_state); + struct intel_plane *primary_crtc_plane = + intel_crtc_get_plane(primary_crtc, plane->id); - new_master_plane_state = - intel_atomic_get_new_plane_state(state, master_plane); + new_primary_crtc_plane_state = + intel_atomic_get_new_plane_state(state, primary_crtc_plane); } else { - new_master_plane_state = new_plane_state; + new_primary_crtc_plane_state = new_plane_state; } intel_plane_copy_uapi_to_hw_state(new_plane_state, - new_master_plane_state, + new_primary_crtc_plane_state, crtc); new_plane_state->uapi.visible = false; diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 5d35c5537eaa..6df526e189b5 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -223,8 +223,8 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, pipe_config->sync_mode_slaves_mask); drm_printf(&p, "joiner: %s, pipes: 0x%x\n", - intel_crtc_is_joiner_slave(pipe_config) ? "slave" : - intel_crtc_is_joiner_master(pipe_config) ? "master" : "no", + intel_crtc_is_joiner_secondary(pipe_config) ? "secondary" : + intel_crtc_is_joiner_primary(pipe_config) ? "primary" : "no", pipe_config->joiner_pipes); drm_printf(&p, "splitter: %s, link count %d, overlap %d\n", diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index eb265eac2ad7..ba7d0a706a20 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -3516,11 +3516,10 @@ intel_ddi_pre_pll_enable(struct intel_atomic_state *state, bool is_tc_port = intel_encoder_is_tc(encoder); if (is_tc_port) { - struct intel_crtc *master_crtc = - to_intel_crtc(crtc_state->uapi.crtc); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); intel_tc_port_get_link(dig_port, crtc_state->lane_count); - intel_ddi_update_active_dpll(state, encoder, master_crtc); + intel_ddi_update_active_dpll(state, encoder, crtc); } main_link_aux_power_domain_get(dig_port, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index bea388d71b50..77220254e8b8 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -246,33 +246,33 @@ is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state) is_trans_port_sync_slave(crtc_state); } -static enum pipe joiner_master_pipe(const struct intel_crtc_state *crtc_state) +static enum pipe joiner_primary_pipe(const struct intel_crtc_state *crtc_state) { return ffs(crtc_state->joiner_pipes) - 1; } -u8 intel_crtc_joiner_slave_pipes(const struct intel_crtc_state *crtc_state) +u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state) { if (crtc_state->joiner_pipes) - return crtc_state->joiner_pipes & ~BIT(joiner_master_pipe(crtc_state)); + return crtc_state->joiner_pipes & ~BIT(joiner_primary_pipe(crtc_state)); else return 0; } -bool intel_crtc_is_joiner_slave(const struct intel_crtc_state *crtc_state) +bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); return crtc_state->joiner_pipes && - crtc->pipe != joiner_master_pipe(crtc_state); + crtc->pipe != joiner_primary_pipe(crtc_state); } -bool intel_crtc_is_joiner_master(const struct intel_crtc_state *crtc_state) +bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); return crtc_state->joiner_pipes && - crtc->pipe == joiner_master_pipe(crtc_state); + crtc->pipe == joiner_primary_pipe(crtc_state); } static int intel_joiner_num_pipes(const struct intel_crtc_state *crtc_state) @@ -287,12 +287,12 @@ u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state) return BIT(crtc->pipe) | crtc_state->joiner_pipes; } -struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state) +struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - if (intel_crtc_is_joiner_slave(crtc_state)) - return intel_crtc_for_pipe(i915, joiner_master_pipe(crtc_state)); + if (intel_crtc_is_joiner_secondary(crtc_state)) + return intel_crtc_for_pipe(i915, joiner_primary_pipe(crtc_state)); else return to_intel_crtc(crtc_state->uapi.crtc); } @@ -803,14 +803,14 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state, const struct drm_connector_state *connector_state; const struct drm_connector *connector; struct intel_encoder *encoder = NULL; - struct intel_crtc *master_crtc; + struct intel_crtc *primary_crtc; int num_encoders = 0; int i; - master_crtc = intel_master_crtc(crtc_state); + primary_crtc = intel_primary_crtc(crtc_state); for_each_new_connector_in_state(&state->base, connector, connector_state, i) { - if (connector_state->crtc != &master_crtc->base) + if (connector_state->crtc != &primary_crtc->base) continue; encoder = to_intel_encoder(connector_state->best_encoder); @@ -819,7 +819,7 @@ intel_get_crtc_new_encoder(const struct intel_atomic_state *state, drm_WARN(state->base.dev, num_encoders != 1, "%d encoders for pipe %c\n", - num_encoders, pipe_name(master_crtc->pipe)); + num_encoders, pipe_name(primary_crtc->pipe)); return encoder; } @@ -2876,17 +2876,17 @@ static void intel_joiner_adjust_pipe_src(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); int num_pipes = intel_joiner_num_pipes(crtc_state); - enum pipe master_pipe, pipe = crtc->pipe; + enum pipe primary_pipe, pipe = crtc->pipe; int width; if (num_pipes < 2) return; - master_pipe = joiner_master_pipe(crtc_state); + primary_pipe = joiner_primary_pipe(crtc_state); width = drm_rect_width(&crtc_state->pipe_src); drm_rect_translate_to(&crtc_state->pipe_src, - (pipe - master_pipe) * width, 0); + (pipe - primary_pipe) * width, 0); } static void intel_get_pipe_src_size(struct intel_crtc *crtc, @@ -3523,12 +3523,12 @@ static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv, } static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, - u8 *master_pipes, u8 *slave_pipes) + u8 *primary_pipes, u8 *secondary_pipes) { struct intel_crtc *crtc; - *master_pipes = 0; - *slave_pipes = 0; + *primary_pipes = 0; + *secondary_pipes = 0; for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, joiner_pipes(dev_priv)) { @@ -3543,10 +3543,10 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, if (!(tmp & BIG_JOINER_ENABLE)) continue; - if (tmp & MASTER_BIG_JOINER_ENABLE) - *master_pipes |= BIT(pipe); + if (tmp & PRIMARY_BIG_JOINER_ENABLE) + *primary_pipes |= BIT(pipe); else - *slave_pipes |= BIT(pipe); + *secondary_pipes |= BIT(pipe); } if (DISPLAY_VER(dev_priv) < 13) @@ -3556,48 +3556,48 @@ static void enabled_joiner_pipes(struct drm_i915_private *dev_priv, with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) { u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe)); - if (tmp & UNCOMPRESSED_JOINER_MASTER) - *master_pipes |= BIT(pipe); - if (tmp & UNCOMPRESSED_JOINER_SLAVE) - *slave_pipes |= BIT(pipe); + if (tmp & UNCOMPRESSED_JOINER_PRIMARY) + *primary_pipes |= BIT(pipe); + if (tmp & UNCOMPRESSED_JOINER_SECONDARY) + *secondary_pipes |= BIT(pipe); } } - /* Joiner pipes should always be consecutive master and slave */ - drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1, - "Joiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n", - *master_pipes, *slave_pipes); + /* Joiner pipes should always be consecutive primary and secondary */ + drm_WARN(&dev_priv->drm, *secondary_pipes != *primary_pipes << 1, + "Joiner misconfigured (primary pipes 0x%x, secondary pipes 0x%x)\n", + *primary_pipes, *secondary_pipes); } -static enum pipe get_joiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes) +static enum pipe get_joiner_primary_pipe(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes) { - if ((slave_pipes & BIT(pipe)) == 0) + if ((secondary_pipes & BIT(pipe)) == 0) return pipe; /* ignore everything above our pipe */ - master_pipes &= ~GENMASK(7, pipe); + primary_pipes &= ~GENMASK(7, pipe); - /* highest remaining bit should be our master pipe */ - return fls(master_pipes) - 1; + /* highest remaining bit should be our primary pipe */ + return fls(primary_pipes) - 1; } -static u8 get_joiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes) +static u8 get_joiner_secondary_pipes(enum pipe pipe, u8 primary_pipes, u8 secondary_pipes) { - enum pipe master_pipe, next_master_pipe; + enum pipe primary_pipe, next_primary_pipe; - master_pipe = get_joiner_master_pipe(pipe, master_pipes, slave_pipes); + primary_pipe = get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes); - if ((master_pipes & BIT(master_pipe)) == 0) + if ((primary_pipes & BIT(primary_pipe)) == 0) return 0; - /* ignore our master pipe and everything below it */ - master_pipes &= ~GENMASK(master_pipe, 0); + /* ignore our primary pipe and everything below it */ + primary_pipes &= ~GENMASK(primary_pipe, 0); /* make sure a high bit is set for the ffs() */ - master_pipes |= BIT(7); - /* lowest remaining bit should be the next master pipe */ - next_master_pipe = ffs(master_pipes) - 1; + primary_pipes |= BIT(7); + /* lowest remaining bit should be the next primary pipe */ + next_primary_pipe = ffs(primary_pipes) - 1; - return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe); + return secondary_pipes & GENMASK(next_primary_pipe - 1, primary_pipe); } static u8 hsw_panel_transcoders(struct drm_i915_private *i915) @@ -3616,7 +3616,7 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) struct drm_i915_private *dev_priv = to_i915(dev); u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv); enum transcoder cpu_transcoder; - u8 master_pipes, slave_pipes; + u8 primary_pipes, secondary_pipes; u8 enabled_transcoders = 0; /* @@ -3663,16 +3663,16 @@ static u8 hsw_enabled_transcoders(struct intel_crtc *crtc) enabled_transcoders |= BIT(cpu_transcoder); } - /* single pipe or joiner master */ + /* single pipe or joiner primary */ cpu_transcoder = (enum transcoder) crtc->pipe; if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) enabled_transcoders |= BIT(cpu_transcoder); - /* joiner slave -> consider the master pipe's transcoder as well */ - enabled_joiner_pipes(dev_priv, &master_pipes, &slave_pipes); - if (slave_pipes & BIT(crtc->pipe)) { + /* joiner secondary -> consider the primary pipe's transcoder as well */ + enabled_joiner_pipes(dev_priv, &primary_pipes, &secondary_pipes); + if (secondary_pipes & BIT(crtc->pipe)) { cpu_transcoder = (enum transcoder) - get_joiner_master_pipe(crtc->pipe, master_pipes, slave_pipes); + get_joiner_primary_pipe(crtc->pipe, primary_pipes, secondary_pipes); if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder)) enabled_transcoders |= BIT(cpu_transcoder); } @@ -3803,17 +3803,17 @@ static void intel_joiner_get_config(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - u8 master_pipes, slave_pipes; + u8 primary_pipes, secondary_pipes; enum pipe pipe = crtc->pipe; - enabled_joiner_pipes(i915, &master_pipes, &slave_pipes); + enabled_joiner_pipes(i915, &primary_pipes, &secondary_pipes); - if (((master_pipes | slave_pipes) & BIT(pipe)) == 0) + if (((primary_pipes | secondary_pipes) & BIT(pipe)) == 0) return; crtc_state->joiner_pipes = - BIT(get_joiner_master_pipe(pipe, master_pipes, slave_pipes)) | - get_joiner_slave_pipes(pipe, master_pipes, slave_pipes); + BIT(get_joiner_primary_pipe(pipe, primary_pipes, secondary_pipes)) | + get_joiner_secondary_pipes(pipe, primary_pipes, secondary_pipes); } static bool hsw_get_pipe_config(struct intel_crtc *crtc, @@ -4480,7 +4480,7 @@ intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - WARN_ON(intel_crtc_is_joiner_slave(crtc_state)); + WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); drm_property_replace_blob(&crtc_state->hw.degamma_lut, crtc_state->uapi.degamma_lut); @@ -4497,7 +4497,7 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - WARN_ON(intel_crtc_is_joiner_slave(crtc_state)); + WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); crtc_state->hw.enable = crtc_state->uapi.enable; crtc_state->hw.active = crtc_state->uapi.active; @@ -4512,78 +4512,78 @@ intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state, static void copy_joiner_crtc_state_nomodeset(struct intel_atomic_state *state, - struct intel_crtc *slave_crtc) + struct intel_crtc *secondary_crtc) { - struct intel_crtc_state *slave_crtc_state = - intel_atomic_get_new_crtc_state(state, slave_crtc); - struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); - const struct intel_crtc_state *master_crtc_state = - intel_atomic_get_new_crtc_state(state, master_crtc); + struct intel_crtc_state *secondary_crtc_state = + intel_atomic_get_new_crtc_state(state, secondary_crtc); + struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); + const struct intel_crtc_state *primary_crtc_state = + intel_atomic_get_new_crtc_state(state, primary_crtc); - drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut, - master_crtc_state->hw.degamma_lut); - drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut, - master_crtc_state->hw.gamma_lut); - drm_property_replace_blob(&slave_crtc_state->hw.ctm, - master_crtc_state->hw.ctm); + drm_property_replace_blob(&secondary_crtc_state->hw.degamma_lut, + primary_crtc_state->hw.degamma_lut); + drm_property_replace_blob(&secondary_crtc_state->hw.gamma_lut, + primary_crtc_state->hw.gamma_lut); + drm_property_replace_blob(&secondary_crtc_state->hw.ctm, + primary_crtc_state->hw.ctm); - slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed; + secondary_crtc_state->uapi.color_mgmt_changed = primary_crtc_state->uapi.color_mgmt_changed; } static int copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, - struct intel_crtc *slave_crtc) + struct intel_crtc *secondary_crtc) { - struct intel_crtc_state *slave_crtc_state = - intel_atomic_get_new_crtc_state(state, slave_crtc); - struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state); - const struct intel_crtc_state *master_crtc_state = - intel_atomic_get_new_crtc_state(state, master_crtc); + struct intel_crtc_state *secondary_crtc_state = + intel_atomic_get_new_crtc_state(state, secondary_crtc); + struct intel_crtc *primary_crtc = intel_primary_crtc(secondary_crtc_state); + const struct intel_crtc_state *primary_crtc_state = + intel_atomic_get_new_crtc_state(state, primary_crtc); struct intel_crtc_state *saved_state; - WARN_ON(master_crtc_state->joiner_pipes != - slave_crtc_state->joiner_pipes); + WARN_ON(primary_crtc_state->joiner_pipes != + secondary_crtc_state->joiner_pipes); - saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL); + saved_state = kmemdup(primary_crtc_state, sizeof(*saved_state), GFP_KERNEL); if (!saved_state) return -ENOMEM; /* preserve some things from the slave's original crtc state */ - saved_state->uapi = slave_crtc_state->uapi; - saved_state->scaler_state = slave_crtc_state->scaler_state; - saved_state->shared_dpll = slave_crtc_state->shared_dpll; - saved_state->crc_enabled = slave_crtc_state->crc_enabled; - - intel_crtc_free_hw_state(slave_crtc_state); - if (slave_crtc_state->dp_tunnel_ref.tunnel) - drm_dp_tunnel_ref_put(&slave_crtc_state->dp_tunnel_ref); - memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state)); + saved_state->uapi = secondary_crtc_state->uapi; + saved_state->scaler_state = secondary_crtc_state->scaler_state; + saved_state->shared_dpll = secondary_crtc_state->shared_dpll; + saved_state->crc_enabled = secondary_crtc_state->crc_enabled; + + intel_crtc_free_hw_state(secondary_crtc_state); + if (secondary_crtc_state->dp_tunnel_ref.tunnel) + drm_dp_tunnel_ref_put(&secondary_crtc_state->dp_tunnel_ref); + memcpy(secondary_crtc_state, saved_state, sizeof(*secondary_crtc_state)); kfree(saved_state); /* Re-init hw state */ - memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw)); - slave_crtc_state->hw.enable = master_crtc_state->hw.enable; - slave_crtc_state->hw.active = master_crtc_state->hw.active; - drm_mode_copy(&slave_crtc_state->hw.mode, - &master_crtc_state->hw.mode); - drm_mode_copy(&slave_crtc_state->hw.pipe_mode, - &master_crtc_state->hw.pipe_mode); - drm_mode_copy(&slave_crtc_state->hw.adjusted_mode, - &master_crtc_state->hw.adjusted_mode); - slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter; - - if (master_crtc_state->dp_tunnel_ref.tunnel) - drm_dp_tunnel_ref_get(master_crtc_state->dp_tunnel_ref.tunnel, - &slave_crtc_state->dp_tunnel_ref); - - copy_joiner_crtc_state_nomodeset(state, slave_crtc); - - slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed; - slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed; - slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed; - - WARN_ON(master_crtc_state->joiner_pipes != - slave_crtc_state->joiner_pipes); + memset(&secondary_crtc_state->hw, 0, sizeof(secondary_crtc_state->hw)); + secondary_crtc_state->hw.enable = primary_crtc_state->hw.enable; + secondary_crtc_state->hw.active = primary_crtc_state->hw.active; + drm_mode_copy(&secondary_crtc_state->hw.mode, + &primary_crtc_state->hw.mode); + drm_mode_copy(&secondary_crtc_state->hw.pipe_mode, + &primary_crtc_state->hw.pipe_mode); + drm_mode_copy(&secondary_crtc_state->hw.adjusted_mode, + &primary_crtc_state->hw.adjusted_mode); + secondary_crtc_state->hw.scaling_filter = primary_crtc_state->hw.scaling_filter; + + if (primary_crtc_state->dp_tunnel_ref.tunnel) + drm_dp_tunnel_ref_get(primary_crtc_state->dp_tunnel_ref.tunnel, + &secondary_crtc_state->dp_tunnel_ref); + + copy_joiner_crtc_state_nomodeset(state, secondary_crtc); + + secondary_crtc_state->uapi.mode_changed = primary_crtc_state->uapi.mode_changed; + secondary_crtc_state->uapi.connectors_changed = primary_crtc_state->uapi.connectors_changed; + secondary_crtc_state->uapi.active_changed = primary_crtc_state->uapi.active_changed; + + WARN_ON(primary_crtc_state->joiner_pipes != + secondary_crtc_state->joiner_pipes); return 0; } @@ -5950,69 +5950,69 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state, } static int intel_atomic_check_joiner(struct intel_atomic_state *state, - struct intel_crtc *master_crtc) + struct intel_crtc *primary_crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); - struct intel_crtc_state *master_crtc_state = - intel_atomic_get_new_crtc_state(state, master_crtc); - struct intel_crtc *slave_crtc; + struct intel_crtc_state *primary_crtc_state = + intel_atomic_get_new_crtc_state(state, primary_crtc); + struct intel_crtc *secondary_crtc; - if (!master_crtc_state->joiner_pipes) + if (!primary_crtc_state->joiner_pipes) return 0; /* sanity check */ if (drm_WARN_ON(&i915->drm, - master_crtc->pipe != joiner_master_pipe(master_crtc_state))) + primary_crtc->pipe != joiner_primary_pipe(primary_crtc_state))) return -EINVAL; - if (master_crtc_state->joiner_pipes & ~joiner_pipes(i915)) { + if (primary_crtc_state->joiner_pipes & ~joiner_pipes(i915)) { drm_dbg_kms(&i915->drm, - "[CRTC:%d:%s] Cannot act as joiner master " + "[CRTC:%d:%s] Cannot act as joiner primary " "(need 0x%x as pipes, only 0x%x possible)\n", - master_crtc->base.base.id, master_crtc->base.name, - master_crtc_state->joiner_pipes, joiner_pipes(i915)); + primary_crtc->base.base.id, primary_crtc->base.name, + primary_crtc_state->joiner_pipes, joiner_pipes(i915)); return -EINVAL; } - for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, - intel_crtc_joiner_slave_pipes(master_crtc_state)) { - struct intel_crtc_state *slave_crtc_state; + for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, + intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { + struct intel_crtc_state *secondary_crtc_state; int ret; - slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc); - if (IS_ERR(slave_crtc_state)) - return PTR_ERR(slave_crtc_state); + secondary_crtc_state = intel_atomic_get_crtc_state(&state->base, secondary_crtc); + if (IS_ERR(secondary_crtc_state)) + return PTR_ERR(secondary_crtc_state); - /* master being enabled, slave was already configured? */ - if (slave_crtc_state->uapi.enable) { + /* primary being enabled, secondary was already configured? */ + if (secondary_crtc_state->uapi.enable) { drm_dbg_kms(&i915->drm, - "[CRTC:%d:%s] Slave is enabled as normal CRTC, but " + "[CRTC:%d:%s] secondary is enabled as normal CRTC, but " "[CRTC:%d:%s] claiming this CRTC for joiner.\n", - slave_crtc->base.base.id, slave_crtc->base.name, - master_crtc->base.base.id, master_crtc->base.name); + secondary_crtc->base.base.id, secondary_crtc->base.name, + primary_crtc->base.base.id, primary_crtc->base.name); return -EINVAL; } /* - * The state copy logic assumes the master crtc gets processed - * before the slave crtc during the main compute_config loop. + * The state copy logic assumes the primary crtc gets processed + * before the secondary crtc during the main compute_config loop. * This works because the crtcs are created in pipe order, - * and the hardware requires master pipe < slave pipe as well. + * and the hardware requires primary pipe < secondary pipe as well. * Should that change we need to rethink the logic. */ - if (WARN_ON(drm_crtc_index(&master_crtc->base) > - drm_crtc_index(&slave_crtc->base))) + if (WARN_ON(drm_crtc_index(&primary_crtc->base) > + drm_crtc_index(&secondary_crtc->base))) return -EINVAL; drm_dbg_kms(&i915->drm, - "[CRTC:%d:%s] Used as slave for joiner master [CRTC:%d:%s]\n", - slave_crtc->base.base.id, slave_crtc->base.name, - master_crtc->base.base.id, master_crtc->base.name); + "[CRTC:%d:%s] Used as secondary for joiner primary [CRTC:%d:%s]\n", + secondary_crtc->base.base.id, secondary_crtc->base.name, + primary_crtc->base.base.id, primary_crtc->base.name); - slave_crtc_state->joiner_pipes = - master_crtc_state->joiner_pipes; + secondary_crtc_state->joiner_pipes = + primary_crtc_state->joiner_pipes; - ret = copy_joiner_crtc_state_modeset(state, slave_crtc); + ret = copy_joiner_crtc_state_modeset(state, secondary_crtc); if (ret) return ret; } @@ -6020,25 +6020,25 @@ static int intel_atomic_check_joiner(struct intel_atomic_state *state, return 0; } -static void kill_joiner_slave(struct intel_atomic_state *state, - struct intel_crtc *master_crtc) +static void kill_joiner_secondaries(struct intel_atomic_state *state, + struct intel_crtc *primary_crtc) { struct drm_i915_private *i915 = to_i915(state->base.dev); - struct intel_crtc_state *master_crtc_state = - intel_atomic_get_new_crtc_state(state, master_crtc); - struct intel_crtc *slave_crtc; + struct intel_crtc_state *primary_crtc_state = + intel_atomic_get_new_crtc_state(state, primary_crtc); + struct intel_crtc *secondary_crtc; - for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, - intel_crtc_joiner_slave_pipes(master_crtc_state)) { - struct intel_crtc_state *slave_crtc_state = - intel_atomic_get_new_crtc_state(state, slave_crtc); + for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, + intel_crtc_joiner_secondary_pipes(primary_crtc_state)) { + struct intel_crtc_state *secondary_crtc_state = + intel_atomic_get_new_crtc_state(state, secondary_crtc); - slave_crtc_state->joiner_pipes = 0; + secondary_crtc_state->joiner_pipes = 0; - intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc); + intel_crtc_copy_uapi_to_hw_state_modeset(state, secondary_crtc); } - master_crtc_state->joiner_pipes = 0; + primary_crtc_state->joiner_pipes = 0; } /** @@ -6358,8 +6358,8 @@ static int intel_joiner_add_affected_crtcs(struct intel_atomic_state *state) for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) { /* Kill old joiner link, we may re-establish afterwards */ if (intel_crtc_needs_modeset(crtc_state) && - intel_crtc_is_joiner_master(crtc_state)) - kill_joiner_slave(state, crtc); + intel_crtc_is_joiner_primary(crtc_state)) + kill_joiner_secondaries(state, crtc); } return 0; @@ -6387,14 +6387,14 @@ static int intel_atomic_check_config(struct intel_atomic_state *state, for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) { if (!intel_crtc_needs_modeset(new_crtc_state)) { - if (intel_crtc_is_joiner_slave(new_crtc_state)) + if (intel_crtc_is_joiner_secondary(new_crtc_state)) copy_joiner_crtc_state_nomodeset(state, crtc); else intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc); continue; } - if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_slave(new_crtc_state))) + if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) continue; ret = intel_crtc_prepare_cleared_state(state, crtc); @@ -6413,7 +6413,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state, if (!intel_crtc_needs_modeset(new_crtc_state)) continue; - if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_slave(new_crtc_state))) + if (drm_WARN_ON(&i915->drm, intel_crtc_is_joiner_secondary(new_crtc_state))) continue; if (!new_crtc_state->hw.enable) @@ -6524,7 +6524,7 @@ int intel_atomic_check(struct drm_device *dev, if (!intel_crtc_needs_modeset(new_crtc_state)) continue; - if (intel_crtc_is_joiner_slave(new_crtc_state)) { + if (intel_crtc_is_joiner_secondary(new_crtc_state)) { drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable); continue; } @@ -6995,7 +6995,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) if ((disable_pipes & BIT(crtc->pipe)) == 0) continue; - if (intel_crtc_is_joiner_slave(old_crtc_state)) + if (intel_crtc_is_joiner_secondary(old_crtc_state)) continue; /* In case of Transcoder port Sync master slave CRTCs can be @@ -7017,7 +7017,7 @@ static void intel_commit_modeset_disables(struct intel_atomic_state *state) if ((disable_pipes & BIT(crtc->pipe)) == 0) continue; - if (intel_crtc_is_joiner_slave(old_crtc_state)) + if (intel_crtc_is_joiner_secondary(old_crtc_state)) continue; intel_old_crtc_state_disables(state, crtc); @@ -7096,8 +7096,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) while (update_pipes) { /* - * Commit in reverse order to make joiner master - * send the uapi events after slaves are done. + * Commit in reverse order to make joiner primary + * send the uapi events after secondaries are done. */ for_each_oldnew_intel_crtc_in_state_reverse(state, crtc, old_crtc_state, new_crtc_state, i) { @@ -7142,7 +7142,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((modeset_pipes & BIT(pipe)) == 0) continue; - if (intel_crtc_is_joiner_slave(new_crtc_state)) + if (intel_crtc_is_joiner_secondary(new_crtc_state)) continue; if (intel_dp_mst_is_slave_trans(new_crtc_state) || @@ -7164,7 +7164,7 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) if ((modeset_pipes & BIT(pipe)) == 0) continue; - if (intel_crtc_is_joiner_slave(new_crtc_state)) + if (intel_crtc_is_joiner_secondary(new_crtc_state)) continue; modeset_pipes &= ~intel_crtc_joined_pipe_mask(new_crtc_state); @@ -7185,8 +7185,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state) } /* - * Commit in reverse order to make joiner master - * send the uapi events after slaves are done. + * Commit in reverse order to make joiner primary + * send the uapi events after secondaries are done. */ for_each_new_intel_crtc_in_state_reverse(state, crtc, new_crtc_state, i) { enum pipe pipe = crtc->pipe; diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index a2ec5309113e..48454cf21906 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -423,10 +423,10 @@ enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port); bool is_trans_port_sync_mode(const struct intel_crtc_state *state); bool is_trans_port_sync_master(const struct intel_crtc_state *state); u8 intel_crtc_joined_pipe_mask(const struct intel_crtc_state *crtc_state); -bool intel_crtc_is_joiner_slave(const struct intel_crtc_state *crtc_state); -bool intel_crtc_is_joiner_master(const struct intel_crtc_state *crtc_state); -u8 intel_crtc_joiner_slave_pipes(const struct intel_crtc_state *crtc_state); -struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state); +bool intel_crtc_is_joiner_secondary(const struct intel_crtc_state *crtc_state); +bool intel_crtc_is_joiner_primary(const struct intel_crtc_state *crtc_state); +u8 intel_crtc_joiner_secondary_pipes(const struct intel_crtc_state *crtc_state); +struct intel_crtc *intel_primary_crtc(const struct intel_crtc_state *crtc_state); bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state); bool intel_pipe_config_compare(const struct intel_crtc_state *current_config, const struct intel_crtc_state *pipe_config, diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 7090f6dccd6c..959e894e27d3 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -578,7 +578,7 @@ static void intel_crtc_info(struct seq_file *m, struct intel_crtc *crtc) if (crtc_state->joiner_pipes) seq_printf(m, "\tLinked to 0x%x pipes as a %s\n", crtc_state->joiner_pipes, - intel_crtc_is_joiner_slave(crtc_state) ? "slave" : "master"); + intel_crtc_is_joiner_secondary(crtc_state) ? "slave" : "master"); for_each_intel_encoder_mask(&dev_priv->drm, encoder, crtc_state->uapi.encoder_mask) diff --git a/drivers/gpu/drm/i915/display/intel_drrs.c b/drivers/gpu/drm/i915/display/intel_drrs.c index 8af5ee434782..3ca29afa5422 100644 --- a/drivers/gpu/drm/i915/display/intel_drrs.c +++ b/drivers/gpu/drm/i915/display/intel_drrs.c @@ -157,7 +157,7 @@ void intel_drrs_activate(const struct intel_crtc_state *crtc_state) if (!crtc_state->hw.active) return; - if (intel_crtc_is_joiner_slave(crtc_state)) + if (intel_crtc_is_joiner_secondary(crtc_state)) return; mutex_lock(&crtc->drrs.mutex); @@ -189,7 +189,7 @@ void intel_drrs_deactivate(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->hw.active) return; - if (intel_crtc_is_joiner_slave(old_crtc_state)) + if (intel_crtc_is_joiner_secondary(old_crtc_state)) return; mutex_lock(&crtc->drrs.mutex); diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c index 066252c45e12..7602cb30ebf1 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c @@ -68,7 +68,7 @@ static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc, /* Everything's already locked, -EDEADLK can't happen. */ for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, BIT(pipe) | - intel_crtc_joiner_slave_pipes(crtc_state)) { + intel_crtc_joiner_secondary_pipes(crtc_state)) { struct intel_crtc_state *temp_crtc_state = intel_atomic_get_crtc_state(state, temp_crtc); int ret; @@ -189,7 +189,7 @@ static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc) /* * Return all the pipes using a transcoder in @transcoder_mask. - * For joiner configs return only the joiner master. + * For joiner configs return only the joiner primary. */ static u8 get_transcoder_pipes(struct drm_i915_private *i915, u8 transcoder_mask) @@ -204,7 +204,7 @@ static u8 get_transcoder_pipes(struct drm_i915_private *i915, if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER) continue; - if (intel_crtc_is_joiner_slave(temp_crtc_state)) + if (intel_crtc_is_joiner_secondary(temp_crtc_state)) continue; if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder)) @@ -216,7 +216,7 @@ static u8 get_transcoder_pipes(struct drm_i915_private *i915, /* * Return the port sync master and slave pipes linked to @crtc. - * For joiner configs return only the joiner master pipes. + * For joiner configs return only the joiner primary pipes. */ static void get_portsync_pipes(struct intel_crtc *crtc, u8 *master_pipe_mask, u8 *slave_pipes_mask) @@ -248,16 +248,16 @@ static void get_portsync_pipes(struct intel_crtc *crtc, *slave_pipes_mask = get_transcoder_pipes(i915, master_crtc_state->sync_mode_slaves_mask); } -static u8 get_joiner_slave_pipes(struct drm_i915_private *i915, u8 master_pipes_mask) +static u8 get_joiner_secondary_pipes(struct drm_i915_private *i915, u8 primary_pipes_mask) { - struct intel_crtc *master_crtc; + struct intel_crtc *primary_crtc; u8 pipes = 0; - for_each_intel_crtc_in_pipe_mask(&i915->drm, master_crtc, master_pipes_mask) { - struct intel_crtc_state *master_crtc_state = - to_intel_crtc_state(master_crtc->base.state); + for_each_intel_crtc_in_pipe_mask(&i915->drm, primary_crtc, primary_pipes_mask) { + struct intel_crtc_state *primary_crtc_state = + to_intel_crtc_state(primary_crtc->base.state); - pipes |= intel_crtc_joiner_slave_pipes(master_crtc_state); + pipes |= intel_crtc_joiner_secondary_pipes(primary_crtc_state); } return pipes; @@ -269,21 +269,21 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, struct drm_i915_private *i915 = to_i915(crtc->base.dev); u8 portsync_master_mask; u8 portsync_slaves_mask; - u8 joiner_slaves_mask; + u8 joiner_secondaries_mask; struct intel_crtc *temp_crtc; /* TODO: Add support for MST */ get_portsync_pipes(crtc, &portsync_master_mask, &portsync_slaves_mask); - joiner_slaves_mask = get_joiner_slave_pipes(i915, - portsync_master_mask | - portsync_slaves_mask); + joiner_secondaries_mask = get_joiner_secondary_pipes(i915, + portsync_master_mask | + portsync_slaves_mask); drm_WARN_ON(&i915->drm, portsync_master_mask & portsync_slaves_mask || - portsync_master_mask & joiner_slaves_mask || - portsync_slaves_mask & joiner_slaves_mask); + portsync_master_mask & joiner_secondaries_mask || + portsync_slaves_mask & joiner_secondaries_mask); - for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, joiner_slaves_mask) + for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, joiner_secondaries_mask) intel_crtc_disable_noatomic_begin(temp_crtc, ctx); for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_slaves_mask) @@ -293,7 +293,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc, intel_crtc_disable_noatomic_begin(temp_crtc, ctx); for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, - joiner_slaves_mask | + joiner_secondaries_mask | portsync_slaves_mask | portsync_master_mask) intel_crtc_disable_noatomic_complete(temp_crtc); @@ -326,7 +326,7 @@ static void intel_modeset_update_connector_atomic_state(struct drm_i915_private static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state) { - if (intel_crtc_is_joiner_slave(crtc_state)) + if (intel_crtc_is_joiner_secondary(crtc_state)) return; crtc_state->uapi.enable = crtc_state->hw.enable; @@ -474,7 +474,7 @@ static bool intel_sanitize_crtc(struct intel_crtc *crtc, } if (!crtc_state->hw.active || - intel_crtc_is_joiner_slave(crtc_state)) + intel_crtc_is_joiner_secondary(crtc_state)) return false; needs_link_reset = intel_crtc_needs_link_reset(crtc); @@ -728,19 +728,19 @@ static void intel_modeset_readout_hw_state(struct drm_i915_private *i915) encoder->base.crtc = &crtc->base; intel_encoder_get_config(encoder, crtc_state); - /* read out to slave crtc as well for joiner */ + /* read out to secondary crtc as well for joiner */ if (crtc_state->joiner_pipes) { - struct intel_crtc *slave_crtc; + struct intel_crtc *secondary_crtc; - /* encoder should read be linked to joiner master */ - WARN_ON(intel_crtc_is_joiner_slave(crtc_state)); + /* encoder should read be linked to joiner primary */ + WARN_ON(intel_crtc_is_joiner_secondary(crtc_state)); - for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc, - intel_crtc_joiner_slave_pipes(crtc_state)) { - struct intel_crtc_state *slave_crtc_state; + for_each_intel_crtc_in_pipe_mask(&i915->drm, secondary_crtc, + intel_crtc_joiner_secondary_pipes(crtc_state)) { + struct intel_crtc_state *secondary_crtc_state; - slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state); - intel_encoder_get_config(encoder, slave_crtc_state); + secondary_crtc_state = to_intel_crtc_state(secondary_crtc->base.state); + intel_encoder_get_config(encoder, secondary_crtc_state); } } diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index 076298a8d405..3491db5cad31 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -166,7 +166,7 @@ verify_crtc_state(struct intel_atomic_state *state, const struct intel_crtc_state *sw_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); struct intel_crtc_state *hw_crtc_state; - struct intel_crtc *master_crtc; + struct intel_crtc *primary_crtc; struct intel_encoder *encoder; hw_crtc_state = intel_crtc_state_alloc(crtc); @@ -193,9 +193,9 @@ verify_crtc_state(struct intel_atomic_state *state, "transitional active state does not match atomic hw state (expected %i, found %i)\n", sw_crtc_state->hw.active, crtc->active); - master_crtc = intel_master_crtc(sw_crtc_state); + primary_crtc = intel_primary_crtc(sw_crtc_state); - for_each_encoder_on_crtc(dev, &master_crtc->base, encoder) { + for_each_encoder_on_crtc(dev, &primary_crtc->base, encoder) { enum pipe pipe; bool active; @@ -205,7 +205,7 @@ verify_crtc_state(struct intel_atomic_state *state, encoder->base.base.id, active, sw_crtc_state->hw.active); - I915_STATE_WARN(i915, active && master_crtc->pipe != pipe, + I915_STATE_WARN(i915, active && primary_crtc->pipe != pipe, "Encoder connected to wrong pipe %c\n", pipe_name(pipe)); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 56827340982b..b9687b7692b8 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -761,10 +761,10 @@ void intel_uncompressed_joiner_enable(const struct intel_crtc_state *crtc_state) u32 dss_ctl1_val = 0; if (crtc_state->joiner_pipes && !crtc_state->dsc.compression_enable) { - if (intel_crtc_is_joiner_slave(crtc_state)) - dss_ctl1_val |= UNCOMPRESSED_JOINER_SLAVE; + if (intel_crtc_is_joiner_secondary(crtc_state)) + dss_ctl1_val |= UNCOMPRESSED_JOINER_SECONDARY; else - dss_ctl1_val |= UNCOMPRESSED_JOINER_MASTER; + dss_ctl1_val |= UNCOMPRESSED_JOINER_PRIMARY; intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); } @@ -790,8 +790,8 @@ void intel_dsc_enable(const struct intel_crtc_state *crtc_state) } if (crtc_state->joiner_pipes) { dss_ctl1_val |= BIG_JOINER_ENABLE; - if (!intel_crtc_is_joiner_slave(crtc_state)) - dss_ctl1_val |= MASTER_BIG_JOINER_ENABLE; + if (!intel_crtc_is_joiner_secondary(crtc_state)) + dss_ctl1_val |= PRIMARY_BIG_JOINER_ENABLE; } intel_de_write(dev_priv, dss_ctl1_reg(crtc, crtc_state->cpu_transcoder), dss_ctl1_val); intel_de_write(dev_priv, dss_ctl2_reg(crtc, crtc_state->cpu_transcoder), dss_ctl2_val); diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h index 8b21dc8e26d5..f921ad67b587 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h @@ -32,13 +32,13 @@ _ICL_PIPE_DSS_CTL1_PB, \ _ICL_PIPE_DSS_CTL1_PC) #define BIG_JOINER_ENABLE (1 << 29) -#define MASTER_BIG_JOINER_ENABLE (1 << 28) +#define PRIMARY_BIG_JOINER_ENABLE (1 << 28) #define VGA_CENTERING_ENABLE (1 << 27) #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) -#define UNCOMPRESSED_JOINER_MASTER (1 << 21) -#define UNCOMPRESSED_JOINER_SLAVE (1 << 20) +#define UNCOMPRESSED_JOINER_PRIMARY (1 << 21) +#define UNCOMPRESSED_JOINER_SECONDARY (1 << 20) #define _ICL_PIPE_DSS_CTL2_PB 0x78204 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 -- cgit From 5a5bdc17a2fc8dabfcf630bed84d4fbca0985c3a Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Tue, 11 Jun 2024 17:35:24 +0530 Subject: drm/i915/display: Send vrr vsync params whne vrr is enabled Compute trans vrr vsync params only when either VRR or CMRR is enabled. Fixes: 5922f45329cd ("drm/i915/display: Compute vrr vsync params") Cc: Mitul Golani Cc: Ankit Nautiyal Cc: Suraj Kandpal Cc: Jani Nikula Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Signed-off-by: Suraj Kandpal Link: https://patchwork.freedesktop.org/patch/msgid/20240611120525.148042-1-mitulkumar.ajitkumar.golani@intel.com --- drivers/gpu/drm/i915/display/intel_vrr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 1bef1f6f58ee..eb5b62b54d32 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -232,7 +232,8 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, crtc_state->mode_flags |= I915_MODE_FLAG_VRR; } - if (intel_dp_as_sdp_supported(intel_dp)) { + if (intel_dp_as_sdp_supported(intel_dp) && + crtc_state->vrr.enable) { crtc_state->vrr.vsync_start = (crtc_state->hw.adjusted_mode.crtc_vtotal - crtc_state->hw.adjusted_mode.vsync_start); -- cgit From efde66b9654830170f46667a8f0ddf16fae6dbef Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 11 Jun 2024 18:33:51 +0300 Subject: drm/i915/dp_mst: Fix DSC input BPP computation The branch or sink device decompressing a stream may have a limitation on the input/uncompressed BPP, which is lower than the base line BPP (determined by the sink's EDID). In some cases a stream with an input BPP higher than this limit will be converted automatically by the device decompressing the stream, by truncating the BPP, however in some cases - seen at least in Dell dock's DP->HDMI converters - the decompression will fail. Fix the above by limiting the input BPP correctly. This is done already correctly for SST outputs. Reviewed-by: Luca Coelho Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240611153351.3013235-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index c3c889a5b7ee..6fd0511ab7dd 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -349,6 +349,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, if (max_bpp > sink_max_bpp) max_bpp = sink_max_bpp; + crtc_state->pipe_bpp = max_bpp; + max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector, crtc_state, max_bpp / 3); -- cgit From 1bcbe192e0dc758873003a0059bce9cc27d4bad1 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:13 +0300 Subject: drm/i915/dp_mst: Align TUs to avoid splitting symbols across MTPs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Symbols consisting of multiple (4) TU timeslots may get split across MTPs when using 2 or 1 link lanes. Avoid this, as required by Bspec by aligning the allocated TUs to 2 when using 2 lanes and 4 when using 1 lane. Atm, we also have to align the PBNs used to allocate BW along the MST path, since DRM core keeps track of its own TU value, derived from the PBN and that TU value must match what the driver calculates. On some platforms the alignment is only required on 8b/10b links, a follow-up patch will remove the limitation for those. Bspec: 49266, 68922 Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-2-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 27 +++++++++++++++++++++++---- 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 6fd0511ab7dd..06fa0641f78f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -207,6 +207,7 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, int remote_bw_overhead; int link_bpp_x16; int remote_tu; + fixed20_12 pbn; drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); @@ -237,11 +238,29 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, * crtc_state->dp_m_n.tu), provided that the driver doesn't * enable SSC on the corresponding link. */ - crtc_state->pbn = intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, - link_bpp_x16, - remote_bw_overhead); + pbn.full = dfixed_const(intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock, + link_bpp_x16, + remote_bw_overhead)); + remote_tu = DIV_ROUND_UP(pbn.full, mst_state->pbn_div.full); - remote_tu = DIV_ROUND_UP(dfixed_const(crtc_state->pbn), mst_state->pbn_div.full); + /* + * Aligning the TUs ensures that symbols consisting of multiple + * (4) symbol cycles don't get split between two consecutive + * MTPs, as required by Bspec. + * TODO: remove the alignment restriction for 128b/132b links + * on some platforms, where Bspec allows this. + */ + remote_tu = ALIGN(remote_tu, 4 / crtc_state->lane_count); + + /* + * Also align PBNs accordingly, since MST core will derive its + * own copy of TU from the PBN in drm_dp_atomic_find_time_slots(). + * The above comment about the difference between the PBN + * allocated for the whole path and the TUs allocated for the + * first branch device's link also applies here. + */ + pbn.full = remote_tu * mst_state->pbn_div.full; + crtc_state->pbn = dfixed_trunc(pbn); drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu); crtc_state->dp_m_n.tu = remote_tu; -- cgit From 6a03100200ddaf38ca6719c80c0ce454e990e1a0 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:14 +0300 Subject: drm/i915/dp: Move link train params to a substruct in intel_dp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For clarity move the link training parameters updated during link training based on the pass/fail LT result under a substruct in intel_dp. This prepares for later patches in this patchset adding similar params here. Rename intel_dp_reset_max_link_params() to intel_dp_reset_link_params() to better reflect what state gets reset. v2: Add the parameters to a more generic link substruct. (Jani) Cc: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-3-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 13 ++++++---- drivers/gpu/drm/i915/display/intel_dp.c | 30 +++++++++++----------- 2 files changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 4fa785fd664e..3e493472cf06 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1739,7 +1739,6 @@ struct intel_dp { u8 lane_count; u8 sink_count; bool link_trained; - bool reset_link_params; bool use_max_params; u8 dpcd[DP_RECEIVER_CAP_SIZE]; u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; @@ -1761,10 +1760,14 @@ struct intel_dp { /* intersection of source and sink rates */ int num_common_rates; int common_rates[DP_MAX_SUPPORTED_RATES]; - /* Max lane count for the current link */ - int max_link_lane_count; - /* Max rate for the current link */ - int max_link_rate; + struct { + /* TODO: move the rest of link specific fields to here */ + /* Max lane count for the current link */ + int max_lane_count; + /* Max rate for the current link */ + int max_rate; + } link; + bool reset_link_params; int mso_link_count; int mso_pixel_overlap; /* sink or branch descriptor */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b56752873a68..8541a304a72d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -373,13 +373,13 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) int intel_dp_max_lane_count(struct intel_dp *intel_dp) { - switch (intel_dp->max_link_lane_count) { + switch (intel_dp->link.max_lane_count) { case 1: case 2: case 4: - return intel_dp->max_link_lane_count; + return intel_dp->link.max_lane_count; default: - MISSING_CASE(intel_dp->max_link_lane_count); + MISSING_CASE(intel_dp->link.max_lane_count); return 1; } } @@ -645,7 +645,7 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, * boot-up. */ if (link_rate == 0 || - link_rate > intel_dp->max_link_rate) + link_rate > intel_dp->link.max_rate) return false; if (lane_count == 0 || @@ -706,8 +706,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, "Retrying Link training for eDP with same parameters\n"); return 0; } - intel_dp->max_link_rate = intel_dp_common_rate(intel_dp, index - 1); - intel_dp->max_link_lane_count = lane_count; + intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1); + intel_dp->link.max_lane_count = lane_count; } else if (lane_count > 1) { if (intel_dp_is_edp(intel_dp) && !intel_dp_can_link_train_fallback_for_edp(intel_dp, @@ -717,8 +717,8 @@ int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, "Retrying Link training for eDP with same parameters\n"); return 0; } - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); - intel_dp->max_link_lane_count = lane_count >> 1; + intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.max_lane_count = lane_count >> 1; } else { drm_err(&i915->drm, "Link Training Unsuccessful\n"); return -1; @@ -1383,7 +1383,7 @@ intel_dp_max_link_rate(struct intel_dp *intel_dp) { int len; - len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); + len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate); return intel_dp_common_rate(intel_dp, len - 1); } @@ -3027,10 +3027,10 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, intel_dp->lane_count = lane_count; } -static void intel_dp_reset_max_link_params(struct intel_dp *intel_dp) +static void intel_dp_reset_link_params(struct intel_dp *intel_dp) { - intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); - intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); + intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); } /* Enable backlight PWM and backlight PP control. */ @@ -3365,7 +3365,7 @@ void intel_dp_sync_state(struct intel_encoder *encoder, intel_dp_tunnel_resume(intel_dp, crtc_state, dpcd_updated); if (crtc_state) - intel_dp_reset_max_link_params(intel_dp); + intel_dp_reset_link_params(intel_dp); } bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, @@ -5907,7 +5907,7 @@ intel_dp_detect(struct drm_connector *connector, * supports link training fallback params. */ if (intel_dp->reset_link_params || intel_dp->is_mst) { - intel_dp_reset_max_link_params(intel_dp); + intel_dp_reset_link_params(intel_dp); intel_dp->reset_link_params = false; } @@ -6761,7 +6761,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, intel_dp_set_source_rates(intel_dp); intel_dp_set_common_rates(intel_dp); - intel_dp_reset_max_link_params(intel_dp); + intel_dp_reset_link_params(intel_dp); /* init MST on ports that can support it */ intel_dp_mst_encoder_init(dig_port, -- cgit From dd1eae474e4e93c4076997a749d744fa01396a01 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:15 +0300 Subject: drm/i915/dp: Move link train fallback to intel_dp_link_training.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the functions used to reduce the link parameters during link training to intel_dp_link_training.c . Reviewed-by: Ville Syrjälä Reviewed-by: Manasi Navare Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-4-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 76 +--------------------- drivers/gpu/drm/i915/display/intel_dp.h | 4 +- .../gpu/drm/i915/display/intel_dp_link_training.c | 73 +++++++++++++++++++++ 3 files changed, 77 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8541a304a72d..7386c1050d4f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -330,7 +330,7 @@ static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, intel_dp->num_common_rates, max_rate); } -static int intel_dp_common_rate(struct intel_dp *intel_dp, int index) +int intel_dp_common_rate(struct intel_dp *intel_dp, int index) { if (drm_WARN_ON(&dp_to_i915(intel_dp)->drm, index < 0 || index >= intel_dp->num_common_rates)) @@ -605,7 +605,7 @@ static int intersect_rates(const int *source_rates, int source_len, } /* return index of rate in rates array, or -1 if not found */ -static int intel_dp_rate_index(const int *rates, int len, int rate) +int intel_dp_rate_index(const int *rates, int len, int rate) { int i; @@ -655,78 +655,6 @@ static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, return true; } -static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, - int link_rate, - u8 lane_count) -{ - /* FIXME figure out what we actually want here */ - const struct drm_display_mode *fixed_mode = - intel_panel_preferred_fixed_mode(intel_dp->attached_connector); - int mode_rate, max_rate; - - mode_rate = intel_dp_link_required(fixed_mode->clock, 18); - max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); - if (mode_rate > max_rate) - return false; - - return true; -} - -int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, - int link_rate, u8 lane_count) -{ - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int index; - - /* - * TODO: Enable fallback on MST links once MST link compute can handle - * the fallback params. - */ - if (intel_dp->is_mst) { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); - return -1; - } - - if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with max parameters\n"); - intel_dp->use_max_params = true; - return 0; - } - - index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - link_rate); - if (index > 0) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_common_rate(intel_dp, index - 1), - lane_count)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1); - intel_dp->link.max_lane_count = lane_count; - } else if (lane_count > 1) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_max_common_rate(intel_dp), - lane_count >> 1)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); - intel_dp->link.max_lane_count = lane_count >> 1; - } else { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); - return -1; - } - - return 0; -} - u32 intel_dp_mode_to_fec_clock(u32 mode_clock) { return div_u64(mul_u32_u32(mode_clock, DP_DSC_FEC_OVERHEAD_FACTOR), diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index f14506a63aa0..0d169027067f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -55,8 +55,6 @@ void intel_dp_connector_sync_state(struct intel_connector *connector, const struct intel_crtc_state *crtc_state); void intel_dp_set_link_params(struct intel_dp *intel_dp, int link_rate, int lane_count); -int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, - int link_rate, u8 lane_count); int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask); @@ -107,6 +105,8 @@ int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); int intel_dp_max_common_rate(struct intel_dp *intel_dp); int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); +int intel_dp_common_rate(struct intel_dp *intel_dp, int index); +int intel_dp_rate_index(const int *rates, int len, int rate); void intel_dp_update_sink_caps(struct intel_dp *intel_dp); void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 947575140059..4db293f25689 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -25,6 +25,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" +#include "intel_panel.h" #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ @@ -1091,6 +1092,78 @@ out: return ret; } +static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, + int link_rate, + u8 lane_count) +{ + /* FIXME figure out what we actually want here */ + const struct drm_display_mode *fixed_mode = + intel_panel_preferred_fixed_mode(intel_dp->attached_connector); + int mode_rate, max_rate; + + mode_rate = intel_dp_link_required(fixed_mode->clock, 18); + max_rate = intel_dp_max_link_data_rate(intel_dp, link_rate, lane_count); + if (mode_rate > max_rate) + return false; + + return true; +} + +static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, + int link_rate, u8 lane_count) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + int index; + + /* + * TODO: Enable fallback on MST links once MST link compute can handle + * the fallback params. + */ + if (intel_dp->is_mst) { + drm_err(&i915->drm, "Link Training Unsuccessful\n"); + return -1; + } + + if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with max parameters\n"); + intel_dp->use_max_params = true; + return 0; + } + + index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + link_rate); + if (index > 0) { + if (intel_dp_is_edp(intel_dp) && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, + intel_dp_common_rate(intel_dp, index - 1), + lane_count)) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1); + intel_dp->link.max_lane_count = lane_count; + } else if (lane_count > 1) { + if (intel_dp_is_edp(intel_dp) && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, + intel_dp_max_common_rate(intel_dp), + lane_count >> 1)) { + drm_dbg_kms(&i915->drm, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.max_lane_count = lane_count >> 1; + } else { + drm_err(&i915->drm, "Link Training Unsuccessful\n"); + return -1; + } + + return 0; +} + static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { -- cgit From 9eb4aab86a87e4bd65530dd90a97f45ba13a368a Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:16 +0300 Subject: drm/i915/dp: Sanitize intel_dp_get_link_train_fallback_values() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reduce the indentation in intel_dp_get_link_train_fallback_values() by adding separate helpers to reduce the link rate and lane count. Also simplify things by passing crtc_state to the function. This also prepares for later patches in the patchset adding a limitation on how the link params are reduced. While at it use lt_dbg()/lt_err() for debug/error prints in the function which will also print the connector/encoder prefix and add a debug print about reducing the link parameters. v2: - Align reduce_lane_count()'s error handling flow with reduce_link_rate(). (Ville, Jani) - Use lt_dbg()/lt_err() in the function. Cc: Jani Nikula Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-5-imre.deak@intel.com --- .../gpu/drm/i915/display/intel_dp_link_training.c | 92 +++++++++++++--------- 1 file changed, 56 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 4db293f25689..190372cf76e5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1109,58 +1109,80 @@ static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, return true; } +static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) +{ + int rate_index; + int new_rate; + + rate_index = intel_dp_rate_index(intel_dp->common_rates, + intel_dp->num_common_rates, + current_rate); + + if (rate_index <= 0) + return -1; + + new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); + + return new_rate; +} + +static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) +{ + if (current_lane_count == 1) + return -1; + + return current_lane_count >> 1; +} + static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, - int link_rate, u8 lane_count) + const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - int index; + int new_link_rate; + int new_lane_count; /* * TODO: Enable fallback on MST links once MST link compute can handle * the fallback params. */ if (intel_dp->is_mst) { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); + lt_err(intel_dp, DP_PHY_DPRX, "Link Training Unsuccessful\n"); return -1; } if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with max parameters\n"); + lt_dbg(intel_dp, DP_PHY_DPRX, + "Retrying Link training for eDP with max parameters\n"); intel_dp->use_max_params = true; return 0; } - index = intel_dp_rate_index(intel_dp->common_rates, - intel_dp->num_common_rates, - link_rate); - if (index > 0) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_common_rate(intel_dp, index - 1), - lane_count)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link.max_rate = intel_dp_common_rate(intel_dp, index - 1); - intel_dp->link.max_lane_count = lane_count; - } else if (lane_count > 1) { - if (intel_dp_is_edp(intel_dp) && - !intel_dp_can_link_train_fallback_for_edp(intel_dp, - intel_dp_max_common_rate(intel_dp), - lane_count >> 1)) { - drm_dbg_kms(&i915->drm, - "Retrying Link training for eDP with same parameters\n"); - return 0; - } - intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); - intel_dp->link.max_lane_count = lane_count >> 1; - } else { - drm_err(&i915->drm, "Link Training Unsuccessful\n"); + new_lane_count = crtc_state->lane_count; + new_link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); + if (new_link_rate < 0) { + new_lane_count = reduce_lane_count(intel_dp, crtc_state->lane_count); + new_link_rate = intel_dp_max_common_rate(intel_dp); + } + + if (new_lane_count < 0) { + lt_err(intel_dp, DP_PHY_DPRX, "Link Training Unsuccessful\n"); return -1; } + if (intel_dp_is_edp(intel_dp) && + !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { + lt_dbg(intel_dp, DP_PHY_DPRX, + "Retrying Link training for eDP with same parameters\n"); + return 0; + } + + lt_dbg(intel_dp, DP_PHY_DPRX, + "Reducing link parameters from %dx%d to %dx%d\n", + crtc_state->lane_count, crtc_state->port_clock, + new_lane_count, new_link_rate); + + intel_dp->link.max_rate = new_link_rate; + intel_dp->link.max_lane_count = new_lane_count; + return 0; } @@ -1178,9 +1200,7 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed with HOBL active, not enabling it from now on\n"); intel_dp->hobl_failed = true; - } else if (intel_dp_get_link_train_fallback_values(intel_dp, - crtc_state->port_clock, - crtc_state->lane_count)) { + } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { return; } -- cgit From e5bf189a0f2508ec6e72926728aec35f806dca76 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:17 +0300 Subject: drm/i915: Factor out function to modeset commit a set of pipes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Factor out a function to modeset commit a set of pipes, which a later patch will reuse for DP link retraining. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-6-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_ddi.c | 31 +------------------------ drivers/gpu/drm/i915/display/intel_display.c | 34 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_display.h | 3 +++ 3 files changed, 38 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index ba7d0a706a20..4e033e4066b1 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4453,35 +4453,6 @@ intel_ddi_init_dp_connector(struct intel_digital_port *dig_port) return connector; } -static int modeset_pipe(struct drm_crtc *crtc, - struct drm_modeset_acquire_ctx *ctx) -{ - struct drm_atomic_state *state; - struct drm_crtc_state *crtc_state; - int ret; - - state = drm_atomic_state_alloc(crtc->dev); - if (!state) - return -ENOMEM; - - state->acquire_ctx = ctx; - to_intel_atomic_state(state)->internal = true; - - crtc_state = drm_atomic_get_crtc_state(state, crtc); - if (IS_ERR(crtc_state)) { - ret = PTR_ERR(crtc_state); - goto out; - } - - crtc_state->connectors_changed = true; - - ret = drm_atomic_commit(state); -out: - drm_atomic_state_put(state); - - return ret; -} - static int intel_hdmi_reset_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx) { @@ -4551,7 +4522,7 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, * would be perfectly happy if were to just reconfigure * the SCDC settings on the fly. */ - return modeset_pipe(&crtc->base, ctx); + return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); } static enum intel_hotplug_state diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index 77220254e8b8..7bc4f3de691e 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -5631,6 +5631,40 @@ int intel_modeset_all_pipes_late(struct intel_atomic_state *state, return 0; } +int intel_modeset_commit_pipes(struct drm_i915_private *i915, + u8 pipe_mask, + struct drm_modeset_acquire_ctx *ctx) +{ + struct drm_atomic_state *state; + struct intel_crtc *crtc; + int ret; + + state = drm_atomic_state_alloc(&i915->drm); + if (!state) + return -ENOMEM; + + state->acquire_ctx = ctx; + to_intel_atomic_state(state)->internal = true; + + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) { + struct intel_crtc_state *crtc_state = + intel_atomic_get_crtc_state(state, crtc); + + if (IS_ERR(crtc_state)) { + ret = PTR_ERR(crtc_state); + goto out; + } + + crtc_state->uapi.connectors_changed = true; + } + + ret = drm_atomic_commit(state); +out: + drm_atomic_state_put(state); + + return ret; +} + /* * This implements the workaround described in the "notes" section of the mode * set sequence documentation. When going from no pipes or single pipe to diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h index 48454cf21906..b0cf6ca70952 100644 --- a/drivers/gpu/drm/i915/display/intel_display.h +++ b/drivers/gpu/drm/i915/display/intel_display.h @@ -537,6 +537,9 @@ int intel_modeset_pipes_in_mask_early(struct intel_atomic_state *state, const char *reason, u8 pipe_mask); int intel_modeset_all_pipes_late(struct intel_atomic_state *state, const char *reason); +int intel_modeset_commit_pipes(struct drm_i915_private *i915, + u8 pipe_mask, + struct drm_modeset_acquire_ctx *ctx); void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state, struct intel_power_domain_mask *old_domains); void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc, -- cgit From 4ce7cff538cda112891d9baab703529bfed15d7d Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:18 +0300 Subject: drm/i915/dp: Use a commit modeset for link retraining MST links MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of direct calls to the link train functions, retrain the link via a commit modeset. The direct call means that the output port will be disabled/re-enabled while the rest of the pipeline (transcoder) is active, which doesn't seem to work on MST at least. It leads to underruns and black screen, presumedly because the transcoder is not disabled/re-enabled along the port. Leave switching to a commit modeset on SST for a later patchset, as that seems to work ok currently (though better to using a commit there too, due to the suppressed underruns). v2: Keep reverse line length order for local variables. (Ville) Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-7-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 7386c1050d4f..edd3e0e7085f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5164,6 +5164,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_crtc *crtc; + bool mst_output = false; u8 pipe_mask; int ret; @@ -5195,6 +5196,11 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { + mst_output = true; + break; + } + /* Suppress underruns caused by re-training */ intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); if (crtc_state->has_pch_encoder) @@ -5202,16 +5208,23 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, intel_crtc_pch_transcoder(crtc), false); } + /* TODO: use a modeset for SST as well. */ + if (mst_output) { + ret = intel_modeset_commit_pipes(dev_priv, pipe_mask, ctx); + + if (ret && ret != -EDEADLK) + drm_dbg_kms(&dev_priv->drm, + "[ENCODER:%d:%s] link retraining failed: %pe\n", + encoder->base.base.id, encoder->base.name, + ERR_PTR(ret)); + + return ret; + } + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { const struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state); - /* retrain on the MST master transcoder */ - if (DISPLAY_VER(dev_priv) >= 12 && - intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && - !intel_dp_mst_is_master_trans(crtc_state)) - continue; - intel_dp_check_frl_training(intel_dp); intel_dp_pcon_dsc_configure(intel_dp, crtc_state); intel_dp_start_link_train(intel_dp, crtc_state); -- cgit From 3b3be899fc81d5957c5dba8907263b52d92993ed Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 21:14:28 +0300 Subject: drm/i915/dp: Recheck link state after modeset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Recheck the link state after a passing link training, with a 2 sec delay to account for cases where the link goes bad following the link training and the sink doesn't report this via an HPD IRQ. The delayed work added here will be also used by a later patch after a failed link training to try to retrain the link with unchanged link params before reducing the link params. v2: Don't flush an uninitialized delayed work (on HDMI-only DDI ports). v3: - Move the helpers to a new intel_encoder.c file, rename them accordingly. (Ville) - Add the work to intel_encoder instead of intel_digital_port. - Call the encoder specific link check function via an encoder hook. - Flush the link check work during encoder destroy from intel_dp_encoder_flush_work(). - Flush the link check work during encoder suspend as well. v4: Call intel_encoder_link_check_init() with a valid encoder pointer. Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610181428.2955658-1-imre.deak@intel.com --- drivers/gpu/drm/i915/Makefile | 1 + drivers/gpu/drm/i915/display/g4x_dp.c | 13 ++++++++ drivers/gpu/drm/i915/display/intel_ddi.c | 19 +++++++++++ drivers/gpu/drm/i915/display/intel_display_types.h | 5 +++ drivers/gpu/drm/i915/display/intel_dp.c | 21 ++++++++++-- drivers/gpu/drm/i915/display/intel_dp.h | 1 + .../gpu/drm/i915/display/intel_dp_link_training.c | 13 ++++++-- drivers/gpu/drm/i915/display/intel_encoder.c | 39 ++++++++++++++++++++++ drivers/gpu/drm/i915/display/intel_encoder.h | 16 +++++++++ drivers/gpu/drm/xe/Makefile | 1 + 10 files changed, 124 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/i915/display/intel_encoder.c create mode 100644 drivers/gpu/drm/i915/display/intel_encoder.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 06e6486c07b5..23840e53acba 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -329,6 +329,7 @@ i915-y += \ display/intel_dsi_dcs_backlight.o \ display/intel_dsi_vbt.o \ display/intel_dvo.o \ + display/intel_encoder.o \ display/intel_gmbus.o \ display/intel_hdmi.o \ display/intel_lspcon.o \ diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 40fee8380a81..4d279cadf7e2 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -20,6 +20,7 @@ #include "intel_dp_aux.h" #include "intel_dp_link_training.h" #include "intel_dpio_phy.h" +#include "intel_encoder.h" #include "intel_fifo_underrun.h" #include "intel_hdmi.h" #include "intel_hotplug.h" @@ -1239,6 +1240,15 @@ static bool ilk_digital_port_connected(struct intel_encoder *encoder) return intel_de_read(dev_priv, DEISR) & bit; } +static void g4x_dp_suspend_complete(struct intel_encoder *encoder) +{ + /* + * TODO: Move this to intel_dp_encoder_suspend(), + * once modeset locking around that is removed. + */ + intel_encoder_link_check_flush_work(encoder); +} + static void intel_dp_encoder_destroy(struct drm_encoder *encoder) { intel_dp_encoder_flush_work(encoder); @@ -1325,6 +1335,8 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, "DP %c", port_name(port))) goto err_encoder_init; + intel_encoder_link_check_init(intel_encoder, intel_dp_link_check); + intel_encoder->hotplug = intel_dp_hotplug; intel_encoder->compute_config = intel_dp_compute_config; intel_encoder->get_hw_state = intel_dp_get_hw_state; @@ -1333,6 +1345,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv, intel_encoder->initial_fastset_check = intel_dp_initial_fastset_check; intel_encoder->update_pipe = intel_backlight_update; intel_encoder->suspend = intel_dp_encoder_suspend; + intel_encoder->suspend_complete = g4x_dp_suspend_complete; intel_encoder->shutdown = intel_dp_encoder_shutdown; if (IS_CHERRYVIEW(dev_priv)) { intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 4e033e4066b1..823c66ad8988 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -57,6 +57,7 @@ #include "intel_dp_tunnel.h" #include "intel_dpio_phy.h" #include "intel_dsi.h" +#include "intel_encoder.h" #include "intel_fdi.h" #include "intel_fifo_underrun.h" #include "intel_gmbus.h" @@ -4525,6 +4526,17 @@ static int intel_hdmi_reset_link(struct intel_encoder *encoder, return intel_modeset_commit_pipes(dev_priv, BIT(crtc->pipe), ctx); } +static void intel_ddi_link_check(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + + /* TODO: Move checking the HDMI link state here as well. */ + drm_WARN_ON(&i915->drm, !dig_port->dp.attached_connector); + + intel_dp_link_check(encoder); +} + static enum intel_hotplug_state intel_ddi_hotplug(struct intel_encoder *encoder, struct intel_connector *connector) @@ -4768,6 +4780,11 @@ static void intel_ddi_tc_encoder_suspend_complete(struct intel_encoder *encoder) struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + /* + * TODO: Move this to intel_dp_encoder_suspend(), + * once modeset locking around that is removed. + */ + intel_encoder_link_check_flush_work(encoder); intel_tc_port_suspend(dig_port); } @@ -4958,6 +4975,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, "DDI %c/PHY %c", port_name(port), phy_name(phy)); } + intel_encoder_link_check_init(encoder, intel_ddi_link_check); + mutex_init(&dig_port->hdcp_mutex); dig_port->num_hdcp_streams = 0; diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 3e493472cf06..1af3d48a7b86 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -161,6 +161,11 @@ struct intel_encoder { enum port port; u16 cloneable; u8 pipe_mask; + + /* Check and recover a bad link state. */ + struct delayed_work link_check_work; + void (*link_check)(struct intel_encoder *encoder); + enum intel_hotplug_state (*hotplug)(struct intel_encoder *encoder, struct intel_connector *connector); enum intel_output_type (*compute_output_type)(struct intel_encoder *, diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index edd3e0e7085f..0833302baabc 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -69,6 +69,7 @@ #include "intel_dpio_phy.h" #include "intel_dpll.h" #include "intel_drrs.h" +#include "intel_encoder.h" #include "intel_fifo_underrun.h" #include "intel_hdcp.h" #include "intel_hdmi.h" @@ -76,6 +77,7 @@ #include "intel_hotplug_irq.h" #include "intel_lspcon.h" #include "intel_lvds.h" +#include "intel_modeset_lock.h" #include "intel_panel.h" #include "intel_pch_display.h" #include "intel_pps.h" @@ -5248,6 +5250,18 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, return 0; } +void intel_dp_link_check(struct intel_encoder *encoder) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + struct drm_modeset_acquire_ctx ctx; + int ret; + + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) + ret = intel_dp_retrain_link(encoder, &ctx); + + drm_WARN_ON(&i915->drm, ret); +} + static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask) @@ -6014,11 +6028,14 @@ void intel_dp_connector_sync_state(struct intel_connector *connector, } } -void intel_dp_encoder_flush_work(struct drm_encoder *encoder) +void intel_dp_encoder_flush_work(struct drm_encoder *_encoder) { - struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); + struct intel_encoder *encoder = to_intel_encoder(_encoder); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct intel_dp *intel_dp = &dig_port->dp; + intel_encoder_link_check_flush_work(encoder); + intel_dp_mst_encoder_cleanup(dig_port); intel_dp_tunnel_destroy(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 0d169027067f..79193af55518 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -60,6 +60,7 @@ int intel_dp_get_active_pipes(struct intel_dp *intel_dp, u8 *pipe_mask); int intel_dp_retrain_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx); +void intel_dp_link_check(struct intel_encoder *encoder); void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 190372cf76e5..1164255cf5f2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -25,6 +25,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dp_link_training.h" +#include "intel_encoder.h" #include "intel_panel.h" #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " @@ -1464,6 +1465,8 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &dig_port->base; bool passed; /* @@ -1483,6 +1486,11 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, else passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); + if (passed) { + intel_encoder_link_check_queue_work(encoder, 2000); + return; + } + /* * Ignore the link failure in CI * @@ -1495,13 +1503,12 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, * For test cases which rely on the link training or processing of HPDs * ignore_long_hpd flag can unset from the testcase. */ - if (!passed && i915->display.hotplug.ignore_long_hpd) { + if (i915->display.hotplug.ignore_long_hpd) { lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n"); return; } - if (!passed) - intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); + intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); } void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_encoder.c b/drivers/gpu/drm/i915/display/intel_encoder.c new file mode 100644 index 000000000000..dee55f56960f --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_encoder.c @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2024 Intel Corporation + */ + +#include + +#include "i915_drv.h" + +#include "intel_display_types.h" +#include "intel_encoder.h" + +static void intel_encoder_link_check_work_fn(struct work_struct *work) +{ + struct intel_encoder *encoder = + container_of(work, typeof(*encoder), link_check_work.work); + + encoder->link_check(encoder); +} + +void intel_encoder_link_check_init(struct intel_encoder *encoder, + void (*callback)(struct intel_encoder *encoder)) +{ + INIT_DELAYED_WORK(&encoder->link_check_work, intel_encoder_link_check_work_fn); + encoder->link_check = callback; +} + +void intel_encoder_link_check_flush_work(struct intel_encoder *encoder) +{ + cancel_delayed_work_sync(&encoder->link_check_work); +} + +void intel_encoder_link_check_queue_work(struct intel_encoder *encoder, int delay_ms) +{ + struct drm_i915_private *i915 = to_i915(encoder->base.dev); + + mod_delayed_work(i915->unordered_wq, + &encoder->link_check_work, msecs_to_jiffies(delay_ms)); +} diff --git a/drivers/gpu/drm/i915/display/intel_encoder.h b/drivers/gpu/drm/i915/display/intel_encoder.h new file mode 100644 index 000000000000..2cda054e2b15 --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_encoder.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2024 Intel Corporation + */ + +#ifndef __INTEL_ENCODER_H__ +#define __INTEL_ENCODER_H__ + +struct intel_encoder; + +void intel_encoder_link_check_init(struct intel_encoder *encoder, + void (*callback)(struct intel_encoder *encoder)); +void intel_encoder_link_check_queue_work(struct intel_encoder *encoder, int delay_ms); +void intel_encoder_link_check_flush_work(struct intel_encoder *encoder); + +#endif /* __INTEL_ENCODER_H__ */ diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 0132397a1a31..1e5d88d6a152 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -258,6 +258,7 @@ xe-$(CONFIG_DRM_XE_DISPLAY) += \ i915-display/intel_dsi.o \ i915-display/intel_dsi_dcs_backlight.o \ i915-display/intel_dsi_vbt.o \ + i915-display/intel_encoder.o \ i915-display/intel_fb.o \ i915-display/intel_fbc.o \ i915-display/intel_fdi.o \ -- cgit From 5bd3e7ea8854601866bac507b3cdda5fd3a29c15 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:20 +0300 Subject: drm/i915/dp: Reduce link params only after retrying with unchanged params MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Try to maintain the current link parameters by retrying the link training with unchanged link parameters before reducing these parameters (sending an uevent to userspace to retrain the link instead). Signed-off-by: Imre Deak Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-9-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++ drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ drivers/gpu/drm/i915/display/intel_dp_link_training.c | 8 ++++++++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 1af3d48a7b86..a50310f412dd 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1771,6 +1771,8 @@ struct intel_dp { int max_lane_count; /* Max rate for the current link */ int max_rate; + /* Sequential link training failures after a passing LT */ + int seq_train_failures; } link; bool reset_link_params; int mso_link_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0833302baabc..5f54b0a9f597 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2961,6 +2961,7 @@ static void intel_dp_reset_link_params(struct intel_dp *intel_dp) { intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.seq_train_failures = 0; } /* Enable backlight PWM and backlight PP control. */ @@ -5075,6 +5076,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) intel_dp->lane_count)) return false; + if (intel_dp->link.seq_train_failures) + return true; + /* Retrain if link not ok */ return !intel_dp_link_ok(intel_dp, link_status); } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 1164255cf5f2..8caf740e642f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1487,10 +1487,13 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); if (passed) { + intel_dp->link.seq_train_failures = 0; intel_encoder_link_check_queue_work(encoder, 2000); return; } + intel_dp->link.seq_train_failures++; + /* * Ignore the link failure in CI * @@ -1508,6 +1511,11 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, return; } + if (intel_dp->link.seq_train_failures < 2) { + intel_encoder_link_check_queue_work(encoder, 0); + return; + } + intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); } -- cgit From 182c6be08b81b367b98634c40870fc06cd4eca42 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:21 +0300 Subject: drm/i915/dp: Pass atomic state to link training function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The next patch adds sending a modeset-retry uevent after a link training failure to all MST connectors on link. This requires the atomic state, so pass it to intel_dp_start_link_train(). In case of SST where retraining still happens by calling this function directly instead of a modeset commit the atomic state is not available and NULL is passed instead. This is ok, since in this case the encoder's only DP connector is available from intel_dp->attached_connector not requiring the atomic state. v2: Add NOTE that the atomic state may not be valid for SST links and assert that it's valid for MST links. (Ville) Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-10-imre.deak@intel.com --- drivers/gpu/drm/i915/display/g4x_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_ddi.c | 6 +++--- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 11 ++++++++++- drivers/gpu/drm/i915/display/intel_dp_link_training.h | 4 +++- 5 files changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 4d279cadf7e2..a0406a71dbde 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -707,7 +707,7 @@ static void intel_enable_dp(struct intel_atomic_state *state, intel_dp_configure_protocol_converter(intel_dp, pipe_config); intel_dp_check_frl_training(intel_dp); intel_dp_pcon_dsc_configure(intel_dp, pipe_config); - intel_dp_start_link_train(intel_dp, pipe_config); + intel_dp_start_link_train(state, intel_dp, pipe_config); intel_dp_stop_link_train(intel_dp, pipe_config); } diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 823c66ad8988..958effb273ff 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -2596,7 +2596,7 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state, * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) * (timeout after 800 us) */ - intel_dp_start_link_train(intel_dp, crtc_state); + intel_dp_start_link_train(state, intel_dp, crtc_state); /* 6.n Set DP_TP_CTL link training to Normal */ if (!is_trans_port_sync_mode(crtc_state)) @@ -2738,7 +2738,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state, * Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent) * (timeout after 800 us) */ - intel_dp_start_link_train(intel_dp, crtc_state); + intel_dp_start_link_train(state, intel_dp, crtc_state); /* 7.k Set DP_TP_CTL link training to Normal */ if (!is_trans_port_sync_mode(crtc_state)) @@ -2805,7 +2805,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state, to_intel_connector(conn_state->connector), crtc_state); intel_dp_sink_set_fec_ready(intel_dp, crtc_state, true); - intel_dp_start_link_train(intel_dp, crtc_state); + intel_dp_start_link_train(state, intel_dp, crtc_state); if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) && !is_trans_port_sync_mode(crtc_state)) intel_dp_stop_link_train(intel_dp, crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 5f54b0a9f597..d41c00f720a1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5233,7 +5233,7 @@ int intel_dp_retrain_link(struct intel_encoder *encoder, intel_dp_check_frl_training(intel_dp); intel_dp_pcon_dsc_configure(intel_dp, crtc_state); - intel_dp_start_link_train(intel_dp, crtc_state); + intel_dp_start_link_train(NULL, intel_dp, crtc_state); intel_dp_stop_link_train(intel_dp, crtc_state); break; } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 8caf740e642f..04629a4341ee 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1453,6 +1453,7 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, /** * intel_dp_start_link_train - start link training + * @state: Atomic state * @intel_dp: DP struct * @crtc_state: state for CRTC attached to the encoder * @@ -1460,8 +1461,11 @@ intel_dp_128b132b_link_train(struct intel_dp *intel_dp, * retraining with reduced link rate/lane parameters if the link training * fails. * After calling this function intel_dp_stop_link_train() must be called. + * + * NOTE: @state is only valid for MST links and can be %NULL for SST. */ -void intel_dp_start_link_train(struct intel_dp *intel_dp, +void intel_dp_start_link_train(struct intel_atomic_state *state, + struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -1475,6 +1479,11 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp, */ int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); + if (drm_WARN_ON(&i915->drm, + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && + !state)) + return; + if (lttpr_count < 0) /* Still continue with enabling the port and link training. */ lttpr_count = 0; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index 19836a8a4f90..f65823096033 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -8,6 +8,7 @@ #include +struct intel_atomic_state; struct intel_crtc_state; struct intel_dp; @@ -25,7 +26,8 @@ void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, void intel_dp_set_signal_levels(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state, enum drm_dp_phy dp_phy); -void intel_dp_start_link_train(struct intel_dp *intel_dp, +void intel_dp_start_link_train(struct intel_atomic_state *state, + struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); void intel_dp_stop_link_train(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); -- cgit From c9a5f6019c6ce9245b8fd11a66d405f26e6cfa34 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:22 +0300 Subject: drm/i915/dp: Send a link training modeset-retry uevent to all MST connectors MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Send a modeset-retry uevent to all connectors in the same MST topology after a link training failure and reduction of the link parameters. This matches the way the same uevent is sent after a DP tunnel BW allocation failure. v2: Add NOTE that the atomic state may not be valid for SST links and assert that it's valid for MST links. (Ville) Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-11-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 7 ++++++- drivers/gpu/drm/i915/display/intel_dp.h | 1 - drivers/gpu/drm/i915/display/intel_dp_link_training.c | 16 ++++++++++++---- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d41c00f720a1..afc8719cf5f5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2801,7 +2801,7 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder, intel_dp_is_uhbr(pipe_config); } -void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) +static void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) { struct drm_i915_private *i915 = to_i915(connector->base.dev); @@ -2810,6 +2810,7 @@ void intel_dp_queue_modeset_retry_work(struct intel_connector *connector) drm_connector_put(&connector->base); } +/* NOTE: @state is only valid for MST links and can be %NULL for SST. */ void intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, struct intel_encoder *encoder, @@ -2818,6 +2819,7 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, struct intel_connector *connector; struct intel_digital_connector_state *conn_state; struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i; if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) { @@ -2826,6 +2828,9 @@ intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, return; } + if (drm_WARN_ON(&i915->drm, !state)) + return; + for_each_new_intel_connector_in_state(state, connector, conn_state, i) { if (!conn_state->base.crtc) continue; diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 79193af55518..ebacc94b6c9c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -44,7 +44,6 @@ bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state); int intel_dp_min_bpp(enum intel_output_format output_format); void intel_dp_init_modeset_retry_work(struct intel_connector *connector); -void intel_dp_queue_modeset_retry_work(struct intel_connector *connector); void intel_dp_queue_modeset_retry_for_link(struct intel_atomic_state *state, struct intel_encoder *encoder, diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 04629a4341ee..bb8680ac7f4d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1187,10 +1187,13 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, return 0; } -static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, +/* NOTE: @state is only valid for MST links and can be %NULL for SST. */ +static void intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, + struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { - struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); @@ -1205,8 +1208,13 @@ static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, return; } + if (drm_WARN_ON(&i915->drm, + intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && + !state)) + return; + /* Schedule a Hotplug Uevent to userspace to start modeset */ - intel_dp_queue_modeset_retry_work(intel_connector); + intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); } /* Perform the link training on all LTTPRs and the DPRX on a link. */ @@ -1525,7 +1533,7 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, return; } - intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); + intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state); } void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, -- cgit From b22b4dd96e5250c84d58de94513b4c6cd0825ce7 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:23 +0300 Subject: drm/i915/dp: Use check link state work in the hotplug handler MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simplify things by retraining a DP link if a bad link is detected in the hotplug handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-12-imre.deak@intel.com --- drivers/gpu/drm/i915/display/g4x_dp.c | 20 +------------------- drivers/gpu/drm/i915/display/intel_ddi.c | 11 +++++------ drivers/gpu/drm/i915/display/intel_dp.c | 14 ++++++++++++++ drivers/gpu/drm/i915/display/intel_dp.h | 1 + 4 files changed, 21 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index a0406a71dbde..a8e746a0f670 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -1160,9 +1160,7 @@ intel_dp_hotplug(struct intel_encoder *encoder, struct intel_connector *connector) { struct intel_dp *intel_dp = enc_to_intel_dp(encoder); - struct drm_modeset_acquire_ctx ctx; enum intel_hotplug_state state; - int ret; if (intel_dp->compliance.test_active && intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) { @@ -1173,23 +1171,7 @@ intel_dp_hotplug(struct intel_encoder *encoder, state = intel_encoder_hotplug(encoder, connector); - drm_modeset_acquire_init(&ctx, 0); - - for (;;) { - ret = intel_dp_retrain_link(encoder, &ctx); - - if (ret == -EDEADLK) { - drm_modeset_backoff(&ctx); - continue; - } - - break; - } - - drm_modeset_drop_locks(&ctx); - drm_modeset_acquire_fini(&ctx); - drm_WARN(encoder->base.dev, ret, - "Acquiring modeset locks failed with %i\n", ret); + intel_dp_check_link_state(intel_dp); /* * Keeping it consistent with intel_ddi_hotplug() and diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 958effb273ff..bb13a3ca8c7c 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -4558,14 +4558,13 @@ intel_ddi_hotplug(struct intel_encoder *encoder, state = intel_encoder_hotplug(encoder, connector); if (!intel_tc_port_link_reset(dig_port)) { - intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) { - if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) + if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA) { + intel_modeset_lock_ctx_retry(&ctx, NULL, 0, ret) ret = intel_hdmi_reset_link(encoder, &ctx); - else - ret = intel_dp_retrain_link(encoder, &ctx); + drm_WARN_ON(encoder->base.dev, ret); + } else { + intel_dp_check_link_state(intel_dp); } - - drm_WARN_ON(encoder->base.dev, ret); } /* diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index afc8719cf5f5..fd6069ea8f2a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5271,6 +5271,20 @@ void intel_dp_link_check(struct intel_encoder *encoder) drm_WARN_ON(&i915->drm, ret); } +void intel_dp_check_link_state(struct intel_dp *intel_dp) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &dig_port->base; + + if (!intel_dp_is_connected(intel_dp)) + return; + + if (!intel_dp_needs_link_retrain(intel_dp)) + return; + + intel_encoder_link_check_queue_work(encoder, 0); +} + static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask) diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index ebacc94b6c9c..a283641c1a9c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -60,6 +60,7 @@ int intel_dp_get_active_pipes(struct intel_dp *intel_dp, int intel_dp_retrain_link(struct intel_encoder *encoder, struct drm_modeset_acquire_ctx *ctx); void intel_dp_link_check(struct intel_encoder *encoder); +void intel_dp_check_link_state(struct intel_dp *intel_dp); void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); -- cgit From ff68f68c0ec5e4ad6ee3216ee53d12dd48d06b93 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:24 +0300 Subject: drm/i915/dp: Use check link state work in the detect handler MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simplify things by retraining a DP link if a bad link is detected in the connector detect handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. v2: Add TODO: comment to remove the detect-time link state check. (Ville) Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-13-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 15 ++++++++------- drivers/gpu/drm/i915/display/intel_dp.h | 2 -- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index fd6069ea8f2a..06ebf3267038 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5169,8 +5169,8 @@ static bool intel_dp_is_connected(struct intel_dp *intel_dp) intel_dp->is_mst; } -int intel_dp_retrain_link(struct intel_encoder *encoder, - struct drm_modeset_acquire_ctx *ctx) +static int intel_dp_retrain_link(struct intel_encoder *encoder, + struct drm_modeset_acquire_ctx *ctx) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_dp *intel_dp = enc_to_intel_dp(encoder); @@ -5904,12 +5904,13 @@ intel_dp_detect(struct drm_connector *connector, /* * Some external monitors do not signal loss of link synchronization * with an IRQ_HPD, so force a link status check. + * + * TODO: this probably became redundant, so remove it: the link state + * is rechecked/recovered now after modesets, where the loss of + * synchronization tends to occur. */ - if (!intel_dp_is_edp(intel_dp)) { - ret = intel_dp_retrain_link(encoder, ctx); - if (ret) - return ret; - } + if (!intel_dp_is_edp(intel_dp)) + intel_dp_check_link_state(intel_dp); /* * Clearing NACK and defer counts to get their exact values diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index a283641c1a9c..0dca688fac6b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -57,8 +57,6 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, int intel_dp_get_active_pipes(struct intel_dp *intel_dp, struct drm_modeset_acquire_ctx *ctx, u8 *pipe_mask); -int intel_dp_retrain_link(struct intel_encoder *encoder, - struct drm_modeset_acquire_ctx *ctx); void intel_dp_link_check(struct intel_encoder *encoder); void intel_dp_check_link_state(struct intel_dp *intel_dp); void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode); -- cgit From 34aca703d4fdb1ec289a514d0eed1a53d46f5ffd Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:25 +0300 Subject: drm/i915/dp: Use check link state work in the HPD IRQ handler MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simplify things by retraining a DP link if a bad link is detected in the HPD IRQ handler from the encoder's check link state work, similarly to how this is done after a modeset link training failure. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-14-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 06ebf3267038..a6204e469b3f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -4974,6 +4974,8 @@ static bool intel_dp_check_mst_status(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_encoder *encoder = &dig_port->base; bool link_ok = true; bool reprobe_needed = false; @@ -5019,7 +5021,10 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); } - return link_ok && !reprobe_needed; + if (!link_ok) + intel_encoder_link_check_queue_work(encoder, 0); + + return !reprobe_needed; } static void @@ -5495,9 +5500,7 @@ intel_dp_short_pulse(struct intel_dp *intel_dp) /* Handle CEC interrupts, if any */ drm_dp_cec_irq(&intel_dp->aux); - /* defer to the hotplug work for link retraining if needed */ - if (intel_dp_needs_link_retrain(intel_dp)) - return false; + intel_dp_check_link_state(intel_dp); intel_psr_short_pulse(intel_dp); -- cgit From 81c9642b2a03c375e46442147234016578f12181 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:26 +0300 Subject: drm/i915/dp: Disable link retraining after the last fallback step MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit After a link training failure if the link parameters can't be further reduced, there is no point in trying to retrain the link in the driver. This avoids excessive retrain attempts after detecting a bad link, for instance while handling MST HPD IRQs, which is likely redundant as the link training failed already twice with the same minimum link parameters. Userspace can still try to retrain the link with these parameters via a modeset. While at it make the error message more accurate. v2: Move converting the error to a debug message to the relevant follow-up patch. (Ville) Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-15-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ .../gpu/drm/i915/display/intel_dp_link_training.c | 21 +++++++++++++-------- 3 files changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index a50310f412dd..50f8b329c0c8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1771,6 +1771,7 @@ struct intel_dp { int max_lane_count; /* Max rate for the current link */ int max_rate; + bool retrain_disabled; /* Sequential link training failures after a passing LT */ int seq_train_failures; } link; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a6204e469b3f..500090674c7a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2966,6 +2966,7 @@ static void intel_dp_reset_link_params(struct intel_dp *intel_dp) { intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); + intel_dp->link.retrain_disabled = false; intel_dp->link.seq_train_failures = 0; } @@ -5086,6 +5087,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) intel_dp->lane_count)) return false; + if (intel_dp->link.retrain_disabled) + return false; + if (intel_dp->link.seq_train_failures) return true; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index bb8680ac7f4d..e106a9e6ea3b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1164,10 +1164,8 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, new_link_rate = intel_dp_max_common_rate(intel_dp); } - if (new_lane_count < 0) { - lt_err(intel_dp, DP_PHY_DPRX, "Link Training Unsuccessful\n"); + if (new_lane_count < 0) return -1; - } if (intel_dp_is_edp(intel_dp) && !intel_dp_can_link_train_fallback_for_edp(intel_dp, new_link_rate, new_lane_count)) { @@ -1188,7 +1186,7 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, } /* NOTE: @state is only valid for MST links and can be %NULL for SST. */ -static void intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, +static bool intel_dp_schedule_fallback_link_training(struct intel_atomic_state *state, struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state) { @@ -1197,7 +1195,7 @@ static void intel_dp_schedule_fallback_link_training(struct intel_atomic_state * if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); - return; + return true; } if (intel_dp->hobl_active) { @@ -1205,16 +1203,18 @@ static void intel_dp_schedule_fallback_link_training(struct intel_atomic_state * "Link Training failed with HOBL active, not enabling it from now on\n"); intel_dp->hobl_failed = true; } else if (intel_dp_get_link_train_fallback_values(intel_dp, crtc_state)) { - return; + return false; } if (drm_WARN_ON(&i915->drm, intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && !state)) - return; + return false; /* Schedule a Hotplug Uevent to userspace to start modeset */ intel_dp_queue_modeset_retry_for_link(state, encoder, crtc_state); + + return true; } /* Perform the link training on all LTTPRs and the DPRX on a link. */ @@ -1533,7 +1533,12 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, return; } - intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state); + if (intel_dp_schedule_fallback_link_training(state, intel_dp, crtc_state)) + return; + + intel_dp->link.retrain_disabled = true; + + lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); } void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, -- cgit From e3e70d08409086ada2c864373d9d8b8ef9a55936 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:27 +0300 Subject: drm/i915/dp_mst: Reset intel_dp->link_trained during disabling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reset the flag indicating an active link after disabling an MST link, similarly to how this is done for SST outputs. This avoids trying to retrain an MST link while its disabled. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-16-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 06fa0641f78f..e92a10c1f34e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -983,6 +983,9 @@ static void intel_mst_disable_dp(struct intel_atomic_state *state, drm_dbg_kms(&i915->drm, "active links %d\n", intel_dp->active_mst_links); + if (intel_dp->active_mst_links == 1) + intel_dp->link_trained = false; + intel_hdcp_disable(intel_mst->connector); intel_dp_sink_disable_decompression(state, connector, old_crtc_state); -- cgit From 73afc1e2fd1d3b3f086a4ba1714c8d1ecc40d4f9 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:28 +0300 Subject: drm/i915/dp_mst: Enable link training fallback for MST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reduce the link parameters after a link training failure for MST outputs, similarly to how this is done for SST. For now allow the reduction only by staying in the 8b/10b vs. 128b/132b mode. Enabling the mode switch is left for a follow-up patchset, after taking measures ensuring that the mode switch happens properly. In particular a rediscovery of the whole MST topology may be required for such a switch, see the References below. Link: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10970 Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-17-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 6 +----- drivers/gpu/drm/i915/display/intel_dp_link_training.c | 13 ++++--------- 2 files changed, 5 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 500090674c7a..795498382254 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5887,11 +5887,7 @@ intel_dp_detect(struct drm_connector *connector, intel_dp_mst_configure(intel_dp); - /* - * TODO: Reset link params when switching to MST mode, until MST - * supports link training fallback params. - */ - if (intel_dp->reset_link_params || intel_dp->is_mst) { + if (intel_dp->reset_link_params) { intel_dp_reset_link_params(intel_dp); intel_dp->reset_link_params = false; } diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index e106a9e6ea3b..af6536936550 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1124,6 +1124,10 @@ static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) new_rate = intel_dp_common_rate(intel_dp, rate_index - 1); + /* TODO: Make switching from UHBR to non-UHBR rates work. */ + if (drm_dp_is_uhbr_rate(current_rate) != drm_dp_is_uhbr_rate(new_rate)) + return -1; + return new_rate; } @@ -1141,15 +1145,6 @@ static int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, int new_link_rate; int new_lane_count; - /* - * TODO: Enable fallback on MST links once MST link compute can handle - * the fallback params. - */ - if (intel_dp->is_mst) { - lt_err(intel_dp, DP_PHY_DPRX, "Link Training Unsuccessful\n"); - return -1; - } - if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { lt_dbg(intel_dp, DP_PHY_DPRX, "Retrying Link training for eDP with max parameters\n"); -- cgit From c3c90de3a7dec171c671ffcc99eb5cdfe5e88c23 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:29 +0300 Subject: drm/i915/dp: Add debugfs entries to force the link rate/lane count MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add connector debugfs entries to force the link rate/lane count to be used by a link training afterwards. These settings will be clamped to the supported, i.e. the source's and sink's common rate/lane count. After forcing the link rate/lane count reset the link training parameters and for a non-auto setting disable reducing the link parameters via the fallback logic. The former one can be used after testing link training failure scenarios - via debugfs entries added later - to reset the reduced link parameters after the test. v2: - Add the entries from intel_dp_link_training.c (Jani) - Rename the entries to i915_dp_set_link_rate/lane_count. v3: (Ville) - Rename the entries/struct fields to force_link_rate/lane_count. - Lock connection_mutex only for the required intel_dp state. Cc: Jani Nikula Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-18-imre.deak@intel.com --- .../gpu/drm/i915/display/intel_display_debugfs.c | 2 + drivers/gpu/drm/i915/display/intel_display_types.h | 2 + drivers/gpu/drm/i915/display/intel_dp.c | 57 ++++- drivers/gpu/drm/i915/display/intel_dp.h | 2 + .../gpu/drm/i915/display/intel_dp_link_training.c | 229 +++++++++++++++++++++ .../gpu/drm/i915/display/intel_dp_link_training.h | 4 + 6 files changed, 289 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index 959e894e27d3..91757fed9c6d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -24,6 +24,7 @@ #include "intel_display_types.h" #include "intel_dmc.h" #include "intel_dp.h" +#include "intel_dp_link_training.h" #include "intel_dp_mst.h" #include "intel_drrs.h" #include "intel_fbc.h" @@ -1517,6 +1518,7 @@ void intel_connector_debugfs_add(struct intel_connector *connector) intel_pps_connector_debugfs_add(connector); intel_psr_connector_debugfs_add(connector); intel_alpm_lobf_debugfs_add(connector); + intel_dp_link_training_debugfs_add(connector); if (connector_type == DRM_MODE_CONNECTOR_DisplayPort || connector_type == DRM_MODE_CONNECTOR_HDMIA || diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 50f8b329c0c8..8e9245161e4d 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1771,6 +1771,8 @@ struct intel_dp { int max_lane_count; /* Max rate for the current link */ int max_rate; + int force_lane_count; + int force_rate; bool retrain_disabled; /* Sequential link training failures after a passing LT */ int seq_train_failures; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 795498382254..1fa6f50213e9 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -347,7 +347,7 @@ int intel_dp_max_common_rate(struct intel_dp *intel_dp) return intel_dp_common_rate(intel_dp, intel_dp->num_common_rates - 1); } -static int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) +int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port) { int vbt_max_lanes = intel_bios_dp_max_lane_count(dig_port->base.devdata); int max_lanes = dig_port->max_lanes; @@ -373,19 +373,39 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) return min3(source_max, sink_max, lane_max); } +static int forced_lane_count(struct intel_dp *intel_dp) +{ + return clamp(intel_dp->link.force_lane_count, 1, intel_dp_max_common_lane_count(intel_dp)); +} + int intel_dp_max_lane_count(struct intel_dp *intel_dp) { - switch (intel_dp->link.max_lane_count) { + int lane_count; + + if (intel_dp->link.force_lane_count) + lane_count = forced_lane_count(intel_dp); + else + lane_count = intel_dp->link.max_lane_count; + + switch (lane_count) { case 1: case 2: case 4: - return intel_dp->link.max_lane_count; + return lane_count; default: - MISSING_CASE(intel_dp->link.max_lane_count); + MISSING_CASE(lane_count); return 1; } } +static int intel_dp_min_lane_count(struct intel_dp *intel_dp) +{ + if (intel_dp->link.force_lane_count) + return forced_lane_count(intel_dp); + + return 1; +} + /* * The required data bandwidth for a mode with given pixel clock and bpp. This * is the required net bandwidth independent of the data bandwidth efficiency. @@ -1308,16 +1328,38 @@ static void intel_dp_print_rates(struct intel_dp *intel_dp) drm_dbg_kms(&i915->drm, "common rates: %s\n", str); } +static int forced_link_rate(struct intel_dp *intel_dp) +{ + int len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.force_rate); + + if (len == 0) + return intel_dp_common_rate(intel_dp, 0); + + return intel_dp_common_rate(intel_dp, len - 1); +} + int intel_dp_max_link_rate(struct intel_dp *intel_dp) { int len; + if (intel_dp->link.force_rate) + return forced_link_rate(intel_dp); + len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->link.max_rate); return intel_dp_common_rate(intel_dp, len - 1); } +static int +intel_dp_min_link_rate(struct intel_dp *intel_dp) +{ + if (intel_dp->link.force_rate) + return forced_link_rate(intel_dp); + + return intel_dp_common_rate(intel_dp, 0); +} + int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -2287,13 +2329,14 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp, bool dsc, struct link_config_limits *limits) { - limits->min_rate = intel_dp_common_rate(intel_dp, 0); + limits->min_rate = intel_dp_min_link_rate(intel_dp); limits->max_rate = intel_dp_max_link_rate(intel_dp); /* FIXME 128b/132b SST support missing */ limits->max_rate = min(limits->max_rate, 810000); + limits->min_rate = min(limits->min_rate, limits->max_rate); - limits->min_lane_count = 1; + limits->min_lane_count = intel_dp_min_lane_count(intel_dp); limits->max_lane_count = intel_dp_max_lane_count(intel_dp); limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format); @@ -2962,7 +3005,7 @@ void intel_dp_set_link_params(struct intel_dp *intel_dp, intel_dp->lane_count = lane_count; } -static void intel_dp_reset_link_params(struct intel_dp *intel_dp) +void intel_dp_reset_link_params(struct intel_dp *intel_dp) { intel_dp->link.max_lane_count = intel_dp_max_common_lane_count(intel_dp); intel_dp->link.max_rate = intel_dp_max_common_rate(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 0dca688fac6b..32da3bdba9f6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -98,6 +98,7 @@ void intel_edp_backlight_off(const struct drm_connector_state *conn_state); void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp); void intel_dp_mst_suspend(struct drm_i915_private *dev_priv); void intel_dp_mst_resume(struct drm_i915_private *dev_priv); +int intel_dp_max_source_lane_count(struct intel_digital_port *dig_port); int intel_dp_max_link_rate(struct intel_dp *intel_dp); int intel_dp_max_lane_count(struct intel_dp *intel_dp); int intel_dp_config_required_rate(const struct intel_crtc_state *crtc_state); @@ -107,6 +108,7 @@ int intel_dp_max_common_lane_count(struct intel_dp *intel_dp); int intel_dp_common_rate(struct intel_dp *intel_dp, int index); int intel_dp_rate_index(const int *rates, int len, int rate); void intel_dp_update_sink_caps(struct intel_dp *intel_dp); +void intel_dp_reset_link_params(struct intel_dp *intel_dp); void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, u8 *link_bw, u8 *rate_select); diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index af6536936550..8a2ebee7a842 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1115,6 +1115,9 @@ static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) int rate_index; int new_rate; + if (intel_dp->link.force_rate) + return -1; + rate_index = intel_dp_rate_index(intel_dp->common_rates, intel_dp->num_common_rates, current_rate); @@ -1133,6 +1136,9 @@ static int reduce_link_rate(struct intel_dp *intel_dp, int current_rate) static int reduce_lane_count(struct intel_dp *intel_dp, int current_lane_count) { + if (intel_dp->link.force_lane_count) + return -1; + if (current_lane_count == 1) return -1; @@ -1555,3 +1561,226 @@ void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); } + +static struct intel_dp *intel_connector_to_intel_dp(struct intel_connector *connector) +{ + if (connector->mst_port) + return connector->mst_port; + else + return enc_to_intel_dp(intel_attached_encoder(connector)); +} + +static int i915_dp_force_link_rate_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int current_rate = -1; + int force_rate; + int err; + int i; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + if (intel_dp->link_trained) + current_rate = intel_dp->link_rate; + force_rate = intel_dp->link.force_rate; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + seq_printf(m, "%sauto%s", + force_rate == 0 ? "[" : "", + force_rate == 0 ? "]" : ""); + + for (i = 0; i < intel_dp->num_source_rates; i++) + seq_printf(m, " %s%d%s%s", + intel_dp->source_rates[i] == force_rate ? "[" : "", + intel_dp->source_rates[i], + intel_dp->source_rates[i] == current_rate ? "*" : "", + intel_dp->source_rates[i] == force_rate ? "]" : ""); + + seq_putc(m, '\n'); + + return 0; +} + +static int parse_link_rate(struct intel_dp *intel_dp, const char __user *ubuf, size_t len) +{ + char *kbuf; + const char *p; + int rate; + int ret = 0; + + kbuf = memdup_user_nul(ubuf, len); + if (IS_ERR(kbuf)) + return PTR_ERR(kbuf); + + p = strim(kbuf); + + if (!strcmp(p, "auto")) { + rate = 0; + } else { + ret = kstrtoint(p, 0, &rate); + if (ret < 0) + goto out_free; + + if (intel_dp_rate_index(intel_dp->source_rates, + intel_dp->num_source_rates, + rate) < 0) + ret = -EINVAL; + } + +out_free: + kfree(kbuf); + + return ret < 0 ? ret : rate; +} + +static ssize_t i915_dp_force_link_rate_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int rate; + int err; + + rate = parse_link_rate(intel_dp, ubuf, len); + if (rate < 0) + return rate; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp_reset_link_params(intel_dp); + intel_dp->link.force_rate = rate; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + *offp += len; + + return len; +} +DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_link_rate); + +static int i915_dp_force_lane_count_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int current_lane_count = -1; + int force_lane_count; + int err; + int i; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + if (intel_dp->link_trained) + current_lane_count = intel_dp->lane_count; + force_lane_count = intel_dp->link.force_lane_count; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + seq_printf(m, "%sauto%s", + force_lane_count == 0 ? "[" : "", + force_lane_count == 0 ? "]" : ""); + + for (i = 1; i <= 4; i <<= 1) + seq_printf(m, " %s%d%s%s", + i == force_lane_count ? "[" : "", + i, + i == current_lane_count ? "*" : "", + i == force_lane_count ? "]" : ""); + + seq_putc(m, '\n'); + + return 0; +} + +static int parse_lane_count(const char __user *ubuf, size_t len) +{ + char *kbuf; + const char *p; + int lane_count; + int ret = 0; + + kbuf = memdup_user_nul(ubuf, len); + if (IS_ERR(kbuf)) + return PTR_ERR(kbuf); + + p = strim(kbuf); + + if (!strcmp(p, "auto")) { + lane_count = 0; + } else { + ret = kstrtoint(p, 0, &lane_count); + if (ret < 0) + goto out_free; + + switch (lane_count) { + case 1: + case 2: + case 4: + break; + default: + ret = -EINVAL; + } + } + +out_free: + kfree(kbuf); + + return ret < 0 ? ret : lane_count; +} + +static ssize_t i915_dp_force_lane_count_write(struct file *file, + const char __user *ubuf, + size_t len, loff_t *offp) +{ + struct seq_file *m = file->private_data; + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int lane_count; + int err; + + lane_count = parse_lane_count(ubuf, len); + if (lane_count < 0) + return lane_count; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp_reset_link_params(intel_dp); + intel_dp->link.force_lane_count = lane_count; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + *offp += len; + + return len; +} +DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_lane_count); + +void intel_dp_link_training_debugfs_add(struct intel_connector *connector) +{ + struct dentry *root = connector->base.debugfs_entry; + + if (connector->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort && + connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) + return; + + debugfs_create_file("i915_dp_force_link_rate", 0644, root, + connector, &i915_dp_force_link_rate_fops); + + debugfs_create_file("i915_dp_force_lane_count", 0644, root, + connector, &i915_dp_force_lane_count_fops); +} diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.h b/drivers/gpu/drm/i915/display/intel_dp_link_training.h index f65823096033..42e7fc6cb171 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.h +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.h @@ -9,6 +9,7 @@ #include struct intel_atomic_state; +struct intel_connector; struct intel_crtc_state; struct intel_dp; @@ -44,4 +45,7 @@ static inline u8 intel_dp_training_pattern_symbol(u8 pattern) void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, const struct intel_crtc_state *crtc_state); + +void intel_dp_link_training_debugfs_add(struct intel_connector *connector); + #endif /* __INTEL_DP_LINK_TRAINING_H__ */ -- cgit From fe089d5b9ace6f31e27c1bfa1245d592443aefb7 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:30 +0300 Subject: drm/i915/dp: Add debugfs entries to get the max link rate/lane count MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add connector debugfs entries to get the maximum link rate and lane count. v2: Lock connection_mutex only for the required intel_dp state. (Ville) Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-19-imre.deak@intel.com --- .../gpu/drm/i915/display/intel_dp_link_training.c | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 8a2ebee7a842..184206067fa6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1770,6 +1770,44 @@ static ssize_t i915_dp_force_lane_count_write(struct file *file, } DEFINE_SHOW_STORE_ATTRIBUTE(i915_dp_force_lane_count); +static int i915_dp_max_link_rate_show(void *data, u64 *val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + *val = intel_dp->link.max_rate; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_link_rate_fops, i915_dp_max_link_rate_show, NULL, "%llu\n"); + +static int i915_dp_max_lane_count_show(void *data, u64 *val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + *val = intel_dp->link.max_lane_count; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n"); + void intel_dp_link_training_debugfs_add(struct intel_connector *connector) { struct dentry *root = connector->base.debugfs_entry; @@ -1783,4 +1821,10 @@ void intel_dp_link_training_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_force_lane_count", 0644, root, connector, &i915_dp_force_lane_count_fops); + + debugfs_create_file("i915_dp_max_link_rate", 0444, root, + connector, &i915_dp_max_link_rate_fops); + + debugfs_create_file("i915_dp_max_lane_count", 0444, root, + connector, &i915_dp_max_lane_count_fops); } -- cgit From 0e0af7e052ddd3e5a237977d681ab244459fa828 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:31 +0300 Subject: drm/i915/dp: Add debugfs entry to force link training failure MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a connector debugfs entry to force a failure during the following 1-2 link training. The entry will auto-reset after the specified link training events are complete. v2: Add the entry from intel_dp_link_training.c (Jani) v3: Lock connection_mutex only for the required intel_dp state. (Ville) Cc: Jani Nikula Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-20-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + .../gpu/drm/i915/display/intel_dp_link_training.c | 55 +++++++++++++++++++++- 2 files changed, 54 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8e9245161e4d..9ae22e8dd2e2 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1776,6 +1776,7 @@ struct intel_dp { bool retrain_disabled; /* Sequential link training failures after a passing LT */ int seq_train_failures; + int force_train_failure; } link; bool reset_link_params; int mso_link_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 184206067fa6..a6ea92b54c2f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1504,7 +1504,10 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, else passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); - if (passed) { + if (intel_dp->link.force_train_failure) { + intel_dp->link.force_train_failure--; + lt_dbg(intel_dp, DP_PHY_DPRX, "Forcing link training failure\n"); + } else if (passed) { intel_dp->link.seq_train_failures = 0; intel_encoder_link_check_queue_work(encoder, 2000); return; @@ -1539,7 +1542,10 @@ void intel_dp_start_link_train(struct intel_atomic_state *state, intel_dp->link.retrain_disabled = true; - lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); + if (!passed) + lt_err(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after failure\n"); + else + lt_dbg(intel_dp, DP_PHY_DPRX, "Can't reduce link training parameters after forced failure\n"); } void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, @@ -1808,6 +1814,48 @@ static int i915_dp_max_lane_count_show(void *data, u64 *val) } DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_max_lane_count_fops, i915_dp_max_lane_count_show, NULL, "%llu\n"); +static int i915_dp_force_link_training_failure_show(void *data, u64 *val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + *val = intel_dp->link.force_train_failure; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} + +static int i915_dp_force_link_training_failure_write(void *data, u64 val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int err; + + if (val > 2) + return -EINVAL; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp->link.force_train_failure = val; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, + i915_dp_force_link_training_failure_show, + i915_dp_force_link_training_failure_write, "%llu\n"); + void intel_dp_link_training_debugfs_add(struct intel_connector *connector) { struct dentry *root = connector->base.debugfs_entry; @@ -1827,4 +1875,7 @@ void intel_dp_link_training_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_max_lane_count", 0444, root, connector, &i915_dp_max_lane_count_fops); + + debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, + connector, &i915_dp_force_link_training_failure_fops); } -- cgit From 09f08c6ccc04ff7530e0c4166c3ec4bf3565bcee Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:32 +0300 Subject: drm/i915/dp: Add debugfs entry to force link retrain MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a connector debugfs entry to force retrain an active link. This can be used to test both custom link parameters (previously forced via the force_link_rate/lane_count entries) or link train failure scenarios (previously forced via the force_link_training_failure entry). The entry will autoreset after the link-retrain is complete. v2: Add the entry from intel_dp_link_training.c (Jani) v3: Lock connection_mutex only for the required intel_dp state. (Ville) Cc: Jani Nikula Cc: Ville Syrjälä Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-21-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 18 ++++++--- .../gpu/drm/i915/display/intel_dp_link_training.c | 45 ++++++++++++++++++++++ 3 files changed, 59 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 9ae22e8dd2e2..02ebe6f3e765 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1777,6 +1777,7 @@ struct intel_dp { /* Sequential link training failures after a passing LT */ int seq_train_failures; int force_train_failure; + bool force_retrain; } link; bool reset_link_params; int mso_link_count; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 1fa6f50213e9..9a9bb0f5b7fe 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -5065,7 +5065,7 @@ intel_dp_check_mst_status(struct intel_dp *intel_dp) drm_dp_mst_hpd_irq_send_new_request(&intel_dp->mst_mgr); } - if (!link_ok) + if (!link_ok || intel_dp->link.force_retrain) intel_encoder_link_check_queue_work(encoder, 0); return !reprobe_needed; @@ -5114,6 +5114,9 @@ intel_dp_needs_link_retrain(struct intel_dp *intel_dp) if (intel_psr_enabled(intel_dp)) return false; + if (intel_dp->link.force_retrain) + return true; + if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, link_status) < 0) return false; @@ -5252,8 +5255,9 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder, if (!intel_dp_needs_link_retrain(intel_dp)) return 0; - drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", - encoder->base.base.id, encoder->base.name); + drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link (forced %s)\n", + encoder->base.base.id, encoder->base.name, + str_yes_no(intel_dp->link.force_retrain)); for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { const struct intel_crtc_state *crtc_state = @@ -5281,7 +5285,7 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder, encoder->base.base.id, encoder->base.name, ERR_PTR(ret)); - return ret; + goto out; } for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, pipe_mask) { @@ -5308,7 +5312,11 @@ static int intel_dp_retrain_link(struct intel_encoder *encoder, intel_crtc_pch_transcoder(crtc), true); } - return 0; +out: + if (ret != -EDEADLK) + intel_dp->link.force_retrain = false; + + return ret; } void intel_dp_link_check(struct intel_encoder *encoder) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index a6ea92b54c2f..4da550d6e0ff 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -26,6 +26,7 @@ #include "intel_dp.h" #include "intel_dp_link_training.h" #include "intel_encoder.h" +#include "intel_hotplug.h" #include "intel_panel.h" #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " @@ -1856,6 +1857,47 @@ DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_training_failure_fops, i915_dp_force_link_training_failure_show, i915_dp_force_link_training_failure_write, "%llu\n"); +static int i915_dp_force_link_retrain_show(void *data, u64 *val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + *val = intel_dp->link.force_retrain; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} + +static int i915_dp_force_link_retrain_write(void *data, u64 val) +{ + struct intel_connector *connector = to_intel_connector(data); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + intel_dp->link.force_retrain = val; + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, + i915_dp_force_link_retrain_show, + i915_dp_force_link_retrain_write, "%llu\n"); + void intel_dp_link_training_debugfs_add(struct intel_connector *connector) { struct dentry *root = connector->base.debugfs_entry; @@ -1878,4 +1920,7 @@ void intel_dp_link_training_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_force_link_training_failure", 0644, root, connector, &i915_dp_force_link_training_failure_fops); + + debugfs_create_file("i915_dp_force_link_retrain", 0644, root, + connector, &i915_dp_force_link_retrain_fops); } -- cgit From d6bbb6e581743fa9f6a31346b3a6d147e8cd2560 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Mon, 10 Jun 2024 19:49:33 +0300 Subject: drm/i915/dp: Add debugfs entry to get the link retrain disabled state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a connector debugfs entry showing if link retraining is disabled. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20240610164933.2947366-22-imre.deak@intel.com --- .../gpu/drm/i915/display/intel_dp_link_training.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c index 4da550d6e0ff..1bc4ef84ff3b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c +++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c @@ -1898,6 +1898,25 @@ DEFINE_DEBUGFS_ATTRIBUTE(i915_dp_force_link_retrain_fops, i915_dp_force_link_retrain_show, i915_dp_force_link_retrain_write, "%llu\n"); +static int i915_dp_link_retrain_disabled_show(struct seq_file *m, void *data) +{ + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + struct intel_dp *intel_dp = intel_connector_to_intel_dp(connector); + int err; + + err = drm_modeset_lock_single_interruptible(&i915->drm.mode_config.connection_mutex); + if (err) + return err; + + seq_printf(m, "%s\n", str_yes_no(intel_dp->link.retrain_disabled)); + + drm_modeset_unlock(&i915->drm.mode_config.connection_mutex); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(i915_dp_link_retrain_disabled); + void intel_dp_link_training_debugfs_add(struct intel_connector *connector) { struct dentry *root = connector->base.debugfs_entry; @@ -1923,4 +1942,7 @@ void intel_dp_link_training_debugfs_add(struct intel_connector *connector) debugfs_create_file("i915_dp_force_link_retrain", 0644, root, connector, &i915_dp_force_link_retrain_fops); + + debugfs_create_file("i915_dp_link_retrain_disabled", 0444, root, + connector, &i915_dp_link_retrain_disabled_fops); } -- cgit From 084a55b264a4918227d4eb52c792350791f2d26c Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 7 Jun 2024 18:25:35 +0300 Subject: drm/i915/gvt: remove the unused end parameter from calc_index() All callers of calc_index() pass 0 for the end parameter. Remove it. Cc: Zhenyu Wang Cc: Zhi Wang Cc: intel-gvt-dev@lists.freedesktop.org Reviewed-by: Zhi Wang Link: https://patchwork.freedesktop.org/patch/msgid/aaa24a5cbcf876d3b95e0f5f6594f972a860b6bc.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/handlers.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 073edabf24a5..5bb5eaea77d2 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -881,12 +881,11 @@ static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, #define INVALID_INDEX (~0U) static unsigned int calc_index(unsigned int offset, unsigned int start, - unsigned int next, unsigned int end, i915_reg_t i915_end) + unsigned int next, i915_reg_t _end) { + u32 end = i915_mmio_reg_offset(_end); unsigned int range = next - start; - if (!end) - end = i915_mmio_reg_offset(i915_end); if (offset < start || offset > end) return INVALID_INDEX; offset -= start; @@ -894,13 +893,13 @@ static unsigned int calc_index(unsigned int offset, unsigned int start, } #define FDI_RX_CTL_TO_PIPE(offset) \ - calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C)) + calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, FDI_RX_CTL(PIPE_C)) #define FDI_TX_CTL_TO_PIPE(offset) \ - calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C)) + calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, FDI_TX_CTL(PIPE_C)) #define FDI_RX_IMR_TO_PIPE(offset) \ - calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C)) + calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, FDI_RX_IMR(PIPE_C)) static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) @@ -944,7 +943,7 @@ static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, } #define DP_TP_CTL_TO_PORT(offset) \ - calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E)) + calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, DP_TP_CTL(PORT_E)) static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) @@ -1008,7 +1007,7 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, } #define DSPSURF_TO_PIPE(offset) \ - calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(dev_priv, PIPE_C)) + calc_index(offset, _DSPASURF, _DSPBSURF, DSPSURF(dev_priv, PIPE_C)) static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) @@ -1031,7 +1030,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, } #define SPRSURF_TO_PIPE(offset) \ - calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C)) + calc_index(offset, _SPRA_SURF, _SPRB_SURF, SPRSURF(PIPE_C)) static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) -- cgit From 51715cdc98596d92f4c6cde89946991ef0e5021e Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 7 Jun 2024 18:25:36 +0300 Subject: drm/i915/gvt: use proper i915_reg_t for calc_index() parameters In order to be able to use the proper register macros instead of the underscore prefixed ones, pass i915_reg_t for the calc_index() parameters. Side note: DSPSURF is really about planes, not pipes. Fixed stride doesn't work for plane C for CHV (but that's okay for gvt). This doesn't support planes beyond C either. But all that is unrelated to the change at hand. Cc: Zhenyu Wang Cc: Zhi Wang Cc: intel-gvt-dev@lists.freedesktop.org Reviewed-by: Zhi Wang Link: https://patchwork.freedesktop.org/patch/msgid/282b19c44d83c96b52c261cfc7218e7e54076cba.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/handlers.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 5bb5eaea77d2..446df8116114 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -880,9 +880,11 @@ static int check_fdi_rx_train_status(struct intel_vgpu *vgpu, #define INVALID_INDEX (~0U) -static unsigned int calc_index(unsigned int offset, unsigned int start, - unsigned int next, i915_reg_t _end) +static unsigned int calc_index(unsigned int offset, i915_reg_t _start, + i915_reg_t _next, i915_reg_t _end) { + u32 start = i915_mmio_reg_offset(_start); + u32 next = i915_mmio_reg_offset(_next); u32 end = i915_mmio_reg_offset(_end); unsigned int range = next - start; @@ -893,13 +895,13 @@ static unsigned int calc_index(unsigned int offset, unsigned int start, } #define FDI_RX_CTL_TO_PIPE(offset) \ - calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, FDI_RX_CTL(PIPE_C)) + calc_index(offset, FDI_RX_CTL(PIPE_A), FDI_RX_CTL(PIPE_B), FDI_RX_CTL(PIPE_C)) #define FDI_TX_CTL_TO_PIPE(offset) \ - calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, FDI_TX_CTL(PIPE_C)) + calc_index(offset, FDI_TX_CTL(PIPE_A), FDI_TX_CTL(PIPE_B), FDI_TX_CTL(PIPE_C)) #define FDI_RX_IMR_TO_PIPE(offset) \ - calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, FDI_RX_IMR(PIPE_C)) + calc_index(offset, FDI_RX_IMR(PIPE_A), FDI_RX_IMR(PIPE_B), FDI_RX_IMR(PIPE_C)) static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) @@ -943,7 +945,7 @@ static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu, } #define DP_TP_CTL_TO_PORT(offset) \ - calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, DP_TP_CTL(PORT_E)) + calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E)) static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) @@ -1007,7 +1009,7 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, } #define DSPSURF_TO_PIPE(offset) \ - calc_index(offset, _DSPASURF, _DSPBSURF, DSPSURF(dev_priv, PIPE_C)) + calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C)) static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) @@ -1030,7 +1032,7 @@ static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, } #define SPRSURF_TO_PIPE(offset) \ - calc_index(offset, _SPRA_SURF, _SPRB_SURF, SPRSURF(PIPE_C)) + calc_index(offset, SPRSURF(PIPE_A), SPRSURF(PIPE_B), SPRSURF(PIPE_C)) static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) -- cgit From 200f178d7ca0b5dac1080a0e9e9bc02a8b65d17d Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 7 Jun 2024 18:25:37 +0300 Subject: drm/i915/gvt: rename range variable to stride Range is a bit odd name for what really is stride. Rename. Switch to u32 while at it. Cc: Zhenyu Wang Cc: Zhi Wang Cc: intel-gvt-dev@lists.freedesktop.org Reviewed-by: Zhi Wang Link: https://patchwork.freedesktop.org/patch/msgid/8b8d4acee15da07845ed1779d6856d5c3f50a132.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/handlers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 446df8116114..084d62b3e6e8 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -886,12 +886,12 @@ static unsigned int calc_index(unsigned int offset, i915_reg_t _start, u32 start = i915_mmio_reg_offset(_start); u32 next = i915_mmio_reg_offset(_next); u32 end = i915_mmio_reg_offset(_end); - unsigned int range = next - start; + u32 stride = next - start; if (offset < start || offset > end) return INVALID_INDEX; offset -= start; - return offset / range; + return offset / stride; } #define FDI_RX_CTL_TO_PIPE(offset) \ -- cgit From b1e6ae07c72ed93f1017e1821155212f33f465fe Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 7 Jun 2024 18:25:38 +0300 Subject: drm/i915/gvt: do not use implict dev_priv in DSPSURF_TO_PIPE() Do not rely on having dev_priv local variable, pass it to the macro. Cc: Zhenyu Wang Cc: Zhi Wang Cc: intel-gvt-dev@lists.freedesktop.org Reviewed-by: Zhi Wang Link: https://patchwork.freedesktop.org/patch/msgid/2ff78ebd0dc84178f5feacee7ef2a6cb4132b9ae.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gvt/handlers.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 084d62b3e6e8..9753a9cff33c 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -1008,14 +1008,14 @@ static int south_chicken2_mmio_write(struct intel_vgpu *vgpu, return 0; } -#define DSPSURF_TO_PIPE(offset) \ +#define DSPSURF_TO_PIPE(dev_priv, offset) \ calc_index(offset, DSPSURF(dev_priv, PIPE_A), DSPSURF(dev_priv, PIPE_B), DSPSURF(dev_priv, PIPE_C)) static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, void *p_data, unsigned int bytes) { struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915; - u32 pipe = DSPSURF_TO_PIPE(offset); + u32 pipe = DSPSURF_TO_PIPE(dev_priv, offset); int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY); write_vreg(vgpu, offset, p_data, bytes); -- cgit From d6bbc4da2149f9dbf78c9f0fb742dea67cfa8057 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 7 Jun 2024 18:25:39 +0300 Subject: drm/i915: relocate some DSPCNTR reg bit definitions Some plane B/C specific bits were left next to the unused _DSPBCNTR macro. Move them next to the DSPCNTR() macro. Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/85409fbe5073797c0dc17df43eeb25abe9ff889f.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_plane_regs.h | 2 ++ drivers/gpu/drm/i915/i915_reg.h | 2 -- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h index a2ba55fa2b30..5d7ba824f354 100644 --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h @@ -38,10 +38,12 @@ #define DISP_STEREO_POLARITY_SECOND REG_BIT(18) #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */ #define DISP_ROTATE_180 REG_BIT(15) /* i965+ */ +#define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) /* pre-g4x plane B */ #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */ #define DISP_TILED REG_BIT(10) /* i965+ */ #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */ #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */ +#define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) /* pre-g4x plane B/C */ #define _DSPAADDR 0x70184 /* pre-i965 */ #define DSPADDR(dev_priv, plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index df58cf38e144..4b05ce58b3a4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2126,8 +2126,6 @@ /* Display B control */ #define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) -#define DISP_ALPHA_TRANS_ENABLE REG_BIT(15) -#define DISP_SPRITE_ABOVE_OVERLAY REG_BIT(0) #define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) #define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) #define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) -- cgit From f8324128fdf8aeb174b4bda689121a3d6c48c860 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 7 Jun 2024 18:25:40 +0300 Subject: drm/i915: remove unused pipe/plane B register macros None of these are used. The parametrized register macros all depend on the pipe/plane A offset macros alone. Remove the unused ones. v2: Rebase Reviewed-by: Rodrigo Vivi Link: https://patchwork.freedesktop.org/patch/msgid/16d278bea466a69cdce94fd83d98dd15ce1a8c89.1717773890.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg.h | 21 --------------------- 1 file changed, 21 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 4b05ce58b3a4..8e4478194d11 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2114,27 +2114,6 @@ #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) -/* Pipe B */ -#define _PIPEBDSL (DISPLAY_MMIO_BASE(dev_priv) + 0x71000) -#define _TRANSBCONF (DISPLAY_MMIO_BASE(dev_priv) + 0x71008) -#define _PIPEBSTAT (DISPLAY_MMIO_BASE(dev_priv) + 0x71024) -#define _PIPEBFRAMEHIGH 0x71040 -#define _PIPEBFRAMEPIXEL 0x71044 -#define _PIPEB_FRMCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71040) -#define _PIPEB_FLIPCOUNT_G4X (DISPLAY_MMIO_BASE(dev_priv) + 0x71044) - - -/* Display B control */ -#define _DSPBCNTR (DISPLAY_MMIO_BASE(dev_priv) + 0x71180) -#define _DSPBADDR (DISPLAY_MMIO_BASE(dev_priv) + 0x71184) -#define _DSPBSTRIDE (DISPLAY_MMIO_BASE(dev_priv) + 0x71188) -#define _DSPBPOS (DISPLAY_MMIO_BASE(dev_priv) + 0x7118C) -#define _DSPBSIZE (DISPLAY_MMIO_BASE(dev_priv) + 0x71190) -#define _DSPBSURF (DISPLAY_MMIO_BASE(dev_priv) + 0x7119C) -#define _DSPBTILEOFF (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) -#define _DSPBOFFSET (DISPLAY_MMIO_BASE(dev_priv) + 0x711A4) -#define _DSPBSURFLIVE (DISPLAY_MMIO_BASE(dev_priv) + 0x711AC) - /* ICL DSI 0 and 1 */ #define _PIPEDSI0CONF 0x7b008 #define _PIPEDSI1CONF 0x7b808 -- cgit From 7997a9e4f89f124c700986baf220b5421fe1158b Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 17 May 2024 17:53:50 +0300 Subject: drm/i915: Drop redundant dsc_decompression_aux check MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If we have no dsc_decompression_aux (only possible on MST) then we won't have the dsc_dpcd caps either. So checking both is not needed. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240517145356.26103-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9a9bb0f5b7fe..09a06fb232f3 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1424,7 +1424,6 @@ static bool intel_dp_supports_dsc(const struct intel_connector *connector, return false; return intel_dsc_source_support(crtc_state) && - connector->dp.dsc_decompression_aux && drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd); } -- cgit From 35859d448a2097d9197aecc61b55f158cba0a17d Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 17 May 2024 17:53:51 +0300 Subject: drm/i915: Extract intel_dp_has_dsc() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Extract a helper to check whether the source+sink combo supports DSC. That basic check is needed both during mode validation and compute config. We'll also need to add extra checks to both places, so having a single place for it is nicer. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240517145356.26103-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 09a06fb232f3..a1792da3b6c7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1171,6 +1171,19 @@ bool intel_dp_need_joiner(struct intel_dp *intel_dp, connector->force_bigjoiner_enable; } +static bool intel_dp_has_dsc(const struct intel_connector *connector) +{ + struct drm_i915_private *i915 = to_i915(connector->base.dev); + + if (!HAS_DSC(i915)) + return false; + + if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) + return false; + + return true; +} + static enum drm_mode_status intel_dp_mode_valid(struct drm_connector *_connector, struct drm_display_mode *mode) @@ -1225,8 +1238,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, mode_rate = intel_dp_link_required(target_clock, intel_dp_mode_min_output_bpp(connector, mode)); - if (HAS_DSC(dev_priv) && - drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) { + if (intel_dp_has_dsc(connector)) { enum intel_output_format sink_format, output_format; int pipe_bpp; -- cgit From 0c0543ff0a8d8f5312d66d2b863032acdf6d77d0 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 17 May 2024 17:53:52 +0300 Subject: drm/i915: Handle MST in intel_dp_has_dsc() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Utilize intel_dp_has_dsc() for MST as well. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240517145356.26103-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp.c | 5 ++++- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +-- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a1792da3b6c7..4364af21d5d8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1171,13 +1171,16 @@ bool intel_dp_need_joiner(struct intel_dp *intel_dp, connector->force_bigjoiner_enable; } -static bool intel_dp_has_dsc(const struct intel_connector *connector) +bool intel_dp_has_dsc(const struct intel_connector *connector) { struct drm_i915_private *i915 = to_i915(connector->base.dev); if (!HAS_DSC(i915)) return false; + if (connector->mst_port && !HAS_DSC_MST(i915)) + return false; + if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) return false; diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 32da3bdba9f6..212fe041018c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -87,6 +87,7 @@ bool intel_dp_has_hdmi_sink(struct intel_dp *intel_dp); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_as_sdp_supported(struct intel_dp *intel_dp); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); +bool intel_dp_has_dsc(const struct intel_connector *connector); int intel_dp_link_symbol_size(int rate); int intel_dp_link_symbol_clock(int rate); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e92a10c1f34e..a9a07dcf3ab4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1459,8 +1459,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, return 0; } - if (HAS_DSC_MST(dev_priv) && - drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) { + if (intel_dp_has_dsc(intel_connector)) { /* * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked -- cgit From 8de66736bcd87b89fff489a6fa2ad2312fc0de0d Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 17 May 2024 17:53:53 +0300 Subject: drm/i915: Use intel_dp_has_dsc() during .compute_config() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reuse intel_dp_has_dsc() during .compute_config() instead of repeating some of the checks again by hand. We'll be adding more checks to intel_dp_has_dsc() and this will make sure we cover both .mode_valid() and .compute_config() with them. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240517145356.26103-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 4364af21d5d8..b19ffd160bf8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1435,11 +1435,13 @@ bool intel_dp_supports_fec(struct intel_dp *intel_dp, static bool intel_dp_supports_dsc(const struct intel_connector *connector, const struct intel_crtc_state *crtc_state) { + if (!intel_dp_has_dsc(connector)) + return false; + if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable) return false; - return intel_dsc_source_support(crtc_state) && - drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd); + return intel_dsc_source_support(crtc_state); } static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, -- cgit From cf235914f0e75eaa791ecfede2010fb701184bba Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 17 May 2024 17:53:54 +0300 Subject: drm/i915: Reuse intel_dp_supports_dsc() for MST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel_dp_supports_dsc() now works for MST as well, reuse it. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240517145356.26103-6-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dp.h | 3 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 16 ++-------------- 3 files changed, 7 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index b19ffd160bf8..926b0beed666 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1432,8 +1432,8 @@ bool intel_dp_supports_fec(struct intel_dp *intel_dp, drm_dp_sink_supports_fec(connector->dp.fec_capability); } -static bool intel_dp_supports_dsc(const struct intel_connector *connector, - const struct intel_crtc_state *crtc_state) +bool intel_dp_supports_dsc(const struct intel_connector *connector, + const struct intel_crtc_state *crtc_state) { if (!intel_dp_has_dsc(connector)) return false; diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 212fe041018c..a0f990a95ecc 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -171,6 +171,9 @@ bool intel_dp_supports_fec(struct intel_dp *intel_dp, const struct intel_connector *connector, const struct intel_crtc_state *pipe_config); +bool intel_dp_supports_dsc(const struct intel_connector *connector, + const struct intel_crtc_state *crtc_state); + u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp); void intel_ddi_update_pipe(struct intel_atomic_state *state, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index a9a07dcf3ab4..e1f09108f19a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -421,18 +421,6 @@ static int intel_dp_mst_update_slots(struct intel_encoder *encoder, return 0; } -static bool -intel_dp_mst_dsc_source_support(const struct intel_crtc_state *crtc_state) -{ - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - - /* - * FIXME: Enabling DSC on ICL results in blank screen and FIFO pipe / - * transcoder underruns, re-enable DSC after fixing this issue. - */ - return DISPLAY_VER(i915) >= 12 && intel_dsc_source_support(crtc_state); -} - static int mode_hblank_period_ns(const struct drm_display_mode *mode) { return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay, @@ -477,7 +465,7 @@ adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *conne return true; if (!dsc) { - if (intel_dp_mst_dsc_source_support(crtc_state)) { + if (intel_dp_supports_dsc(connector, crtc_state)) { drm_dbg_kms(&i915->drm, "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n", crtc->base.base.id, crtc->base.name, @@ -623,7 +611,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, str_yes_no(ret), str_yes_no(joiner_needs_dsc), str_yes_no(intel_dp->force_dsc_en)); - if (!intel_dp_mst_dsc_source_support(pipe_config)) + if (!intel_dp_supports_dsc(connector, pipe_config)) return -EINVAL; if (!intel_dp_mst_compute_config_limits(intel_dp, -- cgit From b47e62b1ed1306a5fd7ad5d2419ef865fd322851 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 17 May 2024 17:53:55 +0300 Subject: drm/i915: Utilize edp_disable_dsc from VBT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Disable eDP DSC usage when instructed to do so by the VBT. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240517145356.26103-7-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_bios.c | 4 ++++ drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ 3 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index def2ade61954..ec1e3a380360 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -1525,6 +1525,10 @@ parse_edp(struct drm_i915_private *i915, if (i915->display.vbt.version >= 244) panel->vbt.edp.max_link_rate = edp->edp_max_port_link_rate[panel_type] * 20; + + if (i915->display.vbt.version >= 251) + panel->vbt.edp.dsc_disable = + panel_bool(edp->edp_dsc_disable, panel_type); } static void diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 02ebe6f3e765..46b3cbeb4a82 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -335,6 +335,7 @@ struct intel_vbt_panel_data { u8 drrs_msa_timing_delay; bool low_vswing; bool hobl; + bool dsc_disable; } edp; struct { diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 926b0beed666..fda9a704cd80 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1181,6 +1181,10 @@ bool intel_dp_has_dsc(const struct intel_connector *connector) if (connector->mst_port && !HAS_DSC_MST(i915)) return false; + if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && + connector->panel.vbt.edp.dsc_disable) + return false; + if (!drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) return false; -- cgit From 574884438c3827a842926bbff4a0a2d96597a388 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Fri, 17 May 2024 17:53:56 +0300 Subject: drm/i915: Remove bogus MST check in intel_dp_has_audio() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit No idea what this MST checks is doing in intel_dp_has_audio(). Looks completely pointless, so get rid of it. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240517145356.26103-8-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index fda9a704cd80..53b26c354f38 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2788,7 +2788,6 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, } static bool intel_dp_has_audio(struct intel_encoder *encoder, - struct intel_crtc_state *crtc_state, const struct drm_connector_state *conn_state) { struct drm_i915_private *i915 = to_i915(encoder->base.dev); @@ -2797,8 +2796,7 @@ static bool intel_dp_has_audio(struct intel_encoder *encoder, struct intel_connector *connector = to_intel_connector(conn_state->connector); - if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && - !intel_dp_port_has_audio(i915, encoder->port)) + if (!intel_dp_port_has_audio(i915, encoder->port)) return false; if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) @@ -2857,7 +2855,7 @@ intel_dp_audio_compute_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state) { pipe_config->has_audio = - intel_dp_has_audio(encoder, pipe_config, conn_state) && + intel_dp_has_audio(encoder, conn_state) && intel_audio_compute_config(encoder, pipe_config, conn_state); pipe_config->sdp_split_enable = pipe_config->has_audio && -- cgit From 8b5a92ca24eb96bb71e2a55e352687487d87687f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 17:23:11 +0300 Subject: drm/i915/mso: using joiner is not possible with eDP MSO MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's not possible to use the joiner at the same time with eDP MSO. When a panel needs MSO, it's not optional, so MSO trumps joiner. v3: Only change intel_dp_has_joiner(), leave debugfs alone (Ville) Fixes: bc71194e8897 ("drm/i915/edp: enable eDP MSO during link training") Cc: # v5.13+ Cc: Ville Syrjala Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/1668 Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20240614142311.589089-1-jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 53b26c354f38..3903f6ead6e6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -465,6 +465,10 @@ bool intel_dp_has_joiner(struct intel_dp *intel_dp) struct intel_encoder *encoder = &intel_dig_port->base; struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + /* eDP MSO is not compatible with joiner */ + if (intel_dp->mso_link_count) + return false; + return DISPLAY_VER(dev_priv) >= 12 || (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A); -- cgit From 105dadedc4ef42bbcf6b819d962908e482b7d5bb Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:29 +0300 Subject: drm/i915/wm: rename intel_get_cxsr_latency -> pnv_get_cxsr_latency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clarify that the function is specific to PNV, making subsequent changes slightly easier to grasp. Reviewed-by: Matt Roper Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/7d4e3c9a4220ff84af2741e5cd7bb62d1b4f2a44.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_wm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index a12765d9e9e4..ba4a38be7545 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -70,7 +70,7 @@ static const struct cxsr_latency cxsr_latency_table[] = { {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ }; -static const struct cxsr_latency *intel_get_cxsr_latency(struct drm_i915_private *i915) +static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private *i915) { int i; @@ -637,7 +637,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) u32 reg; unsigned int wm; - latency = intel_get_cxsr_latency(dev_priv); + latency = pnv_get_cxsr_latency(dev_priv); if (!latency) { drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM found, disable CxSR\n"); @@ -4029,7 +4029,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv) g4x_setup_wm_latency(dev_priv); dev_priv->display.funcs.wm = &g4x_wm_funcs; } else if (IS_PINEVIEW(dev_priv)) { - if (!intel_get_cxsr_latency(dev_priv)) { + if (!pnv_get_cxsr_latency(dev_priv)) { drm_info(&dev_priv->drm, "failed to find known CxSR latency " "(found ddr%s fsb freq %d, mem freq %d), " -- cgit From 322dc10b2af8b066cfd4b6ea53f5522028eb6b30 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:30 +0300 Subject: drm/i915/wm: clarify logging on not finding CxSR latency config MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Clarify and unify the logging on not finding PNV CxSR latency config. Just let the i915->fsb_freq == 0 || i915->mem_freq == 0 case go through the table instead of checking for it separately. v2: Do not check for fsb == 0 || mem == 0 separately (Matt) Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/6333cb0675c531e971e829105f1ecfc4d71bdc6b.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_wm.c | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index ba4a38be7545..f70ac2f06968 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -74,9 +74,6 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private * { int i; - if (i915->fsb_freq == 0 || i915->mem_freq == 0) - return NULL; - for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { const struct cxsr_latency *latency = &cxsr_latency_table[i]; bool is_desktop = !IS_MOBILE(i915); @@ -88,7 +85,9 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private * return latency; } - drm_dbg_kms(&i915->drm, "Unknown FSB/MEM found, disable CxSR\n"); + drm_dbg_kms(&i915->drm, + "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n", + i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq); return NULL; } @@ -639,8 +638,7 @@ static void pnv_update_wm(struct drm_i915_private *dev_priv) latency = pnv_get_cxsr_latency(dev_priv); if (!latency) { - drm_dbg_kms(&dev_priv->drm, - "Unknown FSB/MEM found, disable CxSR\n"); + drm_dbg_kms(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n"); intel_set_memory_cxsr(dev_priv, false); return; } @@ -4030,12 +4028,7 @@ void i9xx_wm_init(struct drm_i915_private *dev_priv) dev_priv->display.funcs.wm = &g4x_wm_funcs; } else if (IS_PINEVIEW(dev_priv)) { if (!pnv_get_cxsr_latency(dev_priv)) { - drm_info(&dev_priv->drm, - "failed to find known CxSR latency " - "(found ddr%s fsb freq %d, mem freq %d), " - "disabling CxSR\n", - (dev_priv->is_ddr3 == 1) ? "3" : "2", - dev_priv->fsb_freq, dev_priv->mem_freq); + drm_info(&dev_priv->drm, "Unknown FSB/MEM, disabling CxSR\n"); /* Disable CxSR and never update its watermark again */ intel_set_memory_cxsr(dev_priv, false); dev_priv->display.funcs.wm = &nop_funcs; -- cgit From 9d4f1aeb25be7f92825f614b57fa91518c47d39f Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:31 +0300 Subject: drm/i915/dram: separate fsb freq detection from mem freq MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To simplify further changes, add separate functions for reading the fsb frequency. This ends up reading CLKCFG register twice, but it's not a big deal. Reviewed-by: Matt Roper Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/7582651aa21ac2c1472111c4e81ba8fee182f80e.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/soc/intel_dram.c | 106 +++++++++++++++++++--------------- 1 file changed, 60 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 18a879e98f03..3dce9b9a2c5e 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -49,21 +49,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG); - switch (tmp & CLKCFG_FSB_MASK) { - case CLKCFG_FSB_533: - dev_priv->fsb_freq = 533; /* 133*4 */ - break; - case CLKCFG_FSB_800: - dev_priv->fsb_freq = 800; /* 200*4 */ - break; - case CLKCFG_FSB_667: - dev_priv->fsb_freq = 667; /* 167*4 */ - break; - case CLKCFG_FSB_400: - dev_priv->fsb_freq = 400; /* 100*4 */ - break; - } - switch (tmp & CLKCFG_MEM_MASK) { case CLKCFG_MEM_533: dev_priv->mem_freq = 533; @@ -83,7 +68,7 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv) { - u16 ddrpll, csipll; + u16 ddrpll; ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); switch (ddrpll & 0xff) { @@ -105,36 +90,6 @@ static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv) dev_priv->mem_freq = 0; break; } - - csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0); - switch (csipll & 0x3ff) { - case 0x00c: - dev_priv->fsb_freq = 3200; - break; - case 0x00e: - dev_priv->fsb_freq = 3733; - break; - case 0x010: - dev_priv->fsb_freq = 4266; - break; - case 0x012: - dev_priv->fsb_freq = 4800; - break; - case 0x014: - dev_priv->fsb_freq = 5333; - break; - case 0x016: - dev_priv->fsb_freq = 5866; - break; - case 0x018: - dev_priv->fsb_freq = 6400; - break; - default: - drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", - csipll & 0x3ff); - dev_priv->fsb_freq = 0; - break; - } } static void chv_detect_mem_freq(struct drm_i915_private *i915) @@ -192,6 +147,64 @@ static void detect_mem_freq(struct drm_i915_private *i915) drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); } +static unsigned int pnv_fsb_freq(struct drm_i915_private *i915) +{ + u32 fsb; + + fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; + + switch (fsb) { + case CLKCFG_FSB_400: + return 400; + case CLKCFG_FSB_533: + return 533; + case CLKCFG_FSB_667: + return 667; + case CLKCFG_FSB_800: + return 800; + } + + return 0; +} + +static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv) +{ + u16 fsb; + + fsb = intel_uncore_read16(&dev_priv->uncore, CSIPLL0) & 0x3ff; + + switch (fsb) { + case 0x00c: + return 3200; + case 0x00e: + return 3733; + case 0x010: + return 4266; + case 0x012: + return 4800; + case 0x014: + return 5333; + case 0x016: + return 5866; + case 0x018: + return 6400; + default: + drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb); + return 0; + } +} + +static void detect_fsb_freq(struct drm_i915_private *i915) +{ + if (GRAPHICS_VER(i915) == 5) + i915->fsb_freq = ilk_fsb_freq(i915); + else if (IS_PINEVIEW(i915)) + i915->fsb_freq = pnv_fsb_freq(i915); + + if (i915->fsb_freq) + drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq); +} + static int intel_dimm_num_devices(const struct dram_dimm_info *dimm) { return dimm->ranks * 64 / (dimm->width ?: 1); @@ -661,6 +674,7 @@ void intel_dram_detect(struct drm_i915_private *i915) struct dram_info *dram_info = &i915->dram_info; int ret; + detect_fsb_freq(i915); detect_mem_freq(i915); if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915)) -- cgit From e6534546a4b98542ec26375548dbca87f2e1e312 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:32 +0300 Subject: drm/i915/dram: split out pnv DDR3 detection MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split out the PNV DDR3 detection to a distinct step instead of conflating it with mem freq detection. Reviewed-by: Matt Roper Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/c4bf9d32479ab5024e9daa37a996508f543f05e9.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/soc/intel_dram.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 3dce9b9a2c5e..1a4db52ac258 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -43,6 +43,11 @@ static const char *intel_dram_type_str(enum intel_dram_type type) #undef DRAM_TYPE_STR +static bool pnv_is_ddr3(struct drm_i915_private *i915) +{ + return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3; +} + static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) { u32 tmp; @@ -60,10 +65,6 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) dev_priv->mem_freq = 800; break; } - - /* detect pineview DDR3 setting */ - tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL); - dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; } static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv) @@ -143,6 +144,9 @@ static void detect_mem_freq(struct drm_i915_private *i915) else if (IS_VALLEYVIEW(i915)) vlv_detect_mem_freq(i915); + if (IS_PINEVIEW(i915)) + i915->is_ddr3 = pnv_is_ddr3(i915); + if (i915->mem_freq) drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); } -- cgit From 846bd6086d3536d2f9b5a4b289a75d7e7c7753dd Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:33 +0300 Subject: drm/i915/dram: rearrange mem freq init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Follow the same style in mem freq init as in fsb freq init, returning the value instead of assigning in multiple places. Reviewed-by: Matt Roper Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/f098ccdbb0c42016d5dad81e0b089bb4babe29f0.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/soc/intel_dram.c | 59 +++++++++++++++-------------------- 1 file changed, 25 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 1a4db52ac258..266ed6cfa485 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -48,7 +48,7 @@ static bool pnv_is_ddr3(struct drm_i915_private *i915) return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3; } -static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) +static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv) { u32 tmp; @@ -56,44 +56,38 @@ static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv) switch (tmp & CLKCFG_MEM_MASK) { case CLKCFG_MEM_533: - dev_priv->mem_freq = 533; - break; + return 533; case CLKCFG_MEM_667: - dev_priv->mem_freq = 667; - break; + return 667; case CLKCFG_MEM_800: - dev_priv->mem_freq = 800; - break; + return 800; } + + return 0; } -static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv) +static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv) { u16 ddrpll; ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); switch (ddrpll & 0xff) { case 0xc: - dev_priv->mem_freq = 800; - break; + return 800; case 0x10: - dev_priv->mem_freq = 1066; - break; + return 1066; case 0x14: - dev_priv->mem_freq = 1333; - break; + return 1333; case 0x18: - dev_priv->mem_freq = 1600; - break; + return 1600; default: drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n", ddrpll & 0xff); - dev_priv->mem_freq = 0; - break; + return 0; } } -static void chv_detect_mem_freq(struct drm_i915_private *i915) +static unsigned int chv_mem_freq(struct drm_i915_private *i915) { u32 val; @@ -103,15 +97,13 @@ static void chv_detect_mem_freq(struct drm_i915_private *i915) switch ((val >> 2) & 0x7) { case 3: - i915->mem_freq = 2000; - break; + return 2000; default: - i915->mem_freq = 1600; - break; + return 1600; } } -static void vlv_detect_mem_freq(struct drm_i915_private *i915) +static unsigned int vlv_mem_freq(struct drm_i915_private *i915) { u32 val; @@ -122,27 +114,26 @@ static void vlv_detect_mem_freq(struct drm_i915_private *i915) switch ((val >> 6) & 3) { case 0: case 1: - i915->mem_freq = 800; - break; + return 800; case 2: - i915->mem_freq = 1066; - break; + return 1066; case 3: - i915->mem_freq = 1333; - break; + return 1333; } + + return 0; } static void detect_mem_freq(struct drm_i915_private *i915) { if (IS_PINEVIEW(i915)) - pnv_detect_mem_freq(i915); + i915->mem_freq = pnv_mem_freq(i915); else if (GRAPHICS_VER(i915) == 5) - ilk_detect_mem_freq(i915); + i915->mem_freq = ilk_mem_freq(i915); else if (IS_CHERRYVIEW(i915)) - chv_detect_mem_freq(i915); + i915->mem_freq = chv_mem_freq(i915); else if (IS_VALLEYVIEW(i915)) - vlv_detect_mem_freq(i915); + i915->mem_freq = vlv_mem_freq(i915); if (IS_PINEVIEW(i915)) i915->is_ddr3 = pnv_is_ddr3(i915); -- cgit From 024a05a47e4475dbcab489777861e2161e1b28c8 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:34 +0300 Subject: drm/i915/gt: remove mem freq from gt debugfs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit It's a bit out of place, and only printed for VLV/CHV. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/bbfec4c67a81d1d3de1f40484a80b7164e69df21.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c index 4fcba42cfe34..c1ce6258e55c 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c @@ -367,7 +367,6 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, struct drm_printer *p) vlv_punit_put(i915); drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); - drm_printf(p, "DDR freq: %d MHz\n", i915->mem_freq); drm_printf(p, "actual GPU freq: %d MHz\n", intel_gpu_freq(rps, (freq_sts >> 8) & 0xff)); -- cgit From a4ad402078ad18ae6a7cc9be91b3492832a481a1 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:35 +0300 Subject: drm/i915: convert fsb_freq and mem_freq to kHz MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We'll want to use fsb frequency for deriving GT clock and rawclk frequencies in the future. Increase the accuracy by converting to kHz. Do the same for mem freq to be aligned. Round the frequencies ending in 666 to 667. v2: Also handle mem_freq in gen5_rps_init() (Ville) Reviewed-by: Matt Roper Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/17fe2544b876549f63fac0f956273f5f282081b3.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/i9xx_wm.c | 6 ++-- drivers/gpu/drm/i915/gt/intel_rps.c | 11 ++++---- drivers/gpu/drm/i915/soc/intel_dram.c | 50 +++++++++++++++++----------------- 3 files changed, 34 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c index f70ac2f06968..2b7c3d270b17 100644 --- a/drivers/gpu/drm/i915/display/i9xx_wm.c +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c @@ -80,13 +80,13 @@ static const struct cxsr_latency *pnv_get_cxsr_latency(struct drm_i915_private * if (is_desktop == latency->is_desktop && i915->is_ddr3 == latency->is_ddr3 && - i915->fsb_freq == latency->fsb_freq && - i915->mem_freq == latency->mem_freq) + DIV_ROUND_CLOSEST(i915->fsb_freq, 1000) == latency->fsb_freq && + DIV_ROUND_CLOSEST(i915->mem_freq, 1000) == latency->mem_freq) return latency; } drm_dbg_kms(&i915->drm, - "Could not find CxSR latency for DDR%s, FSB %u MHz, MEM %u MHz\n", + "Could not find CxSR latency for DDR%s, FSB %u kHz, MEM %u kHz\n", i915->is_ddr3 ? "3" : "2", i915->fsb_freq, i915->mem_freq); return NULL; diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c index 70176be269d3..fa304ea088e4 100644 --- a/drivers/gpu/drm/i915/gt/intel_rps.c +++ b/drivers/gpu/drm/i915/gt/intel_rps.c @@ -265,10 +265,10 @@ static const struct cparams { u16 c; } cparams[] = { { 1, 1333, 301, 28664 }, - { 1, 1066, 294, 24460 }, + { 1, 1067, 294, 24460 }, { 1, 800, 294, 25192 }, { 0, 1333, 276, 27605 }, - { 0, 1066, 276, 27605 }, + { 0, 1067, 276, 27605 }, { 0, 800, 231, 23784 }, }; @@ -280,15 +280,16 @@ static void gen5_rps_init(struct intel_rps *rps) u32 rgvmodectl; int c_m, i; - if (i915->fsb_freq <= 3200) + if (i915->fsb_freq <= 3200000) c_m = 0; - else if (i915->fsb_freq <= 4800) + else if (i915->fsb_freq <= 4800000) c_m = 1; else c_m = 2; for (i = 0; i < ARRAY_SIZE(cparams); i++) { - if (cparams[i].i == c_m && cparams[i].t == i915->mem_freq) { + if (cparams[i].i == c_m && + cparams[i].t == DIV_ROUND_CLOSEST(i915->mem_freq, 1000)) { rps->ips.m = cparams[i].m; rps->ips.c = cparams[i].c; break; diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 266ed6cfa485..ace9372244a4 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -56,11 +56,11 @@ static unsigned int pnv_mem_freq(struct drm_i915_private *dev_priv) switch (tmp & CLKCFG_MEM_MASK) { case CLKCFG_MEM_533: - return 533; + return 533333; case CLKCFG_MEM_667: - return 667; + return 666667; case CLKCFG_MEM_800: - return 800; + return 800000; } return 0; @@ -73,13 +73,13 @@ static unsigned int ilk_mem_freq(struct drm_i915_private *dev_priv) ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1); switch (ddrpll & 0xff) { case 0xc: - return 800; + return 800000; case 0x10: - return 1066; + return 1066667; case 0x14: - return 1333; + return 1333333; case 0x18: - return 1600; + return 1600000; default: drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n", ddrpll & 0xff); @@ -97,9 +97,9 @@ static unsigned int chv_mem_freq(struct drm_i915_private *i915) switch ((val >> 2) & 0x7) { case 3: - return 2000; + return 2000000; default: - return 1600; + return 1600000; } } @@ -114,11 +114,11 @@ static unsigned int vlv_mem_freq(struct drm_i915_private *i915) switch ((val >> 6) & 3) { case 0: case 1: - return 800; + return 800000; case 2: - return 1066; + return 1066667; case 3: - return 1333; + return 1333333; } return 0; @@ -139,7 +139,7 @@ static void detect_mem_freq(struct drm_i915_private *i915) i915->is_ddr3 = pnv_is_ddr3(i915); if (i915->mem_freq) - drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq); + drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq); } static unsigned int pnv_fsb_freq(struct drm_i915_private *i915) @@ -150,13 +150,13 @@ static unsigned int pnv_fsb_freq(struct drm_i915_private *i915) switch (fsb) { case CLKCFG_FSB_400: - return 400; + return 400000; case CLKCFG_FSB_533: - return 533; + return 533333; case CLKCFG_FSB_667: - return 667; + return 666667; case CLKCFG_FSB_800: - return 800; + return 800000; } return 0; @@ -170,19 +170,19 @@ static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv) switch (fsb) { case 0x00c: - return 3200; + return 3200000; case 0x00e: - return 3733; + return 3733333; case 0x010: - return 4266; + return 4266667; case 0x012: - return 4800; + return 4800000; case 0x014: - return 5333; + return 5333333; case 0x016: - return 5866; + return 5866667; case 0x018: - return 6400; + return 6400000; default: drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n", fsb); return 0; @@ -197,7 +197,7 @@ static void detect_fsb_freq(struct drm_i915_private *i915) i915->fsb_freq = pnv_fsb_freq(i915); if (i915->fsb_freq) - drm_dbg(&i915->drm, "FSB frequency: %d MHz\n", i915->fsb_freq); + drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq); } static int intel_dimm_num_devices(const struct dram_dimm_info *dimm) -- cgit From fc8bf961059c3795bf8f4bdb5948bff8417df1f6 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:36 +0300 Subject: drm/i915: extend the fsb_freq initialization to more platforms MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Initialize fsb frequency for more platforms to be able to use it for GT clock and rawclk frequency initialization. Note: There's a discrepancy between existing pnv_fsb_freq() and i9xx_hrawclk() regarding CLKCFG interpretation. Presume all PNV is mobile. Default to 1333 MHz for unknown values, similar to i9xx_hrawclk(). v2: - Add MISSING_CASE() (Ville) - Default to the same frequency for both branches (Ville) Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/7cd6dbd4dafb900ac1dd12be0ec096ff1d5fc6cf.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/soc/intel_dram.c | 55 ++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index ace9372244a4..1b01e5130f79 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -142,24 +142,51 @@ static void detect_mem_freq(struct drm_i915_private *i915) drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq); } -static unsigned int pnv_fsb_freq(struct drm_i915_private *i915) +static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) { u32 fsb; fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; - switch (fsb) { - case CLKCFG_FSB_400: - return 400000; - case CLKCFG_FSB_533: - return 533333; - case CLKCFG_FSB_667: - return 666667; - case CLKCFG_FSB_800: - return 800000; + if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) { + switch (fsb) { + case CLKCFG_FSB_400: + return 400000; + case CLKCFG_FSB_533: + return 533333; + case CLKCFG_FSB_667: + return 666667; + case CLKCFG_FSB_800: + return 800000; + case CLKCFG_FSB_1067: + return 1066667; + case CLKCFG_FSB_1333: + return 1333333; + default: + MISSING_CASE(fsb); + return 1333333; + } + } else { + switch (fsb) { + case CLKCFG_FSB_400_ALT: + return 400000; + case CLKCFG_FSB_533: + return 533333; + case CLKCFG_FSB_667: + return 666667; + case CLKCFG_FSB_800: + return 800000; + case CLKCFG_FSB_1067_ALT: + return 1066667; + case CLKCFG_FSB_1333_ALT: + return 1333333; + case CLKCFG_FSB_1600_ALT: + return 1600000; + default: + MISSING_CASE(fsb); + return 1333333; + } } - - return 0; } static unsigned int ilk_fsb_freq(struct drm_i915_private *dev_priv) @@ -193,8 +220,8 @@ static void detect_fsb_freq(struct drm_i915_private *i915) { if (GRAPHICS_VER(i915) == 5) i915->fsb_freq = ilk_fsb_freq(i915); - else if (IS_PINEVIEW(i915)) - i915->fsb_freq = pnv_fsb_freq(i915); + else if (GRAPHICS_VER(i915) == 3 || GRAPHICS_VER(i915) == 4) + i915->fsb_freq = i9xx_fsb_freq(i915); if (i915->fsb_freq) drm_dbg(&i915->drm, "FSB frequency: %d kHz\n", i915->fsb_freq); -- cgit From d0a6e5015f0e1c8c40adee1119213f7d72bdb65d Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:37 +0300 Subject: drm/i915: use i9xx_fsb_freq() for GT clock frequency MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Reuse i9xx_fsb_freq() for GT clock frequency initialization instead of depending on rawclk_freq. Note: If the init order was changed, we could use i915->fsb_freq directly. However, GT clock initialization is done in i915_driver_mmio_probe(), but intel_dram_detect() later in i915_driver_hw_probe(), with a dependency on intel_pcode_init(). Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/0678d8ec9772725b47d4fa5b14e3b3a34256d5cf.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c | 3 ++- drivers/gpu/drm/i915/soc/intel_dram.c | 2 +- drivers/gpu/drm/i915/soc/intel_dram.h | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c index 7c9be4fd1c8c..6e63505fe478 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c +++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c @@ -9,6 +9,7 @@ #include "intel_gt_clock_utils.h" #include "intel_gt_print.h" #include "intel_gt_regs.h" +#include "soc/intel_dram.h" static u32 read_reference_ts_freq(struct intel_uncore *uncore) { @@ -151,7 +152,7 @@ static u32 gen4_read_clock_frequency(struct intel_uncore *uncore) * * Testing on actual hardware has shown there is no /16. */ - return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000; + return DIV_ROUND_CLOSEST(i9xx_fsb_freq(uncore->i915), 4) * 1000; } static u32 read_clock_frequency(struct intel_uncore *uncore) diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index 1b01e5130f79..dac39b41fa51 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -142,7 +142,7 @@ static void detect_mem_freq(struct drm_i915_private *i915) drm_dbg(&i915->drm, "DDR speed: %d kHz\n", i915->mem_freq); } -static unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) +unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) { u32 fsb; diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h index 4ba13c13162c..a10136eda674 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.h +++ b/drivers/gpu/drm/i915/soc/intel_dram.h @@ -10,5 +10,6 @@ struct drm_i915_private; void intel_dram_edram_detect(struct drm_i915_private *i915); void intel_dram_detect(struct drm_i915_private *i915); +unsigned int i9xx_fsb_freq(struct drm_i915_private *i915); #endif /* __INTEL_DRAM_H__ */ -- cgit From 1cd377f33d4c042786f2d170a7097021787816f1 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:38 +0300 Subject: drm/i915/cdclk: use i9xx_fsb_freq() for rawclk_freq initialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of duplicating the CLKCFG parsing, reuse i9xx_fsb_freq() to figure out rawclk_freq where applicable. Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/21511f155f1f446e066117bc6ed3165618d7afd6.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cdclk.c | 46 ++---------------------------- 1 file changed, 3 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index c5bc49e48c88..b6adcbd9025f 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -23,6 +23,7 @@ #include +#include "soc/intel_dram.h" #include "hsw_ips.h" #include "i915_reg.h" #include "intel_atomic.h" @@ -3539,10 +3540,8 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv) CCK_DISPLAY_REF_CLOCK_CONTROL); } -static int i9xx_hrawclk(struct drm_i915_private *dev_priv) +static int i9xx_hrawclk(struct drm_i915_private *i915) { - u32 clkcfg; - /* * hrawclock is 1/4 the FSB frequency * @@ -3553,46 +3552,7 @@ static int i9xx_hrawclk(struct drm_i915_private *dev_priv) * don't know which registers have that information, * and all the relevant docs have gone to bit heaven :( */ - clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK; - - if (IS_MOBILE(dev_priv)) { - switch (clkcfg) { - case CLKCFG_FSB_400: - return 100000; - case CLKCFG_FSB_533: - return 133333; - case CLKCFG_FSB_667: - return 166667; - case CLKCFG_FSB_800: - return 200000; - case CLKCFG_FSB_1067: - return 266667; - case CLKCFG_FSB_1333: - return 333333; - default: - MISSING_CASE(clkcfg); - return 133333; - } - } else { - switch (clkcfg) { - case CLKCFG_FSB_400_ALT: - return 100000; - case CLKCFG_FSB_533: - return 133333; - case CLKCFG_FSB_667: - return 166667; - case CLKCFG_FSB_800: - return 200000; - case CLKCFG_FSB_1067_ALT: - return 266667; - case CLKCFG_FSB_1333_ALT: - return 333333; - case CLKCFG_FSB_1600_ALT: - return 400000; - default: - return 133333; - } - } + return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); } /** -- cgit From b2956099379edd869e9efa31876aeb65996c62d6 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Fri, 14 Jun 2024 12:22:39 +0300 Subject: drm/i915: move comments about FSB straps to proper place MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the comment about FSB straps to where the relevant register is read. Suggested-by: Ville Syrjälä Reviewed-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/8a5b6cd3db80259c30263861f1a9ff04fea2e7f0.1718356614.git.jani.nikula@intel.com Signed-off-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_cdclk.c | 11 +---------- drivers/gpu/drm/i915/soc/intel_dram.c | 8 ++++++++ 2 files changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index b6adcbd9025f..16d5550f7e5e 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -3542,16 +3542,7 @@ static int vlv_hrawclk(struct drm_i915_private *dev_priv) static int i9xx_hrawclk(struct drm_i915_private *i915) { - /* - * hrawclock is 1/4 the FSB frequency - * - * Note that this only reads the state of the FSB - * straps, not the actual FSB frequency. Some BIOSen - * let you configure each independently. Ideally we'd - * read out the actual FSB frequency but sadly we - * don't know which registers have that information, - * and all the relevant docs have gone to bit heaven :( - */ + /* hrawclock is 1/4 the FSB frequency */ return DIV_ROUND_CLOSEST(i9xx_fsb_freq(i915), 4); } diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c index dac39b41fa51..4aba47bccc63 100644 --- a/drivers/gpu/drm/i915/soc/intel_dram.c +++ b/drivers/gpu/drm/i915/soc/intel_dram.c @@ -146,6 +146,14 @@ unsigned int i9xx_fsb_freq(struct drm_i915_private *i915) { u32 fsb; + /* + * Note that this only reads the state of the FSB + * straps, not the actual FSB frequency. Some BIOSen + * let you configure each independently. Ideally we'd + * read out the actual FSB frequency but sadly we + * don't know which registers have that information, + * and all the relevant docs have gone to bit heaven :( + */ fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; if (IS_PINEVIEW(i915) || IS_MOBILE(i915)) { -- cgit From 355d210aad943ed12e70c79576406c0c303af815 Mon Sep 17 00:00:00 2001 From: Vinod Govindapillai Date: Tue, 28 May 2024 14:48:26 +0300 Subject: drm/i915/display: update handling of FBC when VT-d active workaround MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the handling of the disabling FBC when VT-d is active wa as part of the intel_fbc_check_plane(). As the hw is still there, intel_fbc_sanitize should be able to handle the state properly. v2: update the patch description (Jani Nikula) v3: fix the return value in wa handling (Jani Nikula) Bspec: 21664 Suggested-by: Ville Syrjälä Signed-off-by: Vinod Govindapillai Reviewed-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20240528114826.134958-1-vinod.govindapillai@intel.com --- drivers/gpu/drm/i915/display/intel_fbc.c | 22 ++++++---------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 8e956e7a1964..67116c9f1464 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -1237,6 +1237,12 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state, return 0; } + /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ + if (i915_vtd_active(i915) && (IS_SKYLAKE(i915) || IS_BROXTON(i915))) { + plane_state->no_fbc_reason = "VT-d enabled"; + return 0; + } + crtc_state = intel_atomic_get_new_crtc_state(state, crtc); if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { @@ -1822,19 +1828,6 @@ static int intel_sanitize_fbc_option(struct drm_i915_private *i915) return 0; } -static bool need_fbc_vtd_wa(struct drm_i915_private *i915) -{ - /* WaFbcTurnOffFbcWhenHyperVisorIsUsed:skl,bxt */ - if (i915_vtd_active(i915) && - (IS_SKYLAKE(i915) || IS_BROXTON(i915))) { - drm_info(&i915->drm, - "Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled\n"); - return true; - } - - return false; -} - void intel_fbc_add_plane(struct intel_fbc *fbc, struct intel_plane *plane) { plane->fbc = fbc; @@ -1880,9 +1873,6 @@ void intel_fbc_init(struct drm_i915_private *i915) { enum intel_fbc_id fbc_id; - if (need_fbc_vtd_wa(i915)) - DISPLAY_RUNTIME_INFO(i915)->fbc_mask = 0; - i915->display.params.enable_fbc = intel_sanitize_fbc_option(i915); drm_dbg_kms(&i915->drm, "Sanitized enable_fbc value: %d\n", i915->display.params.enable_fbc); -- cgit From e2dc7cb72b25f90759382a065787c8ed81beb21b Mon Sep 17 00:00:00 2001 From: Mitul Golani Date: Fri, 14 Jun 2024 10:12:13 +0530 Subject: drm/i915/display: Update calculation to avoid overflow Update calculation to avoid overflow. -v2: Remove extra line between cc and signed-off. Fixes: 1676ecd303ac ("drm/i915: Compute CMRR and calculate vtotal") Cc: Mitul Golani Cc: Ankit Nautiyal Cc: Suraj Kandpal Cc: Jani Nikula Cc: Stephen Rothwell Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal Acked-by: Lucas De Marchi Link: https://patchwork.freedesktop.org/patch/msgid/20240614044213.377710-1-mitulkumar.ajitkumar.golani@intel.com Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/display/intel_vrr.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index eb5b62b54d32..6430da25957d 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -147,10 +147,11 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) multiplier_n = 1000; } - crtc_state->cmrr.cmrr_n = - desired_refresh_rate * adjusted_mode->crtc_htotal * multiplier_n; - vtotal = (adjusted_mode->crtc_clock * 1000 * multiplier_n) / crtc_state->cmrr.cmrr_n; - adjusted_pixel_rate = adjusted_mode->crtc_clock * 1000 * multiplier_m; + crtc_state->cmrr.cmrr_n = mul_u32_u32(desired_refresh_rate * adjusted_mode->crtc_htotal, + multiplier_n); + vtotal = DIV_ROUND_UP_ULL(mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_n), + crtc_state->cmrr.cmrr_n); + adjusted_pixel_rate = mul_u32_u32(adjusted_mode->crtc_clock * 1000, multiplier_m); crtc_state->cmrr.cmrr_m = do_div(adjusted_pixel_rate, crtc_state->cmrr.cmrr_n); return vtotal; -- cgit From 97db7348640ececd60a0bfd85b6c0a3a0f81459a Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 18 Jun 2024 08:30:18 +0300 Subject: drm/i915/psr: Set SU area width as pipe src width MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently SU area width is set as MAX_INT. This is causing problems. Instead set it as pipe src width. Fixes: 86b26b6aeac7 ("drm/i915/psr: Carry su area in crtc_state") Signed-off-by: Jouni Högander Reviewed-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-2-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 920186c2264d..3f36b94020ff 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2316,7 +2316,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, crtc_state->psr2_su_area.x1 = 0; crtc_state->psr2_su_area.y1 = -1; - crtc_state->psr2_su_area.x2 = INT_MAX; + crtc_state->psr2_su_area.x2 = drm_rect_width(&crtc_state->pipe_src); crtc_state->psr2_su_area.y2 = -1; /* -- cgit From 1eb28818c2418e341af2e8b5385243e03e841ae8 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 18 Jun 2024 08:30:19 +0300 Subject: drm/i915/display: Wa 16021440873 is writing wrong register MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Wa 16021440873 is writing wrong register. Instead of PIPE_SRCSZ_ERLY_TPT write CURPOS_ERLY_TPT. v2: use right offset as well Fixes: 29cdef8539c3 ("drm/i915/display: Implement Wa_16021440873") Signed-off-by: Jouni Högander Reviewed-by: Mika Kahola Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-3-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_cursor.c | 4 ++-- drivers/gpu/drm/i915/display/intel_psr.c | 12 +++--------- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c index 7f7fc710350c..66436e526021 100644 --- a/drivers/gpu/drm/i915/display/intel_cursor.c +++ b/drivers/gpu/drm/i915/display/intel_cursor.c @@ -524,8 +524,8 @@ static void wa_16021440873(struct intel_plane *plane, intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl); - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe), - PIPESRC_HEIGHT(et_y_position)); + intel_de_write(dev_priv, CURPOS_ERLY_TPT(dev_priv, pipe), + CURSOR_POS_Y(et_y_position)); } static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 3f36b94020ff..2a33e35ceeff 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -2164,19 +2164,14 @@ exit: crtc_state->psr2_man_track_ctl = val; } -static u32 -psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, - bool full_update, bool cursor_in_su_area) +static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state, + bool full_update) { int width, height; if (!crtc_state->enable_psr2_su_region_et || full_update) return 0; - if (!cursor_in_su_area) - return PIPESRC_WIDTH(0) | - PIPESRC_HEIGHT(drm_rect_height(&crtc_state->pipe_src)); - width = drm_rect_width(&crtc_state->psr2_su_area); height = drm_rect_height(&crtc_state->psr2_su_area); @@ -2485,8 +2480,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state, skip_sel_fetch_set_loop: psr2_man_trk_ctl_calc(crtc_state, full_update); crtc_state->pipe_srcsz_early_tpt = - psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update, - cursor_in_su_area); + psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update); return 0; } -- cgit From 22f3a60558da4509c0c3fa49b82a5d7e6f677cf5 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 18 Jun 2024 08:30:20 +0300 Subject: drm/i915/alpm: Fix port clock usage in AUX Less wake time calculation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Port clock is link rate in 10 kbit/s units. Take this into account when calculating AUX Less wake time. Fixes: da6a9836ac09 ("drm/i915/psr: Calculate aux less wake time") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-4-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_alpm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 90072f6e3a33..67848fc1e24d 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -125,7 +125,8 @@ static int _lnl_compute_aux_less_wake_time(int port_clock) int tsilence_max = 180; int t1 = 50 * 1000; int tps4 = 252; - int tml_phy_lock = 1000 * 1000 * tps4 * 10 / port_clock; + /* port_clock is link rate in 10kbit/s units */ + int tml_phy_lock = 1000 * 1000 * tps4 / port_clock; int num_ml_phy_lock = 7 + DIV_ROUND_UP(6500, tml_phy_lock) + 1; int t2 = num_ml_phy_lock * tml_phy_lock; int tcds = 1 * t2; -- cgit From b445130c35e5bfe7917e44140e259b2babeec87f Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 18 Jun 2024 08:30:21 +0300 Subject: drm/i915/psr: Disable Panel Replay if PSR mode is set via module parameter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit If user is specifically limiting PSR mode to PSR1 or PSR2: disable Panel Replay. With default value -1 all modes are allowed including Panel Replay. Disabling PSR using value 0 disables Panel Replay as well. Also own compute config helper is added for Panel Replay. This makes sense because number of Panel Replay specific checks are increasing. v2: Squash adding Panel Replay compute config helper Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-5-jouni.hogander@intel.com --- .../gpu/drm/i915/display/intel_display_params.c | 3 +-- drivers/gpu/drm/i915/display/intel_psr.c | 27 ++++++++++++++++++++-- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_params.c b/drivers/gpu/drm/i915/display/intel_display_params.c index aebdb7b59dbf..79107607a6ff 100644 --- a/drivers/gpu/drm/i915/display/intel_display_params.c +++ b/drivers/gpu/drm/i915/display/intel_display_params.c @@ -106,8 +106,7 @@ intel_display_param_named_unsafe(enable_fbc, int, 0400, intel_display_param_named_unsafe(enable_psr, int, 0400, "Enable PSR " - "(0=disabled, 1=enable up to PSR1 and Panel Replay full frame update, " - "2=enable up to PSR2 and Panel Replay Selective Update) " + "(0=disabled, 1=enable up to PSR1, 2=enable up to PSR2) " "Default: -1 (use per-chip default)"); intel_display_param_named(psr_safest_params, bool, 0400, diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 2a33e35ceeff..cfce0fe05d92 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -235,6 +235,15 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp) } } +static bool panel_replay_global_enabled(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (i915->display.params.enable_psr != -1) + return false; + return true; +} + static u32 psr_irq_psr_error_bit_get(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -1455,6 +1464,21 @@ static bool _psr_compute_config(struct intel_dp *intel_dp, return true; } +static bool _panel_replay_compute_config(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (!CAN_PANEL_REPLAY(intel_dp)) + return false; + + if (!panel_replay_global_enabled(intel_dp)) { + drm_dbg_kms(&i915->drm, "Panel Replay disabled by flag\n"); + return false; + } + + return true; +} + void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -1490,8 +1514,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, return; } - if (CAN_PANEL_REPLAY(intel_dp)) - crtc_state->has_panel_replay = true; + crtc_state->has_panel_replay = _panel_replay_compute_config(intel_dp); crtc_state->has_psr = crtc_state->has_panel_replay ? true : _psr_compute_config(intel_dp, crtc_state); -- cgit From aeb7a0fe21dca9f8322906e6c5bd45c8b3d9b768 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 18 Jun 2024 08:30:22 +0300 Subject: drm/i915/psr: Disable PSR2 SU Region ET if enable_psr module parameter is set MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently PSR2 SU Region Early Transport is enabled by default on Lunarlake if panel supports it despite enable_psr module parameter value. This patch makes it possible for user to limit used PSR mode and prevent SU Region Early Transport by setting enable_psr as 2. With default (-1) PSR2 SU Region Early Transport is allowed. v2: fix/improve commit desciption Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-6-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index cfce0fe05d92..800cfeabc139 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -235,6 +235,16 @@ static bool psr2_global_enabled(struct intel_dp *intel_dp) } } +static bool psr2_su_region_et_global_enabled(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + if (i915->display.params.enable_psr != -1) + return false; + + return true; +} + static bool panel_replay_global_enabled(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -683,7 +693,8 @@ static bool psr2_su_region_et_valid(struct intel_dp *intel_dp, bool panel_replay return panel_replay ? intel_dp->pr_dpcd & DP_PANEL_REPLAY_EARLY_TRANSPORT_SUPPORT : - intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED; + intel_dp->psr_dpcd[0] == DP_PSR2_WITH_Y_COORD_ET_SUPPORTED && + psr2_su_region_et_global_enabled(intel_dp); } static void _panel_replay_enable_sink(struct intel_dp *intel_dp, -- cgit From 3ec391a007f405b4fe48ecf2bf55d3ff0fc7d1b2 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 18 Jun 2024 08:30:23 +0300 Subject: drm/i915/psr: Disable PSR/Panel Replay on sink side for PSR only MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Enabling/disabling Panel Replay on sink side has to be done before link training. We can't disable it in sink side on PSR disable. Fixes: 88ae6c65ecdb ("drm/i915/psr: Unify panel replay enable/disable sink") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-7-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 800cfeabc139..595097353ceb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1974,13 +1974,13 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp) } /* Disable PSR on Sink */ - drm_dp_dpcd_writeb(&intel_dp->aux, - intel_dp->psr.panel_replay_enabled ? - PANEL_REPLAY_CONFIG : DP_PSR_EN_CFG, 0); + if (!intel_dp->psr.panel_replay_enabled) { + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, 0); - if (!intel_dp->psr.panel_replay_enabled && - intel_dp->psr.sel_update_enabled) - drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, 0); + if (intel_dp->psr.sel_update_enabled) + drm_dp_dpcd_writeb(&intel_dp->aux, + DP_RECEIVER_ALPM_CONFIG, 0); + } intel_dp->psr.enabled = false; intel_dp->psr.panel_replay_enabled = false; -- cgit From c52a3187a1bf0a13c3a0119d057781166f12a8ee Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 18 Jun 2024 08:30:24 +0300 Subject: drm/i915/psr: Add new debug bit to disable Panel Replay MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add new debug bit to be used with i915_edp_psr_debug debugfs interface. This can be used to disable Panel Replay. v2: ensure that fastset is performed when the bit changes Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-8-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 11 ++++++++--- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 46b3cbeb4a82..8fe7942511f8 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1703,6 +1703,7 @@ struct intel_psr { #define I915_PSR_DEBUG_ENABLE_SEL_FETCH 0x4 #define I915_PSR_DEBUG_IRQ 0x10 #define I915_PSR_DEBUG_SU_REGION_ET_DISABLE 0x20 +#define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40 u32 debug; bool sink_support; diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 595097353ceb..cd76109e928a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -249,7 +249,8 @@ static bool panel_replay_global_enabled(struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); - if (i915->display.params.enable_psr != -1) + if ((i915->display.params.enable_psr != -1) || + (intel_dp->psr.debug & I915_PSR_DEBUG_PANEL_REPLAY_DISABLE)) return false; return true; } @@ -2788,11 +2789,13 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); const u32 mode = val & I915_PSR_DEBUG_MODE_MASK; - const u32 disable_bits = val & I915_PSR_DEBUG_SU_REGION_ET_DISABLE; + const u32 disable_bits = val & (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | + I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); u32 old_mode, old_disable_bits; int ret; if (val & ~(I915_PSR_DEBUG_IRQ | I915_PSR_DEBUG_SU_REGION_ET_DISABLE | + I915_PSR_DEBUG_PANEL_REPLAY_DISABLE | I915_PSR_DEBUG_MODE_MASK) || mode > I915_PSR_DEBUG_ENABLE_SEL_FETCH) { drm_dbg_kms(&dev_priv->drm, "Invalid debug mask %llx\n", val); @@ -2805,7 +2808,9 @@ int intel_psr_debug_set(struct intel_dp *intel_dp, u64 val) old_mode = intel_dp->psr.debug & I915_PSR_DEBUG_MODE_MASK; old_disable_bits = intel_dp->psr.debug & - I915_PSR_DEBUG_SU_REGION_ET_DISABLE; + (I915_PSR_DEBUG_SU_REGION_ET_DISABLE | + I915_PSR_DEBUG_PANEL_REPLAY_DISABLE); + intel_dp->psr.debug = val; /* -- cgit From dc9cfe9f1d22b359d6f316005c887c1a6e31701d Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 18 Jun 2024 08:30:25 +0300 Subject: Revert "drm/i915/psr: Disable early transport by default" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This reverts commit f3c2031db7dfdf470a2d9bf3bd1efa6edfa72d8d. We want to notice possible issues faced with PSR2 Region Early Transport as early as possible -> let's revert patch disabling Region Early Transport by default. Also eDP 1.5 Panel Replay requires Early Transport. Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-9-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index cd76109e928a..a9d9383e4ee5 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3110,9 +3110,6 @@ void intel_psr_init(struct intel_dp *intel_dp) else intel_dp->psr.source_support = true; - /* Disable early transport for now */ - intel_dp->psr.debug |= I915_PSR_DEBUG_SU_REGION_ET_DISABLE; - /* Set link_standby x link_off defaults */ if (DISPLAY_VER(dev_priv) < 12) /* For new platforms up to TGL let's respect VBT back again */ -- cgit From dcaacff03a9fa2838f936e1009b4b7ad56807152 Mon Sep 17 00:00:00 2001 From: Jouni Högander Date: Tue, 18 Jun 2024 08:30:26 +0300 Subject: intel_alpm: Fix wrong offset for PORT_ALPM_* registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PORT_ALPM_* registers are using MMIO_TRANS2 macro. This is not correct as they are port register. Use _PORT_MMIO instead. Fixes: 4ee30a448255 ("drm/i915/alpm: Add ALPM register definitions") Signed-off-by: Jouni Högander Reviewed-by: Animesh Manna Link: https://patchwork.freedesktop.org/patch/msgid/20240618053026.3268759-10-jouni.hogander@intel.com --- drivers/gpu/drm/i915/display/intel_alpm.c | 5 +++-- drivers/gpu/drm/i915/display/intel_psr_regs.h | 6 ++++-- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c index 67848fc1e24d..c7092af7da33 100644 --- a/drivers/gpu/drm/i915/display/intel_alpm.c +++ b/drivers/gpu/drm/i915/display/intel_alpm.c @@ -310,6 +310,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + enum port port = dp_to_dig_port(intel_dp)->base.port; u32 alpm_ctl; if (DISPLAY_VER(dev_priv) < 20 || (!intel_dp->psr.sel_update_enabled && @@ -328,7 +329,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, ALPM_CTL_AUX_LESS_WAKE_TIME(intel_dp->alpm_parameters.aux_less_wake_lines); intel_de_write(dev_priv, - PORT_ALPM_CTL(dev_priv, cpu_transcoder), + PORT_ALPM_CTL(dev_priv, port), PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE | PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(15) | PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(0) | @@ -336,7 +337,7 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp, intel_dp->alpm_parameters.silence_period_sym_clocks)); intel_de_write(dev_priv, - PORT_ALPM_LFPS_CTL(dev_priv, cpu_transcoder), + PORT_ALPM_LFPS_CTL(dev_priv, port), PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT(10) | PORT_ALPM_LFPS_CTL_LFPS_HALF_CYCLE_DURATION( intel_dp->alpm_parameters.lfps_half_cycle_num_of_syms) | diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 1e503209da09..642bb15fb547 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -294,7 +294,8 @@ #define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) #define _PORT_ALPM_CTL_A 0x16fa2c -#define PORT_ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A) +#define _PORT_ALPM_CTL_B 0x16fc2c +#define PORT_ALPM_CTL(dev_priv, port) _MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B) #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) @@ -304,7 +305,8 @@ #define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val) #define _PORT_ALPM_LFPS_CTL_A 0x16fa30 -#define PORT_ALPM_LFPS_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A) +#define _PORT_ALPM_LFPS_CTL_B 0x16fc30 +#define PORT_ALPM_LFPS_CTL(dev_priv, port) _MMIO_PORT(port, _PORT_ALPM_LFPS_CTL_A, _PORT_ALPM_LFPS_CTL_B) #define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31) #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24) #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7 -- cgit