From d0c908d2978e0ef3c1ac1357c1c58224a153f8d4 Mon Sep 17 00:00:00 2001 From: Shekhar Chauhan Date: Wed, 11 Oct 2023 13:30:39 +0530 Subject: drm/i915: Add new DG2 PCI IDs Add recently added PCI IDs for DG2 BSpec: 44477 Signed-off-by: Shekhar Chauhan Reviewed-by: Matt Roper Signed-off-by: Matt Roper Link: https://patchwork.freedesktop.org/patch/msgid/20231011080039.2781048-1-shekhar.chauhan@intel.com --- include/drm/i915_pciids.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h index 1256770d3827..1c9ea6ab3eb9 100644 --- a/include/drm/i915_pciids.h +++ b/include/drm/i915_pciids.h @@ -718,7 +718,11 @@ INTEL_VGA_DEVICE(0x56A5, info), \ INTEL_VGA_DEVICE(0x56A6, info), \ INTEL_VGA_DEVICE(0x56B0, info), \ - INTEL_VGA_DEVICE(0x56B1, info) + INTEL_VGA_DEVICE(0x56B1, info), \ + INTEL_VGA_DEVICE(0x56BA, info), \ + INTEL_VGA_DEVICE(0x56BB, info), \ + INTEL_VGA_DEVICE(0x56BC, info), \ + INTEL_VGA_DEVICE(0x56BD, info) #define INTEL_DG2_G12_IDS(info) \ INTEL_VGA_DEVICE(0x5696, info), \ -- cgit From a2cd15c2411624a7a97bad60d98d7e0a1e5002a6 Mon Sep 17 00:00:00 2001 From: Mika Kahola Date: Tue, 10 Oct 2023 12:52:33 +0300 Subject: drm/i915/lnl: Remove watchdog timers for PSR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Watchdog timers for Lunarlake HW were removed for PSR/PSR2 The patch removes the use of these timers from the driver code. BSpec: 69895 v2: Reword commit message (Ville) Drop HPD mask from LNL (Ville) Revise masking logic (Jouni) v3: Revise commit message (Ville) Revert HPD mask removal as irrelevant for this patch (Ville) Signed-off-by: Mika Kahola Reviewed-by: Jouni Högander Signed-off-by: Jouni Högander Link: https://patchwork.freedesktop.org/patch/msgid/20231010095233.590613-1-mika.kahola@intel.com --- drivers/gpu/drm/i915/display/intel_psr.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index bb65881e87cc..4f1f31fc9529 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -676,7 +676,9 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) val |= EDP_PSR_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); - val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time); + if (DISPLAY_VER(dev_priv) < 20) + val |= EDP_PSR_MAX_SLEEP_TIME(max_sleep_time); + if (IS_HASWELL(dev_priv)) val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; @@ -1400,8 +1402,10 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, */ mask = EDP_PSR_DEBUG_MASK_MEMUP | EDP_PSR_DEBUG_MASK_HPD | - EDP_PSR_DEBUG_MASK_LPSP | - EDP_PSR_DEBUG_MASK_MAX_SLEEP; + EDP_PSR_DEBUG_MASK_LPSP; + + if (DISPLAY_VER(dev_priv) < 20) + mask |= EDP_PSR_DEBUG_MASK_MAX_SLEEP; /* * No separate pipe reg write mask on hsw/bdw, so have to unmask all -- cgit From bcdcae63274047dea5acf27432bbceb8191d012e Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 9 Oct 2023 16:22:01 +0300 Subject: drm/i915/dsb: Allocate command buffer from local memory MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Using system memory for the DSB command buffer doesn't appear to work. On DG2 it seems like the hardware internally replaces the actual memory reads with zeroes, and so we end up executing a bunch of NOOPs instead of whatever commands we put in the buffer. To determine that I measured the time it takes to execute the instructions, and the results are always more or less consistent with executing a buffer full of NOOPs from local memory. Another theory I considered was some kind of cache coherency issue. Looks like i915_gem_object_pin_map_unlocked() will in fact give you a WB mapping for system memory on DGFX regardless of what mapping mode was requested (WC in case of the DSB code). But clflush did not change the behaviour at all, so that theory seems moot. On DG1 it looks like the hardware might actually be fetching data from system memory as the logs indicate that we just get underruns. But that is equally bad, so doesn't look like we can really use system memory on DG1 either. Thus always allocate the DSB command buffer from local memory on discrete GPUs. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20231009132204.15098-1-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_dsb.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 3e32aa49b8eb..7410ba3126f9 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -5,6 +5,7 @@ */ #include "gem/i915_gem_internal.h" +#include "gem/i915_gem_lmem.h" #include "i915_drv.h" #include "i915_irq.h" @@ -461,7 +462,11 @@ struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, /* ~1 qword per instruction, full cachelines */ size = ALIGN(max_cmds * 8, CACHELINE_BYTES); - obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size)); + if (HAS_LMEM(i915)) + obj = i915_gem_object_create_lmem(i915, PAGE_ALIGN(size), + I915_BO_ALLOC_CONTIGUOUS); + else + obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size)); if (IS_ERR(obj)) goto out_put_rpm; -- cgit From 631b117ea8c3b7d4ec21ece69be6c465e79330fa Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 9 Oct 2023 16:22:02 +0300 Subject: drm/i915/dsb: Correct DSB command buffer cache coherency settings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The display engine does not snoop the caches so we should mark the DSB command buffer as I915_CACHE_NONE. i915_gem_object_create_internal() always gives us I915_CACHE_LLC on LLC platforms. And to make things 100% correct we should also clflush at the end, if necessary. Note that currently this is a non-issue as we always write the command buffer through a WC mapping, so a cache flush is not actually needed. But we might actually want to consider a WB mapping since we also end up reading from the command buffer (in the indexed reg write handling). Either that or we should do something else to avoid those reads (might actually be even more sensible on DGFX since we end up reading over PCIe). But we should measure the overhead first... Anyways, no real harm in adding the belts and suspenders here so that the code will work correctly regardless of how we map the buffer. If we do get a WC mapping (as we request) i915_gem_object_flush_map() will be a nop. Well, apart form a wmb() which may just flush the WC buffer a bit earlier than would otherwise happen (at the latest the mmio accesses would trigger the WC flush). Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20231009132204.15098-2-ville.syrjala@linux.intel.com Reviewed-by: Uma Shankar --- drivers/gpu/drm/i915/display/intel_dsb.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c index 7410ba3126f9..78b6fe24dcd8 100644 --- a/drivers/gpu/drm/i915/display/intel_dsb.c +++ b/drivers/gpu/drm/i915/display/intel_dsb.c @@ -316,6 +316,8 @@ void intel_dsb_finish(struct intel_dsb *dsb) DSB_FORCE_DEWAKE, 0); intel_dsb_align_tail(dsb); + + i915_gem_object_flush_map(dsb->vma->obj); } static int intel_dsb_dewake_scanline(const struct intel_crtc_state *crtc_state) @@ -462,13 +464,18 @@ struct intel_dsb *intel_dsb_prepare(const struct intel_crtc_state *crtc_state, /* ~1 qword per instruction, full cachelines */ size = ALIGN(max_cmds * 8, CACHELINE_BYTES); - if (HAS_LMEM(i915)) + if (HAS_LMEM(i915)) { obj = i915_gem_object_create_lmem(i915, PAGE_ALIGN(size), I915_BO_ALLOC_CONTIGUOUS); - else + if (IS_ERR(obj)) + goto out_put_rpm; + } else { obj = i915_gem_object_create_internal(i915, PAGE_ALIGN(size)); - if (IS_ERR(obj)) - goto out_put_rpm; + if (IS_ERR(obj)) + goto out_put_rpm; + + i915_gem_object_set_cache_coherency(obj, I915_CACHE_NONE); + } vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, 0); if (IS_ERR(vma)) { -- cgit From 34d8311f4a1c464ae0ce4470f2e3932c1a40d83e Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Mon, 9 Oct 2023 16:22:03 +0300 Subject: drm/i915/dsb: Re-instate DSB for LUT updates MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit With all the known issues sorted out we can start to use DSB to load the LUTs. Reviewed-by: Uma Shankar Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20231009132204.15098-3-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_color.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 2a2a163ea652..1d26be54ddfc 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -1895,9 +1895,6 @@ void intel_color_prepare_commit(struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); - /* FIXME DSB has issues loading LUTs, disable it for now */ - return; - if (!crtc_state->hw.active || intel_crtc_needs_modeset(crtc_state)) return; -- cgit From 90780a633cec2c904adbd9027f003d7eea89254b Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Wed, 11 Oct 2023 20:16:04 +0300 Subject: drm/i915/dp: Sanitize DPCD revision check in intel_dp_get_dsc_sink_cap() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Check only the eDP or the DP specific DPCD revision depending on the sink type. Pass the corresponding revision to the function, which allows getting the DSC caps of a branch device (in an MST topology, which has its own DPCD and so DPCD revision). While at it use DP_DPCD_REV_14 instead of open coding it and for clarity add a separate function to read out the DSC capability on eDP. v2: - Use DP_DPCD_REV_14 instead of open coding it. (Stan) - Check EDP_DCPD_REV/DPCD_REV in a clearer way. (Ville) v3: - Fix the read-out for eDP in intel_dp_detect(). Cc: Ville Syrjälä Reviewed-by: Stanislav Lisovskiy (v1) Reviewed-by: Ville Syrjälä (v2) Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231011171606.2540078-1-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 81 ++++++++++++++++++++++----------- 1 file changed, 55 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index f0f43aeabd21..a010e021c48c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3467,7 +3467,23 @@ bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; } -static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) +static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, + u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + if (drm_dp_dpcd_read(aux, DP_DSC_SUPPORT, dsc_dpcd, + DP_DSC_RECEIVER_CAP_SIZE) < 0) { + drm_err(aux->drm_dev, + "Failed to read DPCD register 0x%x\n", + DP_DSC_SUPPORT); + return; + } + + drm_dbg_kms(aux->drm_dev, "DSC DPCD: %*ph\n", + DP_DSC_RECEIVER_CAP_SIZE, + dsc_dpcd); +} + +static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -3480,30 +3496,27 @@ static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) /* Clear fec_capable to avoid using stale values */ intel_dp->fec_capable = 0; - /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ - if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || - intel_dp->edp_dpcd[0] >= DP_EDP_14) { - if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, - intel_dp->dsc_dpcd, - sizeof(intel_dp->dsc_dpcd)) < 0) - drm_err(&i915->drm, - "Failed to read DPCD register 0x%x\n", - DP_DSC_SUPPORT); - - drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n", - (int)sizeof(intel_dp->dsc_dpcd), - intel_dp->dsc_dpcd); + if (dpcd_rev < DP_DPCD_REV_14) + return; - /* FEC is supported only on DP 1.4 */ - if (!intel_dp_is_edp(intel_dp) && - drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, - &intel_dp->fec_capable) < 0) - drm_err(&i915->drm, - "Failed to read FEC DPCD register\n"); + intel_dp_read_dsc_dpcd(&intel_dp->aux, intel_dp->dsc_dpcd); - drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", - intel_dp->fec_capable); + if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, + &intel_dp->fec_capable) < 0) { + drm_err(&i915->drm, "Failed to read FEC DPCD register\n"); + return; } + + drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", + intel_dp->fec_capable); +} + +static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_dp *intel_dp) +{ + if (edp_dpcd_rev < DP_EDP_14) + return; + + intel_dp_read_dsc_dpcd(&intel_dp->aux, intel_dp->dsc_dpcd); } static void intel_edp_mso_mode_fixup(struct intel_connector *connector, @@ -3674,7 +3687,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) /* Read the eDP DSC DPCD registers */ if (HAS_DSC(dev_priv)) - intel_dp_get_dsc_sink_cap(intel_dp); + intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], + intel_dp); /* * If needed, program our source OUI so we can make various Intel-specific AUX services @@ -5342,6 +5356,23 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) false); } +static void +intel_dp_detect_dsc_caps(struct intel_dp *intel_dp) +{ + struct drm_i915_private *i915 = dp_to_i915(intel_dp); + + /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ + if (!HAS_DSC(i915)) + return; + + if (intel_dp_is_edp(intel_dp)) + intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], + intel_dp); + else + intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], + intel_dp); +} + static int intel_dp_detect(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx, @@ -5386,9 +5417,7 @@ intel_dp_detect(struct drm_connector *connector, goto out; } - /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ - if (HAS_DSC(dev_priv)) - intel_dp_get_dsc_sink_cap(intel_dp); + intel_dp_detect_dsc_caps(intel_dp); intel_dp_configure_mst(intel_dp); -- cgit From 7389829f212d30d9588b969ff4a7b4d0005720a1 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Wed, 11 Oct 2023 20:16:05 +0300 Subject: drm/i915/dp: Store DSC DPCD capabilities in the connector MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In an MST topology the DSC capabilities are specific to each connector, retrieved either from the sink if it decompresses the stream, or from a branch device between the source and the sink in case this branch device does the decompression. Accordingly each connector needs to cache its own DSC DPCD and FEC capabilities, along with the AUX device through which the decompression can be enabled. This patch prepares for that by storing the capabilities and the DSC AUX device in the connector, for now these just matching the version stored in intel_dp. The follow-up patches will convert all users to look up these in the connector instead of intel_dp, after which the intel_dp copies are removed. v2: - Rebased on intel_edp_get_dsc_sink_cap() addition in previous patch. v3: - Rebased on read-out fix for eDP in previous patch. Reviewed-by: Stanislav Lisovskiy (v1) Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231011171606.2540078-2-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 6 +++ drivers/gpu/drm/i915/display/intel_dp.c | 58 +++++++++++++++------- 2 files changed, 47 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 8d8b2f8d37a9..d6600079bcf7 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -620,6 +620,12 @@ struct intel_connector { struct intel_dp *mst_port; + struct { + struct drm_dp_aux *dsc_decompression_aux; + u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; + u8 fec_capability; + } dp; + /* Work struct to schedule a uevent on link train failure */ struct work_struct modeset_retry_work; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index a010e021c48c..857cee5a5be8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3483,7 +3483,8 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, dsc_dpcd); } -static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp) +static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, + struct intel_connector *connector) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -3491,32 +3492,46 @@ static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp) * Clear the cached register set to avoid using stale values * for the sinks that do not support DSC. */ - memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + memset(connector->dp.dsc_dpcd, 0, sizeof(connector->dp.dsc_dpcd)); /* Clear fec_capable to avoid using stale values */ - intel_dp->fec_capable = 0; + connector->dp.fec_capability = 0; if (dpcd_rev < DP_DPCD_REV_14) return; - intel_dp_read_dsc_dpcd(&intel_dp->aux, intel_dp->dsc_dpcd); + intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, + connector->dp.dsc_dpcd); - if (drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, - &intel_dp->fec_capable) < 0) { + if (drm_dp_dpcd_readb(connector->dp.dsc_decompression_aux, DP_FEC_CAPABILITY, + &connector->dp.fec_capability) < 0) { drm_err(&i915->drm, "Failed to read FEC DPCD register\n"); return; } drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", - intel_dp->fec_capable); + connector->dp.fec_capability); + + /* + * TODO: remove the following intel_dp copies once all users + * are converted to look up DSC DPCD/FEC capability via the + * connector. + */ + memcpy(intel_dp->dsc_dpcd, connector->dp.dsc_dpcd, + sizeof(intel_dp->dsc_dpcd)); + intel_dp->fec_capable = connector->dp.fec_capability; } -static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_dp *intel_dp) +static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_dp *intel_dp, + struct intel_connector *connector) { if (edp_dpcd_rev < DP_EDP_14) return; - intel_dp_read_dsc_dpcd(&intel_dp->aux, intel_dp->dsc_dpcd); + intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); + + memcpy(intel_dp->dsc_dpcd, connector->dp.dsc_dpcd, + sizeof(intel_dp->dsc_dpcd)); } static void intel_edp_mso_mode_fixup(struct intel_connector *connector, @@ -3608,7 +3623,7 @@ static void intel_edp_mso_init(struct intel_dp *intel_dp) } static bool -intel_edp_init_dpcd(struct intel_dp *intel_dp) +intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector) { struct drm_i915_private *dev_priv = to_i915(dp_to_dig_port(intel_dp)->base.base.dev); @@ -3688,7 +3703,8 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp) /* Read the eDP DSC DPCD registers */ if (HAS_DSC(dev_priv)) intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], - intel_dp); + intel_dp, + connector); /* * If needed, program our source OUI so we can make various Intel-specific AUX services @@ -5357,7 +5373,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp) } static void -intel_dp_detect_dsc_caps(struct intel_dp *intel_dp) +intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *connector) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -5367,10 +5383,10 @@ intel_dp_detect_dsc_caps(struct intel_dp *intel_dp) if (intel_dp_is_edp(intel_dp)) intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], - intel_dp); + intel_dp, connector); else intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], - intel_dp); + intel_dp, connector); } static int @@ -5379,7 +5395,9 @@ intel_dp_detect(struct drm_connector *connector, bool force) { struct drm_i915_private *dev_priv = to_i915(connector->dev); - struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); + struct intel_connector *intel_connector = + to_intel_connector(connector); + struct intel_dp *intel_dp = intel_attached_dp(intel_connector); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct intel_encoder *encoder = &dig_port->base; enum drm_connector_status status; @@ -5402,7 +5420,12 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); + /* + * TODO: Remove clearing the DPCD in intel_dp, once all + * user are converted to using the DPCD in connector. + */ memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); + memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd)); if (intel_dp->is_mst) { drm_dbg_kms(&dev_priv->drm, @@ -5417,7 +5440,7 @@ intel_dp_detect(struct drm_connector *connector, goto out; } - intel_dp_detect_dsc_caps(intel_dp); + intel_dp_detect_dsc_caps(intel_dp, intel_connector); intel_dp_configure_mst(intel_dp); @@ -6002,7 +6025,7 @@ static bool intel_edp_init_connector(struct intel_dp *intel_dp, intel_hpd_enable_detection(encoder); /* Cache DPCD and EDID for edp. */ - has_dpcd = intel_edp_init_dpcd(intel_dp); + has_dpcd = intel_edp_init_dpcd(intel_dp, intel_connector); if (!has_dpcd) { /* if this fails, presume the device is a ghost */ @@ -6176,6 +6199,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port, intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); intel_dp_aux_init(intel_dp); + intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; drm_dbg_kms(&dev_priv->drm, "Adding %s connector on [ENCODER:%d:%s]\n", -- cgit From 808b43fa7e56e94563b86af2703ba88ee156e3c2 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Tue, 10 Oct 2023 14:25:03 +0300 Subject: drm/i915/dp_mst: Set connector DSC capabilities and decompression AUX MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Similarly to eDP and SST-DP connectors read out the DSC capabilities for MST connectors as well. Atm these will match the root port's DSC caps and only used after a follow-up change enables the decompression for each stream separately (vs. the current way of enabling it only globally in the first branch device downstream of the root port). Reviewed-by: Stanislav Lisovskiy Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231010112504.2156789-3-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dp.h | 3 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++++++++++++++++++++++ 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 857cee5a5be8..c9d8fa4349b2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3483,8 +3483,8 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, dsc_dpcd); } -static void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, - struct intel_connector *connector) +void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, + struct intel_connector *connector) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 2cf3681bac64..bd9cb9680b4c 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -162,4 +162,7 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, bool dsc, struct link_config_limits *limits); +void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, + struct intel_connector *connector); + #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 73e397736463..e01f669d2c8a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1126,6 +1126,21 @@ static int intel_dp_mst_add_properties(struct intel_dp *intel_dp, return drm_connector_set_path_property(connector, pathprop); } +static void +intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp, + struct intel_connector *connector) +{ + u8 dpcd_caps[DP_RECEIVER_CAP_SIZE]; + + if (!connector->dp.dsc_decompression_aux) + return; + + if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0) + return; + + intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], intel_dp, connector); +} + static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) @@ -1159,6 +1174,14 @@ static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topolo drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); + /* + * TODO: set the AUX for the actual MST port decompressing the stream. + * At the moment the driver only supports enabling this globally in the + * first downstream MST branch, via intel_dp's (root port) AUX. + */ + intel_connector->dp.dsc_decompression_aux = &intel_dp->aux; + intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector); + for_each_pipe(dev_priv, pipe) { struct drm_encoder *enc = &intel_dp->mst_encoders[pipe]->base.base; -- cgit From 829d8a19437cdbaec19836835025833ebab232a2 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:12 +0300 Subject: drm/i915/dp: Use i915/intel connector local variables in i915_dsc_fec_support_show() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cache the i915 specific device and connector pointers in i915_dsc_fec_support_show(). v2: - s/Cahce/Cache typo in commit log. (Stan) Reviewed-by: Stanislav Lisovskiy Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-5-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index f6d7c4d45fae..cdadda327272 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1192,8 +1192,8 @@ DEFINE_SHOW_ATTRIBUTE(i915_lpsp_capability); static int i915_dsc_fec_support_show(struct seq_file *m, void *data) { - struct drm_connector *connector = m->private; - struct drm_device *dev = connector->dev; + struct intel_connector *connector = to_intel_connector(m->private); + struct drm_i915_private *i915 = to_i915(connector->base.dev); struct drm_crtc *crtc; struct intel_dp *intel_dp; struct drm_modeset_acquire_ctx ctx; @@ -1205,7 +1205,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) do { try_again = false; - ret = drm_modeset_lock(&dev->mode_config.connection_mutex, + ret = drm_modeset_lock(&i915->drm.mode_config.connection_mutex, &ctx); if (ret) { if (ret == -EDEADLK && !drm_modeset_backoff(&ctx)) { @@ -1214,8 +1214,8 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) } break; } - crtc = connector->state->crtc; - if (connector->status != connector_status_connected || !crtc) { + crtc = connector->base.state->crtc; + if (connector->base.status != connector_status_connected || !crtc) { ret = -ENODEV; break; } @@ -1230,7 +1230,7 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) } else if (ret) { break; } - intel_dp = intel_attached_dp(to_intel_connector(connector)); + intel_dp = intel_attached_dp(connector); crtc_state = to_intel_crtc_state(crtc->state); seq_printf(m, "DSC_Enabled: %s\n", str_yes_no(crtc_state->dsc.compression_enable)); -- cgit From 102c8013b6536d93506d85d6664968e51556102c Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:13 +0300 Subject: drm/i915/dp: Use connector DSC DPCD in i915_dsc_fec_support_show() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in i915_dsc_fec_support_show() instead of the version stored in the encoder. Atm the two are identical, but a follow-up patch will store the (MST) connector specific version in the connector. Reviewed-by: Stanislav Lisovskiy Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-6-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display_debugfs.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c index cdadda327272..1610c2b6a644 100644 --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c @@ -1235,19 +1235,19 @@ static int i915_dsc_fec_support_show(struct seq_file *m, void *data) seq_printf(m, "DSC_Enabled: %s\n", str_yes_no(crtc_state->dsc.compression_enable)); seq_printf(m, "DSC_Sink_Support: %s\n", - str_yes_no(drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd))); + str_yes_no(drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd))); seq_printf(m, "DSC_Output_Format_Sink_Support: RGB: %s YCBCR420: %s YCBCR444: %s\n", - str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, + str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, DP_DSC_RGB)), - str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, + str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, DP_DSC_YCbCr420_Native)), - str_yes_no(drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, + str_yes_no(drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, DP_DSC_YCbCr444))); seq_printf(m, "Force_DSC_Enable: %s\n", str_yes_no(intel_dp->force_dsc_en)); if (!intel_dp_is_edp(intel_dp)) seq_printf(m, "FEC_Sink_Support: %s\n", - str_yes_no(drm_dp_sink_supports_fec(intel_dp->fec_capable))); + str_yes_no(drm_dp_sink_supports_fec(connector->dp.fec_capability))); } while (try_again); drm_modeset_drop_locks(&ctx); -- cgit From f52bbfe2ac657c3bd82fdbdcdffc2c8054358b37 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:14 +0300 Subject: drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_max_bpp() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in intel_dp_dsc_compute_max_bpp() instead of the version stored in the encoder. Reviewed-by: Stanislav Lisovskiy Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-7-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 13 ++++++++----- drivers/gpu/drm/i915/display/intel_dp.h | 3 ++- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c9d8fa4349b2..01762d9ee5e1 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1215,7 +1215,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX); + pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, U8_MAX); /* * Output bpp is stored in 6.4 format so right shift by 4 to get the @@ -1577,9 +1577,10 @@ u8 intel_dp_dsc_max_src_input_bpc(struct drm_i915_private *i915) return 0; } -int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, + u8 max_req_bpc) { - struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *i915 = to_i915(connector->base.dev); int i, num_bpc; u8 dsc_bpc[3] = {0}; u8 dsc_max_bpc; @@ -1591,7 +1592,7 @@ int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc); - num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); for (i = 0; i < num_bpc; i++) { if (dsc_max_bpc >= dsc_bpc[i]) @@ -2056,6 +2057,8 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct link_config_limits *limits) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct intel_connector *connector = + to_intel_connector(conn_state->connector); int pipe_bpp, forced_bpp; int dsc_src_min_bpp, dsc_sink_min_bpp, dsc_min_bpp; int dsc_src_max_bpp, dsc_sink_max_bpp, dsc_max_bpp; @@ -2068,7 +2071,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, int max_bpc = min(limits->pipe.max_bpp / 3, (int)conn_state->max_requested_bpc); /* For eDP use max bpp that can be supported with DSC. */ - pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, max_bpc); + pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); if (!is_dsc_pipe_bpp_sufficient(i915, conn_state, limits, pipe_bpp)) { drm_dbg_kms(&i915->drm, "Computed BPC is not in DSC BPC limits\n"); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index bd9cb9680b4c..af87aa2a5ed6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -116,7 +116,8 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); -int intel_dp_dsc_compute_max_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, + u8 dsc_max_bpc); u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e01f669d2c8a..3ff429c30f30 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1003,7 +1003,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_dp, U8_MAX); + int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX); if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { dsc_max_compressed_bpp = -- cgit From 987c945ab2eef9529b56bda4ff6f0def98cd0238 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:15 +0300 Subject: drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_fec() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in intel_dp_supports_fec(). Reviewed-by: Stanislav Lisovskiy Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-8-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 01762d9ee5e1..274044eb9db8 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1370,10 +1370,11 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, } static bool intel_dp_supports_fec(struct intel_dp *intel_dp, + const struct intel_connector *connector, const struct intel_crtc_state *pipe_config) { return intel_dp_source_supports_fec(intel_dp, pipe_config) && - drm_dp_sink_supports_fec(intel_dp->fec_capable); + drm_dp_sink_supports_fec(connector->dp.fec_capability); } static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, @@ -2110,12 +2111,14 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); + const struct intel_connector *connector = + to_intel_connector(conn_state->connector); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; int ret; pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && - intel_dp_supports_fec(intel_dp, pipe_config); + intel_dp_supports_fec(intel_dp, connector, pipe_config); if (!intel_dp_supports_dsc(intel_dp, pipe_config)) return -EINVAL; -- cgit From 0d8665e068186b78028df67120fb99471c006ddb Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:16 +0300 Subject: drm/i915/dp: Use connector DSC DPCD in intel_dp_supports_dsc() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in intel_dp_supports_dsc(). Reviewed-by: Stanislav Lisovskiy Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-9-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 274044eb9db8..98fccce5c07e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1377,14 +1377,14 @@ static bool intel_dp_supports_fec(struct intel_dp *intel_dp, drm_dp_sink_supports_fec(connector->dp.fec_capability); } -static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, +static bool intel_dp_supports_dsc(const struct intel_connector *connector, const struct intel_crtc_state *crtc_state) { if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable) return false; return intel_dsc_source_support(crtc_state) && - drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); + drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd); } static int intel_dp_hdmi_compute_bpc(struct intel_dp *intel_dp, @@ -2120,7 +2120,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && intel_dp_supports_fec(intel_dp, connector, pipe_config); - if (!intel_dp_supports_dsc(intel_dp, pipe_config)) + if (!intel_dp_supports_dsc(connector, pipe_config)) return -EINVAL; if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) -- cgit From bb414c941bf07e127615bf3e775733c7e8d5a0b1 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:17 +0300 Subject: drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_max_sink_compressed_bppx16() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in intel_dp_dsc_max_sink_compressed_bppx16(). Reviewed-by: Stanislav Lisovskiy Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-10-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 98fccce5c07e..2eb7645410af 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1767,11 +1767,11 @@ static int dsc_compute_link_config(struct intel_dp *intel_dp, } static -u16 intel_dp_dsc_max_sink_compressed_bppx16(struct intel_dp *intel_dp, +u16 intel_dp_dsc_max_sink_compressed_bppx16(const struct intel_connector *connector, struct intel_crtc_state *pipe_config, int bpc) { - u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd); + u16 max_bppx16 = drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd); if (max_bppx16) return max_bppx16; @@ -1810,11 +1810,11 @@ static int dsc_sink_min_compressed_bpp(struct intel_crtc_state *pipe_config) return 0; } -static int dsc_sink_max_compressed_bpp(struct intel_dp *intel_dp, +static int dsc_sink_max_compressed_bpp(const struct intel_connector *connector, struct intel_crtc_state *pipe_config, int bpc) { - return intel_dp_dsc_max_sink_compressed_bppx16(intel_dp, + return intel_dp_dsc_max_sink_compressed_bppx16(connector, pipe_config, bpc) >> 4; } @@ -1913,6 +1913,7 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, } static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, + const struct intel_connector *connector, struct intel_crtc_state *pipe_config, struct link_config_limits *limits, int pipe_bpp, @@ -1930,7 +1931,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp, dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16)); dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); - dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3); + dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, pipe_bpp / 3); dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; dsc_joiner_max_bpp = get_max_compressed_bpp_with_joiner(i915, adjusted_mode->clock, @@ -2002,6 +2003,8 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, int timeslots) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); + const struct intel_connector *connector = + to_intel_connector(conn_state->connector); u8 max_req_bpc = conn_state->max_requested_bpc; u8 dsc_max_bpc, dsc_max_bpp; u8 dsc_min_bpc, dsc_min_bpp; @@ -2012,7 +2015,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, conn_state, limits); if (forced_bpp) { - ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, + ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, limits, forced_bpp, timeslots); if (ret == 0) { pipe_config->pipe_bpp = forced_bpp; @@ -2041,7 +2044,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, break; if (pipe_bpp > dsc_max_bpp) continue; - ret = dsc_compute_compressed_bpp(intel_dp, pipe_config, + ret = dsc_compute_compressed_bpp(intel_dp, connector, pipe_config, limits, pipe_bpp, timeslots); if (ret == 0) { pipe_config->pipe_bpp = pipe_bpp; @@ -2088,7 +2091,7 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16)); dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp); - dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3); + dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(connector, pipe_config, pipe_bpp / 3); dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp; dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16)); -- cgit From cc81951d9a2078a252ce8667d3b47ef8aa6934d0 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:18 +0300 Subject: drm/i915/dp: Pass connector DSC DPCD to drm_dp_dsc_sink_supported_input_bpcs() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in drm_dp_dsc_sink_supported_input_bpcs(). Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-11-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 2eb7645410af..33de923e584d 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2037,7 +2037,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, * Get the maximum DSC bpc that will be supported by any valid * link configuration and compressed bpp. */ - num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, dsc_bpc); + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); for (i = 0; i < num_bpc; i++) { pipe_bpp = dsc_bpc[i] * 3; if (pipe_bpp < dsc_min_bpp) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 3ff429c30f30..303734ab7ef4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -185,8 +185,6 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, struct drm_connector_state *conn_state, struct link_config_limits *limits) { - struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); - struct intel_dp *intel_dp = &intel_mst->primary->dp; struct intel_connector *connector = to_intel_connector(conn_state->connector); struct drm_i915_private *i915 = to_i915(connector->base.dev); @@ -209,7 +207,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp); min_bpp = limits->pipe.min_bpp; - num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd, dsc_bpc); drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n", -- cgit From 6a60a8fa7c3af598885a554d1966ec0723ed39a6 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:19 +0300 Subject: drm/i915/dp: Pass only the required i915 to intel_dp_source_dsc_version_minor() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel_dp_source_dsc_version_minor() only requires the i915 pointer, so pass only this to the function. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-12-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 33de923e584d..0d15e3f97dca 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1603,10 +1603,8 @@ int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, return 0; } -static int intel_dp_source_dsc_version_minor(struct intel_dp *intel_dp) +static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915) { - struct drm_i915_private *i915 = dp_to_i915(intel_dp); - return DISPLAY_VER(i915) >= 14 ? 2 : 1; } @@ -1666,7 +1664,7 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; vdsc_cfg->dsc_version_minor = - min(intel_dp_source_dsc_version_minor(intel_dp), + min(intel_dp_source_dsc_version_minor(i915), intel_dp_sink_dsc_version_minor(intel_dp)); if (vdsc_cfg->convert_rgb) vdsc_cfg->convert_rgb = @@ -1697,6 +1695,7 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, enum intel_output_format output_format) { + struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 sink_dsc_format; switch (output_format) { @@ -1707,7 +1706,7 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, sink_dsc_format = DP_DSC_YCbCr444; break; case INTEL_OUTPUT_FORMAT_YCBCR420: - if (min(intel_dp_source_dsc_version_minor(intel_dp), + if (min(intel_dp_source_dsc_version_minor(i915), intel_dp_sink_dsc_version_minor(intel_dp)) < 2) return false; sink_dsc_format = DP_DSC_YCbCr420_Native; -- cgit From 11a33d6b265faf898ae591a535b65fe9ca0eb532 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:20 +0300 Subject: drm/i915/dp: Pass only the required DSC DPCD to intel_dp_sink_dsc_version_minor() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel_dp_sink_dsc_version_minor() only requires the DSC DPCD, so pass only this to the function. Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-13-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0d15e3f97dca..744c73a5a796 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1608,9 +1608,9 @@ static int intel_dp_source_dsc_version_minor(struct drm_i915_private *i915) return DISPLAY_VER(i915) >= 14 ? 2 : 1; } -static int intel_dp_sink_dsc_version_minor(struct intel_dp *intel_dp) +static int intel_dp_sink_dsc_version_minor(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) { - return (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> + return (dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT; } @@ -1665,7 +1665,7 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; vdsc_cfg->dsc_version_minor = min(intel_dp_source_dsc_version_minor(i915), - intel_dp_sink_dsc_version_minor(intel_dp)); + intel_dp_sink_dsc_version_minor(intel_dp->dsc_dpcd)); if (vdsc_cfg->convert_rgb) vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & @@ -1707,7 +1707,7 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, break; case INTEL_OUTPUT_FORMAT_YCBCR420: if (min(intel_dp_source_dsc_version_minor(i915), - intel_dp_sink_dsc_version_minor(intel_dp)) < 2) + intel_dp_sink_dsc_version_minor(intel_dp->dsc_dpcd)) < 2) return false; sink_dsc_format = DP_DSC_YCbCr420_Native; break; -- cgit From 2c4907c2e604d4eecd302c791ca9bddb6b31279c Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:21 +0300 Subject: drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_params() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in intel_dp_dsc_compute_params(). Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-14-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 744c73a5a796..324fdfb5513e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1636,11 +1636,10 @@ static int intel_dp_get_slice_height(int vactive) return 2; } -static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, +static int intel_dp_dsc_compute_params(const struct intel_connector *connector, struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(encoder->base.dev); - struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + struct drm_i915_private *i915 = to_i915(connector->base.dev); struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; u8 line_buf_depth; int ret; @@ -1661,17 +1660,17 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return ret; vdsc_cfg->dsc_version_major = - (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & + (connector->dp.dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; vdsc_cfg->dsc_version_minor = min(intel_dp_source_dsc_version_minor(i915), - intel_dp_sink_dsc_version_minor(intel_dp->dsc_dpcd)); + intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)); if (vdsc_cfg->convert_rgb) vdsc_cfg->convert_rgb = - intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & + connector->dp.dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & DP_DSC_RGB; - line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); + line_buf_depth = drm_dp_dsc_sink_line_buf_depth(connector->dp.dsc_dpcd); if (!line_buf_depth) { drm_dbg_kms(&i915->drm, "DSC Sink Line Buffer Depth invalid\n"); @@ -1686,7 +1685,7 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; vdsc_cfg->block_pred_enable = - intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & + connector->dp.dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & DP_DSC_BLK_PREDICTION_IS_SUPPORTED; return drm_dsc_compute_rc_parameters(vdsc_cfg); @@ -2182,7 +2181,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (pipe_config->bigjoiner_pipes || pipe_config->dsc.slice_count > 1) pipe_config->dsc.dsc_split = true; - ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); + ret = intel_dp_dsc_compute_params(connector, pipe_config); if (ret < 0) { drm_dbg_kms(&dev_priv->drm, "Cannot compute valid DSC parameters for Input Bpp = %d " -- cgit From 926b726c3d61153bf8e1702d4cc0a37606fd3017 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:22 +0300 Subject: drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_supports_format() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in intel_dp_dsc_supports_format(). Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-15-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 324fdfb5513e..8e42950bbd4b 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1691,10 +1691,10 @@ static int intel_dp_dsc_compute_params(const struct intel_connector *connector, return drm_dsc_compute_rc_parameters(vdsc_cfg); } -static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, +static bool intel_dp_dsc_supports_format(const struct intel_connector *connector, enum intel_output_format output_format) { - struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *i915 = to_i915(connector->base.dev); u8 sink_dsc_format; switch (output_format) { @@ -1706,7 +1706,7 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, break; case INTEL_OUTPUT_FORMAT_YCBCR420: if (min(intel_dp_source_dsc_version_minor(i915), - intel_dp_sink_dsc_version_minor(intel_dp->dsc_dpcd)) < 2) + intel_dp_sink_dsc_version_minor(connector->dp.dsc_dpcd)) < 2) return false; sink_dsc_format = DP_DSC_YCbCr420_Native; break; @@ -1714,7 +1714,7 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, return false; } - return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); + return drm_dp_dsc_sink_supports_format(connector->dp.dsc_dpcd, sink_dsc_format); } static bool is_bw_sufficient_for_dsc_config(u16 compressed_bpp, u32 link_clock, @@ -2124,7 +2124,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_supports_dsc(connector, pipe_config)) return -EINVAL; - if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) + if (!intel_dp_dsc_supports_format(connector, pipe_config->output_format)) return -EINVAL; /* -- cgit From 7bca1b801e48176283c5658e9092ea170fd7320e Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:23 +0300 Subject: drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_get_slice_count() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in intel_dp_dsc_get_slice_count(). Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-16-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 12 ++++++------ drivers/gpu/drm/i915/display/intel_dp.h | 2 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8e42950bbd4b..c6f0f959b4ad 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -823,11 +823,11 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, return bits_per_pixel; } -u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, +u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, bool bigjoiner) { - struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *i915 = to_i915(connector->base.dev); u8 min_slice_count, i; int max_slice_width; @@ -845,7 +845,7 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, if (mode_clock >= ((i915->display.cdclk.max_cdclk_freq * 85) / 100)) min_slice_count = max_t(u8, min_slice_count, 2); - max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); + max_slice_width = drm_dp_dsc_sink_max_slice_width(connector->dp.dsc_dpcd); if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { drm_dbg_kms(&i915->drm, "Unsupported slice width %d by DP DSC Sink device\n", @@ -862,7 +862,7 @@ u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner; if (test_slice_count > - drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false)) + drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, false)) break; /* big joiner needs small joiner to be enabled */ @@ -1238,7 +1238,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, output_format, pipe_bpp, 64); dsc_slice_count = - intel_dp_dsc_get_slice_count(intel_dp, + intel_dp_dsc_get_slice_count(connector, target_clock, mode->hdisplay, bigjoiner); @@ -2161,7 +2161,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, u8 dsc_dp_slice_count; dsc_dp_slice_count = - intel_dp_dsc_get_slice_count(intel_dp, + intel_dp_dsc_get_slice_count(connector, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index af87aa2a5ed6..51edb587e4d2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -125,7 +125,7 @@ u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, enum intel_output_format output_format, u32 pipe_bpp, u32 timeslots); -u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, +u8 intel_dp_dsc_get_slice_count(const struct intel_connector *connector, int mode_clock, int mode_hdisplay, bool bigjoiner); bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 303734ab7ef4..115d4d8870b0 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1014,7 +1014,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, INTEL_OUTPUT_FORMAT_RGB, pipe_bpp, 64); dsc_slice_count = - intel_dp_dsc_get_slice_count(intel_dp, + intel_dp_dsc_get_slice_count(intel_connector, target_clock, mode->hdisplay, bigjoiner); -- cgit From 031c19b52c20f2b3a8fb7bbff21b276d46e70c4f Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:24 +0300 Subject: drm/i915/dp: Use connector DSC DPCD in intel_dp_mode_valid() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in intel_dp_mode_valid(). Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-17-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index c6f0f959b4ad..8ebc54f167cc 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1205,7 +1205,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, intel_dp_mode_min_output_bpp(connector, mode)); if (HAS_DSC(dev_priv) && - drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + drm_dp_sink_supports_dsc(connector->dp.dsc_dpcd)) { enum intel_output_format sink_format, output_format; int pipe_bpp; @@ -1223,11 +1223,11 @@ intel_dp_mode_valid(struct drm_connector *_connector, */ if (intel_dp_is_edp(intel_dp)) { dsc_max_compressed_bpp = - drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; + drm_edp_dsc_sink_output_bpp(connector->dp.dsc_dpcd) >> 4; dsc_slice_count = - drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, + drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, true); - } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { + } else if (drm_dp_sink_supports_fec(connector->dp.fec_capability)) { dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(dev_priv, max_link_clock, -- cgit From 2bd3d20ffa4e297923160bbccda50bf7685eba57 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:25 +0300 Subject: drm/i915/dp: Use connector DSC DPCD in intel_dp_dsc_compute_config() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in intel_dp_dsc_compute_config(). Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-18-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 8ebc54f167cc..54a9ac555f18 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2150,7 +2150,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, /* Calculate Slice count */ if (intel_dp_is_edp(intel_dp)) { pipe_config->dsc.slice_count = - drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, + drm_dp_dsc_sink_max_slice_count(connector->dp.dsc_dpcd, true); if (!pipe_config->dsc.slice_count) { drm_dbg_kms(&dev_priv->drm, "Unsupported Slice Count %d\n", -- cgit From d19daffc89fe50f1a3ab3007e006d0f97544a27c Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Fri, 6 Oct 2023 16:37:26 +0300 Subject: drm/i915/dp_mst: Use connector DSC DPCD in intel_dp_mst_mode_valid_ctx() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the connector's DSC DPCD capabilities in intel_dp_mst_mode_valid_ctx(). Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231006133727.1822579-19-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 115d4d8870b0..a065388c2199 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -996,14 +996,14 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, } if (DISPLAY_VER(dev_priv) >= 10 && - drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) { /* * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX); - if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { + if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) { dsc_max_compressed_bpp = intel_dp_dsc_get_max_compressed_bpp(dev_priv, max_link_clock, -- cgit From 02c8d561dbbf4258c3314ddb85fe609990b61316 Mon Sep 17 00:00:00 2001 From: Imre Deak Date: Wed, 11 Oct 2023 20:16:06 +0300 Subject: drm/i915/dp: Remove unused DSC caps from intel_dp MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The previous patches converted all users of the DSC DPCD caps to look these up from the connector, so remove the version stored in intel_dp. A follow-up patchset will read out the MST connector specific capabilities in intel_dp_add_mst_connector() -> intel_dp_mst_read_decompression_port_dsc_caps(). v2: - Rebased on intel_edp_get_dsc_sink_cap() addition in the patchset. v3: - Rebased on read-out fix for eDP in the patchset. Reviewed-by: Stanislav Lisovskiy (v1) Reviewed-by: Ville Syrjälä Signed-off-by: Imre Deak Link: https://patchwork.freedesktop.org/patch/msgid/20231011171606.2540078-3-imre.deak@intel.com --- drivers/gpu/drm/i915/display/intel_display_types.h | 2 -- drivers/gpu/drm/i915/display/intel_dp.c | 30 ++++------------------ drivers/gpu/drm/i915/display/intel_dp.h | 3 +-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- 4 files changed, 7 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index d6600079bcf7..65ea37fe8cff 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1725,10 +1725,8 @@ struct intel_dp { u8 psr_dpcd[EDP_PSR_RECEIVER_CAP_SIZE]; u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]; u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; - u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]; u8 lttpr_common_caps[DP_LTTPR_COMMON_CAP_SIZE]; u8 lttpr_phy_caps[DP_MAX_LTTPR_COUNT][DP_LTTPR_PHY_CAP_SIZE]; - u8 fec_capable; u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]; /* source rates */ int num_source_rates; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 54a9ac555f18..d324204c1ce6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -3490,10 +3490,9 @@ static void intel_dp_read_dsc_dpcd(struct drm_dp_aux *aux, dsc_dpcd); } -void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, - struct intel_connector *connector) +void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector) { - struct drm_i915_private *i915 = dp_to_i915(intel_dp); + struct drm_i915_private *i915 = to_i915(connector->base.dev); /* * Clear the cached register set to avoid using stale values @@ -3518,27 +3517,14 @@ void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", connector->dp.fec_capability); - - /* - * TODO: remove the following intel_dp copies once all users - * are converted to look up DSC DPCD/FEC capability via the - * connector. - */ - memcpy(intel_dp->dsc_dpcd, connector->dp.dsc_dpcd, - sizeof(intel_dp->dsc_dpcd)); - intel_dp->fec_capable = connector->dp.fec_capability; } -static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_dp *intel_dp, - struct intel_connector *connector) +static void intel_edp_get_dsc_sink_cap(u8 edp_dpcd_rev, struct intel_connector *connector) { if (edp_dpcd_rev < DP_EDP_14) return; intel_dp_read_dsc_dpcd(connector->dp.dsc_decompression_aux, connector->dp.dsc_dpcd); - - memcpy(intel_dp->dsc_dpcd, connector->dp.dsc_dpcd, - sizeof(intel_dp->dsc_dpcd)); } static void intel_edp_mso_mode_fixup(struct intel_connector *connector, @@ -3710,7 +3696,6 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *connector /* Read the eDP DSC DPCD registers */ if (HAS_DSC(dev_priv)) intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], - intel_dp, connector); /* @@ -5390,10 +5375,10 @@ intel_dp_detect_dsc_caps(struct intel_dp *intel_dp, struct intel_connector *conn if (intel_dp_is_edp(intel_dp)) intel_edp_get_dsc_sink_cap(intel_dp->edp_dpcd[0], - intel_dp, connector); + connector); else intel_dp_get_dsc_sink_cap(intel_dp->dpcd[DP_DPCD_REV], - intel_dp, connector); + connector); } static int @@ -5427,11 +5412,6 @@ intel_dp_detect(struct drm_connector *connector, if (status == connector_status_disconnected) { memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); - /* - * TODO: Remove clearing the DPCD in intel_dp, once all - * user are converted to using the DPCD in connector. - */ - memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); memset(intel_connector->dp.dsc_dpcd, 0, sizeof(intel_connector->dp.dsc_dpcd)); if (intel_dp->is_mst) { diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 51edb587e4d2..484aea215a25 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -163,7 +163,6 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp, bool dsc, struct link_config_limits *limits); -void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_dp *intel_dp, - struct intel_connector *connector); +void intel_dp_get_dsc_sink_cap(u8 dpcd_rev, struct intel_connector *connector); #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index a065388c2199..47f1efb50ea2 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -1136,7 +1136,7 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp, if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0) return; - intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], intel_dp, connector); + intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector); } static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, -- cgit From eebc1525bacbd4faa46a99c37329414fb17cfa51 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 12 Oct 2023 15:24:37 +0300 Subject: drm/i915/display: Clean up zero initializers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20231012122442.15718-2-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/display/intel_acpi.c | 2 +- drivers/gpu/drm/i915/display/intel_cx0_phy.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.c | 6 +++--- drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c | 4 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +- drivers/gpu/drm/i915/display/intel_gmbus.c | 2 +- drivers/gpu/drm/i915/display/intel_plane_initial.c | 2 +- drivers/gpu/drm/i915/display/intel_sdvo.c | 2 +- drivers/gpu/drm/i915/display/intel_snps_phy.c | 2 +- drivers/gpu/drm/i915/display/intel_wm.c | 2 +- 10 files changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_acpi.c b/drivers/gpu/drm/i915/display/intel_acpi.c index 9df78e7caa2b..0aa3999374e2 100644 --- a/drivers/gpu/drm/i915/display/intel_acpi.c +++ b/drivers/gpu/drm/i915/display/intel_acpi.c @@ -153,7 +153,7 @@ static acpi_handle intel_dsm_pci_probe(struct pci_dev *pdev) static bool intel_dsm_detect(void) { acpi_handle dhandle = NULL; - char acpi_method_name[255] = { 0 }; + char acpi_method_name[255] = {}; struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name}; struct pci_dev *pdev = NULL; int vga_count = 0; diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c index 6e6a1818071e..d414f6b7f993 100644 --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c @@ -3009,7 +3009,7 @@ void intel_c10pll_state_verify(struct intel_atomic_state *state, struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct intel_c10pll_state mpllb_hw_state = { 0 }; + struct intel_c10pll_state mpllb_hw_state = {}; const struct intel_c10pll_state *mpllb_sw_state = &new_crtc_state->cx0pll_state.c10; struct intel_encoder *encoder; enum phy phy; diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index d324204c1ce6..6f46b6692e43 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1583,7 +1583,7 @@ int intel_dp_dsc_compute_max_bpp(const struct intel_connector *connector, { struct drm_i915_private *i915 = to_i915(connector->base.dev); int i, num_bpc; - u8 dsc_bpc[3] = {0}; + u8 dsc_bpc[3] = {}; u8 dsc_max_bpc; dsc_max_bpc = intel_dp_dsc_max_src_input_bpc(i915); @@ -2006,7 +2006,7 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, u8 max_req_bpc = conn_state->max_requested_bpc; u8 dsc_max_bpc, dsc_max_bpp; u8 dsc_min_bpc, dsc_min_bpp; - u8 dsc_bpc[3] = {0}; + u8 dsc_bpc[3] = {}; int forced_bpp, pipe_bpp; int num_bpc, i, ret; @@ -2940,7 +2940,7 @@ intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 oui[] = { 0x00, 0xaa, 0x01 }; - u8 buf[3] = { 0 }; + u8 buf[3] = {}; /* * During driver init, we want to be careful and avoid changing the source OUI if it's diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c index 95cc5251843e..26ea7e9f1b89 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_backlight.c @@ -169,7 +169,7 @@ intel_dp_aux_hdr_get_backlight(struct intel_connector *connector, enum pipe pipe struct intel_panel *panel = &connector->panel; struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); u8 tmp; - u8 buf[2] = { 0 }; + u8 buf[2] = {}; if (drm_dp_dpcd_readb(&intel_dp->aux, INTEL_EDP_HDR_GETSET_CTRL_PARAMS, &tmp) != 1) { drm_err(&i915->drm, "[CONNECTOR:%d:%s] Failed to read current backlight mode from DPCD\n", @@ -204,7 +204,7 @@ intel_dp_aux_hdr_set_aux_backlight(const struct drm_connector_state *conn_state, struct intel_connector *connector = to_intel_connector(conn_state->connector); struct drm_device *dev = connector->base.dev; struct intel_dp *intel_dp = enc_to_intel_dp(connector->encoder); - u8 buf[4] = { 0 }; + u8 buf[4] = {}; buf[0] = level & 0xFF; buf[1] = (level & 0xFF00) >> 8; diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 47f1efb50ea2..7b4628f4f124 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -192,7 +192,7 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, &crtc_state->hw.adjusted_mode; int slots = -EINVAL; int i, num_bpc; - u8 dsc_bpc[3] = {0}; + u8 dsc_bpc[3] = {}; int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; u8 dsc_max_bpc; bool need_timeslot_recalc = false; diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c index 801fabbccf7e..40d7b6f3f489 100644 --- a/drivers/gpu/drm/i915/display/intel_gmbus.c +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c @@ -781,7 +781,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter) struct intel_gmbus *bus = to_intel_gmbus(adapter); struct drm_i915_private *i915 = bus->i915; u8 cmd = DRM_HDCP_DDC_AKSV; - u8 buf[DRM_HDCP_KSV_LEN] = { 0 }; + u8 buf[DRM_HDCP_KSV_LEN] = {}; struct i2c_msg msgs[] = { { .addr = DRM_HDCP_DDC_ADDR, diff --git a/drivers/gpu/drm/i915/display/intel_plane_initial.c b/drivers/gpu/drm/i915/display/intel_plane_initial.c index 451a642e106e..a55c09cbd0e4 100644 --- a/drivers/gpu/drm/i915/display/intel_plane_initial.c +++ b/drivers/gpu/drm/i915/display/intel_plane_initial.c @@ -166,7 +166,7 @@ intel_alloc_initial_plane_obj(struct intel_crtc *crtc, { struct drm_device *dev = crtc->base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct drm_mode_fb_cmd2 mode_cmd = { 0 }; + struct drm_mode_fb_cmd2 mode_cmd = {}; struct drm_framebuffer *fb = &plane_config->fb->base; struct i915_vma *vma; diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c index 35137e978591..a636f42ceae5 100644 --- a/drivers/gpu/drm/i915/display/intel_sdvo.c +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c @@ -649,7 +649,7 @@ intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo) { - struct intel_sdvo_set_target_input_args targets = {0}; + struct intel_sdvo_set_target_input_args targets = {}; return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_TARGET_INPUT, &targets, sizeof(targets)); diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c index c0285365efae..ce5a73a4cc89 100644 --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c @@ -1998,7 +1998,7 @@ void intel_mpllb_state_verify(struct intel_atomic_state *state, struct drm_i915_private *i915 = to_i915(state->base.dev); const struct intel_crtc_state *new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc); - struct intel_mpllb_state mpllb_hw_state = { 0 }; + struct intel_mpllb_state mpllb_hw_state = {}; const struct intel_mpllb_state *mpllb_sw_state = &new_crtc_state->mpllb_state; struct intel_encoder *encoder; diff --git a/drivers/gpu/drm/i915/display/intel_wm.c b/drivers/gpu/drm/i915/display/intel_wm.c index b615449e70b4..82c4933ad507 100644 --- a/drivers/gpu/drm/i915/display/intel_wm.c +++ b/drivers/gpu/drm/i915/display/intel_wm.c @@ -290,7 +290,7 @@ static ssize_t wm_latency_write(struct file *file, const char __user *ubuf, { struct seq_file *m = file->private_data; struct drm_i915_private *dev_priv = m->private; - u16 new[8] = { 0 }; + u16 new[8] = {}; int level; int ret; char tmp[32]; -- cgit From cc01b0ff18947223fdbe723275e47805965a7790 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 12 Oct 2023 15:24:38 +0300 Subject: drm/i915/hdcp: Clean up zero initializers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20231012122442.15718-3-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- .../gpu/drm/i915/display/intel_hdcp_gsc_message.c | 44 +++++++++++----------- 1 file changed, 21 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c index caa9f0b25729..240b00849f3d 100644 --- a/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c +++ b/drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.c @@ -13,9 +13,8 @@ int intel_hdcp_gsc_initiate_session(struct device *dev, struct hdcp_port_data *data, struct hdcp2_ake_init *ake_data) { - struct wired_cmd_initiate_hdcp2_session_in session_init_in = { { 0 } }; - struct wired_cmd_initiate_hdcp2_session_out - session_init_out = { { 0 } }; + struct wired_cmd_initiate_hdcp2_session_in session_init_in = {}; + struct wired_cmd_initiate_hdcp2_session_out session_init_out = {}; struct drm_i915_private *i915; ssize_t byte; @@ -71,8 +70,8 @@ intel_hdcp_gsc_verify_receiver_cert_prepare_km(struct device *dev, *ek_pub_km, size_t *msg_sz) { - struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = { { 0 } }; - struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = { { 0 } }; + struct wired_cmd_verify_receiver_cert_in verify_rxcert_in = {}; + struct wired_cmd_verify_receiver_cert_out verify_rxcert_out = {}; struct drm_i915_private *i915; ssize_t byte; @@ -134,8 +133,8 @@ int intel_hdcp_gsc_verify_hprime(struct device *dev, struct hdcp_port_data *data, struct hdcp2_ake_send_hprime *rx_hprime) { - struct wired_cmd_ake_send_hprime_in send_hprime_in = { { 0 } }; - struct wired_cmd_ake_send_hprime_out send_hprime_out = { { 0 } }; + struct wired_cmd_ake_send_hprime_in send_hprime_in = {}; + struct wired_cmd_ake_send_hprime_out send_hprime_out = {}; struct drm_i915_private *i915; ssize_t byte; @@ -182,8 +181,8 @@ int intel_hdcp_gsc_store_pairing_info(struct device *dev, struct hdcp_port_data *data, struct hdcp2_ake_send_pairing_info *pairing_info) { - struct wired_cmd_ake_send_pairing_info_in pairing_info_in = { { 0 } }; - struct wired_cmd_ake_send_pairing_info_out pairing_info_out = { { 0 } }; + struct wired_cmd_ake_send_pairing_info_in pairing_info_in = {}; + struct wired_cmd_ake_send_pairing_info_out pairing_info_out = {}; struct drm_i915_private *i915; ssize_t byte; @@ -233,8 +232,8 @@ intel_hdcp_gsc_initiate_locality_check(struct device *dev, struct hdcp_port_data *data, struct hdcp2_lc_init *lc_init_data) { - struct wired_cmd_init_locality_check_in lc_init_in = { { 0 } }; - struct wired_cmd_init_locality_check_out lc_init_out = { { 0 } }; + struct wired_cmd_init_locality_check_in lc_init_in = {}; + struct wired_cmd_init_locality_check_out lc_init_out = {}; struct drm_i915_private *i915; ssize_t byte; @@ -279,8 +278,8 @@ int intel_hdcp_gsc_verify_lprime(struct device *dev, struct hdcp_port_data *data, struct hdcp2_lc_send_lprime *rx_lprime) { - struct wired_cmd_validate_locality_in verify_lprime_in = { { 0 } }; - struct wired_cmd_validate_locality_out verify_lprime_out = { { 0 } }; + struct wired_cmd_validate_locality_in verify_lprime_in = {}; + struct wired_cmd_validate_locality_out verify_lprime_out = {}; struct drm_i915_private *i915; ssize_t byte; @@ -329,8 +328,8 @@ int intel_hdcp_gsc_get_session_key(struct device *dev, struct hdcp_port_data *data, struct hdcp2_ske_send_eks *ske_data) { - struct wired_cmd_get_session_key_in get_skey_in = { { 0 } }; - struct wired_cmd_get_session_key_out get_skey_out = { { 0 } }; + struct wired_cmd_get_session_key_in get_skey_in = {}; + struct wired_cmd_get_session_key_out get_skey_out = {}; struct drm_i915_private *i915; ssize_t byte; @@ -381,8 +380,8 @@ intel_hdcp_gsc_repeater_check_flow_prepare_ack(struct device *dev, struct hdcp2_rep_send_ack *rep_send_ack) { - struct wired_cmd_verify_repeater_in verify_repeater_in = { { 0 } }; - struct wired_cmd_verify_repeater_out verify_repeater_out = { { 0 } }; + struct wired_cmd_verify_repeater_in verify_repeater_in = {}; + struct wired_cmd_verify_repeater_out verify_repeater_out = {}; struct drm_i915_private *i915; ssize_t byte; @@ -442,8 +441,7 @@ int intel_hdcp_gsc_verify_mprime(struct device *dev, struct hdcp2_rep_stream_ready *stream_ready) { struct wired_cmd_repeater_auth_stream_req_in *verify_mprime_in; - struct wired_cmd_repeater_auth_stream_req_out - verify_mprime_out = { { 0 } }; + struct wired_cmd_repeater_auth_stream_req_out verify_mprime_out = {}; struct drm_i915_private *i915; ssize_t byte; size_t cmd_size; @@ -504,8 +502,8 @@ int intel_hdcp_gsc_verify_mprime(struct device *dev, int intel_hdcp_gsc_enable_authentication(struct device *dev, struct hdcp_port_data *data) { - struct wired_cmd_enable_auth_in enable_auth_in = { { 0 } }; - struct wired_cmd_enable_auth_out enable_auth_out = { { 0 } }; + struct wired_cmd_enable_auth_in enable_auth_in = {}; + struct wired_cmd_enable_auth_out enable_auth_out = {}; struct drm_i915_private *i915; ssize_t byte; @@ -549,8 +547,8 @@ int intel_hdcp_gsc_enable_authentication(struct device *dev, int intel_hdcp_gsc_close_session(struct device *dev, struct hdcp_port_data *data) { - struct wired_cmd_close_session_in session_close_in = { { 0 } }; - struct wired_cmd_close_session_out session_close_out = { { 0 } }; + struct wired_cmd_close_session_in session_close_in = {}; + struct wired_cmd_close_session_out session_close_out = {}; struct drm_i915_private *i915; ssize_t byte; -- cgit From 28ec6c558e9f758ec93e8e964b6daeaf642c64c1 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 12 Oct 2023 15:24:40 +0300 Subject: drm/i915/pci: Clean up zero initializers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Just use a simple {} to zero initialize arrays/structs instead of the hodgepodge of stuff we are using currently. Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20231012122442.15718-5-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula --- drivers/gpu/drm/i915/i915_pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index df7c261410f7..454467cfa52b 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -923,7 +923,7 @@ static const struct pci_device_id pciidlist[] = { INTEL_DG2_IDS(&dg2_info), INTEL_ATS_M_IDS(&ats_m_info), INTEL_MTL_IDS(&mtl_info), - {0, 0, 0} + {} }; MODULE_DEVICE_TABLE(pci, pciidlist); -- cgit From 213c43676beb5f5a63cb27a0c8e8e71035b08445 Mon Sep 17 00:00:00 2001 From: Radhakrishna Sripada Date: Sun, 8 Oct 2023 18:48:24 +0200 Subject: drm/i915/mtl: Remove the 'force_probe' requirement for Meteor Lake Meteor Lake has demonstrated consistent stability for some time. All user-space API modifications tide to its core platform functions are operational. The necessary firmware components are set up and comprehensive testing has been condused over a period. Given the recent faborable CI results, as well, we believe it's time to eliminate the 'force_probe' prerequisite and activate the platform by default. Signed-off-by: Aditya Chauhan Signed-off-by: Andrzej Hajda Signed-off-by: Chris Wilson Signed-off-by: Janusz Krzysztofik Signed-off-by: Jonathan Cavitt Signed-off-by: Nirmoy Das Signed-off-by: Radhakrishna Sripada Signed-off-by: Andi Shyti Cc: Jani Nikula Cc: Joonas Lahtinen Cc: Rodrigo Vivi Cc: Tvrtko Ursulin Acked-by: Lee Shawn C Tested-by: Lee Shawn C Tested-by: Karthik B S Link: https://patchwork.freedesktop.org/patch/msgid/20231008164824.919262-1-andi.shyti@linux.intel.com --- drivers/gpu/drm/i915/i915_pci.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 454467cfa52b..bb577345bc0e 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -836,7 +836,6 @@ static const struct intel_device_info mtl_info = { .has_pxp = 1, .memory_regions = REGION_SMEM | REGION_STOLEN_LMEM, .platform_engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(CCS0), - .require_force_probe = 1, MTL_CACHELEVEL, }; -- cgit