From 863a6670a4f1901d1c9088f357337f3c8a17ab35 Mon Sep 17 00:00:00 2001 From: YueHaibing Date: Wed, 17 Jul 2019 14:56:26 +0800 Subject: drm/nouveau/secboot: Make acr_r352_ls_gpccs_func static Fix sparse warning: drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c:1092:1: warning: symbol 'acr_r352_ls_gpccs_func' was not declared. Should it be static? Reported-by: Hulk Robot Signed-off-by: YueHaibing Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index 4fd4cfe459b8..7af971db91bc 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -1088,7 +1088,7 @@ acr_r352_ls_gpccs_func_0 = { .lhdr_flags = LSF_FLAG_FORCE_PRIV_LOAD, }; -const struct acr_r352_ls_func +static const struct acr_r352_ls_func acr_r352_ls_gpccs_func = { .load = acr_ls_ucode_load_gpccs, .version_max = 0, -- cgit From fcca420d66046d5ddac55a9ddecb0e387547f7a0 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Tue, 14 May 2019 21:57:01 +0100 Subject: drm/nouveau/bios/init: fix spelling mistake "CONDITON" -> "CONDITION" There is a spelling mistake in a warning message. Fix it. Signed-off-by: Colin Ian King Reviewed-by: Mukesh Ojha Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index ec0e9f7224b5..3f4f27d191ae 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c @@ -834,7 +834,7 @@ init_generic_condition(struct nvbios_init *init) init_exec_set(init, false); break; default: - warn("INIT_GENERIC_CONDITON: unknown 0x%02x\n", cond); + warn("INIT_GENERIC_CONDITION: unknown 0x%02x\n", cond); init->offset += size; break; } -- cgit From 977b7e81df7300b5e79d680ae4e02be9fbab0fc2 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sun, 19 May 2019 16:00:41 +0200 Subject: drm/nouveau: drop use of DRM_UDELAY The DRM_UDELAY is a simple wrapper for udealy() and to be consistent call udelay() direct like in may other places. This avoids the need to pull in drm_os_linux.h when we later drop drmP.h uses in nouveau. Signed-off-by: Sam Ravnborg Cc: Ben Skeggs Cc: nouveau@lists.freedesktop.org Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_dma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c index 078f65d849ce..3c430a550a51 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dma.c +++ b/drivers/gpu/drm/nouveau/nouveau_dma.c @@ -118,7 +118,7 @@ nv50_dma_push_wait(struct nouveau_channel *chan, int count) } if ((++cnt & 0xff) == 0) { - DRM_UDELAY(1); + udelay(1); if (cnt > 100000) return -EBUSY; } -- cgit From c587cd6fc8b3ed497d1b478ba789311b3156d560 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sun, 19 May 2019 16:00:42 +0200 Subject: drm/nouveau: drop drmP.h from nouveau_drv.h Drop the deprecated drmP.h header from nouveau_drv.h. Fix fallout in other parts of the driver. Build tested using allmodconfig and allyesconfig. Signed-off-by: Sam Ravnborg Cc: Ben Skeggs Cc: nouveau@lists.freedesktop.org Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 2 ++ drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 1 + drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 ++ drivers/gpu/drm/nouveau/nouveau_display.h | 4 ++++ drivers/gpu/drm/nouveau/nouveau_drv.h | 5 ++++- 5 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index d5e295ca2caa..80e020611bcb 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -25,7 +25,9 @@ #include #include +#include #include + #include "nouveau_bo.h" void diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index cc417664f823..7354aaf79158 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -23,6 +23,7 @@ #include "atom.h" #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 027a01b97d1c..2dfb652d1e93 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -26,6 +26,8 @@ #include #include +#include + #include "nouveau_bo.h" static void diff --git a/drivers/gpu/drm/nouveau/nouveau_display.h b/drivers/gpu/drm/nouveau/nouveau_display.h index 9185f01e2d9b..6e8e66882e45 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.h +++ b/drivers/gpu/drm/nouveau/nouveau_display.h @@ -1,9 +1,13 @@ /* SPDX-License-Identifier: MIT */ #ifndef __NOUVEAU_DISPLAY_H__ #define __NOUVEAU_DISPLAY_H__ + #include "nouveau_drv.h" + #include +#include + struct nouveau_framebuffer { struct drm_framebuffer base; struct nouveau_bo *nvbo; diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index aae035816383..62e01919bb5f 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -46,7 +46,10 @@ #include #include -#include +#include +#include +#include +#include #include #include -- cgit From 3a2b92725bc846ee5e4d25cbe7c0dcac61083632 Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sun, 19 May 2019 16:00:43 +0200 Subject: drm/nouveau: drop drmP.h from all header files Drop include of the deprecated drmP.h from all nouveau heder files. This allows us to remove drmP.h from all .c files without any side-effects in a follow-up commit. Build tested using allyeyconfig and allmodconfig Signed-off-by: Sam Ravnborg Cc: Ben Skeggs Cc: nouveau@lists.freedesktop.org Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/hw.h | 1 - drivers/gpu/drm/nouveau/nouveau_crtc.h | 2 ++ drivers/gpu/drm/nouveau/nouveau_debugfs.h | 2 +- drivers/gpu/drm/nouveau/nouveau_gem.h | 2 -- 4 files changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.h b/drivers/gpu/drm/nouveau/dispnv04/hw.h index 3a2be47fb4f1..6987e1766cd2 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.h +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.h @@ -23,7 +23,6 @@ #ifndef __NOUVEAU_HW_H__ #define __NOUVEAU_HW_H__ -#include #include "disp.h" #include "nvreg.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_crtc.h b/drivers/gpu/drm/nouveau/nouveau_crtc.h index 366acb928f57..7f63be2ec35d 100644 --- a/drivers/gpu/drm/nouveau/nouveau_crtc.h +++ b/drivers/gpu/drm/nouveau/nouveau_crtc.h @@ -27,6 +27,8 @@ #ifndef __NOUVEAU_CRTC_H__ #define __NOUVEAU_CRTC_H__ +#include + #include struct nouveau_crtc { diff --git a/drivers/gpu/drm/nouveau/nouveau_debugfs.h b/drivers/gpu/drm/nouveau/nouveau_debugfs.h index 9420a6aca138..8909c010e8ea 100644 --- a/drivers/gpu/drm/nouveau/nouveau_debugfs.h +++ b/drivers/gpu/drm/nouveau/nouveau_debugfs.h @@ -2,7 +2,7 @@ #ifndef __NOUVEAU_DEBUGFS_H__ #define __NOUVEAU_DEBUGFS_H__ -#include +#include #if defined(CONFIG_DEBUG_FS) diff --git a/drivers/gpu/drm/nouveau/nouveau_gem.h b/drivers/gpu/drm/nouveau/nouveau_gem.h index 40ba0f1ba5aa..978e07591990 100644 --- a/drivers/gpu/drm/nouveau/nouveau_gem.h +++ b/drivers/gpu/drm/nouveau/nouveau_gem.h @@ -2,8 +2,6 @@ #ifndef __NOUVEAU_GEM_H__ #define __NOUVEAU_GEM_H__ -#include - #include "nouveau_drv.h" #include "nouveau_bo.h" -- cgit From 690ae20c0426f8a6f48d2c285a53c465ebcb0c1f Mon Sep 17 00:00:00 2001 From: Sam Ravnborg Date: Sun, 19 May 2019 16:00:44 +0200 Subject: drm/nouveau: drop use of drmp.h Drop use of the deprecated drmP.h file from drm/nouveau. Build tested using allyesconfig and allmodconfig. Signed-off-by: Sam Ravnborg Cc: Ben Skeggs Cc: nouveau@lists.freedesktop.org Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/arb.c | 2 -- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 3 ++- drivers/gpu/drm/nouveau/dispnv04/cursor.c | 1 - drivers/gpu/drm/nouveau/dispnv04/dac.c | 1 - drivers/gpu/drm/nouveau/dispnv04/dfp.c | 2 +- drivers/gpu/drm/nouveau/dispnv04/disp.c | 1 - drivers/gpu/drm/nouveau/dispnv04/hw.c | 1 - drivers/gpu/drm/nouveau/dispnv04/overlay.c | 1 - drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c | 1 - drivers/gpu/drm/nouveau/dispnv04/tvnv04.c | 1 - drivers/gpu/drm/nouveau/dispnv04/tvnv17.c | 1 - drivers/gpu/drm/nouveau/dispnv50/disp.c | 4 ++-- drivers/gpu/drm/nouveau/nouveau_bios.c | 2 -- drivers/gpu/drm/nouveau/nouveau_connector.c | 1 - drivers/gpu/drm/nouveau/nouveau_display.c | 4 +++- drivers/gpu/drm/nouveau/nouveau_dp.c | 1 - drivers/gpu/drm/nouveau/nouveau_drm.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_fbcon.c | 2 +- drivers/gpu/drm/nouveau/nouveau_fence.c | 3 +-- drivers/gpu/drm/nouveau/nouveau_hwmon.c | 2 -- drivers/gpu/drm/nouveau/nouveau_ioc32.c | 3 ++- drivers/gpu/drm/nouveau/nouveau_prime.c | 1 - drivers/gpu/drm/nouveau/nouveau_vga.c | 1 - 23 files changed, 14 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv04/arb.c b/drivers/gpu/drm/nouveau/dispnv04/arb.c index c79160c37f84..362495535e69 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/arb.c +++ b/drivers/gpu/drm/nouveau/dispnv04/arb.c @@ -21,8 +21,6 @@ * SOFTWARE. */ -#include - #include "nouveau_drv.h" #include "nouveau_reg.h" #include "hw.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index f22f01020625..210f13b145c1 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -24,9 +24,10 @@ */ #include -#include #include +#include #include +#include #include "nouveau_drv.h" #include "nouveau_reg.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/cursor.c b/drivers/gpu/drm/nouveau/dispnv04/cursor.c index 16e09f6b9113..4c6440d29c3f 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/cursor.c +++ b/drivers/gpu/drm/nouveau/dispnv04/cursor.c @@ -1,5 +1,4 @@ // SPDX-License-Identifier: MIT -#include #include #include "nouveau_drv.h" #include "nouveau_reg.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/dac.c b/drivers/gpu/drm/nouveau/dispnv04/dac.c index e7af95d37ddb..e8eef88a8382 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dac.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dac.c @@ -24,7 +24,6 @@ * DEALINGS IN THE SOFTWARE. */ -#include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/dfp.c b/drivers/gpu/drm/nouveau/dispnv04/dfp.c index 73d41abbb510..f9f4482c79b5 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/dfp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/dfp.c @@ -24,8 +24,8 @@ * DEALINGS IN THE SOFTWARE. */ -#include #include +#include #include "nouveau_drv.h" #include "nouveau_reg.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c index 5713bacaee80..0f8e186f3d07 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c @@ -22,7 +22,6 @@ * Author: Ben Skeggs */ -#include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/hw.c b/drivers/gpu/drm/nouveau/dispnv04/hw.c index 0c9bdf023f5b..3fdfafa8b0ad 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/hw.c +++ b/drivers/gpu/drm/nouveau/dispnv04/hw.c @@ -22,7 +22,6 @@ * SOFTWARE. */ -#include #include "nouveau_drv.h" #include "hw.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/overlay.c b/drivers/gpu/drm/nouveau/dispnv04/overlay.c index df4358e31075..a3a0a73ae8ab 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/overlay.c +++ b/drivers/gpu/drm/nouveau/dispnv04/overlay.c @@ -23,7 +23,6 @@ * written by Arthur Huillet. */ -#include #include #include diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c index 2b83b2c39d1d..2f6d2b6711ab 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c +++ b/drivers/gpu/drm/nouveau/dispnv04/tvmodesnv17.c @@ -24,7 +24,6 @@ * */ -#include #include #include "nouveau_drv.h" #include "nouveau_encoder.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c index de4490b4ed30..b701a4d8fe76 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c +++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv04.c @@ -24,7 +24,6 @@ * */ -#include #include "nouveau_drv.h" #include "nouveau_reg.h" #include "nouveau_encoder.h" diff --git a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c index 26fd71c06626..03466f04c741 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c +++ b/drivers/gpu/drm/nouveau/dispnv04/tvnv17.c @@ -24,7 +24,6 @@ * */ -#include #include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 126703816794..7ce7145f82b8 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -30,14 +30,14 @@ #include #include -#include #include #include +#include #include #include #include #include -#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 66bf2aff4a3e..1e93f82c96fa 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -22,8 +22,6 @@ * SOFTWARE. */ -#include - #include "nouveau_drv.h" #include "nouveau_reg.h" #include "dispnv04/hw.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c index 330d7d29a6e3..94dfa2e5a9ab 100644 --- a/drivers/gpu/drm/nouveau/nouveau_connector.c +++ b/drivers/gpu/drm/nouveau/nouveau_connector.c @@ -29,7 +29,6 @@ #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c index 98afc50162e9..6f038511a03a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_display.c +++ b/drivers/gpu/drm/nouveau/nouveau_display.c @@ -25,12 +25,14 @@ */ #include -#include + #include #include #include #include +#include #include +#include #include "nouveau_fbcon.h" #include "nouveau_crtc.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_dp.c b/drivers/gpu/drm/nouveau/nouveau_dp.c index 0d052e1660f8..2674f1587457 100644 --- a/drivers/gpu/drm/nouveau/nouveau_dp.c +++ b/drivers/gpu/drm/nouveau/nouveau_dp.c @@ -22,7 +22,6 @@ * Authors: Ben Skeggs */ -#include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_drm.c b/drivers/gpu/drm/nouveau/nouveau_drm.c index 7e045580a3a4..bdc948352467 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drm.c +++ b/drivers/gpu/drm/nouveau/nouveau_drm.c @@ -29,8 +29,9 @@ #include #include -#include #include +#include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c index 73cc3217068a..f439f0a5b43a 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c +++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c @@ -37,10 +37,10 @@ #include #include -#include #include #include #include +#include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_fence.c b/drivers/gpu/drm/nouveau/nouveau_fence.c index 8df390078c85..9118df035b28 100644 --- a/drivers/gpu/drm/nouveau/nouveau_fence.c +++ b/drivers/gpu/drm/nouveau/nouveau_fence.c @@ -24,10 +24,9 @@ * */ -#include - #include #include +#include #include #include diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c b/drivers/gpu/drm/nouveau/nouveau_hwmon.c index 6af2d299c3f9..d445c6f3fece 100644 --- a/drivers/gpu/drm/nouveau/nouveau_hwmon.c +++ b/drivers/gpu/drm/nouveau/nouveau_hwmon.c @@ -29,8 +29,6 @@ #include #include -#include - #include "nouveau_drv.h" #include "nouveau_hwmon.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_ioc32.c b/drivers/gpu/drm/nouveau/nouveau_ioc32.c index 462679a8fec5..adf01ca9e035 100644 --- a/drivers/gpu/drm/nouveau/nouveau_ioc32.c +++ b/drivers/gpu/drm/nouveau/nouveau_ioc32.c @@ -33,7 +33,8 @@ #include -#include +#include +#include #include "nouveau_ioctl.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_prime.c b/drivers/gpu/drm/nouveau/nouveau_prime.c index 7262ced9688a..6a222cdf2935 100644 --- a/drivers/gpu/drm/nouveau/nouveau_prime.c +++ b/drivers/gpu/drm/nouveau/nouveau_prime.c @@ -22,7 +22,6 @@ * Authors: Dave Airlie */ -#include #include #include "nouveau_drv.h" diff --git a/drivers/gpu/drm/nouveau/nouveau_vga.c b/drivers/gpu/drm/nouveau/nouveau_vga.c index 8f4b12a8092c..d865d8aeac3c 100644 --- a/drivers/gpu/drm/nouveau/nouveau_vga.c +++ b/drivers/gpu/drm/nouveau/nouveau_vga.c @@ -2,7 +2,6 @@ #include #include -#include #include #include -- cgit From 7b97492555b1063417c143d2c22c503f6299c0b0 Mon Sep 17 00:00:00 2001 From: "Gustavo A. R. Silva" Date: Fri, 24 May 2019 12:15:36 -0500 Subject: drm/nouveau/mmu: use struct_size() helper Make use of the struct_size() helper instead of an open-coded version in order to avoid any potential type mistakes, in particular in the context in which this code is being used. So, replace the following form: sizeof(*kind) + sizeof(*kind->data) * mmu->kind_nr; with: struct_size(kind, data, mmu->kind_nr) This code was detected with the help of Coccinelle. Signed-off-by: Gustavo A. R. Silva Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvif/mmu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvif/mmu.c b/drivers/gpu/drm/nouveau/nvif/mmu.c index ae08a1ca8044..5641bda2046d 100644 --- a/drivers/gpu/drm/nouveau/nvif/mmu.c +++ b/drivers/gpu/drm/nouveau/nvif/mmu.c @@ -110,7 +110,7 @@ nvif_mmu_init(struct nvif_object *parent, s32 oclass, struct nvif_mmu *mmu) if (mmu->kind_nr) { struct nvif_mmu_kind_v0 *kind; - u32 argc = sizeof(*kind) + sizeof(*kind->data) * mmu->kind_nr; + size_t argc = struct_size(kind, data, mmu->kind_nr); if (ret = -ENOMEM, !(kind = kmalloc(argc, GFP_KERNEL))) goto done; -- cgit From c8b3585d4fbdf48b692c14b41dd1d53c329f7592 Mon Sep 17 00:00:00 2001 From: Hariprasad Kelam Date: Sun, 26 May 2019 16:29:36 +0530 Subject: drm/nouveau/dispnv04: subdev/bios.h is included more than once remove duplicate inclusion of subdev/bios.h Issue identified by includecheck Signed-off-by: Hariprasad Kelam Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/disp.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.h b/drivers/gpu/drm/nouveau/dispnv04/disp.h index 6ccfc09bcf0f..495d3284e876 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.h +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.h @@ -161,7 +161,6 @@ nv_match_device(struct drm_device *dev, unsigned device, dev->pdev->subsystem_device == sub_device; } -#include #include static inline void -- cgit From eb3f4cfa53bca7c17feefa926a365e80844198d6 Mon Sep 17 00:00:00 2001 From: Hariprasad Kelam Date: Sun, 26 May 2019 16:36:25 +0530 Subject: drm/nouveau: fix nvif/device.h is included more than once remove duplicate inclusion of nvif/device.h Issue identified by includecheck Signed-off-by: Hariprasad Kelam Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_drv.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index 62e01919bb5f..cf0d0a416af6 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -130,7 +130,6 @@ nouveau_cli(struct drm_file *fpriv) } #include -#include struct nouveau_drm { struct nouveau_cli master; -- cgit From 0446f48cb53d0fa2e122504ce235fcb25b1e2a19 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 28 May 2019 16:33:59 +1000 Subject: drm/nouveau/kms/gv100: allow windows to use PACKED8BPP formats Required for upcoming FP16 scanout support. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/corec37d.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c index 7860774b65bc..40d9b654ab8c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/corec37d.c +++ b/drivers/gpu/drm/nouveau/dispnv50/corec37d.c @@ -82,7 +82,7 @@ corec37d_init(struct nv50_core *core) for (i = 0; i < windows; i++) { evo_mthd(push, 0x1000 + (i * 0x080), 3); evo_data(push, i >> 1); - evo_data(push, 0x00000017); + evo_data(push, 0x0000001f); evo_data(push, 0x00000000); evo_mthd(push, 0x1010 + (i * 0x080), 1); evo_data(push, 0x00127fff); -- cgit From 1e339ab2ac3c769c1b06b9fb7d532f8495ebc56d Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 29 May 2019 15:44:57 +1000 Subject: drm/nouveau/kms/tu102-: disable input lut when input is already FP16 On Turing, an input LUT is required to transform inputs in fixed-point formats to FP16 for the internal display pipe. We provide an identity mapping whenever a window is enabled for this reason. HW has error checks to ensure when the input is already FP16, that the input LUT is also disabled. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 2dfb652d1e93..5a8af9a0479a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -322,7 +322,9 @@ nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, asyh->wndw.olut &= ~BIT(wndw->id); } - if (!ilut && wndw->func->ilut_identity) { + if (!ilut && wndw->func->ilut_identity && + asyw->state.fb->format->format != DRM_FORMAT_XBGR16161616F && + asyw->state.fb->format->format != DRM_FORMAT_ABGR16161616F) { static struct drm_property_blob dummy = {}; ilut = &dummy; } -- cgit From ebf8ca6b3d6d7310646b092f3d5219abe2858e81 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 29 May 2019 16:39:53 +1000 Subject: drm/nouveau/kms/nv50-: disable input lut harder Under some circumstances, it could be left enabled when it shouldn't be. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 5a8af9a0479a..0aaa7e0013f6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -336,6 +336,8 @@ nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, asyw->xlut.handle = wndw->wndw.vram.handle; asyw->xlut.i.buffer = !asyw->xlut.i.buffer; asyw->set.xlut = true; + } else { + asyw->clr.xlut = armw->xlut.handle != 0; } /* Handle setting base SET_OUTPUT_LUT_LO_ENABLE_USE_CORE_LUT. */ -- cgit From 38a72243235ecf2c1359ce66ebed29a7dfb680f7 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Mon, 27 May 2019 22:58:37 -0400 Subject: drm/nouveau/kms/nv50-: add fp16 scanout support Older hardware seems to want 0..1024 values, while new hardware takes 0..1 values. We set the gain to 1024 for the earlier display classes. Signed-off-by: Ilia Mirkin Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/base507c.c | 24 ++++++++++++++++++++---- drivers/gpu/drm/nouveau/dispnv50/base827c.c | 11 ++++++++++- drivers/gpu/drm/nouveau/dispnv50/base917c.c | 2 ++ drivers/gpu/drm/nouveau/dispnv50/ovly907e.c | 17 ++++++++++++++++- drivers/gpu/drm/nouveau/dispnv50/ovly917e.c | 2 ++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 26 ++++++++++++++------------ drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 ++ 7 files changed, 66 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base507c.c b/drivers/gpu/drm/nouveau/dispnv50/base507c.c index 80e020611bcb..00a85f1e1a4a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base507c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base507c.c @@ -58,12 +58,21 @@ static void base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { u32 *push; - if ((push = evo_wait(&wndw->wndw, 10))) { + if ((push = evo_wait(&wndw->wndw, 13))) { evo_mthd(push, 0x0084, 1); evo_data(push, asyw->image.mode << 8 | asyw->image.interval << 4); evo_mthd(push, 0x00c0, 1); evo_data(push, asyw->image.handle[0]); + if (asyw->image.format == 0xca) { + evo_mthd(push, 0x0110, 2); + evo_data(push, 1); + evo_data(push, 0x6400); + } else { + evo_mthd(push, 0x0110, 2); + evo_data(push, 0); + evo_data(push, 0); + } evo_mthd(push, 0x0800, 5); evo_data(push, asyw->image.offset[0] >> 8); evo_data(push, 0x00000000); @@ -181,9 +190,6 @@ base507c_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, const struct drm_framebuffer *fb = asyw->state.fb; int ret; - if (!fb->format->depth) - return -EINVAL; - ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state, DRM_PLANE_HELPER_NO_SCALING, DRM_PLANE_HELPER_NO_SCALING, @@ -202,6 +208,14 @@ base507c_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, asyh->base.y = asyw->state.src.y1 >> 16; asyh->base.w = asyw->state.fb->width; asyh->base.h = asyw->state.fb->height; + + /* Some newer formats, esp FP16 ones, don't have a + * "depth". There's nothing that really makes sense there + * either, so just set it to the implicit bit count. + */ + if (!asyh->base.depth) + asyh->base.depth = asyh->base.cpp * 8; + return 0; } @@ -217,6 +231,8 @@ base507c_format[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_XBGR8888, DRM_FORMAT_ABGR8888, + DRM_FORMAT_XBGR16161616F, + DRM_FORMAT_ABGR16161616F, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/base827c.c b/drivers/gpu/drm/nouveau/dispnv50/base827c.c index 73646819a0d6..f4c05949dd62 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base827c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base827c.c @@ -25,12 +25,21 @@ static void base827c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { u32 *push; - if ((push = evo_wait(&wndw->wndw, 10))) { + if ((push = evo_wait(&wndw->wndw, 13))) { evo_mthd(push, 0x0084, 1); evo_data(push, asyw->image.mode << 8 | asyw->image.interval << 4); evo_mthd(push, 0x00c0, 1); evo_data(push, asyw->image.handle[0]); + if (asyw->image.format == 0xca) { + evo_mthd(push, 0x0110, 2); + evo_data(push, 1); + evo_data(push, 0x6400); + } else { + evo_mthd(push, 0x0110, 2); + evo_data(push, 0); + evo_data(push, 0); + } evo_mthd(push, 0x0800, 5); evo_data(push, asyw->image.offset[0] >> 8); evo_data(push, 0x00000000); diff --git a/drivers/gpu/drm/nouveau/dispnv50/base917c.c b/drivers/gpu/drm/nouveau/dispnv50/base917c.c index 54d705bb81a5..a1baed4fe0e9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base917c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base917c.c @@ -36,6 +36,8 @@ base917c_format[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, + DRM_FORMAT_XBGR16161616F, + DRM_FORMAT_ABGR16161616F, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c index a3ce53046015..f947117d62b1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c @@ -61,10 +61,25 @@ ovly907e = { .update = ovly507e_update, }; +static const u32 +ovly907e_format[] = { + DRM_FORMAT_YUYV, + DRM_FORMAT_UYVY, + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XRGB1555, + DRM_FORMAT_ARGB1555, + DRM_FORMAT_XBGR2101010, + DRM_FORMAT_ABGR2101010, + DRM_FORMAT_XBGR16161616F, + DRM_FORMAT_ABGR16161616F, + 0 +}; + int ovly907e_new(struct nouveau_drm *drm, int head, s32 oclass, struct nv50_wndw **pwndw) { - return ovly507e_new_(&ovly907e, ovly827e_format, drm, head, oclass, + return ovly507e_new_(&ovly907e, ovly907e_format, drm, head, oclass, 0x00000004 << (head * 4), pwndw); } diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c index 505fa7e78523..fab567e258f9 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c @@ -33,6 +33,8 @@ ovly917e_format[] = { DRM_FORMAT_ABGR2101010, DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, + DRM_FORMAT_XBGR16161616F, + DRM_FORMAT_ABGR16161616F, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 0aaa7e0013f6..dd01ea21da97 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -204,18 +204,20 @@ static int nv50_wndw_atomic_check_acquire_rgb(struct nv50_wndw_atom *asyw) { switch (asyw->state.fb->format->format) { - case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; - case DRM_FORMAT_XRGB8888 : - case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; - case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; - case DRM_FORMAT_XRGB1555 : - case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; - case DRM_FORMAT_XBGR2101010: - case DRM_FORMAT_ABGR2101010: asyw->image.format = 0xd1; break; - case DRM_FORMAT_XBGR8888 : - case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; - case DRM_FORMAT_XRGB2101010: - case DRM_FORMAT_ARGB2101010: asyw->image.format = 0xdf; break; + case DRM_FORMAT_C8 : asyw->image.format = 0x1e; break; + case DRM_FORMAT_XRGB8888 : + case DRM_FORMAT_ARGB8888 : asyw->image.format = 0xcf; break; + case DRM_FORMAT_RGB565 : asyw->image.format = 0xe8; break; + case DRM_FORMAT_XRGB1555 : + case DRM_FORMAT_ARGB1555 : asyw->image.format = 0xe9; break; + case DRM_FORMAT_XBGR2101010 : + case DRM_FORMAT_ABGR2101010 : asyw->image.format = 0xd1; break; + case DRM_FORMAT_XBGR8888 : + case DRM_FORMAT_ABGR8888 : asyw->image.format = 0xd5; break; + case DRM_FORMAT_XRGB2101010 : + case DRM_FORMAT_ARGB2101010 : asyw->image.format = 0xdf; break; + case DRM_FORMAT_XBGR16161616F: + case DRM_FORMAT_ABGR16161616F: asyw->image.format = 0xca; break; default: return -EINVAL; } diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index e52a85c83f7a..826d1d760d3a 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -216,6 +216,8 @@ wndwc37e_format[] = { DRM_FORMAT_ABGR8888, DRM_FORMAT_XRGB2101010, DRM_FORMAT_ARGB2101010, + DRM_FORMAT_XBGR16161616F, + DRM_FORMAT_ABGR16161616F, 0 }; -- cgit From ad45354a631bb05a53e535ac28b608fa6bd85561 Mon Sep 17 00:00:00 2001 From: Ville Syrjälä Date: Thu, 13 Sep 2018 19:31:46 +0300 Subject: drm/nouveau: Disable atomic support on a per-device basis MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We now have per-device driver_features, so let's use that to disable atomic only for pre-nv50. Cc: Ben Skeggs Cc: Lyude Paul Cc: nouveau@lists.freedesktop.org Cc: Daniel Vetter Reviewed-by: Daniel Vetter Suggested-by: Daniel Vetter Signed-off-by: Ville Syrjälä Reviewed-by: Lyude Paul Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/disp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv04/disp.c b/drivers/gpu/drm/nouveau/dispnv04/disp.c index 0f8e186f3d07..dc64863b5fd8 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv04/disp.c @@ -209,7 +209,7 @@ nv04_display_create(struct drm_device *dev) nouveau_display(dev)->fini = nv04_display_fini; /* Pre-nv50 doesn't support atomic, so don't expose the ioctls */ - dev->driver->driver_features &= ~DRIVER_ATOMIC; + dev->driver_features &= ~DRIVER_ATOMIC; /* Request page flip completion event. */ if (drm->nvsw.client) { -- cgit From 607db661b7ac338943bb5efd94a7eac0051af440 Mon Sep 17 00:00:00 2001 From: Rhys Kidd Date: Sun, 2 Jun 2019 22:07:27 +1000 Subject: drm/nouveau/bios: downgrade absence of tmds table to info from an error Absence of a TMDS Info Table is common on Optimus setups where the NVIDIA gpu is not connected directly to any outputs. Reporting an error in this scenario is too harsh. Accordingly, change the error message to an info message. By default the error message also causes a boot flicker for these sytems. Signed-off-by: Rhys Kidd Reviewed-by: Lyude Paul Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nouveau_bios.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c index 1e93f82c96fa..d204ea8a5618 100644 --- a/drivers/gpu/drm/nouveau/nouveau_bios.c +++ b/drivers/gpu/drm/nouveau/nouveau_bios.c @@ -933,7 +933,7 @@ static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, tmdstableptr = ROM16(bios->data[bitentry->offset]); if (!tmdstableptr) { - NV_ERROR(drm, "Pointer to TMDS table invalid\n"); + NV_INFO(drm, "Pointer to TMDS table not found\n"); return -EINVAL; } -- cgit From 66cbcc72ae34711854ae7af8056bfb7169f874fd Mon Sep 17 00:00:00 2001 From: Rhys Kidd Date: Mon, 3 Jun 2019 00:13:14 +1000 Subject: drm/nouveau/bios/init: handle INIT_RESET_BEGUN devinit opcode Signal that the reset sequence has begun. This opcode signals that the software reset sequence has begun. Ordinarily, no actual operations are performed by the opcode. However it allows for possible software work arounds by devinit engines in software agents other than the VBIOS, such as the resman, FCODE, and EFI driver. Signed-off-by: Rhys Kidd Reviewed-by: Lyude Paul Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index 3f4f27d191ae..5e02832304e2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c @@ -1934,6 +1934,17 @@ init_ram_restrict_pll(struct nvbios_init *init) } } +/** + * INIT_RESET_BEGUN - opcode 0x8c + * + */ +static void +init_reset_begun(struct nvbios_init *init) +{ + trace("RESET_BEGUN\n"); + init->offset += 1; +} + /** * INIT_GPIO - opcode 0x8e * @@ -2260,7 +2271,7 @@ static struct nvbios_init_opcode { [0x79] = { init_pll }, [0x7a] = { init_zm_reg }, [0x87] = { init_ram_restrict_pll }, - [0x8c] = { init_reserved }, + [0x8c] = { init_reset_begun }, [0x8d] = { init_reserved }, [0x8e] = { init_gpio }, [0x8f] = { init_ram_restrict_zm_reg_group }, -- cgit From 9f9b450752d38c86f4f830214bb9276ed174d5d3 Mon Sep 17 00:00:00 2001 From: Rhys Kidd Date: Mon, 3 Jun 2019 00:13:15 +1000 Subject: drm/nouveau/bios/init: handle INIT_RESET_END devinit opcode Signal that the reset sequence has completed. This opcode signals that the software reset sequence has completed. Ordinarily, no actual operations are performed by the opcode. However it allows for possible software work arounds by devinit engines in software agents other than the VBIOS, such as the resman, FCODE, and EFI driver. Signed-off-by: Rhys Kidd Reviewed-by: Lyude Paul Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c index 5e02832304e2..9de74f41dcd2 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.c @@ -1945,6 +1945,17 @@ init_reset_begun(struct nvbios_init *init) init->offset += 1; } +/** + * INIT_RESET_END - opcode 0x8d + * + */ +static void +init_reset_end(struct nvbios_init *init) +{ + trace("RESET_END\n"); + init->offset += 1; +} + /** * INIT_GPIO - opcode 0x8e * @@ -2272,7 +2283,7 @@ static struct nvbios_init_opcode { [0x7a] = { init_zm_reg }, [0x87] = { init_ram_restrict_pll }, [0x8c] = { init_reset_begun }, - [0x8d] = { init_reserved }, + [0x8d] = { init_reset_end }, [0x8e] = { init_gpio }, [0x8f] = { init_ram_restrict_zm_reg_group }, [0x90] = { init_copy_zm_reg }, -- cgit From cf9518b50a9c68cafb07e05fc54731071228ced3 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 13 Jun 2019 13:58:50 +1000 Subject: drm/nouveau/fifo/gf1xx: convert to using nvkm_fault_data Would like to be able to reuse gf100_fifo_intr_fault() for (some of) the later chipsets too, as it's identical. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c | 188 +++++++++++++---------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 2 +- drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h | 2 + 3 files changed, 106 insertions(+), 86 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c index 10a2e7039a75..5a39e51d42d7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -193,68 +194,6 @@ gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, nvkm_fifo_kevent(&fifo->base, chid); } -static const struct nvkm_enum -gf100_fifo_sched_reason[] = { - { 0x0a, "CTXSW_TIMEOUT" }, - {} -}; - -static void -gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) -{ - struct nvkm_device *device = fifo->base.engine.subdev.device; - struct nvkm_engine *engine; - struct gf100_fifo_chan *chan; - unsigned long flags; - u32 engn; - - spin_lock_irqsave(&fifo->base.lock, flags); - for (engn = 0; engn < 6; engn++) { - u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); - u32 busy = (stat & 0x80000000); - u32 save = (stat & 0x00100000); /* maybe? */ - u32 unk0 = (stat & 0x00040000); - u32 unk1 = (stat & 0x00001000); - u32 chid = (stat & 0x0000007f); - (void)save; - - if (busy && unk0 && unk1) { - list_for_each_entry(chan, &fifo->chan, head) { - if (chan->base.chid == chid) { - engine = gf100_fifo_engine(fifo, engn); - if (!engine) - break; - gf100_fifo_recover(fifo, engine, chan); - break; - } - } - } - } - spin_unlock_irqrestore(&fifo->base.lock, flags); -} - -static void -gf100_fifo_intr_sched(struct gf100_fifo *fifo) -{ - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - u32 intr = nvkm_rd32(device, 0x00254c); - u32 code = intr & 0x000000ff; - const struct nvkm_enum *en; - - en = nvkm_enum_find(gf100_fifo_sched_reason, code); - - nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); - - switch (code) { - case 0x0a: - gf100_fifo_intr_sched_ctxsw(fifo); - break; - default: - break; - } -} - static const struct nvkm_enum gf100_fifo_fault_engine[] = { { 0x00, "PGRAPH", NULL, NVKM_ENGINE_GR }, @@ -315,32 +254,24 @@ gf100_fifo_fault_gpcclient[] = { }; static void -gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) +gf100_fifo_fault(struct nvkm_fifo *base, struct nvkm_fault_data *info) { + struct gf100_fifo *fifo = gf100_fifo(base); struct nvkm_subdev *subdev = &fifo->base.engine.subdev; struct nvkm_device *device = subdev->device; - u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); - u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); - u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); - u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10)); - u32 gpc = (stat & 0x1f000000) >> 24; - u32 client = (stat & 0x00001f00) >> 8; - u32 write = (stat & 0x00000080); - u32 hub = (stat & 0x00000040); - u32 reason = (stat & 0x0000000f); const struct nvkm_enum *er, *eu, *ec; struct nvkm_engine *engine = NULL; struct nvkm_fifo_chan *chan; unsigned long flags; char gpcid[8] = ""; - er = nvkm_enum_find(gf100_fifo_fault_reason, reason); - eu = nvkm_enum_find(gf100_fifo_fault_engine, unit); - if (hub) { - ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client); + er = nvkm_enum_find(gf100_fifo_fault_reason, info->reason); + eu = nvkm_enum_find(gf100_fifo_fault_engine, info->engine); + if (info->hub) { + ec = nvkm_enum_find(gf100_fifo_fault_hubclient, info->client); } else { - ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client); - snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc); + ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, info->client); + snprintf(gpcid, sizeof(gpcid), "GPC%d/", info->gpc); } if (eu && eu->data2) { @@ -360,22 +291,108 @@ gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) } } - chan = nvkm_fifo_chan_inst(&fifo->base, (u64)inst << 12, &flags); + chan = nvkm_fifo_chan_inst(&fifo->base, info->inst, &flags); nvkm_error(subdev, "%s fault at %010llx engine %02x [%s] client %02x [%s%s] " "reason %02x [%s] on channel %d [%010llx %s]\n", - write ? "write" : "read", (u64)vahi << 32 | valo, - unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "", - reason, er ? er->name : "", chan ? chan->chid : -1, - (u64)inst << 12, - chan ? chan->object.client->name : "unknown"); + info->access ? "write" : "read", info->addr, + info->engine, eu ? eu->name : "", + info->client, gpcid, ec ? ec->name : "", + info->reason, er ? er->name : "", chan ? chan->chid : -1, + info->inst, chan ? chan->object.client->name : "unknown"); if (engine && chan) gf100_fifo_recover(fifo, engine, (void *)chan); nvkm_fifo_chan_put(&fifo->base, flags, &chan); } +static const struct nvkm_enum +gf100_fifo_sched_reason[] = { + { 0x0a, "CTXSW_TIMEOUT" }, + {} +}; + +static void +gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) +{ + struct nvkm_device *device = fifo->base.engine.subdev.device; + struct nvkm_engine *engine; + struct gf100_fifo_chan *chan; + unsigned long flags; + u32 engn; + + spin_lock_irqsave(&fifo->base.lock, flags); + for (engn = 0; engn < 6; engn++) { + u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); + u32 busy = (stat & 0x80000000); + u32 save = (stat & 0x00100000); /* maybe? */ + u32 unk0 = (stat & 0x00040000); + u32 unk1 = (stat & 0x00001000); + u32 chid = (stat & 0x0000007f); + (void)save; + + if (busy && unk0 && unk1) { + list_for_each_entry(chan, &fifo->chan, head) { + if (chan->base.chid == chid) { + engine = gf100_fifo_engine(fifo, engn); + if (!engine) + break; + gf100_fifo_recover(fifo, engine, chan); + break; + } + } + } + } + spin_unlock_irqrestore(&fifo->base.lock, flags); +} + +static void +gf100_fifo_intr_sched(struct gf100_fifo *fifo) +{ + struct nvkm_subdev *subdev = &fifo->base.engine.subdev; + struct nvkm_device *device = subdev->device; + u32 intr = nvkm_rd32(device, 0x00254c); + u32 code = intr & 0x000000ff; + const struct nvkm_enum *en; + + en = nvkm_enum_find(gf100_fifo_sched_reason, code); + + nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); + + switch (code) { + case 0x0a: + gf100_fifo_intr_sched_ctxsw(fifo); + break; + default: + break; + } +} + +void +gf100_fifo_intr_fault(struct nvkm_fifo *fifo, int unit) +{ + struct nvkm_device *device = fifo->engine.subdev.device; + u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); + u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); + u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); + u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); + struct nvkm_fault_data info; + + info.inst = (u64)inst << 12; + info.addr = ((u64)vahi << 32) | valo; + info.time = 0; + info.engine = unit; + info.valid = 1; + info.gpc = (type & 0x1f000000) >> 24; + info.client = (type & 0x00001f00) >> 8; + info.access = (type & 0x00000080) >> 7; + info.hub = (type & 0x00000040) >> 6; + info.reason = (type & 0x0000000f); + + nvkm_fifo_fault(fifo, &info); +} + static const struct nvkm_bitfield gf100_fifo_pbdma_intr[] = { /* { 0x00008000, "" } seen with null ib push */ @@ -518,7 +535,7 @@ gf100_fifo_intr(struct nvkm_fifo *base) u32 mask = nvkm_rd32(device, 0x00259c); while (mask) { u32 unit = __ffs(mask); - gf100_fifo_intr_fault(fifo, unit); + gf100_fifo_intr_fault(&fifo->base, unit); nvkm_wr32(device, 0x00259c, (1 << unit)); mask &= ~(1 << unit); } @@ -655,6 +672,7 @@ gf100_fifo = { .init = gf100_fifo_init, .fini = gf100_fifo_fini, .intr = gf100_fifo_intr, + .fault = gf100_fifo_fault, .uevent_init = gf100_fifo_uevent_init, .uevent_fini = gf100_fifo_uevent_fini, .chan = { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index 1053fe796466..ac9abcc1470a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -666,7 +666,7 @@ gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) info.client = (type & 0x00001f00) >> 8; info.access = (type & 0x00000080) >> 7; info.hub = (type & 0x00000040) >> 6; - info.reason = (type & 0x000000ff); + info.reason = (type & 0x0000001f); nvkm_fifo_fault(&fifo->base, &info); } diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h index c66f5370b21f..0ef8baab513e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h @@ -37,4 +37,6 @@ struct nvkm_fifo_func { void nv04_fifo_intr(struct nvkm_fifo *); void nv04_fifo_pause(struct nvkm_fifo *, unsigned long *); void nv04_fifo_start(struct nvkm_fifo *, unsigned long *); + +void gf100_fifo_intr_fault(struct nvkm_fifo *, int); #endif -- cgit From cde540211ab1346a262ad9a5ecc52c9ff8f5975f Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Thu, 13 Jun 2019 14:23:04 +1000 Subject: drm/nouveau/fifo/gk104-: fix parsing of mmu fault data Pascal was particularly incorrect, as the register changed to be more in the same format as the MMU fault buffers are. Shouldn't have impacted much more than confusing MMU fault log messages. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c | 28 ++---------------------- drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h | 6 +++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c | 26 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c | 1 + drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c | 27 +++++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c | 1 + 10 files changed, 67 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c index ac9abcc1470a..5d4b695cab8e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.c @@ -646,31 +646,6 @@ gk104_fifo_intr_dropped_fault(struct gk104_fifo *fifo) nvkm_error(subdev, "DROPPED_MMU_FAULT %08x\n", stat); } -static void -gk104_fifo_intr_fault(struct gk104_fifo *fifo, int unit) -{ - struct nvkm_subdev *subdev = &fifo->base.engine.subdev; - struct nvkm_device *device = subdev->device; - u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); - u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); - u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); - u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); - struct nvkm_fault_data info; - - info.inst = (u64)inst << 12; - info.addr = ((u64)vahi << 32) | valo; - info.time = 0; - info.engine = unit; - info.valid = 1; - info.gpc = (type & 0x1f000000) >> 24; - info.client = (type & 0x00001f00) >> 8; - info.access = (type & 0x00000080) >> 7; - info.hub = (type & 0x00000040) >> 6; - info.reason = (type & 0x0000001f); - - nvkm_fifo_fault(&fifo->base, &info); -} - static const struct nvkm_bitfield gk104_fifo_pbdma_intr_0[] = { { 0x00000001, "MEMREQ" }, { 0x00000002, "MEMACK_TIMEOUT" }, @@ -849,7 +824,7 @@ gk104_fifo_intr(struct nvkm_fifo *base) u32 mask = nvkm_rd32(device, 0x00259c); while (mask) { u32 unit = __ffs(mask); - gk104_fifo_intr_fault(fifo, unit); + fifo->func->intr.fault(&fifo->base, unit); nvkm_wr32(device, 0x00259c, (1 << unit)); mask &= ~(1 << unit); } @@ -1204,6 +1179,7 @@ gk104_fifo_fault_gpcclient[] = { static const struct gk104_fifo_func gk104_fifo = { + .intr.fault = gf100_fifo_intr_fault, .pbdma = &gk104_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gk104_fifo_fault_engine, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h index c33f4593cbc6..6407a4a174cf 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.h @@ -45,6 +45,10 @@ struct gk104_fifo { }; struct gk104_fifo_func { + struct { + void (*fault)(struct nvkm_fifo *, int unit); + } intr; + const struct gk104_fifo_pbdma_func { int (*nr)(struct gk104_fifo *); void (*init)(struct gk104_fifo *); @@ -110,12 +114,14 @@ void gk110_fifo_runlist_cgrp(struct nvkm_fifo_cgrp *, extern const struct gk104_fifo_pbdma_func gk208_fifo_pbdma; void gk208_fifo_pbdma_init_timeout(struct gk104_fifo *); +void gm107_fifo_intr_fault(struct nvkm_fifo *, int); extern const struct nvkm_enum gm107_fifo_fault_engine[]; extern const struct gk104_fifo_runlist_func gm107_fifo_runlist; extern const struct gk104_fifo_pbdma_func gm200_fifo_pbdma; int gm200_fifo_pbdma_nr(struct gk104_fifo *); +void gp100_fifo_intr_fault(struct nvkm_fifo *, int); extern const struct nvkm_enum gp100_fifo_fault_engine[]; extern const struct nvkm_enum gv100_fifo_fault_access[]; diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c index 8adfa6b182cb..f820969e4405 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.c @@ -48,6 +48,7 @@ gk110_fifo_runlist = { static const struct gk104_fifo_func gk110_fifo = { + .intr.fault = gf100_fifo_intr_fault, .pbdma = &gk104_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gk104_fifo_fault_engine, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c index 9553fb4af601..2f54787b5fd0 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.c @@ -45,6 +45,7 @@ gk208_fifo_pbdma = { static const struct gk104_fifo_func gk208_fifo = { + .intr.fault = gf100_fifo_intr_fault, .pbdma = &gk208_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gk104_fifo_fault_engine, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c index a4c6ac3cd6c7..a814c4e0ed3e 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.c @@ -26,6 +26,7 @@ static const struct gk104_fifo_func gk20a_fifo = { + .intr.fault = gf100_fifo_intr_fault, .pbdma = &gk208_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gk104_fifo_fault_engine, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c index acf230764cb0..c2a2e4572f6c 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.c @@ -25,6 +25,7 @@ #include "changk104.h" #include +#include #include @@ -67,8 +68,33 @@ gm107_fifo_fault_engine[] = { {} }; +void +gm107_fifo_intr_fault(struct nvkm_fifo *fifo, int unit) +{ + struct nvkm_device *device = fifo->engine.subdev.device; + u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); + u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); + u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); + u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); + struct nvkm_fault_data info; + + info.inst = (u64)inst << 12; + info.addr = ((u64)vahi << 32) | valo; + info.time = 0; + info.engine = unit; + info.valid = 1; + info.gpc = (type & 0x1f000000) >> 24; + info.client = (type & 0x00003f00) >> 8; + info.access = (type & 0x00000080) >> 7; + info.hub = (type & 0x00000040) >> 6; + info.reason = (type & 0x0000000f); + + nvkm_fifo_fault(fifo, &info); +} + static const struct gk104_fifo_func gm107_fifo = { + .intr.fault = gm107_fifo_intr_fault, .pbdma = &gk208_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gm107_fifo_fault_engine, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c index b96c1c5d6577..b8cfe3b28c4f 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.c @@ -42,6 +42,7 @@ gm200_fifo_pbdma = { static const struct gk104_fifo_func gm200_fifo = { + .intr.fault = gm107_fifo_intr_fault, .pbdma = &gm200_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gm107_fifo_fault_engine, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c index a49539b9e4ec..70b4feebc1fa 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm20b.c @@ -26,6 +26,7 @@ static const struct gk104_fifo_func gm20b_fifo = { + .intr.fault = gm107_fifo_intr_fault, .pbdma = &gm200_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gm107_fifo_fault_engine, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c index 54377e0f6a88..2c7a0176b3c8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.c @@ -24,6 +24,8 @@ #include "gk104.h" #include "changk104.h" +#include + #include const struct nvkm_enum @@ -50,8 +52,33 @@ gp100_fifo_fault_engine[] = { {} }; +void +gp100_fifo_intr_fault(struct nvkm_fifo *fifo, int unit) +{ + struct nvkm_device *device = fifo->engine.subdev.device; + u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); + u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); + u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); + u32 type = nvkm_rd32(device, 0x00280c + (unit * 0x10)); + struct nvkm_fault_data info; + + info.inst = (u64)inst << 12; + info.addr = ((u64)vahi << 32) | valo; + info.time = 0; + info.engine = unit; + info.valid = 1; + info.gpc = (type & 0x1f000000) >> 24; + info.hub = (type & 0x00100000) >> 20; + info.access = (type & 0x00070000) >> 16; + info.client = (type & 0x00007f00) >> 8; + info.reason = (type & 0x0000001f); + + nvkm_fifo_fault(fifo, &info); +} + static const struct gk104_fifo_func gp100_fifo = { + .intr.fault = gp100_fifo_intr_fault, .pbdma = &gm200_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gp100_fifo_fault_engine, diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c index 778ba7e46fb3..8c65ad4feedb 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp10b.c @@ -26,6 +26,7 @@ static const struct gk104_fifo_func gp10b_fifo = { + .intr.fault = gp100_fifo_intr_fault, .pbdma = &gm200_fifo_pbdma, .fault.access = gk104_fifo_fault_access, .fault.engine = gp100_fifo_fault_engine, -- cgit From 7c844e9d95fb210b40398516d3d7525e8fa38a5f Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Mon, 3 Jun 2019 01:59:42 -0400 Subject: drm/nouveau/kms/nv50-: remove overlay alpha formats The overlay logic can only do colorkey-based selection, not alpha-blending. Signed-off-by: Ilia Mirkin Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/ovly507e.c | 2 -- drivers/gpu/drm/nouveau/dispnv50/ovly827e.c | 3 --- drivers/gpu/drm/nouveau/dispnv50/ovly907e.c | 4 ---- drivers/gpu/drm/nouveau/dispnv50/ovly917e.c | 5 ----- 4 files changed, 14 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c index 7354aaf79158..8ccd96113bad 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly507e.c @@ -161,9 +161,7 @@ ovly507e_format[] = { DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB1555, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c index aaa9fe5a4fc8..2e68fc736fe1 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly827e.c @@ -90,11 +90,8 @@ ovly827e_format[] = { DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_XBGR2101010, - DRM_FORMAT_ABGR2101010, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c index f947117d62b1..9efe5e9d5ce4 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly907e.c @@ -66,13 +66,9 @@ ovly907e_format[] = { DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_XBGR2101010, - DRM_FORMAT_ABGR2101010, DRM_FORMAT_XBGR16161616F, - DRM_FORMAT_ABGR16161616F, 0 }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c b/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c index fab567e258f9..e24d6fd23450 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/ovly917e.c @@ -26,15 +26,10 @@ ovly917e_format[] = { DRM_FORMAT_YUYV, DRM_FORMAT_UYVY, DRM_FORMAT_XRGB8888, - DRM_FORMAT_ARGB8888, DRM_FORMAT_XRGB1555, - DRM_FORMAT_ARGB1555, DRM_FORMAT_XBGR2101010, - DRM_FORMAT_ABGR2101010, DRM_FORMAT_XRGB2101010, - DRM_FORMAT_ARGB2101010, DRM_FORMAT_XBGR16161616F, - DRM_FORMAT_ABGR16161616F, 0 }; -- cgit From 88b703527ba70659365d989f29579f1292ebf9c3 Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Tue, 11 Jun 2019 22:40:36 -0400 Subject: drm/nouveau/kms/gf119-: add ctm property support This adds support on GF119:GV100 (exclusive) for CTM (aka CSC). Signed-off-by: Ilia Mirkin --- drivers/gpu/drm/nouveau/dispnv50/atom.h | 6 +++ drivers/gpu/drm/nouveau/dispnv50/base907c.c | 65 +++++++++++++++++++++++++++++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 14 +++++++ drivers/gpu/drm/nouveau/dispnv50/wndw.h | 4 ++ 4 files changed, 89 insertions(+) diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h index b5fae5ab3fa8..75bda111da10 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/atom.h +++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h @@ -184,6 +184,11 @@ struct nv50_wndw_atom { } i; } xlut; + struct { + u32 matrix[12]; + bool valid; + } csc; + struct { u8 mode:2; u8 interval:4; @@ -221,6 +226,7 @@ struct nv50_wndw_atom { bool ntfy:1; bool sema:1; bool xlut:1; + bool csc:1; bool image:1; bool scale:1; bool point:1; diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index 049ce6da321c..fd0c1d84730b 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -83,6 +83,68 @@ base907c_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) asyw->xlut.i.load = head907d_olut_load; } +static inline u32 +csc_drm_to_base(u64 in) +{ + /* base takes a 19-bit 2's complement value in S3.16 format */ + bool sign = in & BIT_ULL(63); + u32 integer = (in >> 32) & 0x7fffffff; + u32 fraction = in & 0xffffffff; + + if (integer >= 4) { + return (1 << 18) - (sign ? 0 : 1); + } else { + u32 ret = (integer << 16) | (fraction >> 16); + if (sign) + ret = -ret; + return ret & GENMASK(18, 0); + } +} + +static void +base907c_csc(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, + const struct drm_color_ctm *ctm) +{ + int i, j; + + for (j = 0; j < 3; j++) { + for (i = 0; i < 4; i++) { + u32 *val = &asyw->csc.matrix[j * 4 + i]; + /* DRM does not support constant offset, while + * HW CSC does. Skip it. */ + if (i == 3) { + *val = 0; + } else { + *val = csc_drm_to_base(ctm->matrix[j * 3 + i]); + } + } + } +} + +static void +base907c_csc_clr(struct nv50_wndw *wndw) +{ + u32 *push; + if ((push = evo_wait(&wndw->wndw, 2))) { + evo_mthd(push, 0x0140, 1); + evo_data(push, 0x00000000); + evo_kick(push, &wndw->wndw); + } +} + +static void +base907c_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) +{ + u32 *push, i; + if ((push = evo_wait(&wndw->wndw, 13))) { + evo_mthd(push, 0x0140, 12); + evo_data(push, asyw->csc.matrix[0] | 0x80000000); + for (i = 1; i < 12; i++) + evo_data(push, asyw->csc.matrix[i]); + evo_kick(push, &wndw->wndw); + } +} + const struct nv50_wndw_func base907c = { .acquire = base507c_acquire, @@ -94,6 +156,9 @@ base907c = { .ntfy_clr = base507c_ntfy_clr, .ntfy_wait_begun = base507c_ntfy_wait_begun, .ilut = base907c_ilut, + .csc = base907c_csc, + .csc_set = base907c_csc_set, + .csc_clr = base907c_csc_clr, .olut_core = true, .xlut_set = base907c_xlut_set, .xlut_clr = base907c_xlut_clr, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index dd01ea21da97..c8d078629722 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -120,6 +120,7 @@ nv50_wndw_flush_clr(struct nv50_wndw *wndw, u32 *interlock, bool flush, if (clr.sema ) wndw->func-> sema_clr(wndw); if (clr.ntfy ) wndw->func-> ntfy_clr(wndw); if (clr.xlut ) wndw->func-> xlut_clr(wndw); + if (clr.csc ) wndw->func-> csc_clr(wndw); if (clr.image) wndw->func->image_clr(wndw); interlock[wndw->interlock.type] |= wndw->interlock.data; @@ -147,6 +148,7 @@ nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, wndw->func->xlut_set(wndw, asyw); } + if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); if (asyw->set.scale) wndw->func->scale_set(wndw, asyw); if (asyw->set.point) { if (asyw->set.point = false, asyw->set.mask) @@ -347,6 +349,16 @@ nv50_wndw_atomic_check_lut(struct nv50_wndw *wndw, (!armw->visible || (armw->xlut.handle && !asyw->xlut.handle))) asyw->set.xlut = true; + if (wndw->func->csc && asyh->state.ctm) { + const struct drm_color_ctm *ctm = asyh->state.ctm->data; + wndw->func->csc(wndw, asyw, ctm); + asyw->csc.valid = true; + asyw->set.csc = true; + } else { + asyw->csc.valid = false; + asyw->clr.csc = armw->csc.valid; + } + /* Can't do an immediate flip while changing the LUT. */ asyh->state.pageflip_flags &= ~DRM_MODE_PAGE_FLIP_ASYNC; } @@ -416,6 +428,7 @@ nv50_wndw_atomic_check(struct drm_plane *plane, struct drm_plane_state *state) asyw->clr.ntfy = armw->ntfy.handle != 0; asyw->clr.sema = armw->sema.handle != 0; asyw->clr.xlut = armw->xlut.handle != 0; + asyw->clr.csc = armw->csc.valid; if (wndw->func->image_clr) asyw->clr.image = armw->image.handle[0] != 0; } @@ -507,6 +520,7 @@ nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) asyw->ntfy = armw->ntfy; asyw->ilut = NULL; asyw->xlut = armw->xlut; + asyw->csc = armw->csc; asyw->image = armw->image; asyw->point = armw->point; asyw->clr.mask = 0; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 03f3d8dc235a..1e781d80c990 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -65,6 +65,10 @@ struct nv50_wndw_func { int (*ntfy_wait_begun)(struct nouveau_bo *, u32 offset, struct nvif_device *); void (*ilut)(struct nv50_wndw *, struct nv50_wndw_atom *); + void (*csc)(struct nv50_wndw *, struct nv50_wndw_atom *, + const struct drm_color_ctm *); + void (*csc_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + void (*csc_clr)(struct nv50_wndw *); bool ilut_identity; bool olut_core; void (*xlut_set)(struct nv50_wndw *, struct nv50_wndw_atom *); -- cgit From af364a447b4ac34c719751fdec5dbdd74d888c3b Mon Sep 17 00:00:00 2001 From: Ilia Mirkin Date: Mon, 10 Jun 2019 22:32:45 -0400 Subject: drm/nouveau/kms/nv50-: enable modern color management properties For GF119:GV100, we can enable DEGAMMA/CTM/GAMMA. For earlier GPUs, as there is no CTM, having both degamma and gamma is a bit pointless. Later GPUs currently lack an implementation. Signed-off-by: Ilia Mirkin Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/head.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 929d93b1677e..46e7f4c51f10 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -512,6 +512,11 @@ nv50_head_create(struct drm_device *dev, int index) &nv50_head_func, "head-%d", head->base.index); drm_crtc_helper_add(crtc, &nv50_head_help); drm_mode_crtc_set_gamma_size(crtc, 256); + if (disp->disp->object.oclass >= GF110_DISP && + disp->disp->object.oclass < GV100_DISP) + drm_crtc_enable_color_mgmt(crtc, 256, true, 256); + else + drm_crtc_enable_color_mgmt(crtc, 0, false, 256); if (head->func->olut_set) { ret = nv50_lut_init(disp, &drm->client.mmu, &head->olut); -- cgit From 2c7442ea17f32a9d6eb8c6672478e7a6fafd4631 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 14:54:32 +1000 Subject: drm/nouveau/kms/gv100-: use premultiplied alpha blending between planes This is apparently the assumed default behaviour when blend properties are absent. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 826d1d760d3a..8a4f0e436be6 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -107,10 +107,10 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) asyw->state.crtc_w); /*XXX: Composition-related stuff. Need to implement properly. */ - evo_mthd(push, 0x02ec, 1); + evo_mthd(push, 0x02ec, 7); evo_data(push, (2 - (wndw->id & 1)) << 4); - evo_mthd(push, 0x02f4, 5); - evo_data(push, 0x00000011); + evo_data(push, 0x000000ff); + evo_data(push, 0x00007722); evo_data(push, 0xffff0000); evo_data(push, 0xffff0000); evo_data(push, 0xffff0000); -- cgit From dffa487822d1ff8f44817124d8f2927057a57775 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 17:46:39 +1000 Subject: drm/nouveau/kms/gv100-: implement csc + enable modern colour managment properties Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/base907c.c | 2 +- drivers/gpu/drm/nouveau/dispnv50/head.c | 3 +- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 4 +- drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 26 ++++++++++- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 71 ++++++++++++++++++++++++++++- 5 files changed, 99 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/base907c.c b/drivers/gpu/drm/nouveau/dispnv50/base907c.c index fd0c1d84730b..5f2de77e0f32 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/base907c.c +++ b/drivers/gpu/drm/nouveau/dispnv50/base907c.c @@ -101,7 +101,7 @@ csc_drm_to_base(u64 in) } } -static void +void base907c_csc(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw, const struct drm_color_ctm *ctm) { diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 46e7f4c51f10..0d1108eadcff 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -512,8 +512,7 @@ nv50_head_create(struct drm_device *dev, int index) &nv50_head_func, "head-%d", head->base.index); drm_crtc_helper_add(crtc, &nv50_head_help); drm_mode_crtc_set_gamma_size(crtc, 256); - if (disp->disp->object.oclass >= GF110_DISP && - disp->disp->object.oclass < GV100_DISP) + if (disp->disp->object.oclass >= GF110_DISP) drm_crtc_enable_color_mgmt(crtc, 256, true, 256); else drm_crtc_enable_color_mgmt(crtc, 0, false, 256); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 1e781d80c990..59ff8f082542 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -85,6 +85,9 @@ extern const struct drm_plane_funcs nv50_wndw; void base507c_ntfy_reset(struct nouveau_bo *, u32); int base507c_ntfy_wait_begun(struct nouveau_bo *, u32, struct nvif_device *); +void base907c_csc(struct nv50_wndw *, struct nv50_wndw_atom *, + const struct drm_color_ctm *); + struct nv50_wimm_func { void (*point)(struct nv50_wndw *, struct nv50_wndw_atom *); @@ -106,7 +109,6 @@ void wndwc37e_sema_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_sema_clr(struct nv50_wndw *); void wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_ntfy_clr(struct nv50_wndw *); -void wndwc37e_image_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_image_clr(struct nv50_wndw *); void wndwc37e_update(struct nv50_wndw *, u32 *); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 8a4f0e436be6..0d270cd5ac4c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -28,6 +28,23 @@ #include +static void +wndwc37e_csc_clr(struct nv50_wndw *wndw) +{ +} + +static void +wndwc37e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) +{ + u32 *push, i; + if ((push = evo_wait(&wndw->wndw, 13))) { + evo_mthd(push, 0x02bc, 12); + for (i = 0; i < 12; i++) + evo_data(push, asyw->csc.matrix[i]); + evo_kick(push, &wndw->wndw); + } +} + static void wndwc37e_ilut_clr(struct nv50_wndw *wndw) { @@ -77,7 +94,7 @@ wndwc37e_image_clr(struct nv50_wndw *wndw) } } -void +static void wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { u32 *push; @@ -90,7 +107,9 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) evo_mthd(push, 0x0224, 4); evo_data(push, asyw->image.h << 16 | asyw->image.w); evo_data(push, asyw->image.layout << 4 | asyw->image.blockh); - evo_data(push, asyw->image.colorspace << 8 | asyw->image.format); + evo_data(push, asyw->csc.valid << 17 | + asyw->image.colorspace << 8 | + asyw->image.format); evo_data(push, asyw->image.blocks[0] | (asyw->image.pitch[0] >> 6)); evo_mthd(push, 0x0240, 1); evo_data(push, asyw->image.handle[0]); @@ -234,6 +253,9 @@ wndwc37e = { .ilut = wndwc37e_ilut, .xlut_set = wndwc37e_ilut_set, .xlut_clr = wndwc37e_ilut_clr, + .csc = base907c_csc, + .csc_set = wndwc37e_csc_set, + .csc_clr = wndwc37e_csc_clr, .image_set = wndwc37e_image_set, .image_clr = wndwc37e_image_clr, .update = wndwc37e_update, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index ba89f1a5fcfa..d5e4b006ae1e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -28,6 +28,72 @@ #include +static void +wndwc57e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) +{ + u32 *push; + + if (!(push = evo_wait(&wndw->wndw, 17))) + return; + + evo_mthd(push, 0x0308, 1); + evo_data(push, asyw->image.mode << 4 | asyw->image.interval); + evo_mthd(push, 0x0224, 4); + evo_data(push, asyw->image.h << 16 | asyw->image.w); + evo_data(push, asyw->image.layout << 4 | asyw->image.blockh); + evo_data(push, asyw->image.colorspace << 8 | + asyw->image.format); + evo_data(push, asyw->image.blocks[0] | (asyw->image.pitch[0] >> 6)); + evo_mthd(push, 0x0240, 1); + evo_data(push, asyw->image.handle[0]); + evo_mthd(push, 0x0260, 1); + evo_data(push, asyw->image.offset[0] >> 8); + evo_mthd(push, 0x0290, 1); + evo_data(push, (asyw->state.src_y >> 16) << 16 | + (asyw->state.src_x >> 16)); + evo_mthd(push, 0x0298, 1); + evo_data(push, (asyw->state.src_h >> 16) << 16 | + (asyw->state.src_w >> 16)); + evo_mthd(push, 0x02a4, 1); + evo_data(push, asyw->state.crtc_h << 16 | + asyw->state.crtc_w); + evo_kick(push, &wndw->wndw); +} + +static void +wndwc57e_csc_clr(struct nv50_wndw *wndw) +{ + u32 *push; + if ((push = evo_wait(&wndw->wndw, 13))) { + evo_mthd(push, 0x0400, 12); + evo_data(push, 0x00010000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00010000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00000000); + evo_data(push, 0x00010000); + evo_data(push, 0x00000000); + evo_kick(push, &wndw->wndw); + } +} + +static void +wndwc57e_csc_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) +{ + u32 *push, i; + if ((push = evo_wait(&wndw->wndw, 13))) { + evo_mthd(push, 0x0400, 12); + for (i = 0; i < 12; i++) + evo_data(push, asyw->csc.matrix[i]); + evo_kick(push, &wndw->wndw); + } +} + static void wndwc57e_ilut_clr(struct nv50_wndw *wndw) { @@ -119,7 +185,10 @@ wndwc57e = { .ilut_identity = true, .xlut_set = wndwc57e_ilut_set, .xlut_clr = wndwc57e_ilut_clr, - .image_set = wndwc37e_image_set, + .csc = base907c_csc, + .csc_set = wndwc57e_csc_set, + .csc_clr = wndwc57e_csc_clr, + .image_set = wndwc57e_image_set, .image_clr = wndwc37e_image_clr, .update = wndwc37e_update, }; -- cgit From a4ec848910a32c0a1e35504088d579c6e2a017f4 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 18:04:42 +1000 Subject: drm/nouveau/kms/nv50-: use __drm_atomic_helper_plane_reset() We have some of this open-coded already, use the helper to prevent problems when adding (for example) support for the alpha property. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/wndw.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index c8d078629722..f671fea8b26d 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -538,9 +538,8 @@ nv50_wndw_reset(struct drm_plane *plane) if (plane->state) plane->funcs->atomic_destroy_state(plane, plane->state); - plane->state = &asyw->state; - plane->state->plane = plane; - plane->state->rotation = DRM_MODE_ROTATE_0; + + __drm_atomic_helper_plane_reset(plane, &asyw->state); } static void -- cgit From 6f78991fbcfe44c762fe783812f08500a8411ea9 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 17:03:21 +1000 Subject: drm/nouveau/kms/nv50-: create primary plane before overlay planes zpos normalisation uses plane id to determine ordering for duplicate zpos values, and we likely want to keep primary plane on the bottom here. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/head.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/head.c b/drivers/gpu/drm/nouveau/dispnv50/head.c index 0d1108eadcff..71c23bf1fe25 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/head.c +++ b/drivers/gpu/drm/nouveau/dispnv50/head.c @@ -480,7 +480,7 @@ nv50_head_create(struct drm_device *dev, int index) struct nouveau_drm *drm = nouveau_drm(dev); struct nv50_disp *disp = nv50_disp(dev); struct nv50_head *head; - struct nv50_wndw *curs, *wndw; + struct nv50_wndw *base, *ovly, *curs; struct drm_crtc *crtc; int ret; @@ -492,13 +492,13 @@ nv50_head_create(struct drm_device *dev, int index) head->base.index = index; if (disp->disp->object.oclass < GV100_DISP) { - ret = nv50_ovly_new(drm, head->base.index, &wndw); - ret = nv50_base_new(drm, head->base.index, &wndw); + ret = nv50_base_new(drm, head->base.index, &base); + ret = nv50_ovly_new(drm, head->base.index, &ovly); } else { - ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY, - head->base.index * 2 + 1, &wndw); ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_PRIMARY, - head->base.index * 2 + 0, &wndw); + head->base.index * 2 + 0, &base); + ret = nv50_wndw_new(drm, DRM_PLANE_TYPE_OVERLAY, + head->base.index * 2 + 1, &ovly); } if (ret == 0) ret = nv50_curs_new(drm, head->base.index, &curs); @@ -508,7 +508,7 @@ nv50_head_create(struct drm_device *dev, int index) } crtc = &head->base.base; - drm_crtc_init_with_planes(dev, crtc, &wndw->plane, &curs->plane, + drm_crtc_init_with_planes(dev, crtc, &base->plane, &curs->plane, &nv50_head_func, "head-%d", head->base.index); drm_crtc_helper_add(crtc, &nv50_head_help); drm_mode_crtc_set_gamma_size(crtc, 256); -- cgit From 7a962f2b7276ccfb844583f0db5680e763d6f6da Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 16:40:31 +1000 Subject: drm/nouveau/kms/nv50-: attach immutable zpos property to planes Defaulting to the fixed layout enforced in HW by EVO, and that we currently use by default on NVD. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 1 + drivers/gpu/drm/nouveau/dispnv50/wndw.c | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 7ce7145f82b8..146e54ef672e 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -2316,6 +2316,7 @@ nv50_display_create(struct drm_device *dev) disp->disp = &nouveau_display(dev)->disp; dev->mode_config.funcs = &nv50_disp_func; dev->mode_config.quirk_addfb_prefer_xbgr_30bpp = true; + dev->mode_config.normalize_zpos = true; /* small shared memory area we use for notifiers and semaphores */ ret = nouveau_bo_new(&drm->client, 4096, 0x1000, TTM_PL_FLAG_VRAM, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index f671fea8b26d..b347a68eebd0 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -528,6 +528,13 @@ nv50_wndw_atomic_duplicate_state(struct drm_plane *plane) return &asyw->state; } +static int +nv50_wndw_zpos_default(struct drm_plane *plane) +{ + return (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : + (plane->type == DRM_PLANE_TYPE_OVERLAY) ? 1 : 255; +} + static void nv50_wndw_reset(struct drm_plane *plane) { @@ -540,6 +547,8 @@ nv50_wndw_reset(struct drm_plane *plane) plane->funcs->atomic_destroy_state(plane, plane->state); __drm_atomic_helper_plane_reset(plane, &asyw->state); + plane->state->zpos = nv50_wndw_zpos_default(plane); + plane->state->normalized_zpos = nv50_wndw_zpos_default(plane); } static void @@ -634,6 +643,14 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, } wndw->notify.func = nv50_wndw_notify; + + if (1) { + ret = drm_plane_create_zpos_immutable_property(&wndw->plane, + nv50_wndw_zpos_default(&wndw->plane)); + if (ret) + return ret; + } + return 0; } -- cgit From 9a99e904cc5b08f8eda2366135404fe72dae16af Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 16:46:13 +1000 Subject: drm/nouveau/kms/gv100-: add support for plane zpos property Has a nice side-effect that we only update HW for this when it changes now, rather than every time we do a page flip. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/atom.h | 5 +++++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 14 +++++++++++++- drivers/gpu/drm/nouveau/dispnv50/wndw.h | 2 ++ drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 30 ++++++++++++++++++----------- drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c | 1 + 5 files changed, 40 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h index 75bda111da10..3192f067d291 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/atom.h +++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h @@ -221,6 +221,10 @@ struct nv50_wndw_atom { u16 y; } point; + struct { + u8 depth; + } blend; + union nv50_wndw_atom_mask { struct { bool ntfy:1; @@ -230,6 +234,7 @@ struct nv50_wndw_atom { bool image:1; bool scale:1; bool point:1; + bool blend:1; }; u8 mask; } set, clr; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index b347a68eebd0..10fcd4e1e44c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -150,6 +150,7 @@ nv50_wndw_flush_set(struct nv50_wndw *wndw, u32 *interlock, if (asyw->set.csc ) wndw->func->csc_set (wndw, asyw); if (asyw->set.scale) wndw->func->scale_set(wndw, asyw); + if (asyw->set.blend) wndw->func->blend_set(wndw, asyw); if (asyw->set.point) { if (asyw->set.point = false, asyw->set.mask) interlock[wndw->interlock.type] |= wndw->interlock.data; @@ -285,6 +286,12 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, asyw->set.scale = true; } + if (wndw->func->blend_set) { + asyw->blend.depth = 255 - asyw->state.normalized_zpos; + if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) + asyw->set.blend = true; + } + if (wndw->immd) { asyw->point.x = asyw->state.crtc_x; asyw->point.y = asyw->state.crtc_y; @@ -644,7 +651,12 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, wndw->notify.func = nv50_wndw_notify; - if (1) { + if (wndw->func->blend_set) { + ret = drm_plane_create_zpos_property(&wndw->plane, + nv50_wndw_zpos_default(&wndw->plane), 0, 254); + if (ret) + return ret; + } else { ret = drm_plane_create_zpos_immutable_property(&wndw->plane, nv50_wndw_zpos_default(&wndw->plane)); if (ret) diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.h b/drivers/gpu/drm/nouveau/dispnv50/wndw.h index 59ff8f082542..c63bd3bdaf06 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.h +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.h @@ -76,6 +76,7 @@ struct nv50_wndw_func { void (*image_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*image_clr)(struct nv50_wndw *); void (*scale_set)(struct nv50_wndw *, struct nv50_wndw_atom *); + void (*blend_set)(struct nv50_wndw *, struct nv50_wndw_atom *); void (*update)(struct nv50_wndw *, u32 *interlock); }; @@ -110,6 +111,7 @@ void wndwc37e_sema_clr(struct nv50_wndw *); void wndwc37e_ntfy_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_ntfy_clr(struct nv50_wndw *); void wndwc37e_image_clr(struct nv50_wndw *); +void wndwc37e_blend_set(struct nv50_wndw *, struct nv50_wndw_atom *); void wndwc37e_update(struct nv50_wndw *, u32 *); int wndwc57e_new(struct nouveau_drm *, enum drm_plane_type, int, s32, diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 0d270cd5ac4c..4d2d54a8c659 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -81,6 +81,23 @@ wndwc37e_ilut(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) asyw->xlut.i.load = head907d_olut_load; } +void +wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) +{ + u32 *push; + if ((push = evo_wait(&wndw->wndw, 8))) { + evo_mthd(push, 0x02ec, 7); + evo_data(push, asyw->blend.depth << 4); + evo_data(push, 0x000000ff); + evo_data(push, 0x00007722); + evo_data(push, 0xffff0000); + evo_data(push, 0xffff0000); + evo_data(push, 0xffff0000); + evo_data(push, 0xffff0000); + evo_kick(push, &wndw->wndw); + } +} + void wndwc37e_image_clr(struct nv50_wndw *wndw) { @@ -99,7 +116,7 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) { u32 *push; - if (!(push = evo_wait(&wndw->wndw, 25))) + if (!(push = evo_wait(&wndw->wndw, 17))) return; evo_mthd(push, 0x0308, 1); @@ -124,16 +141,6 @@ wndwc37e_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) evo_mthd(push, 0x02a4, 1); evo_data(push, asyw->state.crtc_h << 16 | asyw->state.crtc_w); - - /*XXX: Composition-related stuff. Need to implement properly. */ - evo_mthd(push, 0x02ec, 7); - evo_data(push, (2 - (wndw->id & 1)) << 4); - evo_data(push, 0x000000ff); - evo_data(push, 0x00007722); - evo_data(push, 0xffff0000); - evo_data(push, 0xffff0000); - evo_data(push, 0xffff0000); - evo_data(push, 0xffff0000); evo_kick(push, &wndw->wndw); } @@ -258,6 +265,7 @@ wndwc37e = { .csc_clr = wndwc37e_csc_clr, .image_set = wndwc37e_image_set, .image_clr = wndwc37e_image_clr, + .blend_set = wndwc37e_blend_set, .update = wndwc37e_update, }; diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c index d5e4b006ae1e..a311c79e5295 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc57e.c @@ -190,6 +190,7 @@ wndwc57e = { .csc_clr = wndwc57e_csc_clr, .image_set = wndwc57e_image_set, .image_clr = wndwc37e_image_clr, + .blend_set = wndwc37e_blend_set, .update = wndwc37e_update, }; -- cgit From a0a76244760d8b72ba1bb9c6998e41f5d286d6aa Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 11 Jun 2019 17:13:04 +1000 Subject: drm/nouveau/kms/gv100-: attach alpha property to planes Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/atom.h | 1 + drivers/gpu/drm/nouveau/dispnv50/wndw.c | 5 +++++ drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h index 3192f067d291..973074403f3c 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/atom.h +++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h @@ -223,6 +223,7 @@ struct nv50_wndw_atom { struct { u8 depth; + u8 k1; } blend; union nv50_wndw_atom_mask { diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 10fcd4e1e44c..76c69c6eca77 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -288,6 +288,7 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, if (wndw->func->blend_set) { asyw->blend.depth = 255 - asyw->state.normalized_zpos; + asyw->blend.k1 = asyw->state.alpha >> 8; if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) asyw->set.blend = true; } @@ -656,6 +657,10 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, nv50_wndw_zpos_default(&wndw->plane), 0, 254); if (ret) return ret; + + ret = drm_plane_create_alpha_property(&wndw->plane); + if (ret) + return ret; } else { ret = drm_plane_create_zpos_immutable_property(&wndw->plane, nv50_wndw_zpos_default(&wndw->plane)); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 4d2d54a8c659..3c6d64d1b708 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -88,7 +88,7 @@ wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) if ((push = evo_wait(&wndw->wndw, 8))) { evo_mthd(push, 0x02ec, 7); evo_data(push, asyw->blend.depth << 4); - evo_data(push, 0x000000ff); + evo_data(push, asyw->blend.k1); evo_data(push, 0x00007722); evo_data(push, 0xffff0000); evo_data(push, 0xffff0000); -- cgit From edc641b2b2f494ce74a2f657544133faf451a80c Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Wed, 12 Jun 2019 17:37:23 +1000 Subject: drm/nouveau/kms/gv100-: attach pixel blend mode property to planes Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/atom.h | 2 ++ drivers/gpu/drm/nouveau/dispnv50/wndw.c | 22 ++++++++++++++++++++++ drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c | 5 ++++- 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/atom.h b/drivers/gpu/drm/nouveau/dispnv50/atom.h index 973074403f3c..43df86c38f58 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/atom.h +++ b/drivers/gpu/drm/nouveau/dispnv50/atom.h @@ -224,6 +224,8 @@ struct nv50_wndw_atom { struct { u8 depth; u8 k1; + u8 src_color:4; + u8 dst_color:4; } blend; union nv50_wndw_atom_mask { diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndw.c b/drivers/gpu/drm/nouveau/dispnv50/wndw.c index 76c69c6eca77..2db029371c91 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndw.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndw.c @@ -289,6 +289,21 @@ nv50_wndw_atomic_check_acquire(struct nv50_wndw *wndw, bool modeset, if (wndw->func->blend_set) { asyw->blend.depth = 255 - asyw->state.normalized_zpos; asyw->blend.k1 = asyw->state.alpha >> 8; + switch (asyw->state.pixel_blend_mode) { + case DRM_MODE_BLEND_PREMULTI: + asyw->blend.src_color = 2; /* K1 */ + asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ + break; + case DRM_MODE_BLEND_COVERAGE: + asyw->blend.src_color = 5; /* K1_TIMES_SRC */ + asyw->blend.dst_color = 7; /* NEG_K1_TIMES_SRC */ + break; + case DRM_MODE_BLEND_PIXEL_NONE: + default: + asyw->blend.src_color = 2; /* K1 */ + asyw->blend.dst_color = 4; /* NEG_K1 */ + break; + } if (memcmp(&armw->blend, &asyw->blend, sizeof(asyw->blend))) asyw->set.blend = true; } @@ -661,6 +676,13 @@ nv50_wndw_new_(const struct nv50_wndw_func *func, struct drm_device *dev, ret = drm_plane_create_alpha_property(&wndw->plane); if (ret) return ret; + + ret = drm_plane_create_blend_mode_property(&wndw->plane, + BIT(DRM_MODE_BLEND_PIXEL_NONE) | + BIT(DRM_MODE_BLEND_PREMULTI) | + BIT(DRM_MODE_BLEND_COVERAGE)); + if (ret) + return ret; } else { ret = drm_plane_create_zpos_immutable_property(&wndw->plane, nv50_wndw_zpos_default(&wndw->plane)); diff --git a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c index 3c6d64d1b708..0f9402162bde 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c +++ b/drivers/gpu/drm/nouveau/dispnv50/wndwc37e.c @@ -89,7 +89,10 @@ wndwc37e_blend_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw) evo_mthd(push, 0x02ec, 7); evo_data(push, asyw->blend.depth << 4); evo_data(push, asyw->blend.k1); - evo_data(push, 0x00007722); + evo_data(push, asyw->blend.dst_color << 12 | + asyw->blend.dst_color << 8 | + asyw->blend.src_color << 4 | + asyw->blend.src_color); evo_data(push, 0xffff0000); evo_data(push, 0xffff0000); evo_data(push, 0xffff0000); -- cgit From f0790cda65a1f1a3818db16e95c04c06cb7f2421 Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 2 Jul 2019 12:52:11 +1000 Subject: drm/nouveau/therm: skip probing for devices not specified in thermal tables Saves some time during driver load, as described by the relevant section[1] of the DCB 4.x specification. [1] https://nvidia.github.io/open-gpu-doc/DCB/DCB-4.x-Specification.html#_i2c_device_table Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h | 2 ++ drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c | 13 +++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c | 3 +++ 3 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h index f29f2d8da142..9ac3dda4b44f 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/extdev.h @@ -26,4 +26,6 @@ nvbios_extdev_parse(struct nvkm_bios *, int, struct nvbios_extdev_func *); int nvbios_extdev_find(struct nvkm_bios *, enum nvbios_extdev_type, struct nvbios_extdev_func *); + +bool nvbios_extdev_skip_probe(struct nvkm_bios *); #endif diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c index b8578359e61b..118e33174cbe 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.c @@ -46,6 +46,19 @@ extdev_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *len, u8 *cnt) return extdev + *hdr; } +bool +nvbios_extdev_skip_probe(struct nvkm_bios *bios) +{ + u8 ver, hdr, len, cnt; + u16 data = extdev_table(bios, &ver, &hdr, &len, &cnt); + if (data && ver == 0x40 && hdr >= 5) { + u8 flags = nvbios_rd08(bios, data - hdr + 4); + if (flags & 1) + return true; + } + return false; +} + static u16 nvbios_extdev_entry(struct nvkm_bios *bios, int idx, u8 *ver, u8 *len) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c index 6e0ddc1bb583..03b355dabab3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.c @@ -116,6 +116,9 @@ nvkm_therm_ic_ctor(struct nvkm_therm *therm) return; } + if (nvbios_extdev_skip_probe(bios)) + return; + /* The vbios doesn't provide the address of an exisiting monitoring device. Let's try our static list. */ -- cgit From 69cbbb7b04ff57c17018b27a86e9c2d758d4366e Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Tue, 2 Jul 2019 14:19:12 +1000 Subject: drm/nouveau/therm: don't attempt fan control where PMU is already managing it There's already a condition in place which attempts to detect this, but since we've begun to require a PMU subdev even on boards where we don't load a custom FW, it's become inaccurate. This will prevent unnecessarily running a periodic fan update thread on GP100 and newer, where we don't yet override the default PMU FW. Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c | 18 ++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c | 7 ++++--- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h index 24fbcccd93eb..4752006880f3 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/pmu.h @@ -30,6 +30,7 @@ struct nvkm_pmu { int nvkm_pmu_send(struct nvkm_pmu *, u32 reply[2], u32 process, u32 message, u32 data0, u32 data1); void nvkm_pmu_pgob(struct nvkm_pmu *, bool enable); +bool nvkm_pmu_fan_controlled(struct nvkm_device *); int gt215_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); int gf100_pmu_new(struct nvkm_device *, int, struct nvkm_pmu **); diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c index ce70a193caa7..ea2e11771bca 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.c @@ -26,6 +26,24 @@ #include #include +bool +nvkm_pmu_fan_controlled(struct nvkm_device *device) +{ + struct nvkm_pmu *pmu = device->pmu; + + /* Internal PMU FW does not currently control fans in any way, + * allow SW control of fans instead. + */ + if (pmu && pmu->func->code.size) + return false; + + /* Default (board-loaded, or VBIOS PMU/PREOS) PMU FW on Fermi + * and newer automatically control the fan speed, which would + * interfere with SW control. + */ + return (device->chipset >= 0xc0); +} + void nvkm_pmu_pgob(struct nvkm_pmu *pmu, bool enable) { diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c index 07914e36939e..4a4d1e224126 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c @@ -21,9 +21,11 @@ * * Authors: Martin Peres */ -#include #include "priv.h" +#include +#include + int nvkm_therm_temp_get(struct nvkm_therm *therm) { @@ -192,8 +194,7 @@ nvkm_therm_fan_mode(struct nvkm_therm *therm, int mode) /* The default PPWR ucode on fermi interferes with fan management */ if ((mode >= ARRAY_SIZE(name)) || - (mode != NVKM_THERM_CTRL_NONE && device->card_type >= NV_C0 && - !device->pmu)) + (mode != NVKM_THERM_CTRL_NONE && nvkm_pmu_fan_controlled(device))) return -EINVAL; /* do not allow automatic fan management if the thermal sensor is -- cgit From e79ef1c0076ad82bab6915ada633a9d0efcb73fa Mon Sep 17 00:00:00 2001 From: Mark Menzynski Date: Thu, 18 Jul 2019 10:07:38 +0200 Subject: drm/nouveau/bios/gpio: sort gpios by values One gpio was in wrong place, moved it for better readability. Signed-off-by: Mark Menzynski Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h index 7c4f00366e71..3f74b2726cf2 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h @@ -3,9 +3,9 @@ #define __NVBIOS_GPIO_H__ enum dcb_gpio_func_name { DCB_GPIO_PANEL_POWER = 0x01, + DCB_GPIO_FAN = 0x09, DCB_GPIO_TVDAC0 = 0x0c, DCB_GPIO_TVDAC1 = 0x2d, - DCB_GPIO_FAN = 0x09, DCB_GPIO_FAN_SENSE = 0x3d, DCB_GPIO_LOGO_LED_PWM = 0x84, DCB_GPIO_UNUSED = 0xff, -- cgit From 72251fac062c0b4fe98670ec9e3db3f0702c50ae Mon Sep 17 00:00:00 2001 From: Mark Menzynski Date: Thu, 18 Jul 2019 10:07:39 +0200 Subject: drm/nouveau/gpio: fail if gpu external power is missing Currently, nouveau doesn't check if GPU is missing power. This patch makes nouveau fail when this happens on latest GPUs. It checks GPIO function 121 (External Power Emergency), which should detect power problems on GPU initialization. This can be disabled with nouveau.config=NvPowerChecks=1 Tested on TU104, GP106 and GF100. v3: * Add config override for disabling power checks Signed-off-by: Mark Menzynski Signed-off-by: Ben Skeggs --- .../drm/nouveau/include/nvkm/subdev/bios/gpio.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c | 30 ++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h index 3f74b2726cf2..d036cdc45201 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h @@ -7,6 +7,7 @@ enum dcb_gpio_func_name { DCB_GPIO_TVDAC0 = 0x0c, DCB_GPIO_TVDAC1 = 0x2d, DCB_GPIO_FAN_SENSE = 0x3d, + DCB_GPIO_EXT_POWER_LOW = 0x79, DCB_GPIO_LOGO_LED_PWM = 0x84, DCB_GPIO_UNUSED = 0xff, DCB_GPIO_VID0 = 0x04, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c index 1399d923d446..1337a110c0e3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c @@ -23,6 +23,7 @@ */ #include "priv.h" +#include #include static int @@ -182,12 +183,41 @@ static const struct dmi_system_id gpio_reset_ids[] = { { } }; +static enum dcb_gpio_func_name power_checks[] = { + DCB_GPIO_EXT_POWER_LOW, +}; + static int nvkm_gpio_init(struct nvkm_subdev *subdev) { struct nvkm_gpio *gpio = nvkm_gpio(subdev); + struct dcb_gpio_func func; + int ret; + int i; + if (dmi_check_system(gpio_reset_ids)) nvkm_gpio_reset(gpio, DCB_GPIO_UNUSED); + + if (nvkm_boolopt(subdev->device->cfgopt, "NvPowerChecks", true)) { + for (i = 0; i < ARRAY_SIZE(power_checks); ++i) { + ret = nvkm_gpio_find(gpio, 0, power_checks[i], + DCB_GPIO_UNUSED, &func); + if (ret) + continue; + + ret = nvkm_gpio_get(gpio, 0, func.func, func.line); + if (!ret) + continue; + + nvkm_error(&gpio->subdev, + "GPU is missing power, check its power " + "cables. Boot with " + "nouveau.config=NvPowerChecks=0 to " + "disable.\n"); + return -EINVAL; + } + } + return 0; } -- cgit From 940794b3dd343ba86a4c50f7e6db285c0a9c8776 Mon Sep 17 00:00:00 2001 From: Mark Menzynski Date: Thu, 18 Jul 2019 10:07:40 +0200 Subject: drm/nouveau/gpio: check the gpio function 16 in the power check as well Added GPIO is "Thermal and External Power Detect". It's uncertain if this GPIO is set on GPU initialization or only if a change is detected by the GPU at runtime. This GPIO can be found in Rankine and Curie and rarely on Tesla GPUs VBIOS. Untested, wrote according to documentation. Signed-off-by: Mark Menzynski Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h index d036cdc45201..f454bbd29a7a 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h @@ -5,6 +5,7 @@ enum dcb_gpio_func_name { DCB_GPIO_PANEL_POWER = 0x01, DCB_GPIO_FAN = 0x09, DCB_GPIO_TVDAC0 = 0x0c, + DCB_GPIO_THERM_EXT_POWER_EVENT = 0x10, DCB_GPIO_TVDAC1 = 0x2d, DCB_GPIO_FAN_SENSE = 0x3d, DCB_GPIO_EXT_POWER_LOW = 0x79, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c index 1337a110c0e3..2aa809ce7ff3 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c @@ -184,6 +184,7 @@ static const struct dmi_system_id gpio_reset_ids[] = { }; static enum dcb_gpio_func_name power_checks[] = { + DCB_GPIO_THERM_EXT_POWER_EVENT, DCB_GPIO_EXT_POWER_LOW, }; -- cgit From 3c978f73959c295ac737b917795926534a7aea01 Mon Sep 17 00:00:00 2001 From: Mark Menzynski Date: Thu, 18 Jul 2019 10:07:41 +0200 Subject: drm/nouveau/gpio: check function 76 in the power check as well Added GPIO is "Power Alert". It's uncertain if this GPIO is set on GPU initialization or only if a change is detected by the GPU at runtime. This GPIO can be found on Tesla and sometimes on Fermi GPUs. Untested, wrote according to documentation. Signed-off-by: Mark Menzynski Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h | 1 + drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h index f454bbd29a7a..3f785f29dfac 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/gpio.h @@ -8,6 +8,7 @@ enum dcb_gpio_func_name { DCB_GPIO_THERM_EXT_POWER_EVENT = 0x10, DCB_GPIO_TVDAC1 = 0x2d, DCB_GPIO_FAN_SENSE = 0x3d, + DCB_GPIO_POWER_ALERT = 0x4c, DCB_GPIO_EXT_POWER_LOW = 0x79, DCB_GPIO_LOGO_LED_PWM = 0x84, DCB_GPIO_UNUSED = 0xff, diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c index 2aa809ce7ff3..914276410ef8 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.c @@ -185,6 +185,7 @@ static const struct dmi_system_id gpio_reset_ids[] = { static enum dcb_gpio_func_name power_checks[] = { DCB_GPIO_THERM_EXT_POWER_EVENT, + DCB_GPIO_POWER_ALERT, DCB_GPIO_EXT_POWER_LOW, }; -- cgit From 2b7e7bb16812cd3a8f85f1d8e2752ab66130a0fe Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Wed, 7 Aug 2019 19:47:05 -0400 Subject: drm/nouveau/dispnv04: Remove runtime PM Originally when trying to fix the issue of runtime PM references with non-blocking CRTCs on nv50, I ended up stumbling on this code when trying to remove nouveau_drm->have_disp_power_ref, and attempted to fix it to remove the dependency on have_disp_power_ref. However, Ilia Mirkin pointed out that this code is actually completely useless, as pre-nv50 never had runtime PM support in the first place! Go figure. So, since it's useless just get rid of it. Note that since the only thing nouveau_crtc_set_config() was doing was grabbing a runtime PM ref, calling drm_crtc_helper_set_config() then dropping the ref; we can just remove the function entirely and just call drm_crtc_helper_set_config() directly. Signed-off-by: Lyude Paul Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv04/crtc.c | 51 +-------------------------------- 1 file changed, 1 insertion(+), 50 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv04/crtc.c b/drivers/gpu/drm/nouveau/dispnv04/crtc.c index 210f13b145c1..37c50ea8f847 100644 --- a/drivers/gpu/drm/nouveau/dispnv04/crtc.c +++ b/drivers/gpu/drm/nouveau/dispnv04/crtc.c @@ -22,8 +22,6 @@ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * DEALINGS IN THE SOFTWARE. */ -#include - #include #include #include @@ -1032,53 +1030,6 @@ nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) return 0; } -static int -nouveau_crtc_set_config(struct drm_mode_set *set, - struct drm_modeset_acquire_ctx *ctx) -{ - struct drm_device *dev; - struct nouveau_drm *drm; - int ret; - struct drm_crtc *crtc; - bool active = false; - if (!set || !set->crtc) - return -EINVAL; - - dev = set->crtc->dev; - - /* get a pm reference here */ - ret = pm_runtime_get_sync(dev->dev); - if (ret < 0 && ret != -EACCES) - return ret; - - ret = drm_crtc_helper_set_config(set, ctx); - - drm = nouveau_drm(dev); - - /* if we get here with no crtcs active then we can drop a reference */ - list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { - if (crtc->enabled) - active = true; - } - - pm_runtime_mark_last_busy(dev->dev); - /* if we have active crtcs and we don't have a power ref, - take the current one */ - if (active && !drm->have_disp_power_ref) { - drm->have_disp_power_ref = true; - return ret; - } - /* if we have no active crtcs, then drop the power ref - we got before */ - if (!active && drm->have_disp_power_ref) { - pm_runtime_put_autosuspend(dev->dev); - drm->have_disp_power_ref = false; - } - /* drop the power reference we got coming in here */ - pm_runtime_put_autosuspend(dev->dev); - return ret; -} - struct nv04_page_flip_state { struct list_head head; struct drm_pending_vblank_event *event; @@ -1294,7 +1245,7 @@ static const struct drm_crtc_funcs nv04_crtc_funcs = { .cursor_set = nv04_crtc_cursor_set, .cursor_move = nv04_crtc_cursor_move, .gamma_set = nv_crtc_gamma_set, - .set_config = nouveau_crtc_set_config, + .set_config = drm_crtc_helper_set_config, .page_flip = nv04_crtc_page_flip, .destroy = nv_crtc_destroy, }; -- cgit From ed22eb56f2bf2908fef7a108809ffa208ff62c0c Mon Sep 17 00:00:00 2001 From: Lyude Paul Date: Wed, 7 Aug 2019 19:47:06 -0400 Subject: drm/nouveau/dispnv50: Fix runtime PM ref tracking for non-blocking modesets This is something that got noticed a while ago back when I was fixing a large number of runtime PM related issues in nouveau, but never got fixed: https://patchwork.freedesktop.org/series/46815/#rev7 It's not safe to iterate the entire list of CRTCs in nv50_disp_atomic_commit(), as we could be doing a non-blocking modeset on one CRTC in parallel with one or more other CRTCs. Likewise, this means it's also not safe to do so in order to track runtime PM state. While this code is certainly wrong, so far the only issues I've seen this cause in the wild is the occasional PM ref unbalance after an atomic check failure + module reloading (since the PCI device will outlive nouveau in such scenarios). So, do this far more elegantly: grab a runtime PM ref across the modeset and commit tail, then grab/put references for each CRTC enable/disable. This also ends up being much simpler then the previous broken solution we had. Finally, since we've removed all it's users: get rid of nouveau_drm->have_disp_power_ref. Signed-off-by: Lyude Paul Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/dispnv50/disp.c | 38 +++++++++++++++------------------ drivers/gpu/drm/nouveau/nouveau_drv.h | 3 --- 2 files changed, 17 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c index 146e54ef672e..f1dbc7852414 100644 --- a/drivers/gpu/drm/nouveau/dispnv50/disp.c +++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c @@ -1826,8 +1826,11 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) NV_ATOMIC(drm, "%s: clr %04x (set %04x)\n", crtc->name, asyh->clr.mask, asyh->set.mask); - if (old_crtc_state->active && !new_crtc_state->active) + + if (old_crtc_state->active && !new_crtc_state->active) { + pm_runtime_put_noidle(dev->dev); drm_crtc_vblank_off(crtc); + } if (asyh->clr.mask) { nv50_head_flush_clr(head, asyh, atom->flush_disable); @@ -1913,8 +1916,10 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) } if (new_crtc_state->active) { - if (!old_crtc_state->active) + if (!old_crtc_state->active) { drm_crtc_vblank_on(crtc); + pm_runtime_get_noresume(dev->dev); + } if (new_crtc_state->event) drm_crtc_vblank_get(crtc); } @@ -1979,6 +1984,10 @@ nv50_disp_atomic_commit_tail(struct drm_atomic_state *state) drm_atomic_helper_cleanup_planes(dev, state); drm_atomic_helper_commit_cleanup_done(state); drm_atomic_state_put(state); + + /* Drop the RPM ref we got from nv50_disp_atomic_commit() */ + pm_runtime_mark_last_busy(dev->dev); + pm_runtime_put_autosuspend(dev->dev); } static void @@ -1993,11 +2002,8 @@ static int nv50_disp_atomic_commit(struct drm_device *dev, struct drm_atomic_state *state, bool nonblock) { - struct nouveau_drm *drm = nouveau_drm(dev); struct drm_plane_state *new_plane_state; struct drm_plane *plane; - struct drm_crtc *crtc; - bool active = false; int ret, i; ret = pm_runtime_get_sync(dev->dev); @@ -2034,27 +2040,17 @@ nv50_disp_atomic_commit(struct drm_device *dev, drm_atomic_state_get(state); + /* + * Grab another RPM ref for the commit tail, which will release the + * ref when it's finished + */ + pm_runtime_get_noresume(dev->dev); + if (nonblock) queue_work(system_unbound_wq, &state->commit_work); else nv50_disp_atomic_commit_tail(state); - drm_for_each_crtc(crtc, dev) { - if (crtc->state->active) { - if (!drm->have_disp_power_ref) { - drm->have_disp_power_ref = true; - return 0; - } - active = true; - break; - } - } - - if (!active && drm->have_disp_power_ref) { - pm_runtime_put_autosuspend(dev->dev); - drm->have_disp_power_ref = false; - } - err_cleanup: if (ret) drm_atomic_helper_cleanup_planes(dev, state); diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h index cf0d0a416af6..70f34cacc552 100644 --- a/drivers/gpu/drm/nouveau/nouveau_drv.h +++ b/drivers/gpu/drm/nouveau/nouveau_drv.h @@ -206,9 +206,6 @@ struct nouveau_drm { /* led management */ struct nouveau_led *led; - /* display power reference */ - bool have_disp_power_ref; - struct dev_pm_domain vga_pm_domain; struct nouveau_svm *svm; -- cgit From a1af2afbd244089560794c260b2d4326a86e39b6 Mon Sep 17 00:00:00 2001 From: Mark Menzynski Date: Fri, 2 Aug 2019 11:21:00 +0200 Subject: drm/nouveau/volt: Fix for some cards having 0 maximum voltage Some, mostly Fermi, vbioses appear to have zero max voltage. That causes Nouveau to not parse voltage entries, thus users not being able to set higher clocks. When changing this value Nvidia driver still appeared to ignore it, and I wasn't able to find out why, thus the code is ignoring the value if it is zero. CC: Maarten Lankhorst Signed-off-by: Mark Menzynski Reviewed-by: Karol Herbst Signed-off-by: Ben Skeggs --- drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c index 7143ea4611aa..33a9fb5ac558 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.c @@ -96,6 +96,8 @@ nvbios_volt_parse(struct nvkm_bios *bios, u8 *ver, u8 *hdr, u8 *cnt, u8 *len, info->min = min(info->base, info->base + info->step * info->vidmask); info->max = nvbios_rd32(bios, volt + 0x0e); + if (!info->max) + info->max = max(info->base, info->base + info->step * info->vidmask); break; case 0x50: info->min = nvbios_rd32(bios, volt + 0x0a); -- cgit