From ccb5597f9ba11b67b8aa8c6f4682675eceee0e21 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Mon, 5 Oct 2015 20:06:01 +0200 Subject: tools lib api fs: No need to use PATH_MAX + 1 Because there's no point, PATH_MAX is big enough. Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Don Zickus Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1444068369-20978-2-git-send-email-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/lib/api/fs/fs.c | 2 +- tools/lib/api/fs/tracing_path.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/lib/api/fs/fs.c b/tools/lib/api/fs/fs.c index 732dbef588b0..459599d1b6c4 100644 --- a/tools/lib/api/fs/fs.c +++ b/tools/lib/api/fs/fs.c @@ -69,7 +69,7 @@ static const char * const tracefs__known_mountpoints[] = { struct fs { const char *name; const char * const *mounts; - char path[PATH_MAX + 1]; + char path[PATH_MAX]; bool found; long magic; }; diff --git a/tools/lib/api/fs/tracing_path.c b/tools/lib/api/fs/tracing_path.c index 0406a7d5c891..a26bb5ea8283 100644 --- a/tools/lib/api/fs/tracing_path.c +++ b/tools/lib/api/fs/tracing_path.c @@ -12,9 +12,9 @@ #include "tracing_path.h" -char tracing_mnt[PATH_MAX + 1] = "/sys/kernel/debug"; -char tracing_path[PATH_MAX + 1] = "/sys/kernel/debug/tracing"; -char tracing_events_path[PATH_MAX + 1] = "/sys/kernel/debug/tracing/events"; +char tracing_mnt[PATH_MAX] = "/sys/kernel/debug"; +char tracing_path[PATH_MAX] = "/sys/kernel/debug/tracing"; +char tracing_events_path[PATH_MAX] = "/sys/kernel/debug/tracing/events"; static void __tracing_path_set(const char *tracing, const char *mountpoint) -- cgit From 84422592e58f6f1ea03688fcf92143bbc095fa88 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Mon, 5 Oct 2015 20:06:02 +0200 Subject: perf evlist: Display DATA_SRC sample type bit Adding DATA_SRC bit_name call to display sample_type properly. $ perf evlist -v cpu/mem-loads/pp: ...SNIP... sample_type: IP|TID|TIME|ADDR|CPU|PERIOD|DATA_SRC, ... Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Don Zickus Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1444068369-20978-3-git-send-email-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evsel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 58890044d835..0b1c289da36d 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -1178,7 +1178,7 @@ static void __p_sample_type(char *buf, size_t size, u64 value) bit_name(READ), bit_name(CALLCHAIN), bit_name(ID), bit_name(CPU), bit_name(PERIOD), bit_name(STREAM_ID), bit_name(RAW), bit_name(BRANCH_STACK), bit_name(REGS_USER), bit_name(STACK_USER), - bit_name(IDENTIFIER), bit_name(REGS_INTR), + bit_name(IDENTIFIER), bit_name(REGS_INTR), bit_name(DATA_SRC), { .name = NULL, } }; #undef bit_name -- cgit From 5ec4502d774699194952209ff3ebe65d2472e15a Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Mon, 5 Oct 2015 20:06:03 +0200 Subject: perf annotate: Fix sizeof_sym_hist overflow issue The annotated_source::sizeof_sym_hist could easily overflow int size, resulting in crash in __symbol__inc_addr_samples. Changing its type int size_t as was probably intended from beginning based on the initialization code in symbol__alloc_hist. Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Don Zickus Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1444068369-20978-4-git-send-email-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/annotate.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tools/perf/util/annotate.h b/tools/perf/util/annotate.h index e9996092a093..cea323d9ee7e 100644 --- a/tools/perf/util/annotate.h +++ b/tools/perf/util/annotate.h @@ -122,7 +122,7 @@ struct annotated_source { struct list_head source; struct source_line *lines; int nr_histograms; - int sizeof_sym_hist; + size_t sizeof_sym_hist; struct cyc_hist *cycles_hist; struct sym_hist histograms[0]; }; -- cgit From 45cf6c33f95448752dd3d5531388429c3a5012d0 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Mon, 5 Oct 2015 20:06:04 +0200 Subject: perf tools: Export perf_event_attr__set_max_precise_ip() It'll be used in following patch. Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Don Zickus Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1444068369-20978-5-git-send-email-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/evlist.c | 2 +- tools/perf/util/evlist.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c index e7e195d867ea..d1392194a9a9 100644 --- a/tools/perf/util/evlist.c +++ b/tools/perf/util/evlist.c @@ -205,7 +205,7 @@ void perf_evlist__set_leader(struct perf_evlist *evlist) } } -static void perf_event_attr__set_max_precise_ip(struct perf_event_attr *attr) +void perf_event_attr__set_max_precise_ip(struct perf_event_attr *attr) { attr->precise_ip = 3; diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h index 66bc9d4c0869..a459fe71b452 100644 --- a/tools/perf/util/evlist.h +++ b/tools/perf/util/evlist.h @@ -290,4 +290,6 @@ void perf_evlist__to_front(struct perf_evlist *evlist, void perf_evlist__set_tracking_event(struct perf_evlist *evlist, struct perf_evsel *tracking_evsel); + +void perf_event_attr__set_max_precise_ip(struct perf_event_attr *attr); #endif /* __PERF_EVLIST_H */ -- cgit From 7f94af7a489fada17d28cc60e8f4409ce216bd6d Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Mon, 5 Oct 2015 20:06:05 +0200 Subject: perf tools: Introduce 'P' modifier to request max precision The 'P' will cause the event to get maximum possible detected precise level. Following record: $ perf record -e cycles:P ... will detect maximum precise level for 'cycles' event and use it. Commiter note: Testing it: $ perf record -e cycles:P usleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 0.013 MB perf.data (9 samples) ] $ perf evlist cycles:P $ perf evlist -v cycles:P: size: 112, { sample_period, sample_freq }: 4000, sample_type: IP|TID|TIME|PERIOD, disabled: 1, inherit: 1, mmap: 1, comm: 1, freq: 1, enable_on_exec: 1, task: 1, precise_ip: 2, sample_id_all: 1, mmap2: 1, comm_exec: 1 $ Signed-off-by: Jiri Olsa Tested-by: Arnaldo Carvalho de Melo Cc: David Ahern Cc: Don Zickus Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1444068369-20978-6-git-send-email-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-list.txt | 1 + tools/perf/util/evsel.c | 3 +++ tools/perf/util/evsel.h | 1 + tools/perf/util/parse-events.c | 8 +++++++- tools/perf/util/parse-events.l | 2 +- 5 files changed, 13 insertions(+), 2 deletions(-) diff --git a/tools/perf/Documentation/perf-list.txt b/tools/perf/Documentation/perf-list.txt index ad60c6ea1997..79483f40e991 100644 --- a/tools/perf/Documentation/perf-list.txt +++ b/tools/perf/Documentation/perf-list.txt @@ -30,6 +30,7 @@ counted. The following modifiers exist: G - guest counting (in KVM guests) H - host counting (not in KVM guests) p - precise level + P - use maximum detected precise level S - read sample value (PERF_SAMPLE_READ) D - pin the event to the PMU diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index 0b1c289da36d..8be867ccefe9 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -882,6 +882,9 @@ void perf_evsel__config(struct perf_evsel *evsel, struct record_opts *opts) attr->clockid = opts->clockid; } + if (evsel->precise_max) + perf_event_attr__set_max_precise_ip(attr); + /* * Apply event specific term settings, * it overloads any global configuration. diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 7906666580da..02a5fed8d924 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -111,6 +111,7 @@ struct perf_evsel { bool system_wide; bool tracking; bool per_pkg; + bool precise_max; /* parse modifier helper */ int exclude_GH; int nr_members; diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 5d0cfce2599b..3ed8bf175163 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -923,6 +923,7 @@ struct event_modifier { int eG; int eI; int precise; + int precise_max; int exclude_GH; int sample_read; int pinned; @@ -938,6 +939,7 @@ static int get_event_modifier(struct event_modifier *mod, char *str, int eG = evsel ? evsel->attr.exclude_guest : 0; int eI = evsel ? evsel->attr.exclude_idle : 0; int precise = evsel ? evsel->attr.precise_ip : 0; + int precise_max = 0; int sample_read = 0; int pinned = evsel ? evsel->attr.pinned : 0; @@ -974,6 +976,8 @@ static int get_event_modifier(struct event_modifier *mod, char *str, /* use of precise requires exclude_guest */ if (!exclude_GH) eG = 1; + } else if (*str == 'P') { + precise_max = 1; } else if (*str == 'S') { sample_read = 1; } else if (*str == 'D') { @@ -1004,6 +1008,7 @@ static int get_event_modifier(struct event_modifier *mod, char *str, mod->eG = eG; mod->eI = eI; mod->precise = precise; + mod->precise_max = precise_max; mod->exclude_GH = exclude_GH; mod->sample_read = sample_read; mod->pinned = pinned; @@ -1020,7 +1025,7 @@ static int check_modifier(char *str) char *p = str; /* The sizeof includes 0 byte as well. */ - if (strlen(str) > (sizeof("ukhGHpppSDI") - 1)) + if (strlen(str) > (sizeof("ukhGHpppPSDI") - 1)) return -1; while (*p) { @@ -1059,6 +1064,7 @@ int parse_events__modifier_event(struct list_head *list, char *str, bool add) evsel->attr.exclude_idle = mod.eI; evsel->exclude_GH = mod.exclude_GH; evsel->sample_read = mod.sample_read; + evsel->precise_max = mod.precise_max; if (perf_evsel__is_group_leader(evsel)) evsel->attr.pinned = mod.pinned; diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index c29832bce496..be244573a02e 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -122,7 +122,7 @@ num_raw_hex [a-fA-F0-9]+ name [a-zA-Z_*?][a-zA-Z0-9_*?.]* name_minus [a-zA-Z_*?][a-zA-Z0-9\-_*?.]* /* If you add a modifier you need to update check_modifier() */ -modifier_event [ukhpGHSDI]+ +modifier_event [ukhpPGHSDI]+ modifier_bp [rwx]{1,3} %% -- cgit From ddd83c9717ef8204f17cc63d6dcb5053d472caee Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Mon, 5 Oct 2015 20:06:06 +0200 Subject: perf tests: Add parsing test for 'P' modifier We cant test 'P' modifier gets properly parsed, the functionality test itself is beyond this suite. Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Don Zickus Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1444068369-20978-7-git-send-email-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/tests/parse-events.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-events.c index 3a2ebe666192..0648b84a9171 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -1259,6 +1259,17 @@ test__checkevent_breakpoint_len_rw_modifier(struct perf_evlist *evlist) return test__checkevent_breakpoint_rw(evlist); } +static int test__checkevent_precise_max_modifier(struct perf_evlist *evlist) +{ + struct perf_evsel *evsel = perf_evlist__first(evlist); + + TEST_ASSERT_VAL("wrong number of entries", 2 == evlist->nr_entries); + TEST_ASSERT_VAL("wrong type", PERF_TYPE_SOFTWARE == evsel->attr.type); + TEST_ASSERT_VAL("wrong config", + PERF_COUNT_SW_TASK_CLOCK == evsel->attr.config); + return 0; +} + static int count_tracepoints(void) { struct dirent *events_ent; @@ -1562,6 +1573,11 @@ static struct evlist_test test__events[] = { .check = test__checkevent_exclude_idle_modifier_1, .id = 46, }, + { + .name = "task-clock:P,cycles", + .check = test__checkevent_precise_max_modifier, + .id = 47, + }, }; static struct evlist_test test__events_pmu[] = { -- cgit From 28e6db205b3ed3f1d86a00c69b3304190377da5f Mon Sep 17 00:00:00 2001 From: Don Zickus Date: Mon, 5 Oct 2015 20:06:07 +0200 Subject: perf tools: Add support for sorting on the iaddr Sorting on 'symbol' gives to broad a resolution as it can cover a range of IP address. Use the iaddr instead to get proper sorting on IP addresses. Need to use the 'mem_sort' feature of perf record. New sort option is: symbol_iaddr, header label is 'Code Symbol'. $ perf mem report --stdio -F +symbol_iaddr # Overhead Samples Code Symbol Local Weight # ........ ............ ........................ ............ # 54.08% 1 [k] nmi_handle 192 4.51% 1 [k] finish_task_switch 16 3.66% 1 [.] malloc 13 3.10% 1 [.] __strcoll_l 11 Signed-off-by: Don Zickus Cc: David Ahern Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1444068369-20978-8-git-send-email-jolsa@kernel.org Signed-off-by: Jiri Olsa Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/hist.h | 1 + tools/perf/util/sort.c | 37 +++++++++++++++++++++++++++++++++++++ tools/perf/util/sort.h | 1 + 3 files changed, 39 insertions(+) diff --git a/tools/perf/util/hist.h b/tools/perf/util/hist.h index 8c20a8f6b214..a48a2078d288 100644 --- a/tools/perf/util/hist.h +++ b/tools/perf/util/hist.h @@ -49,6 +49,7 @@ enum hist_column { HISTC_MEM_LVL, HISTC_MEM_SNOOP, HISTC_MEM_DCACHELINE, + HISTC_MEM_IADDR_SYMBOL, HISTC_TRANSACTION, HISTC_CYCLES, HISTC_NR_COLS, /* Last entry */ diff --git a/tools/perf/util/sort.c b/tools/perf/util/sort.c index 6b9556d298c9..ee94b728fca4 100644 --- a/tools/perf/util/sort.c +++ b/tools/perf/util/sort.c @@ -654,6 +654,35 @@ static int hist_entry__daddr_snprintf(struct hist_entry *he, char *bf, width); } +static int64_t +sort__iaddr_cmp(struct hist_entry *left, struct hist_entry *right) +{ + uint64_t l = 0, r = 0; + + if (left->mem_info) + l = left->mem_info->iaddr.addr; + if (right->mem_info) + r = right->mem_info->iaddr.addr; + + return (int64_t)(r - l); +} + +static int hist_entry__iaddr_snprintf(struct hist_entry *he, char *bf, + size_t size, unsigned int width) +{ + uint64_t addr = 0; + struct map *map = NULL; + struct symbol *sym = NULL; + + if (he->mem_info) { + addr = he->mem_info->iaddr.addr; + map = he->mem_info->iaddr.map; + sym = he->mem_info->iaddr.sym; + } + return _hist_entry__sym_snprintf(map, sym, addr, he->level, bf, size, + width); +} + static int64_t sort__dso_daddr_cmp(struct hist_entry *left, struct hist_entry *right) { @@ -1077,6 +1106,13 @@ struct sort_entry sort_mem_daddr_sym = { .se_width_idx = HISTC_MEM_DADDR_SYMBOL, }; +struct sort_entry sort_mem_iaddr_sym = { + .se_header = "Code Symbol", + .se_cmp = sort__iaddr_cmp, + .se_snprintf = hist_entry__iaddr_snprintf, + .se_width_idx = HISTC_MEM_IADDR_SYMBOL, +}; + struct sort_entry sort_mem_daddr_dso = { .se_header = "Data Object", .se_cmp = sort__dso_daddr_cmp, @@ -1299,6 +1335,7 @@ static struct sort_dimension bstack_sort_dimensions[] = { static struct sort_dimension memory_sort_dimensions[] = { DIM(SORT_MEM_DADDR_SYMBOL, "symbol_daddr", sort_mem_daddr_sym), + DIM(SORT_MEM_IADDR_SYMBOL, "symbol_iaddr", sort_mem_iaddr_sym), DIM(SORT_MEM_DADDR_DSO, "dso_daddr", sort_mem_daddr_dso), DIM(SORT_MEM_LOCKED, "locked", sort_mem_locked), DIM(SORT_MEM_TLB, "tlb", sort_mem_tlb), diff --git a/tools/perf/util/sort.h b/tools/perf/util/sort.h index c06b75746613..33b3d30e18d3 100644 --- a/tools/perf/util/sort.h +++ b/tools/perf/util/sort.h @@ -201,6 +201,7 @@ enum sort_type { SORT_MEM_LVL, SORT_MEM_SNOOP, SORT_MEM_DCACHELINE, + SORT_MEM_IADDR_SYMBOL, }; /* -- cgit From b34b3bf0798633cc248b682f5b4f6509739ce234 Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Mon, 5 Oct 2015 20:06:08 +0200 Subject: perf tools: Setup proper width for symbol_iaddr field We need to properly initialize column width for symbol_iaddr field, so all symbols could fit in the column. Signed-off-by: Jiri Olsa Cc: David Ahern Cc: Don Zickus Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1444068369-20978-9-git-send-email-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/hist.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tools/perf/util/hist.c b/tools/perf/util/hist.c index c346b331b892..4fd37d6708cb 100644 --- a/tools/perf/util/hist.c +++ b/tools/perf/util/hist.c @@ -132,6 +132,18 @@ void hists__calc_col_len(struct hists *hists, struct hist_entry *h) hists__new_col_len(hists, HISTC_MEM_DADDR_SYMBOL, symlen); } + + if (h->mem_info->iaddr.sym) { + symlen = (int)h->mem_info->iaddr.sym->namelen + 4 + + unresolved_col_width + 2; + hists__new_col_len(hists, HISTC_MEM_IADDR_SYMBOL, + symlen); + } else { + symlen = unresolved_col_width + 4 + 2; + hists__new_col_len(hists, HISTC_MEM_IADDR_SYMBOL, + symlen); + } + if (h->mem_info->daddr.map) { symlen = dso__name_len(h->mem_info->daddr.map->dso); hists__new_col_len(hists, HISTC_MEM_DADDR_DSO, @@ -143,6 +155,7 @@ void hists__calc_col_len(struct hists *hists, struct hist_entry *h) } else { symlen = unresolved_col_width + 4 + 2; hists__new_col_len(hists, HISTC_MEM_DADDR_SYMBOL, symlen); + hists__new_col_len(hists, HISTC_MEM_IADDR_SYMBOL, symlen); hists__set_unres_dso_col_len(hists, HISTC_MEM_DADDR_DSO); } -- cgit From a1853e2c6f8ed488adcd84fb162c5b3f0b674d9b Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Mon, 5 Oct 2015 20:06:09 +0200 Subject: perf tools: Handle -h and -v options Adding handling for '-h' and '-v' options to invoke help and version command respectively. Current behaviour is: $ perf -v Unknown option: -v Usage: perf [--version] [--help] [OPTIONS] COMMAND [ARGS] $ perf -h Unknown option: -h Usage: perf [--version] [--help] [OPTIONS] COMMAND [ARGS] New behaviour: $ perf -h usage: perf [--version] [--help] [OPTIONS] COMMAND [ARGS] The most commonly used perf commands are: annotate Read perf.data (created by perf record) and display annotated code archive Create archive with object files with build-ids found in perf.data file bench General framework for benchmark suites ... $ perf -v perf version 4.3.rc3.gc99e32 Updated man page. Requested-by: Peter Zijlstra Signed-off-by: Jiri Olsa Tested-by: Arnaldo Carvalho de Melo Cc: David Ahern Cc: Don Zickus Cc: Kan Liang Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1444068369-20978-10-git-send-email-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf.txt | 8 ++++++++ tools/perf/perf.c | 14 ++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/tools/perf/Documentation/perf.txt b/tools/perf/Documentation/perf.txt index 2b131776363e..864e37597252 100644 --- a/tools/perf/Documentation/perf.txt +++ b/tools/perf/Documentation/perf.txt @@ -27,6 +27,14 @@ OPTIONS Setup buildid cache directory. It has higher priority than buildid.dir config file option. +-v:: +--version:: + Display perf version. + +-h:: +--help:: + Run perf help command. + DESCRIPTION ----------- Performance counters for Linux are a new kernel-based subsystem diff --git a/tools/perf/perf.c b/tools/perf/perf.c index 1fded922bcc8..543713422d14 100644 --- a/tools/perf/perf.c +++ b/tools/perf/perf.c @@ -161,6 +161,20 @@ static int handle_options(const char ***argv, int *argc, int *envchanged) if (!strcmp(cmd, "--help") || !strcmp(cmd, "--version")) break; + /* + * Shortcut for '-h' and '-v' options to invoke help + * and version command. + */ + if (!strcmp(cmd, "-h")) { + (*argv)[0] = "--help"; + break; + } + + if (!strcmp(cmd, "-v")) { + (*argv)[0] = "--version"; + break; + } + /* * Check remaining flags. */ -- cgit From 31b6753f95320260b160935d0e9c0b29f096ab57 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Mon, 5 Oct 2015 15:40:19 +0100 Subject: perf tests: Add arch tests Tests that only make sense for some architectures currently live in the same place as the generic tests. Move out the x86-specific tests into tools/perf/arch/x86/tests and define an 'arch_tests' array, which is the list of tests that only apply to the build architecture. The main idea is to encourage developers to add arch tests to build out perf's test coverage, without dumping everything in tools/perf/tests. Signed-off-by: Matt Fleming Cc: Adrian Hunter Cc: Andi Kleen Cc: Fenghua Yu Cc: Jiri Olsa Cc: Kanaka Juvva Cc: Peter Zijlstra Cc: Vikas Shivappa Cc: Vince Weaver Link: http://lkml.kernel.org/n/tip-p4uc1c15ssbj8xj7ku5slpa6@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/Build | 2 +- tools/perf/arch/x86/include/arch-tests.h | 6 ++++++ tools/perf/arch/x86/tests/Build | 6 ++++-- tools/perf/arch/x86/tests/arch-tests.c | 10 ++++++++++ tools/perf/tests/builtin-test.c | 28 ++++++++++++++++++++-------- tools/perf/tests/tests.h | 5 +++++ 6 files changed, 46 insertions(+), 11 deletions(-) create mode 100644 tools/perf/arch/x86/include/arch-tests.h create mode 100644 tools/perf/arch/x86/tests/arch-tests.c diff --git a/tools/perf/arch/x86/Build b/tools/perf/arch/x86/Build index 41bf61da476a..db52fa22d3a1 100644 --- a/tools/perf/arch/x86/Build +++ b/tools/perf/arch/x86/Build @@ -1,2 +1,2 @@ libperf-y += util/ -libperf-$(CONFIG_DWARF_UNWIND) += tests/ +libperf-y += tests/ diff --git a/tools/perf/arch/x86/include/arch-tests.h b/tools/perf/arch/x86/include/arch-tests.h new file mode 100644 index 000000000000..4bd41d8e1ca4 --- /dev/null +++ b/tools/perf/arch/x86/include/arch-tests.h @@ -0,0 +1,6 @@ +#ifndef ARCH_TESTS_H +#define ARCH_TESTS_H + +extern struct test arch_tests[]; + +#endif diff --git a/tools/perf/arch/x86/tests/Build b/tools/perf/arch/x86/tests/Build index b30eff9bcc83..d827ef384b33 100644 --- a/tools/perf/arch/x86/tests/Build +++ b/tools/perf/arch/x86/tests/Build @@ -1,2 +1,4 @@ -libperf-y += regs_load.o -libperf-y += dwarf-unwind.o +libperf-$(CONFIG_DWARF_UNWIND) += regs_load.o +libperf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o + +libperf-y += arch-tests.o diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/tests/arch-tests.c new file mode 100644 index 000000000000..fca9eb9d39a2 --- /dev/null +++ b/tools/perf/arch/x86/tests/arch-tests.c @@ -0,0 +1,10 @@ +#include +#include "tests/tests.h" +#include "arch-tests.h" + +struct test arch_tests[] = { + { + .func = NULL, + }, + +}; diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c index d9bf51dc8cf5..2b6c1bf13456 100644 --- a/tools/perf/tests/builtin-test.c +++ b/tools/perf/tests/builtin-test.c @@ -14,10 +14,13 @@ #include "parse-options.h" #include "symbol.h" -static struct test { - const char *desc; - int (*func)(void); -} tests[] = { +struct test __weak arch_tests[] = { + { + .func = NULL, + }, +}; + +static struct test generic_tests[] = { { .desc = "vmlinux symtab matches kallsyms", .func = test__vmlinux_matches_kallsyms, @@ -195,6 +198,11 @@ static struct test { }, }; +static struct test *tests[] = { + generic_tests, + arch_tests, +}; + static bool perf_test__matches(struct test *test, int curr, int argc, const char *argv[]) { int i; @@ -249,22 +257,25 @@ static int run_test(struct test *test) return err; } -#define for_each_test(t) for (t = &tests[0]; t->func; t++) +#define for_each_test(j, t) \ + for (j = 0; j < ARRAY_SIZE(tests); j++) \ + for (t = &tests[j][0]; t->func; t++) static int __cmd_test(int argc, const char *argv[], struct intlist *skiplist) { struct test *t; + unsigned int j; int i = 0; int width = 0; - for_each_test(t) { + for_each_test(j, t) { int len = strlen(t->desc); if (width < len) width = len; } - for_each_test(t) { + for_each_test(j, t) { int curr = i++, err; if (!perf_test__matches(t, curr, argc, argv)) @@ -300,10 +311,11 @@ static int __cmd_test(int argc, const char *argv[], struct intlist *skiplist) static int perf_test__list(int argc, const char **argv) { + unsigned int j; struct test *t; int i = 0; - for_each_test(t) { + for_each_test(j, t) { if (argc > 1 && !strstr(t->desc, argv[1])) continue; diff --git a/tools/perf/tests/tests.h b/tools/perf/tests/tests.h index 0b3549672c16..b1cb1c081e3c 100644 --- a/tools/perf/tests/tests.h +++ b/tools/perf/tests/tests.h @@ -24,6 +24,11 @@ enum { TEST_SKIP = -2, }; +struct test { + const char *desc; + int (*func)(void); +}; + /* Tests */ int test__vmlinux_matches_kallsyms(void); int test__openat_syscall_event(void); -- cgit From d8b167f9d8af817073ee35cf904e2e527465dbc1 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Mon, 5 Oct 2015 15:40:20 +0100 Subject: perf tests: Move x86 tests into arch directory Move out the x86-specific tests into tools/perf/arch/x86/tests and define an 'arch_tests' array, which is the list of tests that only apply to the build architecture. We can also now begin to get rid of some of the #ifdef code that is present in the generic perf tests. Signed-off-by: Matt Fleming Cc: Adrian Hunter Cc: Andi Kleen Cc: Fenghua Yu Cc: Jiri Olsa Cc: Kanaka Juvva Cc: Peter Zijlstra Cc: Vikas Shivappa Cc: Vince Weaver Link: http://lkml.kernel.org/n/tip-9s68h4ptg06ah0lgnjz55mqn@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/include/arch-tests.h | 12 + tools/perf/arch/x86/tests/Build | 3 + tools/perf/arch/x86/tests/arch-tests.c | 20 + tools/perf/arch/x86/tests/dwarf-unwind.c | 1 + tools/perf/arch/x86/tests/gen-insn-x86-dat.awk | 75 +++ tools/perf/arch/x86/tests/gen-insn-x86-dat.sh | 43 ++ tools/perf/arch/x86/tests/insn-x86-dat-32.c | 658 +++++++++++++++++++ tools/perf/arch/x86/tests/insn-x86-dat-64.c | 768 ++++++++++++++++++++++ tools/perf/arch/x86/tests/insn-x86-dat-src.c | 877 +++++++++++++++++++++++++ tools/perf/arch/x86/tests/insn-x86.c | 185 ++++++ tools/perf/arch/x86/tests/perf-time-to-tsc.c | 164 +++++ tools/perf/arch/x86/tests/rdpmc.c | 174 +++++ tools/perf/tests/Build | 6 - tools/perf/tests/builtin-test.c | 28 - tools/perf/tests/dwarf-unwind.c | 4 + tools/perf/tests/gen-insn-x86-dat.awk | 75 --- tools/perf/tests/gen-insn-x86-dat.sh | 43 -- tools/perf/tests/insn-x86-dat-32.c | 658 ------------------- tools/perf/tests/insn-x86-dat-64.c | 768 ---------------------- tools/perf/tests/insn-x86-dat-src.c | 877 ------------------------- tools/perf/tests/insn-x86.c | 184 ------ tools/perf/tests/perf-time-to-tsc.c | 162 ----- tools/perf/tests/rdpmc.c | 177 ----- tools/perf/tests/tests.h | 5 +- 24 files changed, 2985 insertions(+), 2982 deletions(-) create mode 100644 tools/perf/arch/x86/tests/gen-insn-x86-dat.awk create mode 100755 tools/perf/arch/x86/tests/gen-insn-x86-dat.sh create mode 100644 tools/perf/arch/x86/tests/insn-x86-dat-32.c create mode 100644 tools/perf/arch/x86/tests/insn-x86-dat-64.c create mode 100644 tools/perf/arch/x86/tests/insn-x86-dat-src.c create mode 100644 tools/perf/arch/x86/tests/insn-x86.c create mode 100644 tools/perf/arch/x86/tests/perf-time-to-tsc.c create mode 100644 tools/perf/arch/x86/tests/rdpmc.c delete mode 100644 tools/perf/tests/gen-insn-x86-dat.awk delete mode 100755 tools/perf/tests/gen-insn-x86-dat.sh delete mode 100644 tools/perf/tests/insn-x86-dat-32.c delete mode 100644 tools/perf/tests/insn-x86-dat-64.c delete mode 100644 tools/perf/tests/insn-x86-dat-src.c delete mode 100644 tools/perf/tests/insn-x86.c delete mode 100644 tools/perf/tests/perf-time-to-tsc.c delete mode 100644 tools/perf/tests/rdpmc.c diff --git a/tools/perf/arch/x86/include/arch-tests.h b/tools/perf/arch/x86/include/arch-tests.h index 4bd41d8e1ca4..5927cf224325 100644 --- a/tools/perf/arch/x86/include/arch-tests.h +++ b/tools/perf/arch/x86/include/arch-tests.h @@ -1,6 +1,18 @@ #ifndef ARCH_TESTS_H #define ARCH_TESTS_H +/* Tests */ +int test__rdpmc(void); +int test__perf_time_to_tsc(void); +int test__insn_x86(void); + +#ifdef HAVE_DWARF_UNWIND_SUPPORT +struct thread; +struct perf_sample; +int test__arch_unwind_sample(struct perf_sample *sample, + struct thread *thread); +#endif + extern struct test arch_tests[]; #endif diff --git a/tools/perf/arch/x86/tests/Build b/tools/perf/arch/x86/tests/Build index d827ef384b33..8e2c5a38c3b9 100644 --- a/tools/perf/arch/x86/tests/Build +++ b/tools/perf/arch/x86/tests/Build @@ -2,3 +2,6 @@ libperf-$(CONFIG_DWARF_UNWIND) += regs_load.o libperf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o libperf-y += arch-tests.o +libperf-y += rdpmc.o +libperf-y += perf-time-to-tsc.o +libperf-$(CONFIG_AUXTRACE) += insn-x86.o diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/tests/arch-tests.c index fca9eb9d39a2..d116c217af99 100644 --- a/tools/perf/arch/x86/tests/arch-tests.c +++ b/tools/perf/arch/x86/tests/arch-tests.c @@ -3,6 +3,26 @@ #include "arch-tests.h" struct test arch_tests[] = { + { + .desc = "x86 rdpmc test", + .func = test__rdpmc, + }, + { + .desc = "Test converting perf time to TSC", + .func = test__perf_time_to_tsc, + }, +#ifdef HAVE_DWARF_UNWIND_SUPPORT + { + .desc = "Test dwarf unwind", + .func = test__dwarf_unwind, + }, +#endif +#ifdef HAVE_AUXTRACE_SUPPORT + { + .desc = "Test x86 instruction decoder - new instructions", + .func = test__insn_x86, + }, +#endif { .func = NULL, }, diff --git a/tools/perf/arch/x86/tests/dwarf-unwind.c b/tools/perf/arch/x86/tests/dwarf-unwind.c index d8bbf7ad1681..7f209ce827bf 100644 --- a/tools/perf/arch/x86/tests/dwarf-unwind.c +++ b/tools/perf/arch/x86/tests/dwarf-unwind.c @@ -5,6 +5,7 @@ #include "event.h" #include "debug.h" #include "tests/tests.h" +#include "arch-tests.h" #define STACK_SIZE 8192 diff --git a/tools/perf/arch/x86/tests/gen-insn-x86-dat.awk b/tools/perf/arch/x86/tests/gen-insn-x86-dat.awk new file mode 100644 index 000000000000..a21454835cd4 --- /dev/null +++ b/tools/perf/arch/x86/tests/gen-insn-x86-dat.awk @@ -0,0 +1,75 @@ +#!/bin/awk -f +# gen-insn-x86-dat.awk: script to convert data for the insn-x86 test +# Copyright (c) 2015, Intel Corporation. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +BEGIN { + print "/*" + print " * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk" + print " * from insn-x86-dat-src.c for inclusion by insn-x86.c" + print " * Do not change this code." + print "*/\n" + op = "" + branch = "" + rel = 0 + going = 0 +} + +/ Start here / { + going = 1 +} + +/ Stop here / { + going = 0 +} + +/^\s*[0-9a-fA-F]+\:/ { + if (going) { + colon_pos = index($0, ":") + useful_line = substr($0, colon_pos + 1) + first_pos = match(useful_line, "[0-9a-fA-F]") + useful_line = substr(useful_line, first_pos) + gsub("\t", "\\t", useful_line) + printf "{{" + len = 0 + for (i = 2; i <= NF; i++) { + if (match($i, "^[0-9a-fA-F][0-9a-fA-F]$")) { + printf "0x%s, ", $i + len += 1 + } else { + break + } + } + printf "}, %d, %s, \"%s\", \"%s\",", len, rel, op, branch + printf "\n\"%s\",},\n", useful_line + op = "" + branch = "" + rel = 0 + } +} + +/ Expecting: / { + expecting_str = " Expecting: " + expecting_len = length(expecting_str) + expecting_pos = index($0, expecting_str) + useful_line = substr($0, expecting_pos + expecting_len) + for (i = 1; i <= NF; i++) { + if ($i == "Expecting:") { + i++ + op = $i + i++ + branch = $i + i++ + rel = $i + break + } + } +} diff --git a/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh b/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh new file mode 100755 index 000000000000..2d4ef94cff98 --- /dev/null +++ b/tools/perf/arch/x86/tests/gen-insn-x86-dat.sh @@ -0,0 +1,43 @@ +#!/bin/sh +# gen-insn-x86-dat: generate data for the insn-x86 test +# Copyright (c) 2015, Intel Corporation. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms and conditions of the GNU General Public License, +# version 2, as published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +# more details. + +set -e + +if [ "$(uname -m)" != "x86_64" ]; then + echo "ERROR: This script only works on x86_64" + exit 1 +fi + +cd $(dirname $0) + +trap 'echo "Might need a more recent version of binutils"' EXIT + +echo "Compiling insn-x86-dat-src.c to 64-bit object" + +gcc -g -c insn-x86-dat-src.c + +objdump -dSw insn-x86-dat-src.o | awk -f gen-insn-x86-dat.awk > insn-x86-dat-64.c + +rm -f insn-x86-dat-src.o + +echo "Compiling insn-x86-dat-src.c to 32-bit object" + +gcc -g -c -m32 insn-x86-dat-src.c + +objdump -dSw insn-x86-dat-src.o | awk -f gen-insn-x86-dat.awk > insn-x86-dat-32.c + +rm -f insn-x86-dat-src.o + +trap - EXIT + +echo "Done (use git diff to see the changes)" diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-32.c b/tools/perf/arch/x86/tests/insn-x86-dat-32.c new file mode 100644 index 000000000000..3b491cfe204e --- /dev/null +++ b/tools/perf/arch/x86/tests/insn-x86-dat-32.c @@ -0,0 +1,658 @@ +/* + * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk + * from insn-x86-dat-src.c for inclusion by insn-x86.c + * Do not change this code. +*/ + +{{0x0f, 0x31, }, 2, 0, "", "", +"0f 31 \trdtsc ",}, +{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", +"f3 0f 1b 00 \tbndmk (%eax),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f3 0f 1b 05 78 56 34 12 \tbndmk 0x12345678,%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", +"f3 0f 1b 18 \tbndmk (%eax),%bnd3",}, +{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", +"f3 0f 1b 04 01 \tbndmk (%ecx,%eax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%eax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", +"f3 0f 1b 04 08 \tbndmk (%eax,%ecx,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", +"f3 0f 1b 04 c8 \tbndmk (%eax,%ecx,8),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", +"f3 0f 1b 40 12 \tbndmk 0x12(%eax),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", +"f3 0f 1b 45 12 \tbndmk 0x12(%ebp),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", +"f3 0f 1b 44 01 12 \tbndmk 0x12(%ecx,%eax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", +"f3 0f 1b 44 05 12 \tbndmk 0x12(%ebp,%eax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", +"f3 0f 1b 44 08 12 \tbndmk 0x12(%eax,%ecx,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", +"f3 0f 1b 44 c8 12 \tbndmk 0x12(%eax,%ecx,8),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%eax),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%ebp),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%ecx,%eax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 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@@ -0,0 +1,768 @@ +/* + * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk + * from insn-x86-dat-src.c for inclusion by insn-x86.c + * Do not change this code. +*/ + +{{0x0f, 0x31, }, 2, 0, "", "", +"0f 31 \trdtsc ",}, +{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", +"f3 0f 1b 00 \tbndmk (%rax),%bnd0",}, +{{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", +"f3 41 0f 1b 00 \tbndmk (%r8),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1b 04 25 78 56 34 12 \tbndmk 0x12345678,%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", +"f3 0f 1b 18 \tbndmk (%rax),%bnd3",}, +{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", +"f3 0f 1b 04 01 \tbndmk (%rcx,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", +"f3 0f 1b 04 08 \tbndmk (%rax,%rcx,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", +"f3 0f 1b 04 c8 \tbndmk (%rax,%rcx,8),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", +"f3 0f 1b 40 12 \tbndmk 0x12(%rax),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", +"f3 0f 1b 45 12 \tbndmk 0x12(%rbp),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", +"f3 0f 1b 44 01 12 \tbndmk 0x12(%rcx,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", +"f3 0f 1b 44 05 12 \tbndmk 0x12(%rbp,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", +"f3 0f 1b 44 08 12 \tbndmk 0x12(%rax,%rcx,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", +"f3 0f 1b 44 c8 12 \tbndmk 0x12(%rax,%rcx,8),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%rax),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%rbp),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%rcx,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1b 84 05 78 56 34 12 \tbndmk 0x12345678(%rbp,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1b 84 08 78 56 34 12 \tbndmk 0x12345678(%rax,%rcx,1),%bnd0",}, +{{0xf3, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1b 84 c8 78 56 34 12 \tbndmk 0x12345678(%rax,%rcx,8),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", +"f3 0f 1a 00 \tbndcl (%rax),%bnd0",}, +{{0xf3, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "", +"f3 41 0f 1a 00 \tbndcl (%r8),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1a 04 25 78 56 34 12 \tbndcl 0x12345678,%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", +"f3 0f 1a 18 \tbndcl (%rax),%bnd3",}, +{{0xf3, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", +"f3 0f 1a 04 01 \tbndcl (%rcx,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1a 04 05 78 56 34 12 \tbndcl 0x12345678(,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "", +"f3 0f 1a 04 08 \tbndcl (%rax,%rcx,1),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "", +"f3 0f 1a 04 c8 \tbndcl (%rax,%rcx,8),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "", +"f3 0f 1a 40 12 \tbndcl 0x12(%rax),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "", +"f3 0f 1a 45 12 \tbndcl 0x12(%rbp),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "", +"f3 0f 1a 44 01 12 \tbndcl 0x12(%rcx,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "", +"f3 0f 1a 44 05 12 \tbndcl 0x12(%rbp,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "", +"f3 0f 1a 44 08 12 \tbndcl 0x12(%rax,%rcx,1),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "", +"f3 0f 1a 44 c8 12 \tbndcl 0x12(%rax,%rcx,8),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f3 0f 1a 80 78 56 34 12 \tbndcl 0x12345678(%rax),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f3 0f 1a 85 78 56 34 12 \tbndcl 0x12345678(%rbp),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1a 84 01 78 56 34 12 \tbndcl 0x12345678(%rcx,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1a 84 05 78 56 34 12 \tbndcl 0x12345678(%rbp,%rax,1),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1a 84 08 78 56 34 12 \tbndcl 0x12345678(%rax,%rcx,1),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f3 0f 1a 84 c8 78 56 34 12 \tbndcl 0x12345678(%rax,%rcx,8),%bnd0",}, +{{0xf3, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "", +"f3 0f 1a c0 \tbndcl %rax,%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", +"f2 0f 1a 00 \tbndcu (%rax),%bnd0",}, +{{0xf2, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "", +"f2 41 0f 1a 00 \tbndcu (%r8),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1a 04 25 78 56 34 12 \tbndcu 0x12345678,%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", +"f2 0f 1a 18 \tbndcu (%rax),%bnd3",}, +{{0xf2, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", +"f2 0f 1a 04 01 \tbndcu (%rcx,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1a 04 05 78 56 34 12 \tbndcu 0x12345678(,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "", +"f2 0f 1a 04 08 \tbndcu (%rax,%rcx,1),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "", +"f2 0f 1a 04 c8 \tbndcu (%rax,%rcx,8),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "", +"f2 0f 1a 40 12 \tbndcu 0x12(%rax),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "", +"f2 0f 1a 45 12 \tbndcu 0x12(%rbp),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "", +"f2 0f 1a 44 01 12 \tbndcu 0x12(%rcx,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "", +"f2 0f 1a 44 05 12 \tbndcu 0x12(%rbp,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "", +"f2 0f 1a 44 08 12 \tbndcu 0x12(%rax,%rcx,1),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "", +"f2 0f 1a 44 c8 12 \tbndcu 0x12(%rax,%rcx,8),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f2 0f 1a 80 78 56 34 12 \tbndcu 0x12345678(%rax),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f2 0f 1a 85 78 56 34 12 \tbndcu 0x12345678(%rbp),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1a 84 01 78 56 34 12 \tbndcu 0x12345678(%rcx,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1a 84 05 78 56 34 12 \tbndcu 0x12345678(%rbp,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1a 84 08 78 56 34 12 \tbndcu 0x12345678(%rax,%rcx,1),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1a 84 c8 78 56 34 12 \tbndcu 0x12345678(%rax,%rcx,8),%bnd0",}, +{{0xf2, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "", +"f2 0f 1a c0 \tbndcu %rax,%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", +"f2 0f 1b 00 \tbndcn (%rax),%bnd0",}, +{{0xf2, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", +"f2 41 0f 1b 00 \tbndcn (%r8),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1b 04 25 78 56 34 12 \tbndcn 0x12345678,%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", +"f2 0f 1b 18 \tbndcn (%rax),%bnd3",}, +{{0xf2, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", +"f2 0f 1b 04 01 \tbndcn (%rcx,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1b 04 05 78 56 34 12 \tbndcn 0x12345678(,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", +"f2 0f 1b 04 08 \tbndcn (%rax,%rcx,1),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", +"f2 0f 1b 04 c8 \tbndcn (%rax,%rcx,8),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", +"f2 0f 1b 40 12 \tbndcn 0x12(%rax),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", +"f2 0f 1b 45 12 \tbndcn 0x12(%rbp),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", +"f2 0f 1b 44 01 12 \tbndcn 0x12(%rcx,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", +"f2 0f 1b 44 05 12 \tbndcn 0x12(%rbp,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", +"f2 0f 1b 44 08 12 \tbndcn 0x12(%rax,%rcx,1),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", +"f2 0f 1b 44 c8 12 \tbndcn 0x12(%rax,%rcx,8),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f2 0f 1b 80 78 56 34 12 \tbndcn 0x12345678(%rax),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"f2 0f 1b 85 78 56 34 12 \tbndcn 0x12345678(%rbp),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1b 84 01 78 56 34 12 \tbndcn 0x12345678(%rcx,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1b 84 05 78 56 34 12 \tbndcn 0x12345678(%rbp,%rax,1),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1b 84 08 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,1),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"f2 0f 1b 84 c8 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,8),%bnd0",}, +{{0xf2, 0x0f, 0x1b, 0xc0, }, 4, 0, "", "", +"f2 0f 1b c0 \tbndcn %rax,%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", +"66 0f 1a 00 \tbndmov (%rax),%bnd0",}, +{{0x66, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "", +"66 41 0f 1a 00 \tbndmov (%r8),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 1a 04 25 78 56 34 12 \tbndmov 0x12345678,%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", +"66 0f 1a 18 \tbndmov (%rax),%bnd3",}, +{{0x66, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", +"66 0f 1a 04 01 \tbndmov (%rcx,%rax,1),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 1a 04 05 78 56 34 12 \tbndmov 0x12345678(,%rax,1),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "", +"66 0f 1a 04 08 \tbndmov (%rax,%rcx,1),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "", +"66 0f 1a 04 c8 \tbndmov (%rax,%rcx,8),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "", +"66 0f 1a 40 12 \tbndmov 0x12(%rax),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "", +"66 0f 1a 45 12 \tbndmov 0x12(%rbp),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "", +"66 0f 1a 44 01 12 \tbndmov 0x12(%rcx,%rax,1),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "", +"66 0f 1a 44 05 12 \tbndmov 0x12(%rbp,%rax,1),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "", +"66 0f 1a 44 08 12 \tbndmov 0x12(%rax,%rcx,1),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "", +"66 0f 1a 44 c8 12 \tbndmov 0x12(%rax,%rcx,8),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"66 0f 1a 80 78 56 34 12 \tbndmov 0x12345678(%rax),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"66 0f 1a 85 78 56 34 12 \tbndmov 0x12345678(%rbp),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 1a 84 01 78 56 34 12 \tbndmov 0x12345678(%rcx,%rax,1),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 1a 84 05 78 56 34 12 \tbndmov 0x12345678(%rbp,%rax,1),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 1a 84 08 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,1),%bnd0",}, +{{0x66, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 1a 84 c8 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,8),%bnd0",}, +{{0x66, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", +"66 0f 1b 00 \tbndmov %bnd0,(%rax)",}, +{{0x66, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", +"66 41 0f 1b 00 \tbndmov %bnd0,(%r8)",}, +{{0x66, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 1b 04 25 78 56 34 12 \tbndmov %bnd0,0x12345678",}, +{{0x66, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", +"66 0f 1b 18 \tbndmov %bnd3,(%rax)",}, +{{0x66, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", +"66 0f 1b 04 01 \tbndmov %bnd0,(%rcx,%rax,1)",}, +{{0x66, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 1b 04 05 78 56 34 12 \tbndmov %bnd0,0x12345678(,%rax,1)",}, +{{0x66, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", +"66 0f 1b 04 08 \tbndmov %bnd0,(%rax,%rcx,1)",}, +{{0x66, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", +"66 0f 1b 04 c8 \tbndmov %bnd0,(%rax,%rcx,8)",}, +{{0x66, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", +"66 0f 1b 40 12 \tbndmov %bnd0,0x12(%rax)",}, +{{0x66, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", +"66 0f 1b 45 12 \tbndmov %bnd0,0x12(%rbp)",}, +{{0x66, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", +"66 0f 1b 44 01 12 \tbndmov %bnd0,0x12(%rcx,%rax,1)",}, +{{0x66, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", +"66 0f 1b 44 05 12 \tbndmov %bnd0,0x12(%rbp,%rax,1)",}, +{{0x66, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", +"66 0f 1b 44 08 12 \tbndmov %bnd0,0x12(%rax,%rcx,1)",}, +{{0x66, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", +"66 0f 1b 44 c8 12 \tbndmov %bnd0,0x12(%rax,%rcx,8)",}, +{{0x66, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"66 0f 1b 80 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax)",}, +{{0x66, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"66 0f 1b 85 78 56 34 12 \tbndmov %bnd0,0x12345678(%rbp)",}, +{{0x66, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f 1b 84 01 78 56 34 12 \tbndmov %bnd0,0x12345678(%rcx,%rax,1)",}, +{{0x66, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 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+"45 0f 38 cd c7 \tsha256msg2 %xmm15,%xmm8",}, +{{0x0f, 0x38, 0xcd, 0x00, }, 4, 0, "", "", +"0f 38 cd 00 \tsha256msg2 (%rax),%xmm0",}, +{{0x41, 0x0f, 0x38, 0xcd, 0x00, }, 5, 0, "", "", +"41 0f 38 cd 00 \tsha256msg2 (%r8),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"0f 38 cd 04 25 78 56 34 12 \tsha256msg2 0x12345678,%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x18, }, 4, 0, "", "", +"0f 38 cd 18 \tsha256msg2 (%rax),%xmm3",}, +{{0x0f, 0x38, 0xcd, 0x04, 0x01, }, 5, 0, "", "", +"0f 38 cd 04 01 \tsha256msg2 (%rcx,%rax,1),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"0f 38 cd 04 05 78 56 34 12 \tsha256msg2 0x12345678(,%rax,1),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x04, 0x08, }, 5, 0, "", "", +"0f 38 cd 04 08 \tsha256msg2 (%rax,%rcx,1),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x04, 0xc8, }, 5, 0, "", "", +"0f 38 cd 04 c8 \tsha256msg2 (%rax,%rcx,8),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x40, 0x12, }, 5, 0, "", "", +"0f 38 cd 40 12 \tsha256msg2 0x12(%rax),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x45, 0x12, }, 5, 0, "", "", +"0f 38 cd 45 12 \tsha256msg2 0x12(%rbp),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x44, 0x01, 0x12, }, 6, 0, "", "", +"0f 38 cd 44 01 12 \tsha256msg2 0x12(%rcx,%rax,1),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x44, 0x05, 0x12, }, 6, 0, "", "", +"0f 38 cd 44 05 12 \tsha256msg2 0x12(%rbp,%rax,1),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x44, 0x08, 0x12, }, 6, 0, "", "", +"0f 38 cd 44 08 12 \tsha256msg2 0x12(%rax,%rcx,1),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x44, 0xc8, 0x12, }, 6, 0, "", "", +"0f 38 cd 44 c8 12 \tsha256msg2 0x12(%rax,%rcx,8),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f 38 cd 80 78 56 34 12 \tsha256msg2 0x12345678(%rax),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f 38 cd 85 78 56 34 12 \tsha256msg2 0x12345678(%rbp),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"0f 38 cd 84 01 78 56 34 12 \tsha256msg2 0x12345678(%rcx,%rax,1),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"0f 38 cd 84 05 78 56 34 12 \tsha256msg2 0x12345678(%rbp,%rax,1),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"0f 38 cd 84 08 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,1),%xmm0",}, +{{0x0f, 0x38, 0xcd, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"0f 38 cd 84 c8 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,8),%xmm0",}, +{{0x44, 0x0f, 0x38, 0xcd, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"44 0f 38 cd bc c8 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,8),%xmm15",}, +{{0x66, 0x0f, 0xae, 0x38, }, 4, 0, "", "", +"66 0f ae 38 \tclflushopt (%rax)",}, +{{0x66, 0x41, 0x0f, 0xae, 0x38, }, 5, 0, "", "", +"66 41 0f ae 38 \tclflushopt (%r8)",}, +{{0x66, 0x0f, 0xae, 0x3c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f ae 3c 25 78 56 34 12 \tclflushopt 0x12345678",}, +{{0x66, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%rax,%rcx,8)",}, +{{0x66, 0x41, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"66 41 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%r8,%rcx,8)",}, +{{0x0f, 0xae, 0x38, }, 3, 0, "", "", +"0f ae 38 \tclflush (%rax)",}, +{{0x41, 0x0f, 0xae, 0x38, }, 4, 0, "", "", +"41 0f ae 38 \tclflush (%r8)",}, +{{0x0f, 0xae, 0xf8, }, 3, 0, "", "", +"0f ae f8 \tsfence ",}, +{{0x66, 0x0f, 0xae, 0x30, }, 4, 0, "", "", +"66 0f ae 30 \tclwb (%rax)",}, +{{0x66, 0x41, 0x0f, 0xae, 0x30, }, 5, 0, "", "", +"66 41 0f ae 30 \tclwb (%r8)",}, +{{0x66, 0x0f, 0xae, 0x34, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f ae 34 25 78 56 34 12 \tclwb 0x12345678",}, +{{0x66, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"66 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%rax,%rcx,8)",}, +{{0x66, 0x41, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", +"66 41 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%r8,%rcx,8)",}, +{{0x0f, 0xae, 0x30, }, 3, 0, "", "", +"0f ae 30 \txsaveopt (%rax)",}, +{{0x41, 0x0f, 0xae, 0x30, }, 4, 0, "", "", +"41 0f ae 30 \txsaveopt (%r8)",}, +{{0x0f, 0xae, 0xf0, }, 3, 0, "", "", +"0f ae f0 \tmfence ",}, +{{0x0f, 0xc7, 0x20, }, 3, 0, "", "", +"0f c7 20 \txsavec (%rax)",}, +{{0x41, 0x0f, 0xc7, 0x20, }, 4, 0, "", "", +"41 0f c7 20 \txsavec (%r8)",}, +{{0x0f, 0xc7, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f c7 24 25 78 56 34 12 \txsavec 0x12345678",}, +{{0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%rax,%rcx,8)",}, +{{0x41, 0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"41 0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%r8,%rcx,8)",}, +{{0x0f, 0xc7, 0x28, }, 3, 0, "", "", +"0f c7 28 \txsaves (%rax)",}, +{{0x41, 0x0f, 0xc7, 0x28, }, 4, 0, "", "", +"41 0f c7 28 \txsaves (%r8)",}, +{{0x0f, 0xc7, 0x2c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f c7 2c 25 78 56 34 12 \txsaves 0x12345678",}, +{{0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%rax,%rcx,8)",}, +{{0x41, 0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"41 0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%r8,%rcx,8)",}, +{{0x0f, 0xc7, 0x18, }, 3, 0, "", "", +"0f c7 18 \txrstors (%rax)",}, +{{0x41, 0x0f, 0xc7, 0x18, }, 4, 0, "", "", +"41 0f c7 18 \txrstors (%r8)",}, +{{0x0f, 0xc7, 0x1c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f c7 1c 25 78 56 34 12 \txrstors 0x12345678",}, +{{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", +"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%rax,%rcx,8)",}, +{{0x41, 0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", +"41 0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%r8,%rcx,8)",}, +{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "", +"66 0f ae f8 \tpcommit ",}, diff --git a/tools/perf/arch/x86/tests/insn-x86-dat-src.c b/tools/perf/arch/x86/tests/insn-x86-dat-src.c new file mode 100644 index 000000000000..41b1b1c62660 --- /dev/null +++ b/tools/perf/arch/x86/tests/insn-x86-dat-src.c @@ -0,0 +1,877 @@ +/* + * This file contains instructions for testing by the test titled: + * + * "Test x86 instruction decoder - new instructions" + * + * Note that the 'Expecting' comment lines are consumed by the + * gen-insn-x86-dat.awk script and have the format: + * + * Expecting: + * + * If this file is changed, remember to run the gen-insn-x86-dat.sh + * script and commit the result. + * + * Refer to insn-x86.c for more details. + */ + +int main(void) +{ + /* Following line is a marker for the awk script - do not change */ + asm volatile("rdtsc"); /* Start here */ + +#ifdef __x86_64__ + + /* bndmk m64, bnd */ + + asm volatile("bndmk (%rax), %bnd0"); + asm volatile("bndmk (%r8), %bnd0"); + asm volatile("bndmk (0x12345678), %bnd0"); + asm volatile("bndmk (%rax), %bnd3"); + asm volatile("bndmk (%rcx,%rax,1), %bnd0"); + asm volatile("bndmk 0x12345678(,%rax,1), %bnd0"); + asm volatile("bndmk (%rax,%rcx,1), %bnd0"); + asm volatile("bndmk (%rax,%rcx,8), %bnd0"); + asm volatile("bndmk 0x12(%rax), %bnd0"); + asm volatile("bndmk 0x12(%rbp), %bnd0"); + asm volatile("bndmk 0x12(%rcx,%rax,1), %bnd0"); + asm volatile("bndmk 0x12(%rbp,%rax,1), %bnd0"); + asm volatile("bndmk 0x12(%rax,%rcx,1), %bnd0"); + asm volatile("bndmk 0x12(%rax,%rcx,8), %bnd0"); + asm volatile("bndmk 0x12345678(%rax), %bnd0"); + asm volatile("bndmk 0x12345678(%rbp), %bnd0"); + asm volatile("bndmk 0x12345678(%rcx,%rax,1), %bnd0"); + asm volatile("bndmk 0x12345678(%rbp,%rax,1), %bnd0"); + asm volatile("bndmk 0x12345678(%rax,%rcx,1), %bnd0"); + asm volatile("bndmk 0x12345678(%rax,%rcx,8), %bnd0"); + + /* bndcl r/m64, bnd */ + + asm volatile("bndcl (%rax), %bnd0"); + asm volatile("bndcl (%r8), %bnd0"); + asm volatile("bndcl (0x12345678), %bnd0"); + asm volatile("bndcl (%rax), %bnd3"); + asm volatile("bndcl (%rcx,%rax,1), %bnd0"); + asm volatile("bndcl 0x12345678(,%rax,1), %bnd0"); + asm volatile("bndcl (%rax,%rcx,1), %bnd0"); + asm volatile("bndcl (%rax,%rcx,8), %bnd0"); + asm volatile("bndcl 0x12(%rax), %bnd0"); + asm volatile("bndcl 0x12(%rbp), %bnd0"); + asm volatile("bndcl 0x12(%rcx,%rax,1), %bnd0"); + asm volatile("bndcl 0x12(%rbp,%rax,1), %bnd0"); + asm volatile("bndcl 0x12(%rax,%rcx,1), %bnd0"); + asm volatile("bndcl 0x12(%rax,%rcx,8), %bnd0"); + asm volatile("bndcl 0x12345678(%rax), %bnd0"); + asm volatile("bndcl 0x12345678(%rbp), %bnd0"); + asm volatile("bndcl 0x12345678(%rcx,%rax,1), %bnd0"); + asm volatile("bndcl 0x12345678(%rbp,%rax,1), %bnd0"); + asm volatile("bndcl 0x12345678(%rax,%rcx,1), %bnd0"); + asm volatile("bndcl 0x12345678(%rax,%rcx,8), %bnd0"); + asm volatile("bndcl %rax, %bnd0"); + + /* bndcu r/m64, bnd */ + + asm volatile("bndcu (%rax), %bnd0"); + asm volatile("bndcu (%r8), %bnd0"); + asm volatile("bndcu (0x12345678), %bnd0"); + asm volatile("bndcu (%rax), %bnd3"); + asm volatile("bndcu (%rcx,%rax,1), %bnd0"); + asm volatile("bndcu 0x12345678(,%rax,1), %bnd0"); + asm volatile("bndcu (%rax,%rcx,1), %bnd0"); + asm volatile("bndcu (%rax,%rcx,8), %bnd0"); + asm volatile("bndcu 0x12(%rax), %bnd0"); + asm volatile("bndcu 0x12(%rbp), %bnd0"); + asm volatile("bndcu 0x12(%rcx,%rax,1), %bnd0"); + asm volatile("bndcu 0x12(%rbp,%rax,1), %bnd0"); + asm volatile("bndcu 0x12(%rax,%rcx,1), %bnd0"); + asm volatile("bndcu 0x12(%rax,%rcx,8), %bnd0"); + asm volatile("bndcu 0x12345678(%rax), %bnd0"); + asm volatile("bndcu 0x12345678(%rbp), %bnd0"); + asm volatile("bndcu 0x12345678(%rcx,%rax,1), %bnd0"); + asm volatile("bndcu 0x12345678(%rbp,%rax,1), %bnd0"); + asm volatile("bndcu 0x12345678(%rax,%rcx,1), %bnd0"); + asm volatile("bndcu 0x12345678(%rax,%rcx,8), %bnd0"); + asm volatile("bndcu %rax, %bnd0"); + + /* bndcn r/m64, bnd */ + + asm volatile("bndcn (%rax), %bnd0"); + asm volatile("bndcn (%r8), %bnd0"); + asm volatile("bndcn (0x12345678), %bnd0"); + asm volatile("bndcn (%rax), %bnd3"); + asm volatile("bndcn (%rcx,%rax,1), %bnd0"); + asm volatile("bndcn 0x12345678(,%rax,1), %bnd0"); + asm volatile("bndcn (%rax,%rcx,1), %bnd0"); + asm volatile("bndcn (%rax,%rcx,8), %bnd0"); + asm volatile("bndcn 0x12(%rax), %bnd0"); + asm volatile("bndcn 0x12(%rbp), %bnd0"); + asm volatile("bndcn 0x12(%rcx,%rax,1), %bnd0"); + asm volatile("bndcn 0x12(%rbp,%rax,1), %bnd0"); + asm volatile("bndcn 0x12(%rax,%rcx,1), %bnd0"); + asm volatile("bndcn 0x12(%rax,%rcx,8), %bnd0"); + asm volatile("bndcn 0x12345678(%rax), %bnd0"); + asm volatile("bndcn 0x12345678(%rbp), %bnd0"); + asm volatile("bndcn 0x12345678(%rcx,%rax,1), %bnd0"); + asm volatile("bndcn 0x12345678(%rbp,%rax,1), %bnd0"); + asm volatile("bndcn 0x12345678(%rax,%rcx,1), %bnd0"); + asm volatile("bndcn 0x12345678(%rax,%rcx,8), %bnd0"); + asm volatile("bndcn %rax, %bnd0"); + + /* bndmov m128, bnd */ + + asm volatile("bndmov (%rax), %bnd0"); + asm volatile("bndmov (%r8), %bnd0"); + asm volatile("bndmov (0x12345678), %bnd0"); + asm volatile("bndmov (%rax), %bnd3"); + asm volatile("bndmov (%rcx,%rax,1), %bnd0"); + asm volatile("bndmov 0x12345678(,%rax,1), %bnd0"); + asm volatile("bndmov (%rax,%rcx,1), %bnd0"); + asm volatile("bndmov (%rax,%rcx,8), %bnd0"); + asm volatile("bndmov 0x12(%rax), %bnd0"); + asm volatile("bndmov 0x12(%rbp), %bnd0"); + asm volatile("bndmov 0x12(%rcx,%rax,1), %bnd0"); + asm volatile("bndmov 0x12(%rbp,%rax,1), %bnd0"); + asm volatile("bndmov 0x12(%rax,%rcx,1), %bnd0"); + asm volatile("bndmov 0x12(%rax,%rcx,8), %bnd0"); + asm volatile("bndmov 0x12345678(%rax), %bnd0"); + asm volatile("bndmov 0x12345678(%rbp), %bnd0"); + asm volatile("bndmov 0x12345678(%rcx,%rax,1), %bnd0"); + asm volatile("bndmov 0x12345678(%rbp,%rax,1), %bnd0"); + asm volatile("bndmov 0x12345678(%rax,%rcx,1), %bnd0"); + asm volatile("bndmov 0x12345678(%rax,%rcx,8), %bnd0"); + + /* bndmov bnd, m128 */ + + asm volatile("bndmov %bnd0, (%rax)"); + asm volatile("bndmov %bnd0, (%r8)"); + asm volatile("bndmov %bnd0, (0x12345678)"); + asm volatile("bndmov %bnd3, (%rax)"); + asm volatile("bndmov %bnd0, (%rcx,%rax,1)"); + asm volatile("bndmov %bnd0, 0x12345678(,%rax,1)"); + asm volatile("bndmov %bnd0, (%rax,%rcx,1)"); + asm volatile("bndmov %bnd0, (%rax,%rcx,8)"); + asm volatile("bndmov %bnd0, 0x12(%rax)"); + asm volatile("bndmov %bnd0, 0x12(%rbp)"); + asm volatile("bndmov %bnd0, 0x12(%rcx,%rax,1)"); + asm volatile("bndmov %bnd0, 0x12(%rbp,%rax,1)"); + asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,1)"); + asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,8)"); + asm volatile("bndmov %bnd0, 0x12345678(%rax)"); + asm volatile("bndmov %bnd0, 0x12345678(%rbp)"); + asm volatile("bndmov %bnd0, 0x12345678(%rcx,%rax,1)"); + asm volatile("bndmov %bnd0, 0x12345678(%rbp,%rax,1)"); + asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,1)"); + asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,8)"); + + /* bndmov bnd2, bnd1 */ + + asm volatile("bndmov %bnd0, %bnd1"); + asm volatile("bndmov %bnd1, %bnd0"); + + /* bndldx mib, bnd */ + + asm volatile("bndldx (%rax), %bnd0"); + asm volatile("bndldx (%r8), %bnd0"); + asm volatile("bndldx (0x12345678), %bnd0"); + asm volatile("bndldx (%rax), %bnd3"); + asm volatile("bndldx (%rcx,%rax,1), %bnd0"); + asm volatile("bndldx 0x12345678(,%rax,1), %bnd0"); + asm volatile("bndldx (%rax,%rcx,1), %bnd0"); + asm volatile("bndldx 0x12(%rax), %bnd0"); + asm volatile("bndldx 0x12(%rbp), %bnd0"); + asm volatile("bndldx 0x12(%rcx,%rax,1), %bnd0"); + asm volatile("bndldx 0x12(%rbp,%rax,1), %bnd0"); + asm volatile("bndldx 0x12(%rax,%rcx,1), %bnd0"); + asm volatile("bndldx 0x12345678(%rax), %bnd0"); + asm volatile("bndldx 0x12345678(%rbp), %bnd0"); + asm volatile("bndldx 0x12345678(%rcx,%rax,1), %bnd0"); + asm volatile("bndldx 0x12345678(%rbp,%rax,1), %bnd0"); + asm volatile("bndldx 0x12345678(%rax,%rcx,1), %bnd0"); + + /* bndstx bnd, mib */ + + asm volatile("bndstx %bnd0, (%rax)"); + asm volatile("bndstx %bnd0, (%r8)"); + asm volatile("bndstx %bnd0, (0x12345678)"); + asm volatile("bndstx %bnd3, (%rax)"); + asm volatile("bndstx %bnd0, (%rcx,%rax,1)"); + asm volatile("bndstx %bnd0, 0x12345678(,%rax,1)"); + asm volatile("bndstx %bnd0, (%rax,%rcx,1)"); + asm volatile("bndstx %bnd0, 0x12(%rax)"); + asm volatile("bndstx %bnd0, 0x12(%rbp)"); + asm volatile("bndstx %bnd0, 0x12(%rcx,%rax,1)"); + asm volatile("bndstx %bnd0, 0x12(%rbp,%rax,1)"); + asm volatile("bndstx %bnd0, 0x12(%rax,%rcx,1)"); + asm volatile("bndstx %bnd0, 0x12345678(%rax)"); + asm volatile("bndstx %bnd0, 0x12345678(%rbp)"); + asm volatile("bndstx %bnd0, 0x12345678(%rcx,%rax,1)"); + asm volatile("bndstx %bnd0, 0x12345678(%rbp,%rax,1)"); + asm volatile("bndstx %bnd0, 0x12345678(%rax,%rcx,1)"); + + /* bnd prefix on call, ret, jmp and all jcc */ + + asm volatile("bnd call label1"); /* Expecting: call unconditional 0 */ + asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */ + asm volatile("bnd ret"); /* Expecting: ret indirect 0 */ + asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */ + asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */ + asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */ + asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0 */ + + /* sha1rnds4 imm8, xmm2/m128, xmm1 */ + + asm volatile("sha1rnds4 $0x0, %xmm1, %xmm0"); + asm volatile("sha1rnds4 $0x91, %xmm7, %xmm2"); + asm volatile("sha1rnds4 $0x91, %xmm8, %xmm0"); + asm volatile("sha1rnds4 $0x91, %xmm7, %xmm8"); + asm volatile("sha1rnds4 $0x91, %xmm15, %xmm8"); + asm volatile("sha1rnds4 $0x91, (%rax), %xmm0"); + asm volatile("sha1rnds4 $0x91, (%r8), %xmm0"); + asm volatile("sha1rnds4 $0x91, (0x12345678), %xmm0"); + asm volatile("sha1rnds4 $0x91, (%rax), %xmm3"); + asm volatile("sha1rnds4 $0x91, (%rcx,%rax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(,%rax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, (%rax,%rcx,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, (%rax,%rcx,8), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%rax), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%rbp), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%rcx,%rax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%rbp,%rax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%rax,%rcx,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%rax,%rcx,8), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%rax), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%rbp), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%rcx,%rax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%rbp,%rax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,8), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,8), %xmm15"); + + /* sha1nexte xmm2/m128, xmm1 */ + + asm volatile("sha1nexte %xmm1, %xmm0"); + asm volatile("sha1nexte %xmm7, %xmm2"); + asm volatile("sha1nexte %xmm8, %xmm0"); + asm volatile("sha1nexte %xmm7, %xmm8"); + asm volatile("sha1nexte %xmm15, %xmm8"); + asm volatile("sha1nexte (%rax), %xmm0"); + asm volatile("sha1nexte (%r8), %xmm0"); + asm volatile("sha1nexte (0x12345678), %xmm0"); + asm volatile("sha1nexte (%rax), %xmm3"); + asm volatile("sha1nexte (%rcx,%rax,1), %xmm0"); + asm volatile("sha1nexte 0x12345678(,%rax,1), %xmm0"); + asm volatile("sha1nexte (%rax,%rcx,1), %xmm0"); + asm volatile("sha1nexte (%rax,%rcx,8), %xmm0"); + asm volatile("sha1nexte 0x12(%rax), %xmm0"); + asm volatile("sha1nexte 0x12(%rbp), %xmm0"); + asm volatile("sha1nexte 0x12(%rcx,%rax,1), %xmm0"); + asm volatile("sha1nexte 0x12(%rbp,%rax,1), %xmm0"); + asm volatile("sha1nexte 0x12(%rax,%rcx,1), %xmm0"); + asm volatile("sha1nexte 0x12(%rax,%rcx,8), %xmm0"); + asm volatile("sha1nexte 0x12345678(%rax), %xmm0"); + asm volatile("sha1nexte 0x12345678(%rbp), %xmm0"); + asm volatile("sha1nexte 0x12345678(%rcx,%rax,1), %xmm0"); + asm volatile("sha1nexte 0x12345678(%rbp,%rax,1), %xmm0"); + asm volatile("sha1nexte 0x12345678(%rax,%rcx,1), %xmm0"); + asm volatile("sha1nexte 0x12345678(%rax,%rcx,8), %xmm0"); + asm volatile("sha1nexte 0x12345678(%rax,%rcx,8), %xmm15"); + + /* sha1msg1 xmm2/m128, xmm1 */ + + asm volatile("sha1msg1 %xmm1, %xmm0"); + asm volatile("sha1msg1 %xmm7, %xmm2"); + asm volatile("sha1msg1 %xmm8, %xmm0"); + asm volatile("sha1msg1 %xmm7, %xmm8"); + asm volatile("sha1msg1 %xmm15, %xmm8"); + asm volatile("sha1msg1 (%rax), %xmm0"); + asm volatile("sha1msg1 (%r8), %xmm0"); + asm volatile("sha1msg1 (0x12345678), %xmm0"); + asm volatile("sha1msg1 (%rax), %xmm3"); + asm volatile("sha1msg1 (%rcx,%rax,1), %xmm0"); + asm volatile("sha1msg1 0x12345678(,%rax,1), %xmm0"); + asm volatile("sha1msg1 (%rax,%rcx,1), %xmm0"); + asm volatile("sha1msg1 (%rax,%rcx,8), %xmm0"); + asm volatile("sha1msg1 0x12(%rax), %xmm0"); + asm volatile("sha1msg1 0x12(%rbp), %xmm0"); + asm volatile("sha1msg1 0x12(%rcx,%rax,1), %xmm0"); + asm volatile("sha1msg1 0x12(%rbp,%rax,1), %xmm0"); + asm volatile("sha1msg1 0x12(%rax,%rcx,1), %xmm0"); + asm volatile("sha1msg1 0x12(%rax,%rcx,8), %xmm0"); + asm volatile("sha1msg1 0x12345678(%rax), %xmm0"); + asm volatile("sha1msg1 0x12345678(%rbp), %xmm0"); + asm volatile("sha1msg1 0x12345678(%rcx,%rax,1), %xmm0"); + asm volatile("sha1msg1 0x12345678(%rbp,%rax,1), %xmm0"); + asm volatile("sha1msg1 0x12345678(%rax,%rcx,1), %xmm0"); + asm volatile("sha1msg1 0x12345678(%rax,%rcx,8), %xmm0"); + asm volatile("sha1msg1 0x12345678(%rax,%rcx,8), %xmm15"); + + /* sha1msg2 xmm2/m128, xmm1 */ + + asm volatile("sha1msg2 %xmm1, %xmm0"); + asm volatile("sha1msg2 %xmm7, %xmm2"); + asm volatile("sha1msg2 %xmm8, %xmm0"); + asm volatile("sha1msg2 %xmm7, %xmm8"); + asm volatile("sha1msg2 %xmm15, %xmm8"); + asm volatile("sha1msg2 (%rax), %xmm0"); + asm volatile("sha1msg2 (%r8), %xmm0"); + asm volatile("sha1msg2 (0x12345678), %xmm0"); + asm volatile("sha1msg2 (%rax), %xmm3"); + asm volatile("sha1msg2 (%rcx,%rax,1), %xmm0"); + asm volatile("sha1msg2 0x12345678(,%rax,1), %xmm0"); + asm volatile("sha1msg2 (%rax,%rcx,1), %xmm0"); + asm volatile("sha1msg2 (%rax,%rcx,8), %xmm0"); + asm volatile("sha1msg2 0x12(%rax), %xmm0"); + asm volatile("sha1msg2 0x12(%rbp), %xmm0"); + asm volatile("sha1msg2 0x12(%rcx,%rax,1), %xmm0"); + asm volatile("sha1msg2 0x12(%rbp,%rax,1), %xmm0"); + asm volatile("sha1msg2 0x12(%rax,%rcx,1), %xmm0"); + asm volatile("sha1msg2 0x12(%rax,%rcx,8), %xmm0"); + asm volatile("sha1msg2 0x12345678(%rax), %xmm0"); + asm volatile("sha1msg2 0x12345678(%rbp), %xmm0"); + asm volatile("sha1msg2 0x12345678(%rcx,%rax,1), %xmm0"); + asm volatile("sha1msg2 0x12345678(%rbp,%rax,1), %xmm0"); + asm volatile("sha1msg2 0x12345678(%rax,%rcx,1), %xmm0"); + asm volatile("sha1msg2 0x12345678(%rax,%rcx,8), %xmm0"); + asm volatile("sha1msg2 0x12345678(%rax,%rcx,8), %xmm15"); + + /* sha256rnds2 , xmm2/m128, xmm1 */ + /* Note sha256rnds2 has an implicit operand 'xmm0' */ + + asm volatile("sha256rnds2 %xmm4, %xmm1"); + asm volatile("sha256rnds2 %xmm7, %xmm2"); + asm volatile("sha256rnds2 %xmm8, %xmm1"); + asm volatile("sha256rnds2 %xmm7, %xmm8"); + asm volatile("sha256rnds2 %xmm15, %xmm8"); + asm volatile("sha256rnds2 (%rax), %xmm1"); + asm volatile("sha256rnds2 (%r8), %xmm1"); + asm volatile("sha256rnds2 (0x12345678), %xmm1"); + asm volatile("sha256rnds2 (%rax), %xmm3"); + asm volatile("sha256rnds2 (%rcx,%rax,1), %xmm1"); + asm volatile("sha256rnds2 0x12345678(,%rax,1), %xmm1"); + asm volatile("sha256rnds2 (%rax,%rcx,1), %xmm1"); + asm volatile("sha256rnds2 (%rax,%rcx,8), %xmm1"); + asm volatile("sha256rnds2 0x12(%rax), %xmm1"); + asm volatile("sha256rnds2 0x12(%rbp), %xmm1"); + asm volatile("sha256rnds2 0x12(%rcx,%rax,1), %xmm1"); + asm volatile("sha256rnds2 0x12(%rbp,%rax,1), %xmm1"); + asm volatile("sha256rnds2 0x12(%rax,%rcx,1), %xmm1"); + asm volatile("sha256rnds2 0x12(%rax,%rcx,8), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%rax), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%rbp), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%rcx,%rax,1), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%rbp,%rax,1), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%rax,%rcx,1), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%rax,%rcx,8), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%rax,%rcx,8), %xmm15"); + + /* sha256msg1 xmm2/m128, xmm1 */ + + asm volatile("sha256msg1 %xmm1, %xmm0"); + asm volatile("sha256msg1 %xmm7, %xmm2"); + asm volatile("sha256msg1 %xmm8, %xmm0"); + asm volatile("sha256msg1 %xmm7, %xmm8"); + asm volatile("sha256msg1 %xmm15, %xmm8"); + asm volatile("sha256msg1 (%rax), %xmm0"); + asm volatile("sha256msg1 (%r8), %xmm0"); + asm volatile("sha256msg1 (0x12345678), %xmm0"); + asm volatile("sha256msg1 (%rax), %xmm3"); + asm volatile("sha256msg1 (%rcx,%rax,1), %xmm0"); + asm volatile("sha256msg1 0x12345678(,%rax,1), %xmm0"); + asm volatile("sha256msg1 (%rax,%rcx,1), %xmm0"); + asm volatile("sha256msg1 (%rax,%rcx,8), %xmm0"); + asm volatile("sha256msg1 0x12(%rax), %xmm0"); + asm volatile("sha256msg1 0x12(%rbp), %xmm0"); + asm volatile("sha256msg1 0x12(%rcx,%rax,1), %xmm0"); + asm volatile("sha256msg1 0x12(%rbp,%rax,1), %xmm0"); + asm volatile("sha256msg1 0x12(%rax,%rcx,1), %xmm0"); + asm volatile("sha256msg1 0x12(%rax,%rcx,8), %xmm0"); + asm volatile("sha256msg1 0x12345678(%rax), %xmm0"); + asm volatile("sha256msg1 0x12345678(%rbp), %xmm0"); + asm volatile("sha256msg1 0x12345678(%rcx,%rax,1), %xmm0"); + asm volatile("sha256msg1 0x12345678(%rbp,%rax,1), %xmm0"); + asm volatile("sha256msg1 0x12345678(%rax,%rcx,1), %xmm0"); + asm volatile("sha256msg1 0x12345678(%rax,%rcx,8), %xmm0"); + asm volatile("sha256msg1 0x12345678(%rax,%rcx,8), %xmm15"); + + /* sha256msg2 xmm2/m128, xmm1 */ + + asm volatile("sha256msg2 %xmm1, %xmm0"); + asm volatile("sha256msg2 %xmm7, %xmm2"); + asm volatile("sha256msg2 %xmm8, %xmm0"); + asm volatile("sha256msg2 %xmm7, %xmm8"); + asm volatile("sha256msg2 %xmm15, %xmm8"); + asm volatile("sha256msg2 (%rax), %xmm0"); + asm volatile("sha256msg2 (%r8), %xmm0"); + asm volatile("sha256msg2 (0x12345678), %xmm0"); + asm volatile("sha256msg2 (%rax), %xmm3"); + asm volatile("sha256msg2 (%rcx,%rax,1), %xmm0"); + asm volatile("sha256msg2 0x12345678(,%rax,1), %xmm0"); + asm volatile("sha256msg2 (%rax,%rcx,1), %xmm0"); + asm volatile("sha256msg2 (%rax,%rcx,8), %xmm0"); + asm volatile("sha256msg2 0x12(%rax), %xmm0"); + asm volatile("sha256msg2 0x12(%rbp), %xmm0"); + asm volatile("sha256msg2 0x12(%rcx,%rax,1), %xmm0"); + asm volatile("sha256msg2 0x12(%rbp,%rax,1), %xmm0"); + asm volatile("sha256msg2 0x12(%rax,%rcx,1), %xmm0"); + asm volatile("sha256msg2 0x12(%rax,%rcx,8), %xmm0"); + asm volatile("sha256msg2 0x12345678(%rax), %xmm0"); + asm volatile("sha256msg2 0x12345678(%rbp), %xmm0"); + asm volatile("sha256msg2 0x12345678(%rcx,%rax,1), %xmm0"); + asm volatile("sha256msg2 0x12345678(%rbp,%rax,1), %xmm0"); + asm volatile("sha256msg2 0x12345678(%rax,%rcx,1), %xmm0"); + asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm0"); + asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm15"); + + /* clflushopt m8 */ + + asm volatile("clflushopt (%rax)"); + asm volatile("clflushopt (%r8)"); + asm volatile("clflushopt (0x12345678)"); + asm volatile("clflushopt 0x12345678(%rax,%rcx,8)"); + asm volatile("clflushopt 0x12345678(%r8,%rcx,8)"); + /* Also check instructions in the same group encoding as clflushopt */ + asm volatile("clflush (%rax)"); + asm volatile("clflush (%r8)"); + asm volatile("sfence"); + + /* clwb m8 */ + + asm volatile("clwb (%rax)"); + asm volatile("clwb (%r8)"); + asm volatile("clwb (0x12345678)"); + asm volatile("clwb 0x12345678(%rax,%rcx,8)"); + asm volatile("clwb 0x12345678(%r8,%rcx,8)"); + /* Also check instructions in the same group encoding as clwb */ + asm volatile("xsaveopt (%rax)"); + asm volatile("xsaveopt (%r8)"); + asm volatile("mfence"); + + /* xsavec mem */ + + asm volatile("xsavec (%rax)"); + asm volatile("xsavec (%r8)"); + asm volatile("xsavec (0x12345678)"); + asm volatile("xsavec 0x12345678(%rax,%rcx,8)"); + asm volatile("xsavec 0x12345678(%r8,%rcx,8)"); + + /* xsaves mem */ + + asm volatile("xsaves (%rax)"); + asm volatile("xsaves (%r8)"); + asm volatile("xsaves (0x12345678)"); + asm volatile("xsaves 0x12345678(%rax,%rcx,8)"); + asm volatile("xsaves 0x12345678(%r8,%rcx,8)"); + + /* xrstors mem */ + + asm volatile("xrstors (%rax)"); + asm volatile("xrstors (%r8)"); + asm volatile("xrstors (0x12345678)"); + asm volatile("xrstors 0x12345678(%rax,%rcx,8)"); + asm volatile("xrstors 0x12345678(%r8,%rcx,8)"); + +#else /* #ifdef __x86_64__ */ + + /* bndmk m32, bnd */ + + asm volatile("bndmk (%eax), %bnd0"); + asm volatile("bndmk (0x12345678), %bnd0"); + asm volatile("bndmk (%eax), %bnd3"); + asm volatile("bndmk (%ecx,%eax,1), %bnd0"); + asm volatile("bndmk 0x12345678(,%eax,1), %bnd0"); + asm volatile("bndmk (%eax,%ecx,1), %bnd0"); + asm volatile("bndmk (%eax,%ecx,8), %bnd0"); + asm volatile("bndmk 0x12(%eax), %bnd0"); + asm volatile("bndmk 0x12(%ebp), %bnd0"); + asm volatile("bndmk 0x12(%ecx,%eax,1), %bnd0"); + asm volatile("bndmk 0x12(%ebp,%eax,1), %bnd0"); + asm volatile("bndmk 0x12(%eax,%ecx,1), %bnd0"); + asm volatile("bndmk 0x12(%eax,%ecx,8), %bnd0"); + asm volatile("bndmk 0x12345678(%eax), %bnd0"); + asm volatile("bndmk 0x12345678(%ebp), %bnd0"); + asm volatile("bndmk 0x12345678(%ecx,%eax,1), %bnd0"); + asm volatile("bndmk 0x12345678(%ebp,%eax,1), %bnd0"); + asm volatile("bndmk 0x12345678(%eax,%ecx,1), %bnd0"); + asm volatile("bndmk 0x12345678(%eax,%ecx,8), %bnd0"); + + /* bndcl r/m32, bnd */ + + asm volatile("bndcl (%eax), %bnd0"); + asm volatile("bndcl (0x12345678), %bnd0"); + asm volatile("bndcl (%eax), %bnd3"); + asm volatile("bndcl (%ecx,%eax,1), %bnd0"); + asm volatile("bndcl 0x12345678(,%eax,1), %bnd0"); + asm volatile("bndcl (%eax,%ecx,1), %bnd0"); + asm volatile("bndcl (%eax,%ecx,8), %bnd0"); + asm volatile("bndcl 0x12(%eax), %bnd0"); + asm volatile("bndcl 0x12(%ebp), %bnd0"); + asm volatile("bndcl 0x12(%ecx,%eax,1), %bnd0"); + asm volatile("bndcl 0x12(%ebp,%eax,1), %bnd0"); + asm volatile("bndcl 0x12(%eax,%ecx,1), %bnd0"); + asm volatile("bndcl 0x12(%eax,%ecx,8), %bnd0"); + asm volatile("bndcl 0x12345678(%eax), %bnd0"); + asm volatile("bndcl 0x12345678(%ebp), %bnd0"); + asm volatile("bndcl 0x12345678(%ecx,%eax,1), %bnd0"); + asm volatile("bndcl 0x12345678(%ebp,%eax,1), %bnd0"); + asm volatile("bndcl 0x12345678(%eax,%ecx,1), %bnd0"); + asm volatile("bndcl 0x12345678(%eax,%ecx,8), %bnd0"); + asm volatile("bndcl %eax, %bnd0"); + + /* bndcu r/m32, bnd */ + + asm volatile("bndcu (%eax), %bnd0"); + asm volatile("bndcu (0x12345678), %bnd0"); + asm volatile("bndcu (%eax), %bnd3"); + asm volatile("bndcu (%ecx,%eax,1), %bnd0"); + asm volatile("bndcu 0x12345678(,%eax,1), %bnd0"); + asm volatile("bndcu (%eax,%ecx,1), %bnd0"); + asm volatile("bndcu (%eax,%ecx,8), %bnd0"); + asm volatile("bndcu 0x12(%eax), %bnd0"); + asm volatile("bndcu 0x12(%ebp), %bnd0"); + asm volatile("bndcu 0x12(%ecx,%eax,1), %bnd0"); + asm volatile("bndcu 0x12(%ebp,%eax,1), %bnd0"); + asm volatile("bndcu 0x12(%eax,%ecx,1), %bnd0"); + asm volatile("bndcu 0x12(%eax,%ecx,8), %bnd0"); + asm volatile("bndcu 0x12345678(%eax), %bnd0"); + asm volatile("bndcu 0x12345678(%ebp), %bnd0"); + asm volatile("bndcu 0x12345678(%ecx,%eax,1), %bnd0"); + asm volatile("bndcu 0x12345678(%ebp,%eax,1), %bnd0"); + asm volatile("bndcu 0x12345678(%eax,%ecx,1), %bnd0"); + asm volatile("bndcu 0x12345678(%eax,%ecx,8), %bnd0"); + asm volatile("bndcu %eax, %bnd0"); + + /* bndcn r/m32, bnd */ + + asm volatile("bndcn (%eax), %bnd0"); + asm volatile("bndcn (0x12345678), %bnd0"); + asm volatile("bndcn (%eax), %bnd3"); + asm volatile("bndcn (%ecx,%eax,1), %bnd0"); + asm volatile("bndcn 0x12345678(,%eax,1), %bnd0"); + asm volatile("bndcn (%eax,%ecx,1), %bnd0"); + asm volatile("bndcn (%eax,%ecx,8), %bnd0"); + asm volatile("bndcn 0x12(%eax), %bnd0"); + asm volatile("bndcn 0x12(%ebp), %bnd0"); + asm volatile("bndcn 0x12(%ecx,%eax,1), %bnd0"); + asm volatile("bndcn 0x12(%ebp,%eax,1), %bnd0"); + asm volatile("bndcn 0x12(%eax,%ecx,1), %bnd0"); + asm volatile("bndcn 0x12(%eax,%ecx,8), %bnd0"); + asm volatile("bndcn 0x12345678(%eax), %bnd0"); + asm volatile("bndcn 0x12345678(%ebp), %bnd0"); + asm volatile("bndcn 0x12345678(%ecx,%eax,1), %bnd0"); + asm volatile("bndcn 0x12345678(%ebp,%eax,1), %bnd0"); + asm volatile("bndcn 0x12345678(%eax,%ecx,1), %bnd0"); + asm volatile("bndcn 0x12345678(%eax,%ecx,8), %bnd0"); + asm volatile("bndcn %eax, %bnd0"); + + /* bndmov m64, bnd */ + + asm volatile("bndmov (%eax), %bnd0"); + asm volatile("bndmov (0x12345678), %bnd0"); + asm volatile("bndmov (%eax), %bnd3"); + asm volatile("bndmov (%ecx,%eax,1), %bnd0"); + asm volatile("bndmov 0x12345678(,%eax,1), %bnd0"); + asm volatile("bndmov (%eax,%ecx,1), %bnd0"); + asm volatile("bndmov (%eax,%ecx,8), %bnd0"); + asm volatile("bndmov 0x12(%eax), %bnd0"); + asm volatile("bndmov 0x12(%ebp), %bnd0"); + asm volatile("bndmov 0x12(%ecx,%eax,1), %bnd0"); + asm volatile("bndmov 0x12(%ebp,%eax,1), %bnd0"); + asm volatile("bndmov 0x12(%eax,%ecx,1), %bnd0"); + asm volatile("bndmov 0x12(%eax,%ecx,8), %bnd0"); + asm volatile("bndmov 0x12345678(%eax), %bnd0"); + asm volatile("bndmov 0x12345678(%ebp), %bnd0"); + asm volatile("bndmov 0x12345678(%ecx,%eax,1), %bnd0"); + asm volatile("bndmov 0x12345678(%ebp,%eax,1), %bnd0"); + asm volatile("bndmov 0x12345678(%eax,%ecx,1), %bnd0"); + asm volatile("bndmov 0x12345678(%eax,%ecx,8), %bnd0"); + + /* bndmov bnd, m64 */ + + asm volatile("bndmov %bnd0, (%eax)"); + asm volatile("bndmov %bnd0, (0x12345678)"); + asm volatile("bndmov %bnd3, (%eax)"); + asm volatile("bndmov %bnd0, (%ecx,%eax,1)"); + asm volatile("bndmov %bnd0, 0x12345678(,%eax,1)"); + asm volatile("bndmov %bnd0, (%eax,%ecx,1)"); + asm volatile("bndmov %bnd0, (%eax,%ecx,8)"); + asm volatile("bndmov %bnd0, 0x12(%eax)"); + asm volatile("bndmov %bnd0, 0x12(%ebp)"); + asm volatile("bndmov %bnd0, 0x12(%ecx,%eax,1)"); + asm volatile("bndmov %bnd0, 0x12(%ebp,%eax,1)"); + asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,1)"); + asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,8)"); + asm volatile("bndmov %bnd0, 0x12345678(%eax)"); + asm volatile("bndmov %bnd0, 0x12345678(%ebp)"); + asm volatile("bndmov %bnd0, 0x12345678(%ecx,%eax,1)"); + asm volatile("bndmov %bnd0, 0x12345678(%ebp,%eax,1)"); + asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,1)"); + asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,8)"); + + /* bndmov bnd2, bnd1 */ + + asm volatile("bndmov %bnd0, %bnd1"); + asm volatile("bndmov %bnd1, %bnd0"); + + /* bndldx mib, bnd */ + + asm volatile("bndldx (%eax), %bnd0"); + asm volatile("bndldx (0x12345678), %bnd0"); + asm volatile("bndldx (%eax), %bnd3"); + asm volatile("bndldx (%ecx,%eax,1), %bnd0"); + asm volatile("bndldx 0x12345678(,%eax,1), %bnd0"); + asm volatile("bndldx (%eax,%ecx,1), %bnd0"); + asm volatile("bndldx 0x12(%eax), %bnd0"); + asm volatile("bndldx 0x12(%ebp), %bnd0"); + asm volatile("bndldx 0x12(%ecx,%eax,1), %bnd0"); + asm volatile("bndldx 0x12(%ebp,%eax,1), %bnd0"); + asm volatile("bndldx 0x12(%eax,%ecx,1), %bnd0"); + asm volatile("bndldx 0x12345678(%eax), %bnd0"); + asm volatile("bndldx 0x12345678(%ebp), %bnd0"); + asm volatile("bndldx 0x12345678(%ecx,%eax,1), %bnd0"); + asm volatile("bndldx 0x12345678(%ebp,%eax,1), %bnd0"); + asm volatile("bndldx 0x12345678(%eax,%ecx,1), %bnd0"); + + /* bndstx bnd, mib */ + + asm volatile("bndstx %bnd0, (%eax)"); + asm volatile("bndstx %bnd0, (0x12345678)"); + asm volatile("bndstx %bnd3, (%eax)"); + asm volatile("bndstx %bnd0, (%ecx,%eax,1)"); + asm volatile("bndstx %bnd0, 0x12345678(,%eax,1)"); + asm volatile("bndstx %bnd0, (%eax,%ecx,1)"); + asm volatile("bndstx %bnd0, 0x12(%eax)"); + asm volatile("bndstx %bnd0, 0x12(%ebp)"); + asm volatile("bndstx %bnd0, 0x12(%ecx,%eax,1)"); + asm volatile("bndstx %bnd0, 0x12(%ebp,%eax,1)"); + asm volatile("bndstx %bnd0, 0x12(%eax,%ecx,1)"); + asm volatile("bndstx %bnd0, 0x12345678(%eax)"); + asm volatile("bndstx %bnd0, 0x12345678(%ebp)"); + asm volatile("bndstx %bnd0, 0x12345678(%ecx,%eax,1)"); + asm volatile("bndstx %bnd0, 0x12345678(%ebp,%eax,1)"); + asm volatile("bndstx %bnd0, 0x12345678(%eax,%ecx,1)"); + + /* bnd prefix on call, ret, jmp and all jcc */ + + asm volatile("bnd call label1"); /* Expecting: call unconditional 0xfffffffc */ + asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */ + asm volatile("bnd ret"); /* Expecting: ret indirect 0 */ + asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */ + asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */ + asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */ + asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0xfffffffc */ + + /* sha1rnds4 imm8, xmm2/m128, xmm1 */ + + asm volatile("sha1rnds4 $0x0, %xmm1, %xmm0"); + asm volatile("sha1rnds4 $0x91, %xmm7, %xmm2"); + asm volatile("sha1rnds4 $0x91, (%eax), %xmm0"); + asm volatile("sha1rnds4 $0x91, (0x12345678), %xmm0"); + asm volatile("sha1rnds4 $0x91, (%eax), %xmm3"); + asm volatile("sha1rnds4 $0x91, (%ecx,%eax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(,%eax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, (%eax,%ecx,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, (%eax,%ecx,8), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%eax), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%ebp), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%ecx,%eax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%ebp,%eax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%eax,%ecx,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12(%eax,%ecx,8), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%eax), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%ebp), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%ecx,%eax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%ebp,%eax,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%eax,%ecx,1), %xmm0"); + asm volatile("sha1rnds4 $0x91, 0x12345678(%eax,%ecx,8), %xmm0"); + + /* sha1nexte xmm2/m128, xmm1 */ + + asm volatile("sha1nexte %xmm1, %xmm0"); + asm volatile("sha1nexte %xmm7, %xmm2"); + asm volatile("sha1nexte (%eax), %xmm0"); + asm volatile("sha1nexte (0x12345678), %xmm0"); + asm volatile("sha1nexte (%eax), %xmm3"); + asm volatile("sha1nexte (%ecx,%eax,1), %xmm0"); + asm volatile("sha1nexte 0x12345678(,%eax,1), %xmm0"); + asm volatile("sha1nexte (%eax,%ecx,1), %xmm0"); + asm volatile("sha1nexte (%eax,%ecx,8), %xmm0"); + asm volatile("sha1nexte 0x12(%eax), %xmm0"); + asm volatile("sha1nexte 0x12(%ebp), %xmm0"); + asm volatile("sha1nexte 0x12(%ecx,%eax,1), %xmm0"); + asm volatile("sha1nexte 0x12(%ebp,%eax,1), %xmm0"); + asm volatile("sha1nexte 0x12(%eax,%ecx,1), %xmm0"); + asm volatile("sha1nexte 0x12(%eax,%ecx,8), %xmm0"); + asm volatile("sha1nexte 0x12345678(%eax), %xmm0"); + asm volatile("sha1nexte 0x12345678(%ebp), %xmm0"); + asm volatile("sha1nexte 0x12345678(%ecx,%eax,1), %xmm0"); + asm volatile("sha1nexte 0x12345678(%ebp,%eax,1), %xmm0"); + asm volatile("sha1nexte 0x12345678(%eax,%ecx,1), %xmm0"); + asm volatile("sha1nexte 0x12345678(%eax,%ecx,8), %xmm0"); + + /* sha1msg1 xmm2/m128, xmm1 */ + + asm volatile("sha1msg1 %xmm1, %xmm0"); + asm volatile("sha1msg1 %xmm7, %xmm2"); + asm volatile("sha1msg1 (%eax), %xmm0"); + asm volatile("sha1msg1 (0x12345678), %xmm0"); + asm volatile("sha1msg1 (%eax), %xmm3"); + asm volatile("sha1msg1 (%ecx,%eax,1), %xmm0"); + asm volatile("sha1msg1 0x12345678(,%eax,1), %xmm0"); + asm volatile("sha1msg1 (%eax,%ecx,1), %xmm0"); + asm volatile("sha1msg1 (%eax,%ecx,8), %xmm0"); + asm volatile("sha1msg1 0x12(%eax), %xmm0"); + asm volatile("sha1msg1 0x12(%ebp), %xmm0"); + asm volatile("sha1msg1 0x12(%ecx,%eax,1), %xmm0"); + asm volatile("sha1msg1 0x12(%ebp,%eax,1), %xmm0"); + asm volatile("sha1msg1 0x12(%eax,%ecx,1), %xmm0"); + asm volatile("sha1msg1 0x12(%eax,%ecx,8), %xmm0"); + asm volatile("sha1msg1 0x12345678(%eax), %xmm0"); + asm volatile("sha1msg1 0x12345678(%ebp), %xmm0"); + asm volatile("sha1msg1 0x12345678(%ecx,%eax,1), %xmm0"); + asm volatile("sha1msg1 0x12345678(%ebp,%eax,1), %xmm0"); + asm volatile("sha1msg1 0x12345678(%eax,%ecx,1), %xmm0"); + asm volatile("sha1msg1 0x12345678(%eax,%ecx,8), %xmm0"); + + /* sha1msg2 xmm2/m128, xmm1 */ + + asm volatile("sha1msg2 %xmm1, %xmm0"); + asm volatile("sha1msg2 %xmm7, %xmm2"); + asm volatile("sha1msg2 (%eax), %xmm0"); + asm volatile("sha1msg2 (0x12345678), %xmm0"); + asm volatile("sha1msg2 (%eax), %xmm3"); + asm volatile("sha1msg2 (%ecx,%eax,1), %xmm0"); + asm volatile("sha1msg2 0x12345678(,%eax,1), %xmm0"); + asm volatile("sha1msg2 (%eax,%ecx,1), %xmm0"); + asm volatile("sha1msg2 (%eax,%ecx,8), %xmm0"); + asm volatile("sha1msg2 0x12(%eax), %xmm0"); + asm volatile("sha1msg2 0x12(%ebp), %xmm0"); + asm volatile("sha1msg2 0x12(%ecx,%eax,1), %xmm0"); + asm volatile("sha1msg2 0x12(%ebp,%eax,1), %xmm0"); + asm volatile("sha1msg2 0x12(%eax,%ecx,1), %xmm0"); + asm volatile("sha1msg2 0x12(%eax,%ecx,8), %xmm0"); + asm volatile("sha1msg2 0x12345678(%eax), %xmm0"); + asm volatile("sha1msg2 0x12345678(%ebp), %xmm0"); + asm volatile("sha1msg2 0x12345678(%ecx,%eax,1), %xmm0"); + asm volatile("sha1msg2 0x12345678(%ebp,%eax,1), %xmm0"); + asm volatile("sha1msg2 0x12345678(%eax,%ecx,1), %xmm0"); + asm volatile("sha1msg2 0x12345678(%eax,%ecx,8), %xmm0"); + + /* sha256rnds2 , xmm2/m128, xmm1 */ + /* Note sha256rnds2 has an implicit operand 'xmm0' */ + + asm volatile("sha256rnds2 %xmm4, %xmm1"); + asm volatile("sha256rnds2 %xmm7, %xmm2"); + asm volatile("sha256rnds2 (%eax), %xmm1"); + asm volatile("sha256rnds2 (0x12345678), %xmm1"); + asm volatile("sha256rnds2 (%eax), %xmm3"); + asm volatile("sha256rnds2 (%ecx,%eax,1), %xmm1"); + asm volatile("sha256rnds2 0x12345678(,%eax,1), %xmm1"); + asm volatile("sha256rnds2 (%eax,%ecx,1), %xmm1"); + asm volatile("sha256rnds2 (%eax,%ecx,8), %xmm1"); + asm volatile("sha256rnds2 0x12(%eax), %xmm1"); + asm volatile("sha256rnds2 0x12(%ebp), %xmm1"); + asm volatile("sha256rnds2 0x12(%ecx,%eax,1), %xmm1"); + asm volatile("sha256rnds2 0x12(%ebp,%eax,1), %xmm1"); + asm volatile("sha256rnds2 0x12(%eax,%ecx,1), %xmm1"); + asm volatile("sha256rnds2 0x12(%eax,%ecx,8), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%eax), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%ebp), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%ecx,%eax,1), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%ebp,%eax,1), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%eax,%ecx,1), %xmm1"); + asm volatile("sha256rnds2 0x12345678(%eax,%ecx,8), %xmm1"); + + /* sha256msg1 xmm2/m128, xmm1 */ + + asm volatile("sha256msg1 %xmm1, %xmm0"); + asm volatile("sha256msg1 %xmm7, %xmm2"); + asm volatile("sha256msg1 (%eax), %xmm0"); + asm volatile("sha256msg1 (0x12345678), %xmm0"); + asm volatile("sha256msg1 (%eax), %xmm3"); + asm volatile("sha256msg1 (%ecx,%eax,1), %xmm0"); + asm volatile("sha256msg1 0x12345678(,%eax,1), %xmm0"); + asm volatile("sha256msg1 (%eax,%ecx,1), %xmm0"); + asm volatile("sha256msg1 (%eax,%ecx,8), %xmm0"); + asm volatile("sha256msg1 0x12(%eax), %xmm0"); + asm volatile("sha256msg1 0x12(%ebp), %xmm0"); + asm volatile("sha256msg1 0x12(%ecx,%eax,1), %xmm0"); + asm volatile("sha256msg1 0x12(%ebp,%eax,1), %xmm0"); + asm volatile("sha256msg1 0x12(%eax,%ecx,1), %xmm0"); + asm volatile("sha256msg1 0x12(%eax,%ecx,8), %xmm0"); + asm volatile("sha256msg1 0x12345678(%eax), %xmm0"); + asm volatile("sha256msg1 0x12345678(%ebp), %xmm0"); + asm volatile("sha256msg1 0x12345678(%ecx,%eax,1), %xmm0"); + asm volatile("sha256msg1 0x12345678(%ebp,%eax,1), %xmm0"); + asm volatile("sha256msg1 0x12345678(%eax,%ecx,1), %xmm0"); + asm volatile("sha256msg1 0x12345678(%eax,%ecx,8), %xmm0"); + + /* sha256msg2 xmm2/m128, xmm1 */ + + asm volatile("sha256msg2 %xmm1, %xmm0"); + asm volatile("sha256msg2 %xmm7, %xmm2"); + asm volatile("sha256msg2 (%eax), %xmm0"); + asm volatile("sha256msg2 (0x12345678), %xmm0"); + asm volatile("sha256msg2 (%eax), %xmm3"); + asm volatile("sha256msg2 (%ecx,%eax,1), %xmm0"); + asm volatile("sha256msg2 0x12345678(,%eax,1), %xmm0"); + asm volatile("sha256msg2 (%eax,%ecx,1), %xmm0"); + asm volatile("sha256msg2 (%eax,%ecx,8), %xmm0"); + asm volatile("sha256msg2 0x12(%eax), %xmm0"); + asm volatile("sha256msg2 0x12(%ebp), %xmm0"); + asm volatile("sha256msg2 0x12(%ecx,%eax,1), %xmm0"); + asm volatile("sha256msg2 0x12(%ebp,%eax,1), %xmm0"); + asm volatile("sha256msg2 0x12(%eax,%ecx,1), %xmm0"); + asm volatile("sha256msg2 0x12(%eax,%ecx,8), %xmm0"); + asm volatile("sha256msg2 0x12345678(%eax), %xmm0"); + asm volatile("sha256msg2 0x12345678(%ebp), %xmm0"); + asm volatile("sha256msg2 0x12345678(%ecx,%eax,1), %xmm0"); + asm volatile("sha256msg2 0x12345678(%ebp,%eax,1), %xmm0"); + asm volatile("sha256msg2 0x12345678(%eax,%ecx,1), %xmm0"); + asm volatile("sha256msg2 0x12345678(%eax,%ecx,8), %xmm0"); + + /* clflushopt m8 */ + + asm volatile("clflushopt (%eax)"); + asm volatile("clflushopt (0x12345678)"); + asm volatile("clflushopt 0x12345678(%eax,%ecx,8)"); + /* Also check instructions in the same group encoding as clflushopt */ + asm volatile("clflush (%eax)"); + asm volatile("sfence"); + + /* clwb m8 */ + + asm volatile("clwb (%eax)"); + asm volatile("clwb (0x12345678)"); + asm volatile("clwb 0x12345678(%eax,%ecx,8)"); + /* Also check instructions in the same group encoding as clwb */ + asm volatile("xsaveopt (%eax)"); + asm volatile("mfence"); + + /* xsavec mem */ + + asm volatile("xsavec (%eax)"); + asm volatile("xsavec (0x12345678)"); + asm volatile("xsavec 0x12345678(%eax,%ecx,8)"); + + /* xsaves mem */ + + asm volatile("xsaves (%eax)"); + asm volatile("xsaves (0x12345678)"); + asm volatile("xsaves 0x12345678(%eax,%ecx,8)"); + + /* xrstors mem */ + + asm volatile("xrstors (%eax)"); + asm volatile("xrstors (0x12345678)"); + asm volatile("xrstors 0x12345678(%eax,%ecx,8)"); + +#endif /* #ifndef __x86_64__ */ + + /* pcommit */ + + asm volatile("pcommit"); + + /* Following line is a marker for the awk script - do not change */ + asm volatile("rdtsc"); /* Stop here */ + + return 0; +} diff --git a/tools/perf/arch/x86/tests/insn-x86.c b/tools/perf/arch/x86/tests/insn-x86.c new file mode 100644 index 000000000000..b6115dfd28f0 --- /dev/null +++ b/tools/perf/arch/x86/tests/insn-x86.c @@ -0,0 +1,185 @@ +#include + +#include "debug.h" +#include "tests/tests.h" +#include "arch-tests.h" + +#include "intel-pt-decoder/insn.h" +#include "intel-pt-decoder/intel-pt-insn-decoder.h" + +struct test_data { + u8 data[MAX_INSN_SIZE]; + int expected_length; + int expected_rel; + const char *expected_op_str; + const char *expected_branch_str; + const char *asm_rep; +}; + +struct test_data test_data_32[] = { +#include "insn-x86-dat-32.c" + {{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"}, + {{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"}, + {{0}, 0, 0, NULL, NULL, NULL}, +}; + +struct test_data test_data_64[] = { +#include "insn-x86-dat-64.c" + {{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"}, + {{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"}, + {{0}, 0, 0, NULL, NULL, NULL}, +}; + +static int get_op(const char *op_str) +{ + struct val_data { + const char *name; + int val; + } vals[] = { + {"other", INTEL_PT_OP_OTHER}, + {"call", INTEL_PT_OP_CALL}, + {"ret", INTEL_PT_OP_RET}, + {"jcc", INTEL_PT_OP_JCC}, + {"jmp", INTEL_PT_OP_JMP}, + {"loop", INTEL_PT_OP_LOOP}, + {"iret", INTEL_PT_OP_IRET}, + {"int", INTEL_PT_OP_INT}, + {"syscall", INTEL_PT_OP_SYSCALL}, + {"sysret", INTEL_PT_OP_SYSRET}, + {NULL, 0}, + }; + struct val_data *val; + + if (!op_str || !strlen(op_str)) + return 0; + + for (val = vals; val->name; val++) { + if (!strcmp(val->name, op_str)) + return val->val; + } + + pr_debug("Failed to get op\n"); + + return -1; +} + +static int get_branch(const char *branch_str) +{ + struct val_data { + const char *name; + int val; + } vals[] = { + {"no_branch", INTEL_PT_BR_NO_BRANCH}, + {"indirect", INTEL_PT_BR_INDIRECT}, + {"conditional", INTEL_PT_BR_CONDITIONAL}, + {"unconditional", INTEL_PT_BR_UNCONDITIONAL}, + {NULL, 0}, + }; + struct val_data *val; + + if (!branch_str || !strlen(branch_str)) + return 0; + + for (val = vals; val->name; val++) { + if (!strcmp(val->name, branch_str)) + return val->val; + } + + pr_debug("Failed to get branch\n"); + + return -1; +} + +static int test_data_item(struct test_data *dat, int x86_64) +{ + struct intel_pt_insn intel_pt_insn; + struct insn insn; + int op, branch; + + insn_init(&insn, dat->data, MAX_INSN_SIZE, x86_64); + insn_get_length(&insn); + + if (!insn_complete(&insn)) { + pr_debug("Failed to decode: %s\n", dat->asm_rep); + return -1; + } + + if (insn.length != dat->expected_length) { + pr_debug("Failed to decode length (%d vs expected %d): %s\n", + insn.length, dat->expected_length, dat->asm_rep); + return -1; + } + + op = get_op(dat->expected_op_str); + branch = get_branch(dat->expected_branch_str); + + if (intel_pt_get_insn(dat->data, MAX_INSN_SIZE, x86_64, &intel_pt_insn)) { + pr_debug("Intel PT failed to decode: %s\n", dat->asm_rep); + return -1; + } + + if ((int)intel_pt_insn.op != op) { + pr_debug("Failed to decode 'op' value (%d vs expected %d): %s\n", + intel_pt_insn.op, op, dat->asm_rep); + return -1; + } + + if ((int)intel_pt_insn.branch != branch) { + pr_debug("Failed to decode 'branch' value (%d vs expected %d): %s\n", + intel_pt_insn.branch, branch, dat->asm_rep); + return -1; + } + + if (intel_pt_insn.rel != dat->expected_rel) { + pr_debug("Failed to decode 'rel' value (%#x vs expected %#x): %s\n", + intel_pt_insn.rel, dat->expected_rel, dat->asm_rep); + return -1; + } + + pr_debug("Decoded ok: %s\n", dat->asm_rep); + + return 0; +} + +static int test_data_set(struct test_data *dat_set, int x86_64) +{ + struct test_data *dat; + int ret = 0; + + for (dat = dat_set; dat->expected_length; dat++) { + if (test_data_item(dat, x86_64)) + ret = -1; + } + + return ret; +} + +/** + * test__insn_x86 - test x86 instruction decoder - new instructions. + * + * This function implements a test that decodes a selection of instructions and + * checks the results. The Intel PT function that further categorizes + * instructions (i.e. intel_pt_get_insn()) is also checked. + * + * The instructions are originally in insn-x86-dat-src.c which has been + * processed by scripts gen-insn-x86-dat.sh and gen-insn-x86-dat.awk to produce + * insn-x86-dat-32.c and insn-x86-dat-64.c which are included into this program. + * i.e. to add new instructions to the test, edit insn-x86-dat-src.c, run the + * gen-insn-x86-dat.sh script, make perf, and then run the test. + * + * If the test passes %0 is returned, otherwise %-1 is returned. Use the + * verbose (-v) option to see all the instructions and whether or not they + * decoded successfuly. + */ +int test__insn_x86(void) +{ + int ret = 0; + + if (test_data_set(test_data_32, 0)) + ret = -1; + + if (test_data_set(test_data_64, 1)) + ret = -1; + + return ret; +} diff --git a/tools/perf/arch/x86/tests/perf-time-to-tsc.c b/tools/perf/arch/x86/tests/perf-time-to-tsc.c new file mode 100644 index 000000000000..658cd200af74 --- /dev/null +++ b/tools/perf/arch/x86/tests/perf-time-to-tsc.c @@ -0,0 +1,164 @@ +#include +#include +#include +#include + +#include "parse-events.h" +#include "evlist.h" +#include "evsel.h" +#include "thread_map.h" +#include "cpumap.h" +#include "tsc.h" +#include "tests/tests.h" + +#include "arch-tests.h" + +#define CHECK__(x) { \ + while ((x) < 0) { \ + pr_debug(#x " failed!\n"); \ + goto out_err; \ + } \ +} + +#define CHECK_NOT_NULL__(x) { \ + while ((x) == NULL) { \ + pr_debug(#x " failed!\n"); \ + goto out_err; \ + } \ +} + +/** + * test__perf_time_to_tsc - test converting perf time to TSC. + * + * This function implements a test that checks that the conversion of perf time + * to and from TSC is consistent with the order of events. If the test passes + * %0 is returned, otherwise %-1 is returned. If TSC conversion is not + * supported then then the test passes but " (not supported)" is printed. + */ +int test__perf_time_to_tsc(void) +{ + struct record_opts opts = { + .mmap_pages = UINT_MAX, + .user_freq = UINT_MAX, + .user_interval = ULLONG_MAX, + .freq = 4000, + .target = { + .uses_mmap = true, + }, + .sample_time = true, + }; + struct thread_map *threads = NULL; + struct cpu_map *cpus = NULL; + struct perf_evlist *evlist = NULL; + struct perf_evsel *evsel = NULL; + int err = -1, ret, i; + const char *comm1, *comm2; + struct perf_tsc_conversion tc; + struct perf_event_mmap_page *pc; + union perf_event *event; + u64 test_tsc, comm1_tsc, comm2_tsc; + u64 test_time, comm1_time = 0, comm2_time = 0; + + threads = thread_map__new(-1, getpid(), UINT_MAX); + CHECK_NOT_NULL__(threads); + + cpus = cpu_map__new(NULL); + CHECK_NOT_NULL__(cpus); + + evlist = perf_evlist__new(); + CHECK_NOT_NULL__(evlist); + + perf_evlist__set_maps(evlist, cpus, threads); + + CHECK__(parse_events(evlist, "cycles:u", NULL)); + + perf_evlist__config(evlist, &opts); + + evsel = perf_evlist__first(evlist); + + evsel->attr.comm = 1; + evsel->attr.disabled = 1; + evsel->attr.enable_on_exec = 0; + + CHECK__(perf_evlist__open(evlist)); + + CHECK__(perf_evlist__mmap(evlist, UINT_MAX, false)); + + pc = evlist->mmap[0].base; + ret = perf_read_tsc_conversion(pc, &tc); + if (ret) { + if (ret == -EOPNOTSUPP) { + fprintf(stderr, " (not supported)"); + return 0; + } + goto out_err; + } + + perf_evlist__enable(evlist); + + comm1 = "Test COMM 1"; + CHECK__(prctl(PR_SET_NAME, (unsigned long)comm1, 0, 0, 0)); + + test_tsc = rdtsc(); + + comm2 = "Test COMM 2"; + CHECK__(prctl(PR_SET_NAME, (unsigned long)comm2, 0, 0, 0)); + + perf_evlist__disable(evlist); + + for (i = 0; i < evlist->nr_mmaps; i++) { + while ((event = perf_evlist__mmap_read(evlist, i)) != NULL) { + struct perf_sample sample; + + if (event->header.type != PERF_RECORD_COMM || + (pid_t)event->comm.pid != getpid() || + (pid_t)event->comm.tid != getpid()) + goto next_event; + + if (strcmp(event->comm.comm, comm1) == 0) { + CHECK__(perf_evsel__parse_sample(evsel, event, + &sample)); + comm1_time = sample.time; + } + if (strcmp(event->comm.comm, comm2) == 0) { + CHECK__(perf_evsel__parse_sample(evsel, event, + &sample)); + comm2_time = sample.time; + } +next_event: + perf_evlist__mmap_consume(evlist, i); + } + } + + if (!comm1_time || !comm2_time) + goto out_err; + + test_time = tsc_to_perf_time(test_tsc, &tc); + comm1_tsc = perf_time_to_tsc(comm1_time, &tc); + comm2_tsc = perf_time_to_tsc(comm2_time, &tc); + + pr_debug("1st event perf time %"PRIu64" tsc %"PRIu64"\n", + comm1_time, comm1_tsc); + pr_debug("rdtsc time %"PRIu64" tsc %"PRIu64"\n", + test_time, test_tsc); + pr_debug("2nd event perf time %"PRIu64" tsc %"PRIu64"\n", + comm2_time, comm2_tsc); + + if (test_time <= comm1_time || + test_time >= comm2_time) + goto out_err; + + if (test_tsc <= comm1_tsc || + test_tsc >= comm2_tsc) + goto out_err; + + err = 0; + +out_err: + if (evlist) { + perf_evlist__disable(evlist); + perf_evlist__delete(evlist); + } + + return err; +} diff --git a/tools/perf/arch/x86/tests/rdpmc.c b/tools/perf/arch/x86/tests/rdpmc.c new file mode 100644 index 000000000000..e7688214c7cf --- /dev/null +++ b/tools/perf/arch/x86/tests/rdpmc.c @@ -0,0 +1,174 @@ +#include +#include +#include +#include +#include +#include "perf.h" +#include "debug.h" +#include "tests/tests.h" +#include "cloexec.h" +#include "arch-tests.h" + +static u64 rdpmc(unsigned int counter) +{ + unsigned int low, high; + + asm volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (counter)); + + return low | ((u64)high) << 32; +} + +static u64 rdtsc(void) +{ + unsigned int low, high; + + asm volatile("rdtsc" : "=a" (low), "=d" (high)); + + return low | ((u64)high) << 32; +} + +static u64 mmap_read_self(void *addr) +{ + struct perf_event_mmap_page *pc = addr; + u32 seq, idx, time_mult = 0, time_shift = 0; + u64 count, cyc = 0, time_offset = 0, enabled, running, delta; + + do { + seq = pc->lock; + barrier(); + + enabled = pc->time_enabled; + running = pc->time_running; + + if (enabled != running) { + cyc = rdtsc(); + time_mult = pc->time_mult; + time_shift = pc->time_shift; + time_offset = pc->time_offset; + } + + idx = pc->index; + count = pc->offset; + if (idx) + count += rdpmc(idx - 1); + + barrier(); + } while (pc->lock != seq); + + if (enabled != running) { + u64 quot, rem; + + quot = (cyc >> time_shift); + rem = cyc & ((1 << time_shift) - 1); + delta = time_offset + quot * time_mult + + ((rem * time_mult) >> time_shift); + + enabled += delta; + if (idx) + running += delta; + + quot = count / running; + rem = count % running; + count = quot * enabled + (rem * enabled) / running; + } + + return count; +} + +/* + * If the RDPMC instruction faults then signal this back to the test parent task: + */ +static void segfault_handler(int sig __maybe_unused, + siginfo_t *info __maybe_unused, + void *uc __maybe_unused) +{ + exit(-1); +} + +static int __test__rdpmc(void) +{ + volatile int tmp = 0; + u64 i, loops = 1000; + int n; + int fd; + void *addr; + struct perf_event_attr attr = { + .type = PERF_TYPE_HARDWARE, + .config = PERF_COUNT_HW_INSTRUCTIONS, + .exclude_kernel = 1, + }; + u64 delta_sum = 0; + struct sigaction sa; + char sbuf[STRERR_BUFSIZE]; + + sigfillset(&sa.sa_mask); + sa.sa_sigaction = segfault_handler; + sigaction(SIGSEGV, &sa, NULL); + + fd = sys_perf_event_open(&attr, 0, -1, -1, + perf_event_open_cloexec_flag()); + if (fd < 0) { + pr_err("Error: sys_perf_event_open() syscall returned " + "with %d (%s)\n", fd, + strerror_r(errno, sbuf, sizeof(sbuf))); + return -1; + } + + addr = mmap(NULL, page_size, PROT_READ, MAP_SHARED, fd, 0); + if (addr == (void *)(-1)) { + pr_err("Error: mmap() syscall returned with (%s)\n", + strerror_r(errno, sbuf, sizeof(sbuf))); + goto out_close; + } + + for (n = 0; n < 6; n++) { + u64 stamp, now, delta; + + stamp = mmap_read_self(addr); + + for (i = 0; i < loops; i++) + tmp++; + + now = mmap_read_self(addr); + loops *= 10; + + delta = now - stamp; + pr_debug("%14d: %14Lu\n", n, (long long)delta); + + delta_sum += delta; + } + + munmap(addr, page_size); + pr_debug(" "); +out_close: + close(fd); + + if (!delta_sum) + return -1; + + return 0; +} + +int test__rdpmc(void) +{ + int status = 0; + int wret = 0; + int ret; + int pid; + + pid = fork(); + if (pid < 0) + return -1; + + if (!pid) { + ret = __test__rdpmc(); + + exit(ret); + } + + wret = waitpid(pid, &status, 0); + if (wret < 0 || status) + return -1; + + return 0; +} diff --git a/tools/perf/tests/Build b/tools/perf/tests/Build index c6f198ae65fb..50de2253cff6 100644 --- a/tools/perf/tests/Build +++ b/tools/perf/tests/Build @@ -8,7 +8,6 @@ perf-y += openat-syscall-all-cpus.o perf-y += openat-syscall-tp-fields.o perf-y += mmap-basic.o perf-y += perf-record.o -perf-y += rdpmc.o perf-y += evsel-roundtrip-name.o perf-y += evsel-tp-sched.o perf-y += fdarray.o @@ -35,11 +34,6 @@ perf-y += thread-map.o perf-y += llvm.o perf-y += topology.o -perf-$(CONFIG_X86) += perf-time-to-tsc.o -ifdef CONFIG_AUXTRACE -perf-$(CONFIG_X86) += insn-x86.o -endif - ifeq ($(ARCH),$(filter $(ARCH),x86 arm arm64)) perf-$(CONFIG_DWARF_UNWIND) += dwarf-unwind.o endif diff --git a/tools/perf/tests/builtin-test.c b/tools/perf/tests/builtin-test.c index 2b6c1bf13456..66f72d3d6677 100644 --- a/tools/perf/tests/builtin-test.c +++ b/tools/perf/tests/builtin-test.c @@ -41,12 +41,6 @@ static struct test generic_tests[] = { .desc = "parse events tests", .func = test__parse_events, }, -#if defined(__x86_64__) || defined(__i386__) - { - .desc = "x86 rdpmc test", - .func = test__rdpmc, - }, -#endif { .desc = "Validate PERF_RECORD_* events & perf_sample fields", .func = test__PERF_RECORD, @@ -107,12 +101,6 @@ static struct test generic_tests[] = { .desc = "Test software clock events have valid period values", .func = test__sw_clock_freq, }, -#if defined(__x86_64__) || defined(__i386__) - { - .desc = "Test converting perf time to TSC", - .func = test__perf_time_to_tsc, - }, -#endif { .desc = "Test object code reading", .func = test__code_reading, @@ -129,14 +117,6 @@ static struct test generic_tests[] = { .desc = "Test parsing with no sample_id_all bit set", .func = test__parse_no_sample_id_all, }, -#if defined(__x86_64__) || defined(__i386__) || defined(__arm__) || defined(__aarch64__) -#ifdef HAVE_DWARF_UNWIND_SUPPORT - { - .desc = "Test dwarf unwind", - .func = test__dwarf_unwind, - }, -#endif -#endif { .desc = "Test filtering hist entries", .func = test__hists_filter, @@ -181,14 +161,6 @@ static struct test generic_tests[] = { .desc = "Test LLVM searching and compiling", .func = test__llvm, }, -#ifdef HAVE_AUXTRACE_SUPPORT -#if defined(__x86_64__) || defined(__i386__) - { - .desc = "Test x86 instruction decoder - new instructions", - .func = test__insn_x86, - }, -#endif -#endif { .desc = "Test topology in session", .func = test_session_topology, diff --git a/tools/perf/tests/dwarf-unwind.c b/tools/perf/tests/dwarf-unwind.c index 40b36c462427..07221793a3ac 100644 --- a/tools/perf/tests/dwarf-unwind.c +++ b/tools/perf/tests/dwarf-unwind.c @@ -11,6 +11,10 @@ #include "thread.h" #include "callchain.h" +#if defined (__x86_64__) || defined (__i386__) +#include "arch-tests.h" +#endif + /* For bsearch. We try to unwind functions in shared object. */ #include diff --git a/tools/perf/tests/gen-insn-x86-dat.awk b/tools/perf/tests/gen-insn-x86-dat.awk deleted file mode 100644 index a21454835cd4..000000000000 --- a/tools/perf/tests/gen-insn-x86-dat.awk +++ /dev/null @@ -1,75 +0,0 @@ -#!/bin/awk -f -# gen-insn-x86-dat.awk: script to convert data for the insn-x86 test -# Copyright (c) 2015, Intel Corporation. -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. - -BEGIN { - print "/*" - print " * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk" - print " * from insn-x86-dat-src.c for inclusion by insn-x86.c" - print " * Do not change this code." - print "*/\n" - op = "" - branch = "" - rel = 0 - going = 0 -} - -/ Start here / { - going = 1 -} - -/ Stop here / { - going = 0 -} - -/^\s*[0-9a-fA-F]+\:/ { - if (going) { - colon_pos = index($0, ":") - useful_line = substr($0, colon_pos + 1) - first_pos = match(useful_line, "[0-9a-fA-F]") - useful_line = substr(useful_line, first_pos) - gsub("\t", "\\t", useful_line) - printf "{{" - len = 0 - for (i = 2; i <= NF; i++) { - if (match($i, "^[0-9a-fA-F][0-9a-fA-F]$")) { - printf "0x%s, ", $i - len += 1 - } else { - break - } - } - printf "}, %d, %s, \"%s\", \"%s\",", len, rel, op, branch - printf "\n\"%s\",},\n", useful_line - op = "" - branch = "" - rel = 0 - } -} - -/ Expecting: / { - expecting_str = " Expecting: " - expecting_len = length(expecting_str) - expecting_pos = index($0, expecting_str) - useful_line = substr($0, expecting_pos + expecting_len) - for (i = 1; i <= NF; i++) { - if ($i == "Expecting:") { - i++ - op = $i - i++ - branch = $i - i++ - rel = $i - break - } - } -} diff --git a/tools/perf/tests/gen-insn-x86-dat.sh b/tools/perf/tests/gen-insn-x86-dat.sh deleted file mode 100755 index 2d4ef94cff98..000000000000 --- a/tools/perf/tests/gen-insn-x86-dat.sh +++ /dev/null @@ -1,43 +0,0 @@ -#!/bin/sh -# gen-insn-x86-dat: generate data for the insn-x86 test -# Copyright (c) 2015, Intel Corporation. -# -# This program is free software; you can redistribute it and/or modify it -# under the terms and conditions of the GNU General Public License, -# version 2, as published by the Free Software Foundation. -# -# This program is distributed in the hope it will be useful, but WITHOUT -# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -# more details. - -set -e - -if [ "$(uname -m)" != "x86_64" ]; then - echo "ERROR: This script only works on x86_64" - exit 1 -fi - -cd $(dirname $0) - -trap 'echo "Might need a more recent version of binutils"' EXIT - -echo "Compiling insn-x86-dat-src.c to 64-bit object" - -gcc -g -c insn-x86-dat-src.c - -objdump -dSw insn-x86-dat-src.o | awk -f gen-insn-x86-dat.awk > insn-x86-dat-64.c - -rm -f insn-x86-dat-src.o - -echo "Compiling insn-x86-dat-src.c to 32-bit object" - -gcc -g -c -m32 insn-x86-dat-src.c - -objdump -dSw insn-x86-dat-src.o | awk -f gen-insn-x86-dat.awk > insn-x86-dat-32.c - -rm -f insn-x86-dat-src.o - -trap - EXIT - -echo "Done (use git diff to see the changes)" diff --git a/tools/perf/tests/insn-x86-dat-32.c b/tools/perf/tests/insn-x86-dat-32.c deleted file mode 100644 index 3b491cfe204e..000000000000 --- a/tools/perf/tests/insn-x86-dat-32.c +++ /dev/null @@ -1,658 +0,0 @@ -/* - * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk - * from insn-x86-dat-src.c for inclusion by insn-x86.c - * Do not change this code. -*/ - -{{0x0f, 0x31, }, 2, 0, "", "", -"0f 31 \trdtsc ",}, -{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", -"f3 0f 1b 00 \tbndmk (%eax),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x05, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f3 0f 1b 05 78 56 34 12 \tbndmk 0x12345678,%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", -"f3 0f 1b 18 \tbndmk (%eax),%bnd3",}, -{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", -"f3 0f 1b 04 01 \tbndmk (%ecx,%eax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%eax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", -"f3 0f 1b 04 08 \tbndmk (%eax,%ecx,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", -"f3 0f 1b 04 c8 \tbndmk (%eax,%ecx,8),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", -"f3 0f 1b 40 12 \tbndmk 0x12(%eax),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", -"f3 0f 1b 45 12 \tbndmk 0x12(%ebp),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", -"f3 0f 1b 44 01 12 \tbndmk 0x12(%ecx,%eax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", -"f3 0f 1b 44 05 12 \tbndmk 0x12(%ebp,%eax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", -"f3 0f 1b 44 08 12 \tbndmk 0x12(%eax,%ecx,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", -"f3 0f 1b 44 c8 12 \tbndmk 0x12(%eax,%ecx,8),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%eax),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%ebp),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%ecx,%eax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 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- * Generated by gen-insn-x86-dat.sh and gen-insn-x86-dat.awk - * from insn-x86-dat-src.c for inclusion by insn-x86.c - * Do not change this code. -*/ - -{{0x0f, 0x31, }, 2, 0, "", "", -"0f 31 \trdtsc ",}, -{{0xf3, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", -"f3 0f 1b 00 \tbndmk (%rax),%bnd0",}, -{{0xf3, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", -"f3 41 0f 1b 00 \tbndmk (%r8),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1b 04 25 78 56 34 12 \tbndmk 0x12345678,%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", -"f3 0f 1b 18 \tbndmk (%rax),%bnd3",}, -{{0xf3, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", -"f3 0f 1b 04 01 \tbndmk (%rcx,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1b 04 05 78 56 34 12 \tbndmk 0x12345678(,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", -"f3 0f 1b 04 08 \tbndmk (%rax,%rcx,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", -"f3 0f 1b 04 c8 \tbndmk (%rax,%rcx,8),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", -"f3 0f 1b 40 12 \tbndmk 0x12(%rax),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", -"f3 0f 1b 45 12 \tbndmk 0x12(%rbp),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", -"f3 0f 1b 44 01 12 \tbndmk 0x12(%rcx,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", -"f3 0f 1b 44 05 12 \tbndmk 0x12(%rbp,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", -"f3 0f 1b 44 08 12 \tbndmk 0x12(%rax,%rcx,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", -"f3 0f 1b 44 c8 12 \tbndmk 0x12(%rax,%rcx,8),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f3 0f 1b 80 78 56 34 12 \tbndmk 0x12345678(%rax),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f3 0f 1b 85 78 56 34 12 \tbndmk 0x12345678(%rbp),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1b 84 01 78 56 34 12 \tbndmk 0x12345678(%rcx,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1b 84 05 78 56 34 12 \tbndmk 0x12345678(%rbp,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1b 84 08 78 56 34 12 \tbndmk 0x12345678(%rax,%rcx,1),%bnd0",}, -{{0xf3, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1b 84 c8 78 56 34 12 \tbndmk 0x12345678(%rax,%rcx,8),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", -"f3 0f 1a 00 \tbndcl (%rax),%bnd0",}, -{{0xf3, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "", -"f3 41 0f 1a 00 \tbndcl (%r8),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1a 04 25 78 56 34 12 \tbndcl 0x12345678,%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", -"f3 0f 1a 18 \tbndcl (%rax),%bnd3",}, -{{0xf3, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", -"f3 0f 1a 04 01 \tbndcl (%rcx,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1a 04 05 78 56 34 12 \tbndcl 0x12345678(,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "", -"f3 0f 1a 04 08 \tbndcl (%rax,%rcx,1),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "", -"f3 0f 1a 04 c8 \tbndcl (%rax,%rcx,8),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "", -"f3 0f 1a 40 12 \tbndcl 0x12(%rax),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "", -"f3 0f 1a 45 12 \tbndcl 0x12(%rbp),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "", -"f3 0f 1a 44 01 12 \tbndcl 0x12(%rcx,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "", -"f3 0f 1a 44 05 12 \tbndcl 0x12(%rbp,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "", -"f3 0f 1a 44 08 12 \tbndcl 0x12(%rax,%rcx,1),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "", -"f3 0f 1a 44 c8 12 \tbndcl 0x12(%rax,%rcx,8),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f3 0f 1a 80 78 56 34 12 \tbndcl 0x12345678(%rax),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f3 0f 1a 85 78 56 34 12 \tbndcl 0x12345678(%rbp),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1a 84 01 78 56 34 12 \tbndcl 0x12345678(%rcx,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1a 84 05 78 56 34 12 \tbndcl 0x12345678(%rbp,%rax,1),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1a 84 08 78 56 34 12 \tbndcl 0x12345678(%rax,%rcx,1),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f3 0f 1a 84 c8 78 56 34 12 \tbndcl 0x12345678(%rax,%rcx,8),%bnd0",}, -{{0xf3, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "", -"f3 0f 1a c0 \tbndcl %rax,%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", -"f2 0f 1a 00 \tbndcu (%rax),%bnd0",}, -{{0xf2, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "", -"f2 41 0f 1a 00 \tbndcu (%r8),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1a 04 25 78 56 34 12 \tbndcu 0x12345678,%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", -"f2 0f 1a 18 \tbndcu (%rax),%bnd3",}, -{{0xf2, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", -"f2 0f 1a 04 01 \tbndcu (%rcx,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1a 04 05 78 56 34 12 \tbndcu 0x12345678(,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "", -"f2 0f 1a 04 08 \tbndcu (%rax,%rcx,1),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "", -"f2 0f 1a 04 c8 \tbndcu (%rax,%rcx,8),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "", -"f2 0f 1a 40 12 \tbndcu 0x12(%rax),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "", -"f2 0f 1a 45 12 \tbndcu 0x12(%rbp),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "", -"f2 0f 1a 44 01 12 \tbndcu 0x12(%rcx,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "", -"f2 0f 1a 44 05 12 \tbndcu 0x12(%rbp,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "", -"f2 0f 1a 44 08 12 \tbndcu 0x12(%rax,%rcx,1),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "", -"f2 0f 1a 44 c8 12 \tbndcu 0x12(%rax,%rcx,8),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f2 0f 1a 80 78 56 34 12 \tbndcu 0x12345678(%rax),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f2 0f 1a 85 78 56 34 12 \tbndcu 0x12345678(%rbp),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1a 84 01 78 56 34 12 \tbndcu 0x12345678(%rcx,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1a 84 05 78 56 34 12 \tbndcu 0x12345678(%rbp,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1a 84 08 78 56 34 12 \tbndcu 0x12345678(%rax,%rcx,1),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1a 84 c8 78 56 34 12 \tbndcu 0x12345678(%rax,%rcx,8),%bnd0",}, -{{0xf2, 0x0f, 0x1a, 0xc0, }, 4, 0, "", "", -"f2 0f 1a c0 \tbndcu %rax,%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", -"f2 0f 1b 00 \tbndcn (%rax),%bnd0",}, -{{0xf2, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", -"f2 41 0f 1b 00 \tbndcn (%r8),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1b 04 25 78 56 34 12 \tbndcn 0x12345678,%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", -"f2 0f 1b 18 \tbndcn (%rax),%bnd3",}, -{{0xf2, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", -"f2 0f 1b 04 01 \tbndcn (%rcx,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1b 04 05 78 56 34 12 \tbndcn 0x12345678(,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", -"f2 0f 1b 04 08 \tbndcn (%rax,%rcx,1),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", -"f2 0f 1b 04 c8 \tbndcn (%rax,%rcx,8),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", -"f2 0f 1b 40 12 \tbndcn 0x12(%rax),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", -"f2 0f 1b 45 12 \tbndcn 0x12(%rbp),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", -"f2 0f 1b 44 01 12 \tbndcn 0x12(%rcx,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", -"f2 0f 1b 44 05 12 \tbndcn 0x12(%rbp,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", -"f2 0f 1b 44 08 12 \tbndcn 0x12(%rax,%rcx,1),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", -"f2 0f 1b 44 c8 12 \tbndcn 0x12(%rax,%rcx,8),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f2 0f 1b 80 78 56 34 12 \tbndcn 0x12345678(%rax),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"f2 0f 1b 85 78 56 34 12 \tbndcn 0x12345678(%rbp),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1b 84 01 78 56 34 12 \tbndcn 0x12345678(%rcx,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1b 84 05 78 56 34 12 \tbndcn 0x12345678(%rbp,%rax,1),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1b 84 08 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,1),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"f2 0f 1b 84 c8 78 56 34 12 \tbndcn 0x12345678(%rax,%rcx,8),%bnd0",}, -{{0xf2, 0x0f, 0x1b, 0xc0, }, 4, 0, "", "", -"f2 0f 1b c0 \tbndcn %rax,%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x00, }, 4, 0, "", "", -"66 0f 1a 00 \tbndmov (%rax),%bnd0",}, -{{0x66, 0x41, 0x0f, 0x1a, 0x00, }, 5, 0, "", "", -"66 41 0f 1a 00 \tbndmov (%r8),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f 1a 04 25 78 56 34 12 \tbndmov 0x12345678,%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x18, }, 4, 0, "", "", -"66 0f 1a 18 \tbndmov (%rax),%bnd3",}, -{{0x66, 0x0f, 0x1a, 0x04, 0x01, }, 5, 0, "", "", -"66 0f 1a 04 01 \tbndmov (%rcx,%rax,1),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f 1a 04 05 78 56 34 12 \tbndmov 0x12345678(,%rax,1),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x04, 0x08, }, 5, 0, "", "", -"66 0f 1a 04 08 \tbndmov (%rax,%rcx,1),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x04, 0xc8, }, 5, 0, "", "", -"66 0f 1a 04 c8 \tbndmov (%rax,%rcx,8),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x40, 0x12, }, 5, 0, "", "", -"66 0f 1a 40 12 \tbndmov 0x12(%rax),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x45, 0x12, }, 5, 0, "", "", -"66 0f 1a 45 12 \tbndmov 0x12(%rbp),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x44, 0x01, 0x12, }, 6, 0, "", "", -"66 0f 1a 44 01 12 \tbndmov 0x12(%rcx,%rax,1),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x44, 0x05, 0x12, }, 6, 0, "", "", -"66 0f 1a 44 05 12 \tbndmov 0x12(%rbp,%rax,1),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x44, 0x08, 0x12, }, 6, 0, "", "", -"66 0f 1a 44 08 12 \tbndmov 0x12(%rax,%rcx,1),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x44, 0xc8, 0x12, }, 6, 0, "", "", -"66 0f 1a 44 c8 12 \tbndmov 0x12(%rax,%rcx,8),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"66 0f 1a 80 78 56 34 12 \tbndmov 0x12345678(%rax),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"66 0f 1a 85 78 56 34 12 \tbndmov 0x12345678(%rbp),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f 1a 84 01 78 56 34 12 \tbndmov 0x12345678(%rcx,%rax,1),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f 1a 84 05 78 56 34 12 \tbndmov 0x12345678(%rbp,%rax,1),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f 1a 84 08 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,1),%bnd0",}, -{{0x66, 0x0f, 0x1a, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f 1a 84 c8 78 56 34 12 \tbndmov 0x12345678(%rax,%rcx,8),%bnd0",}, -{{0x66, 0x0f, 0x1b, 0x00, }, 4, 0, "", "", -"66 0f 1b 00 \tbndmov %bnd0,(%rax)",}, -{{0x66, 0x41, 0x0f, 0x1b, 0x00, }, 5, 0, "", "", -"66 41 0f 1b 00 \tbndmov %bnd0,(%r8)",}, -{{0x66, 0x0f, 0x1b, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f 1b 04 25 78 56 34 12 \tbndmov %bnd0,0x12345678",}, -{{0x66, 0x0f, 0x1b, 0x18, }, 4, 0, "", "", -"66 0f 1b 18 \tbndmov %bnd3,(%rax)",}, -{{0x66, 0x0f, 0x1b, 0x04, 0x01, }, 5, 0, "", "", -"66 0f 1b 04 01 \tbndmov %bnd0,(%rcx,%rax,1)",}, -{{0x66, 0x0f, 0x1b, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f 1b 04 05 78 56 34 12 \tbndmov %bnd0,0x12345678(,%rax,1)",}, -{{0x66, 0x0f, 0x1b, 0x04, 0x08, }, 5, 0, "", "", -"66 0f 1b 04 08 \tbndmov %bnd0,(%rax,%rcx,1)",}, -{{0x66, 0x0f, 0x1b, 0x04, 0xc8, }, 5, 0, "", "", -"66 0f 1b 04 c8 \tbndmov %bnd0,(%rax,%rcx,8)",}, -{{0x66, 0x0f, 0x1b, 0x40, 0x12, }, 5, 0, "", "", -"66 0f 1b 40 12 \tbndmov %bnd0,0x12(%rax)",}, -{{0x66, 0x0f, 0x1b, 0x45, 0x12, }, 5, 0, "", "", -"66 0f 1b 45 12 \tbndmov %bnd0,0x12(%rbp)",}, -{{0x66, 0x0f, 0x1b, 0x44, 0x01, 0x12, }, 6, 0, "", "", -"66 0f 1b 44 01 12 \tbndmov %bnd0,0x12(%rcx,%rax,1)",}, -{{0x66, 0x0f, 0x1b, 0x44, 0x05, 0x12, }, 6, 0, "", "", -"66 0f 1b 44 05 12 \tbndmov %bnd0,0x12(%rbp,%rax,1)",}, -{{0x66, 0x0f, 0x1b, 0x44, 0x08, 0x12, }, 6, 0, "", "", -"66 0f 1b 44 08 12 \tbndmov %bnd0,0x12(%rax,%rcx,1)",}, -{{0x66, 0x0f, 0x1b, 0x44, 0xc8, 0x12, }, 6, 0, "", "", -"66 0f 1b 44 c8 12 \tbndmov %bnd0,0x12(%rax,%rcx,8)",}, -{{0x66, 0x0f, 0x1b, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"66 0f 1b 80 78 56 34 12 \tbndmov %bnd0,0x12345678(%rax)",}, -{{0x66, 0x0f, 0x1b, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"66 0f 1b 85 78 56 34 12 \tbndmov %bnd0,0x12345678(%rbp)",}, -{{0x66, 0x0f, 0x1b, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f 1b 84 01 78 56 34 12 \tbndmov %bnd0,0x12345678(%rcx,%rax,1)",}, -{{0x66, 0x0f, 0x1b, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 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%xmm15,%xmm8",}, -{{0x0f, 0x38, 0xcd, 0x00, }, 4, 0, "", "", -"0f 38 cd 00 \tsha256msg2 (%rax),%xmm0",}, -{{0x41, 0x0f, 0x38, 0xcd, 0x00, }, 5, 0, "", "", -"41 0f 38 cd 00 \tsha256msg2 (%r8),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x04, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"0f 38 cd 04 25 78 56 34 12 \tsha256msg2 0x12345678,%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x18, }, 4, 0, "", "", -"0f 38 cd 18 \tsha256msg2 (%rax),%xmm3",}, -{{0x0f, 0x38, 0xcd, 0x04, 0x01, }, 5, 0, "", "", -"0f 38 cd 04 01 \tsha256msg2 (%rcx,%rax,1),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x04, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"0f 38 cd 04 05 78 56 34 12 \tsha256msg2 0x12345678(,%rax,1),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x04, 0x08, }, 5, 0, "", "", -"0f 38 cd 04 08 \tsha256msg2 (%rax,%rcx,1),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x04, 0xc8, }, 5, 0, "", "", -"0f 38 cd 04 c8 \tsha256msg2 (%rax,%rcx,8),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x40, 0x12, }, 5, 0, "", "", -"0f 38 cd 40 12 \tsha256msg2 0x12(%rax),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x45, 0x12, }, 5, 0, "", "", -"0f 38 cd 45 12 \tsha256msg2 0x12(%rbp),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x44, 0x01, 0x12, }, 6, 0, "", "", -"0f 38 cd 44 01 12 \tsha256msg2 0x12(%rcx,%rax,1),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x44, 0x05, 0x12, }, 6, 0, "", "", -"0f 38 cd 44 05 12 \tsha256msg2 0x12(%rbp,%rax,1),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x44, 0x08, 0x12, }, 6, 0, "", "", -"0f 38 cd 44 08 12 \tsha256msg2 0x12(%rax,%rcx,1),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x44, 0xc8, 0x12, }, 6, 0, "", "", -"0f 38 cd 44 c8 12 \tsha256msg2 0x12(%rax,%rcx,8),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x80, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"0f 38 cd 80 78 56 34 12 \tsha256msg2 0x12345678(%rax),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x85, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"0f 38 cd 85 78 56 34 12 \tsha256msg2 0x12345678(%rbp),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x84, 0x01, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"0f 38 cd 84 01 78 56 34 12 \tsha256msg2 0x12345678(%rcx,%rax,1),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x84, 0x05, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"0f 38 cd 84 05 78 56 34 12 \tsha256msg2 0x12345678(%rbp,%rax,1),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x84, 0x08, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"0f 38 cd 84 08 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,1),%xmm0",}, -{{0x0f, 0x38, 0xcd, 0x84, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"0f 38 cd 84 c8 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,8),%xmm0",}, -{{0x44, 0x0f, 0x38, 0xcd, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", -"44 0f 38 cd bc c8 78 56 34 12 \tsha256msg2 0x12345678(%rax,%rcx,8),%xmm15",}, -{{0x66, 0x0f, 0xae, 0x38, }, 4, 0, "", "", -"66 0f ae 38 \tclflushopt (%rax)",}, -{{0x66, 0x41, 0x0f, 0xae, 0x38, }, 5, 0, "", "", -"66 41 0f ae 38 \tclflushopt (%r8)",}, -{{0x66, 0x0f, 0xae, 0x3c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f ae 3c 25 78 56 34 12 \tclflushopt 0x12345678",}, -{{0x66, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%rax,%rcx,8)",}, -{{0x66, 0x41, 0x0f, 0xae, 0xbc, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", -"66 41 0f ae bc c8 78 56 34 12 \tclflushopt 0x12345678(%r8,%rcx,8)",}, -{{0x0f, 0xae, 0x38, }, 3, 0, "", "", -"0f ae 38 \tclflush (%rax)",}, -{{0x41, 0x0f, 0xae, 0x38, }, 4, 0, "", "", -"41 0f ae 38 \tclflush (%r8)",}, -{{0x0f, 0xae, 0xf8, }, 3, 0, "", "", -"0f ae f8 \tsfence ",}, -{{0x66, 0x0f, 0xae, 0x30, }, 4, 0, "", "", -"66 0f ae 30 \tclwb (%rax)",}, -{{0x66, 0x41, 0x0f, 0xae, 0x30, }, 5, 0, "", "", -"66 41 0f ae 30 \tclwb (%r8)",}, -{{0x66, 0x0f, 0xae, 0x34, 0x25, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f ae 34 25 78 56 34 12 \tclwb 0x12345678",}, -{{0x66, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"66 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%rax,%rcx,8)",}, -{{0x66, 0x41, 0x0f, 0xae, 0xb4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 10, 0, "", "", -"66 41 0f ae b4 c8 78 56 34 12 \tclwb 0x12345678(%r8,%rcx,8)",}, -{{0x0f, 0xae, 0x30, }, 3, 0, "", "", -"0f ae 30 \txsaveopt (%rax)",}, -{{0x41, 0x0f, 0xae, 0x30, }, 4, 0, "", "", -"41 0f ae 30 \txsaveopt (%r8)",}, -{{0x0f, 0xae, 0xf0, }, 3, 0, "", "", -"0f ae f0 \tmfence ",}, -{{0x0f, 0xc7, 0x20, }, 3, 0, "", "", -"0f c7 20 \txsavec (%rax)",}, -{{0x41, 0x0f, 0xc7, 0x20, }, 4, 0, "", "", -"41 0f c7 20 \txsavec (%r8)",}, -{{0x0f, 0xc7, 0x24, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"0f c7 24 25 78 56 34 12 \txsavec 0x12345678",}, -{{0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%rax,%rcx,8)",}, -{{0x41, 0x0f, 0xc7, 0xa4, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"41 0f c7 a4 c8 78 56 34 12 \txsavec 0x12345678(%r8,%rcx,8)",}, -{{0x0f, 0xc7, 0x28, }, 3, 0, "", "", -"0f c7 28 \txsaves (%rax)",}, -{{0x41, 0x0f, 0xc7, 0x28, }, 4, 0, "", "", -"41 0f c7 28 \txsaves (%r8)",}, -{{0x0f, 0xc7, 0x2c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"0f c7 2c 25 78 56 34 12 \txsaves 0x12345678",}, -{{0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%rax,%rcx,8)",}, -{{0x41, 0x0f, 0xc7, 0xac, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"41 0f c7 ac c8 78 56 34 12 \txsaves 0x12345678(%r8,%rcx,8)",}, -{{0x0f, 0xc7, 0x18, }, 3, 0, "", "", -"0f c7 18 \txrstors (%rax)",}, -{{0x41, 0x0f, 0xc7, 0x18, }, 4, 0, "", "", -"41 0f c7 18 \txrstors (%r8)",}, -{{0x0f, 0xc7, 0x1c, 0x25, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"0f c7 1c 25 78 56 34 12 \txrstors 0x12345678",}, -{{0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 8, 0, "", "", -"0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%rax,%rcx,8)",}, -{{0x41, 0x0f, 0xc7, 0x9c, 0xc8, 0x78, 0x56, 0x34, 0x12, }, 9, 0, "", "", -"41 0f c7 9c c8 78 56 34 12 \txrstors 0x12345678(%r8,%rcx,8)",}, -{{0x66, 0x0f, 0xae, 0xf8, }, 4, 0, "", "", -"66 0f ae f8 \tpcommit ",}, diff --git a/tools/perf/tests/insn-x86-dat-src.c b/tools/perf/tests/insn-x86-dat-src.c deleted file mode 100644 index 41b1b1c62660..000000000000 --- a/tools/perf/tests/insn-x86-dat-src.c +++ /dev/null @@ -1,877 +0,0 @@ -/* - * This file contains instructions for testing by the test titled: - * - * "Test x86 instruction decoder - new instructions" - * - * Note that the 'Expecting' comment lines are consumed by the - * gen-insn-x86-dat.awk script and have the format: - * - * Expecting: - * - * If this file is changed, remember to run the gen-insn-x86-dat.sh - * script and commit the result. - * - * Refer to insn-x86.c for more details. - */ - -int main(void) -{ - /* Following line is a marker for the awk script - do not change */ - asm volatile("rdtsc"); /* Start here */ - -#ifdef __x86_64__ - - /* bndmk m64, bnd */ - - asm volatile("bndmk (%rax), %bnd0"); - asm volatile("bndmk (%r8), %bnd0"); - asm volatile("bndmk (0x12345678), %bnd0"); - asm volatile("bndmk (%rax), %bnd3"); - asm volatile("bndmk (%rcx,%rax,1), %bnd0"); - asm volatile("bndmk 0x12345678(,%rax,1), %bnd0"); - asm volatile("bndmk (%rax,%rcx,1), %bnd0"); - asm volatile("bndmk (%rax,%rcx,8), %bnd0"); - asm volatile("bndmk 0x12(%rax), %bnd0"); - asm volatile("bndmk 0x12(%rbp), %bnd0"); - asm volatile("bndmk 0x12(%rcx,%rax,1), %bnd0"); - asm volatile("bndmk 0x12(%rbp,%rax,1), %bnd0"); - asm volatile("bndmk 0x12(%rax,%rcx,1), %bnd0"); - asm volatile("bndmk 0x12(%rax,%rcx,8), %bnd0"); - asm volatile("bndmk 0x12345678(%rax), %bnd0"); - asm volatile("bndmk 0x12345678(%rbp), %bnd0"); - asm volatile("bndmk 0x12345678(%rcx,%rax,1), %bnd0"); - asm volatile("bndmk 0x12345678(%rbp,%rax,1), %bnd0"); - asm volatile("bndmk 0x12345678(%rax,%rcx,1), %bnd0"); - asm volatile("bndmk 0x12345678(%rax,%rcx,8), %bnd0"); - - /* bndcl r/m64, bnd */ - - asm volatile("bndcl (%rax), %bnd0"); - asm volatile("bndcl (%r8), %bnd0"); - asm volatile("bndcl (0x12345678), %bnd0"); - asm volatile("bndcl (%rax), %bnd3"); - asm volatile("bndcl (%rcx,%rax,1), %bnd0"); - asm volatile("bndcl 0x12345678(,%rax,1), %bnd0"); - asm volatile("bndcl (%rax,%rcx,1), %bnd0"); - asm volatile("bndcl (%rax,%rcx,8), %bnd0"); - asm volatile("bndcl 0x12(%rax), %bnd0"); - asm volatile("bndcl 0x12(%rbp), %bnd0"); - asm volatile("bndcl 0x12(%rcx,%rax,1), %bnd0"); - asm volatile("bndcl 0x12(%rbp,%rax,1), %bnd0"); - asm volatile("bndcl 0x12(%rax,%rcx,1), %bnd0"); - asm volatile("bndcl 0x12(%rax,%rcx,8), %bnd0"); - asm volatile("bndcl 0x12345678(%rax), %bnd0"); - asm volatile("bndcl 0x12345678(%rbp), %bnd0"); - asm volatile("bndcl 0x12345678(%rcx,%rax,1), %bnd0"); - asm volatile("bndcl 0x12345678(%rbp,%rax,1), %bnd0"); - asm volatile("bndcl 0x12345678(%rax,%rcx,1), %bnd0"); - asm volatile("bndcl 0x12345678(%rax,%rcx,8), %bnd0"); - asm volatile("bndcl %rax, %bnd0"); - - /* bndcu r/m64, bnd */ - - asm volatile("bndcu (%rax), %bnd0"); - asm volatile("bndcu (%r8), %bnd0"); - asm volatile("bndcu (0x12345678), %bnd0"); - asm volatile("bndcu (%rax), %bnd3"); - asm volatile("bndcu (%rcx,%rax,1), %bnd0"); - asm volatile("bndcu 0x12345678(,%rax,1), %bnd0"); - asm volatile("bndcu (%rax,%rcx,1), %bnd0"); - asm volatile("bndcu (%rax,%rcx,8), %bnd0"); - asm volatile("bndcu 0x12(%rax), %bnd0"); - asm volatile("bndcu 0x12(%rbp), %bnd0"); - asm volatile("bndcu 0x12(%rcx,%rax,1), %bnd0"); - asm volatile("bndcu 0x12(%rbp,%rax,1), %bnd0"); - asm volatile("bndcu 0x12(%rax,%rcx,1), %bnd0"); - asm volatile("bndcu 0x12(%rax,%rcx,8), %bnd0"); - asm volatile("bndcu 0x12345678(%rax), %bnd0"); - asm volatile("bndcu 0x12345678(%rbp), %bnd0"); - asm volatile("bndcu 0x12345678(%rcx,%rax,1), %bnd0"); - asm volatile("bndcu 0x12345678(%rbp,%rax,1), %bnd0"); - asm volatile("bndcu 0x12345678(%rax,%rcx,1), %bnd0"); - asm volatile("bndcu 0x12345678(%rax,%rcx,8), %bnd0"); - asm volatile("bndcu %rax, %bnd0"); - - /* bndcn r/m64, bnd */ - - asm volatile("bndcn (%rax), %bnd0"); - asm volatile("bndcn (%r8), %bnd0"); - asm volatile("bndcn (0x12345678), %bnd0"); - asm volatile("bndcn (%rax), %bnd3"); - asm volatile("bndcn (%rcx,%rax,1), %bnd0"); - asm volatile("bndcn 0x12345678(,%rax,1), %bnd0"); - asm volatile("bndcn (%rax,%rcx,1), %bnd0"); - asm volatile("bndcn (%rax,%rcx,8), %bnd0"); - asm volatile("bndcn 0x12(%rax), %bnd0"); - asm volatile("bndcn 0x12(%rbp), %bnd0"); - asm volatile("bndcn 0x12(%rcx,%rax,1), %bnd0"); - asm volatile("bndcn 0x12(%rbp,%rax,1), %bnd0"); - asm volatile("bndcn 0x12(%rax,%rcx,1), %bnd0"); - asm volatile("bndcn 0x12(%rax,%rcx,8), %bnd0"); - asm volatile("bndcn 0x12345678(%rax), %bnd0"); - asm volatile("bndcn 0x12345678(%rbp), %bnd0"); - asm volatile("bndcn 0x12345678(%rcx,%rax,1), %bnd0"); - asm volatile("bndcn 0x12345678(%rbp,%rax,1), %bnd0"); - asm volatile("bndcn 0x12345678(%rax,%rcx,1), %bnd0"); - asm volatile("bndcn 0x12345678(%rax,%rcx,8), %bnd0"); - asm volatile("bndcn %rax, %bnd0"); - - /* bndmov m128, bnd */ - - asm volatile("bndmov (%rax), %bnd0"); - asm volatile("bndmov (%r8), %bnd0"); - asm volatile("bndmov (0x12345678), %bnd0"); - asm volatile("bndmov (%rax), %bnd3"); - asm volatile("bndmov (%rcx,%rax,1), %bnd0"); - asm volatile("bndmov 0x12345678(,%rax,1), %bnd0"); - asm volatile("bndmov (%rax,%rcx,1), %bnd0"); - asm volatile("bndmov (%rax,%rcx,8), %bnd0"); - asm volatile("bndmov 0x12(%rax), %bnd0"); - asm volatile("bndmov 0x12(%rbp), %bnd0"); - asm volatile("bndmov 0x12(%rcx,%rax,1), %bnd0"); - asm volatile("bndmov 0x12(%rbp,%rax,1), %bnd0"); - asm volatile("bndmov 0x12(%rax,%rcx,1), %bnd0"); - asm volatile("bndmov 0x12(%rax,%rcx,8), %bnd0"); - asm volatile("bndmov 0x12345678(%rax), %bnd0"); - asm volatile("bndmov 0x12345678(%rbp), %bnd0"); - asm volatile("bndmov 0x12345678(%rcx,%rax,1), %bnd0"); - asm volatile("bndmov 0x12345678(%rbp,%rax,1), %bnd0"); - asm volatile("bndmov 0x12345678(%rax,%rcx,1), %bnd0"); - asm volatile("bndmov 0x12345678(%rax,%rcx,8), %bnd0"); - - /* bndmov bnd, m128 */ - - asm volatile("bndmov %bnd0, (%rax)"); - asm volatile("bndmov %bnd0, (%r8)"); - asm volatile("bndmov %bnd0, (0x12345678)"); - asm volatile("bndmov %bnd3, (%rax)"); - asm volatile("bndmov %bnd0, (%rcx,%rax,1)"); - asm volatile("bndmov %bnd0, 0x12345678(,%rax,1)"); - asm volatile("bndmov %bnd0, (%rax,%rcx,1)"); - asm volatile("bndmov %bnd0, (%rax,%rcx,8)"); - asm volatile("bndmov %bnd0, 0x12(%rax)"); - asm volatile("bndmov %bnd0, 0x12(%rbp)"); - asm volatile("bndmov %bnd0, 0x12(%rcx,%rax,1)"); - asm volatile("bndmov %bnd0, 0x12(%rbp,%rax,1)"); - asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,1)"); - asm volatile("bndmov %bnd0, 0x12(%rax,%rcx,8)"); - asm volatile("bndmov %bnd0, 0x12345678(%rax)"); - asm volatile("bndmov %bnd0, 0x12345678(%rbp)"); - asm volatile("bndmov %bnd0, 0x12345678(%rcx,%rax,1)"); - asm volatile("bndmov %bnd0, 0x12345678(%rbp,%rax,1)"); - asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,1)"); - asm volatile("bndmov %bnd0, 0x12345678(%rax,%rcx,8)"); - - /* bndmov bnd2, bnd1 */ - - asm volatile("bndmov %bnd0, %bnd1"); - asm volatile("bndmov %bnd1, %bnd0"); - - /* bndldx mib, bnd */ - - asm volatile("bndldx (%rax), %bnd0"); - asm volatile("bndldx (%r8), %bnd0"); - asm volatile("bndldx (0x12345678), %bnd0"); - asm volatile("bndldx (%rax), %bnd3"); - asm volatile("bndldx (%rcx,%rax,1), %bnd0"); - asm volatile("bndldx 0x12345678(,%rax,1), %bnd0"); - asm volatile("bndldx (%rax,%rcx,1), %bnd0"); - asm volatile("bndldx 0x12(%rax), %bnd0"); - asm volatile("bndldx 0x12(%rbp), %bnd0"); - asm volatile("bndldx 0x12(%rcx,%rax,1), %bnd0"); - asm volatile("bndldx 0x12(%rbp,%rax,1), %bnd0"); - asm volatile("bndldx 0x12(%rax,%rcx,1), %bnd0"); - asm volatile("bndldx 0x12345678(%rax), %bnd0"); - asm volatile("bndldx 0x12345678(%rbp), %bnd0"); - asm volatile("bndldx 0x12345678(%rcx,%rax,1), %bnd0"); - asm volatile("bndldx 0x12345678(%rbp,%rax,1), %bnd0"); - asm volatile("bndldx 0x12345678(%rax,%rcx,1), %bnd0"); - - /* bndstx bnd, mib */ - - asm volatile("bndstx %bnd0, (%rax)"); - asm volatile("bndstx %bnd0, (%r8)"); - asm volatile("bndstx %bnd0, (0x12345678)"); - asm volatile("bndstx %bnd3, (%rax)"); - asm volatile("bndstx %bnd0, (%rcx,%rax,1)"); - asm volatile("bndstx %bnd0, 0x12345678(,%rax,1)"); - asm volatile("bndstx %bnd0, (%rax,%rcx,1)"); - asm volatile("bndstx %bnd0, 0x12(%rax)"); - asm volatile("bndstx %bnd0, 0x12(%rbp)"); - asm volatile("bndstx %bnd0, 0x12(%rcx,%rax,1)"); - asm volatile("bndstx %bnd0, 0x12(%rbp,%rax,1)"); - asm volatile("bndstx %bnd0, 0x12(%rax,%rcx,1)"); - asm volatile("bndstx %bnd0, 0x12345678(%rax)"); - asm volatile("bndstx %bnd0, 0x12345678(%rbp)"); - asm volatile("bndstx %bnd0, 0x12345678(%rcx,%rax,1)"); - asm volatile("bndstx %bnd0, 0x12345678(%rbp,%rax,1)"); - asm volatile("bndstx %bnd0, 0x12345678(%rax,%rcx,1)"); - - /* bnd prefix on call, ret, jmp and all jcc */ - - asm volatile("bnd call label1"); /* Expecting: call unconditional 0 */ - asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */ - asm volatile("bnd ret"); /* Expecting: ret indirect 0 */ - asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */ - asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0 */ - asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */ - asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0 */ - - /* sha1rnds4 imm8, xmm2/m128, xmm1 */ - - asm volatile("sha1rnds4 $0x0, %xmm1, %xmm0"); - asm volatile("sha1rnds4 $0x91, %xmm7, %xmm2"); - asm volatile("sha1rnds4 $0x91, %xmm8, %xmm0"); - asm volatile("sha1rnds4 $0x91, %xmm7, %xmm8"); - asm volatile("sha1rnds4 $0x91, %xmm15, %xmm8"); - asm volatile("sha1rnds4 $0x91, (%rax), %xmm0"); - asm volatile("sha1rnds4 $0x91, (%r8), %xmm0"); - asm volatile("sha1rnds4 $0x91, (0x12345678), %xmm0"); - asm volatile("sha1rnds4 $0x91, (%rax), %xmm3"); - asm volatile("sha1rnds4 $0x91, (%rcx,%rax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(,%rax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, (%rax,%rcx,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, (%rax,%rcx,8), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%rax), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%rbp), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%rcx,%rax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%rbp,%rax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%rax,%rcx,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%rax,%rcx,8), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%rax), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%rbp), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%rcx,%rax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%rbp,%rax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,8), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%rax,%rcx,8), %xmm15"); - - /* sha1nexte xmm2/m128, xmm1 */ - - asm volatile("sha1nexte %xmm1, %xmm0"); - asm volatile("sha1nexte %xmm7, %xmm2"); - asm volatile("sha1nexte %xmm8, %xmm0"); - asm volatile("sha1nexte %xmm7, %xmm8"); - asm volatile("sha1nexte %xmm15, %xmm8"); - asm volatile("sha1nexte (%rax), %xmm0"); - asm volatile("sha1nexte (%r8), %xmm0"); - asm volatile("sha1nexte (0x12345678), %xmm0"); - asm volatile("sha1nexte (%rax), %xmm3"); - asm volatile("sha1nexte (%rcx,%rax,1), %xmm0"); - asm volatile("sha1nexte 0x12345678(,%rax,1), %xmm0"); - asm volatile("sha1nexte (%rax,%rcx,1), %xmm0"); - asm volatile("sha1nexte (%rax,%rcx,8), %xmm0"); - asm volatile("sha1nexte 0x12(%rax), %xmm0"); - asm volatile("sha1nexte 0x12(%rbp), %xmm0"); - asm volatile("sha1nexte 0x12(%rcx,%rax,1), %xmm0"); - asm volatile("sha1nexte 0x12(%rbp,%rax,1), %xmm0"); - asm volatile("sha1nexte 0x12(%rax,%rcx,1), %xmm0"); - asm volatile("sha1nexte 0x12(%rax,%rcx,8), %xmm0"); - asm volatile("sha1nexte 0x12345678(%rax), %xmm0"); - asm volatile("sha1nexte 0x12345678(%rbp), %xmm0"); - asm volatile("sha1nexte 0x12345678(%rcx,%rax,1), %xmm0"); - asm volatile("sha1nexte 0x12345678(%rbp,%rax,1), %xmm0"); - asm volatile("sha1nexte 0x12345678(%rax,%rcx,1), %xmm0"); - asm volatile("sha1nexte 0x12345678(%rax,%rcx,8), %xmm0"); - asm volatile("sha1nexte 0x12345678(%rax,%rcx,8), %xmm15"); - - /* sha1msg1 xmm2/m128, xmm1 */ - - asm volatile("sha1msg1 %xmm1, %xmm0"); - asm volatile("sha1msg1 %xmm7, %xmm2"); - asm volatile("sha1msg1 %xmm8, %xmm0"); - asm volatile("sha1msg1 %xmm7, %xmm8"); - asm volatile("sha1msg1 %xmm15, %xmm8"); - asm volatile("sha1msg1 (%rax), %xmm0"); - asm volatile("sha1msg1 (%r8), %xmm0"); - asm volatile("sha1msg1 (0x12345678), %xmm0"); - asm volatile("sha1msg1 (%rax), %xmm3"); - asm volatile("sha1msg1 (%rcx,%rax,1), %xmm0"); - asm volatile("sha1msg1 0x12345678(,%rax,1), %xmm0"); - asm volatile("sha1msg1 (%rax,%rcx,1), %xmm0"); - asm volatile("sha1msg1 (%rax,%rcx,8), %xmm0"); - asm volatile("sha1msg1 0x12(%rax), %xmm0"); - asm volatile("sha1msg1 0x12(%rbp), %xmm0"); - asm volatile("sha1msg1 0x12(%rcx,%rax,1), %xmm0"); - asm volatile("sha1msg1 0x12(%rbp,%rax,1), %xmm0"); - asm volatile("sha1msg1 0x12(%rax,%rcx,1), %xmm0"); - asm volatile("sha1msg1 0x12(%rax,%rcx,8), %xmm0"); - asm volatile("sha1msg1 0x12345678(%rax), %xmm0"); - asm volatile("sha1msg1 0x12345678(%rbp), %xmm0"); - asm volatile("sha1msg1 0x12345678(%rcx,%rax,1), %xmm0"); - asm volatile("sha1msg1 0x12345678(%rbp,%rax,1), %xmm0"); - asm volatile("sha1msg1 0x12345678(%rax,%rcx,1), %xmm0"); - asm volatile("sha1msg1 0x12345678(%rax,%rcx,8), %xmm0"); - asm volatile("sha1msg1 0x12345678(%rax,%rcx,8), %xmm15"); - - /* sha1msg2 xmm2/m128, xmm1 */ - - asm volatile("sha1msg2 %xmm1, %xmm0"); - asm volatile("sha1msg2 %xmm7, %xmm2"); - asm volatile("sha1msg2 %xmm8, %xmm0"); - asm volatile("sha1msg2 %xmm7, %xmm8"); - asm volatile("sha1msg2 %xmm15, %xmm8"); - asm volatile("sha1msg2 (%rax), %xmm0"); - asm volatile("sha1msg2 (%r8), %xmm0"); - asm volatile("sha1msg2 (0x12345678), %xmm0"); - asm volatile("sha1msg2 (%rax), %xmm3"); - asm volatile("sha1msg2 (%rcx,%rax,1), %xmm0"); - asm volatile("sha1msg2 0x12345678(,%rax,1), %xmm0"); - asm volatile("sha1msg2 (%rax,%rcx,1), %xmm0"); - asm volatile("sha1msg2 (%rax,%rcx,8), %xmm0"); - asm volatile("sha1msg2 0x12(%rax), %xmm0"); - asm volatile("sha1msg2 0x12(%rbp), %xmm0"); - asm volatile("sha1msg2 0x12(%rcx,%rax,1), %xmm0"); - asm volatile("sha1msg2 0x12(%rbp,%rax,1), %xmm0"); - asm volatile("sha1msg2 0x12(%rax,%rcx,1), %xmm0"); - asm volatile("sha1msg2 0x12(%rax,%rcx,8), %xmm0"); - asm volatile("sha1msg2 0x12345678(%rax), %xmm0"); - asm volatile("sha1msg2 0x12345678(%rbp), %xmm0"); - asm volatile("sha1msg2 0x12345678(%rcx,%rax,1), %xmm0"); - asm volatile("sha1msg2 0x12345678(%rbp,%rax,1), %xmm0"); - asm volatile("sha1msg2 0x12345678(%rax,%rcx,1), %xmm0"); - asm volatile("sha1msg2 0x12345678(%rax,%rcx,8), %xmm0"); - asm volatile("sha1msg2 0x12345678(%rax,%rcx,8), %xmm15"); - - /* sha256rnds2 , xmm2/m128, xmm1 */ - /* Note sha256rnds2 has an implicit operand 'xmm0' */ - - asm volatile("sha256rnds2 %xmm4, %xmm1"); - asm volatile("sha256rnds2 %xmm7, %xmm2"); - asm volatile("sha256rnds2 %xmm8, %xmm1"); - asm volatile("sha256rnds2 %xmm7, %xmm8"); - asm volatile("sha256rnds2 %xmm15, %xmm8"); - asm volatile("sha256rnds2 (%rax), %xmm1"); - asm volatile("sha256rnds2 (%r8), %xmm1"); - asm volatile("sha256rnds2 (0x12345678), %xmm1"); - asm volatile("sha256rnds2 (%rax), %xmm3"); - asm volatile("sha256rnds2 (%rcx,%rax,1), %xmm1"); - asm volatile("sha256rnds2 0x12345678(,%rax,1), %xmm1"); - asm volatile("sha256rnds2 (%rax,%rcx,1), %xmm1"); - asm volatile("sha256rnds2 (%rax,%rcx,8), %xmm1"); - asm volatile("sha256rnds2 0x12(%rax), %xmm1"); - asm volatile("sha256rnds2 0x12(%rbp), %xmm1"); - asm volatile("sha256rnds2 0x12(%rcx,%rax,1), %xmm1"); - asm volatile("sha256rnds2 0x12(%rbp,%rax,1), %xmm1"); - asm volatile("sha256rnds2 0x12(%rax,%rcx,1), %xmm1"); - asm volatile("sha256rnds2 0x12(%rax,%rcx,8), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%rax), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%rbp), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%rcx,%rax,1), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%rbp,%rax,1), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%rax,%rcx,1), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%rax,%rcx,8), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%rax,%rcx,8), %xmm15"); - - /* sha256msg1 xmm2/m128, xmm1 */ - - asm volatile("sha256msg1 %xmm1, %xmm0"); - asm volatile("sha256msg1 %xmm7, %xmm2"); - asm volatile("sha256msg1 %xmm8, %xmm0"); - asm volatile("sha256msg1 %xmm7, %xmm8"); - asm volatile("sha256msg1 %xmm15, %xmm8"); - asm volatile("sha256msg1 (%rax), %xmm0"); - asm volatile("sha256msg1 (%r8), %xmm0"); - asm volatile("sha256msg1 (0x12345678), %xmm0"); - asm volatile("sha256msg1 (%rax), %xmm3"); - asm volatile("sha256msg1 (%rcx,%rax,1), %xmm0"); - asm volatile("sha256msg1 0x12345678(,%rax,1), %xmm0"); - asm volatile("sha256msg1 (%rax,%rcx,1), %xmm0"); - asm volatile("sha256msg1 (%rax,%rcx,8), %xmm0"); - asm volatile("sha256msg1 0x12(%rax), %xmm0"); - asm volatile("sha256msg1 0x12(%rbp), %xmm0"); - asm volatile("sha256msg1 0x12(%rcx,%rax,1), %xmm0"); - asm volatile("sha256msg1 0x12(%rbp,%rax,1), %xmm0"); - asm volatile("sha256msg1 0x12(%rax,%rcx,1), %xmm0"); - asm volatile("sha256msg1 0x12(%rax,%rcx,8), %xmm0"); - asm volatile("sha256msg1 0x12345678(%rax), %xmm0"); - asm volatile("sha256msg1 0x12345678(%rbp), %xmm0"); - asm volatile("sha256msg1 0x12345678(%rcx,%rax,1), %xmm0"); - asm volatile("sha256msg1 0x12345678(%rbp,%rax,1), %xmm0"); - asm volatile("sha256msg1 0x12345678(%rax,%rcx,1), %xmm0"); - asm volatile("sha256msg1 0x12345678(%rax,%rcx,8), %xmm0"); - asm volatile("sha256msg1 0x12345678(%rax,%rcx,8), %xmm15"); - - /* sha256msg2 xmm2/m128, xmm1 */ - - asm volatile("sha256msg2 %xmm1, %xmm0"); - asm volatile("sha256msg2 %xmm7, %xmm2"); - asm volatile("sha256msg2 %xmm8, %xmm0"); - asm volatile("sha256msg2 %xmm7, %xmm8"); - asm volatile("sha256msg2 %xmm15, %xmm8"); - asm volatile("sha256msg2 (%rax), %xmm0"); - asm volatile("sha256msg2 (%r8), %xmm0"); - asm volatile("sha256msg2 (0x12345678), %xmm0"); - asm volatile("sha256msg2 (%rax), %xmm3"); - asm volatile("sha256msg2 (%rcx,%rax,1), %xmm0"); - asm volatile("sha256msg2 0x12345678(,%rax,1), %xmm0"); - asm volatile("sha256msg2 (%rax,%rcx,1), %xmm0"); - asm volatile("sha256msg2 (%rax,%rcx,8), %xmm0"); - asm volatile("sha256msg2 0x12(%rax), %xmm0"); - asm volatile("sha256msg2 0x12(%rbp), %xmm0"); - asm volatile("sha256msg2 0x12(%rcx,%rax,1), %xmm0"); - asm volatile("sha256msg2 0x12(%rbp,%rax,1), %xmm0"); - asm volatile("sha256msg2 0x12(%rax,%rcx,1), %xmm0"); - asm volatile("sha256msg2 0x12(%rax,%rcx,8), %xmm0"); - asm volatile("sha256msg2 0x12345678(%rax), %xmm0"); - asm volatile("sha256msg2 0x12345678(%rbp), %xmm0"); - asm volatile("sha256msg2 0x12345678(%rcx,%rax,1), %xmm0"); - asm volatile("sha256msg2 0x12345678(%rbp,%rax,1), %xmm0"); - asm volatile("sha256msg2 0x12345678(%rax,%rcx,1), %xmm0"); - asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm0"); - asm volatile("sha256msg2 0x12345678(%rax,%rcx,8), %xmm15"); - - /* clflushopt m8 */ - - asm volatile("clflushopt (%rax)"); - asm volatile("clflushopt (%r8)"); - asm volatile("clflushopt (0x12345678)"); - asm volatile("clflushopt 0x12345678(%rax,%rcx,8)"); - asm volatile("clflushopt 0x12345678(%r8,%rcx,8)"); - /* Also check instructions in the same group encoding as clflushopt */ - asm volatile("clflush (%rax)"); - asm volatile("clflush (%r8)"); - asm volatile("sfence"); - - /* clwb m8 */ - - asm volatile("clwb (%rax)"); - asm volatile("clwb (%r8)"); - asm volatile("clwb (0x12345678)"); - asm volatile("clwb 0x12345678(%rax,%rcx,8)"); - asm volatile("clwb 0x12345678(%r8,%rcx,8)"); - /* Also check instructions in the same group encoding as clwb */ - asm volatile("xsaveopt (%rax)"); - asm volatile("xsaveopt (%r8)"); - asm volatile("mfence"); - - /* xsavec mem */ - - asm volatile("xsavec (%rax)"); - asm volatile("xsavec (%r8)"); - asm volatile("xsavec (0x12345678)"); - asm volatile("xsavec 0x12345678(%rax,%rcx,8)"); - asm volatile("xsavec 0x12345678(%r8,%rcx,8)"); - - /* xsaves mem */ - - asm volatile("xsaves (%rax)"); - asm volatile("xsaves (%r8)"); - asm volatile("xsaves (0x12345678)"); - asm volatile("xsaves 0x12345678(%rax,%rcx,8)"); - asm volatile("xsaves 0x12345678(%r8,%rcx,8)"); - - /* xrstors mem */ - - asm volatile("xrstors (%rax)"); - asm volatile("xrstors (%r8)"); - asm volatile("xrstors (0x12345678)"); - asm volatile("xrstors 0x12345678(%rax,%rcx,8)"); - asm volatile("xrstors 0x12345678(%r8,%rcx,8)"); - -#else /* #ifdef __x86_64__ */ - - /* bndmk m32, bnd */ - - asm volatile("bndmk (%eax), %bnd0"); - asm volatile("bndmk (0x12345678), %bnd0"); - asm volatile("bndmk (%eax), %bnd3"); - asm volatile("bndmk (%ecx,%eax,1), %bnd0"); - asm volatile("bndmk 0x12345678(,%eax,1), %bnd0"); - asm volatile("bndmk (%eax,%ecx,1), %bnd0"); - asm volatile("bndmk (%eax,%ecx,8), %bnd0"); - asm volatile("bndmk 0x12(%eax), %bnd0"); - asm volatile("bndmk 0x12(%ebp), %bnd0"); - asm volatile("bndmk 0x12(%ecx,%eax,1), %bnd0"); - asm volatile("bndmk 0x12(%ebp,%eax,1), %bnd0"); - asm volatile("bndmk 0x12(%eax,%ecx,1), %bnd0"); - asm volatile("bndmk 0x12(%eax,%ecx,8), %bnd0"); - asm volatile("bndmk 0x12345678(%eax), %bnd0"); - asm volatile("bndmk 0x12345678(%ebp), %bnd0"); - asm volatile("bndmk 0x12345678(%ecx,%eax,1), %bnd0"); - asm volatile("bndmk 0x12345678(%ebp,%eax,1), %bnd0"); - asm volatile("bndmk 0x12345678(%eax,%ecx,1), %bnd0"); - asm volatile("bndmk 0x12345678(%eax,%ecx,8), %bnd0"); - - /* bndcl r/m32, bnd */ - - asm volatile("bndcl (%eax), %bnd0"); - asm volatile("bndcl (0x12345678), %bnd0"); - asm volatile("bndcl (%eax), %bnd3"); - asm volatile("bndcl (%ecx,%eax,1), %bnd0"); - asm volatile("bndcl 0x12345678(,%eax,1), %bnd0"); - asm volatile("bndcl (%eax,%ecx,1), %bnd0"); - asm volatile("bndcl (%eax,%ecx,8), %bnd0"); - asm volatile("bndcl 0x12(%eax), %bnd0"); - asm volatile("bndcl 0x12(%ebp), %bnd0"); - asm volatile("bndcl 0x12(%ecx,%eax,1), %bnd0"); - asm volatile("bndcl 0x12(%ebp,%eax,1), %bnd0"); - asm volatile("bndcl 0x12(%eax,%ecx,1), %bnd0"); - asm volatile("bndcl 0x12(%eax,%ecx,8), %bnd0"); - asm volatile("bndcl 0x12345678(%eax), %bnd0"); - asm volatile("bndcl 0x12345678(%ebp), %bnd0"); - asm volatile("bndcl 0x12345678(%ecx,%eax,1), %bnd0"); - asm volatile("bndcl 0x12345678(%ebp,%eax,1), %bnd0"); - asm volatile("bndcl 0x12345678(%eax,%ecx,1), %bnd0"); - asm volatile("bndcl 0x12345678(%eax,%ecx,8), %bnd0"); - asm volatile("bndcl %eax, %bnd0"); - - /* bndcu r/m32, bnd */ - - asm volatile("bndcu (%eax), %bnd0"); - asm volatile("bndcu (0x12345678), %bnd0"); - asm volatile("bndcu (%eax), %bnd3"); - asm volatile("bndcu (%ecx,%eax,1), %bnd0"); - asm volatile("bndcu 0x12345678(,%eax,1), %bnd0"); - asm volatile("bndcu (%eax,%ecx,1), %bnd0"); - asm volatile("bndcu (%eax,%ecx,8), %bnd0"); - asm volatile("bndcu 0x12(%eax), %bnd0"); - asm volatile("bndcu 0x12(%ebp), %bnd0"); - asm volatile("bndcu 0x12(%ecx,%eax,1), %bnd0"); - asm volatile("bndcu 0x12(%ebp,%eax,1), %bnd0"); - asm volatile("bndcu 0x12(%eax,%ecx,1), %bnd0"); - asm volatile("bndcu 0x12(%eax,%ecx,8), %bnd0"); - asm volatile("bndcu 0x12345678(%eax), %bnd0"); - asm volatile("bndcu 0x12345678(%ebp), %bnd0"); - asm volatile("bndcu 0x12345678(%ecx,%eax,1), %bnd0"); - asm volatile("bndcu 0x12345678(%ebp,%eax,1), %bnd0"); - asm volatile("bndcu 0x12345678(%eax,%ecx,1), %bnd0"); - asm volatile("bndcu 0x12345678(%eax,%ecx,8), %bnd0"); - asm volatile("bndcu %eax, %bnd0"); - - /* bndcn r/m32, bnd */ - - asm volatile("bndcn (%eax), %bnd0"); - asm volatile("bndcn (0x12345678), %bnd0"); - asm volatile("bndcn (%eax), %bnd3"); - asm volatile("bndcn (%ecx,%eax,1), %bnd0"); - asm volatile("bndcn 0x12345678(,%eax,1), %bnd0"); - asm volatile("bndcn (%eax,%ecx,1), %bnd0"); - asm volatile("bndcn (%eax,%ecx,8), %bnd0"); - asm volatile("bndcn 0x12(%eax), %bnd0"); - asm volatile("bndcn 0x12(%ebp), %bnd0"); - asm volatile("bndcn 0x12(%ecx,%eax,1), %bnd0"); - asm volatile("bndcn 0x12(%ebp,%eax,1), %bnd0"); - asm volatile("bndcn 0x12(%eax,%ecx,1), %bnd0"); - asm volatile("bndcn 0x12(%eax,%ecx,8), %bnd0"); - asm volatile("bndcn 0x12345678(%eax), %bnd0"); - asm volatile("bndcn 0x12345678(%ebp), %bnd0"); - asm volatile("bndcn 0x12345678(%ecx,%eax,1), %bnd0"); - asm volatile("bndcn 0x12345678(%ebp,%eax,1), %bnd0"); - asm volatile("bndcn 0x12345678(%eax,%ecx,1), %bnd0"); - asm volatile("bndcn 0x12345678(%eax,%ecx,8), %bnd0"); - asm volatile("bndcn %eax, %bnd0"); - - /* bndmov m64, bnd */ - - asm volatile("bndmov (%eax), %bnd0"); - asm volatile("bndmov (0x12345678), %bnd0"); - asm volatile("bndmov (%eax), %bnd3"); - asm volatile("bndmov (%ecx,%eax,1), %bnd0"); - asm volatile("bndmov 0x12345678(,%eax,1), %bnd0"); - asm volatile("bndmov (%eax,%ecx,1), %bnd0"); - asm volatile("bndmov (%eax,%ecx,8), %bnd0"); - asm volatile("bndmov 0x12(%eax), %bnd0"); - asm volatile("bndmov 0x12(%ebp), %bnd0"); - asm volatile("bndmov 0x12(%ecx,%eax,1), %bnd0"); - asm volatile("bndmov 0x12(%ebp,%eax,1), %bnd0"); - asm volatile("bndmov 0x12(%eax,%ecx,1), %bnd0"); - asm volatile("bndmov 0x12(%eax,%ecx,8), %bnd0"); - asm volatile("bndmov 0x12345678(%eax), %bnd0"); - asm volatile("bndmov 0x12345678(%ebp), %bnd0"); - asm volatile("bndmov 0x12345678(%ecx,%eax,1), %bnd0"); - asm volatile("bndmov 0x12345678(%ebp,%eax,1), %bnd0"); - asm volatile("bndmov 0x12345678(%eax,%ecx,1), %bnd0"); - asm volatile("bndmov 0x12345678(%eax,%ecx,8), %bnd0"); - - /* bndmov bnd, m64 */ - - asm volatile("bndmov %bnd0, (%eax)"); - asm volatile("bndmov %bnd0, (0x12345678)"); - asm volatile("bndmov %bnd3, (%eax)"); - asm volatile("bndmov %bnd0, (%ecx,%eax,1)"); - asm volatile("bndmov %bnd0, 0x12345678(,%eax,1)"); - asm volatile("bndmov %bnd0, (%eax,%ecx,1)"); - asm volatile("bndmov %bnd0, (%eax,%ecx,8)"); - asm volatile("bndmov %bnd0, 0x12(%eax)"); - asm volatile("bndmov %bnd0, 0x12(%ebp)"); - asm volatile("bndmov %bnd0, 0x12(%ecx,%eax,1)"); - asm volatile("bndmov %bnd0, 0x12(%ebp,%eax,1)"); - asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,1)"); - asm volatile("bndmov %bnd0, 0x12(%eax,%ecx,8)"); - asm volatile("bndmov %bnd0, 0x12345678(%eax)"); - asm volatile("bndmov %bnd0, 0x12345678(%ebp)"); - asm volatile("bndmov %bnd0, 0x12345678(%ecx,%eax,1)"); - asm volatile("bndmov %bnd0, 0x12345678(%ebp,%eax,1)"); - asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,1)"); - asm volatile("bndmov %bnd0, 0x12345678(%eax,%ecx,8)"); - - /* bndmov bnd2, bnd1 */ - - asm volatile("bndmov %bnd0, %bnd1"); - asm volatile("bndmov %bnd1, %bnd0"); - - /* bndldx mib, bnd */ - - asm volatile("bndldx (%eax), %bnd0"); - asm volatile("bndldx (0x12345678), %bnd0"); - asm volatile("bndldx (%eax), %bnd3"); - asm volatile("bndldx (%ecx,%eax,1), %bnd0"); - asm volatile("bndldx 0x12345678(,%eax,1), %bnd0"); - asm volatile("bndldx (%eax,%ecx,1), %bnd0"); - asm volatile("bndldx 0x12(%eax), %bnd0"); - asm volatile("bndldx 0x12(%ebp), %bnd0"); - asm volatile("bndldx 0x12(%ecx,%eax,1), %bnd0"); - asm volatile("bndldx 0x12(%ebp,%eax,1), %bnd0"); - asm volatile("bndldx 0x12(%eax,%ecx,1), %bnd0"); - asm volatile("bndldx 0x12345678(%eax), %bnd0"); - asm volatile("bndldx 0x12345678(%ebp), %bnd0"); - asm volatile("bndldx 0x12345678(%ecx,%eax,1), %bnd0"); - asm volatile("bndldx 0x12345678(%ebp,%eax,1), %bnd0"); - asm volatile("bndldx 0x12345678(%eax,%ecx,1), %bnd0"); - - /* bndstx bnd, mib */ - - asm volatile("bndstx %bnd0, (%eax)"); - asm volatile("bndstx %bnd0, (0x12345678)"); - asm volatile("bndstx %bnd3, (%eax)"); - asm volatile("bndstx %bnd0, (%ecx,%eax,1)"); - asm volatile("bndstx %bnd0, 0x12345678(,%eax,1)"); - asm volatile("bndstx %bnd0, (%eax,%ecx,1)"); - asm volatile("bndstx %bnd0, 0x12(%eax)"); - asm volatile("bndstx %bnd0, 0x12(%ebp)"); - asm volatile("bndstx %bnd0, 0x12(%ecx,%eax,1)"); - asm volatile("bndstx %bnd0, 0x12(%ebp,%eax,1)"); - asm volatile("bndstx %bnd0, 0x12(%eax,%ecx,1)"); - asm volatile("bndstx %bnd0, 0x12345678(%eax)"); - asm volatile("bndstx %bnd0, 0x12345678(%ebp)"); - asm volatile("bndstx %bnd0, 0x12345678(%ecx,%eax,1)"); - asm volatile("bndstx %bnd0, 0x12345678(%ebp,%eax,1)"); - asm volatile("bndstx %bnd0, 0x12345678(%eax,%ecx,1)"); - - /* bnd prefix on call, ret, jmp and all jcc */ - - asm volatile("bnd call label1"); /* Expecting: call unconditional 0xfffffffc */ - asm volatile("bnd call *(%eax)"); /* Expecting: call indirect 0 */ - asm volatile("bnd ret"); /* Expecting: ret indirect 0 */ - asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */ - asm volatile("bnd jmp label1"); /* Expecting: jmp unconditional 0xfffffffc */ - asm volatile("bnd jmp *(%ecx)"); /* Expecting: jmp indirect 0 */ - asm volatile("bnd jne label1"); /* Expecting: jcc conditional 0xfffffffc */ - - /* sha1rnds4 imm8, xmm2/m128, xmm1 */ - - asm volatile("sha1rnds4 $0x0, %xmm1, %xmm0"); - asm volatile("sha1rnds4 $0x91, %xmm7, %xmm2"); - asm volatile("sha1rnds4 $0x91, (%eax), %xmm0"); - asm volatile("sha1rnds4 $0x91, (0x12345678), %xmm0"); - asm volatile("sha1rnds4 $0x91, (%eax), %xmm3"); - asm volatile("sha1rnds4 $0x91, (%ecx,%eax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(,%eax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, (%eax,%ecx,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, (%eax,%ecx,8), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%eax), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%ebp), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%ecx,%eax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%ebp,%eax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%eax,%ecx,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12(%eax,%ecx,8), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%eax), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%ebp), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%ecx,%eax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%ebp,%eax,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%eax,%ecx,1), %xmm0"); - asm volatile("sha1rnds4 $0x91, 0x12345678(%eax,%ecx,8), %xmm0"); - - /* sha1nexte xmm2/m128, xmm1 */ - - asm volatile("sha1nexte %xmm1, %xmm0"); - asm volatile("sha1nexte %xmm7, %xmm2"); - asm volatile("sha1nexte (%eax), %xmm0"); - asm volatile("sha1nexte (0x12345678), %xmm0"); - asm volatile("sha1nexte (%eax), %xmm3"); - asm volatile("sha1nexte (%ecx,%eax,1), %xmm0"); - asm volatile("sha1nexte 0x12345678(,%eax,1), %xmm0"); - asm volatile("sha1nexte (%eax,%ecx,1), %xmm0"); - asm volatile("sha1nexte (%eax,%ecx,8), %xmm0"); - asm volatile("sha1nexte 0x12(%eax), %xmm0"); - asm volatile("sha1nexte 0x12(%ebp), %xmm0"); - asm volatile("sha1nexte 0x12(%ecx,%eax,1), %xmm0"); - asm volatile("sha1nexte 0x12(%ebp,%eax,1), %xmm0"); - asm volatile("sha1nexte 0x12(%eax,%ecx,1), %xmm0"); - asm volatile("sha1nexte 0x12(%eax,%ecx,8), %xmm0"); - asm volatile("sha1nexte 0x12345678(%eax), %xmm0"); - asm volatile("sha1nexte 0x12345678(%ebp), %xmm0"); - asm volatile("sha1nexte 0x12345678(%ecx,%eax,1), %xmm0"); - asm volatile("sha1nexte 0x12345678(%ebp,%eax,1), %xmm0"); - asm volatile("sha1nexte 0x12345678(%eax,%ecx,1), %xmm0"); - asm volatile("sha1nexte 0x12345678(%eax,%ecx,8), %xmm0"); - - /* sha1msg1 xmm2/m128, xmm1 */ - - asm volatile("sha1msg1 %xmm1, %xmm0"); - asm volatile("sha1msg1 %xmm7, %xmm2"); - asm volatile("sha1msg1 (%eax), %xmm0"); - asm volatile("sha1msg1 (0x12345678), %xmm0"); - asm volatile("sha1msg1 (%eax), %xmm3"); - asm volatile("sha1msg1 (%ecx,%eax,1), %xmm0"); - asm volatile("sha1msg1 0x12345678(,%eax,1), %xmm0"); - asm volatile("sha1msg1 (%eax,%ecx,1), %xmm0"); - asm volatile("sha1msg1 (%eax,%ecx,8), %xmm0"); - asm volatile("sha1msg1 0x12(%eax), %xmm0"); - asm volatile("sha1msg1 0x12(%ebp), %xmm0"); - asm volatile("sha1msg1 0x12(%ecx,%eax,1), %xmm0"); - asm volatile("sha1msg1 0x12(%ebp,%eax,1), %xmm0"); - asm volatile("sha1msg1 0x12(%eax,%ecx,1), %xmm0"); - asm volatile("sha1msg1 0x12(%eax,%ecx,8), %xmm0"); - asm volatile("sha1msg1 0x12345678(%eax), %xmm0"); - asm volatile("sha1msg1 0x12345678(%ebp), %xmm0"); - asm volatile("sha1msg1 0x12345678(%ecx,%eax,1), %xmm0"); - asm volatile("sha1msg1 0x12345678(%ebp,%eax,1), %xmm0"); - asm volatile("sha1msg1 0x12345678(%eax,%ecx,1), %xmm0"); - asm volatile("sha1msg1 0x12345678(%eax,%ecx,8), %xmm0"); - - /* sha1msg2 xmm2/m128, xmm1 */ - - asm volatile("sha1msg2 %xmm1, %xmm0"); - asm volatile("sha1msg2 %xmm7, %xmm2"); - asm volatile("sha1msg2 (%eax), %xmm0"); - asm volatile("sha1msg2 (0x12345678), %xmm0"); - asm volatile("sha1msg2 (%eax), %xmm3"); - asm volatile("sha1msg2 (%ecx,%eax,1), %xmm0"); - asm volatile("sha1msg2 0x12345678(,%eax,1), %xmm0"); - asm volatile("sha1msg2 (%eax,%ecx,1), %xmm0"); - asm volatile("sha1msg2 (%eax,%ecx,8), %xmm0"); - asm volatile("sha1msg2 0x12(%eax), %xmm0"); - asm volatile("sha1msg2 0x12(%ebp), %xmm0"); - asm volatile("sha1msg2 0x12(%ecx,%eax,1), %xmm0"); - asm volatile("sha1msg2 0x12(%ebp,%eax,1), %xmm0"); - asm volatile("sha1msg2 0x12(%eax,%ecx,1), %xmm0"); - asm volatile("sha1msg2 0x12(%eax,%ecx,8), %xmm0"); - asm volatile("sha1msg2 0x12345678(%eax), %xmm0"); - asm volatile("sha1msg2 0x12345678(%ebp), %xmm0"); - asm volatile("sha1msg2 0x12345678(%ecx,%eax,1), %xmm0"); - asm volatile("sha1msg2 0x12345678(%ebp,%eax,1), %xmm0"); - asm volatile("sha1msg2 0x12345678(%eax,%ecx,1), %xmm0"); - asm volatile("sha1msg2 0x12345678(%eax,%ecx,8), %xmm0"); - - /* sha256rnds2 , xmm2/m128, xmm1 */ - /* Note sha256rnds2 has an implicit operand 'xmm0' */ - - asm volatile("sha256rnds2 %xmm4, %xmm1"); - asm volatile("sha256rnds2 %xmm7, %xmm2"); - asm volatile("sha256rnds2 (%eax), %xmm1"); - asm volatile("sha256rnds2 (0x12345678), %xmm1"); - asm volatile("sha256rnds2 (%eax), %xmm3"); - asm volatile("sha256rnds2 (%ecx,%eax,1), %xmm1"); - asm volatile("sha256rnds2 0x12345678(,%eax,1), %xmm1"); - asm volatile("sha256rnds2 (%eax,%ecx,1), %xmm1"); - asm volatile("sha256rnds2 (%eax,%ecx,8), %xmm1"); - asm volatile("sha256rnds2 0x12(%eax), %xmm1"); - asm volatile("sha256rnds2 0x12(%ebp), %xmm1"); - asm volatile("sha256rnds2 0x12(%ecx,%eax,1), %xmm1"); - asm volatile("sha256rnds2 0x12(%ebp,%eax,1), %xmm1"); - asm volatile("sha256rnds2 0x12(%eax,%ecx,1), %xmm1"); - asm volatile("sha256rnds2 0x12(%eax,%ecx,8), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%eax), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%ebp), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%ecx,%eax,1), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%ebp,%eax,1), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%eax,%ecx,1), %xmm1"); - asm volatile("sha256rnds2 0x12345678(%eax,%ecx,8), %xmm1"); - - /* sha256msg1 xmm2/m128, xmm1 */ - - asm volatile("sha256msg1 %xmm1, %xmm0"); - asm volatile("sha256msg1 %xmm7, %xmm2"); - asm volatile("sha256msg1 (%eax), %xmm0"); - asm volatile("sha256msg1 (0x12345678), %xmm0"); - asm volatile("sha256msg1 (%eax), %xmm3"); - asm volatile("sha256msg1 (%ecx,%eax,1), %xmm0"); - asm volatile("sha256msg1 0x12345678(,%eax,1), %xmm0"); - asm volatile("sha256msg1 (%eax,%ecx,1), %xmm0"); - asm volatile("sha256msg1 (%eax,%ecx,8), %xmm0"); - asm volatile("sha256msg1 0x12(%eax), %xmm0"); - asm volatile("sha256msg1 0x12(%ebp), %xmm0"); - asm volatile("sha256msg1 0x12(%ecx,%eax,1), %xmm0"); - asm volatile("sha256msg1 0x12(%ebp,%eax,1), %xmm0"); - asm volatile("sha256msg1 0x12(%eax,%ecx,1), %xmm0"); - asm volatile("sha256msg1 0x12(%eax,%ecx,8), %xmm0"); - asm volatile("sha256msg1 0x12345678(%eax), %xmm0"); - asm volatile("sha256msg1 0x12345678(%ebp), %xmm0"); - asm volatile("sha256msg1 0x12345678(%ecx,%eax,1), %xmm0"); - asm volatile("sha256msg1 0x12345678(%ebp,%eax,1), %xmm0"); - asm volatile("sha256msg1 0x12345678(%eax,%ecx,1), %xmm0"); - asm volatile("sha256msg1 0x12345678(%eax,%ecx,8), %xmm0"); - - /* sha256msg2 xmm2/m128, xmm1 */ - - asm volatile("sha256msg2 %xmm1, %xmm0"); - asm volatile("sha256msg2 %xmm7, %xmm2"); - asm volatile("sha256msg2 (%eax), %xmm0"); - asm volatile("sha256msg2 (0x12345678), %xmm0"); - asm volatile("sha256msg2 (%eax), %xmm3"); - asm volatile("sha256msg2 (%ecx,%eax,1), %xmm0"); - asm volatile("sha256msg2 0x12345678(,%eax,1), %xmm0"); - asm volatile("sha256msg2 (%eax,%ecx,1), %xmm0"); - asm volatile("sha256msg2 (%eax,%ecx,8), %xmm0"); - asm volatile("sha256msg2 0x12(%eax), %xmm0"); - asm volatile("sha256msg2 0x12(%ebp), %xmm0"); - asm volatile("sha256msg2 0x12(%ecx,%eax,1), %xmm0"); - asm volatile("sha256msg2 0x12(%ebp,%eax,1), %xmm0"); - asm volatile("sha256msg2 0x12(%eax,%ecx,1), %xmm0"); - asm volatile("sha256msg2 0x12(%eax,%ecx,8), %xmm0"); - asm volatile("sha256msg2 0x12345678(%eax), %xmm0"); - asm volatile("sha256msg2 0x12345678(%ebp), %xmm0"); - asm volatile("sha256msg2 0x12345678(%ecx,%eax,1), %xmm0"); - asm volatile("sha256msg2 0x12345678(%ebp,%eax,1), %xmm0"); - asm volatile("sha256msg2 0x12345678(%eax,%ecx,1), %xmm0"); - asm volatile("sha256msg2 0x12345678(%eax,%ecx,8), %xmm0"); - - /* clflushopt m8 */ - - asm volatile("clflushopt (%eax)"); - asm volatile("clflushopt (0x12345678)"); - asm volatile("clflushopt 0x12345678(%eax,%ecx,8)"); - /* Also check instructions in the same group encoding as clflushopt */ - asm volatile("clflush (%eax)"); - asm volatile("sfence"); - - /* clwb m8 */ - - asm volatile("clwb (%eax)"); - asm volatile("clwb (0x12345678)"); - asm volatile("clwb 0x12345678(%eax,%ecx,8)"); - /* Also check instructions in the same group encoding as clwb */ - asm volatile("xsaveopt (%eax)"); - asm volatile("mfence"); - - /* xsavec mem */ - - asm volatile("xsavec (%eax)"); - asm volatile("xsavec (0x12345678)"); - asm volatile("xsavec 0x12345678(%eax,%ecx,8)"); - - /* xsaves mem */ - - asm volatile("xsaves (%eax)"); - asm volatile("xsaves (0x12345678)"); - asm volatile("xsaves 0x12345678(%eax,%ecx,8)"); - - /* xrstors mem */ - - asm volatile("xrstors (%eax)"); - asm volatile("xrstors (0x12345678)"); - asm volatile("xrstors 0x12345678(%eax,%ecx,8)"); - -#endif /* #ifndef __x86_64__ */ - - /* pcommit */ - - asm volatile("pcommit"); - - /* Following line is a marker for the awk script - do not change */ - asm volatile("rdtsc"); /* Stop here */ - - return 0; -} diff --git a/tools/perf/tests/insn-x86.c b/tools/perf/tests/insn-x86.c deleted file mode 100644 index 5c49eec81349..000000000000 --- a/tools/perf/tests/insn-x86.c +++ /dev/null @@ -1,184 +0,0 @@ -#include - -#include "debug.h" -#include "tests.h" - -#include "intel-pt-decoder/insn.h" -#include "intel-pt-decoder/intel-pt-insn-decoder.h" - -struct test_data { - u8 data[MAX_INSN_SIZE]; - int expected_length; - int expected_rel; - const char *expected_op_str; - const char *expected_branch_str; - const char *asm_rep; -}; - -struct test_data test_data_32[] = { -#include "insn-x86-dat-32.c" - {{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"}, - {{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"}, - {{0}, 0, 0, NULL, NULL, NULL}, -}; - -struct test_data test_data_64[] = { -#include "insn-x86-dat-64.c" - {{0x0f, 0x01, 0xee}, 3, 0, NULL, NULL, "0f 01 ee \trdpkru"}, - {{0x0f, 0x01, 0xef}, 3, 0, NULL, NULL, "0f 01 ef \twrpkru"}, - {{0}, 0, 0, NULL, NULL, NULL}, -}; - -static int get_op(const char *op_str) -{ - struct val_data { - const char *name; - int val; - } vals[] = { - {"other", INTEL_PT_OP_OTHER}, - {"call", INTEL_PT_OP_CALL}, - {"ret", INTEL_PT_OP_RET}, - {"jcc", INTEL_PT_OP_JCC}, - {"jmp", INTEL_PT_OP_JMP}, - {"loop", INTEL_PT_OP_LOOP}, - {"iret", INTEL_PT_OP_IRET}, - {"int", INTEL_PT_OP_INT}, - {"syscall", INTEL_PT_OP_SYSCALL}, - {"sysret", INTEL_PT_OP_SYSRET}, - {NULL, 0}, - }; - struct val_data *val; - - if (!op_str || !strlen(op_str)) - return 0; - - for (val = vals; val->name; val++) { - if (!strcmp(val->name, op_str)) - return val->val; - } - - pr_debug("Failed to get op\n"); - - return -1; -} - -static int get_branch(const char *branch_str) -{ - struct val_data { - const char *name; - int val; - } vals[] = { - {"no_branch", INTEL_PT_BR_NO_BRANCH}, - {"indirect", INTEL_PT_BR_INDIRECT}, - {"conditional", INTEL_PT_BR_CONDITIONAL}, - {"unconditional", INTEL_PT_BR_UNCONDITIONAL}, - {NULL, 0}, - }; - struct val_data *val; - - if (!branch_str || !strlen(branch_str)) - return 0; - - for (val = vals; val->name; val++) { - if (!strcmp(val->name, branch_str)) - return val->val; - } - - pr_debug("Failed to get branch\n"); - - return -1; -} - -static int test_data_item(struct test_data *dat, int x86_64) -{ - struct intel_pt_insn intel_pt_insn; - struct insn insn; - int op, branch; - - insn_init(&insn, dat->data, MAX_INSN_SIZE, x86_64); - insn_get_length(&insn); - - if (!insn_complete(&insn)) { - pr_debug("Failed to decode: %s\n", dat->asm_rep); - return -1; - } - - if (insn.length != dat->expected_length) { - pr_debug("Failed to decode length (%d vs expected %d): %s\n", - insn.length, dat->expected_length, dat->asm_rep); - return -1; - } - - op = get_op(dat->expected_op_str); - branch = get_branch(dat->expected_branch_str); - - if (intel_pt_get_insn(dat->data, MAX_INSN_SIZE, x86_64, &intel_pt_insn)) { - pr_debug("Intel PT failed to decode: %s\n", dat->asm_rep); - return -1; - } - - if ((int)intel_pt_insn.op != op) { - pr_debug("Failed to decode 'op' value (%d vs expected %d): %s\n", - intel_pt_insn.op, op, dat->asm_rep); - return -1; - } - - if ((int)intel_pt_insn.branch != branch) { - pr_debug("Failed to decode 'branch' value (%d vs expected %d): %s\n", - intel_pt_insn.branch, branch, dat->asm_rep); - return -1; - } - - if (intel_pt_insn.rel != dat->expected_rel) { - pr_debug("Failed to decode 'rel' value (%#x vs expected %#x): %s\n", - intel_pt_insn.rel, dat->expected_rel, dat->asm_rep); - return -1; - } - - pr_debug("Decoded ok: %s\n", dat->asm_rep); - - return 0; -} - -static int test_data_set(struct test_data *dat_set, int x86_64) -{ - struct test_data *dat; - int ret = 0; - - for (dat = dat_set; dat->expected_length; dat++) { - if (test_data_item(dat, x86_64)) - ret = -1; - } - - return ret; -} - -/** - * test__insn_x86 - test x86 instruction decoder - new instructions. - * - * This function implements a test that decodes a selection of instructions and - * checks the results. The Intel PT function that further categorizes - * instructions (i.e. intel_pt_get_insn()) is also checked. - * - * The instructions are originally in insn-x86-dat-src.c which has been - * processed by scripts gen-insn-x86-dat.sh and gen-insn-x86-dat.awk to produce - * insn-x86-dat-32.c and insn-x86-dat-64.c which are included into this program. - * i.e. to add new instructions to the test, edit insn-x86-dat-src.c, run the - * gen-insn-x86-dat.sh script, make perf, and then run the test. - * - * If the test passes %0 is returned, otherwise %-1 is returned. Use the - * verbose (-v) option to see all the instructions and whether or not they - * decoded successfuly. - */ -int test__insn_x86(void) -{ - int ret = 0; - - if (test_data_set(test_data_32, 0)) - ret = -1; - - if (test_data_set(test_data_64, 1)) - ret = -1; - - return ret; -} diff --git a/tools/perf/tests/perf-time-to-tsc.c b/tools/perf/tests/perf-time-to-tsc.c deleted file mode 100644 index 5f49484f1abc..000000000000 --- a/tools/perf/tests/perf-time-to-tsc.c +++ /dev/null @@ -1,162 +0,0 @@ -#include -#include -#include -#include - -#include "parse-events.h" -#include "evlist.h" -#include "evsel.h" -#include "thread_map.h" -#include "cpumap.h" -#include "tsc.h" -#include "tests.h" - -#define CHECK__(x) { \ - while ((x) < 0) { \ - pr_debug(#x " failed!\n"); \ - goto out_err; \ - } \ -} - -#define CHECK_NOT_NULL__(x) { \ - while ((x) == NULL) { \ - pr_debug(#x " failed!\n"); \ - goto out_err; \ - } \ -} - -/** - * test__perf_time_to_tsc - test converting perf time to TSC. - * - * This function implements a test that checks that the conversion of perf time - * to and from TSC is consistent with the order of events. If the test passes - * %0 is returned, otherwise %-1 is returned. If TSC conversion is not - * supported then then the test passes but " (not supported)" is printed. - */ -int test__perf_time_to_tsc(void) -{ - struct record_opts opts = { - .mmap_pages = UINT_MAX, - .user_freq = UINT_MAX, - .user_interval = ULLONG_MAX, - .freq = 4000, - .target = { - .uses_mmap = true, - }, - .sample_time = true, - }; - struct thread_map *threads = NULL; - struct cpu_map *cpus = NULL; - struct perf_evlist *evlist = NULL; - struct perf_evsel *evsel = NULL; - int err = -1, ret, i; - const char *comm1, *comm2; - struct perf_tsc_conversion tc; - struct perf_event_mmap_page *pc; - union perf_event *event; - u64 test_tsc, comm1_tsc, comm2_tsc; - u64 test_time, comm1_time = 0, comm2_time = 0; - - threads = thread_map__new(-1, getpid(), UINT_MAX); - CHECK_NOT_NULL__(threads); - - cpus = cpu_map__new(NULL); - CHECK_NOT_NULL__(cpus); - - evlist = perf_evlist__new(); - CHECK_NOT_NULL__(evlist); - - perf_evlist__set_maps(evlist, cpus, threads); - - CHECK__(parse_events(evlist, "cycles:u", NULL)); - - perf_evlist__config(evlist, &opts); - - evsel = perf_evlist__first(evlist); - - evsel->attr.comm = 1; - evsel->attr.disabled = 1; - evsel->attr.enable_on_exec = 0; - - CHECK__(perf_evlist__open(evlist)); - - CHECK__(perf_evlist__mmap(evlist, UINT_MAX, false)); - - pc = evlist->mmap[0].base; - ret = perf_read_tsc_conversion(pc, &tc); - if (ret) { - if (ret == -EOPNOTSUPP) { - fprintf(stderr, " (not supported)"); - return 0; - } - goto out_err; - } - - perf_evlist__enable(evlist); - - comm1 = "Test COMM 1"; - CHECK__(prctl(PR_SET_NAME, (unsigned long)comm1, 0, 0, 0)); - - test_tsc = rdtsc(); - - comm2 = "Test COMM 2"; - CHECK__(prctl(PR_SET_NAME, (unsigned long)comm2, 0, 0, 0)); - - perf_evlist__disable(evlist); - - for (i = 0; i < evlist->nr_mmaps; i++) { - while ((event = perf_evlist__mmap_read(evlist, i)) != NULL) { - struct perf_sample sample; - - if (event->header.type != PERF_RECORD_COMM || - (pid_t)event->comm.pid != getpid() || - (pid_t)event->comm.tid != getpid()) - goto next_event; - - if (strcmp(event->comm.comm, comm1) == 0) { - CHECK__(perf_evsel__parse_sample(evsel, event, - &sample)); - comm1_time = sample.time; - } - if (strcmp(event->comm.comm, comm2) == 0) { - CHECK__(perf_evsel__parse_sample(evsel, event, - &sample)); - comm2_time = sample.time; - } -next_event: - perf_evlist__mmap_consume(evlist, i); - } - } - - if (!comm1_time || !comm2_time) - goto out_err; - - test_time = tsc_to_perf_time(test_tsc, &tc); - comm1_tsc = perf_time_to_tsc(comm1_time, &tc); - comm2_tsc = perf_time_to_tsc(comm2_time, &tc); - - pr_debug("1st event perf time %"PRIu64" tsc %"PRIu64"\n", - comm1_time, comm1_tsc); - pr_debug("rdtsc time %"PRIu64" tsc %"PRIu64"\n", - test_time, test_tsc); - pr_debug("2nd event perf time %"PRIu64" tsc %"PRIu64"\n", - comm2_time, comm2_tsc); - - if (test_time <= comm1_time || - test_time >= comm2_time) - goto out_err; - - if (test_tsc <= comm1_tsc || - test_tsc >= comm2_tsc) - goto out_err; - - err = 0; - -out_err: - if (evlist) { - perf_evlist__disable(evlist); - perf_evlist__delete(evlist); - } - - return err; -} diff --git a/tools/perf/tests/rdpmc.c b/tools/perf/tests/rdpmc.c deleted file mode 100644 index d31f2c4d9f64..000000000000 --- a/tools/perf/tests/rdpmc.c +++ /dev/null @@ -1,177 +0,0 @@ -#include -#include -#include -#include -#include -#include "perf.h" -#include "debug.h" -#include "tests.h" -#include "cloexec.h" - -#if defined(__x86_64__) || defined(__i386__) - -static u64 rdpmc(unsigned int counter) -{ - unsigned int low, high; - - asm volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (counter)); - - return low | ((u64)high) << 32; -} - -static u64 rdtsc(void) -{ - unsigned int low, high; - - asm volatile("rdtsc" : "=a" (low), "=d" (high)); - - return low | ((u64)high) << 32; -} - -static u64 mmap_read_self(void *addr) -{ - struct perf_event_mmap_page *pc = addr; - u32 seq, idx, time_mult = 0, time_shift = 0; - u64 count, cyc = 0, time_offset = 0, enabled, running, delta; - - do { - seq = pc->lock; - barrier(); - - enabled = pc->time_enabled; - running = pc->time_running; - - if (enabled != running) { - cyc = rdtsc(); - time_mult = pc->time_mult; - time_shift = pc->time_shift; - time_offset = pc->time_offset; - } - - idx = pc->index; - count = pc->offset; - if (idx) - count += rdpmc(idx - 1); - - barrier(); - } while (pc->lock != seq); - - if (enabled != running) { - u64 quot, rem; - - quot = (cyc >> time_shift); - rem = cyc & ((1 << time_shift) - 1); - delta = time_offset + quot * time_mult + - ((rem * time_mult) >> time_shift); - - enabled += delta; - if (idx) - running += delta; - - quot = count / running; - rem = count % running; - count = quot * enabled + (rem * enabled) / running; - } - - return count; -} - -/* - * If the RDPMC instruction faults then signal this back to the test parent task: - */ -static void segfault_handler(int sig __maybe_unused, - siginfo_t *info __maybe_unused, - void *uc __maybe_unused) -{ - exit(-1); -} - -static int __test__rdpmc(void) -{ - volatile int tmp = 0; - u64 i, loops = 1000; - int n; - int fd; - void *addr; - struct perf_event_attr attr = { - .type = PERF_TYPE_HARDWARE, - .config = PERF_COUNT_HW_INSTRUCTIONS, - .exclude_kernel = 1, - }; - u64 delta_sum = 0; - struct sigaction sa; - char sbuf[STRERR_BUFSIZE]; - - sigfillset(&sa.sa_mask); - sa.sa_sigaction = segfault_handler; - sigaction(SIGSEGV, &sa, NULL); - - fd = sys_perf_event_open(&attr, 0, -1, -1, - perf_event_open_cloexec_flag()); - if (fd < 0) { - pr_err("Error: sys_perf_event_open() syscall returned " - "with %d (%s)\n", fd, - strerror_r(errno, sbuf, sizeof(sbuf))); - return -1; - } - - addr = mmap(NULL, page_size, PROT_READ, MAP_SHARED, fd, 0); - if (addr == (void *)(-1)) { - pr_err("Error: mmap() syscall returned with (%s)\n", - strerror_r(errno, sbuf, sizeof(sbuf))); - goto out_close; - } - - for (n = 0; n < 6; n++) { - u64 stamp, now, delta; - - stamp = mmap_read_self(addr); - - for (i = 0; i < loops; i++) - tmp++; - - now = mmap_read_self(addr); - loops *= 10; - - delta = now - stamp; - pr_debug("%14d: %14Lu\n", n, (long long)delta); - - delta_sum += delta; - } - - munmap(addr, page_size); - pr_debug(" "); -out_close: - close(fd); - - if (!delta_sum) - return -1; - - return 0; -} - -int test__rdpmc(void) -{ - int status = 0; - int wret = 0; - int ret; - int pid; - - pid = fork(); - if (pid < 0) - return -1; - - if (!pid) { - ret = __test__rdpmc(); - - exit(ret); - } - - wret = waitpid(pid, &status, 0); - if (wret < 0 || status) - return -1; - - return 0; -} - -#endif diff --git a/tools/perf/tests/tests.h b/tools/perf/tests/tests.h index b1cb1c081e3c..c80486969f83 100644 --- a/tools/perf/tests/tests.h +++ b/tools/perf/tests/tests.h @@ -35,7 +35,6 @@ int test__openat_syscall_event(void); int test__openat_syscall_event_on_all_cpus(void); int test__basic_mmap(void); int test__PERF_RECORD(void); -int test__rdpmc(void); int test__perf_evsel__roundtrip_name_test(void); int test__perf_evsel__tp_sched_test(void); int test__syscall_openat_tp_fields(void); @@ -51,7 +50,6 @@ int test__bp_signal(void); int test__bp_signal_overflow(void); int test__task_exit(void); int test__sw_clock_freq(void); -int test__perf_time_to_tsc(void); int test__code_reading(void); int test__sample_parsing(void); int test__keep_tracking(void); @@ -68,10 +66,9 @@ int test__fdarray__add(void); int test__kmod_path__parse(void); int test__thread_map(void); int test__llvm(void); -int test__insn_x86(void); int test_session_topology(void); -#if defined(__x86_64__) || defined(__i386__) || defined(__arm__) || defined(__aarch64__) +#if defined(__arm__) || defined(__aarch64__) #ifdef HAVE_DWARF_UNWIND_SUPPORT struct thread; struct perf_sample; -- cgit From 035827e9f2bd71a280f4eb58c65811d377ab2217 Mon Sep 17 00:00:00 2001 From: Matt Fleming Date: Mon, 5 Oct 2015 15:40:21 +0100 Subject: perf tests: Add Intel CQM test Peter reports that it's possible to trigger a WARN_ON_ONCE() in the Intel CQM code by combining a hardware event and an Intel CQM (software) event into a group. Unfortunately, the perf tools are not able to create this bundle and we need to manually construct a test case. For posterity, record Peter's proof of concept test case in tools/perf so that it presents a model for how we can perform architecture specific tests, or "arch tests", in perf in the future. The particular issue triggered in the test case is that when the counter for the hardware event overflows and triggers a PMI we'll read both the hardware event and the software event counters. Unfortunately, for CQM that involves performing an IPI to read the CQM event counters on all sockets, which in NMI context triggers the WARN_ON_ONCE(). Reported-by: Peter Zijlstra Signed-off-by: Matt Fleming Cc: Adrian Hunter Cc: Andi Kleen Cc: Fenghua Yu Cc: Jiri Olsa Cc: Kanaka Juvva Cc: Vikas Shivappa Cc: Vince Weaver Link: http://lkml.kernel.org/r/1437490509-15373-1-git-send-email-matt@codeblueprint.co.uk Link: http://lkml.kernel.org/n/tip-3p4ra0u8vzm7m289a1m799kf@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/arch/x86/include/arch-tests.h | 1 + tools/perf/arch/x86/tests/Build | 1 + tools/perf/arch/x86/tests/arch-tests.c | 4 + tools/perf/arch/x86/tests/intel-cqm.c | 124 +++++++++++++++++++++++++++++++ 4 files changed, 130 insertions(+) create mode 100644 tools/perf/arch/x86/tests/intel-cqm.c diff --git a/tools/perf/arch/x86/include/arch-tests.h b/tools/perf/arch/x86/include/arch-tests.h index 5927cf224325..7ed00f4b0908 100644 --- a/tools/perf/arch/x86/include/arch-tests.h +++ b/tools/perf/arch/x86/include/arch-tests.h @@ -5,6 +5,7 @@ int test__rdpmc(void); int test__perf_time_to_tsc(void); int test__insn_x86(void); +int test__intel_cqm_count_nmi_context(void); #ifdef HAVE_DWARF_UNWIND_SUPPORT struct thread; diff --git a/tools/perf/arch/x86/tests/Build b/tools/perf/arch/x86/tests/Build index 8e2c5a38c3b9..cbb7e978166b 100644 --- a/tools/perf/arch/x86/tests/Build +++ b/tools/perf/arch/x86/tests/Build @@ -5,3 +5,4 @@ libperf-y += arch-tests.o libperf-y += rdpmc.o libperf-y += perf-time-to-tsc.o libperf-$(CONFIG_AUXTRACE) += insn-x86.o +libperf-y += intel-cqm.o diff --git a/tools/perf/arch/x86/tests/arch-tests.c b/tools/perf/arch/x86/tests/arch-tests.c index d116c217af99..2218cb64f840 100644 --- a/tools/perf/arch/x86/tests/arch-tests.c +++ b/tools/perf/arch/x86/tests/arch-tests.c @@ -23,6 +23,10 @@ struct test arch_tests[] = { .func = test__insn_x86, }, #endif + { + .desc = "Test intel cqm nmi context read", + .func = test__intel_cqm_count_nmi_context, + }, { .func = NULL, }, diff --git a/tools/perf/arch/x86/tests/intel-cqm.c b/tools/perf/arch/x86/tests/intel-cqm.c new file mode 100644 index 000000000000..d28c1b6a3b54 --- /dev/null +++ b/tools/perf/arch/x86/tests/intel-cqm.c @@ -0,0 +1,124 @@ +#include "tests/tests.h" +#include "perf.h" +#include "cloexec.h" +#include "debug.h" +#include "evlist.h" +#include "evsel.h" +#include "arch-tests.h" + +#include +#include + +static pid_t spawn(void) +{ + pid_t pid; + + pid = fork(); + if (pid) + return pid; + + while(1); + sleep(5); + return 0; +} + +/* + * Create an event group that contains both a sampled hardware + * (cpu-cycles) and software (intel_cqm/llc_occupancy/) event. We then + * wait for the hardware perf counter to overflow and generate a PMI, + * which triggers an event read for both of the events in the group. + * + * Since reading Intel CQM event counters requires sending SMP IPIs, the + * CQM pmu needs to handle the above situation gracefully, and return + * the last read counter value to avoid triggering a WARN_ON_ONCE() in + * smp_call_function_many() caused by sending IPIs from NMI context. + */ +int test__intel_cqm_count_nmi_context(void) +{ + struct perf_evlist *evlist = NULL; + struct perf_evsel *evsel = NULL; + struct perf_event_attr pe; + int i, fd[2], flag, ret; + size_t mmap_len; + void *event; + pid_t pid; + int err = TEST_FAIL; + + flag = perf_event_open_cloexec_flag(); + + evlist = perf_evlist__new(); + if (!evlist) { + pr_debug("perf_evlist__new failed\n"); + return TEST_FAIL; + } + + ret = parse_events(evlist, "intel_cqm/llc_occupancy/", NULL); + if (ret) { + pr_debug("parse_events failed\n"); + err = TEST_SKIP; + goto out; + } + + evsel = perf_evlist__first(evlist); + if (!evsel) { + pr_debug("perf_evlist__first failed\n"); + goto out; + } + + memset(&pe, 0, sizeof(pe)); + pe.size = sizeof(pe); + + pe.type = PERF_TYPE_HARDWARE; + pe.config = PERF_COUNT_HW_CPU_CYCLES; + pe.read_format = PERF_FORMAT_GROUP; + + pe.sample_period = 128; + pe.sample_type = PERF_SAMPLE_IP | PERF_SAMPLE_READ; + + pid = spawn(); + + fd[0] = sys_perf_event_open(&pe, pid, -1, -1, flag); + if (fd[0] < 0) { + pr_debug("failed to open event\n"); + goto out; + } + + memset(&pe, 0, sizeof(pe)); + pe.size = sizeof(pe); + + pe.type = evsel->attr.type; + pe.config = evsel->attr.config; + + fd[1] = sys_perf_event_open(&pe, pid, -1, fd[0], flag); + if (fd[1] < 0) { + pr_debug("failed to open event\n"); + goto out; + } + + /* + * Pick a power-of-two number of pages + 1 for the meta-data + * page (struct perf_event_mmap_page). See tools/perf/design.txt. + */ + mmap_len = page_size * 65; + + event = mmap(NULL, mmap_len, PROT_READ, MAP_SHARED, fd[0], 0); + if (event == (void *)(-1)) { + pr_debug("failed to mmap %d\n", errno); + goto out; + } + + sleep(1); + + err = TEST_OK; + + munmap(event, mmap_len); + + for (i = 0; i < 2; i++) + close(fd[i]); + + kill(pid, SIGKILL); + wait(NULL); +out: + perf_evlist__delete(evlist); + return err; +} -- cgit From def02db0d662b0edd83f80e3c18f660fc414decb Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Mon, 5 Oct 2015 17:05:35 -0300 Subject: perf callchain: Switch default to 'graph,0.5,caller' Which is the most common default found in other similar tools. Requested-by: Ingo Molnar Cc: Adrian Hunter Cc: Borislav Petkov Cc: Chandler Carruth Cc: David Ahern Cc: Frederic Weisbecker Cc: Jiri Olsa Cc: Namhyung Kim Cc: Stephane Eranian Cc: Wang Nan Link: https://www.youtube.com/watch?v=nXaxk27zwlk Link: http://lkml.kernel.org/n/tip-v8lq36aispvdwgxdmt9p9jd9@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/Documentation/perf-report.txt | 2 +- tools/perf/builtin-report.c | 4 ++-- tools/perf/util/util.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tools/perf/Documentation/perf-report.txt b/tools/perf/Documentation/perf-report.txt index ce499035e6d8..e4fdeeb51123 100644 --- a/tools/perf/Documentation/perf-report.txt +++ b/tools/perf/Documentation/perf-report.txt @@ -192,7 +192,7 @@ OPTIONS when available. Usually more convenient to use --branch-history for this. - Default: fractal,0.5,callee,function. + Default: graph,0.5,caller --children:: Accumulate callchain of children to parent entry so that then can diff --git a/tools/perf/builtin-report.c b/tools/perf/builtin-report.c index b5623639f67d..3b23b25d1589 100644 --- a/tools/perf/builtin-report.c +++ b/tools/perf/builtin-report.c @@ -633,7 +633,7 @@ int cmd_report(int argc, const char **argv, const char *prefix __maybe_unused) bool has_br_stack = false; int branch_mode = -1; bool branch_call_mode = false; - char callchain_default_opt[] = "fractal,0.5,callee"; + char callchain_default_opt[] = "graph,0.5,caller"; const char * const report_usage[] = { "perf report []", NULL @@ -701,7 +701,7 @@ int cmd_report(int argc, const char **argv, const char *prefix __maybe_unused) "Only display entries with parent-match"), OPT_CALLBACK_DEFAULT('g', "call-graph", &report, "output_type,min_percent[,print_limit],call_order[,branch]", "Display callchains using output_type (graph, flat, fractal, or none) , min percent threshold, optional print limit, callchain order, key (function or address), add branches. " - "Default: fractal,0.5,callee,function", &report_parse_callchain_opt, callchain_default_opt), + "Default: graph,0.5,caller", &report_parse_callchain_opt, callchain_default_opt), OPT_BOOLEAN(0, "children", &symbol_conf.cumulate_callchain, "Accumulate callchains of children and show total overhead as well"), OPT_INTEGER(0, "max-stack", &report.max_stack, diff --git a/tools/perf/util/util.c b/tools/perf/util/util.c index ce465b259e52..c1bf9ff210b0 100644 --- a/tools/perf/util/util.c +++ b/tools/perf/util/util.c @@ -17,9 +17,9 @@ #include "callchain.h" struct callchain_param callchain_param = { - .mode = CHAIN_GRAPH_REL, + .mode = CHAIN_GRAPH_ABS, .min_percent = 0.5, - .order = ORDER_CALLEE, + .order = ORDER_CALLER, .key = CCKEY_FUNCTION }; -- cgit From faae6f690eecb82b6d9d9f2112f5b51ac37d4acb Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 11 Aug 2015 17:14:40 -0300 Subject: perf ui browser: Optional horizontal scrolling key binding If the classes derived from ui_browser want to do some sort of horizontal scrolling, they have just to set ui_browser->columns to the number of columns available. Those columns can be the number of characters on the screen, if what is desired is to scroll character by character, or the number of columns in a spreadsheet like table. This is what the hist_browser will do, skipping ui_browser->horiz_scroll columns when rendering each of its lines. Cc: Adrian Hunter Cc: Borislav Petkov Cc: David Ahern Cc: Frederic Weisbecker Cc: Jiri Olsa Cc: Namhyung Kim Cc: Stephane Eranian Link: http://lkml.kernel.org/n/tip-q6a22bpmpgcr1awgzrmd4jrs@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/ui/browser.c | 14 ++++++++++++++ tools/perf/ui/browser.h | 2 +- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/tools/perf/ui/browser.c b/tools/perf/ui/browser.c index c6c7e5189214..e9703c0829f1 100644 --- a/tools/perf/ui/browser.c +++ b/tools/perf/ui/browser.c @@ -393,6 +393,7 @@ int ui_browser__run(struct ui_browser *browser, int delay_secs) if (browser->use_navkeypressed && !browser->navkeypressed) { if (key == K_DOWN || key == K_UP || + (browser->columns && (key == K_LEFT || key == K_RIGHT)) || key == K_PGDN || key == K_PGUP || key == K_HOME || key == K_END || key == ' ') { @@ -421,6 +422,18 @@ int ui_browser__run(struct ui_browser *browser, int delay_secs) browser->seek(browser, -1, SEEK_CUR); } break; + case K_RIGHT: + if (!browser->columns) + goto out; + if (browser->horiz_scroll < browser->columns - 1) + ++browser->horiz_scroll; + break; + case K_LEFT: + if (!browser->columns) + goto out; + if (browser->horiz_scroll != 0) + --browser->horiz_scroll; + break; case K_PGDN: case ' ': if (browser->top_idx + browser->rows > browser->nr_entries - 1) @@ -459,6 +472,7 @@ int ui_browser__run(struct ui_browser *browser, int delay_secs) browser->seek(browser, -offset, SEEK_END); break; default: + out: return key; } } diff --git a/tools/perf/ui/browser.h b/tools/perf/ui/browser.h index f3cef564de02..01781de59532 100644 --- a/tools/perf/ui/browser.h +++ b/tools/perf/ui/browser.h @@ -14,7 +14,7 @@ struct ui_browser { u64 index, top_idx; void *top, *entries; - u16 y, x, width, height, rows; + u16 y, x, width, height, rows, columns, horiz_scroll; int current_color; void *priv; const char *title; -- cgit From c6c3c02dea4034431110923ffd8e296ebfbdbe1b Mon Sep 17 00:00:00 2001 From: Arnaldo Carvalho de Melo Date: Tue, 11 Aug 2015 17:22:43 -0300 Subject: perf hists browser: Implement horizontal scrolling Do it using the recently introduced ui_brower scrolling mode, setting ui_browser.columns to the number of sort columns and then, when rendering each line, skipping as many initial columns as the user pressed the right arrow. As the user presses the left arrow, the ui_browser code will remove the scrolling counter and the left scrolling takes place. The right arrow key was an alias for ENTER, so people used to press it may get a bit annoyed at first, sorry! Ditto for ESC and the left key. Callchains can be left as is or we can, when rendering the Symbol column, store the at what position on the screen it is and then using ui_browser__gotorc() to print it from there, i.e. the callchain would move around with the symbol. Leaving it as is, i.e. at a fixed position, close to the left, saves precious screen real state for it, so I'm inclined to leave it as is now. Cc: Adrian Hunter Cc: Borislav Petkov Cc: Chandler Carruth Cc: David Ahern Cc: Frederic Weisbecker Cc: Jiri Olsa Cc: Namhyung Kim Cc: Stephane Eranian Link: http://lkml.kernel.org/n/tip-ccqq9sabgfge5dwbqjwh71ij@git.kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/ui/browsers/hists.c | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/tools/perf/ui/browsers/hists.c b/tools/perf/ui/browsers/hists.c index a4e9b370c037..9b7346a881cf 100644 --- a/tools/perf/ui/browsers/hists.c +++ b/tools/perf/ui/browsers/hists.c @@ -784,11 +784,12 @@ static int hist_browser__show_entry(struct hist_browser *browser, .size = sizeof(s), .ptr = &arg, }; + int column = 0; hist_browser__gotorc(browser, row, 0); perf_hpp__for_each_format(fmt) { - if (perf_hpp__should_skip(fmt)) + if (perf_hpp__should_skip(fmt) || column++ < browser->b.horiz_scroll) continue; if (current_entry && browser->b.navkeypressed) { @@ -861,14 +862,16 @@ static int advance_hpp_check(struct perf_hpp *hpp, int inc) return hpp->size <= 0; } -static int hists__scnprintf_headers(char *buf, size_t size, struct hists *hists) +static int hists_browser__scnprintf_headers(struct hist_browser *browser, char *buf, size_t size) { + struct hists *hists = browser->hists; struct perf_hpp dummy_hpp = { .buf = buf, .size = size, }; struct perf_hpp_fmt *fmt; size_t ret = 0; + int column = 0; if (symbol_conf.use_callchain) { ret = scnprintf(buf, size, " "); @@ -877,7 +880,7 @@ static int hists__scnprintf_headers(char *buf, size_t size, struct hists *hists) } perf_hpp__for_each_format(fmt) { - if (perf_hpp__should_skip(fmt)) + if (perf_hpp__should_skip(fmt) || column++ < browser->b.horiz_scroll) continue; ret = fmt->header(fmt, &dummy_hpp, hists_to_evsel(hists)); @@ -896,7 +899,7 @@ static void hist_browser__show_headers(struct hist_browser *browser) { char headers[1024]; - hists__scnprintf_headers(headers, sizeof(headers), browser->hists); + hists_browser__scnprintf_headers(browser, headers, sizeof(headers)); ui_browser__gotorc(&browser->b, 0, 0); ui_browser__set_color(&browser->b, HE_COLORSET_ROOT); ui_browser__write_nstring(&browser->b, headers, browser->b.width + 1); @@ -1806,8 +1809,17 @@ static int perf_evsel__hists_browse(struct perf_evsel *evsel, int nr_events, memset(options, 0, sizeof(options)); memset(actions, 0, sizeof(actions)); - perf_hpp__for_each_format(fmt) + perf_hpp__for_each_format(fmt) { perf_hpp__reset_width(fmt, hists); + /* + * This is done just once, and activates the horizontal scrolling + * code in the ui_browser code, it would be better to have a the + * counter in the perf_hpp code, but I couldn't find doing it here + * works, FIXME by setting this in hist_browser__new, for now, be + * clever 8-) + */ + ++browser->b.columns; + } if (symbol_conf.col_width_list_str) perf_hpp__set_user_width(symbol_conf.col_width_list_str); -- cgit From 27bf90bf0690f55c3679bcc4c325823cf1cfd19d Mon Sep 17 00:00:00 2001 From: Jiri Olsa Date: Mon, 5 Oct 2015 21:31:17 +0200 Subject: perf tools: Fail properly in case pattern matching fails to find tracepoint Currently we dont fail properly when pattern matching fails to find any tracepoint. Current behaviour: $ perf record -e 'sched:krava*' sleep 1 WARNING: event parser found nothinginvalid or unsupported event: 'sched:krava*' Run 'perf list' for a list of valid events usage: perf record [] [] or: perf record [] -- [] This patch change: $ perf record -e 'sched:krava*' sleep 1 event syntax error: 'sched:krava*' \___ unknown tracepoint Error: File /sys/kernel/debug/tracing/events/sched/krava* not found. Hint: Perhaps this kernel misses some CONFIG_ setting to enable this feature?. Run 'perf list' for a list of valid events usage: perf record [] [] or: perf record [] -- [] Reported-by: Daniel Bristot de Oliveira Signed-off-by: Jiri Olsa Tested-by: Arnaldo Carvalho de Melo Cc: David Ahern Cc: Namhyung Kim Cc: Peter Zijlstra Link: http://lkml.kernel.org/r/1444073477-3181-1-git-send-email-jolsa@kernel.org Signed-off-by: Arnaldo Carvalho de Melo --- tools/perf/util/parse-events.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 3ed8bf175163..991bbd469bea 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -449,7 +449,7 @@ static int add_tracepoint_multi_event(struct list_head *list, int *idx, char evt_path[MAXPATHLEN]; struct dirent *evt_ent; DIR *evt_dir; - int ret = 0; + int ret = 0, found = 0; snprintf(evt_path, MAXPATHLEN, "%s/%s", tracing_events_path, sys_name); evt_dir = opendir(evt_path); @@ -468,10 +468,17 @@ static int add_tracepoint_multi_event(struct list_head *list, int *idx, if (!strglobmatch(evt_ent->d_name, evt_name)) continue; + found++; + ret = add_tracepoint(list, idx, sys_name, evt_ent->d_name, err, head_config); } + if (!found) { + tracepoint_error(err, ENOENT, sys_name, evt_name); + ret = -1; + } + closedir(evt_dir); return ret; } -- cgit