From b7a791b26409a5853ddd72e85c89214c818ba268 Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Mon, 1 Apr 2024 16:39:51 +0530 Subject: dt-bindings: PCI: ti,j721e-pci-host: Add device-id for TI's J784S4 SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add the device-id of 0xb012 for the PCIe controller on the J784S4 SoC as described in the CTRL_MMR_PCI_DEVICE_ID register's PCI_DEVICE_ID_DEVICE_ID field. The Register descriptions and the Technical Reference Manual for J784S4 SoC can be found at: https://www.ti.com/lit/zip/spruj52 Link: https://lore.kernel.org/linux-pci/20240401110951.3816291-1-s-vadapalli@ti.com Signed-off-by: Siddharth Vadapalli Signed-off-by: Krzysztof Wilczyński Acked-by: Rob Herring --- Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index b7a534cef24d..0b1f21570ed0 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -68,6 +68,7 @@ properties: - 0xb00d - 0xb00f - 0xb010 + - 0xb012 - 0xb013 msi-map: true -- cgit From 78d212851f0e56b7d7083c4d5014aa7fa8b77e20 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 1 Feb 2024 16:52:01 +0100 Subject: dt-bindings: PCI: rcar-pci-host: Add missing IOMMU properties MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit make dtbs_check: arch/arm64/boot/dts/renesas/r8a77951-salvator-xs.dtb: pcie@fe000000: Unevaluated properties are not allowed ('iommu-map', 'iommu-map-mask' were unexpected) from schema $id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml# Fix this by adding the missing IOMMU-related properties. [kwilczynski: added missing Fixes: tag] Fixes: 0d69ce3c2c63 ("dt-bindings: PCI: rcar-pci-host: Convert bindings to json-schema") Link: https://lore.kernel.org/linux-pci/babc878a93cb6461a5d39331f8ecfa654dfda921.1706802597.git.geert+renesas@glider.be Signed-off-by: Geert Uytterhoeven Signed-off-by: Krzysztof Wilczyński Acked-by: Conor Dooley --- Documentation/devicetree/bindings/pci/rcar-pci-host.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml index b6a7cb32f61e..835b6db00c27 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml @@ -77,6 +77,9 @@ properties: vpcie12v-supply: description: The 12v regulator to use for PCIe. + iommu-map: true + iommu-map-mask: true + required: - compatible - reg -- cgit From 01fec70206d48891b76ee8a3a4bfbd331543c18a Mon Sep 17 00:00:00 2001 From: Siddharth Vadapalli Date: Wed, 24 Jan 2024 17:59:36 +0530 Subject: dt-bindings: PCI: ti,j721e-pci-host: Add support for J722S SoC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TI's J722S SoC has one instance of a Gen3 Single-Lane PCIe controller. The controller on J722S SoC is similar to the one present on TI's AM64 SoC, with the difference being that the controller on AM64 SoC supports up to Gen2 link speed while the one on J722S SoC supports Gen3 link speed. Update the bindings with a new compatible for J722S SoC. Technical Reference Manual of J722S SoC: https://www.ti.com/lit/zip/sprujb3 Link: https://lore.kernel.org/linux-pci/20240124122936.816142-1-s-vadapalli@ti.com Signed-off-by: Siddharth Vadapalli Signed-off-by: Krzysztof Wilczyński Acked-by: Conor Dooley --- Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 0b1f21570ed0..15a2658ceeef 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -23,6 +23,10 @@ properties: items: - const: ti,j7200-pcie-host - const: ti,j721e-pcie-host + - description: PCIe controller in J722S + items: + - const: ti,j722s-pcie-host + - const: ti,j721e-pcie-host reg: maxItems: 4 -- cgit From 64e098b59b8af5376c0b4544d6729625a692d400 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 15 Feb 2024 13:55:56 +0100 Subject: dt-bindings: PCI: ti,am65: Fix remaining binding warnings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds the missing num-viewport, phys and phy-name properties to the schema. Based on driver code, num-viewport is required for the root complex, phys are optional. Their number corresponds to the number of lanes. The AM65x supports up to 2 lanes. Link: https://lore.kernel.org/linux-pci/8032b018-c870-403a-9dd9-63440de1da07@siemens.com Signed-off-by: Jan Kiszka Signed-off-by: Krzysztof Wilczyński Reviewed-by: Rob Herring --- .../devicetree/bindings/pci/ti,am65-pci-host.yaml | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index a20dccbafd94..c54d4e57d089 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -55,6 +55,20 @@ properties: dma-coherent: true + num-viewport: + $ref: /schemas/types.yaml#/definitions/uint32 + + phys: + description: per-lane PHYs + minItems: 1 + maxItems: 2 + + phy-names: + minItems: 1 + maxItems: 2 + items: + pattern: '^pcie-phy[0-1]$' + required: - compatible - reg @@ -74,6 +88,7 @@ then: - dma-coherent - power-domains - msi-map + - num-viewport unevaluatedProperties: false @@ -81,6 +96,7 @@ examples: - | #include #include + #include #include pcie0_rc: pcie@5500000 { @@ -98,9 +114,13 @@ examples: ti,syscon-pcie-id = <&scm_conf 0x0210>; ti,syscon-pcie-mode = <&scm_conf 0x4060>; bus-range = <0x0 0xff>; + num-viewport = <16>; max-link-speed = <2>; dma-coherent; interrupts = ; msi-map = <0x0 &gic_its 0x0 0x10000>; device_type = "pci"; + num-lanes = <1>; + phys = <&serdes0 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; }; -- cgit From 51ef0538d4e1ca959b8eb7e78376cab2e94021cb Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 13 Apr 2024 17:16:14 +0200 Subject: dt-bindings: PCI: cdns,cdns-pcie-host: Drop redundant msi-parent and pci-bus.yaml MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The binding reference common cdns-pcie-host.yaml, which already defines msi-parent and has a reference to pci-bus.yaml schema. Drop redundant pieces here to make it a bit smaller. Link: https://lore.kernel.org/linux-pci/20240413151617.35630-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Wilczyński Reviewed-by: Geert Uytterhoeven Acked-by: Rob Herring Acked-by: Sergio Paracuellos --- Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml | 3 --- 1 file changed, 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml index bc3c48f60fff..a8190d9b100f 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-host.yaml @@ -10,7 +10,6 @@ maintainers: - Tom Joseph allOf: - - $ref: /schemas/pci/pci-bus.yaml# - $ref: cdns-pcie-host.yaml# properties: @@ -25,8 +24,6 @@ properties: - const: reg - const: cfg - msi-parent: true - required: - reg - reg-names -- cgit From 36fbed38549c9f9b28f750323ede6bb87413af6e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 13 Apr 2024 17:16:15 +0200 Subject: dt-bindings: PCI: mediatek,mt7621: Add missing child node reg MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit MT7621 PCI host bridge has children which are PCI root ports. The children have "reg" property, but do not explicitly define it. Instead they rely on pci-bus.yaml schema, but that one has "reg" without any constraints. Define the "reg" for the children, so the binding will be more specific and later will allow dropping reference to deprecated pci-bus.yaml schema. Link: https://lore.kernel.org/linux-pci/20240413151617.35630-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Wilczyński Reviewed-by: AngeloGioacchino Del Regno Acked-by: Rob Herring Acked-by: Sergio Paracuellos --- Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml index e63e6458cea8..61d027239910 100644 --- a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml @@ -36,6 +36,9 @@ patternProperties: $ref: /schemas/pci/pci-bus.yaml# properties: + reg: + maxItems: 1 + resets: maxItems: 1 -- cgit From 5db62b7d3c375b8d7926fbc1bb1c2ad9d777fd76 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 13 Apr 2024 17:16:16 +0200 Subject: dt-bindings: PCI: host-bridges: Switch from deprecated pci-bus.yaml MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dtschema package with core schemas deprecated pci-bus.yaml schema in favor of pci-host-bridge.yaml. Update all bindings to use the latter one. The difference between pci-bus.yaml and pci-host-bridge.yaml is only in lack of "reg" property defined by the latter, which should not have any effect here, because all these bindings define the "reg". The change is therefore quite trivial, however it requires dtschema package v2024.02 or newer. Link: https://lore.kernel.org/linux-pci/20240413151617.35630-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Wilczyński Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Geert Uytterhoeven # Renesas Reviewed-by: Rob Herring (Arm) Acked-by: Sergio Paracuellos --- Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml | 2 +- Documentation/devicetree/bindings/pci/apple,pcie.yaml | 2 +- Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml | 2 +- Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 2 +- Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml | 2 +- Documentation/devicetree/bindings/pci/faraday,ftpci100.yaml | 2 +- Documentation/devicetree/bindings/pci/host-generic-pci.yaml | 2 +- Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml | 2 +- Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml | 2 +- Documentation/devicetree/bindings/pci/loongson.yaml | 2 +- Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml | 2 +- Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml | 2 +- Documentation/devicetree/bindings/pci/qcom,pcie.yaml | 2 +- Documentation/devicetree/bindings/pci/rcar-pci-host.yaml | 2 +- Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml | 2 +- Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml | 2 +- Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +- Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml | 2 +- Documentation/devicetree/bindings/pci/versatile.yaml | 2 +- Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml | 2 +- Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml | 2 +- Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml | 2 +- 24 files changed, 24 insertions(+), 24 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml b/Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml index a5bd90bc0712..79a21ba0f9fd 100644 --- a/Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/amlogic,axg-pcie.yaml @@ -13,7 +13,7 @@ description: Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI core. allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - $ref: /schemas/pci/snps,dw-pcie-common.yaml# # We need a select here so we don't match all nodes with 'snps,dw-pcie' diff --git a/Documentation/devicetree/bindings/pci/apple,pcie.yaml b/Documentation/devicetree/bindings/pci/apple,pcie.yaml index 215ff9a9c835..c8775f9cb071 100644 --- a/Documentation/devicetree/bindings/pci/apple,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/apple,pcie.yaml @@ -85,7 +85,7 @@ required: unevaluatedProperties: false allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - $ref: /schemas/interrupt-controller/msi-controller.yaml# - if: properties: diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml index 0e07ab61a48d..5434c144d2ec 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml @@ -11,7 +11,7 @@ maintainers: - Scott Branden allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 22491f7f8852..11f8ea33240c 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -108,7 +108,7 @@ required: - msi-controller allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - $ref: /schemas/interrupt-controller/msi-controller.yaml# - if: properties: diff --git a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml index a6b494401ebb..f4eb82e684bd 100644 --- a/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/cdns-pcie-host.yaml @@ -10,7 +10,7 @@ maintainers: - Tom Joseph allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - $ref: cdns-pcie.yaml# properties: diff --git a/Documentation/devicetree/bindings/pci/faraday,ftpci100.yaml b/Documentation/devicetree/bindings/pci/faraday,ftpci100.yaml index 92efbf0f1297..378dd1c8e2ee 100644 --- a/Documentation/devicetree/bindings/pci/faraday,ftpci100.yaml +++ b/Documentation/devicetree/bindings/pci/faraday,ftpci100.yaml @@ -51,7 +51,7 @@ description: | <0x6000 0 0 4 &pci_intc 2>; allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml index d25423aa7167..3484e0b4b412 100644 --- a/Documentation/devicetree/bindings/pci/host-generic-pci.yaml +++ b/Documentation/devicetree/bindings/pci/host-generic-pci.yaml @@ -116,7 +116,7 @@ required: - ranges allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml b/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml index debfb54a8042..3cae2e0f7f5e 100644 --- a/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml +++ b/Documentation/devicetree/bindings/pci/intel,ixp4xx-pci.yaml @@ -12,7 +12,7 @@ maintainers: description: PCI host controller found in the Intel IXP4xx SoC series. allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml b/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml index 505acc4f3efc..1fd557504b10 100644 --- a/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/intel,keembay-pcie.yaml @@ -11,7 +11,7 @@ maintainers: - Srikanth Thokala allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/loongson.yaml b/Documentation/devicetree/bindings/pci/loongson.yaml index a8324a9bd002..1988465e73a1 100644 --- a/Documentation/devicetree/bindings/pci/loongson.yaml +++ b/Documentation/devicetree/bindings/pci/loongson.yaml @@ -13,7 +13,7 @@ description: |+ PCI host controller found on Loongson PCHs and SoCs. allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 7e8c7a2a5f9b..76d742051f73 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -140,7 +140,7 @@ required: - interrupt-controller allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index f7a3c2636355..a3c4ddc094aa 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -10,7 +10,7 @@ maintainers: - Daire McNamara allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - $ref: /schemas/interrupt-controller/msi-controller.yaml# properties: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 0d1b23523f62..0a39bbfcb28b 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -95,6 +95,6 @@ anyOf: - msi-map allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index cf9a6910b542..f867746b1ae5 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -130,7 +130,7 @@ anyOf: - msi-map allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml index 835b6db00c27..666f013e3af8 100644 --- a/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-pci-host.yaml @@ -12,7 +12,7 @@ maintainers: - Yoshihiro Shimoda allOf: - - $ref: pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml index 5a0d64d3ae6b..b288cdb1ec70 100644 --- a/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,pci-rcar-gen2.yaml @@ -110,7 +110,7 @@ required: - "#interrupt-cells" allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - if: properties: diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml index 531008f0b6ac..60a36b586e1a 100644 --- a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml @@ -10,7 +10,7 @@ maintainers: - Shawn Lin allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - $ref: rockchip,rk3399-pcie-common.yaml# properties: diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 022055edbf9e..548f59d76ef2 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -23,7 +23,7 @@ select: - compatible allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - $ref: /schemas/pci/snps,dw-pcie-common.yaml# - if: not: diff --git a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml index c54d4e57d089..0a9d10532cc8 100644 --- a/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,am65-pci-host.yaml @@ -11,7 +11,7 @@ maintainers: - Kishon Vijay Abraham I allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/versatile.yaml b/Documentation/devicetree/bindings/pci/versatile.yaml index 09748ef6b94f..294c7cd84b37 100644 --- a/Documentation/devicetree/bindings/pci/versatile.yaml +++ b/Documentation/devicetree/bindings/pci/versatile.yaml @@ -13,7 +13,7 @@ description: |+ PCI host controller found on the ARM Versatile PB board's FPGA. allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml index 4734be456bde..b75ceefa6f93 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml +++ b/Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml @@ -10,7 +10,7 @@ maintainers: - Bharat Kumar Gogada allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml index 69b7decabd45..fb87b960a250 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,axi-pcie-host.yaml @@ -10,7 +10,7 @@ maintainers: - Thippeswamy Havalige allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 426f90a47f35..b0d07c71c1c0 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -10,7 +10,7 @@ maintainers: - Thippeswamy Havalige allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# - $ref: /schemas/interrupt-controller/msi-controller.yaml# properties: diff --git a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml index 0aa00b8e49b3..2f59b3a73dd2 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,xdma-host.yaml @@ -10,7 +10,7 @@ maintainers: - Thippeswamy Havalige allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: -- cgit From d3fa4be9033b7b042b3ee9f5e1fc5c44735716b4 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Sat, 13 Apr 2024 17:16:17 +0200 Subject: dt-bindings: PCI: mediatek,mt7621-pcie: Switch from deprecated pci-bus.yaml MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dtschema package with core schemas deprecated pci-bus.yaml schema in favor of individual schemas per host, device and pci-pci. Switch Mediatek MT7621 PCIe host bridge binding to this new schema. This requires dtschema package newer than v2024.02 to work fully. v2024.02 will partially work: with a warning. Link: https://lore.kernel.org/linux-pci/20240413151617.35630-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Wilczyński Reviewed-by: AngeloGioacchino Del Regno Acked-by: Sergio Paracuellos --- Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml index 61d027239910..6fba42156db6 100644 --- a/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek,mt7621-pcie.yaml @@ -14,7 +14,7 @@ description: |+ with 3 Root Ports. Each Root Port supports a Gen1 1-lane Link allOf: - - $ref: /schemas/pci/pci-bus.yaml# + - $ref: /schemas/pci/pci-host-bridge.yaml# properties: compatible: @@ -33,7 +33,7 @@ properties: patternProperties: '^pcie@[0-2],0$': type: object - $ref: /schemas/pci/pci-bus.yaml# + $ref: /schemas/pci/pci-pci-bridge.yaml# properties: reg: -- cgit From 24cd7ecb38864e45f0fa1360e3916cdb69b966cc Mon Sep 17 00:00:00 2001 From: Frank Li Date: Wed, 7 Feb 2024 18:15:49 -0500 Subject: dt-bindings: PCI: layerscape-pci: Convert to YAML format MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Convert layerscape PCIe bind document to the preferred YAML format. [kwilczynski: commit log] Link: https://lore.kernel.org/linux-pci/20240207231550.2663689-1-Frank.Li@nxp.com Signed-off-by: Frank Li Signed-off-by: Krzysztof Wilczyński --- .../bindings/pci/fsl,layerscape-pcie-ep.yaml | 102 +++++++++++++ .../bindings/pci/fsl,layerscape-pcie.yaml | 167 +++++++++++++++++++++ .../devicetree/bindings/pci/layerscape-pci.txt | 79 ---------- 3 files changed, 269 insertions(+), 79 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml create mode 100644 Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml delete mode 100644 Documentation/devicetree/bindings/pci/layerscape-pci.txt diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml new file mode 100644 index 000000000000..399efa7364c9 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie-ep.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape PCIe Endpoint(EP) controller + +maintainers: + - Frank Li + +description: + This PCIe EP controller is based on the Synopsys DesignWare PCIe IP. + + This controller derives its clocks from the Reset Configuration Word (RCW) + which is used to describe the PLL settings at the time of chip-reset. + + Also as per the available Reference Manuals, there is no specific 'version' + register available in the Freescale PCIe controller register set, + which can allow determining the underlying DesignWare PCIe controller version + information. + +properties: + compatible: + enum: + - fsl,ls2088a-pcie-ep + - fsl,ls1088a-pcie-ep + - fsl,ls1046a-pcie-ep + - fsl,ls1028a-pcie-ep + - fsl,lx2160ar2-pcie-ep + + reg: + maxItems: 2 + + reg-names: + items: + - const: regs + - const: addr_space + + fsl,pcie-scfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: A phandle to the SCFG device node. The second entry is the + physical PCIe controller index starting from '0'. This is used to get + SCFG PEXN registers. + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: If the PEX_LUT and PF register block is in big-endian, specify + this property. + + dma-coherent: true + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - reg-names + +allOf: + - if: + properties: + compatible: + enum: + - fsl,ls1028a-pcie-ep + - fsl,ls1046a-pcie-ep + - fsl,ls1088a-pcie-ep + then: + properties: + interrupt-names: + items: + - const: pme + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie_ep1: pcie-ep@3400000 { + compatible = "fsl,ls1028a-pcie-ep"; + reg = <0x00 0x03400000 0x0 0x00100000 + 0x80 0x00000000 0x8 0x00000000>; + reg-names = "regs", "addr_space"; + interrupts = ; /* PME interrupt */ + interrupt-names = "pme"; + num-ib-windows = <6>; + num-ob-windows = <8>; + status = "disabled"; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml new file mode 100644 index 000000000000..793986c5af7f --- /dev/null +++ b/Documentation/devicetree/bindings/pci/fsl,layerscape-pcie.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/fsl,layerscape-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Layerscape PCIe Root Complex(RC) controller + +maintainers: + - Frank Li + +description: + This PCIe RC controller is based on the Synopsys DesignWare PCIe IP + + This controller derives its clocks from the Reset Configuration Word (RCW) + which is used to describe the PLL settings at the time of chip-reset. + + Also as per the available Reference Manuals, there is no specific 'version' + register available in the Freescale PCIe controller register set, + which can allow determining the underlying DesignWare PCIe controller version + information. + +properties: + compatible: + enum: + - fsl,ls1021a-pcie + - fsl,ls2080a-pcie + - fsl,ls2085a-pcie + - fsl,ls2088a-pcie + - fsl,ls1088a-pcie + - fsl,ls1046a-pcie + - fsl,ls1043a-pcie + - fsl,ls1012a-pcie + - fsl,ls1028a-pcie + - fsl,lx2160a-pcie + + reg: + maxItems: 2 + + reg-names: + items: + - const: regs + - const: config + + fsl,pcie-scfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: A phandle to the SCFG device node. The second entry is the + physical PCIe controller index starting from '0'. This is used to get + SCFG PEXN registers. + + big-endian: + $ref: /schemas/types.yaml#/definitions/flag + description: If the PEX_LUT and PF register block is in big-endian, specify + this property. + + dma-coherent: true + + msi-parent: true + + iommu-map: true + + interrupts: + minItems: 1 + maxItems: 2 + + interrupt-names: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - reg-names + - "#address-cells" + - "#size-cells" + - device_type + - bus-range + - ranges + - interrupts + - interrupt-names + - "#interrupt-cells" + - interrupt-map-mask + - interrupt-map + +allOf: + - $ref: /schemas/pci/pci-bus.yaml# + + - if: + properties: + compatible: + enum: + - fsl,ls1028a-pcie + - fsl,ls1046a-pcie + - fsl,ls1043a-pcie + - fsl,ls1012a-pcie + then: + properties: + interrupts: + maxItems: 2 + interrupt-names: + items: + - const: pme + - const: aer + + - if: + properties: + compatible: + enum: + - fsl,ls2080a-pcie + - fsl,ls2085a-pcie + - fsl,ls2088a-pcie + then: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: intr + + - if: + properties: + compatible: + enum: + - fsl,ls1088a-pcie + then: + properties: + interrupts: + maxItems: 1 + interrupt-names: + items: + - const: aer + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@3400000 { + compatible = "fsl,ls1088a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "aer"; + #address-cells = <3>; + #size-cells = <2>; + dma-coherent; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + }; + }; +... diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt deleted file mode 100644 index ee8a4791a78b..000000000000 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ /dev/null @@ -1,79 +0,0 @@ -Freescale Layerscape PCIe controller - -This PCIe host controller is based on the Synopsys DesignWare PCIe IP -and thus inherits all the common properties defined in snps,dw-pcie.yaml. - -This controller derives its clocks from the Reset Configuration Word (RCW) -which is used to describe the PLL settings at the time of chip-reset. - -Also as per the available Reference Manuals, there is no specific 'version' -register available in the Freescale PCIe controller register set, -which can allow determining the underlying DesignWare PCIe controller version -information. - -Required properties: -- compatible: should contain the platform identifier such as: - RC mode: - "fsl,ls1021a-pcie" - "fsl,ls2080a-pcie", "fsl,ls2085a-pcie" - "fsl,ls2088a-pcie" - "fsl,ls1088a-pcie" - "fsl,ls1046a-pcie" - "fsl,ls1043a-pcie" - "fsl,ls1012a-pcie" - "fsl,ls1028a-pcie" - EP mode: - "fsl,ls1028a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls1088a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,ls2088a-pcie-ep", "fsl,ls-pcie-ep" - "fsl,lx2160ar2-pcie-ep", "fsl,ls-pcie-ep" -- reg: base addresses and lengths of the PCIe controller register blocks. -- interrupts: A list of interrupt outputs of the controller. Must contain an - entry for each entry in the interrupt-names property. -- interrupt-names: It could include the following entries: - "aer": Used for interrupt line which reports AER events when - non MSI/MSI-X/INTx mode is used - "pme": Used for interrupt line which reports PME events when - non MSI/MSI-X/INTx mode is used - "intr": Used for SoCs(like ls2080a, lx2160a, ls2080a, ls2088a, ls1088a) - which has a single interrupt line for miscellaneous controller - events(could include AER and PME events). -- fsl,pcie-scfg: Must include two entries. - The first entry must be a link to the SCFG device node - The second entry is the physical PCIe controller index starting from '0'. - This is used to get SCFG PEXN registers -- dma-coherent: Indicates that the hardware IP block can ensure the coherency - of the data transferred from/to the IP block. This can avoid the software - cache flush/invalid actions, and improve the performance significantly. - -Optional properties: -- big-endian: If the PEX_LUT and PF register block is in big-endian, specify - this property. - -Example: - - pcie@3400000 { - compatible = "fsl,ls1088a-pcie"; - reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ - <0x20 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; - interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ - interrupt-names = "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - dma-coherent; - num-viewport = <256>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - msi-parent = <&its>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; - iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ - }; -- cgit From 5220b11a5beb941a0bf882e4f39b7693df093231 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 15 Apr 2024 17:11:29 +0900 Subject: dt-bindings: PCI: rcar-gen4-pci-host: Add R-Car V4H compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document bindings for R-Car V4H (R8A779G0) PCIe host module. Link: https://lore.kernel.org/linux-pci/20240415081135.3814373-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Yoshihiro Shimoda Signed-off-by: Krzysztof Wilczyński Reviewed-by: Geert Uytterhoeven Acked-by: Conor Dooley --- Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml index ffb34339b637..955c664f1fbb 100644 --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -16,7 +16,9 @@ allOf: properties: compatible: items: - - const: renesas,r8a779f0-pcie # R-Car S4-8 + - enum: + - renesas,r8a779f0-pcie # R-Car S4-8 + - renesas,r8a779g0-pcie # R-Car V4H - const: renesas,rcar-gen4-pcie # R-Car Gen4 reg: -- cgit From c037263db4ce4b63b7f56732a46da257ae27c00d Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Mon, 15 Apr 2024 17:11:30 +0900 Subject: dt-bindings: PCI: rcar-gen4-pci-ep: Add R-Car V4H compatible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Document bindings for R-Car V4H (R8A779G0) PCIe endpoint module. Link: https://lore.kernel.org/linux-pci/20240415081135.3814373-3-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Yoshihiro Shimoda Signed-off-by: Krzysztof Wilczyński Reviewed-by: Geert Uytterhoeven Acked-by: Conor Dooley --- Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml index fe38f62da066..91b81ac75592 100644 --- a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-ep.yaml @@ -16,7 +16,9 @@ allOf: properties: compatible: items: - - const: renesas,r8a779f0-pcie-ep # R-Car S4-8 + - enum: + - renesas,r8a779f0-pcie-ep # R-Car S4-8 + - renesas,r8a779g0-pcie-ep # R-Car V4H - const: renesas,rcar-gen4-pcie-ep # R-Car Gen4 reg: -- cgit From 52d06636a4ae4db24ebfe23fae7a525f7e983604 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 1 Apr 2024 12:00:58 +0200 Subject: dt-bindings: PCI: rockchip,rk3399-pcie: Add missing maxItems to ep-gpios MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Properties with GPIOs should define number of actual GPIOs, so add missing maxItems to ep-gpios. Otherwise multiple GPIOs could be provided which is not a true hardware description. Fixes: aa222f9311e1 ("dt-bindings: PCI: Convert Rockchip RK3399 PCIe to DT schema") Link: https://lore.kernel.org/linux-pci/20240401100058.15749-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski Signed-off-by: Krzysztof Wilczyński Acked-by: Conor Dooley --- Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml index 60a36b586e1a..720a5f945a4e 100644 --- a/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml @@ -37,6 +37,7 @@ properties: description: This property is needed if using 24MHz OSC for RC's PHY. ep-gpios: + maxItems: 1 description: pre-reset GPIO vpcie12v-supply: -- cgit