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2016-10-21perf c2c report: Add support to choose local HITMsJiri Olsa1-19/+95
Currently we sort and limit displayed data based on the remote HITMs count. Adding support to switch to local HITMs via --display option: --display ... lcl,rmt Signed-off-by: Jiri Olsa <[email protected]> Tested-by: Arnaldo Carvalho de Melo <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-21perf c2c report: Limit the cachelines table entriesJiri Olsa3-1/+38
Add a limit for entries number of the cachelines table entries. By default now it's the 0.0005% minimum of remote HITMs. Also display only cachelines with remote hitm or store data. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] [ Disabled for now ] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-21perf c2c report: Allow to report callchainsJiri Olsa1-0/+67
Add --call-graph option to properly setup callchain code. Adding default settings to display callchains whenever they are stored in the perf.data. Committer Notes: Testing it: [root@jouet ~]# perf c2c record -a -g sleep 5 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 5.331 MB perf.data (4263 samples) ] [root@jouet ~]# perf evlist -v cpu/mem-loads,ldlat=30/P: type: 4, size: 112, config: 0x1cd, { sample_period, sample_freq }: 4000, sample_type: IP|TID|TIME|ADDR|CALLCHAIN|ID|CPU|PERIOD|DATA_SRC|WEIGHT, read_format: ID, disabled: 1, inherit: 1, mmap: 1, comm: 1, freq: 1, task: 1, precise_ip: 3, mmap_data: 1, sample_id_all: 1, mmap2: 1, comm_exec: 1, { bp_addr, config1 }: 0x1f cpu/mem-stores/P: type: 4, size: 112, config: 0x82d0, { sample_period, sample_freq }: 4000, sample_type: IP|TID|TIME|ADDR|CALLCHAIN|ID|CPU|PERIOD|DATA_SRC|WEIGHT, read_format: ID, disabled: 1, inherit: 1, freq: 1, precise_ip: 3, sample_id_all: 1 [root@jouet ~]# perf c2c report --stats ================================================= Trace Event Information ================================================= Total records : 4263 Locked Load/Store Operations : 220 Load Operations : 2130 Loads - uncacheable : 1 Loads - IO : 7 Loads - Miss : 86 Loads - no mapping : 5 Load Fill Buffer Hit : 609 Load L1D hit : 612 ================================================= Trace Event Information ================================================= Total records : 4263 Locked Load/Store Operations : 220 Load Operations : 2130 Loads - uncacheable : 1 Loads - IO : 7 Loads - Miss : 86 Loads - no mapping : 5 Load Fill Buffer Hit : 609 Load L1D hit : 612 Load L2D hit : 27 Load LLC hit : 607 Load Local HITM : 15 Load Remote HITM : 0 Load Remote HIT : 0 Load Local DRAM : 176 Load Remote DRAM : 0 Load MESI State Exclusive : 176 Load MESI State Shared : 0 Load LLC Misses : 176 LLC Misses to Local DRAM : 100.0% LLC Misses to Remote DRAM : 0.0% LLC Misses to Remote cache (HIT) : 0.0% LLC Misses to Remote cache (HITM) : 0.0% Store Operations : 2133 Store - uncacheable : 0 Store - no mapping : 1 Store L1D Hit : 1967 Store L1D Miss : 165 No Page Map Rejects : 145 Unable to parse data source : 0 ================================================= Global Shared Cache Line Event Information ================================================= Total Shared Cache Lines : 15 Load HITs on shared lines : 26 Fill Buffer Hits on shared lines : 7 L1D hits on shared lines : 3 L2D hits on shared lines : 0 LLC hits on shared lines : 16 Locked Access on shared lines : 2 Store HITs on shared lines : 8 Store L1D hits on shared lines : 7 Total Merged records : 23 ================================================= c2c details ================================================= Events : cpu/mem-loads,ldlat=30/P : cpu/mem-stores/P [root@jouet ~]# [root@jouet ~]# perf c2c report Shared Data Cache Line Table (2378 entries) Total --- LLC Load Hitm -- -- Store Reference - - Load Dram - LLC Total - Core Load Hit - Cacheline records %hitm Total Lcl Rmt Total L1Hit L1Miss Lcl Rmt Ld Miss Loads FB L1 L2 - 0xffff880024380c00 10 0.00% 0 0 0 6 6 0 0 0 0 4 1 3 0 - 0.13% _raw_spin_lock_irqsave - 0.07% ep_poll sys_epoll_wait do_syscall_64 return_from_SYSCALL_64 + 0x103573 - 0.05% ep_poll_callback __wake_up_common - __wake_up_sync_key - 0.02% pipe_read __vfs_read vfs_read sys_read do_syscall_64 return_from_SYSCALL_64 0xfdad + 0.02% sock_def_readable + 0.02% ep_scan_ready_list.constprop.12 + 0.00% mutex_lock + 0.00% __wake_up_common + 0xffff880024380c40 1 0.00% 0 0 0 1 1 0 0 0 0 0 0 0 0 + 0xffff880024380c80 1 0.00% 0 0 0 0 0 0 0 0 0 1 0 0 0 - 0xffff8800243e9f00 1 0.00% 0 0 0 1 1 0 0 0 0 0 0 0 0 enqueue_entity enqueue_task_fair activate_task ttwu_do_activate try_to_wake_up wake_up_process hrtimer_wakeup __hrtimer_run_queues hrtimer_interrupt local_apic_timer_interrupt smp_apic_timer_interrupt apic_timer_interrupt cpuidle_enter call_cpuidle help ------------- And when presing 'd' to see the cacheline details: Cacheline 0xffff880024380c00 ----- HITM ----- -- Store Refs -- --------- cycles ----- cpu Rmt Lcl L1 Hit L1 Miss Off Pid Tid rmt hitm lcl hitm load cnt Symbol - 0.00% 0.00% 100.00% 0.00% 0x0 1473 1474:Chrome_ChildIOT 0 0 41 2 [k] _raw_spin_lock_irqsave [kernel] - _raw_spin_lock_irqsave - 51.52% ep_poll sys_epoll_wait do_syscall_64 return_from_SYSCALL_64 - 0x103573 47.19% 0 4.33% 0xc30bd - 35.93% ep_poll_callback __wake_up_common - __wake_up_sync_key - 18.20% pipe_read __vfs_read vfs_read sys_read do_syscall_64 return_from_SYSCALL_64 0xfdad - 17.73% sock_def_readable unix_stream_sendmsg sock_sendmsg ___sys_sendmsg __sys_sendmsg sys_sendmsg do_syscall_64 return_from_SYSCALL_64 __GI___libc_sendmsg 0x12c036af1fc0 0x16a4050 0x894928ec83485354 + 12.45% ep_scan_ready_list.constprop.12 + 0.00% 0.00% 0.00% 0.00% 0x8 1473 1474:Chrome_ChildIOT 0 0 102 1 [k] mutex_lock [kernel] + 0.00% 0.00% 0.00% 0.00% 0x38 1473 1473:chrome 0 0 88 1 [k] __wake_up_common [kernel] help Signed-off-by: Jiri Olsa <[email protected]> Tested-by: Arnaldo Carvalho de Melo <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-21perf c2c report: Add c2c related stats stdio outputJiri Olsa1-6/+27
Display c2c related configuration options/setup. So far it's output of monitored events: $ perf c2c report --stats ... ================================================= c2c details ================================================= Events : cpu/mem-loads,ldlat=50/pp : cpu/mem-stores/pp Signed-off-by: Jiri Olsa <[email protected]> Tested-by: Arnaldo Carvalho de Melo <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-21perf c2c report: Add shared cachelines stats stdio outputJiri Olsa1-1/+61
Display global shared cachelines related stats table as part of the stdio output or when --stats option is speicified: $ perf c2c report --stats ... ================================================= Global Shared Cache Line Event Information ================================================= Total Shared Cache Lines : 1384 Load HITs on shared lines : 5995 Fill Buffer Hits on shared lines : 1726 L1D hits on shared lines : 1943 L2D hits on shared lines : 0 LLC hits on shared lines : 1360 Locked Access on shared lines : 1993 Store HITs on shared lines : 1504 Store L1D hits on shared lines : 1446 Total Merged records : 3527 Original-patch-by: Dick Fowles <[email protected]> Original-patch-by: Don Zickus <[email protected]> Signed-off-by: Jiri Olsa <[email protected]> Tested-by: Arnaldo Carvalho de Melo <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-21perf c2c report: Add global stats stdio outputJiri Olsa1-0/+56
Display global stats table as part of the stdio output or when --stats option is speicified: $ perf c2c report --stats ================================================= Trace Event Information ================================================= Total records : 41237 Locked Load/Store Operations : 4075 Load Operations : 20526 Loads - uncacheable : 0 Loads - IO : 0 Loads - Miss : 552 Loads - no mapping : 31 Load Fill Buffer Hit : 7333 Load L1D hit : 6398 Load L2D hit : 144 Load LLC hit : 4889 Load Local HITM : 1185 Load Remote HITM : 838 Load Remote HIT : 52 Load Local DRAM : 183 Load Remote DRAM : 106 Load MESI State Exclusive : 289 Load MESI State Shared : 0 Load LLC Misses : 1179 LLC Misses to Local DRAM : 15.5% LLC Misses to Remote DRAM : 9.0% LLC Misses to Remote cache (HIT) : 4.4% LLC Misses to Remote cache (HITM) : 71.1% Store Operations : 20711 Store - uncacheable : 0 Store - no mapping : 1 Store L1D Hit : 20158 Store L1D Miss : 552 No Page Map Rejects : 7 Unable to parse data source : 0 Original-patch-by: Dick Fowles <[email protected]> Original-patch-by: Don Zickus <[email protected]> Signed-off-by: Jiri Olsa <[email protected]> Tested-by: Arnaldo Carvalho de Melo <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-21perf c2c report: Add TUI cacheline browserJiri Olsa1-0/+81
Adding simple TUI cacheline browser. It triggers when you press 'd' in the main browser on the specific cacheline. It allows to navigate through cacheline's offsets and display callchains (implemented in following patches). Signed-off-by: Jiri Olsa <[email protected]> Tested-by: Arnaldo Carvalho de Melo <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-21perf c2c report: Add main TUI browserJiri Olsa3-3/+117
Add the main cachelines TUI browser. It allows to navigate through cachelines and display their details and callchains (implemented in the following patches). Signed-off-by: Jiri Olsa <[email protected]> Tested-by: Arnaldo Carvalho de Melo <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Kim Phillips <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Link: http://lkml.kernel.org/r/20161021001706.GB23970@krava [ Handle file with no entries, fixing segfault reported by Kim Phillips ] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-21ACPICA: MacOSX: Fix wrong sem_destroy definitionLv Zheng1-1/+6
ACPICA commit bbcb58f7875381d5c7f3d614bad3bc628a3f5cc6 The following build errors can be seen for MacOSX builds: .../osunixxf.c:882:9: error: 'sem_close' is deprecated [-Werror,-Wdeprecated-declarations] .../acmacosx.h:122:29: note: expanded from macro 'sem_destroy' #define sem_destroy sem_close sem_destroy() issue is caused by the wrong order of the following lines: #define #sem_destroy sem_close #include <semaphore.h> This patch fixes it by removing the buggy re-definitiion. Lv Zheng. Linux is not affected by this change. Link: https://github.com/acpica/acpica/commit/bbcb58f7 Signed-off-by: Lv Zheng <[email protected]> Signed-off-by: Bob Moore <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
2016-10-21ACPICA: MacOSX: Fix anonymous semaphore implementationLv Zheng1-1/+5
ACPICA commit 01eb9a58f4cf6300a0feb838a02bc4b1895c76e8 ACPICA commit de5b9c0ef1ccb264cbe57c88f6dd3fbf8229f907 The following build errors can be seen for MacOSX builds: .../osunixxf.c:829:42: error: 'tmpnam' is deprecated: This function is provided for compatibility reasons only. Due to security concerns inherent in the design of tmpnam(3), it is highly recommended that you use mkstemp(3) instead. [-Werror,-Wdeprecated-declarations] Using of temporal file name functions can easily result in bus errors on MacOSX. This patch implements anonymous semaphore using an automatic increasing number. Lv Zheng. Linux is not affected by this change. Link: https://github.com/acpica/acpica/commit/01eb9a58 Link: https://github.com/acpica/acpica/commit/de5b9c0e Signed-off-by: Lv Zheng <[email protected]> Signed-off-by: Bob Moore <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
2016-10-19perf c2c report: Add stdio output supportJiri Olsa1-0/+83
Adding the --stdio option output support. The output tables are dumped directly to the stdio. $ perf c2c report ================================================= Shared Data Cache Line Table ================================================= # # Total ----- LLC Load Hitm ----- ---- Store Reference ---- --- Load Dram ---- LLC Total ----- Core Load Hit ----- -- LLC Load Hit -- # Cacheline records %hitm Total Lcl Rmt Total L1Hit L1Miss Lcl Rmt Ld Miss Loads FB L1 L2 Llc Rmt # .................. ....... ....... ....... ....... ....... ....... ....... ....... ........ ........ ....... ....... ....... ....... ....... ........ ........ # 0xffff88000235f840 17 0.00% 0 0 0 17 17 0 0 0 0 0 0 0 0 0 0 ... ================================================= Shared Cache Line Distribution Pareto ================================================= # # ----- HITM ----- -- Store Refs -- Data address ---------- cycles ---------- cpu Shared # Rmt Lcl L1 Hit L1 Miss Offset Pid Tid rmt hitm lcl hitm load cnt Symbol Object Node # ....... ....... ....... ....... .................. ....... ..................... ........ ........ ........ ........ .................... ................. .... # ------------------------------------------------------ 0 0 17 0 0xffff88000235f840 ------------------------------------------------------ 0.00% 0.00% 5.88% 0.00% 0x0 11474 11474:kworker/u16:5 0 0 0 1 [k] rmap_walk_file [kernel.kallsyms] 0 0.00% 0.00% 5.88% 0.00% 0x10 11474 11474:kworker/u16:5 0 0 0 1 [k] lock_page_memcg [kernel.kallsyms] 0 0.00% 0.00% 11.76% 0.00% 0x20 11474 11474:kworker/u16:5 0 0 0 1 [k] page_mapping [kernel.kallsyms] 0 0.00% 0.00% 64.71% 0.00% 0x28 11474 11474:kworker/u16:5 0 0 0 1 [k] __test_set_page_writeback [kernel.kallsyms] 0 0.00% 0.00% 11.76% 0.00% 0x30 11474 11474:kworker/u16:5 0 0 0 1 [k] page_mapped [kernel.kallsyms] 0 ... Signed-off-by: Jiri Olsa <[email protected]> Tested-by: Arnaldo Carvalho de Melo <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Set final resort fieldsJiri Olsa1-0/+31
Set resort/display fields for both cachelines and single cacheline displays. Cachelines are sorted on: rmt_hitm will be made configurable in following patches. Following fields are display for cachelines: dcacheline tot_recs percent_hitm tot_hitm,lcl_hitm,rmt_hitm stores,stores_l1hit,stores_l1miss dram_lcl,dram_rmt ld_llcmiss tot_loads ld_fbhit,ld_l1hit,ld_l2hit ld_lclhit,ld_rmthit The single cacheline is sort by: offset,rmt_hitm,lcl_hitm will be made configurable in following patches. Following fields are display for each cacheline: percent_rmt_hitm percent_lcl_hitm percent_stores_l1hit percent_stores_l1miss offset pid tid mean_rmt mean_lcl mean_load cpucnt symbol dso node Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Setup number of header lines for histsJiri Olsa1-6/+12
Allow to setup number of header lines for c2c hists objects. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add src line sort keyJiri Olsa3-2/+14
It is to be displayed in the single cacheline output: cl_srcline It displays source line related to the code address that accessed cacheline. It's a wrapper to global srcline sort entry. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] [ Remove __maybe_unused from now used 'he' parameter in filter_cb() ] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add 'cpucnt' sort keyJiri Olsa1-0/+23
It is to be displayed in the single cacheline output: cpucnt It displays number of distinct cpus that hit cacheline. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add stats related sort keysJiri Olsa1-0/+80
It is to be displayed in the single cacheline output: median, mean_rmt, mean_lcl, mean_load, stddev It displays statistics hits related to cacheline accesses. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add 'node' sort keyJiri Olsa1-0/+219
It is to be displayed in the single cacheline output: node It displays nodes hits related to cacheline accesses. The node filed comes in 3 flavors: - node IDs separated by ',' - node IDs with stats for each ID, in following format: Node{cpus %hitms %stores} - node IDs with list of affected CPUs in following format: Node{cpu list} User can switch the flavor with -N option (-NN,-NNN). It will be available in TUI to switch this with 'n' key. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add 'symbol' and 'dso' sort keysJiri Olsa1-0/+18
They are to be displayed in the single cacheline output: symbol, dso They are wrappers for global sort_sym and sort_dso sort entries with c2c specific headers. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add 'tid' sort keyJiri Olsa1-0/+7
It is to be displayed in the single cacheline output: tid It's a wrapper for global sort_thread sort entry with c2c specific header. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add 'pid' sort keyJiri Olsa1-0/+25
It is to be displayed in the single cacheline output: pid We currently don't have a single 'pid' sort/display entry, which would output just pid number, hence adding it into c2c code. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add dram related sort keysJiri Olsa1-0/+21
They are to be displayed in the main cachelines overall output: dram_lcl, dram_rmt They display DRAM rmt/lcl access numbers for specific cacheline. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add hitm/store percent related sort keysJiri Olsa1-0/+202
They are to be displayed in the single cacheline output: percent_rmt_hitm, percent_lcl_hitm, percent_stores_l1hit, percent_stores_l1miss They display percentage of HITMs/stores for specific offset in the cacheline. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add hitm percent sort keyJiri Olsa1-0/+91
It is to be displayed in the main cachelines overall output: percent_hitm It displays HITMs percentage for cacheline. It counts remote HITMs at the moment, but it is changed later to support local as well, based on the sort configuration. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add total loads sort keyJiri Olsa1-0/+60
It is to be displayed in the main cachelines overall output: tot_loads It displays sum of all load accesses for cacheline. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add total record sort keyJiri Olsa1-0/+64
It is to be displayed in the main cachelines overall output: tot_recs It displays sum of all cachelines accesses. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add llc load miss dimension keyJiri Olsa1-0/+47
It is to be displayed in the main cachelines overall output: ld_llcmiss It displays bare number of LLC misses for cacheline. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add llc and remote loads related dimension keysJiri Olsa1-0/+20
Add 2 LLC load related dimension key wrappers. They are to be displayed in the main cachelines overall output: ld_lclhit, ld_rmthit They display bare numbers of LLC and remote loads for cacheline. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add loads related dimension keysJiri Olsa1-0/+30
Add 3 loads related dimension key wrappers. They are to be displayed in the main cachelines overall output: ld_fbhit, ld_l1hit, ld_l2hit They all display bare numbers of loads for FB (Fill Buffer), L1 and L2 cache. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add stores related dimension keysJiri Olsa1-0/+48
Add 5 stores related dimension key wrappers. First 3 are to be displayed in the main cachelines overall output: stores, stores_l1hit, stores_l1miss The latter 2 are to be displayed within single cacheline output: cl_stores_l1hit, cl_stores_l1miss They all display bare numbers of stores for cacheline or its related offsets. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add hitm related dimension keysJiri Olsa1-0/+109
Adding 5 hitm related dimension key wrappers. First 3 are to be displayed in the main cachelines overall output: tot_hitm, lcl_hitm, rmt_hitm The latter 2 are to be displayed within single cacheline output: cl_rmt_hitm, cl_lcl_hitm They all display bare numbers of remote/local/total HITMs for cacheline or its related offsets. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add 'iaddr' dimension keyJiri Olsa1-0/+30
It displays the code address (as hex number) responsible for the accesses. Using c2c wrapper to standard 'symbol_iaddr' object to define own header and simple (just address) code address output. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add 'offset' dimension keyJiri Olsa1-0/+36
It displays cacheline offset as hex number. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/n/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add 'dcacheline' dimension keyJiri Olsa1-0/+37
It displays cacheline address as hex number. Using c2c wrapper to standard 'dcacheline' object to defined own header and simple (just address) cacheline output. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add header macrosJiri Olsa1-0/+35
Adding helping macros to define header objects. It will be used in following patches, that add new dimensions. The c2c report will support 2 line headers, hence we only define line[0/1] in macros. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Decode c2c_stats for hist entriesJiri Olsa1-12/+26
Decoding and storing c2c_stats for each hist entry. Changing related function to work with c2c_* objects. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] [ Add '.nr_entries = 0' to the c2c_stats initialization to fix the build on older distros ] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add cacheline hists processingJiri Olsa1-6/+86
Store cacheline related entries in nested hist object for each cacheline data. Nested entries are sorted by 'offset' within related cacheline. We will allow specific sort keys to be configured for nested cacheline data entries in following patches. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] [ he__get_hists() should return NULL when c2c_hists__init() fails ] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add sample processingJiri Olsa1-1/+107
Adding basic sample processing specific hist_entry allocation callbacks (via hists__add_entry_ops). Overloading 'struct hist_entry' object with new 'struct c2c_hist_entry'. The new hist entry object will carry specific stats and nested hists objects. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Fallback to standard dimensionsJiri Olsa1-4/+8
Fallback to standard dimensions in case we don't find the dimension within c2c ones. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add sort_entry dimension supportJiri Olsa1-17/+65
Allow to reuse 'struct sort_entry' objects within c2c dimension support. In case the 'struct sort_entry' object meets the need of c2c report we will use it directly in following patches. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c report: Add dimension supportJiri Olsa1-1/+238
Adding bare bones of dimension support for c2c report. Main interface functions are: c2c_hists__init c2c_hists__reinit which re/initialize 'struct c2c_hists' object with sort/display entries string, in a similar way that setup_sorting function does. We overload the dimension to provide multi line header support for sort/display entries. Also we overload base 'struct perf_hpp_fmt' object with 'struct c2c_fmt' to define c2c specific functions to deal with multi line headers and spans. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c: Add report subcommandJiri Olsa1-1/+65
Adding c2c report subcommand. It reads the perf.data and displays shared data analysis. This patch adds report basic wirings. It gets fully implemented in following patches. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c: Add record subcommandJiri Olsa1-0/+114
Adding c2c record subcommand. It setups options related to HITM cacheline analysis and calls standard perf record command. $ sudo perf c2c record -v -- -a calling: record -W -d --sample-cpu -e cpu/mem-loads,ldlat=30/P -e cpu/mem-stores/P -a ... It produces perf.data, which is to be reported by perf c2c report, that comes in following patches. Details are described in the man page, which is added in one of the following patches. Committer notes: Testing it: # perf c2c record -a sleep 1 [ perf record: Woken up 1 times to write data ] [ perf record: Captured and wrote 5.050 MB perf.data (412 samples) ] # ls -la perf.data -rw-------. 1 root root 5301752 Oct 4 13:32 perf.data # perf evlist cpu/mem-loads,ldlat=30/P cpu/mem-stores/P # perf evlist -v cpu/mem-loads,ldlat=30/P: type: 4, size: 112, config: 0x1cd, { sample_period, sample_freq }: 4000, sample_type: IP|TID|TIME|ADDR|ID|CPU|PERIOD|DATA_SRC|WEIGHT, read_format: ID, disabled: 1, inherit: 1, mmap: 1, comm: 1, freq: 1, task: 1, precise_ip: 3, mmap_data: 1, sample_id_all: 1, mmap2: 1, comm_exec: 1, { bp_addr, config1 }: 0x1f cpu/mem-stores/P: type: 4, size: 112, config: 0x82d0, { sample_period, sample_freq }: 4000, sample_type: IP|TID|TIME|ADDR|ID|CPU|PERIOD|DATA_SRC|WEIGHT, read_format: ID, disabled: 1, inherit: 1, freq: 1, precise_ip: 3, sample_id_all: 1 # # perf report --stdio <SNIP> # Total Lost Samples: 14 # Samples: 216 of event 'cpu/mem-loads,ldlat=30/P' # Event count (approx.): 15207 # Overhead Symbol Shared Object # ........ ..................................... ............................ 10.32% [k] update_blocked_averages [kernel.vmlinux] 3.43% [.] 0x00000000001a2122 qemu-system-x86_64 (deleted) 2.52% [k] enqueue_entity [kernel.vmlinux] 1.88% [.] g_main_context_query libglib-2.0.so.0.4800.2 1.86% [k] __schedule [kernel.vmlinux] <SNIP> # Samples: 196 of event 'cpu/mem-stores/P' # Event count (approx.): 14771346 # Overhead Symbol Shared Object # ........ ................................... ............................ 13.91% [k] intel_idle [kernel.vmlinux] 3.02% [.] 0x00000000022f06ea chrome 2.94% [.] 0x00000000001a1b4c qemu-system-x86_64 (deleted) 2.94% [.] 0x000000000019d8e4 qemu-system-x86_64 (deleted) 2.38% [.] 0x00000000001a1c52 qemu-system-x86_64 (deleted) <SNIP> Signed-off-by: Jiri Olsa <[email protected]> Tested-by: Arnaldo Carvalho de Melo <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c: Add c2c commandJiri Olsa4-0/+26
Adding c2c command base wirings. Its implementation is going to be added gradually in following patches. Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c: Introduce c2c_add_stats functionJiri Olsa2-0/+31
Introducing c2c_add_stats function helper to cumulate c2c_stats. Original-patch-by: Dick Fowles <[email protected]> Original-patch-by: Don Zickus <[email protected]> Signed-off-by: Jiri Olsa <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19perf c2c: Introduce c2c_decode_stats functionJiri Olsa2-0/+134
Introducing c2c_decode_stats function, which decodes data_src data into new struct c2c_stats. Signed-off-by: Jiri Olsa <[email protected]> Original-patch-by: Dick Fowles <[email protected]> Original-patch-by: Don Zickus <[email protected]> Cc: Andi Kleen <[email protected]> Cc: David Ahern <[email protected]> Cc: Don Zickus <[email protected]> Cc: Joe Mario <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
2016-10-19tools/testing/nvdimm: dynamic label supportDan Williams1-7/+23
Update nfit_test infrastructure to enable labels for the dimm on the nfit_test.1 bus. This bus has a pmem region without aliased blk space, so it is a candidate for dynamically enabling label support by writing a namespace index block. Signed-off-by: Dan Williams <[email protected]>
2016-10-19x86/cpufeature: Add AVX512_4VNNIW and AVX512_4FMAPS featuresPiotr Luc1-0/+2
AVX512_4VNNIW - Vector instructions for deep learning enhanced word variable precision. AVX512_4FMAPS - Vector instructions for deep learning floating-point single precision. These new instructions are to be used in future Intel Xeon & Xeon Phi processors. The bits 2&3 of CPUID[level:0x07, EDX] inform that new instructions are supported by a processor. The spec can be found in the Intel Software Developer Manual (SDM) or in the Instruction Set Extensions Programming Reference (ISE). Define new feature flags to enumerate the new instructions in /proc/cpuinfo accordingly to CPUID bits and add the required xsave extensions which are required for proper operation. Signed-off-by: Piotr Luc <[email protected]> Cc: Denys Vlasenko <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Brian Gerst <[email protected]> Cc: Dave Hansen <[email protected]> Cc: Borislav Petkov <[email protected]> Cc: Andy Lutomirski <[email protected]> Cc: Josh Poimboeuf <[email protected]> Cc: Linus Torvalds <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Thomas Gleixner <[email protected]>
2016-10-19bpf: Detect identical PTR_TO_MAP_VALUE_OR_NULL registersThomas Graf1-0/+72
A BPF program is required to check the return register of a map_elem_lookup() call before accessing memory. The verifier keeps track of this by converting the type of the result register from PTR_TO_MAP_VALUE_OR_NULL to PTR_TO_MAP_VALUE after a conditional jump ensures safety. This check is currently exclusively performed for the result register 0. In the event the compiler reorders instructions, BPF_MOV64_REG instructions may be moved before the conditional jump which causes them to keep their type PTR_TO_MAP_VALUE_OR_NULL to which the verifier objects when the register is accessed: 0: (b7) r1 = 10 1: (7b) *(u64 *)(r10 -8) = r1 2: (bf) r2 = r10 3: (07) r2 += -8 4: (18) r1 = 0x59c00000 6: (85) call 1 7: (bf) r4 = r0 8: (15) if r0 == 0x0 goto pc+1 R0=map_value(ks=8,vs=8) R4=map_value_or_null(ks=8,vs=8) R10=fp 9: (7a) *(u64 *)(r4 +0) = 0 R4 invalid mem access 'map_value_or_null' This commit extends the verifier to keep track of all identical PTR_TO_MAP_VALUE_OR_NULL registers after a map_elem_lookup() by assigning them an ID and then marking them all when the conditional jump is observed. Signed-off-by: Thomas Graf <[email protected]> Reviewed-by: Josef Bacik <[email protected]> Acked-by: Daniel Borkmann <[email protected]> Acked-by: Alexei Starovoitov <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2016-10-19Merge tag 'perf-vendor_events-for-mingo-20161018' of ↵Ingo Molnar139-0/+89807
git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux into perf/core Pull perf/vendor_events event tables from Arnaldo Carvalho de Melo: - Add JSON files with vendor event naming for Intel and Power8 processors, allowing users of tools like oprofile to keep using the event names they are used to, as well as people reading vendor documentation, where such naming is used. (Andi Kleen, Sukadev Bhattiprolu) Signed-off-by: Arnaldo Carvalho de Melo <[email protected]> Signed-off-by: Ingo Molnar <[email protected]>
2016-10-18Merge branch 'perf-urgent-for-linus' of ↵Linus Torvalds4-5/+6
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull perf fixes from Ingo Molnar: "Four tooling fixes, two kprobes KASAN related fixes and an x86 PMU driver fix/cleanup" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf jit: Fix build issue on Ubuntu perf jevents: Handle events including .c and .o perf/x86/intel: Remove an inconsistent NULL check kprobes: Unpoison stack in jprobe_return() for KASAN kprobes: Avoid false KASAN reports during stack copy perf header: Set nr_numa_nodes only when we parsed all the data perf top: Fix refreshing hierarchy entries on TUI
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