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2023-03-22libbpf: Use .struct_ops.link section to indicate a struct_ops with a link.Kui-Feng Lee1-16/+44
Flags a struct_ops is to back a bpf_link by putting it to the ".struct_ops.link" section. Once it is flagged, the created struct_ops can be used to create a bpf_link or update a bpf_link that has been backed by another struct_ops. Signed-off-by: Kui-Feng Lee <[email protected]> Acked-by: Andrii Nakryiko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Martin KaFai Lau <[email protected]>
2023-03-22libbpf: Update a bpf_link with another struct_ops.Kui-Feng Lee5-2/+46
Introduce bpf_link__update_map(), which allows to atomically update underlying struct_ops implementation for given struct_ops BPF link. Also add old_map_fd to struct bpf_link_update_opts to handle BPF_F_REPLACE feature. Signed-off-by: Kui-Feng Lee <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Martin KaFai Lau <[email protected]>
2023-03-22bpf: Update the struct_ops of a bpf_link.Kui-Feng Lee1-5/+16
By improving the BPF_LINK_UPDATE command of bpf(), it should allow you to conveniently switch between different struct_ops on a single bpf_link. This would enable smoother transitions from one struct_ops to another. The struct_ops maps passing along with BPF_LINK_UPDATE should have the BPF_F_LINK flag. Signed-off-by: Kui-Feng Lee <[email protected]> Acked-by: Andrii Nakryiko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Martin KaFai Lau <[email protected]>
2023-03-22libbpf: Create a bpf_link in bpf_map__attach_struct_ops().Kui-Feng Lee1-24/+71
bpf_map__attach_struct_ops() was creating a dummy bpf_link as a placeholder, but now it is constructing an authentic one by calling bpf_link_create() if the map has the BPF_F_LINK flag. You can flag a struct_ops map with BPF_F_LINK by calling bpf_map__set_map_flags(). Signed-off-by: Kui-Feng Lee <[email protected]> Acked-by: Andrii Nakryiko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Martin KaFai Lau <[email protected]>
2023-03-22bpf: Create links for BPF struct_ops maps.Kui-Feng Lee1-1/+11
Make bpf_link support struct_ops. Previously, struct_ops were always used alone without any associated links. Upon updating its value, a struct_ops would be activated automatically. Yet other BPF program types required to make a bpf_link with their instances before they could become active. Now, however, you can create an inactive struct_ops, and create a link to activate it later. With bpf_links, struct_ops has a behavior similar to other BPF program types. You can pin/unpin them from their links and the struct_ops will be deactivated when its link is removed while previously need someone to delete the value for it to be deactivated. bpf_links are responsible for registering their associated struct_ops. You can only use a struct_ops that has the BPF_F_LINK flag set to create a bpf_link, while a structs without this flag behaves in the same manner as before and is registered upon updating its value. The BPF_LINK_TYPE_STRUCT_OPS serves a dual purpose. Not only is it used to craft the links for BPF struct_ops programs, but also to create links for BPF struct_ops them-self. Since the links of BPF struct_ops programs are only used to create trampolines internally, they are never seen in other contexts. Thus, they can be reused for struct_ops themself. To maintain a reference to the map supporting this link, we add bpf_struct_ops_link as an additional type. The pointer of the map is RCU and won't be necessary until later in the patchset. Signed-off-by: Kui-Feng Lee <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Martin KaFai Lau <[email protected]>
2023-03-22tools: ynl: Fix genlmsg header encoding formatsDonald Hunter1-3/+3
The pack strings use 'b' signed char for cmd and version but struct genlmsghdr defines them as unsigned char. Use 'B' instead. Fixes: 4e4480e89c47 ("tools: ynl: move the cli and netlink code around") Signed-off-by: Donald Hunter <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
2023-03-22selftests/bpf: Check when bounds are not in the 32-bit rangeXu Kuohai1-0/+121
Add cases to check if bound is updated correctly when 64-bit value is not in the 32-bit range. Signed-off-by: Xu Kuohai <[email protected]> Signed-off-by: Daniel Borkmann <[email protected]> Signed-off-by: Andrii Nakryiko <[email protected]> Acked-by: John Fastabend <[email protected]> Link: https://lore.kernel.org/bpf/[email protected]
2023-03-22bpf: Fix __reg_bound_offset 64->32 var_off subreg propagationDaniel Borkmann1-2/+2
Xu reports that after commit 3f50f132d840 ("bpf: Verifier, do explicit ALU32 bounds tracking"), the following BPF program is rejected by the verifier: 0: (61) r2 = *(u32 *)(r1 +0) ; R2_w=pkt(off=0,r=0,imm=0) 1: (61) r3 = *(u32 *)(r1 +4) ; R3_w=pkt_end(off=0,imm=0) 2: (bf) r1 = r2 3: (07) r1 += 1 4: (2d) if r1 > r3 goto pc+8 5: (71) r1 = *(u8 *)(r2 +0) ; R1_w=scalar(umax=255,var_off=(0x0; 0xff)) 6: (18) r0 = 0x7fffffffffffff10 8: (0f) r1 += r0 ; R1_w=scalar(umin=0x7fffffffffffff10,umax=0x800000000000000f) 9: (18) r0 = 0x8000000000000000 11: (07) r0 += 1 12: (ad) if r0 < r1 goto pc-2 13: (b7) r0 = 0 14: (95) exit And the verifier log says: func#0 @0 0: R1=ctx(off=0,imm=0) R10=fp0 0: (61) r2 = *(u32 *)(r1 +0) ; R1=ctx(off=0,imm=0) R2_w=pkt(off=0,r=0,imm=0) 1: (61) r3 = *(u32 *)(r1 +4) ; R1=ctx(off=0,imm=0) R3_w=pkt_end(off=0,imm=0) 2: (bf) r1 = r2 ; R1_w=pkt(off=0,r=0,imm=0) R2_w=pkt(off=0,r=0,imm=0) 3: (07) r1 += 1 ; R1_w=pkt(off=1,r=0,imm=0) 4: (2d) if r1 > r3 goto pc+8 ; R1_w=pkt(off=1,r=1,imm=0) R3_w=pkt_end(off=0,imm=0) 5: (71) r1 = *(u8 *)(r2 +0) ; R1_w=scalar(umax=255,var_off=(0x0; 0xff)) R2_w=pkt(off=0,r=1,imm=0) 6: (18) r0 = 0x7fffffffffffff10 ; R0_w=9223372036854775568 8: (0f) r1 += r0 ; R0_w=9223372036854775568 R1_w=scalar(umin=9223372036854775568,umax=9223372036854775823,s32_min=-240,s32_max=15) 9: (18) r0 = 0x8000000000000000 ; R0_w=-9223372036854775808 11: (07) r0 += 1 ; R0_w=-9223372036854775807 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775807 R1_w=scalar(umin=9223372036854775568,umax=9223372036854775809) 13: (b7) r0 = 0 ; R0_w=0 14: (95) exit from 12 to 11: R0_w=-9223372036854775807 R1_w=scalar(umin=9223372036854775810,umax=9223372036854775823,var_off=(0x8000000000000000; 0xffffffff)) R2_w=pkt(off=0,r=1,imm=0) R3_w=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775806 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775806 R1_w=scalar(umin=9223372036854775810,umax=9223372036854775810,var_off=(0x8000000000000000; 0xffffffff)) 13: safe [...] from 12 to 11: R0_w=-9223372036854775795 R1=scalar(umin=9223372036854775822,umax=9223372036854775823,var_off=(0x8000000000000000; 0xffffffff)) R2=pkt(off=0,r=1,imm=0) R3=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775794 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775794 R1=scalar(umin=9223372036854775822,umax=9223372036854775822,var_off=(0x8000000000000000; 0xffffffff)) 13: safe from 12 to 11: R0_w=-9223372036854775794 R1=scalar(umin=9223372036854775823,umax=9223372036854775823,var_off=(0x8000000000000000; 0xffffffff)) R2=pkt(off=0,r=1,imm=0) R3=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775793 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775793 R1=scalar(umin=9223372036854775823,umax=9223372036854775823,var_off=(0x8000000000000000; 0xffffffff)) 13: safe from 12 to 11: R0_w=-9223372036854775793 R1=scalar(umin=9223372036854775824,umax=9223372036854775823,var_off=(0x8000000000000000; 0xffffffff)) R2=pkt(off=0,r=1,imm=0) R3=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775792 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775792 R1=scalar(umin=9223372036854775824,umax=9223372036854775823,var_off=(0x8000000000000000; 0xffffffff)) 13: safe [...] The 64bit umin=9223372036854775810 bound continuously bumps by +1 while umax=9223372036854775823 stays as-is until the verifier complexity limit is reached and the program gets finally rejected. During this simulation, the umin also eventually surpasses umax. Looking at the first 'from 12 to 11' output line from the loop, R1 has the following state: R1_w=scalar(umin=0x8000000000000002 (9223372036854775810), umax=0x800000000000000f (9223372036854775823), var_off=(0x8000000000000000; 0xffffffff)) The var_off has technically not an inconsistent state but it's very imprecise and far off surpassing 64bit umax bounds whereas the expected output with refined known bits in var_off should have been like: R1_w=scalar(umin=0x8000000000000002 (9223372036854775810), umax=0x800000000000000f (9223372036854775823), var_off=(0x8000000000000000; 0xf)) In the above log, var_off stays as var_off=(0x8000000000000000; 0xffffffff) and does not converge into a narrower mask where more bits become known, eventually transforming R1 into a constant upon umin=9223372036854775823, umax=9223372036854775823 case where the verifier would have terminated and let the program pass. The __reg_combine_64_into_32() marks the subregister unknown and propagates 64bit {s,u}min/{s,u}max bounds to their 32bit equivalents iff they are within the 32bit universe. The question came up whether __reg_combine_64_into_32() should special case the situation that when 64bit {s,u}min bounds have the same value as 64bit {s,u}max bounds to then assign the latter as well to the 32bit reg->{s,u}32_{min,max}_value. As can be seen from the above example however, that is just /one/ special case and not a /generic/ solution given above example would still not be addressed this way and remain at an imprecise var_off=(0x8000000000000000; 0xffffffff). The improvement is needed in __reg_bound_offset() to refine var32_off with the updated var64_off instead of the prior reg->var_off. The reg_bounds_sync() code first refines information about the register's min/max bounds via __update_reg_bounds() from the current var_off, then in __reg_deduce_bounds() from sign bit and with the potentially learned bits from bounds it'll update the var_off tnum in __reg_bound_offset(). For example, intersecting with the old var_off might have improved bounds slightly, e.g. if umax was 0x7f...f and var_off was (0; 0xf...fc), then new var_off will then result in (0; 0x7f...fc). The intersected var64_off holds then the universe which is a superset of var32_off. The point for the latter is not to broaden, but to further refine known bits based on the intersection of var_off with 32 bit bounds, so that we later construct the final var_off from upper and lower 32 bits. The final __update_reg_bounds() can then potentially still slightly refine bounds if more bits became known from the new var_off. After the improvement, we can see R1 converging successively: func#0 @0 0: R1=ctx(off=0,imm=0) R10=fp0 0: (61) r2 = *(u32 *)(r1 +0) ; R1=ctx(off=0,imm=0) R2_w=pkt(off=0,r=0,imm=0) 1: (61) r3 = *(u32 *)(r1 +4) ; R1=ctx(off=0,imm=0) R3_w=pkt_end(off=0,imm=0) 2: (bf) r1 = r2 ; R1_w=pkt(off=0,r=0,imm=0) R2_w=pkt(off=0,r=0,imm=0) 3: (07) r1 += 1 ; R1_w=pkt(off=1,r=0,imm=0) 4: (2d) if r1 > r3 goto pc+8 ; R1_w=pkt(off=1,r=1,imm=0) R3_w=pkt_end(off=0,imm=0) 5: (71) r1 = *(u8 *)(r2 +0) ; R1_w=scalar(umax=255,var_off=(0x0; 0xff)) R2_w=pkt(off=0,r=1,imm=0) 6: (18) r0 = 0x7fffffffffffff10 ; R0_w=9223372036854775568 8: (0f) r1 += r0 ; R0_w=9223372036854775568 R1_w=scalar(umin=9223372036854775568,umax=9223372036854775823,s32_min=-240,s32_max=15) 9: (18) r0 = 0x8000000000000000 ; R0_w=-9223372036854775808 11: (07) r0 += 1 ; R0_w=-9223372036854775807 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775807 R1_w=scalar(umin=9223372036854775568,umax=9223372036854775809) 13: (b7) r0 = 0 ; R0_w=0 14: (95) exit from 12 to 11: R0_w=-9223372036854775807 R1_w=scalar(umin=9223372036854775810,umax=9223372036854775823,var_off=(0x8000000000000000; 0xf),s32_min=0,s32_max=15,u32_max=15) R2_w=pkt(off=0,r=1,imm=0) R3_w=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775806 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775806 R1_w=-9223372036854775806 13: safe from 12 to 11: R0_w=-9223372036854775806 R1_w=scalar(umin=9223372036854775811,umax=9223372036854775823,var_off=(0x8000000000000000; 0xf),s32_min=0,s32_max=15,u32_max=15) R2_w=pkt(off=0,r=1,imm=0) R3_w=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775805 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775805 R1_w=-9223372036854775805 13: safe [...] from 12 to 11: R0_w=-9223372036854775798 R1=scalar(umin=9223372036854775819,umax=9223372036854775823,var_off=(0x8000000000000008; 0x7),s32_min=8,s32_max=15,u32_min=8,u32_max=15) R2=pkt(off=0,r=1,imm=0) R3=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775797 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775797 R1=-9223372036854775797 13: safe from 12 to 11: R0_w=-9223372036854775797 R1=scalar(umin=9223372036854775820,umax=9223372036854775823,var_off=(0x800000000000000c; 0x3),s32_min=12,s32_max=15,u32_min=12,u32_max=15) R2=pkt(off=0,r=1,imm=0) R3=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775796 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775796 R1=-9223372036854775796 13: safe from 12 to 11: R0_w=-9223372036854775796 R1=scalar(umin=9223372036854775821,umax=9223372036854775823,var_off=(0x800000000000000c; 0x3),s32_min=12,s32_max=15,u32_min=12,u32_max=15) R2=pkt(off=0,r=1,imm=0) R3=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775795 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775795 R1=-9223372036854775795 13: safe from 12 to 11: R0_w=-9223372036854775795 R1=scalar(umin=9223372036854775822,umax=9223372036854775823,var_off=(0x800000000000000e; 0x1),s32_min=14,s32_max=15,u32_min=14,u32_max=15) R2=pkt(off=0,r=1,imm=0) R3=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775794 12: (ad) if r0 < r1 goto pc-2 ; R0_w=-9223372036854775794 R1=-9223372036854775794 13: safe from 12 to 11: R0_w=-9223372036854775794 R1=-9223372036854775793 R2=pkt(off=0,r=1,imm=0) R3=pkt_end(off=0,imm=0) R10=fp0 11: (07) r0 += 1 ; R0_w=-9223372036854775793 12: (ad) if r0 < r1 goto pc-2 last_idx 12 first_idx 12 parent didn't have regs=1 stack=0 marks: R0_rw=P-9223372036854775801 R1_r=scalar(umin=9223372036854775815,umax=9223372036854775823,var_off=(0x8000000000000000; 0xf),s32_min=0,s32_max=15,u32_max=15) R2=pkt(off=0,r=1,imm=0) R3=pkt_end(off=0,imm=0) R10=fp0 last_idx 11 first_idx 11 regs=1 stack=0 before 11: (07) r0 += 1 parent didn't have regs=1 stack=0 marks: R0_rw=P-9223372036854775805 R1_rw=scalar(umin=9223372036854775812,umax=9223372036854775823,var_off=(0x8000000000000000; 0xf),s32_min=0,s32_max=15,u32_max=15) R2_w=pkt(off=0,r=1,imm=0) R3_w=pkt_end(off=0,imm=0) R10=fp0 last_idx 12 first_idx 0 regs=1 stack=0 before 12: (ad) if r0 < r1 goto pc-2 regs=1 stack=0 before 11: (07) r0 += 1 regs=1 stack=0 before 12: (ad) if r0 < r1 goto pc-2 regs=1 stack=0 before 11: (07) r0 += 1 regs=1 stack=0 before 12: (ad) if r0 < r1 goto pc-2 regs=1 stack=0 before 11: (07) r0 += 1 regs=1 stack=0 before 9: (18) r0 = 0x8000000000000000 last_idx 12 first_idx 12 parent didn't have regs=2 stack=0 marks: R0_rw=P-9223372036854775801 R1_r=Pscalar(umin=9223372036854775815,umax=9223372036854775823,var_off=(0x8000000000000000; 0xf),s32_min=0,s32_max=15,u32_max=15) R2=pkt(off=0,r=1,imm=0) R3=pkt_end(off=0,imm=0) R10=fp0 last_idx 11 first_idx 11 regs=2 stack=0 before 11: (07) r0 += 1 parent didn't have regs=2 stack=0 marks: R0_rw=P-9223372036854775805 R1_rw=Pscalar(umin=9223372036854775812,umax=9223372036854775823,var_off=(0x8000000000000000; 0xf),s32_min=0,s32_max=15,u32_max=15) R2_w=pkt(off=0,r=1,imm=0) R3_w=pkt_end(off=0,imm=0) R10=fp0 last_idx 12 first_idx 0 regs=2 stack=0 before 12: (ad) if r0 < r1 goto pc-2 regs=2 stack=0 before 11: (07) r0 += 1 regs=2 stack=0 before 12: (ad) if r0 < r1 goto pc-2 regs=2 stack=0 before 11: (07) r0 += 1 regs=2 stack=0 before 12: (ad) if r0 < r1 goto pc-2 regs=2 stack=0 before 11: (07) r0 += 1 regs=2 stack=0 before 9: (18) r0 = 0x8000000000000000 regs=2 stack=0 before 8: (0f) r1 += r0 regs=3 stack=0 before 6: (18) r0 = 0x7fffffffffffff10 regs=2 stack=0 before 5: (71) r1 = *(u8 *)(r2 +0) 13: safe from 4 to 13: safe verification time 322 usec stack depth 0 processed 56 insns (limit 1000000) max_states_per_insn 1 total_states 3 peak_states 3 mark_read 1 This also fixes up a test case along with this improvement where we match on the verifier log. The updated log now has a refined var_off, too. Fixes: 3f50f132d840 ("bpf: Verifier, do explicit ALU32 bounds tracking") Reported-by: Xu Kuohai <[email protected]> Signed-off-by: Daniel Borkmann <[email protected]> Signed-off-by: Andrii Nakryiko <[email protected]> Reviewed-by: John Fastabend <[email protected]> Link: https://lore.kernel.org/bpf/[email protected] Link: https://lore.kernel.org/bpf/[email protected]
2023-03-22bpf/selftests: coverage for bpf_map_ops errorsJP Kobryn2-0/+300
These tests expose the issue of being unable to properly check for errors returned from inlined bpf map helpers that make calls to the bpf_map_ops functions. At best, a check for zero or non-zero can be done but these tests show it is not possible to check for a negative value or for a specific error value. Signed-off-by: JP Kobryn <[email protected]> Tested-by: Eduard Zingerman <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Alexei Starovoitov <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Update versionZhang Rui1-2/+2
Update tool and supported API version. This is the first version which supports newer Xeon platforms with TPMI support. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: subject and changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Change TRL display for Emerald RapidsSrinivas Pandruvada2-3/+21
Emerald Rapids doesn't specify TRL (Turbo Ratio Limits) based instruction types. Instead it specifies 5 TRL levels, which can be anyone of the instruction types. Increase TRL levels to 5 for Emerald Rapids. Also change display to show by level number. Show only non zero level values. Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Identify Emerald RapidsSrinivas Pandruvada3-2/+12
There are some differences compared to Sapphire Rapids. So, add a separate API. Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Display AMX base frequencySrinivas Pandruvada2-3/+4
AMX frequency is present in non TPMI platforms also. When platform supports, the value is non zero. So, display AMX base frequency when non zero, irrespective of platform API version. Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Use cgroup v2 isolationSrinivas Pandruvada3-2/+173
On supported systems, it is possiible to isolate CPUs instead of CPU online/offline. This is optional and can be specified using -g option when running as daemon or in combination with -o option for SST-PP level change. CPU isolation doesn't isolate IRQs. So IRQs needs to be moved away from isoolated CPUs. This can be done via IRQ sysfs or irqbalance daemon. The IRQ balance daemon is also capable to parse thermal HFI messages to move IRQs away from CPUS, which are supposed be isolated. But this requires version released after July 2022. Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Add missing free cpusetSrinivas Pandruvada1-1/+3
During perf level change cpuset is allocated but not freed. Add free_cpu_set() in success and failure path. Although this is not an issue, as the program will exit after processing of online/offline, but for completeness add the free_cpu_set(). Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Fix clos-max display with TPMI I/FZhang Rui1-1/+1
Comparing clos_config->clos_max with 255 is broken with TPMI I/F because of different isst_get_disp_freq_multiplier() used. Checking for clos_config->clos_max * isst_get_disp_freq_multiplier() instead. Signed-off-by: Zhang Rui <[email protected]> Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Add cpu id checkZhang Rui2-2/+17
Some operations applies to cpu-power-domain only. Add check for cpu id for these functions. Signed-off-by: Zhang Rui <[email protected]> Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Avoid setting duplicate tdp levelZhang Rui1-33/+46
If the new TDP level requetsted is same as the current TDP level, don't call into driver to change level. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Remove cpu mask display for non-cpu ↵Zhang Rui1-21/+23
power domain Non CPU power domains will not have any CPUs. So don't display any CPU count or enable mask. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: subject and changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Hide invalid TRL levelZhang Rui1-0/+3
TRL levels with Zero ratio values is meaningless. Prevent these TRL levels from being displayed. Signed-off-by: Zhang Rui <[email protected]> Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Display fact info for non-cpu power domainZhang Rui1-1/+2
Allow displaying SST-TF info for non-cpu power domain. Signed-off-by: Zhang Rui <[email protected]> Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Show level 0 name for new api_versionZhang Rui1-2/+2
level 0 name is not shown in some case for backward compatibility reason. No need to keep this quirk for new api_version. Signed-off-by: Zhang Rui <[email protected]> Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Prevent cpu clos config for non-cpu ↵Zhang Rui1-0/+6
power domain Non-cpu power domain does not support cpu clos config. Signed-off-by: Zhang Rui <[email protected]> Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Allow display non-cpu power domain infoZhang Rui1-2/+1
Some power domain may not have CPUs associated, allow displaying information for these non-cpu power domains. Signed-off-by: Zhang Rui <[email protected]> Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Display amx_p1 and cooling_typeZhang Rui1-0/+14
amx_p1 and cooling_type are newly introduced for TPMI interface. Display amx_p1 and cooling_type info for platforms that support them. Signed-off-by: Zhang Rui <[email protected]> Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Display punit infoZhang Rui1-21/+18
Display punit info for platforms with new api_version. For platforms with old api_version, don't display the punit info to be backward compatible. For example: Intel(R) Speed Select Technology Executing on CPU model:173[0xad] package-0 die-0 powerdomain-0 cpu-0 get-config-current_level:0 package-0 die-0 powerdomain-3 cpu--1 get-config-current_level:0 package-0 die-0 powerdomain-4 cpu--1 get-config-current_level:0 Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Introduce TPMI interface supportZhang Rui4-1/+794
TPMI (Topology Aware Register and PM Capsule Interface) creates a flexible, extendable and software-PCIe-driver-enumerable MMIO interface for PM features. SST feature is exposed via the TPMI interface on newer Xeon platforms. Kernel TPMI based SST driver provides a series of new IOCTLs for userspace to use. Introduce support for the platforms that do SST control via TPMI interface. Compared with previous platforms, Newer Xeons also supports multi-punit in a package/die, including cpu punit and non-cpu punit. These have already been handled in the generic code. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Get punit core mapping informationSrinivas Pandruvada1-16/+41
Get punit core mapping information using format of MSR 0x54. Based on the API version, decode is done using new format. The new format also include a power domain ID. TPMI SST information is for each power domain. Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Introduce api_version helperZhang Rui2-0/+6
In some cases, the output format may be different with different api_version because of different capabilities or for backward capabilities reason. Introduce api_version() to get the api_version of the platform running. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Support large clos_min/maxZhang Rui1-2/+2
clos_min/max in TPMI interface is frequency in MHz, thus clos_min/max needs to support larger values. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Introduce is_debug_enabled()Zhang Rui2-0/+6
Platform specific code also needs to give debug output. Introduce is_debug_enabled() for this purpose. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Allow api_version based platform callbacksZhang Rui3-11/+16
Different api_version suggests different kernel driver used and different interface is used to communication with the hardware. Allow setting platform specific callbacks based on api_version. Currently, all platforms with api_version 1 uses Mbox/MMIO interfaces. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Move send_mbox_cmd to isst-core-mbox.cZhang Rui2-187/+195
After the previous cleanup, there is no user of send_mbox_cmd outside of isst-core-mbox.c. Thus move send_mbox_cmd to isst-core-mbox.c as internal functions. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract adjust_uncore_freqZhang Rui4-42/+48
Allow platform specific implementation to adjust the uncore frequency. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract read_pm_configZhang Rui3-14/+22
Allow platform specific implementation to get SST-CP capability and current state. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract clos_associateZhang Rui3-16/+26
Allow platform specific implementation to set per core CLOS setting. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract clos_get_assoc_statusZhang Rui3-17/+24
Allow platform specific implementation to get per core CLOS setting. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract set_closZhang Rui3-20/+28
Allow platform specific implementation to set CLOS priority setting. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract pm_get_closZhang Rui3-15/+23
Allow platform specific implementation to get CLOS priority setting. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract pm_qos_configZhang Rui3-84/+93
Allow platform specific implementation to set CLOS config settings. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_clos_informationZhang Rui3-21/+28
Allow platform specific implementation to get CLOS config setting. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_get_trlsZhang Rui3-8/+24
Allow platform specific implementation to get turbo ratio limits of each AVX level, for a selected SST-PP level. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Enhance get_tdp_infoZhang Rui2-59/+60
mbox_get_uncore_p0_p1_info/get_p1_info/get_uncore_mem_freq can be done inside get_tdp_info(). Fold the code into get_tdp_info(). No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_uncore_p0_p1_infoZhang Rui3-42/+50
Allow platform specific implementation to get uncore frequency info. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_fact_infoZhang Rui3-87/+96
Allow platform specific implementation to get SST-TF info. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract set_pbf_fact_statusZhang Rui3-47/+55
Allow platform specific implementation to enable/disable SST-TF/BF. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Remove isst_get_pbf_info_completeZhang Rui3-7/+1
isst_get_pbf_info_complete does nothing but just free the core_mask. Remove the function and do free core_mask directly and free core mask in the caller. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_pbf_infoZhang Rui3-61/+72
Allow platform specific implementation to get SST-BF information. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract set_tdp_levelZhang Rui3-18/+26
Allow platform specific implementation to set a SST-PP level. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>
2023-03-22tools/power/x86/intel-speed-select: Abstract get_trl_bucket_infoZhang Rui3-17/+25
Allow platform specific implementation to get buckets info. No functional changes are expected. Signed-off-by: Zhang Rui <[email protected]> [[email protected]: changelog edits] Signed-off-by: Srinivas Pandruvada <[email protected]>