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Updated the generic SPI EEPROM driver AT25 for support of an additional address
bit in the instruction byte. Certain EEPROMS have a size that is larger than the
number of address bytes would allow (e.g. like M95040 from ST that has 512 Byte
size but uses only one address byte (A0 to A7) for addressing.) For the extra
address bit (A8, A16 or A24) bit 3 of the instruction byte is used. This
instruction bit is normally defined as don't care for other AT25 like chips.
Reviewed-by: Wolfram Sang <[email protected]>
Signed-off-by: Ivo Sieben <[email protected]>
Acked-by: Chris Wright <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
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- Define new setup() hook to export the accessor
- Implement accessor methods
Moves some error checking out of the sysfs interface code into the layer
below it, which is now shared by both sysfs and memory access code.
Signed-off-by: David Brownell <[email protected]>
Signed-off-by: Kevin Hilman <[email protected]>
Cc: Jean Delvare <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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This is adds a simple SPI EEPROM driver, providing access to the EEPROM
through sysfs much like the I2C "eeprom" driver ... except this driver
supports write access, and multiple EEPROM sizes.
From: "Tuppa, Walter" <[email protected]>
Since I have EEPROMs on SPI with different address sizing, I made some
changes to your at25.c to support them. Works perfectly. (Also includes a
small bugfix for the "what size address" test.)
Signed-off-by: David Brownell <[email protected]>
Signed-off-by: Walter Tuppa <[email protected]>
Signed-off-by: Andrew Morton <[email protected]>
Signed-off-by: Linus Torvalds <[email protected]>
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