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2019-04-18mtd: onenand: Store bad block marker position in chip structFrieder Schrempf1-0/+3
The information about where the manufacturer puts the bad block markers inside the bad block and in the OOB data is stored in different places. Let's move this information to the chip struct, as we did it for rawnand. Signed-off-by: Frieder Schrempf <[email protected]> Reviewed-by: Miquel Raynal <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: Always store info about bad block markers in chip structFrieder Schrempf1-1/+15
The information about where the manufacturer puts the bad block markers inside the bad block and in the OOB data is stored in different places. Let's move this information to nand_chip.options and nand_chip.badblockpos. As this chip-specific information is not directly related to the bad block table (BBT), we also rename the flags to NAND_BBM_*. Signed-off-by: Frieder Schrempf <[email protected]> Reviewed-by: Miquel Raynal <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: constify elements of NAND_OP_PARSER(_PATTERN)Masahiro Yamada1-2/+2
Currently, drivers are able to constify a nand_op_parser array, but not nand_op_parser_pattern and nand_op_parser_pattern_elem since they are instantiated by using the NAND_OP_PARSER(_PATTERN). Add 'const' to them in order to move more driver data from .data to .rodata section. Signed-off-by: Masahiro Yamada <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: rawnand: Fix sphinx syntaxJonathan Neuschäfer1-2/+2
Sphinx doesn't handle expressions in identifier references. This fixes the following warnings: ./include/linux/mtd/rawnand.h:1184: WARNING: Inline strong start-string without end-string. ./include/linux/mtd/rawnand.h:1186: WARNING: Inline strong start-string without end-string. Signed-off-by: Jonathan Neuschäfer <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-18mtd: nand: Clarify Kconfig entry for software BCH ECC algorithmMiquel Raynal1-3/+3
There is no point in having two distinct entries, merge them and rename the symbol for more clarity: MTD_NAND_ECC_SW_BCH Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: rawnand: Get rid of chip->ecc_{strength,step}_dsBoris Brezillon1-8/+0
nand_device embeds a nand_ecc_req object which contains the minimum strength and step-size required by the NAND device. Drop the chip->ecc_{strength,step}_ds fields and use chip->base.eccreq.{strength,step_size} instead. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Get rid of chip->numchipsBoris Brezillon1-4/+3
The same information is provided by nanddev_ntargets(). Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Get rid of chip->chipsizeBoris Brezillon1-2/+0
The target size can now be returned by nanddev_get_targetsize(). Get rid of the chip->chipsize field and use this helper instead. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-04-08mtd: rawnand: Get rid of chip->bits_per_cellBoris Brezillon1-4/+2
Now that we inherit from nand_device, we can use nand_device->memorg.bits_per_cell instead of having our own field at the nand_chip level. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Use nanddev_mtd_max_bad_blocks()Boris Brezillon1-5/+0
nanddev_mtd_max_bad_blocks() is implemented by the generic NAND layer and is already doing what we need. Reuse this function instead of having our own implementation. While at it, get rid of the ->max_bb_per_die and ->blocks_per_die fields which are now unused. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Move all page cache related fields to a sub-structBoris Brezillon1-7/+11
Looking at the field names it's hard to tell what ->data_buf, ->pagebuf and ->pagebuf_bitflips are for. Clarify that by moving those fields in a sub-struct named pagecache. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Provide a helper to get chip->data_bufBoris Brezillon1-0/+21
We plan to move cache related fields to a pagecache struct in nand_chip but some drivers access ->pagebuf directly to invalidate the cache before they start using ->data_buf. Let's provide an helper that returns a pointer to ->data_buf after invalidating the cache. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Prepare things to reuse the generic NAND layerBoris Brezillon1-4/+6
The generic NAND layer provides abstraction of NAND devices no matter the bus that is used to communicate with the chip. Basing the raw NAND core on this generic layer should avoid duplication of common operations, like iterating over all pages/blocks for MTD IO/erase operations. In order to re-use this layer, we must first inherit from nand_device and then initialize the nand_device struct appropriately. This patch is taking care of the former. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: rawnand: Use nand_to_mtd() in nand_{set,get}_flash_node()Boris Brezillon1-11/+11
Use the nand_to_mtd() helper to access chip->mtd as done everywhere else. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: nand: Add a helper to retrieve the number of pages per targetBoris Brezillon1-0/+14
Will be used by the raw NAND framework. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: nand: Add a helper returning the number of eraseblocks per targetBoris Brezillon1-0/+12
Some drivers in the raw NAND framework seems to need this helper, so let's just add it instead of open-coding the logic. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-04-08mtd: nand: Add max_bad_eraseblocks_per_lun info to memorgBoris Brezillon1-1/+5
NAND datasheets usually give the maximum number of bad blocks per LUN and this number can be used to help upper layers decide how much blocks they should reserve for bad block handling. Add a max_bad_eraseblocks_per_lun to the nand_memory_organization struct and update the NAND_MEMORG() macro (and its users) accordingly. We also provide a default mtd->_max_bad_blocks() implementation. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]>
2019-03-21mtd: spinand: Use the spi-mem dirmap APIBoris Brezillon1-0/+7
Make use of the spi-mem direct mapping API to let advanced controllers optimize read/write operations when they support direct mapping. Signed-off-by: Boris Brezillon <[email protected]> Cc: Stefan Roese <[email protected]> Signed-off-by: Miquel Raynal <[email protected]> Tested-by: Stefan Roese <[email protected]>
2019-02-25Merge tag 'nand/for-5.1' of git://git.infradead.org/linux-mtd into mtd/nextBoris Brezillon1-17/+9
NAND core changes: - Fourth batch of fixes/cleanup to the raw NAND core impacting various controller drivers (Sunxi, Marvell, MTK, TMIO, OMAP2). - Checking the return code of nand_reset() and nand_readid_op(). - Removing ->legacy.erase and single_erase(). - Simplifying the locking. - Several implicit fall through annotations. Raw NAND controllers drivers changes: - Fixing various possible object reference leaks (MTK, JZ4780, Atmel). - ST: * Adding support for STM32 FMC2 NAND flash controller. - Meson: * Adding support for Amlogic NAND flash controller. - Denali: * Several cleanup patches. - Sunxi: * Several cleanup patches. - FSMC: * Disabling NAND on remove(). * Resetting NAND timings on resume(). SPI-NAND drivers changes: - Toshiba: * Adding support for all Toshiba products. - Macronix: * Fixing ECC status read. - Gigadevice: * Adding support for GD5F1GQ4UExxG.
2019-02-21mtd: spi-nor: Fix wrong abbreviation HWCPASBean Huo1-1/+1
Change SNOR_HWCPAS_READ_OCTAL to SNOR_HWCAPS_READ_OCTAL. Signed-off-by: Bean Huo <[email protected]> Reviewed-by: Tudor Ambarus <[email protected]> Signed-off-by: Boris Brezillon <[email protected]>
2019-02-05mtd: rawnand: remove ->legacy.erase and single_erase()Masahiro Yamada1-2/+0
Now that the last user of this hook, denali.c, stopped using it, we can remove the erase hook from nand_legacy. I squashed single_erase() because only the difference between single_erase() and nand_erase_op() is the number of bit shifts. The status/ret conversion in nand_erase_nand() is unneeded since commit eb94555e9e97 ("mtd: nand: use usual return values for the ->erase() hook"). Cleaned it up now. Signed-off-by: Masahiro Yamada <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-02-05mtd: rawnand: Simplify the lockingBoris Brezillon1-15/+9
nand_get_device() was complex for apparently no good reason. Let's replace this locking scheme with 2 mutexes: one attached to the controller and another one attached to the chip. Every time the core calls nand_get_device(), it will first lock the chip and if the chip is not suspended, will then lock the controller. nand_release_device() will release both lock in the reverse order. nand_get_device() can sleep, just like the previous implementation, which means you should never call that from an atomic context. We also get rid of - the chip->state field, since all it was used for was flagging the chip as suspended. We replace it by a field called chip->suspended and directly set it from nand_suspend/resume() - the controller->wq and controller->active fields which are no longer needed since the new controller->lock (now a mutex) guarantees that all operations are serialized at the controller level - panic_nand_get_device() which would anyway be a no-op. Talking about panic write, I keep thinking the rawnand implementation is unsafe because there's not negotiation with the controller to know when it's actually done with it's previous operation. I don't intend to fix that here, but that's probably something we should look at, or maybe we should consider dropping the ->_panic_write() implementation Last important change to mention: we now return -EBUSY when someone tries to access a device that as been suspended, and propagate this error to the upper layer. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2019-01-17mtd: spi-nor: add opcodes for octal Read/Write commandsYogesh Narayan Gaur1-4/+12
- Add opcodes for octal I/O commands * Read : 1-1-8 and 1-8-8 protocol * Write : 1-1-8 and 1-8-8 protocol * opcodes for 4-byte address mode command - Entry of macros in _convert_3to4_xxx function - Add flag SPI_NOR_OCTAL_READ specifying flash support octal read commands. This flag is required for flashes which didn't provides support for auto detection of Octal mode capabilities i.e. not seems to support newer JESD216C standard. Signed-off-by: Vignesh R <[email protected]> Signed-off-by: Yogesh Narayan Gaur <[email protected]> Reviewed-by: Tudor Ambarus <[email protected]> Signed-off-by: Boris Brezillon <[email protected]>
2018-12-28Merge tag 'char-misc-4.21-rc1' of ↵Linus Torvalds1-0/+2
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver updates from Greg KH: "Here is the big set of char and misc driver patches for 4.21-rc1. Lots of different types of driver things in here, as this tree seems to be the "collection of various driver subsystems not big enough to have their own git tree" lately. Anyway, some highlights of the changes in here: - binderfs: is it a rule that all driver subsystems will eventually grow to have their own filesystem? Binder now has one to handle the use of it in containerized systems. This was discussed at the Plumbers conference a few months ago and knocked into mergable shape very fast by Christian Brauner. Who also has signed up to be another binder maintainer, showing a distinct lack of good judgement :) - binder updates and fixes - mei driver updates - fpga driver updates and additions - thunderbolt driver updates - soundwire driver updates - extcon driver updates - nvmem driver updates - hyper-v driver updates - coresight driver updates - pvpanic driver additions and reworking for more device support - lp driver updates. Yes really, it's _finally_ moved to the proper parallal port driver model, something I never thought I would see happen. Good stuff. - other tiny driver updates and fixes. All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-4.21-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (116 commits) MAINTAINERS: add another Android binder maintainer intel_th: msu: Fix an off-by-one in attribute store stm class: Add a reference to the SyS-T document stm class: Fix a module refcount leak in policy creation error path char: lp: use new parport device model char: lp: properly count the lp devices char: lp: use first unused lp number while registering char: lp: detach the device when parallel port is removed char: lp: introduce list to save port number bus: qcom: remove duplicated include from qcom-ebi2.c VMCI: Use memdup_user() rather than duplicating its implementation char/rtc: Use of_node_name_eq for node name comparisons misc: mic: fix a DMA pool free failure ptp: fix an IS_ERR() vs NULL check genwqe: Fix size check binder: implement binderfs binder: fix use-after-free due to ksys_close() during fdget() bus: fsl-mc: remove duplicated include files bus: fsl-mc: explicitly define the fsl_mc_command endianness misc: ti-st: make array read_ver_cmd static, shrinks object size ...
2018-12-18Merge tag 'spi-nor/for-4.21' of git://git.infradead.org/linux-mtd into mtd/nextBoris Brezillon2-6/+6
Core changes: - Parse the 4BAIT SFDP section - Add a bunch of SPI NOR entries to the flash_info table - Add the concept of SFDP fixups and use it to fix a bug on MX25L25635F - A bunch of minor cleanups/comestic changes
2018-12-18Merge tag 'nand/for-4.21' of git://git.infradead.org/linux-mtd into mtd/nextBoris Brezillon4-92/+91
NAND core changes: - kernel-doc miscellaneous fixes. - Third batch of fixes/cleanup to the raw NAND core impacting various controller drivers (ams-delta, marvell, fsmc, denali, tegra, vf610): * Stopping to pass mtd_info objects to internal functions * Reorganizing code to avoid forward declarations * Dropping useless test in nand_legacy_set_defaults() * Moving nand_exec_op() to internal.h * Adding nand_[de]select_target() helpers * Passing the CS line to be selected in struct nand_operation * Making ->select_chip() optional when ->exec_op() is implemented * Deprecating the ->select_chip() hook * Moving the ->exec_op() method to nand_controller_ops * Moving ->setup_data_interface() to nand_controller_ops * Deprecating the dummy_controller field * Fixing JEDEC detection * Providing a helper for polling GPIO R/B pin Raw NAND chip drivers changes: - Macronix: * Flagging 1.8V AC chips with a broken GET_FEATURES(TIMINGS) Raw NAND controllers drivers changes: - Ams-delta: * Fixing the error path * SPDX tag added * May be compiled with COMPILE_TEST=y * Conversion to ->exec_op() interface * Dropping .IOADDR_R/W use * Use GPIO API for data I/O - Denali: * Removing denali_reset_banks() * Removing ->dev_ready() hook * Including <linux/bits.h> instead of <linux/bitops.h> * Changes to comply with the above fixes/cleanup done in the core. - FSMC: * Adding an SPDX tag to replace the license text * Making conversion from chip to fsmc consistent * Fixing unchecked return value in fsmc_read_page_hwecc * Changes to comply with the above fixes/cleanup done in the core. - Marvell: * Preventing timeouts on a loaded machine (fix) * Changes to comply with the above fixes/cleanup done in the core. - OMAP2: * Pass the parent of pdev to dma_request_chan() (fix) - R852: * Use generic DMA API - sh_flctl: * Converting to SPDX identifiers - Sunxi: * Write pageprog related opcodes to the right register: WCMD_SET (fix) - Tegra: * Stop implementing ->select_chip() - VF610: * Adding an SPDX tag to replace the license text * Changes to comply with the above fixes/cleanup done in the core. - Various trivial/spelling/coding style fixes. SPI-NAND drivers changes: - Removing the depreacated mt29f_spinand driver from staging. - Adding support for: * Toshiba TC58CVG2S0H * GigaDevice GD5FxGQ4xA * Winbond W25N01GV
2018-12-10mtd: spi-nor: parse SFDP 4-byte Address Instruction TableCyrille Pitchen1-0/+1
Add support for SFDP (JESD216B) 4-byte Address Instruction Table. This table is optional but when available, we parse it to get the 4-byte address op codes supported by the memory. Using these op codes is stateless as opposed to entering the 4-byte address mode or setting the Base Address Register (BAR). Flashes that have the 4BAIT table declared can now support SPINOR_OP_PP_1_1_4_4B and SPINOR_OP_PP_1_4_4_4B opcodes. Tested on MX25L25673G. Signed-off-by: Cyrille Pitchen <[email protected]> [[email protected]: - rework erase and page program logic, - pass DMA-able buffer to spi_nor_read_sfdp(), - introduce SPI_NOR_HAS_4BAIT - various minor updates.] Signed-off-by: Tudor Ambarus <[email protected]> Signed-off-by: Boris Brezillon <[email protected]>
2018-12-10mtd: spi-nor: Add an SPDX tag to spi-nor.{c,h}Boris Brezillon1-5/+1
Add SPDX tags to replace the license boiler-plate and fix the MODULE_LICENSE() definition in spi-nor.c to match the license text (GPL v2). Interestingly, spi-nor.h and spi-nor.c do not use the same license (GPL v2+ for spi-nor.h, GPL v2 for spi-nor.c). Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Tudor Ambarus <[email protected]>
2018-12-10mtd: spi-nor: Add the SNOR_F_4B_OPCODES flagBoris Brezillon1-0/+1
Some flash_info entries have the SPI_NOR_4B_OPCODES flag set to let the core know that the flash supports 4B opcode. While this solution works fine for id-based caps detection, it doesn't work that well when relying on SFDP-based caps detection. Let's add an SNOR_F_4B_OPCODES flag so that the SFDP parsing code can set it when appropriate. Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Tudor Ambarus <[email protected]>
2018-12-10mtd: spi-nor: add macros related to MICRON flashYogesh Narayan Gaur2-1/+3
Some MICRON related macros in spi-nor domain were ST. Rename entries related to STMicroelectronics under macro SNOR_MFR_ST. Added entry of MFR Id for Micron flashes, 0x002C. Signed-off-by: Yogesh Gaur <[email protected]> Reviewed-by: Tudor Ambarus <[email protected]> Signed-off-by: Boris Brezillon <[email protected]>
2018-12-07mtd: spinand: add support for GigaDevice GD5FxGQ4xAChuanhong Guo1-0/+1
Add support for GigaDevice GD5F1G/2G/4GQ4xA SPI NAND. Signed-off-by: Chuanhong Guo <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-12-07mtd: rawnand: Deprecate the dummy_controller fieldBoris Brezillon1-3/+3
We try to force NAND controller drivers to properly separate the NAND controller object from the NAND chip one, so let's deprecate the dummy controller object embedded in nand_chip to encourage them to create their own instance. Signed-off-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-12-07mtd: rawnand: Move ->setup_data_interface() to nand_controller_opsBoris Brezillon1-6/+14
->setup_data_interface() is a controller specific method and should thus be placed in nand_controller_ops. In order to make that work with controllers that support keeping pre-configured timings we need to add a new NAND_KEEP_TIMINGS flag to inform the core it should skip the timings selection step. Signed-off-by: Boris Brezillon <[email protected]> Tested-by: Janusz Krzysztofik <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-12-07mtd: rawnand: Move the ->exec_op() method to nand_controller_opsBoris Brezillon1-50/+49
->exec_op() is a controller method and has nothing to do in the nand_chip struct. Let's move it to the nand_controller_ops struct and adjust the core and drivers accordingly. Signed-off-by: Boris Brezillon <[email protected]> Tested-by: Janusz Krzysztofik <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-12-07mtd: rawnand: Deprecate the ->select_chip() hookBoris Brezillon1-2/+2
Now that the CS line to be selected is passed to ->exec_op() and stored in chip->cur_cs and after patching all drivers implementing ->exec_op() to stop implementing this method, we can deprecate it by moving it to the nand_legacy structure. Signed-off-by: Boris Brezillon <[email protected]> Tested-by: Janusz Krzysztofik <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-12-07mtd: rawnand: Pass the CS line to be selected in struct nand_operationBoris Brezillon1-1/+10
In order to deprecate the ->select_chip hook we need to pass the CS line a NAND operations are targeting. This is done through the addition of a cs field to the nand_operation struct. We also need to keep track of the currently selected target to properly initialize op->cs, hence the ->cur_cs field addition to the nand_chip struct. Note that op->cs is not assigned in nand_exec_op() because we might rework the way we execute NAND operations in the future (adopt a queuing mechanism instead of the serialization we have right now). Signed-off-by: Boris Brezillon <[email protected]> Tested-by: Janusz Krzysztofik <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-12-07mtd: rawnand: Add nand_[de]select_target() helpersBoris Brezillon1-1/+4
Add a wrapper to prevent drivers and core code from directly calling the ->select_chip hook which we are about to deprecate. Signed-off-by: Boris Brezillon <[email protected]> Tested-by: Janusz Krzysztofik <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-12-07mtd: rawnand: Remove unused NAND_CONTROLLER_ALLOC flagBoris Brezillon1-4/+0
Looks like NAND_CONTROLLER_ALLOC has been introduced a long time ago back when the dummy nand_hw_ctrl object was dynamically allocated instead of being embedded in nand_chip. We can safely get rid of this unused flag. Signed-off-by: Boris Brezillon <[email protected]> Tested-by: Janusz Krzysztofik <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-12-07mtd: rawnand: Move nand_exec_op() to internal.hBoris Brezillon1-9/+0
nand_exec_op() is only used by core code (nand_xxx.c files). Let's move this inline function in drivers/mtd/nand/raw/internals.h. Signed-off-by: Boris Brezillon <[email protected]> Tested-by: Janusz Krzysztofik <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-12-07mtd: spinand: Add initial support for Toshiba TC58CVG2S0HSchrempf Frieder1-0/+1
Add minimal support for the Toshiba TC58CVG2S0H SPI NAND chip. Signed-off-by: Frieder Schrempf <[email protected]> Acked-by: Clément Péron <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-12-06mtd: add support for reading MTD devices via the nvmem APIAlban Bedel1-0/+2
Allow drivers that use the nvmem API to read data stored on MTD devices. For this the mtd devices are registered as read-only NVMEM providers. We don't support device tree systems for now. Signed-off-by: Alban Bedel <[email protected]> [Bartosz: - include linux/nvmem-provider.h - set the name of the nvmem provider - set no_of_node to true in nvmem_config - don't check the return value of nvmem_unregister() - it cannot fail - tweaked the commit message] Signed-off-by: Bartosz Golaszewski <[email protected]> Acked-by: Boris Brezillon <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-12-02mtd: keep original flags for every struct mtd_infoRafał Miłecki1-0/+1
When allocating a new partition mtd subsystem runs internal tests in the allocate_partition(). They may result in modifying specified flags (e.g. dropping some /features/ like write access). Those constraints don't have to be necessary true for subpartitions. It may happen parent partition isn't block aligned (effectively disabling write access) while subpartition may fit blocks nicely. In such case all checks should be run again (starting with original flags value). Signed-off-by: Rafał Miłecki <[email protected]> Signed-off-by: Boris Brezillon <[email protected]>
2018-12-02mtd: fix mtd_oobavail() incoherent returned valueMiquel Raynal1-1/+1
mtd_oobavail() returns either mtd->oovabail or mtd->oobsize. Both values are unsigned 32-bit entities, so there is no reason to pretend returning a signed one. Signed-off-by: Miquel Raynal <[email protected]> Signed-off-by: Boris Brezillon <[email protected]>
2018-11-13mtd: rawnand: sh_flctl: convert to SPDX identifiersKuninori Morimoto1-14/+2
This patch updates license to use SPDX-License-Identifier instead of verbose license text. As original license mentioned, it is GPL-2.0 in SPDX. Then, MODULE_LICENSE() should be "GPL v2" instead of "GPL". See ${LINUX}/include/linux/module.h "GPL" [GNU Public License v2 or later] "GPL v2" [GNU Public License v2] Signed-off-by: Kuninori Morimoto <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-11-13Merge tag 'v4.20-rc2' of ↵Miquel Raynal1-4/+3
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux into nand/next Linux 4.20-rc2
2018-11-06mtd: nand: Fix nanddev_pos_next_page() kernel-doc headerBoris Brezillon1-1/+1
Function name is wrong in the kernel-doc header. Fixes: 9c3736a3de21 ("mtd: nand: Add core infrastructure to deal with NAND devices") Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Miquel Raynal <[email protected]>
2018-11-05mtd: rawnand: Provide helper for polling GPIO R/B pinJanusz Krzysztofik1-0/+4
Each controller driver having access to NAND R/B pin over GPIO would have to reimplement the polling loop otherwise. Suggested-by: Boris Brezillon <[email protected]> Signed-off-by: Janusz Krzysztofik <[email protected]> Reviewed-by: Boris Brezillon <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>
2018-11-05mtd: nand: Fix nanddev_neraseblocks()Boris Brezillon1-3/+2
nanddev_neraseblocks() currently returns the number pages per LUN instead of the total number of eraseblocks. Fixes: 9c3736a3de21 ("mtd: nand: Add core infrastructure to deal with NAND devices") Cc: <[email protected]> Signed-off-by: Boris Brezillon <[email protected]> Reviewed-by: Miquel Raynal <[email protected]>
2018-10-23Merge tag 'mtd/for-4.20' of git://git.infradead.org/linux-mtdLinus Torvalds7-530/+590
Pull mtd updates from Boris Brezillon: "SPI NOR core changes: - Support non-uniform erase size - Support controllers with limited TX fifo size Driver changes: - m25p80: Re-issue a WREN command after each write access - cadence: Pass a proper dir value to dma_[un]map_single() - fsl-qspi: Check fsl_qspi_get_seqid() return val make sure 4B addressing opcodes are properly handled - intel-spi: Add a new PCI entry for Ice Lake Raw NAND core changes: - Two batchs of cleanups of the NAND API, including: * Deprecating a lot of interfaces (now replaced by ->exec_op()). * Moving code in separate drivers (JEDEC, ONFI), in private files (internals), in platform drivers, etc. * Functions/structures reordering. * Exclusive use of the nand_chip structure instead of the MTD one all across the subsystem. - Addition of the nand_wait_readrdy/rdy_op() helpers. Raw NAND controllers drivers changes: - Various coccinelle patches. - Marvell: * Use regmap_update_bits() for syscon access. * More documentation. * BCH failure path rework. * More layouts to be supported. * IRQ handler complete() condition fixed. - Fsl_ifc: * SRAM initialization fixed for newer controller versions. - Denali: * Fix licenses mismatch and use a SPDX tag. * Set SPARE_AREA_SKIP_BYTES register to 8 if unset. - Qualcomm: * Do not include dma-direct.h. - Docg4: * Removed. - Ams-delta: * Use of a GPIO lookup table * Internal machinery changes. Raw NAND chip drivers changes: - Toshiba: * Add support for Toshiba memory BENAND * Pass a single nand_chip object to the status helper. - ESMT: * New driver to retrieve the ECC requirements from the 5th ID byte. MTD changes: - physmap cleanups/fixe - gpio-addr-flash cleanups/fixes" * tag 'mtd/for-4.20' of git://git.infradead.org/linux-mtd: (93 commits) jffs2: free jffs2_sb_info through jffs2_kill_sb() mtd: spi-nor: fsl-quadspi: fix read error for flash size larger than 16MB mtd: spi-nor: intel-spi: Add support for Intel Ice Lake SPI serial flash mtd: maps: gpio-addr-flash: Convert to gpiod mtd: maps: gpio-addr-flash: Replace array with an integer mtd: maps: gpio-addr-flash: Use order instead of size mtd: spi-nor: fsl-quadspi: Don't let -EINVAL on the bus mtd: devices: m25p80: Make sure WRITE_EN is issued before each write mtd: spi-nor: Support controllers with limited TX FIFO size mtd: spi-nor: cadence-quadspi: Use proper enum for dma_[un]map_single mtd: spi-nor: parse SFDP Sector Map Parameter Table mtd: spi-nor: add support to non-uniform SFDP SPI NOR flash memories mtd: rawnand: marvell: fix the IRQ handler complete() condition mtd: rawnand: denali: set SPARE_AREA_SKIP_BYTES register to 8 if unset mtd: rawnand: r852: fix spelling mistake "card_registred" -> "card_registered" mtd: rawnand: toshiba: Pass a single nand_chip object to the status helper mtd: maps: gpio-addr-flash: Use devm_* functions mtd: maps: gpio-addr-flash: Fix ioremapped size mtd: maps: gpio-addr-flash: Replace custom printk mtd: physmap_of: Release resources on error ...
2018-10-19Merge tag 'nand/for-4.20' of git://git.infradead.org/linux-mtd into mtd/nextBoris Brezillon6-530/+471
NAND core changes: - Two batchs of cleanups of the NAND API, including: * Deprecating a lot of interfaces (now replaced by ->exec_op()). * Moving code in separate drivers (JEDEC, ONFI), in private files (internals), in platform drivers, etc. * Functions/structures reordering. * Exclusive use of the nand_chip structure instead of the MTD one all across the subsystem. - Addition of the nand_wait_readrdy/rdy_op() helpers. Raw NAND controllers drivers changes: - Various coccinelle patches. - Marvell: * Use regmap_update_bits() for syscon access. * More documentation. * BCH failure path rework. * More layouts to be supported. * IRQ handler complete() condition fixed. - Fsl_ifc: * SRAM initialization fixed for newer controller versions. - Denali: * Fix licenses mismatch and use a SPDX tag. * Set SPARE_AREA_SKIP_BYTES register to 8 if unset. - Qualcomm: * Do not include dma-direct.h. - Docg4: * Removed. - Ams-delta: * Use of a GPIO lookup table * Internal machinery changes. Raw NAND chip drivers changes: - Toshiba: * Add support for Toshiba memory BENAND * Pass a single nand_chip object to the status helper. - ESMT: * New driver to retrieve the ECC requirements from the 5th ID byte.
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