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Make use of the existing functions taken from the SPI-NAND core to
instantiate an on-die ECC engine specific to the SPI-NAND core. The
next step will be to tweak the core to use this object instead of
calling the helpers directly.
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
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Prepare the migration to a generic ECC engine by renaming the
nand_ecc_req structure into nand_ecc_props. This structure will be the
base of a wider 'nand_ecc' structure.
In nand_device, these properties are still named "eccreq" even if
"eccprops" might be more descriptive. This is just a transition step,
this field is being replaced very soon by a much wider structure. The
impact of renaming this field would be huge compared to its interest.
Signed-off-by: Miquel Raynal <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
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Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with
the Continuous Read mode.
Some of the Micron SPI NAND devices have the "Continuous Read" feature
enabled by default, which does not fit the subsystem needs.
In this mode, the READ CACHE command doesn't require the starting column
address. The device always output the data starting from the first
column of the cache register, and once the end of the cache register
reached, the data output continues through the next page. With the
continuous read mode, it is possible to read out the entire block using
a single READ command, and once the end of the block reached, the output
pins become High-Z state. However, during this mode the read command
doesn't output the OOB area.
Hence, we disable the feature at probe time.
Signed-off-by: Shivamurthy Shastri <[email protected]>
Reviewed-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
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Currently there are 3 different variants of read_id implementation:
1. opcode only. Found in GD5FxGQ4xF.
2. opcode + 1 addr byte. Found in GD5GxGQ4xA/E
3. opcode + 1 dummy byte. Found in other currently supported chips.
Original implementation was for variant 1 and let detect function
of chips with variant 2 and 3 to ignore the first byte. This isn't
robust:
1. For chips of variant 2, if SPI master doesn't keep MOSI low
during read, chip will get a random id offset, and the entire id
buffer will shift by that offset, causing detect failure.
2. For chips of variant 1, if it happens to get a devid that equals
to manufacture id of variant 2 or 3 chips, it'll get incorrectly
detected.
This patch reworks detect procedure to address problems above. New
logic do detection for all variants separatedly, in 1-2-3 order.
Since all current detect methods do exactly the same id matching
procedure, unify them into core.c and remove detect method from
manufacture_ops.
Tested on GD5F1GQ4UAYIG and W25N01GVZEIG.
Signed-off-by: Chuanhong Guo <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Link: https://lore.kernel.org/linux-mtd/[email protected]
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Add initial support for Paragon Technology
PN26G01Axxxxx and PN26G02Axxxxx SPI NAND
Datasheets available at
http://www.xtxtech.com/upfile/2016082517274590.pdf
http://www.xtxtech.com/upfile/2016082517282329.pdf
Signed-off-by: Jeff Kletsky <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes two-byte device IDs.
http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
Signed-off-by: Jeff Kletsky <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes three-byte addresses
for its page-read ops.
http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/
Signed-off-by: Jeff Kletsky <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Make use of the spi-mem direct mapping API to let advanced controllers
optimize read/write operations when they support direct mapping.
Signed-off-by: Boris Brezillon <[email protected]>
Cc: Stefan Roese <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
Tested-by: Stefan Roese <[email protected]>
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Add support for GigaDevice GD5F1G/2G/4GQ4xA SPI NAND.
Signed-off-by: Chuanhong Guo <[email protected]>
Reviewed-by: Frieder Schrempf <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Add minimal support for the Toshiba TC58CVG2S0H SPI NAND chip.
Signed-off-by: Frieder Schrempf <[email protected]>
Acked-by: Clément Péron <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Add minimal support for the MX35LF1GE4AB SPI NAND chip.
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Add support for the W25M02GV chip.
Signed-off-by: Frieder Schrempf <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Add a basic driver for Micron SPI NANDs. Only one device is supported
right now, but the driver will be extended to support more devices
afterwards.
Signed-off-by: Peter Pan <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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Add a SPI NAND framework based on the generic NAND framework and the
spi-mem infrastructure.
In its current state, this framework supports the following features:
- single/dual/quad IO modes
- on-die ECC
Signed-off-by: Peter Pan <[email protected]>
Signed-off-by: Boris Brezillon <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
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