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Add generic RMII-Reference-Clock-Select support.
Several Micrel PHY have an RMII-Reference-Clock-Select bit to select
25 MHz or 50 MHz clock mode. Recently, support for configuring this
through device tree for KSZ8021 and KSZ8031 was added.
Generalise this support so that it can be configured for other PHY types
as well.
Note that some PHY revisions (of the same type) has this bit inverted.
This should be either configurable through a new device-tree property,
or preferably, determined based on PHY ID if possible.
Also note that this removes support for setting 25 MHz mode from board
files which was also added by the above mentioned commit 45f56cb82e45
("net/phy: micrel: Add clock support for KSZ8021/KSZ8031").
Signed-off-by: Johan Hovold <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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The KSZ8021 and KSZ8031 support RMII reference input clocks of 25MHz
and 50MHz. Both PHYs differ in the default frequency they expect
after reset. If this differs from the actual input clock, then
register 0x1f bit 7 must be changed.
Signed-off-by: Sascha Hauer <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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Renesas R-Car development boards use KSZ8041RNLI PHY which for some reason has
ID of 0x00221537 that is not documented for KSZ8041-family PHYs and does not
match the documented ID of 0x0022151x (where 'x' is the revision). We have
to add the new #define PHY_ID_* and new ksphy_driver[] entry, almost the same
as KSZ8041 one, differing only in the 'phy_id' and 'name' fields.
Signed-off-by: Sergei Shtylyov <[email protected]>
Tested-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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Add defines for common Micrel PHY setups so that other platforms
can use them. Update imx61 and sama5 hardware to use the micrel_phy.h
PHY defines.
Also add support for the KSZ9021RLRN PHY.
Signed-off-by: Dinh Nguyen <[email protected]>
Acked-by: Nicolas Ferre <[email protected]>
Acked-by: David S. Miller <[email protected]>
CC: Andrew Victor <[email protected]>
CC: Jean-Christophe Plagniol-Villard <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Shawn Guo <[email protected]>
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Micrel PHY KSZ8031 is similar to KSZ8021 and also requires the special
initialization of "Operation Mode Strap Override" in reg 0x16
introduced in 212ea99 (phy/micrel: Implement support for KSZ8021).
Signed-off-by: Hector Palacios <[email protected]>
Reviewed-by: Marek Vasut <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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Summary of changes:
.Newly added phys
-KSZ8081/KSZ8091, which has some phy ids.
-KSZ8061
-KSZ9031, which is Gigabit phy.
-KSZ886X, which has a switch function.
-KSZ8031, which has a same phy ids with KSZ8021.
Signed-off-by: David J. Choi <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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this will allow to detect the link between the switch and the soc
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]>
Cc: [email protected]
Signed-off-by: David S. Miller <[email protected]>
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The license header was missing in micrel_phy.h . This patch adds
one.
Signed-off-by: Marek Vasut <[email protected]>
Cc: David J. Choi <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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There is no such part as KS8001, KS8041 or KS8051. There are only
KSZ8001, KSZ8041 and KSZ8051. Rename these parts as such to match
the Micrel naming.
Signed-off-by: Marek Vasut <[email protected]>
Cc: David J. Choi <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Cc: Linux ARM kernel <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Shawn Guo <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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The KSZ8021 PHY was previously caught by KS8051, which is not correct.
This PHY needs additional setup if it is strapped for address 0. In such
case an reserved bit must be written in the 0x16, "Operation Mode Strap
Override" register. According to the KS8051 datasheet, that bit means
"PHY Address 0 in non-broadcast" and it indeed behaves as such on KSZ8021.
The issue where the ethernet controller (Freescale FEC) did not communicate
with network is fixed by writing this bit as 1.
Signed-off-by: Marek Vasut <[email protected]>
Cc: David J. Choi <[email protected]>
Cc: David S. Miller <[email protected]>
Cc: Nobuhiro Iwamatsu <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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Right ID of KSZ9021 is 0x00221610.
Because lower 4bit is a revision number, it varies according to a chip.
Signed-off-by: Nobuhiro Iwamatsu <[email protected]>
Cc: David J. Choi <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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Platform code can now set the MICREL_PHY_50MHZ_CLK bit of dev_flags in a fixup
routine (registered with phy_register_fixup_for_uid()), to make the KZS8051RNL
PHY work with 50MHz RMII reference clock.
Cc: David J. Choi <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
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