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Nothing uses the global gic_present variable anymore; mips_gic_present()
should be used instead. Remove the dead code.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17045/
Signed-off-by: Ralf Baechle <[email protected]>
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All in-tree platforms now probe the GIC driver using device tree, and as
such nothing calls gic_init() any longer. Remove the dead code.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17043/
Signed-off-by: Ralf Baechle <[email protected]>
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The MIPS VDSO code is no longer reliant upon the irqchip driver to
provide the address of the GIC's user-visible section via
gic_get_usm_range(). Remove the now-dead code.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17041/
Signed-off-by: Ralf Baechle <[email protected]>
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Move the definitions of macros used to convert between hardware IRQ
numbers & shared or local interrupt numbers into the irqchip driver,
which is all that should ever need to care about them.
Remove GIC_CPU_TO_VEC_OFFSET() in the process since it's never used.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17039/
Signed-off-by: Ralf Baechle <[email protected]>
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The GIC_CPU_INT* macros are never used. Remove the dead code.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17038/
Signed-off-by: Ralf Baechle <[email protected]>
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Move the definition of VP-local interrupts provided by the MIPS Global
Interrupt Controller to the new asm/mips-gic.h header to be alongside
the new accessor functions. Whilst at it, convert to an enum which lends
itself more easily to expansion & documentation.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17037/
Signed-off-by: Ralf Baechle <[email protected]>
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Convert the remaining accesses to registers in the GIC VP-local &
VP-other register blocks to use the new accessor functions provided by
asm/mips-gic.h, resulting in code which is often shorter & easier to
read.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17036/
Signed-off-by: Ralf Baechle <[email protected]>
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Use the new accessor functions provided by asm/mips-gic.h to access
masks controlling local interrupts, resulting in code which is often
shorter & easier to read.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17035/
Signed-off-by: Ralf Baechle <[email protected]>
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Convert the remaining accesses to registers in the GIC shared register
block to use the new accessor functions provided by asm/mips-gic.h,
resulting in code which is often shorter & easier to read.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17034/
Signed-off-by: Ralf Baechle <[email protected]>
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Remove the gic_map_to_vpe() function in favour of using the new
write_gic_map_vp() accessor function which isn't any more complex to
use & allows us to drop a level of abstraction.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17033/
Signed-off-by: Ralf Baechle <[email protected]>
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Remove the gic_map_to_pin() function in favour of using the new
write_gic_map_pin() accessor function which isn't any more complex to
use & allows us to drop a level of abstraction.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17032/
Signed-off-by: Ralf Baechle <[email protected]>
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Remove the gic_set_dual_edge() function in favour of using the new
change_gic_dual() accessor function which provides equivalent
functionality. This also allows us to remove the gic_update_bits()
function which gic_set_dual_edge() was the last user of, along with the
GIC_INTR_OFS() & GIC_INTR_BIT() macros.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17031/
Signed-off-by: Ralf Baechle <[email protected]>
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Remove the gic_set_trigger() function in favour of using the new
change_gic_trig() accessor function which provides equivalent
functionality.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17030/
Signed-off-by: Ralf Baechle <[email protected]>
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Remove the gic_set_polarity() function in favour of using the new
change_gic_pol() accessor function which provides equivalent
functionality.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17029/
Signed-off-by: Ralf Baechle <[email protected]>
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The gic_set_mask() & gic_reset_mask() functions are now no more
convenient to call than the write_gic_smask() or write_gic_rmask()
accessor functions. Remove the layer of abstraction.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17028/
Signed-off-by: Ralf Baechle <[email protected]>
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Simplify gic_local_irq_domain_map() by:
- Moving the check for invalid IRQs outside of the loop.
- Moving the decision about whether to use gic_cpu_pin or timer_cpu_pin
outside of the loop.
- Using the new write_gic_vo_map() accessor function to avoid the need
to handle each map register separately.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17027/
Signed-off-by: Ralf Baechle <[email protected]>
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Simplify the reads of the bitmaps indicating pending & masked interrupts
in gic_handle_shared_int() using the __ioread32_copy() &
__ioread64_copy() helper functions.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17026/
Signed-off-by: Ralf Baechle <[email protected]>
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Nothing needs gic_read_local_vp_id() any longer, so remove the dead
code.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17024/
Signed-off-by: Ralf Baechle <[email protected]>
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The MIPS GIC clocksource driver is no longer using the accessor
functions provided by the irqchip driver, so remove them.
Signed-off-by: Paul Burton <[email protected]>
Acked-by: Marc Zyngier <[email protected]>
Cc: Jason Cooper <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Cc: [email protected]
Patchwork: https://patchwork.linux-mips.org/patch/17022/
Signed-off-by: Ralf Baechle <[email protected]>
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As KVM needs to know about the availability of GICv4 to enable
direct injection of interrupts, let's advertise the feature in
the gic_kvm_info structure.
Signed-off-by: Marc Zyngier <[email protected]>
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Get the show on the road...
Reviewed-by: Thomas Gleixner <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Add the required interfaces to map, unmap and update a VLPI.
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Add the required interfaces to schedule a VPE and perform a
VINVALL command.
Reviewed-by: Thomas Gleixner <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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When creating a VM, it is very convenient to have an irq domain
containing all the doorbell interrupts associated with that VM
(each interrupt representing a VPE).
Reviewed-by: Thomas Gleixner <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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A long time ago, GITS_CTLR[1] used to be called GITC_CTLR.EnableVLPI.
It has been subsequently deprecated and is now an "Implementation
Defined" bit that may ot may not be set for GICv4. Brilliant.
And the current crop of the FastModel requires that bit for VLPIs
to be enabled. Oh well... Let's set it and find out what breaks.
Signed-off-by: Marc Zyngier <[email protected]>
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When we don't have the DirectLPI feature, we must work around the
architecture shortcomings to be able to perform the required
maintenance (interrupt masking, clearing and injection).
For this, we create a fake device whose sole purpose is to
provide a way to issue commands as if we were dealing with LPIs
coming from that device (while they actually originate from
the ITS). This fake device doesn't have LPIs allocated to it,
but instead uses the VPE LPIs.
Of course, this could be a real bottleneck, and a naive
implementation would require 6 commands to issue an invalidation.
Instead, let's allocate at least one event per physical CPU
(rounded up to the next power of 2), and opportunistically
map the VPE doorbell to an event. This doorbell will be mapped
until we roll over and need to reallocate this slot.
This ensures that most of the time, we only need 2 commands
to issue an INV, INT or CLEAR, making the performance a lot
better, given that we always issue a CLEAR on entry, and
an INV on each side of a trapped WFI.
Signed-off-by: Marc Zyngier <[email protected]>
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When a VPE is scheduled to run, the corresponding redistributor must
be told so, by setting VPROPBASER to the VM's property table, and
VPENDBASER to the vcpu's pending table.
When scheduled out, we preserve the IDAI and PendingLast bits. The
latter is specially important, as it tells the hypervisor that
there are pending interrupts for this vcpu.
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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V{PEND,PROP}BASER being 64bit registers, they need some ad-hoc
accessors on 32bit, specially given that VPENDBASER contains
a Valid bit, making the access a bit convoluted.
Reviewed-by: Thomas Gleixner <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Add the new GICv4 ITS command definitions, most of them, being
defined in terms of their physical counterparts.
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Add a bunch of GICv4-specific data structures that will get used in
subsequent patches.
Reviewed-by: Thomas Gleixner <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Add the probing code for the ITS VLPI support. This includes
configuring the ITS number if not supporting the single VMOVP
command feature.
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Add helper functions that probe for VLPI and DirectLPI properties.
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Thomas Gleixner <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Now that we're able to safely handle common sysreg access, let's
give the user the opportunity to enable it by passing a specific
command-line option (vgic_v3.common_trap).
Tested-by: Alexander Graf <[email protected]>
Acked-by: David Daney <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Acked-by: Christoffer Dall <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
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In order to be able to trap Group-0 GICv3 system registers, we need to
set ICH_HCR_EL2.TALL0 begore entering the guest. This is conditionnaly
done after having restored the guest's state, and cleared on exit.
Tested-by: Alexander Graf <[email protected]>
Acked-by: David Daney <[email protected]>
Acked-by: Christoffer Dall <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
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In order to be able to trap Group-1 GICv3 system registers, we need to
set ICH_HCR_EL2.TALL1 before entering the guest. This is conditionally
done after having restored the guest's state, and cleared on exit.
Tested-by: Alexander Graf <[email protected]>
Acked-by: David Daney <[email protected]>
Acked-by: Christoffer Dall <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
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Add a handler for writing the guest's view of the ICC_EOIR1_EL1
register. This involves dropping the priority of the interrupt,
and deactivating it if required (EOImode == 0).
Tested-by: Alexander Graf <[email protected]>
Acked-by: David Daney <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Reviewed-by: Christoffer Dall <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
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Add a handler for reading the guest's view of the ICC_IAR1_EL1
register. This involves finding the highest priority Group-1
interrupt, checking against both PMR and the active group
priority, activating the interrupt and setting the group
priority as active.
Tested-by: Alexander Graf <[email protected]>
Acked-by: David Daney <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Reviewed-by: Christoffer Dall <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
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We have been a little loose with our intermediate VMCR representation
where we had a 'ctlr' field, but we failed to differentiate between the
GICv2 GICC_CTLR and ICC_CTLR_EL1 layouts, and therefore ended up mapping
the wrong bits into the individual fields of the ICH_VMCR_EL2 when
emulating a GICv2 on a GICv3 system.
Fix this by using explicit fields for the VMCR bits instead.
Cc: Eric Auger <[email protected]>
Reported-by: wanghaibin <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
Tested-by: Marc Zyngier <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD
Second round of KVM/ARM Changes for v4.12.
Changes include:
- A fix related to the 32-bit idmap stub
- A fix to the bitmask used to deode the operands of an AArch32 CP
instruction
- We have moved the files shared between arch/arm/kvm and
arch/arm64/kvm to virt/kvm/arm
- We add support for saving/restoring the virtual ITS state to
userspace
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this new helper synchronizes the irq pending_latch
with the LPI pending bit status found in rdist pending table.
As the status is consumed, we reset the bit in pending table.
As we need the PENDBASER_ADDRESS() in vgic-v3, let's move its
definition in the irqchip header. We restore the full length
of the field, ie [51:16]. Same for PROPBASER_ADDRESS with full
field length of [51:12].
Signed-off-by: Eric Auger <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
Reviewed-by: Christoffer Dall <[email protected]>
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Up to now the MAPD's ITT size field has been ignored. It encodes
the number of eventid bit minus 1. It should be used to check
the eventid when a MAPTI command is issued on a device. Let's
store the number of eventid bits in the its_device and do the
check on MAPTI. Also make sure the ITT size field does
not exceed the GITS_TYPER IDBITS field.
Signed-off-by: Eric Auger <[email protected]>
Reviewed-by: Christoffer Dall <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
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The GITS_IIDR revision field is used to encode the migration ABI
revision. So we need to restore it to check the table layout is
readable by the destination.
By writing the IIDR, userspace thus forces the ABI revision to be
used and this must be less than or equal to the max revision KVM
supports.
Signed-off-by: Eric Auger <[email protected]>
Reviewed-by: Christoffer Dall <[email protected]>
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We plan to support different migration ABIs, ie. characterizing
the ITS table layout format in guest RAM. For example, a new ABI
will be needed if vLPIs get supported for nested use case.
So let's introduce an array of supported ABIs (at the moment a single
ABI is supported though). The following characteristics are foreseen
to vary with the ABI: size of table entries, save/restore operation,
the way abi settings are applied.
By default the MAX_ABI_REV is applied on its creation. In subsequent
patches we will introduce a way for the userspace to change the ABI
in use.
The entry sizes now are set according to the ABI version and not
hardcoded anymore.
Signed-off-by: Eric Auger <[email protected]>
Reviewed-by: Christoffer Dall <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer updates from Thomas Gleixner:
"The timer departement delivers:
- more year 2038 rework
- a massive rework of the arm achitected timer
- preparatory patches to allow NTP correction of clock event devices
to avoid early expiry
- the usual pile of fixes and enhancements all over the place"
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (91 commits)
timer/sysclt: Restrict timer migration sysctl values to 0 and 1
arm64/arch_timer: Mark errata handlers as __maybe_unused
Clocksource/mips-gic: Remove redundant non devicetree init
MIPS/Malta: Probe gic-timer via devicetree
clocksource: Use GENMASK_ULL in definition of CLOCKSOURCE_MASK
acpi/arm64: Add SBSA Generic Watchdog support in GTDT driver
clocksource: arm_arch_timer: add GTDT support for memory-mapped timer
acpi/arm64: Add memory-mapped timer support in GTDT driver
clocksource: arm_arch_timer: simplify ACPI support code.
acpi/arm64: Add GTDT table parse driver
clocksource: arm_arch_timer: split MMIO timer probing.
clocksource: arm_arch_timer: add structs to describe MMIO timer
clocksource: arm_arch_timer: move arch_timer_needs_of_probing into DT init call
clocksource: arm_arch_timer: refactor arch_timer_needs_probing
clocksource: arm_arch_timer: split dt-only rate handling
x86/uv/time: Set ->min_delta_ticks and ->max_delta_ticks
unicore32/time: Set ->min_delta_ticks and ->max_delta_ticks
um/time: Set ->min_delta_ticks and ->max_delta_ticks
tile/time: Set ->min_delta_ticks and ->max_delta_ticks
score/time: Set ->min_delta_ticks and ->max_delta_ticks
...
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Malta was the only platform probing this driver from platform code
without using device tree. With that code removed, gic_clocksource_init
is redundant so remove it.
Signed-off-by: Matt Redfearn <[email protected]>
Cc: [email protected]
Cc: Jason Cooper <[email protected]>
Cc: Paul Burton <[email protected]>
Cc: Daniel Lezcano <[email protected]>
Cc: Ralf Baechle <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Thomas Gleixner <[email protected]>
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As an oversight, for GICv2, we accidentally export the GICC_PMR register
in the format of the GICH_VMCR.VMPriMask field in the lower 5 bits of a
word, meaning that userspace must always use the lower 5 bits to
communicate with the KVM device and must shift the value left by 3
places to obtain the actual priority mask level.
Since GICv3 supports the full 8 bits of priority masking in the ICH_VMCR,
we have to fix the value we export when emulating a GICv2 on top of a
hardware GICv3 and exporting the emulated GICv2 state to userspace.
Take the chance to clarify this aspect of the ABI.
Reviewed-by: Marc Zyngier <[email protected]>
Signed-off-by: Christoffer Dall <[email protected]>
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Our GICv3 emulation always presents ICC_SRE_EL1 with DIB/DFB set to
zero, which implies that there is a way to bypass the GIC and
inject raw IRQ/FIQ by driving the CPU pins.
Of course, we don't allow that when the GIC is configured, but
we fail to indicate that to the guest. The obvious fix is to
set these bits (and never let them being changed again).
Reported-by: Peter Maydell <[email protected]>
Acked-by: Christoffer Dall <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Pull KVM updates from Paolo Bonzini:
"4.11 is going to be a relatively large release for KVM, with a little
over 200 commits and noteworthy changes for most architectures.
ARM:
- GICv3 save/restore
- cache flushing fixes
- working MSI injection for GICv3 ITS
- physical timer emulation
MIPS:
- various improvements under the hood
- support for SMP guests
- a large rewrite of MMU emulation. KVM MIPS can now use MMU
notifiers to support copy-on-write, KSM, idle page tracking,
swapping, ballooning and everything else. KVM_CAP_READONLY_MEM is
also supported, so that writes to some memory regions can be
treated as MMIO. The new MMU also paves the way for hardware
virtualization support.
PPC:
- support for POWER9 using the radix-tree MMU for host and guest
- resizable hashed page table
- bugfixes.
s390:
- expose more features to the guest
- more SIMD extensions
- instruction execution protection
- ESOP2
x86:
- improved hashing in the MMU
- faster PageLRU tracking for Intel CPUs without EPT A/D bits
- some refactoring of nested VMX entry/exit code, preparing for live
migration support of nested hypervisors
- expose yet another AVX512 CPUID bit
- host-to-guest PTP support
- refactoring of interrupt injection, with some optimizations thrown
in and some duct tape removed.
- remove lazy FPU handling
- optimizations of user-mode exits
- optimizations of vcpu_is_preempted() for KVM guests
generic:
- alternative signaling mechanism that doesn't pound on
tsk->sighand->siglock"
* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (195 commits)
x86/kvm: Provide optimized version of vcpu_is_preempted() for x86-64
x86/paravirt: Change vcp_is_preempted() arg type to long
KVM: VMX: use correct vmcs_read/write for guest segment selector/base
x86/kvm/vmx: Defer TR reload after VM exit
x86/asm/64: Drop __cacheline_aligned from struct x86_hw_tss
x86/kvm/vmx: Simplify segment_base()
x86/kvm/vmx: Get rid of segment_base() on 64-bit kernels
x86/kvm/vmx: Don't fetch the TSS base from the GDT
x86/asm: Define the kernel TSS limit in a macro
kvm: fix page struct leak in handle_vmon
KVM: PPC: Book3S HV: Disable HPT resizing on POWER9 for now
KVM: Return an error code only as a constant in kvm_get_dirty_log()
KVM: Return an error code only as a constant in kvm_get_dirty_log_protect()
KVM: Return directly after a failed copy_from_user() in kvm_vm_compat_ioctl()
KVM: x86: remove code for lazy FPU handling
KVM: race-free exit from KVM_RUN without POSIX signals
KVM: PPC: Book3S HV: Turn "KVM guest htab" message into a debug message
KVM: PPC: Book3S PR: Ratelimit copy data failure error messages
KVM: Support vCPU-based gfn->hva cache
KVM: use separate generations for each address space
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GICD_TYPER_LPIS macro is defined twice in this file. This patch removes the
duplicate entry.
Fixes: f5c1434c217f ("irqchip: GICv3: rework redistributor structure")
Signed-off-by: Alim Akhtar <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
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Back in the days when the GICv3/v4 architecture was drafted,
the command to an event to an LPI number was called MAPVI.
Later on, and to avoid confusion with the GICv4 command VMAPI,
it was renamed MAPTI. We've carried the old name for a long
time, but it gets in the way of people reading the code in
the light of the public architecture specification.
Just repaint all the references and kill the old definition.
Signed-off-by: Marc Zyngier <[email protected]>
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