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2018-10-25Merge tag 'mfd-next-4.20' of ↵Linus Torvalds1-0/+17
git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd Pull MFD updates from Lee Jones: "New Drivers - Add support for USART SPI to AT91* New Functionality - Add support for Audio CODECs to motorola-cpcap Fix-ups - DT documentation fix-ups; atmel-usart - Staticise functions/structs; spi-at91-usart, arizona-core - Constify; ti-lmu - Fix memory leaks; menelaus - Change device 'wake-up' status; ti_am335x_tscadc, max8997 - Power Management (suspend/resume) semantic changes; ti_am335x_adc, cros_ec, max8997 - SPDX churn; sec-core (+ headers), max* (+ headers), intel* (+ headers), - Trivial (whitespace, email addresses, alphabetisise); Kconfig, adp5520, intel_soc_pmic_* - Build as module; sec-irq - Use new %pOFn printk format for device_node.name; max77620 - Remove unused code; madera - Use generic MACROs; intel_msic, intel_soc_pmic_crc - Move to GPIOD; ti-lmu - Use managed resources; ti-lmu Bug Fixes - Add missing headers; at91-usart - Prevent device from entering low-power mode; arizona-core - Poll for BOOT_DONE to avoid still-booting NACK; madera-core - Prevent ADC read from shutting down device; mc13xxx-core" * tag 'mfd-next-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (45 commits) mfd: cros_ec: Avoid unneeded internal declaration warning mfd: ti-lmu: Use of_device_get_match_data() helper mfd: ti-lmu: Use managed resource for everything mfd: ti-lmu: Switch to GPIOD mfd: ti-lmu: constify mfd_cell tables mfd: max8997: Disable interrupt handling for suspend/resume cycle mfd: max8997: Enale irq-wakeup unconditionally mfd: arizona: Make array mclk_name static, shrinks object size MAINTAINERS: Add myself as designated reviewer of Intel MFD PMIC mfd: Convert Intel PMIC drivers to use SPDX identifier 1;5201;0c Reduce size of duplicated comments by switching to use SPDX identifier. mfd: Sort headers alphabetically for Intel PMIC drivers mfd: intel_soc_pmic_bxtwc: Chain power button IRQs as well mfd: intel_soc_pmic_crc: Use REGMAP_IRQ_REG() macro mfd: intel_soc_pmic_crc: Use DEFINE_RES_IRQ_NAMED() macro mfd: intel_msic: Use DEFINE_RES_IRQ() macro mfd: motorola-cpcap: Add audio-codec support mfd: mc13xxx-core: Fix PMIC shutdown when reading ADC values mfd: madera: Remove unused forward reference mfd: max77620: Convert to using %pOFn instead of device_node.name mfd: madera: Don't use regmap_read_poll_timeout to poll for BOOT_DONE ...
2018-10-24Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-nextLinus Torvalds2-0/+14
Pull networking updates from David Miller: 1) Add VF IPSEC offload support in ixgbe, from Shannon Nelson. 2) Add zero-copy AF_XDP support to i40e, from Björn Töpel. 3) All in-tree drivers are converted to {g,s}et_link_ksettings() so we can get rid of the {g,s}et_settings ethtool callbacks, from Michal Kubecek. 4) Add software timestamping to veth driver, from Michael Walle. 5) More work to make packet classifiers and actions lockless, from Vlad Buslov. 6) Support sticky FDB entries in bridge, from Nikolay Aleksandrov. 7) Add ipv6 version of IP_MULTICAST_ALL sockopt, from Andre Naujoks. 8) Support batching of XDP buffers in vhost_net, from Jason Wang. 9) Add flow dissector BPF hook, from Petar Penkov. 10) i40e vf --> generic iavf conversion, from Jesse Brandeburg. 11) Add NLA_REJECT netlink attribute policy type, to signal when users provide attributes in situations which don't make sense. From Johannes Berg. 12) Switch TCP and fair-queue scheduler over to earliest departure time model. From Eric Dumazet. 13) Improve guest receive performance by doing rx busy polling in tx path of vhost networking driver, from Tonghao Zhang. 14) Add per-cgroup local storage to bpf 15) Add reference tracking to BPF, from Joe Stringer. The verifier can now make sure that references taken to objects are properly released by the program. 16) Support in-place encryption in TLS, from Vakul Garg. 17) Add new taprio packet scheduler, from Vinicius Costa Gomes. 18) Lots of selftests additions, too numerous to mention one by one here but all of which are very much appreciated. 19) Support offloading of eBPF programs containing BPF to BPF calls in nfp driver, frm Quentin Monnet. 20) Move dpaa2_ptp driver out of staging, from Yangbo Lu. 21) Lots of u32 classifier cleanups and simplifications, from Al Viro. 22) Add new strict versions of netlink message parsers, and enable them for some situations. From David Ahern. 23) Evict neighbour entries on carrier down, also from David Ahern. 24) Support BPF sk_msg verdict programs with kTLS, from Daniel Borkmann and John Fastabend. 25) Add support for filtering route dumps, from David Ahern. 26) New igc Intel driver for 2.5G parts, from Sasha Neftin et al. 27) Allow vxlan enslavement to bridges in mlxsw driver, from Ido Schimmel. 28) Add queue and stack map types to eBPF, from Mauricio Vasquez B. 29) Add back byte-queue-limit support to r8169, with all the bug fixes in other areas of the driver it works now! From Florian Westphal and Heiner Kallweit. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (2147 commits) tcp: add tcp_reset_xmit_timer() helper qed: Fix static checker warning Revert "be2net: remove desc field from be_eq_obj" Revert "net: simplify sock_poll_wait" net: socionext: Reset tx queue in ndo_stop net: socionext: Add dummy PHY register read in phy_write() net: socionext: Stop PHY before resetting netsec net: stmmac: Set OWN bit for jumbo frames arm64: dts: stratix10: Support Ethernet Jumbo frame tls: Add maintainers net: ethernet: ti: cpsw: unsync mcast entries while switch promisc mode octeontx2-af: Support for NIXLF's UCAST/PROMISC/ALLMULTI modes octeontx2-af: Support for setting MAC address octeontx2-af: Support for changing RSS algorithm octeontx2-af: NIX Rx flowkey configuration for RSS octeontx2-af: Install ucast and bcast pkt forwarding rules octeontx2-af: Add LMAC channel info to NIXLF_ALLOC response octeontx2-af: NPC MCAM and LDATA extract minimal configuration octeontx2-af: Enable packet length and csum validation octeontx2-af: Support for VTAG strip and capture ...
2018-10-22dt-bindings: phy: Update SERDES_MAX to be SERDES_MAX + 1Gustavo A. R. Silva1-1/+1
SERDES_MAX is a valid value to index ctrl->phys in drivers/phy/mscc/phy-ocelot-serdes.c. But, currently, there is an out-of-bounds bug in the mentioned driver when reading from ctrl->phys, because the size of array ctrl->phys is SERDES_MAX. Partially fix this by updating SERDES_MAX to be SERDES6G_MAX + 1. Notice that this is the first part of the solution to the out-of-bounds bug mentioned above. Although this change is not dependent on any other one. Suggested-by: Quentin Schulz <[email protected]> Reviewed-by: Quentin Schulz <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-10-18Merge branches 'clk-imx6-mmdc', 'clk-qcom-krait', 'clk-rockchip' and ↵Stephen Boyd7-6/+15
'clk-smp2s11-match' into clk-next - iMX6 MMDC clks - Qualcomm Krait CPU clk support * clk-imx6-mmdc: clk: imx6q: add mmdc0 ipg clock clk: imx6sl: add mmdc ipg clocks clk: imx6sll: add mmdc1 ipg clock clk: imx6sx: add mmdc1 ipg clock clk: imx6ul: add mmdc1 ipg clock * clk-qcom-krait: clk: qcom: Add safe switch hook for krait mux clocks dt-bindings: clock: Document qcom,krait-cc clk: qcom: Add Krait clock controller driver dt-bindings: arm: Document qcom,kpss-gcc clk: qcom: Add KPSS ACC/GCC driver clk: qcom: Add support for Krait clocks clk: qcom: Add IPQ806X's HFPLLs clk: qcom: Add MSM8960/APQ8064's HFPLLs dt-bindings: clock: Document qcom,hfpll clk: qcom: Add HFPLL driver clk: qcom: Add support for High-Frequency PLLs (HFPLLs) ARM: Add Krait L2 register accessor functions * clk-rockchip: clk: rockchip: Fix static checker warning in rockchip_ddrclk_get_parent call clk: rockchip: use the newly added clock-id for hdmi on RK3066 clk: rockchip: add clock-id for HCLK_HDMI on rk3066 clk: rockchip: fix wrong mmc sample phase shift for rk3328 clk: rockchip: improve rk3288 pll rates for better hdmi output * clk-smp2s11-match: clk: s2mps11: Add used attribute to s2mps11_dt_match clk: s2mps11: Fix matching when built as module and DT node contains compatible
2018-10-18Merge branches 'clk-actions-reset', 'clk-imx7-init-critical', 'clk-mmp2-ids' ↵Stephen Boyd3-0/+114
and 'clk-at91-pmc-rework' into clk-next - Reset Controller (RMU) support for Actions Semi Owl S900 and S700 SoCs - Rework at91 PMC clock driver for new DT bindings * clk-actions-reset: clk: actions: Add Actions Semi S900 SoC Reset Management Unit support clk: actions: Add Actions Semi S700 SoC Reset Management Unit support clk: actions: Add Actions Semi Owl SoCs Reset Management Unit support dt-bindings: reset: Add binding constants for Actions Semi S900 RMU dt-bindings: reset: Add binding constants for Actions Semi S700 RMU dt-bindings: clock: Add reset controller bindings for Actions Semi Owl SoCs clk: actions: Cache regmap info in private clock descriptor * clk-imx7-init-critical: clk: imx7d: remove CLK_IS_CRITICAL flag for arm_a7_root_clk clk: imx: cpu clock should be always critical clk: imx: imx7d: remove clks_init_on array clk: imx: imx7d: remove unnecessary clocks from clks_init_on array * clk-mmp2-ids: clk: mmp2: fix the clock id for sdh2_clk and sdh3_clk * clk-at91-pmc-rework: clk: at91: move DT compatibility code to its own file clk: at91: add at91sam9rl PMC driver clk: at91: add at91sam9x5 PMCs driver clk: at91: add at91sam9260 PMC driver clk: at91: add sama5d2 PMC driver clk: at91: add sama5d4 pmc driver clk: at91: add new DT lookup function dt-bindings: clk: at91: Document new PMC binding clk: at91: add pmc_data struct and helpers clk: at91: allow clock registration from C code clk: at91: generated: set audio_pll_allowed in at91_clk_register_generated() clk: at91: audio-pll: separate registration from DT parsing clk: at91: h32mx: separate registration from DT parsing clk: at91: generated: SSCs don't have a gclk clk: at91: audio-pll: fix audio pmc type
2018-10-18Merge branch 'clk-ingenic-jz4725b' into clk-nextStephen Boyd1-0/+35
- Ingenic jz4725b CGU * clk-ingenic-jz4725b: clk: Add Ingenic jz4725b CGU driver dt-bindings: clock: Add jz4725b-cgu.h header dt-bindings: clock: ingenic: Explicitly list compatible strings clk: ingenic: Add proper Kconfig entries
2018-10-18Merge branch 'clk-qcom-qcs404' into clk-nextStephen Boyd1-0/+165
- Qualcomm QCS404 GCC support * clk-qcom-qcs404: clk: qcom: gcc: Add global clock controller driver for QCS404 clk: qcom: Export clk_alpha_pll_configure()
2018-10-18Merge branch 'clk-qcom-sdm660' into clk-nextStephen Boyd1-0/+156
- Qualcomm SDM660 GCC support * clk-qcom-sdm660: clk: qcom: gcc-sdm660: Add MODULE_LICENSE clk: qcom: Add Global Clock controller (GCC) driver for SDM660
2018-10-18Merge branches 'clk-samsung', 'clk-hisi3670' and 'clk-at91-div-0' into clk-nextStephen Boyd12-80/+365
- Hisilicon 3670 SoC support * clk-samsung: dt-bindings: clock: samsung: Add SPDX license identifiers clk: samsung: Use clk_hw API for calling clk framework from clk notifiers clk: samsung: exynos5420: Enable PERIS clocks for suspend clk: samsung: exynos5420: Define CLK_SECKEY gate clock only or Exynos5420 clk: samsung: exynos5433: Keep sclk_uart clocks enabled in suspend clk: samsung: Remove obsolete code for Exynos4412 ISP clocks clk: samsung: exynos5433: Add suspend state for TOP, CPIF & PERIC CMUs clk: samsung: Use NOIRQ stage for Exynos5433 clocks suspend/resume clk: samsung: exynos5420: Use generic helper for handling suspend/resume clk: samsung: exynos4: Use generic helper for handling suspend/resume clk: samsung: Add support for setting registers state before suspend clk: samsung: exynos5250: Use generic helper for handling suspend/resume clk: samsung: s5pv210: Use generic helper for handling suspend/resume clk: samsung: s3c64xx: Use generic helper for handling suspend/resume clk: samsung: s3c2443: Use generic helper for handling suspend/resume clk: samsung: s3c2412: Use generic helper for handling suspend/resume clk: samsung: s3c2410: Use generic helper for handling suspend/resume clk: samsung: Remove excessive include * clk-hisi3670: clk: hisilicon: Add clock driver for Hi3670 SoC dt-bindings: clk: hisilicon: Add bindings for Hi3670 clk * clk-at91-div-0: clk: at91: Fix division by zero in PLL recalc_rate()
2018-10-18Merge branch 'clk-ti' into clk-nextStephen Boyd3-68/+509
* clk-ti: clk: ti: Prepare for remove of OF node name clk: Clean up suspend/resume coding style clk: ti: Add functions to save/restore clk context clk: clk: Add clk_gate_restore_context function clk: Add functions to save/restore clock context en-masse clk: ti: dra7: add new clkctrl data clk: ti: dra7xx: rename existing clkctrl data as compat data clk: ti: am43xx: add new clkctrl data for am43xx clk: ti: am43xx: rename existing clkctrl data as compat data clk: ti: am33xx: add new clkctrl data for am33xx clk: ti: am33xx: rename existing clkctrl data as compat data clk: ti: clkctrl: replace dashes from clkdm name with underscore clk: ti: clkctrl: support multiple clkctrl nodes under a cm node dt-bindings: clock: dra7xx: add clkctrl indices for new data layout dt-bindings: clock: am43xx: add clkctrl indices for new data layout dt-bindings: clock: am33xx: add clkctrl indices for new data layout
2018-10-18Merge branches 'clk-mvebu-periph-pm', 'clk-meson', 'clk-allwinner', ↵Stephen Boyd1-0/+1
'clk-mvebu-dup' and 'clk-davinci' into clk-next - S2RAM support for Marvell mvebu periph clks * clk-mvebu-periph-pm: clk: mvebu: armada-37xx-periph: add suspend/resume support clk: mvebu: armada-37xx-periph: save the IP base address in the driver data * clk-meson: clk: meson: meson8b: use the regmap in the internal reset controller clk: meson: meson8b: register the clock controller early clk: meson-axg: pcie: drop the mpll3 clock parent clk: meson: axg: round audio system master clocks down clk: meson: clk-pll: drop hard-coded rates from pll tables clk: meson: clk-pll: remove od parameters clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary clk: meson: clk-pll: add enable bit * clk-allwinner: dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro clk: sunxi-ng: a64: Add max. rate constraint to video PLLs clk: sunxi-ng: a64: Add minimal rate for video PLLs clk: sunxi-ng: sun50i: h6: Add 2x fixed post-divider to MMC module clocks clk: sunxi-ng: a83t: Add max. rate constraint to video PLLs clk: sunxi-ng: nkmp: Add constraint for maximum rate clk: sunxi-ng: r40: Add max. rate constraint to video PLLs clk: sunxi-ng: h3/h5: Add max. rate constraint to pll-video clk: sunxi-ng: Add maximum rate constraint to NM PLLs clk: sunxi-ng: h6: fix PWM gate/reset offset clk: sunxi-ng: h6: fix bus clocks' divider position * clk-mvebu-dup: clk: mvebu: ap806: Remove superfluous of_clk_add_provider * clk-davinci: clk: davinci: kill davinci_clk_reset_assert/deassert()
2018-10-18Merge branches 'clk-qcom-sdm845-camcc' and 'clk-mtk-unused' into clk-nextStephen Boyd1-0/+116
- Qualcomm SDM845 camera clock controller * clk-qcom-sdm845-camcc: clk: qcom: Add camera clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Camera clock bindings * clk-mtk-unused: clk: mediatek: remove unused array audio_parents
2018-10-18Merge branch 'clk-renesas' into clk-nextStephen Boyd19-93/+207
* clk-renesas: (36 commits) clk: renesas: r7s9210: Add SPI clocks clk: renesas: r7s9210: Move table update to separate function clk: renesas: r7s9210: Convert some clocks to early clk: renesas: cpg-mssr: Add early clock support clk: renesas: r8a77970: Add TPU clock clk: renesas: r8a77990: Fix incorrect PLL0 divider in comment dt-bindings: clock: renesas: cpg-mssr: Document r8a774c0 clk: renesas: cpg-mssr: Add r8a774c0 support clk: renesas: Add r8a774c0 CPG Core Clock Definitions clk: renesas: r8a7743: Add r8a7744 support clk: renesas: Add r8a7744 CPG Core Clock Definitions dt-bindings: clock: renesas: cpg-mssr: Document r8a7744 binding dt-bindings: clock: renesas: Convert to SPDX identifiers clk: renesas: cpg-mssr: Add R7S9210 support clk: renesas: r8a77970: Add TMU clocks clk: renesas: r8a77970: Add CMT clocks clk: renesas: r9a06g032: Fix UART34567 clock rate clk: renesas: r8a77970: Add SD0H/SD0 clocks for SDHI clk: renesas: r8a77980: Add CMT clocks clk: renesas: r8a77990: Add missing I2C7 clock ...
2018-10-18Merge branches 'clk-spdx', 'clk-qcom-dfs', 'clk-smp2s11-include', ↵Stephen Boyd2-0/+12
'clk-qcom-8996-missing' and 'clk-qcom-qspi' into clk-next - Tag various drivers with SPDX license tags - Support dynamic frequency switching (DFS) on qcom SDM845 GCC - Only use s2mps11 dt-binding defines instead of redefining them in the driver - Add some more missing clks to qcom MSM8996 GCC - Quad SPI clks on qcom SDM845 * clk-spdx: clk: mvebu: use SPDX-License-Identifier clk: renesas: Convert to SPDX identifiers clk: renesas: use SPDX identifier for Renesas drivers clk: s2mps11,s3c64xx: Add SPDX license identifiers clk: max77686: Add SPDX license identifiers * clk-qcom-dfs: clk: qcom: Allocate space for NULL terimation in DFS table clk: qcom: gcc: Register QUPv3 RCGs for DFS on SDM845 clk: qcom: Add support for RCG to register for DFS * clk-smp2s11-include: clk: s2mps11: Use existing defines from bindings for clock IDs * clk-qcom-8996-missing: clk: qcom: Add some missing gcc clks for msm8996 * clk-qcom-qspi: clk: qcom: Add qspi (Quad SPI) clocks for sdm845 clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to header
2018-10-17clk: qcom: Add MSM8960/APQ8064's HFPLLsStephen Boyd1-0/+2
Describe the HFPLLs present on MSM8960 and APQ8064 devices. Acked-by: Rob Herring <[email protected]> (bindings) Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Sricharan R <[email protected]> Tested-by: Craig Tatlor <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-17clk: imx6q: add mmdc0 ipg clockAnson Huang1-1/+2
i.MX6Q has MMDC0 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-17clk: imx6sl: add mmdc ipg clocksAnson Huang1-1/+3
i.MX6SL has MMDC0 and MMDC1 ipg clock in CCM CCGR, add them into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-17clk: imx6sll: add mmdc1 ipg clockAnson Huang1-1/+2
i.MX6SLL has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-17clk: imx6sx: add mmdc1 ipg clockAnson Huang1-1/+2
i.MX6SX has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-17clk: imx6ul: add mmdc1 ipg clockAnson Huang1-1/+2
i.MX6UL has MMDC1 ipg clock in CCM CCGR, add it into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-17clk: at91: add new DT lookup functionAlexandre Belloni1-0/+15
Add a new DT lookup function to lookup for PMC clocks. Note that the #ifndef AT91_PMC_MOSCS section will be removed once all the platforms are converted. Signed-off-by: Alexandre Belloni <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16dt-bindings: clock: Add jz4725b-cgu.h headerPaul Cercueil1-0/+35
This will be used from the devicetree bindings to specify the clocks that should be obtained from the jz4725b-cgu driver. Signed-off-by: Paul Cercueil <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: qcom: gcc: Add global clock controller driver for QCS404Shefali Jain1-0/+165
Add the clocks supported in global clock controller which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them. Signed-off-by: Shefali Jain <[email protected]> Signed-off-by: Taniya Das <[email protected]> Co-developed-by: Taniya Das <[email protected]> Signed-off-by: Anu Ramanathan <[email protected]> [bamse, vkoul: rebase and tidyup for upstream] Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Vinod Koul <[email protected]> Acked-by: Rob Herring <[email protected]> [[email protected]: Lowercase hex] Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16clk: qcom: Add Global Clock controller (GCC) driver for SDM660Taniya Das1-0/+156
Add support for the global clock controller found on SDM660 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Based on CAF implementation. Signed-off-by: Taniya Das <[email protected]> [craig: rename parents to fit upstream, and other cleanups] Signed-off-by: Craig Tatlor <[email protected]> Acked-by: Rob Herring <[email protected]> [[email protected]: Rename gcc_660 to gcc_sdm660 and fix numbering of defines to avoid duplicates] Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16dt-bindings: clk: hisilicon: Add bindings for Hi3670 clkManivannan Sadhasivam1-0/+348
Add devicetree bindings for HiSilicon Hi3670 clock controller. Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16dt-bindings: reset: Add binding constants for Actions Semi S900 RMUManivannan Sadhasivam1-0/+65
Add device tree binding constants for Actions Semi S900 SoC Reset Management Unit (RMU). Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16dt-bindings: reset: Add binding constants for Actions Semi S700 RMUManivannan Sadhasivam1-0/+34
Add device tree binding constants for Actions Semi S700 SoC Reset Management Unit (RMU). Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-15dt-bindings: thermal: samsung: Add SPDX license identifierKrzysztof Kozlowski1-11/+1
Replace GPL license statement with SPDX license identifier (GPL-2.0+). Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2018-10-15dt-bindings: clock: samsung: Add SPDX license identifiersKrzysztof Kozlowski11-50/+17
Replace GPL license statements with SPDX license identifiers (GPL-2.0). Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2018-10-11clk: rockchip: add clock-id for HCLK_HDMI on rk3066Heiko Stuebner1-1/+2
RK3066 and RK3188 share most of the clock controller but the rk3066 does have an internal hdmi encoder and associated clock. Therefore add a clock-id so that this clock can be used. Signed-off-by: Heiko Stuebner <[email protected]>
2018-10-10Merge tag 'zynqmp-soc-clk-for-v4.20' of https://github.com/Xilinx/linux-xlnx ↵Arnd Bergmann1-0/+116
into next/drivers arm64: zynqmp: SoC CLK changes for v4.20 This patchset adds CCF compliant clock driver for ZynqMP. Clock driver queries supported clock information from firmware and regiters pll and output clocks with CCF. * tag 'zynqmp-soc-clk-for-v4.20' of https://github.com/Xilinx/linux-xlnx: drivers: clk: Add ZynqMP clock driver dt-bindings: clock: Add bindings for ZynqMP clock driver firmware: xilinx: Add zynqmp IOCTL API for device control Documentation: xilinx: Add documentation for eemi APIs Signed-off-by: Arnd Bergmann <[email protected]>
2018-10-10Merge tag 'reset-for-4.20' of git://git.pengutronix.de/git/pza/linux into ↵Arnd Bergmann1-0/+20
next/drivers Reset controller changes for v4.20 This adds a new driver for the PDC Global (Power Domain Controller) reset controller found on Qualcomm SDM845 SoCs, fixes a potential use-after-free issue in reset_controller_dev.of_xlate() callbacks from __of_reset_control_get(), and trivially fixes a documentation grammar issue. * tag 'reset-for-4.20' of git://git.pengutronix.de/git/pza/linux: reset: Fix potential use-after-free in __of_reset_control_get() reset: qcom: PDC Global (Power Domain Controller) reset controller dt-bindings: reset: Add PDC Global binding for SDM845 SoCs reset: Grammar s/more then once/more than once/ Signed-off-by: Arnd Bergmann <[email protected]>
2018-10-10Merge tag 'sh-pfc-for-v4.20-tag3' of ↵Linus Walleij1-0/+141
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.20 (take three) - Add support for the new RZ/N1D (R9A06G032) and RZ/N1S (R9A06G033) SoCs, - Add INTC-EX pin groups on R-Car E3.
2018-10-09dt-bindings: clock: Add bindings for ZynqMP clock driverRajan Vaja1-0/+116
Add documentation to describe Xilinx ZynqMP clock driver bindings. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2018-10-08dt-bindings: net: vsc8531: add two additional LED modes for VSC8584Quentin Schulz1-0/+2
The VSC8584 (and most likely other PHYs in the same generation) has two additional LED modes that can be picked, so let's add them. Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Andrew Lunn <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-10-05dt-bindings: add constants for Microsemi Ocelot SerDes driverQuentin Schulz1-0/+12
The Microsemi Ocelot has multiple SerDes and requires that the SerDes be muxed accordingly to the hardware representation. Let's add a constant for each SerDes available in the Microsemi Ocelot. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Quentin Schulz <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Signed-off-by: David S. Miller <[email protected]>
2018-10-05dt-bindings: clock: samsung: Add SPDX license identifiersKrzysztof Kozlowski11-50/+17
Replace GPL license statements with SPDX license identifiers (GPL-2.0). Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: Remove obsolete code for Exynos4412 ISP clocksMarek Szyprowski1-30/+0
Exynos4412 ISP clock are provided by separate Exynos4412 ISP clock driver, so support for them in Exynos4-clk driver can be removed. Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05reset: imx7: Add PCIE_CTRL_APPS_TURNOFFLeonard Crestez1-1/+3
This is required for the imx pci driver to send the PME_Turn_Off TLP. Signed-off-by: Leonard Crestez <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]> Acked-by: Philipp Zabel <[email protected]> Acked-by: Rob Herring <[email protected]>
2018-10-05dt-bindings: reset: Add PDC Global binding for SDM845 SoCsSibi Sankar1-0/+20
Add PDC Global (Power Domain Controller) binding for SDM845 SoCs. Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
2018-10-03dt-bindings: clock: dra7xx: add clkctrl indices for new data layoutTero Kristo1-68/+258
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03dt-bindings: clock: am43xx: add clkctrl indices for new data layoutTero Kristo1-0/+132
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03dt-bindings: clock: am33xx: add clkctrl indices for new data layoutTero Kristo1-0/+119
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-02dt-bindings: pinctrl: renesas,rzn1-pinctrl: documentationPhil Edworthy1-0/+141
The Renesas RZ/N1 device family PINCTRL node description. Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy <[email protected]> Reviewed-by: Jacopo Mondi <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-10-02Merge tag 'actions-arm64-dt-for-4.20' of ↵Arnd Bergmann1-0/+23
git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/dt Actions Semi arm64 based SoC DT for v4.20 This updates SPDX headers for remaining files. For S900 it adds clock, pinctrl, i2c and dma nodes. S900 SPS is added via topic branch (shared with driver). For S700 it adds clock nodes. * tag 'actions-arm64-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions: arm64: dts: actions: s700: Set UART clock references from CMU arm64: dts: actions: s700: Add Clock Management Unit arm64: dts: actions: s900: Add DMA Controller arm64: dts: actions: s900-bubblegum-96: Enable I2C1 and I2C2 arm64: dts: actions: s900: Add I2C controller nodes arm64: dts: actions: s900-bubblegum-96: Add gpio line names arm64: dts: actions: s900: Add gpio properties to pinctrl node arm64: dts: actions: s900: Add pinctrl node arm64: dts: actions: s900: Add SPS node arm64: dts: actions: s900: Source CMU clock for UARTs arm64: dts: actions: s900: Add Clock Management Unit nodes dt-bindings: power: Add Actions Semi S900 SPS arm64: dts: actions: Convert to new-style SPDX license identifiers Signed-off-by: Arnd Bergmann <[email protected]>
2018-10-02Merge tag 'actions-drivers+s900-sps-for-4.20' of ↵Arnd Bergmann1-0/+23
git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions into next/drivers Actions Semi SoC drivers for v4.20 #2 The SPS power domain driver is extended for S900 SoC. This required merging a topic branch for the new bindings header. * tag 'actions-drivers+s900-sps-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions: soc: actions: sps: Add S900 power domains dt-bindings: power: Add Actions Semi S900 SPS soc: actions: Update SPS help text for S700 soc: actions: Convert to SPDX license identifiers Signed-off-by: Arnd Bergmann <[email protected]>
2018-09-30dt-bindings: power: Add Actions Semi S900 SPSManivannan Sadhasivam1-0/+23
Define power domains for Actions Semi S900 SoC Smart Power System (SPS). Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Andreas Färber <[email protected]>
2018-09-28Merge tag 'renesas-drivers-for-v4.20' of ↵Arnd Bergmann3-0/+80
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers Renesas ARM Based SoC Drivers Updates for v4.20 * Convert to SPDX identifiers * R-Car V3M (r8a77970) and V3H (r8a77980): Document Timer Unit (TMU) bindings * RZ/G1N (r8a7744) and RZ/G1C (r8a77470) SoCs: - Document APMU and SMP enable method * RZ/G2M (r8a74a1), RZ/G1N (r8a7744) and RZ/G2E (r8a774c0) SoCs: - Add reset support - Add sysc support * RZ/G2M (r8a774a1), RZ/G2E (r8a774c0) and RZ/A2M (r7s9210) SoCs: - Add support for identifying SoC * RZ/A2M (r7s9210) SoC: - Add basic SoC setup support * tag 'renesas-drivers-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (21 commits) dt-bindings: apmu: Document r8a7744 support dt-bindings: timer: renesas: tmu: document R8A779{7|8}0 bindings dt-bindings: apmu: Document r8a77470 support soc: renesas: rcar-rst: Add support for RZ/G1N dt-bindings: reset: rcar-rst: Document r8a7744 reset module soc: renesas: rcar-sysc: Add r8a7744 support dt-bindings: power: rcar-sysc: Add r8a7744 power domain index macros dt-bindings: power: rcar-sysc: Document r8a7744 SYSC binding soc: renesas: rcar-rst: Add support for RZ/G2E dt-bindings: reset: rcar-rst: Document r8a774c0 rst soc: renesas: rcar-sysc: Add r8a774c0 support dt-bindings: power: rcar-sysc: Document r8a774c0 sysc dt-bindings: power: Add r8a774c0 SYSC power domain definitions soc: renesas: Identify RZ/G2E soc: renesas: convert to SPDX identifiers soc: renesas: rcar-rst: Add support for RZ/G2M soc: renesas: rcar-sysc: Add r8a774a1 support dt-bindings: power: Add r8a774a1 SYSC power domain definitions soc: renesas: identify RZ/A2 ARM: shmobile: Add basic RZ/A2 SoC support ... Signed-off-by: Arnd Bergmann <[email protected]>
2018-09-20dt-bindings: connector: Add support for USB-PD PPS APDOs to bindingsAdam Thomson1-0/+26
Add support for PPS APDOs to connector bindings so a port controller can specify support for PPS, as per existing FIXED/BATT/VAR PDOs. Signed-off-by: Adam Thomson <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-09-19clk: renesas: Add r8a774c0 CPG Core Clock DefinitionsFabrizio Castro1-0/+60
Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2g ("List of Clocks [RZ/G2E]") of the RZ/G2 Hardware User's Manual. Signed-off-by: Fabrizio Castro <[email protected]> Reviewed-by: Biju Das <[email protected]> Reviewed-by: Simon Horman <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
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