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2019-05-08Merge tag 'usb-5.2-rc1' of ↵Linus Torvalds1-0/+13
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb Pull USB/PHY updates from Greg KH: "Here is the big set of USB and PHY driver patches for 5.2-rc1 There is the usual set of: - USB gadget updates - PHY driver updates and additions - USB serial driver updates and fixes - typec updates and new chips supported - mtu3 driver updates - xhci driver updates - other tiny driver updates Nothing really interesting, just constant forward progress. All of these have been in linux-next for a while with no reported issues. The usb-gadget and usb-serial trees were merged a bit "late", but both of them had been in linux-next before they got merged here last Friday" * tag 'usb-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb: (206 commits) USB: serial: f81232: implement break control USB: serial: f81232: add high baud rate support USB: serial: f81232: clear overrun flag USB: serial: f81232: fix interrupt worker not stop usb: dwc3: Rename DWC3_DCTL_LPM_ERRATA usb: dwc3: Fix default lpm_nyet_threshold value usb: dwc3: debug: Print GET_STATUS(device) tracepoint usb: dwc3: Do core validation early on probe usb: dwc3: gadget: Set lpm_capable usb: gadget: atmel: tie wake lock to running clock usb: gadget: atmel: support USB suspend usb: gadget: atmel_usba_udc: simplify setting of interrupt-enabled mask dwc2: gadget: Fix completed transfer size calculation in DDMA usb: dwc2: Set lpm mode parameters depend on HW configuration usb: dwc2: Fix channel disable flow usb: dwc2: Set actual frame number for completed ISOC transfer usb: gadget: do not use __constant_cpu_to_le16 usb: dwc2: gadget: Increase descriptors count for ISOC's usb: introduce usb_ep_type_string() function usb: dwc3: move synchronize_irq() out of the spinlock protected block ...
2019-05-07Merge branches 'clk-stm32f4', 'clk-tegra', 'clk-at91', 'clk-sifive-fu540' ↵Stephen Boyd1-2/+5
and 'clk-spdx' into clk-next - Support for STM32F769 - Rework AT91 sckc DT bindings - Fix slow RC oscillator issue on sama5d3 - AT91 sam9x60 PMC support - SiFive FU540 PRCI and PLL support * clk-stm32f4: clk: stm32mp1: Add ddrperfm clock clk: stm32: Introduce clocks of STM32F769 board * clk-tegra: clk: tegra: divider: Mark Memory Controller clock as read-only clk: tegra: emc: Replace BUG() with WARN_ONCE() clk: tegra: emc: Fix EMC max-rate clamping clk: tegra: emc: Support multiple RAM codes clk: tegra: emc: Don't enable EMC clock manually clk: tegra124: Remove lock-enable bit from PLLM clk: tegra: Fix PLLM programming on Tegra124+ when PMC overrides divider clk: tegra: Don't enable already enabled PLLs * clk-at91: clk: at91: Mark struct clk_range as const clk: at91: add sam9x60 pmc driver dt-bindings: clk: at91: add bindings for SAM9X60 pmc clk: at91: add sam9x60 PLL driver clk: at91: master: Add sam9x60 support clk: at91: usb: Add sam9x60 support clk: at91: allow configuring generated PCR layout clk: at91: allow configuring peripheral PCR layout clk: at91: sckc: handle different RC startup time clk: at91: modernize sckc binding dt-bindings: clock: at91: new sckc bindings * clk-sifive-fu540: clk: sifive: add a driver for the SiFive FU540 PRCI IP block clk: analogbits: add Wide-Range PLL library dt-bindings: clk: add documentation for the SiFive PRCI driver * clk-spdx: clk: sunxi-ng: Use the correct style for SPDX License Identifier clk: sprd: Use the correct style for SPDX License Identifier clk: renesas: Use the correct style for SPDX License Identifier clk: qcom: Use the correct style for SPDX License Identifier clk: davinci: Use the correct style for SPDX License Identifier clk: actions: Use the correct style for SPDX License Identifier
2019-05-07Merge branches 'clk-hisi', 'clk-lochnagar', 'clk-allwinner', 'clk-rockchip' ↵Stephen Boyd1-1/+1
and 'clk-qoriq' into clk-next - Mark UFS clk as critical on Hi-Silicon hi3660 SoCs - Support for Cirrus Logic Lochnagar clks * clk-hisi: clk: hi3660: Mark clk_gate_ufs_subsys as critical * clk-lochnagar: clk: lochnagar: Add support for the Cirrus Logic Lochnagar clk: lochnagar: Add initial binding documentation * clk-allwinner: clk: sunxi-ng: sun5i: Export the MBUS clock clk: sunxi-ng: a83t: Add pll-video0 as parent of csi-mclk clk: sunxi-ng: h6: Allow video & vpu clocks to change parent rate clk: sunxi-ng: h6: Preset hdmi-cec clock parent clk: sunxi: Add Kconfig options clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset clk: sunxi-ng: Allow DE clock to set parent rate * clk-rockchip: clk: rockchip: undo several noc and special clocks as critical on rk3288 clk: rockchip: add a COMPOSITE_DIV_OFFSET clock-type clk: rockchip: Turn on "aclk_dmac1" for suspend on rk3288 clk: rockchip: Limit use of USB PHY clock to USB on rk3288 clk: rockchip: Fix video codec clocks on rk3288 clk: rockchip: Make rkpwm a critical clock on rk3288 clk: rockchip: fix wrong clock definitions for rk3328 * clk-qoriq: clk: qoriq: increase array size of cmux_to_group dt-bindings: qoriq-clock: Add ls1028a chip compatible string clk: qoriq: Add ls1028a clock configuration clk: qoriq: add more PLL divider clocks support dt-bindings: qoriq-clock: add more PLL divider clocks support
2019-05-07Merge branches 'clk-sa', 'clk-aspeed', 'clk-samsung', 'clk-ingenic' and ↵Stephen Boyd2-1/+3
'clk-zynq' into clk-next - Various static analysis fixes/finds - Video Engine (ECLK) support on Aspeed SoCs - Xilinx ZynqMP Versal platform support - Convert Xilinx ZynqMP driver to be struct oriented * clk-sa: clk: mvebu: fix spelling mistake "gatable" -> "gateable" clk: ux500: add range to usleep_range clk: tegra: Make tegra_clk_super_mux_ops static clk: davinci: cfgchip: use PTR_ERR_OR_ZERO in da8xx_cfgchip_register_div4p5 * clk-aspeed: clk: Aspeed: Setup video engine clocking * clk-samsung: clk: samsung: exynos5410: Add gate clock for ADC clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410 clk: samsung: dt-bindings: Put CLK_UART3 in order * clk-ingenic: clk: ingenic: jz4725b: Add UDC PHY clock dt-bindings: clock: jz4725b-cgu: Add UDC PHY clock * clk-zynq: clk: zynqmp: use structs for clk query responses clk: zynqmp: fix check for fractional clock clk: zynqmp: do not export zynqmp_clk_register_* functions clk: zynqmp: fix kerneldoc of __zynqmp_clock_get_parents drivers: clk: Update clock driver to handle clock attribute drivers: clk: zynqmp: Allow zero divisor value
2019-05-07Merge branches 'clk-doc', 'clk-more-critical', 'clk-meson' and ↵Stephen Boyd4-21/+22
'clk-basic-be' into clk-next - Remove clk_readl() and introduce BE versions of basic clk types * clk-doc: clk: Drop duplicate clk_register() documentation clk: Document and simplify clk_core_get_rate_nolock() clk: Remove 'flags' member of struct clk_fixed_rate clk: nxp: Drop 'flags' on fixed_rate clk macro clk: Document __clk_mux_determine_rate() clk: Document CLK_MUX_READ_ONLY mux flag clk: Document deprecated things clk: Collapse gpio clk kerneldoc * clk-more-critical: clk: highbank: Convert to CLK_IS_CRITICAL * clk-meson: (21 commits) clk: meson: axg-audio: add g12a support clk: meson: axg-audio: don't register inputs in the onecell data clk: meson: axg_audio: replace prefix axg by aud dt-bindings: clk: axg-audio: add g12a support clk: meson: meson8b: add the video decoder clock trees clk: meson: meson8b: add the VPU clock trees clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2 clk: meson: meson8b: use a separate clock table for Meson8m2 dt-bindings: clock: meson8b: export the video decoder clocks clk: meson-g12a: add video decoder clocks dt-bindings: clock: meson8b: export the VPU clock clk: meson-g12a: add PCIE PLL clocks dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN clk: meson-pll: add reduced specific clk_ops for G12A PCIe PLL dt-bindings: clock: meson8b: drop the "ABP" clock definition clk: meson: g12a: add cpu clocks dt-bindings: clk: g12a-clkc: add VDEC clock IDs dt-bindings: clock: axg-audio: unexpose controller inputs dt-bindings: clk: g12a-clkc: add PCIE PLL clock ID clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock id ... * clk-basic-be: clk: core: replace clk_{readl,writel} with {readl,writel} clk: core: remove powerpc special handling powerpc/512x: mark clocks as big endian clk: mux: add explicit big endian support clk: multiplier: add explicit big endian support clk: gate: add explicit big endian support clk: fractional-divider: add explicit big endian support clk: divider: add explicit big endian support
2019-05-07Merge branches 'clk-renesas', 'clk-qcom', 'clk-mtk', 'clk-milbeaut' and ↵Stephen Boyd5-1/+653
'clk-imx' into clk-next - Qualcomm QCS404 CDSP clk support - Qualcomm QCS404 Turing clk support - Mediatek MT8183 clock support - Mediatek MT8516 clock support - Milbeaut M10V clk controller support * clk-renesas: clk: renesas: rcar-gen3: Remove unused variable clk: renesas: rcar-gen3: Fix cpg_sd_clock_round_rate() return value clk: renesas: r8a77980: Fix RPC-IF module clock's parent clk: renesas: rcar-gen3: Rename DRIF clocks clk: renesas: rcar-gen3: Correct parent clock of Audio-DMAC clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC clk: renesas: rcar-gen3: Correct parent clock of HS-USB clk: renesas: rcar-gen3: Correct parent clock of EHCI/OHCI clk: renesas: r8a774c0: Add Z2 clock clk: renesas: r8a77990: Add Z2 clock clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents math64: New DIV64_U64_ROUND_CLOSEST helper clk: renesas: rcar-gen3: Remove CLK_TYPE_GEN3_Z2 clk: renesas: rcar-gen3: Parameterise Z and Z2 clock offset clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor clk: renesas: r9a06g032: Add missing PCI USB clock clk: renesas: r7s9210: Always use readl() clk: renesas: rcar-gen3: Pass name/offset to cpg_sd_clk_register() * clk-qcom: clk: qcom: Skip halt checks on gcc_pcie_0_pipe_clk for 8998 clk: qcom: Add QCS404 TuringCC clk: qcom: branch: Add AON clock ops dt-bindings: clock: Introduce Qualcomm Turing Clock controller clk: qcom: gcc-qcs404: Add CDSP related clocks and resets * clk-mtk: clk: mediatek: add clock driver for MT8516 dt-bindings: mediatek: apmixedsys: add support for MT8516 dt-bindings: mediatek: infracfg: add support for MT8516 dt-bindings: mediatek: topckgen: add support for MT8516 clk: mediatek: Allow changing PLL rate when it is off clk: mediatek: Add MT8183 clock support clk: mediatek: Add configurable pcw_chg_reg to mtk_pll_data clk: mediatek: Add dt-bindings for MT8183 clocks dt-bindings: ARM: Mediatek: Document bindings for MT8183 clk: mediatek: Add configurable pcwibits and fmin to mtk_pll_data clk: mediatek: Add new clkmux register API clk: mediatek: Disable tuner_en before change PLL rate * clk-milbeaut: clock: milbeaut: Add Milbeaut M10V clock controller dt-bindings: clock: milbeaut: add Milbeaut clock description * clk-imx: clk: imx: correct pfdv2 gate_bit/vld_bit operations clk: imx: clk-pllv3: mark expected switch fall-throughs clk: imx8mq: Add dsi_ipg_div clk: imx: pllv4: add fractional-N pll support clk: imx: keep uart clock on during system boot clk: imx: correct i.MX7D AV PLL num/denom offset clk: imx6sll: Fix mispelling uart4_serial as serail clk: imx: pll14xx: drop unused variable clk: imx: rename clk-imx51-imx53.c to clk-imx5.c clk: imx5: Fix i.MX50 ESDHC clock registers clk: imx5: Fix i.MX50 mainbus clock registers clk: imx: Remove unused imx_get_clk_hw_fixed dt-bindings: clock: imx7ulp: remove SNVS clock clk: imx7ulp: remove snvs clock
2019-05-03Merge 5.1-rc7 into usb-nextGreg Kroah-Hartman2-1/+22
We need this to make the usb-gadget branch merge cleaner. And for testing to keep from hitting the same issues already fixed. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-04-28Merge tag 'imx-bindings-5.2' of ↵Olof Johansson1-17/+8
git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt i.MX DT bindings update for 5.2: - Add vendor prefix for TQ Systems GmbH, Rakuten Kobo and Menlo Systems GmbH. - Add DT schema for SoC i.MX8MM and i.MX50, and board ZII VF610, VF610 SPB4, i.MX7 RPU2, i.MX7S TQ MBa7, M53 Menlo and Eckelmann ci4x10. - Update imx-scu bindings on resource table and general interrupt support. - Add bindings for i.MX MMDC memory controller. - Update i.MX7D ADC bindings to add missing '#io-channel-cells' property. * tag 'imx-bindings-5.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: dt-bindings: iio: imx7d-adc: Add #io-channel-cells to required dt-bindings: arm: fsl: Add support for ZII i.MX7 RPU2 board dt-bindings: arm: fsl: Add devicetree binding for M53 Menlo board. dt-bindings: fsl: scu: add general interrupt support dt-bindings: arm: fsl: Add i.MX50 based boards dt-bindings: Add vendor prefix for Rakuten Kobo, Inc. dt-bindings: arm: add TQ boards dt-bindings: add vendor prefix for TQ Systems GmbH dt-bindings: arm: fsl: Add support for ZII VF610 SPB4 dt-bindings: arm: fsl: Add supported ZII VF610 boards to DT schema dt-bindings: arm: imx: Add the soc binding for imx8mm dt-bindings: arm: fsl: Add devicetree binding for Eckelmann ci4x10 dt-bindings: memory-controllers: freescale: add MMDC binding doc of: Add vendor prefix for Menlo Systems GmbH bindings: fsl-imx-sdma: Document fsl,imx8mq-sdma compatbile string dt-bindings: firmware: imx-scu: add new resources to scu resource table dt-bindings: firmware: imx-scu: remove unused resources from scu resource table Signed-off-by: Olof Johansson <[email protected]>
2019-04-28Merge tag 'amlogic-dt64-2' of ↵Olof Johansson5-22/+16
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt arm64: dts: Amlogic updates for v5.2, round 2 - add display/gfx support for G12a boards - enable USB for g12a boards * tag 'amlogic-dt64-2' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (26 commits) arm64: dts: meson-g12a-u200: Add support for Video Display arm64: dts: meson-g12a-sei510: Add support for Video Display arm64: dts: meson-g12a-x96-max: Add support for Video Display arm64: dts: meson-g12a: Add AO-CEC nodes arm64: dts: meson-g12a: Add VPU and HDMI related nodes arm64: dts: meson-g12a-x96-max: Enable USB arm64: dts: meson-g12a-u200: Enable USB arm64: dts: meson-g12a-sei510: Enable USB arm64: dts: meson-g12a-sei510: Add ADC Key and BT support arm64: dts: meson-g12a-u200: add regulators arm64: dts: meson: g12a: Add mali-g31 gpu node arm64: dts: meson: g12a: Add G12A USB nodes arm64: dts: meson: g12a: Add SAR ADC node dt-bindings: power: amlogic, meson-gx-pwrc: Add G12A compatible arm64: dts: meson-gxm: Add Mali-T820 node dt-bindings: gpu: mali-midgard: Add resets property dt-bindings: clock: meson8b: export the video decoder clocks dt-bindings: clock: meson8b: export the VPU clock dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCIN dt-bindings: clock: meson8b: drop the "ABP" clock definition ... Signed-off-by: Olof Johansson <[email protected]>
2019-04-28Merge tag 'renesas-dt-bindings-for-v5.2' of ↵Olof Johansson1-1/+0
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into arm/dt Renesas ARM Based SoC DT Bindings Updates for v5.2 * R-Car M3-N (r8a77965) SoC - Remove non-existent A3IR power domain * Add vendor prefix for Silicon Linux * tag 'renesas-dt-bindings-for-v5.2' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: dt-bindings: power: r8a77965: Remove non-existent A3IR power domain dt-bindings: Add vendor prefix for Silicon Linux. Signed-off-by: Olof Johansson <[email protected]>
2019-04-28Merge tag 'omap-for-v5.2/dt-am3-signed' of ↵Olof Johansson2-1/+130
git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt Add am335x pinmux defines and start using them This series of changes adds a new pinmux instance defines for am335x, and a new AM33XX_PADCONF macro. And then the rest of the series updates the dts files to use it. The reasons for doing this is the pinmux configuration has been hard to use and read. And we need to do this for eventually for moving to use values. This change is done one machine at a time, and can be easily reverted as needed in case of unexpected trouble. The old macro is still working, and we're planning to keep it around until we eventually change to use * tag 'omap-for-v5.2/dt-am3-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (38 commits) ARM: dts: am335x: wega: Replaced register offsets with defines ARM: dts: am335x: sl50: Replaced register offsets with defines ARM: dts: am335x: shc: Replaced register offsets with defines ARM: dts: am335x: sbc-t335: Replaced register offsets with defines ARM: dts: am335x: sancloud-bbe: Replaced register offsets with defines ARM: dts: am335x: phycore-som: Replaced register offsets with defines ARM: dts: am335x: pepper: Replaced register offsets with defines ARM: dts: am335x: pdu001: Replaced register offsets with defines ARM: dts: am335x: pcm-953: Replaced register offsets with defines ARM: dts: am335x: osd335x-common: Replaced register offsets with defines ARM: dts: am335x: osd3358-sm-red: Replaced register offsets with defines ARM: dts: am335x: nano: Replaced register offsets with defines ARM: dts: am335x: moxa-uc-8100-me-t: Replaced register offsets with defines ARM: dts: am335x: moxa-uc-2101: Replaced register offsets with defines ARM: dts: am335x: moxa-uc-2100-common: Replaced register offsets with defines ARM: dts: am335x: lxm: Replaced register offsets with defines ARM: dts: am335x: igep0033: Replaced register offsets with defines ARM: dts: am335x: icev2: Replaced register offsets with defines ARM: dts: am335x: evmsk: Replaced register offsets with defines ARM: dts: am335x: evm: Replaced register offsets with defines ... Signed-off-by: Olof Johansson <[email protected]>
2019-04-25dt-bindings: mediatek: apmixedsys: add support for MT8516Fabien Parent1-0/+10
Add binding documentation of apmixedsys for MT8516 SoC. Signed-off-by: Fabien Parent <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-04-25dt-bindings: mediatek: infracfg: add support for MT8516Fabien Parent1-0/+9
Add binding documentation of infracfg for MT8516 SoC. Signed-off-by: Fabien Parent <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-04-25dt-bindings: mediatek: topckgen: add support for MT8516Fabien Parent1-0/+192
Add binding documentation of topckgen for MT8516 SoC. Signed-off-by: Fabien Parent <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-04-25clk: stm32: Introduce clocks of STM32F769 boardGabriel Fernandez1-2/+5
STM32F769 clocks are derived from STM32746 clocks. main differences are: - new source clock for SAI1 and SAI2 (HSI or HSE) - Add DFSDM & DSI clocks Signed-off-by: Gabriel Fernandez <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-04-23dt-bindings: pinctrl: stm32: add new entry for package informationAlexandre Torgue1-0/+6
Add "st,package" entry. Possibles values are: -STM32MP_PKG_AA for LFBGA448 (18*18) package -STM32MP_PKG_AB for LFBGA354 (16*16) package -STM32MP_PKG_AC for TFBGA361 (12*12) package -STM32MP_PKG_AD for TFBGA257 (10*10) package Signed-off-by: Alexandre Torgue <[email protected]> Signed-off-by: Linus Walleij <[email protected]>
2019-04-21Merge 5.1-rc6 into staging-nextGreg Kroah-Hartman2-1/+22
We want the fixes in here as well as this resolves an iio driver merge issue. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-04-17dt-bindings: phy: ti: Add dt binding documentation for SERDES in AM654x SoCKishon Vijay Abraham I1-0/+13
AM654x has two SERDES instances. Each instance has three input clocks (left input, externel reference clock and right input) and two output clocks (left output and right output) in addition to a PLL mux clock which the SERDES uses for Clock Multiplier Unit (CMU refclock). The PLL mux clock can select from one of the three input clocks. The right output can select between left input and external reference clock while the left output can select between the right input and external reference clock. The left and right input reference clock of SERDES0 and SERDES1 respectively are connected to the SoC clock. In the case of two lane SERDES personality card, the left input of SERDES1 is connected to the right output of SERDES0 in a chained fashion. See section "Reference Clock Distribution" of AM65x Sitara Processors TRM (SPRUID7 – April 2018) for more details. Add dt-binding documentation in order to represent all these different configurations in device tree. Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2019-04-15Merge branch 'reset/meson-g12a' of git://git.pengutronix.de/pza/linux into ↵Kevin Hilman1-1/+4
v5.2/dt64 * 'reset/meson-g12a' of git://git.pengutronix.de/pza/linux: dt-bindings: reset: meson-g12a: Add missing USB2 PHY resets
2019-04-11dt-bindings: clock: jz4725b-cgu: Add UDC PHY clockPaul Cercueil1-0/+1
Add macro for the UDC PHY clock of the JZ4725B. Signed-off-by: Paul Cercueil <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-04-11dt-bindings: clock: Introduce Qualcomm Turing Clock controllerBjorn Andersson1-0/+15
Add devicetree binding for the turing clock controller found in QCS404. Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-04-11clk: qcom: gcc-qcs404: Add CDSP related clocks and resetsBjorn Andersson1-0/+5
Add the clocks and resets need in order to control the Turing remoteproc. Signed-off-by: Bjorn Andersson <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-04-11clk: mediatek: Add dt-bindings for MT8183 clocksWeiyi Lu1-0/+422
Add MT8183 clock dt-bindings, include topckgen, apmixedsys, infracfg, mcucfg and subsystem clocks. Signed-off-by: Weiyi Lu <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-04-10clk: sunxi-ng: sun5i: Export the MBUS clockMaxime Ripard1-1/+1
The MBUS clock is used by the MBUS controller, so let's export it so that we can use it in our DT node. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2019-04-09dt-bindings: clock: sifive: add FU540-C000 PRCI clock constantsPaul Walmsley1-0/+18
Add preprocessor macros for the important PRCI output clocks that are needed by both the FU540 PRCI driver and DT data. Details are available in the FU540 manual in Chapter 7 of https://static.dev.sifive.com/FU540-C000-v1.0.pdf Signed-off-by: Paul Walmsley <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
2019-04-08ARM: dts: am33xx: Added AM33XX_PADCONF macroChristina Quast1-0/+1
AM33XX_PADCONF takes three instead of two parameters, to make future changes to #pinctrl-cells easier. For old boards which are not mainlined, we left the AM33XX_IOPAD macro. Signed-off-by: Christina Quast <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2019-04-08ARM: dts: am33xx: Added macros for numeric pinmux addressesChristina Quast1-1/+129
The values are extraced from the "AM335x SitaraTM Processors Technical Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on the file autogenerated by TI PinMux. Signed-off-by: Christina Quast <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2019-04-08dt-bindings: clk: axg-audio: add g12a supportJerome Brunet1-0/+10
Add a new compatible string and additional clock ids for audio clock controller of the g12a SoC family. Signed-off-by: Jerome Brunet <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-04-04dt-bindings: iio/temperature: Add thermocouple types (and doc)Patrick Havelange1-0/+16
This patch introduces common thermocouple types used by various temperature sensors. Also a brief documentation explaining this "thermocouple-type" property. Signed-off-by: Patrick Havelange <[email protected]> Signed-off-by: Jonathan Cameron <[email protected]>
2019-04-01dt-bindings: clock: meson8b: export the video decoder clocksMartin Blumenstingl1-0/+4
Export the four video decoder clocks so they can be used by the video decoder driver: - VDEC_1 - VDEC_HCODEC - VDEC_2 - VDEC_HEVC Signed-off-by: Martin Blumenstingl <[email protected]> Acked-by: Jerome Brunet <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-04-01dt-bindings: clock: meson8b: export the VPU clockMartin Blumenstingl1-0/+1
The VPU clock is an input the the "VPU" (Video Processing Unit), which is one of the components of the display controller. Signed-off-by: Martin Blumenstingl <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Jerome Brunet <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-04-01dt-bindings: clock: g12a-aoclk: expose CLKID_AO_CTS_OSCINNeil Armstrong1-0/+1
When submitted v2 of the G12A AO-CLK IDs, the CLKID_AO_CTS_OSCIN was moved to the internal non-exported bindings, but this clock is necessary for the second AO-CEC-B module since it embeds the 32768Hz dual-divider clock generator unlike the AO-CEC-A module. Export it back to the public bindings. Fixes: be3d960b0aeb ("dt-bindings: clk: add G12A AO Clock and Reset Bindings") Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-04-01dt-bindings: clock: meson8b: drop the "ABP" clock definitionMartin Blumenstingl1-1/+0
Commit 8e1dd17c8b0e3f ("dt-bindings: clock: meson8b: export the CPU post dividers") added a new clock ID "CLKID_ABP" which contains a typo. This was fixed by adding a new (typo-free) #define CLKID_APB in commit 40d08f774c17ad ("dt-bindings: clock: meson8b: add APB clock definition"). Now that the new #define is used by the driver we can remove the old one (because the old one is not used anywhere). Signed-off-by: Martin Blumenstingl <[email protected]> Acked-by: Neil Armstrong <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-04-01dt-bindings: clk: g12a-clkc: add VDEC clock IDsMaxime Jourdan1-0/+3
Expose the three clocks related to the video decoder. Signed-off-by: Maxime Jourdan <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-04-01dt-bindings: clock: axg-audio: unexpose controller inputsJerome Brunet1-20/+0
Remove the bindings ID of the clock input of the controller. These clocks are purely internal to the controller, exposing them was a mistake. Actually, these should not even be in the provider and have IDs to begin with. Unexpose these IDs before: * someone starts using them (even if there no valid reason to do so) * the actual clocks are removed. The fact that they exist is just the result of an ugly hack. This will be resolved in CCF when we can reference DT directly in parent table. Signed-off-by: Jerome Brunet <[email protected]> Acked-by: Maxime Jourdan <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-03-25dt-bindings: reset: meson-g12a: Add missing USB2 PHY resetsNeil Armstrong1-1/+4
The G12A Documentation lacked these 2 reset lines, but they are present and used for each USB 2 PHYs. Add them to the dt-bindings for the upcoming USB support. Fixes: dbfc54534dfc ("dt-bindings: reset: meson: add g12a bindings") Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
2019-03-22clk: samsung: dt-bindings: Add ADC clock ID to Exynos5410Krzysztof Kozlowski1-0/+1
Add ID for TSADC clock to Exynos5410. Choose the same value of ID as in Exynos5420 to make it simpler/compatible in future (although clock driver code is not shared). Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2019-03-22clk: samsung: dt-bindings: Put CLK_UART3 in orderKrzysztof Kozlowski1-1/+1
Order the CLK_UART3 by ID. No change in functionality. Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2019-03-20dt-bindings: clock: imx7ulp: remove SNVS clockAnson Huang1-1/+0
Since i.MX7ULP B0 chip, SNVS module is moved into M4 domain, so remove it from Linux clock table. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-03-19dt-bindings: clk: g12a-clkc: add PCIE PLL clock IDNeil Armstrong1-0/+1
Add a clock ID for the reference clock feeding the USB3+PCIe Combo PHY. Signed-off-by: Neil Armstrong <[email protected]> Acked-by: Jerome Brunet <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-03-19clk: g12a-aoclk: re-export CLKID_AO_SAR_ADC_SEL clock idNeil Armstrong1-0/+1
When submitted v2 of the G12A AO-CLK IDs, the SAR_ADC_SEL ID was moved to the internal non-exported bindings, but this clock is necessary and mandatory for the SAR ADC bindings. Export it back to the public bindings. Fixes: be3d960b0aeb ("dt-bindings: clk: add G12A AO Clock and Reset Bindings") Signed-off-by: Neil Armstrong <[email protected]> Acked-by: Jerome Brunet <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-03-19clk: meson-g12a: add cpu clock bindingsNeil Armstrong1-0/+1
Add Amlogic G12A Family CPU clocks bindings, only export CPU_CLK since it should be the only ID used. Signed-off-by: Neil Armstrong <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Jerome Brunet <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-03-19dt-bindings: firmware: imx-scu: add new resources to scu resource tableAnson Huang1-2/+8
Add new resources as below according to latest system controller firmware for new features: IMX_SC_R_PERF IMX_SC_R_OCRAM IMX_SC_R_DMA_5_CH0 IMX_SC_R_DMA_5_CH1 IMX_SC_R_DMA_5_CH2 IMX_SC_R_DMA_5_CH3 IMX_SC_R_ATTESTATION Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-03-19dt-bindings: firmware: imx-scu: remove unused resources from scu resource tableAnson Huang1-15/+0
Removes below resources which were defined during pre-silicon phase and the real silicons do NOT have them, they have never been used, latest system controller firmware also removed them: IMX_SC_R_DC_0_CAPTURE0 IMX_SC_R_DC_0_CAPTURE1 IMX_SC_R_DC_0_INTEGRAL0 IMX_SC_R_DC_0_INTEGRAL1 IMX_SC_R_DC_0_FRAC1 IMX_SC_R_DC_1_CAPTURE0 IMX_SC_R_DC_1_CAPTURE1 IMX_SC_R_DC_1_INTEGRAL0 IMX_SC_R_DC_1_INTEGRAL1 IMX_SC_R_DC_1_FRAC1 IMX_SC_R_GPU_3_PID0 IMX_SC_R_M4_0_SIM IMX_SC_R_M4_0_WDOG IMX_SC_R_M4_1_SIM IMX_SC_R_M4_1_WDOG Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Dong Aisheng <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-03-18include: dt-binding: clock: Rename zynqmp header fileJolly Shah1-8/+18
Rename file name of ZynqMP clk dt-bindings to align with file name of reset and power dt-bindings. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2019-03-18dt-bindings: power: r8a77965: Remove non-existent A3IR power domainGeert Uytterhoeven1-1/+0
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) removed the A3IR power domain on R-Car M3-N, as this SoC does not have an Image Processing Unit (IMP-X5). As of commit d8c6557bc93be73e ("arm64: dts: renesas: r8a77965: Remove non-existent IPMMU-IR"), this definition is no longer used from DT, and thus can be removed. Fixes: a527709b78b3c997 ("soc: renesas: rcar-sysc: Add R-Car M3-N support") Signed-off-by: Geert Uytterhoeven <[email protected]> Reviewed-by: Fabrizio Castro <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2019-03-14Merge tag 'clk-for-linus' of ↵Linus Torvalds19-111/+662
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk subsystem updates from Stephen Boyd: "We have a fairly balanced mix of clk driver updates and clk framework updates this time around. It's the usual pile of new drivers for new hardware out there and the normal small fixes and updates, but then we have some core framework changes too. In the core framework, we introduce support for a clk_get_optional() API to get clks that may not always be populated and a way to devm manage clkdev lookups registered by provider drivers. We also do some refactoring to simplify the interface between clkdev and the common clk framework so we can reuse the DT parsing and clk_get() path in provider drivers in the future. This work will continue in the next few cycles while we convert how providers specify clk parents. On the driver side, the biggest part of the dirstat is the Amlogic clk driver that got support for the G12A SoC. It dominates with almost half the overall diff, while the second largest part of the diff is in the i.MX clk driver that gained support for imx8mm SoCs. After that, we have the Actions Semiconductor and Qualcomm drivers rounding out the big part of the dirstat because they both got new hardware support for SoCs. The rest is just various updates and non-critical fixes for existing drivers. Core: - Convert a few clk bindings to JSON schema format - Add a {devm_}clk_get_optional() API - Add devm_clk_hw_register_clkdev() API to manage clkdev lookups - Start rewriting clk parent registration and supporting device links by moving around code that supports clk_get() and DT parsing of the 'clocks' property New Drivers: - Add Qualcomm MSM8998 RPM managed clks - IPA clk support on Qualcomm RPMh clk controllers - Actions Semi S500 SoC clk support - Support for fixed rate clks populated from an MMIO register - Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car V3H - Add TMU (timer) clocks on Renesas RZ/G2E - Add Amlogic G12A Always-On Clock Controller - Add 32k clock generation for Amlogic AXG - Add support for the Mali GPU clocks on Amlogic Meson8 - Add Amlogic G12A EE clock controller driver - Add missing CANFD clocks on Renesas RZ/G2M and RZ/G2E - Add i.MX8MM SoC clk driver support Removed Drivers: - Remove clps711x driver as the board support is gone Updates: - 3rd ECO fix for Mediatek MT2712 SoCs - Updates for Qualcomm MSM8998 GCC clks - Random static analysis fixes for clk drivers - Support for sleeping gpios in the clk-gpio type - Minor fixes for STM32MP1 clk driver (parents, critical flag, etc.) - Split LCDC into two clks on the Marvell MMP2 SoC - Various DT of_node refcount fixes - Get rid of CLK_IS_BASIC from TI code (yay!) - TI Autoidle clk support - Fix Amlogic Meson8 APB clock ID name - Claim input clocks through DT for Amlogic AXG and GXBB - Correct the DU (display unit) parent clock on Renesas RZ/G2E - Exynos5433 IMEM CMU crypto clk support (SlimSS) - Fix for the PLL-MIPI on the Allwinner A23 - Fix Rockchip rk3328 PLL rate calculation - Add SET_RATE_PARENT flag on display clk of Rockhip rk3066 - i.MX SCU clk driver clk_set_parent() and cpufreq support" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (150 commits) dt-bindings: clock: imx8mq: Fix numbering overlaps and gaps clk: ti: clkctrl: Fix clkdm_name regression for TI_CLK_CLKCTRL_COMPAT clk: fixup default index for of_clk_get_by_name() clk: Move of_clk_*() APIs into clk.c from clkdev.c clk: Inform the core about consumer devices clk: Introduce of_clk_get_hw_from_clkspec() clk: core: clarify the check for runtime PM clk: Combine __clk_get() and __clk_create_clk() clk: imx8mq: add GPIO clocks to clock tree clk: mediatek: correct cpu clock name for MT8173 SoC clk: imx: Refactor entire sccg pll clk clk: imx: scu: add cpu frequency scaling support clk: mediatek: Mark bus and DRAM related clocks as critical clk: mediatek: Add flags to mtk_gate clk: mediatek: Add MUX_FLAGS macro clk: qcom: gcc-sdm845: Define parent of PCIe PIPE clocks clk: ingenic: Remove set but not used variable 'enable' clk: at91: programmable: remove unneeded register read clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel clk: mediatek: add MUX_GATE_FLAGS_2 ...
2019-03-12dt-bindings: clock: imx8mq: Fix numbering overlaps and gapsAbel Vesa1-110/+110
IMX8MQ_CLK_USB_PHY_REF changes from 163 to 153, this way removing the gap. All the following clock ids are now decreased by 10 to keep the numbering right. Doing this, the IMX8MQ_CLK_CSI2_CORE is not overlapped with IMX8MQ_CLK_GPT1 anymore. IMX8MQ_CLK_GPT1_ROOT changes from 193 to 183 and all the following ids are updated accordingly. Reported-by: Patrick Wildt <[email protected]> Fixes: 1cf3817b ("dt-bindings: Add binding for i.MX8MQ CCM") Signed-off-by: Abel Vesa <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-03-11Merge tag 'pinctrl-v5.1-1' of ↵Linus Torvalds1-0/+4
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is a calm cycle, not much happened this time around: not even much incremental development. Some three new drivers, that is all. No core changes. New drivers: - NXP (ex Freescale) i.MX 8QM driver. - NXP (ex Freescale) i.MX 8MM driver. - AT91 SAM9X60 subdriver. Improvements: - Support for external interrups (EINT) on Mediatek virtual GPIOs. - Make BCM2835 pin config fully generic. - Lots of Renesas SH-PFC incremental improvements" * tag 'pinctrl-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (70 commits) pinctrl: imx: fix scu link errors dt-bindings: pinctrl: Document the i.MX50 IOMUXC binding pinctrl: qcom: spmi-gpio: Reorder debug print pinctrl: nomadik: fix possible object reference leak pinctrl: stm32: return error upon hwspinlock failure pinctrl: stm32: fix memory leak issue pinctrl: sh-pfc: r8a77965: Add DRIF pins, groups and functions pinctrl: sh-pfc: r8a77965: Add TMU pins, groups and functions pinctrl: sh-pfc: Validate fixed-size field widths at build time pinctrl: sh-pfc: sh73a0: Fix fsic_spdif pin groups pinctrl: sh-pfc: r8a7792: Fix vin1_data18_b pin group pinctrl: sh-pfc: r8a7791: Fix scifb2_data_c pin group pinctrl: sh-pfc: emev2: Add missing pinmux functions pinctrl: sunxi: Support I/O bias voltage setting on A80 pinctrl: ingenic: Add LCD pins for the JZ4725B SoC pinctrl: samsung: Remove legacy API for handling external wakeup interrupts mask pinctrl: bcm2835: Direct GPIO config changes to generic pinctrl pinctrl: bcm2835: declare pin config as generic pinctrl: qcom: qcs404: Drop unused UFS_RESET macro dt-bindings: add documentation for slew rate ...
2019-03-08Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and ↵Stephen Boyd1-1/+2
'clk-rockchip' into clk-next - Convert a few clk bindings to JSON schema format - 3rd ECO fix for Mediatek MT2712 SoCs * clk-typo: clk: samsung: fix typo * clk-json-schema: dt-bindings: clock: Convert fixed-factor-clock to json-schema dt-bindings: clock: Convert fixed-clock binding to json-schema * clk-mtk-2712-eco: clk: mediatek: update clock driver of MT2712 dt-bindings: clock: add clock for MT2712 * clk-rockchip: clk: rockchip: add CLK_SET_RATE_PARENT for rk3066 lcdc dclks clk: rockchip: fix frac settings of GPLL clock for rk3328
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