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2020-01-27thermal: exynos: Rename Samsung and Exynos to lowercaseKrzysztof Kozlowski1-1/+1
Fix up inconsistent usage of upper and lowercase letters in "Samsung" and "Exynos" names. "SAMSUNG" and "EXYNOS" are not abbreviations but regular trademarked names. Therefore they should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Although advertisement materials usually use uppercase "SAMSUNG", the lowercase version is used in all legal aspects (e.g. on Wikipedia and in privacy/legal statements on https://www.samsung.com/semiconductor/privacy-global/). Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Daniel Lezcano <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-01-23dt-bindings: clock: Add bindings for versal clock driverRajan Vaja1-0/+123
Add documentation to describe Xilinx Versal clock driver bindings. Signed-off-by: Rajan Vaja <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-01-23ARM: dts: Add missing omap5 secure clocksTony Lindgren1-0/+11
The secure clocks on omap5 are similar to what we already have for dra7 with dra7_l4sec_clkctrl_regs and documented in the omap5432 TRM in "Table 3-1044. CORE_CM_CORE Registers Mapping Summary". The secure clocks are part of the l4per clock manager. As the l4per clock manager has now two clock domains as children, let's also update the l4per clockdomain node name to follow the "clock" node naming with a domain specific compatible property. Compared to omap4, omap5 has more clocks working in hardare autogating mode. Cc: [email protected] Cc: Rob Herring <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2020-01-23ARM: dts: Add missing omap4 secure clocksTony Lindgren1-0/+11
The secure clocks on omap4 are similar to what we already have for dra7 in dra7_l4sec_clkctrl_regs and documented in the omap4460 TRM "Table 3-1346 L4PER_CM2 Registers Mapping Summary". The secure clocks are part of the l4_per clock manager. As the l4_per clock manager has now two clock domains as children, let's also update the l4_per clockdomain node name to follow the "clock" node naming with a domain specific compatible property. Cc: [email protected] Cc: Rob Herring <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2020-01-22Merge tag 'icc-5.6-rc1' of https://git.linaro.org/people/georgi.djakov/linux ↵Greg Kroah-Hartman1-0/+100
into char-misc-next Georgi writes: interconnect patches for 5.6 Here are the interconnect patches for the 5.6-rc1 merge window. - New core helper functions for some common functionalities in drivers. - Improvements in the information exposed via debugfs. - Basic tracepoints support. - New interconnect driver for msm8916 platforms. - Misc fixes. Signed-off-by: Georgi Djakov <[email protected]> * tag 'icc-5.6-rc1' of https://git.linaro.org/people/georgi.djakov/linux: interconnect: qcom: Add MSM8916 interconnect provider driver dt-bindings: interconnect: Add Qualcomm MSM8916 DT bindings interconnect: Check for valid path in icc_set_bw() interconnect: Print the tag in the debugfs summary interconnect: Add interconnect_graph file to debugfs interconnect: qcom: Use the standard aggregate function interconnect: Add a common standard aggregate function interconnect: Add basic tracepoints interconnect: Add a name to struct icc_path interconnect: Move internal structs into a separate file interconnect: qcom: Use the new common helper for node removal interconnect: Add a common helper for removing all nodes
2020-01-21Merge 5.5-rc7 into usb-nextGreg Kroah-Hartman1-3/+3
We need the USB fixes in here as well. Signed-off-by: Greg Kroah-Hartman <[email protected]>
2020-01-20Merge tag 'v5.5-next-soc' of ↵Olof Johansson1-0/+14
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/drivers cmdq: - clean ups of unused code and debuggability - add cmdq_instruction to make the function call interface more readable - add functions for polling and providing info for the user of cmdq scpsys: - add bindings for MT6765 * tag 'v5.5-next-soc' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: dt-bindings: mediatek: add MT6765 power dt-bindings soc: mediatek: cmdq: delete not used define soc: mediatek: cmdq: add cmdq_dev_get_client_reg function soc: mediatek: cmdq: add polling function soc: mediatek: cmdq: define the instruction struct soc: mediatek: cmdq: remove OR opertaion from err return Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-20dt-bindings: interrupt-controller: Add Aspeed SCU interrupt controllerEddie James1-0/+23
Document the Aspeed SCU interrupt controller and add an include file for the interrupts it provides. Signed-off-by: Eddie James <[email protected]> Signed-off-by: Marc Zyngier <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Andrew Jeffery <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2020-01-20clk: ti: add clkctrl data dra7 sgxTony Lindgren1-0/+3
This is similar to what we have for omap5 except the gpu_cm address is different, the mux clocks have one more source option, and there's no divider clock. Note that because of the current dts node name dependency for mapping to clock domain, we must still use "gpu-clkctrl@" naming instead of generic "clock@" naming for the node. And because of this, it's probably best to apply the dts node addition together along with the other clock changes. For accessing the GPU, we also need to configure the interconnect target module for GPU similar to what we have for omap5, I'll send that change separately. Cc: Benoit Parrot <[email protected]> Cc: "H. Nikolaus Schaller" <[email protected]> Cc: Robert Nelson <[email protected]> Cc: Tomi Valkeinen <[email protected]> Signed-off-by: Tony Lindgren <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2020-01-20clk: ti: omap5: Add missing AESS clockTony Lindgren1-0/+1
Looks like we're missing AESS clock for omap5. This is similar to what omap4 has. Cc: H. Nikolaus Schaller <[email protected]> Cc: Matthijs van Duin <[email protected]> Cc: Peter Ujfalusi <[email protected]> Signed-off-by: Tony Lindgren <[email protected]> Reviewed-by: Peter Ujfalusi <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2020-01-20clk: ti: dra7: add vpe clkctrl dataBenoit Parrot1-0/+10
Add clkctrl data for VPE. Signed-off-by: Benoit Parrot <[email protected]> Acked-by: Tony Lindgren <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2020-01-20clk: ti: dra7: add cam clkctrl dataBenoit Parrot1-0/+10
Add clkctrl data for CAM domain. Signed-off-by: Benoit Parrot <[email protected]> Acked-by: Tony Lindgren <[email protected]> Acked-by: Rob Herring <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2020-01-20dt-bindings: clock: Move ti-dra7-atl.h to dt-bindings/clockPeter Ujfalusi1-0/+0
Most of the clock related dt-binding header files are located in dt-bindings/clock folder. It would be good to keep all the similar header files at a single location. Suggested-by: Tony Lindgren <[email protected]> Signed-off-by: Peter Ujfalusi <[email protected]> Acked-by: Tony Lindgren <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Tero Kristo <[email protected]>
2020-01-17dt-bindings: phy: Add PHY_TYPE_DP definitionJyri Sarha1-0/+1
Add definition for DisplayPort phy type. Signed-off-by: Jyri Sarha <[email protected]> Reviewed-by: Roger Quadros <[email protected]> Reviewed-by: Kishon Vijay Abraham I <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-01-16Merge tag 'amlogic-dt' of ↵Olof Johansson1-0/+4
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt ARM: dts: Amlogic updates for v5.6 - add DDR clock controller - GPU OPP updates * tag 'amlogic-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: ARM: dts: meson8b: use the actual frequency for the GPU's 364MHz OPP ARM: dts: meson8: use the actual frequency for the GPU's 182.1MHz OPP ARM: dts: meson8b: fix the clock controller compatible string ARM: dts: meson8b: add the DDR clock controller ARM: dts: meson8: add the DDR clock controller ARM: dts: meson: provide the XTAL clock using a fixed-clock dt-bindings: clock: meson8b: add the clock inputs dt-bindings: clock: add the Amlogic Meson8 DDR clock controller binding Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-16Merge tag 'qcom-drivers-for-5.6' of ↵Olof Johansson1-0/+24
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/drivers Qualcomm driver updates for v5.6 * SCM major refactoring and cleanup * Properly flag active only power domains as active only * Add SC7180 and SM8150 RPMH power domains * Return EPROBE_DEFER from QMI if packet family is not yet available * tag 'qcom-drivers-for-5.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (27 commits) firmware: qcom_scm: Dynamically support SMCCC and legacy conventions firmware: qcom_scm: Remove thin wrappers firmware: qcom_scm: Order functions, definitions by service/command firmware: qcom_scm-32: Add device argument to atomic calls firmware: qcom_scm-32: Create common legacy atomic call firmware: qcom_scm-32: Move SMCCC register filling to qcom_scm_call firmware: qcom_scm-32: Use qcom_scm_desc in non-atomic calls firmware: qcom_scm-32: Add funcnum IDs firmware: qcom_scm-32: Use SMC arch wrappers firmware: qcom_scm-64: Improve SMC convention detection firmware: qcom_scm-64: Move SMC register filling to qcom_scm_call_smccc firmware: qcom_scm-64: Add SCM results struct firmware: qcom_scm-64: Move svc/cmd/owner into qcom_scm_desc firmware: qcom_scm-64: Make SMC macros less magical firmware: qcom_scm: Remove unused qcom_scm_get_version firmware: qcom_scm: Apply consistent naming scheme to command IDs firmware: qcom_scm: Rename macros and structures soc: qcom: rpmhpd: Set 'active_only' for active only power domains firmware: scm: Add stubs for OCMEM and restore_sec_cfg_available dt-bindings: power: rpmpd: Convert rpmpd bindings to yaml ... Link: https://lore.kernel.org/r/20200113204405.GD3325@yoga Signed-off-by: Olof Johansson <[email protected]>
2020-01-16Merge tag 'tegra-for-5.6-dt-bindings' of ↵Olof Johansson2-0/+549
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt dt-bindings: Changes for v5.6-rc1 This contains a conversion of the Tegra124 EMC bindings to json-schema as well as the addition of the bindings for the memory subsystem found on Tegra186 and Tegra194. * tag 'tegra-for-5.6-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: dt-bindings: memory: Add Tegra186 memory subsystem dt-bindings: memory: Add Tegra194 memory controller header dt-bindings: memory: Add Tegra186 memory client IDs dt-bindings: memory-controller: Convert Tegra124 EMC to json-schema Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Olof Johansson <[email protected]>
2020-01-12dt-bindings: imx: Add clock binding doc for i.MX8MPAnson Huang1-0/+300
Add the clock binding doc for i.MX8MP. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2020-01-10dt-bindings: mediatek: add MT6765 power dt-bindingsMars Cheng1-0/+14
This adds power dt-bindings for MT6765 Signed-off-by: Mars Cheng <[email protected]> Signed-off-by: Owen Chen <[email protected]> Signed-off-by: Macpaul Lin <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Matthias Brugger <[email protected]>
2020-01-09clk: qcom: Add DT bindings for ipq6018 gcc clock controllerSricharan R2-0/+419
Add the compatible strings and the include file for ipq6018 gcc clock controller. Co-developed-by: Anusha Canchi Ramachandra Rao <[email protected]> Signed-off-by: Anusha Canchi Ramachandra Rao <[email protected]> Co-developed-by: Abhishek Sahu <[email protected]> Signed-off-by: Abhishek Sahu <[email protected]> Co-developed-by: Sivaprakash Murugesan <[email protected]> Signed-off-by: Sivaprakash Murugesan <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Sricharan R <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-01-09dt-bindings: memory: Add Tegra194 memory controller headerThierry Reding1-0/+410
This header contains definitions for the memory controller found on NVIDIA Tegra194 SoCs, such as the stream IDs used for the ARM SMMU and the IDs used to identify the various memory clients. Signed-off-by: Thierry Reding <[email protected]> Acked-by: Rob Herring <[email protected]>
2020-01-09dt-bindings: memory: Add Tegra186 memory client IDsThierry Reding1-0/+139
Add IDs for the memory clients found on NVIDIA Tegra186 SoCs. This will be used to describe interconnect paths from devices to system memory. Signed-off-by: Thierry Reding <[email protected]> Acked-by: Rob Herring <[email protected]>
2020-01-07dt-bindings: interconnect: Add Qualcomm MSM8916 DT bindingsGeorgi Djakov1-0/+100
The Qualcomm MSM8916 platform has several bus fabrics that could be controlled and tuned dynamically according to the bandwidth demand. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Georgi Djakov <[email protected]>
2020-01-06dt-bindings: marvell,mmp2: Add clock ids for the HSIC clocksLubomir Rintel1-0/+2
There are two USB HSIC controllers on MMP2 and MMP3. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Lubomir Rintel <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Olof Johansson <[email protected]>
2020-01-04dt-bindings: clock: Introduce SC7180 QCOM Video clock bindingsTaniya Das1-0/+23
Add device tree bindings for video clock controller for Qualcomm Technology Inc's SC7180 SoCs. Signed-off-by: Taniya Das <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2020-01-04dt-bindings: clock: Introduce SC7180 QCOM Graphics clock bindingsTaniya Das1-0/+21
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SC7180 SoCs. Signed-off-by: Taniya Das <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lkml.kernel.org/r/[email protected] [[email protected]: Indicate sc7180 in commit subject] Signed-off-by: Stephen Boyd <[email protected]>
2020-01-04clk: sunxi: a23/a33: Export the MIPI PLLMaxime Ripard1-0/+2
The MIPI PLL is used for LVDS. Make sure it's exported in the dt bindings headers. Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2020-01-04clk: sunxi: a31: Export the MIPI PLLMaxime Ripard1-0/+2
The MIPI PLL is used for LVDS. Make sure it's exported in the dt bindings headers. Acked-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2020-01-04clk: sunxi-ng: a64: export CLK_CPUX clock for DVFSVasily Khoruzhick1-0/+1
Export CLK_CPUX so we can reference it in CPU node. Signed-off-by: Vasily Khoruzhick <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2020-01-03clk: sunxi-ng: r40: Export MBUS clockChen-Yu Tsai1-1/+1
The MBUS clock needs to be referenced in the MBUS device node. Export it. Signed-off-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2020-01-02dt-bindings: reset: Add binding constants for NPCM7xx reset controllerTomer Maimon1-0/+91
Add device tree binding constants for Nuvoton BMC NPCM7xx reset controller. Signed-off-by: Tomer Maimon <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Philipp Zabel <[email protected]>
2019-12-23dt-bindings: clock: Introduce QCOM sc7180 display clock bindingsTaniya Das1-0/+46
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SC7180 SoCs. Signed-off-by: Taniya Das <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Reviewed-by: Rob Herring <[email protected]> [[email protected]: Add sc7180 to subject] Signed-off-by: Stephen Boyd <[email protected]>
2019-12-23clk: qcom: Add missing msm8998 gcc_bimc_gfx_clkJeffrey Hugo1-0/+1
gcc_bimc_gfx_clk is a required clock for booting the GPU and GPU SMMU. Fixes: 4807c71cc688 (arm64: dts: Add msm8998 SoC and MTP board support) Signed-off-by: Jeffrey Hugo <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2019-12-23dt-bindings: dmaengine: Add X1830 bindings.周琰杰 (Zhou Yanjie)1-0/+39
Add the dmaengine bindings for the X1830 Soc from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2019-12-18dt-bindings: clock: Add support for the MSM8998 mmccJeffrey Hugo1-0/+210
Document the multimedia clock controller found on MSM8998. Signed-off-by: Jeffrey Hugo <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2019-12-18clk: qcom: dispcc: Add support for display port clocksTaniya Das1-1/+12
SDM845 dispcc supports RCG and CBCRs for display port, so add support for the same. Signed-off-by: Taniya Das <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
2019-12-11dt-bindings: power: Add rpmh power-domain bindings for sc7180Sibi Sankar1-0/+10
Add RPMH power-domain bindings for the SC7180 family of SoCs. Reviewed-by: Stephen Boyd <[email protected]> Reviewed-by: Rajendra Nayak <[email protected]> Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Link: https://lore.kernel.org/r/0101016e7f99ca4e-47d442f4-b923-4eea-b812-898e5476beab-000000@us-west-2.amazonses.com Signed-off-by: Bjorn Andersson <[email protected]>
2019-12-11dt-bindings: power: Add rpmh power-domain bindings for SM8150Sibi Sankar1-0/+14
Add RPMH power-domain bindings for the SM8150 family of SoCs. Reviewed-by: Bjorn Andersson <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Reviewed-by: Rajendra Nayak <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Sibi Sankar <[email protected]> Link: https://lore.kernel.org/r/0101016e7f99ad2b-2bce2fac-2f02-4b3f-ac64-09942f7251ea-000000@us-west-2.amazonses.com Signed-off-by: Bjorn Andersson <[email protected]>
2019-12-11dt-bindings: clock: add the Amlogic Meson8 DDR clock controller bindingMartin Blumenstingl1-0/+4
Amlogic Meson8, Meson8b and Meson8m2 SoCs have a DDR clock controller in the MMCBUS registers. There is no public documentation on this, but the GPL u-boot sources from the Amlogic BSP show that: - it uses the same XTAL input as the main clock controller - it contains a PLL which seems to be implemented just like the other PLLs in this SoC - there is a power-of-two PLL post-divider Add the documentation and header file for this DDR clock controller. Reviewed-by: Rob Herring <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2019-12-09dt-bindings: reset: meson8b: fix duplicate reset IDsMartin Blumenstingl1-3/+3
According to the public S805 datasheet the RESET2 register uses the following bits for the PIC_DC, PSC and NAND reset lines: - PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3) - PSC is at bit 4 (meaning: RESET_VD_RMEM + 4) - NAND is at bit 5 (meaning: RESET_VD_RMEM + 4) Update the reset IDs of these three reset lines so they don't conflict with PIC_DC and map to the actual hardware reset lines. Fixes: 79795e20a184eb ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller") Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Kevin Hilman <[email protected]>
2019-12-05Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/socLinus Torvalds2-4/+115
Pull ARM Device-tree updates from Olof Johansson: "As always, the bulk of updates. Some of the news this cycle: New SoC descriptions: - Broadcom BCM2711 - Amlogic Meson A1 and G12 - Freescale S32V234 - Marvell Armada AP807/AP807-quad and CP115 - Realtek RTD1293 and RTD1296 - Rockchip RK3308 New boards and platforms: - Allwinner: NanoPi Duo2 - Amlogic: Ugoos am6 - Atmel at91: Overkiz Kizbox2/4 - Broadcom: RPi4, Luxul XWC-2000 - Marvell: New Espressobin flavor - NXP: i.MX8MN LPDDR4 EVK, i.MX8QXP Colibri, S32V234 EVB, Netronix E60K02 and Kobo Clara HD, Kontron N6311 and N6411, OPOS6UL and OPOS6ULDev - Renesas: Salvator-XS - Rockchip: Beelink A1 (rk3308), rk3308 eval boards, rk3399-roc-pc" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (653 commits) ARM: dts: logicpd-torpedo: Disable USB Host arm: dts: mt6323: add keys, power-controller, rtc and codec arm64: dts: mt8183: add systimer0 device node dt-bindings: mediatek: update bindings for MT8183 systimer arm64: dts: rockchip: fix sdmmc detection on boot on rk3328-roc-cc arm64: dts: rockchip: Split rk3399-roc-pc for with and without mezzanine board. arm64: dts: rockchip: Add Beelink A1 dt-bindings: ARM: rockchip: Add Beelink A1 arm64: dts: rockchip: Add RK3328 audio pipelines arm64: dts: ti: k3-j721e-common-proc-board: Add USB ports arm64: dts: ti: k3-j721e-main: add USB controller nodes ARM: dts: aspeed-g6: Add timer description ARM: dts: aspeed: ast2600evb: Enable i2c buses ARM: dts: at91: add a dts and dtsi file for kizbox2 based boards dt-bindings: arm: at91: Document Kizbox2-2 board binding arm64: dts: meson-gx: fix i2c compatible arm64: dts: meson-gx: cec node should be disabled by default arm64: dts: meson-g12b-odroid-n2: add missing amlogic, s922x compatible arm64: dts: meson-gxm: fix gpu irq order arm64: dts: meson-g12a: fix gpu irq order ...
2019-12-05Merge tag 'armsoc-drivers' of ↵Linus Torvalds3-0/+85
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Olof Johansson: "Various driver updates for platforms: - A larger set of work on Tegra 2/3 around memory controller and regulator features, some fuse cleanups, etc.. - MMP platform drivers, in particular for USB PHY, and other smaller additions. - Samsung Exynos 5422 driver for DMC (dynamic memory configuration), and ASV (adaptive voltage), allowing the platform to run at more optimal operating points. - Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas - Clock/reset control driver for TI/OMAP - Meson-A1 reset controller support - Qualcomm sdm845 and sda845 SoC IDs for socinfo" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits) firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT soc: fsl: add RCPM driver dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver soc: mediatek: Refactor bus protection control soc: mediatek: Refactor sram control ...
2019-12-02Merge tag 'dmaengine-5.5-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds1-0/+40
Pull dmaengine updates from Vinod Koul: "Here are the changes this time around, couple of new drivers and updates to few more: - New drivers for SiFive PDMA, Socionext Milbeaut HDMAC and XDMAC, Freescale dpaa2 qDMA - Support for X1000 in JZ4780 - Xilinx dma updates and support for Xilinx AXI MCDM controller - New bindings for rcar R8A774B1 - Minor updates to dw, dma-jz4780, ti-edma, sprd drivers" * tag 'dmaengine-5.5-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (61 commits) dmaengine: Fix Kconfig indentation dmaengine: sf-pdma: move macro to header file dmaengine: sf-pdma: replace /** with /* for non-function comment dmaengine: ti: edma: fix missed failure handling dmaengine: mmp_pdma: add missed of_dma_controller_free dmaengine: mmp_tdma: add missed of_dma_controller_free dmaengine: sprd: Add wrap address support for link-list mode MAINTAINERS: Add Green as SiFive PDMA driver maintainer dmaengine: sf-pdma: add platform DMA support for HiFive Unleashed A00 dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA dmaengine: zx: remove: removed dmam_pool_destroy dmaengine: mediatek: hsdma_probe: fixed a memory leak when devm_request_irq fails dmaengine: iop-adma: clean up an indentation issue dmaengine: milbeaut-xdmac: remove redundant error log dmaengine: milbeaut-hdmac: remove redundant error log dmaengine: dma-jz4780: add missed clk_disable_unprepare in remove dmaengine: JZ4780: Add support for the X1000. dt-bindings: dmaengine: Add X1000 bindings. dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support dmaengine: xilinx_dma: Extend dma_config struct to store irq routine handle ...
2019-12-01Merge tag 'clk-for-linus' of ↵Linus Torvalds22-8/+588
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "This merge window we have one small clk provider API in the core framework and then a bunch of driver updates and a handful of new drivers. In terms of diffstat the Qualcomm and Amlogic drivers are high up there because of all the clk data introcued by new drivers. The Nvidia Tegra driver had a lot of work done this cycle too to support suspend/resume and memory controllers. And the OMAP clk driver got proper clk and reset handling in place. Rounding out the patches are various updates to remove unused data, mark things static, correct incorrect data in drivers, etc. All the little things that improve drivers and maintain code health. I will point out that there's a patch in here for the GPIO clk driver, that almost nobody uses, which changes behavior and causes clk_set_rate() to try to change the GPIO gate clk's parent. Other than that things are fairly well SoC specific here. Core: - Add a clk provider API to get current parent index - Plug a memory leak in clk_unregister() path New Drivers: - CGU in Ingenix X1000 - Bitmain BM1880 clks - Qualcomm MSM8998 GPU clk controllers - Qualcomm SC7180 GCC and RPMH clk controllers - Qualcomm QCS404 Q6SSTOP clk controllers - Add support for the Renesas R-Car M3-W+ (r8a77961) SoC - Add support for the Renesas RZ/G2N (r8a774b1) SoC - Add Tegra20/30 External Memory Clock (EMC) support Updates: - Make gpio gate clks propagate rate setting up to parent - Prepare Armada 3700 for suspend to RAM by moving PCIe suspend/resume priority - Drop unused variables, enums, etc. in various clk drivers - Convert various drivers to use devm_platform_ioremap_resource() - Use struct_size() some more in various clk drivers - Improve Rockchip px30 clk tree - Add suspend/resume support to Tegra210 clk driver - Reimplement SOR clks on earlier Tegra SoCs, helping HDMI and DP - Allwinner DT exports and H6 clk tree fixes - Proper clk and reset handling for OMAP SoCs - Revamped TI divider clk to clamp max divider - Make 1443X/1416X PLL clock structure common for reusing among i.MX8 SoCs - Drop IMX7ULP_CLK_MIPI_PLL clock, it shouldn't be used - Add VIDEO2_PLL clock for imx8mq - Add missing gate clock for pll1/2 fixed dividers on i.MX8 SoCs - Add sm1 support in the Amlogic audio clock controller - Switch some clocks on R-Car Gen2/3 to .determine_rate() - Remove Renesas R-Car Gen2 legacy DT clock support - Improve arithmetic divisions on Renesas R-Car Gen2 and Gen3 - Improve Renesas R-Car Gen3 SD clock handling - Add rate table for Samsung exynos542x GPU and VPLL clks - Fix potential CPU performance degradation after system suspend/resume cycle on exynos542x SoCs" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (160 commits) clk: aspeed: Add RMII RCLK gates for both AST2500 MACs MAINTAINERS: Add entry for BM1880 SoC clock driver clk: Add common clock driver for BM1880 SoC dt-bindings: clock: Add devicetree binding for BM1880 SoC clk: Add clk_hw_unregister_composite helper function definition clk: Zero init clk_init_data in helpers clk: ingenic: Allow drivers to be built with COMPILE_TEST MAINTAINERS: Update section for Ux500 clock drivers clk: mark clk_disable_unused() as __init clk: Fix memory leak in clk_unregister() clk: Ingenic: Add CGU driver for X1000. dt-bindings: clock: Add X1000 bindings. clk: tegra: Use match_string() helper to simplify the code clk: pxa: fix one of the pxa RTC clocks clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle() clk: armada-xp: remove unused code clk: tegra: Fix build error without CONFIG_PM_SLEEP clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP clk: tegra: Optimize PLLX restore on Tegra20/30 clk: tegra: Add suspend and resume support on Tegra210 ...
2019-11-27Merge tag 'staging-5.5-rc1' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging Pull staging / iio updates from Greg KH: "Here is the big staging and iio set of patches for the 5.5-rc1 release. It's the usual huge collection of cleanup patches all over the drivers/staging/ area, along with a new staging driver, and a bunch of new IIO drivers as well. Full details are in the shortlog, but all of these have been in linux-next for a long time with no reported issues" * tag 'staging-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging: (548 commits) staging: vchiq: Have vchiq_dump_* functions return an error code staging: vchiq: Refactor indentation in vchiq_dump_* functions staging: fwserial: Fix Kconfig indentation (seven spaces) staging: vchiq_dump: Replace min with min_t staging: vchiq: Fix block comment format in vchiq_dump() staging: octeon: indent with tabs instead of spaces staging: comedi: usbduxfast: usbduxfast_ai_cmdtest rounding error staging: most: core: remove sysfs attr remove_link staging: vc04: Fix Kconfig indentation staging: pi433: Fix Kconfig indentation staging: nvec: Fix Kconfig indentation staging: most: Fix Kconfig indentation staging: fwserial: Fix Kconfig indentation staging: fbtft: Fix Kconfig indentation fbtft: Drop OF dependency fbtft: Make use of device property API fbtft: Drop useless #ifdef CONFIG_OF and dead code fbtft: Describe function parameters in kernel-doc fbtft: Make sure string is NULL terminated staging: rtl8723bs: remove set but not used variable 'change', 'pos' ...
2019-11-27Merge tag 'char-misc-5.5-rc1' of ↵Linus Torvalds1-0/+146
git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver updates from Greg KH: "Here is the big set of char/misc and other driver patches for 5.5-rc1 Loads of different things in here, this feels like the catch-all of driver subsystems these days. Full details are in the shortlog, but nothing major overall, just lots of driver updates and additions. All of these have been in linux-next for a while with no reported issues" * tag 'char-misc-5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (198 commits) char: Fix Kconfig indentation, continued habanalabs: add more protection of device during reset habanalabs: flush EQ workers in hard reset habanalabs: make the reset code more consistent habanalabs: expose reset counters via existing INFO IOCTL habanalabs: make code more concise habanalabs: use defines for F/W files habanalabs: remove prints on successful device initialization habanalabs: remove unnecessary checks habanalabs: invalidate MMU cache only once habanalabs: skip VA block list update in reset flow habanalabs: optimize MMU unmap habanalabs: prevent read/write from/to the device during hard reset habanalabs: split MMU properties to PCI/DRAM habanalabs: re-factor MMU masks and documentation habanalabs: type specific MMU cache invalidation habanalabs: re-factor memory module code habanalabs: export uapi defines to user-space habanalabs: don't print error when queues are full habanalabs: increase max jobs number to 512 ...
2019-11-27Merge tag 'pinctrl-v5.5-1' of ↵Linus Torvalds2-2/+75
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for v5.5. It is pretty much business as usual, the most interesting thing I think is the pin controller for a new Intel chip called Lightning Mountain, which is according to news reports some kind of embedded network processor and what is surprising about it is that Intel have decided to use device tree to describe the system rather than ACPI that they have traditionally favored. Core changes: - Avoid taking direct references to device tree-supplied device names: these may changed at runtime under certain circumstances to kstrdup them. GPIO related: - Work is ongoing to move to passing the irqchip along as a templated struct gpio_irq_chip when adding a standard gpiolib-based irqchip to a GPIO controller, a few patches in this cycle switches a few pin control drivers over to using this method. New hardware support: - Intel Lightning Mountain SoC pin controller and GPIO support, a first Intel platform to use device tree rather than ACPI to configure the system. News reports says that this SoC is a network processor. - Qualcomm MSM8976 and MSM8956 - Qualcomm PMIC GPIO now also supports PM6150 and PM6150L - Qualcomm SPMI MPP and SPMI GPIO for PM8950 and PMI8950 - Rockchip RK3308 - Renesas R8A77961 - Allwinner Meson-A1 Driver improvements: - get_multiple and set_multiple support for the AT91-PIO4 driver. - Convert Qualcomm SSBI GPIO to use the hierarchical IRQ helpers in the GPIOlib irqchip" * tag 'pinctrl-v5.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (93 commits) pinctrl: ingenic: Add OTG VBUS pin for the JZ4770 pinctrl: ingenic: Handle PIN_CONFIG_OUTPUT config pinctrl: Fix Kconfig indentation pinctrl: lewisburg: Update pin list according to v1.1v6 MAINTAINERS: Replace my email by one @kernel.org pinctrl: armada-37xx: Fix irq mask access in armada_37xx_irq_set_type() dt-bindings: pinctrl: intel: Add for new SoC pinctrl: Add pinmux & GPIO controller driver for a new SoC pinctrl: rza1: remove unnecessary static inline function pinctrl: meson: add pinctrl driver support for Meson-A1 SoC pinctrl: meson: add a new callback for SoCs fixup pinctrl: nomadik: db8500: Add mc0_a_2 pin group without direction control dt-bindings: pinctrl: Convert generic pin mux and config properties to schema pinctrl: cherryview: Missed type change to unsigned int pinctrl: intel: Missed type change to unsigned int pinctrl: use devm_platform_ioremap_resource() to simplify code pinctrl: just return if no valid maps dt-bindings: pinctrl: qcom-pmic-mpp: Add support for PM/PMI8950 pinctrl: qcom: spmi-mpp: Add PM/PMI8950 compatible strings dt-bindings: pinctrl: qcom-pmic-gpio: Add support for PM/PMI8950 ...
2019-11-27Merge branches 'clk-ingenic', 'clk-init-leak', 'clk-ux500' and 'clk-bitmain' ↵Stephen Boyd2-0/+126
into clk-next - Support CGU in Ingenix X1000 - Support Bitmain BM1880 clks * clk-ingenic: clk: ingenic: Allow drivers to be built with COMPILE_TEST clk: Ingenic: Add CGU driver for X1000. dt-bindings: clock: Add X1000 bindings. * clk-init-leak: clk: mark clk_disable_unused() as __init clk: Fix memory leak in clk_unregister() * clk-ux500: MAINTAINERS: Update section for Ux500 clock drivers * clk-bitmain: MAINTAINERS: Add entry for BM1880 SoC clock driver clk: Add common clock driver for BM1880 SoC dt-bindings: clock: Add devicetree binding for BM1880 SoC clk: Add clk_hw_unregister_composite helper function definition clk: Zero init clk_init_data in helpers
2019-11-27Merge branches 'clk-gpio-flags', 'clk-tegra', 'clk-rockchip', 'clk-sprd' and ↵Stephen Boyd3-4/+7
'clk-pxa' into clk-next - Make gpio gate clks propagate rate setting up to parent * clk-gpio-flags: clk: clk-gpio: propagate rate change to parent * clk-tegra: (23 commits) clk: tegra: Use match_string() helper to simplify the code clk: tegra: Fix build error without CONFIG_PM_SLEEP clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP clk: tegra: Optimize PLLX restore on Tegra20/30 clk: tegra: Add suspend and resume support on Tegra210 clk: tegra: Share clk and rst register defines with Tegra clock driver clk: tegra: Use fence_udelay() during PLLU init clk: tegra: clk-dfll: Add suspend and resume support clk: tegra: clk-super: Add restore-context support clk: tegra: clk-super: Fix to enable PLLP branches to CPU clk: tegra: periph: Add restore_context support clk: tegra: Support for OSC context save and restore clk: tegra: pll: Save and restore pll context clk: tegra: pllout: Save and restore pllout context clk: tegra: divider: Save and restore divider rate clk: tegra: Reimplement SOR clocks on Tegra210 clk: tegra: Reimplement SOR clock on Tegra124 clk: tegra: Rename sor0_lvds to sor0_out clk: tegra: Move SOR0 implementation to Tegra124 clk: tegra: Remove last remains of TEGRA210_CLK_SOR1_SRC ... * clk-rockchip: clk: rockchip: protect the pclk_usb_grf as critical on px30 clk: rockchip: add video-related niu clocks as critical on px30 clk: rockchip: move px30 critical clocks to correct clock controller clk: rockchip: Add div50 clocks for px30 sdmmc, emmc, sdio and nandc clk: rockchip: Add div50 clock-ids for sdmmc on px30 and nandc clk: rockchip: make clk_half_divider_ops static * clk-sprd: clk: sprd: Use IS_ERR() to validate the return value of syscon_regmap_lookup_by_phandle() * clk-pxa: clk: pxa: fix one of the pxa RTC clocks
2019-11-27Merge branches 'clk-ti', 'clk-allwinner', 'clk-qcom', 'clk-sa' and ↵Stephen Boyd7-1/+190
'clk-aspeed' into clk-next - Qualcomm MSM8998 GPU clk controllers - Qualcomm SC7180 GCC and RPMH clk controllers - Qualcomm QCS404 Q6SSTOP clk controllers - Use struct_size() some more in various clk drivers * clk-ti: clk/ti/adpll: allocate room for terminating null ARM: dts: omap3: fix DPLL4 M4 divider max value clk: ti: divider: convert to use min,max,mask instead of width clk: ti: divider: cleanup ti_clk_parse_divider_data API clk: ti: divider: cleanup _register_divider and ti_clk_get_div_table clk: ti: am43xx: drop idlest polling from gfx clock clk: ti: am33xx: drop idlest polling from gfx clock clk: ti: am33xx: drop idlest polling from pruss clkctrl clock clk: ti: am43xx: drop idlest polling from pruss clkctrl clock clk: ti: omap5: Drop idlest polling from IPU & DSP clkctrl clocks clk: ti: omap4: Drop idlest polling from IPU & DSP clkctrl clocks clk: ti: dra7xx: Drop idlest polling from IPU & DSP clkctrl clocks clk: ti: omap5: add IVA subsystem clkctrl data dt-bindings: clk: add omap5 iva clkctrl definitions clk: ti: clkctrl: add new exported API for checking standby info clk: ti: clkctrl: convert to use bit helper macros instead of bitops clk: ti: clkctrl: fix setting up clkctrl clocks * clk-allwinner: clk: sunxi-ng: h3: Export MBUS clock clk: sunxi-ng: h6: Allow GPU to change parent rate clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL * clk-qcom: clk: qcom: rpmh: Reuse sdm845 clks for sm8150 clk: qcom: Add MSM8998 GPU Clock Controller (GPUCC) driver clk: qcom: Allow constant ratio freq tables for rcg clk: qcom: smd: Add missing pnoc clock clk: qcom: Enumerate clocks and reset needed to boot the 8998 modem clk: qcom: clk-rpmh: Add support for RPMHCC for SC7180 dt-bindings: clock: Introduce RPMHCC bindings for SC7180 dt-bindings: clock: Add YAML schemas for the QCOM RPMHCC clock bindings clk: qcom: Add Global Clock controller (GCC) driver for SC7180 dt-bindings: clock: Add sc7180 GCC clock binding dt-bindings: clock: Add YAML schemas for the QCOM GCC clock bindings clk: qcom: common: Return NULL from clk_hw OF provider clk: qcom: rcg: update the DFS macro for RCG clk: qcom: remove unneeded semicolon clk: qcom: Add Q6SSTOP clock controller for QCS404 dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings * clk-sa: drivers/clk: convert VL struct to struct_size * clk-aspeed: clk: aspeed: Add RMII RCLK gates for both AST2500 MACs clk: ast2600: Add RMII RCLK gates for all four MACs dt-bindings: clock: Add AST2600 RMII RCLK gate definitions dt-bindings: clock: Add AST2500 RMII RCLK definitions
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