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2020-11-24dt-bindings: dmaengine: Document qcom,gpi dma bindingVinod Koul1-0/+11
Add devicetree binding documentation for GPI DMA controller implemented on Qualcomm SoCs Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-11-18dt-bindings: dmaengine: Add X2000 bindings.周琰杰 (Zhou Yanjie)1-0/+54
Add the dmaengine bindings for the X2000 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-11-18dt-bindings: dmaengine: Add JZ4775 bindings.周琰杰 (Zhou Yanjie)1-0/+44
Add the dmaengine bindings for the JZ4775 SoC from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2020-07-17dt: bindings: dma: xilinx: dpdma: DT bindings for Xilinx DPDMALaurent Pinchart1-0/+16
The ZynqMP includes the DisplayPort subsystem with its own DMA engine called DPDMA. The DPDMA IP comes with 6 individual channels (4 for display, 2 for audio). This documentation describes DT bindings of DPDMA. Signed-off-by: Hyun Kwon <[email protected]> Signed-off-by: Michal Simek <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2019-12-23dt-bindings: dmaengine: Add X1830 bindings.周琰杰 (Zhou Yanjie)1-0/+39
Add the dmaengine bindings for the X1830 Soc from Ingenic. Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2019-11-06dt-bindings: dmaengine: Add X1000 bindings.Zhou Yanjie1-0/+40
Add the dmaengine bindings for the X1000 Soc from Ingenic. Signed-off-by: Zhou Yanjie <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 498Thomas Gleixner1-2/+1
Based on 1 normalized pattern(s): gplv2 only extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Kate Stewart <[email protected]> Reviewed-by: Enrico Weigelt <[email protected]> Reviewed-by: Armijn Hemel <[email protected]> Reviewed-by: Allison Randal <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 206Thomas Gleixner1-4/+1
Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of version 2 of the gnu general public license as published by the free software foundation extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 107 file(s). Signed-off-by: Thomas Gleixner <[email protected]> Reviewed-by: Allison Randal <[email protected]> Reviewed-by: Richard Fontana <[email protected]> Reviewed-by: Steve Winslow <[email protected]> Reviewed-by: Alexios Zavras <[email protected]> Cc: [email protected] Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Greg Kroah-Hartman <[email protected]>
2018-11-24dt-bindings: dmaengine: dw-dmac: add protection control propertyChristian Lamparter1-0/+14
This patch for the DesignWare AHB Central Direct Memory Access Controller adds the dma protection control property: "snps,dma-protection-control" as well as the properties specific values defines into a new include file: include/dt-bindings/dma/dw-dmac.h Note: The protection control signals are one-to-one mapped to the AHB HPROT[1:3] signals for this controller. The HPROT0 (Data Access) is always hardwired to 1. Reviewed-by: Andy Shevchenko <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Christian Lamparter <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2018-05-02MIPS: dts: jz4780: Add DMA controller node to the devicetreeEzequiel Garcia1-0/+49
Add the devicetree node to support the DMA controller found in JZ480 SoCs. Tested-by: Mathieu Malaterre <[email protected]> Acked-by: James Hogan <[email protected]> Signed-off-by: Ezequiel Garcia <[email protected]> Signed-off-by: Ulf Hansson <[email protected]>
2015-08-23devicetree: Add bindings documentation for Analog Devices AXI-DMACLars-Peter Clausen1-0/+48
Add the devicetree descriptor for the Analog Devices AXI-DMAC DMA controller. This is a soft peripheral used in FPGAs and the bindings describe how it is connected to the system (clock, interrupt, memory map) as well as the configuration options that were used when the peripheral was instantiated. Signed-off-by: Lars-Peter Clausen <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2015-08-18dmaengine: jz4780: Remove request type number definitions headerAlex Smith1-49/+0
The header just includes definitions of hardware-specific numbers which can be written directly in the device tree, there's no need for a public header containing these definitions. Signed-off-by: Alex Smith <[email protected]> Cc: Vinod Koul <[email protected]> Cc: Zubair Lutfullah Kakakhel <[email protected]> Cc: [email protected] Signed-off-by: Vinod Koul <[email protected]>
2015-04-01dmaengine: jz4780: add driver for the Ingenic JZ4780 DMA controllerAlex Smith1-0/+49
This patch adds a driver for the DMA controller found in the Ingenic JZ4780. It currently does not implement any support for the programmable firmware feature of the controller - this is not necessary for most uses. It also does not take priority into account when allocating channels, it just allocates the first available channel. This can be implemented later. Signed-off-by: Alex Smith <[email protected]> Signed-off-by: Zubair Lutfullah Kakakhel <[email protected]> [Updated for dmaengine api changes, Add residue support, couple of minor fixes] Signed-off-by: Vinod Koul <[email protected]>
2015-01-21ARM: sunxi: DT: Convert the DTs to use a header for the DMA argumentsMaxime Ripard1-0/+56
The DMA engine for the A10/A20 and derivatives require an opaque extra argument. Add a dt-bindings header, and convert the device trees to it. Signed-off-by: Maxime Ripard <[email protected]>
2014-11-06dmaengine: at_xdmac: creation of the atmel eXtended DMA Controller driverLudovic Desroches1-0/+25
New atmel DMA controller known as XDMAC, introduced with SAMA5D4 devices. Signed-off-by: Ludovic Desroches <[email protected]> Acked-by: Nicolas Ferre <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2014-08-04dmaengine: add device tree binding documentation for the nbpfaxi driverGuennadi Liakhovetski1-0/+20
The nbpfaxi dmaengine driver doesn't define any new bindings, it only uses standard dmaengine bindings and defines 3 flags for the 3rd parameter of the "dmas" property. Signed-off-by: Guennadi Liakhovetski <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Signed-off-by: Vinod Koul <[email protected]>
2013-06-15ARM: at91: dt: add header to define at_hdmac configurationLudovic Desroches1-0/+27
DMA-cell content is a concatenation of several values. In order to keep this stuff human readable, macros are introduced. The values for the FIFO configuration are not the same as the ones used in the configuration register in order to keep backward compatibility. Most devices use the half FIFO configuration but USART ones have to use the ASAP configuration. This parameter was not initially planed to be into the at91 dma dt binding. The third cell will be used to store this parameter, it will become a concatenation of the FIFO configuration and of the peripheral ID. In order to keep backward compatibility i.e. FIFO configuration is equal to 0, we have to perform a translation since the value to put in the register to set half FIFO is 1. Acked-by: Arnd Bergmann <[email protected]> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]> Signed-off-by: Ludovic Desroches <[email protected]> Signed-off-by: Nicolas Ferre <[email protected]>
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