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2019-02-21clk: qcom: clk-rpmh: Add IPA clock supportDavid Dai1-0/+1
The clk-rpmh driver only supports on and off RPMh clock resources. Let's extend the driver by adding support for clocks that are managed by a different type of RPMh resource known as Bus Clock Manager(BCM). The BCM is a configurable shared resource aggregator that scales performance based on a set of frequency points. The Qualcomm IP Accelerator (IPA) clock is an example of a resource that is managed by the BCM and this a requirement from the IPA driver in order to scale its core clock. Signed-off-by: David Dai <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21dt-bindings: marvell,mmp2: Add clock id for the LCDC clockLubomir Rintel1-0/+1
The peripheral clock is required for access the the LCDC registers. It is in fact separate from the "AXI clock" that is optionally used to generate the pixel clock and as such requires a separate clock id. Link: https://lists.freedesktop.org/archives/dri-devel/2019-January/203975.html Signed-off-by: Lubomir Rintel <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21dt-bindings: imx8mq-clock: Add the missing ARM clockAbel Vesa1-1/+2
Add the missing ARM clock which will be used by cpufreq Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Lucas Stach <[email protected]> [[email protected]: Fixed numbering in dt header] Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx8mq: Add support for the CLKO1 clockFabio Estevam1-1/+3
Add the entry for the CLKO1 clock. Signed-off-by: Fabio Estevam <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21dt-bindings: imx: Add clock binding doc for imx8mmBai Ping1-0/+244
Add the clock binding doc for i.MX8MM. Signed-off-by: Bai Ping <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-21clk: imx5: add imx5_SCC2_IPG_GATEMichael Grzeschik1-1/+2
This adds the missing clock for the SCC2 peripheral unit. Signed-off-by: Michael Grzeschik <[email protected]> Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-13dt-bindings: clock: meson8b: add APB clock definitionMartin Blumenstingl1-0/+1
Commit 8e1dd17c8b0e3f ("dt-bindings: clock: meson8b: export the CPU post dividers") added a clock with the name "ABP". The actual name of this clock is "APB". Add a new #define with the same ID but the correct name. The old #define will be dropped in a follow-up patch because each commit in the tree must compile on it's own (the old #define is still used by the clock controller driver). Fixes: 8e1dd17c8b0e3f ("dt-bindings: clock: meson8b: export the CPU post dividers") Signed-off-by: Martin Blumenstingl <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Acked-by: Jerome Brunet <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-02-13dt-bindings: clk: add G12A AO Clock and Reset BindingsNeil Armstrong1-0/+34
Add bindings for the Amlogic G12A AO Clock and Reset controllers. Signed-off-by: Neil Armstrong <[email protected]> Acked-by: Jerome Brunet <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-02-08Merge tag 'armsoc-fixes-5.0' of ↵Linus Torvalds1-13/+13
git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC fixes from Arnd Bergmann: "This is a bit larger than normal, as we had not managed to send out a pull request before traveling for a week without my signing key. There are multiple code fixes for older bugs, all of which should get backported into stable kernels: - tango: one fix for multiplatform configurations broken on other platforms when tango is enabled - arm_scmi: device unregistration fix - iop32x: fix kernel oops from extraneous __init annotation - pxa: remove a double kfree - fsl qbman: close an interrupt clearing race The rest is the usual collection of smaller fixes for device tree files, on the renesas, allwinner, meson, omap, davinci, qualcomm and imx platforms. Some of these are for compile-time warnings, most are for board specific functionality that fails to work because of incorrect settings" * tag 'armsoc-fixes-5.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (30 commits) ARM: tango: Improve ARCH_MULTIPLATFORM compatibility firmware: arm_scmi: provide the mandatory device release callback ARM: iop32x/n2100: fix PCI IRQ mapping arm64: dts: add msm8996 compatible to gicv3 ARM: dts: am335x-shc.dts: fix wrong cd pin level ARM: dts: n900: fix mmc1 card detect gpio polarity ARM: dts: omap3-gta04: Fix graph_port warning ARM: pxa: ssp: unneeded to free devm_ allocated data ARM: dts: r8a7743: Convert to new LVDS DT bindings soc: fsl: qbman: avoid race in clearing QMan interrupt arm64: dts: renesas: r8a77965: Enable DMA for SCIF2 arm64: dts: renesas: r8a7796: Enable DMA for SCIF2 arm64: dts: renesas: r8a774a1: Enable DMA for SCIF2 ARM: dts: da850: fix interrupt numbers for clocksource dt-bindings: imx8mq: Number clocks consecutively arm64: dts: meson: Fix mmc cd-gpios polarity ARM: dts: imx6sx: correct backward compatible of gpt ARM: dts: imx: replace gpio-key,wakeup with wakeup-source property ARM: dts: vf610-bk4: fix incorrect #address-cells for dspi3 ARM: dts: meson8m2: mxiii-plus: mark the SD card detection GPIO active-low ...
2019-02-05dt-bindings: clock: add clock for MT2712Weiyi Lu1-1/+2
Add new clock according to 3rd ECO design change. It's the parent clock of audio clock mux. Signed-off-by: Weiyi Lu <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-02-04dt-bindings: clk: meson: add g12a periph clock controller bindingsJian Hu1-0/+135
Add new clock controller compatible and dt-bindings header for the Everything-Else domain of the g12a SoC Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Jian Hu <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-02-01clk: samsung: exynos5433: Fix name typo in sssxKamil Konieczny1-1/+1
Fix typo in sssx name, there should be three letters 's'. Acked-by: Rob Herring <[email protected]> Reviewed-by: Chanwoo Choi <[email protected]> Signed-off-by: Kamil Konieczny <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2019-02-01clk: samsung: dt-bindings: Add Exynos5433 IMEM CMU clock IDsKamil Konieczny1-0/+6
Add DT bindings to describe the IMEM CMU clocks for the SlimSSS (Slim Security SubSystem). Signed-off-by: Kamil Konieczny <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Chanwoo Choi <[email protected]> [[email protected]: edited commit description] Signed-off-by: Sylwester Nawrocki <[email protected]>
2019-01-24Revert "dt-bindings: marvell,mmp2: Add clock id for the SP clock"Lubomir Rintel1-1/+0
It seems that the kernel has no business managing this clock: once the SP clock is disabled, it's not sufficient to just enable it in order to bring the SP core back up. Pretty sure nothing ever used this and it's safe to remove. This reverts commit e8a2c779141415105825e65a4715f1130bba61b1. Signed-off-by: Lubomir Rintel <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-01-22MIPS: ath79: export switch MDIO reference clockFelix Fietkau1-1/+2
On AR934x, the MDIO reference clock can be configured to a fixed 100 MHz clock. If that feature is not used, it defaults to the main reference clock, like on all other SoC. Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: John Crispin <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: Rob Herring <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-01-22MIPS: ath79: add helpers for setting clocks and expose the ref clockFelix Fietkau1-1/+2
Preparation for transitioning the legacy clock setup code over to OF. Signed-off-by: Felix Fietkau <[email protected]> Signed-off-by: John Crispin <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Paul Burton <[email protected]> Cc: Ralf Baechle <[email protected]> Cc: James Hogan <[email protected]> Cc: Rob Herring <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected]
2019-01-21clk: renesas: r8a774a1: Add missing CANFD clockFabrizio Castro1-0/+1
This patch adds the missing CANFD clock to the r8a774a1 specific clock driver. Signed-off-by: Fabrizio Castro <[email protected]> Reviewed-by: Chris Paterson <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2019-01-21clk: renesas: r8a774c0: Add missing CANFD clockFabrizio Castro1-0/+1
This patch adds the missing CANFD clock to the r8a774c0 specific clock driver. Signed-off-by: Fabrizio Castro <[email protected]> Reviewed-by: Chris Paterson <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2019-01-17ARM: dts: r8a7778: Add HSCIF0/1 supportUlrich Hecht1-0/+2
Add HSCIF0/1 clocks and device nodes, based on Rev. 1.00 of the R-Car M1A datasheet. Signed-off-by: Ulrich Hecht <[email protected]> [geert: Squashed two patches] [geert: Correct HSCIF1 module clock index] [geert: Correct reg properties for non-LPAE] Signed-off-by: Geert Uytterhoeven <[email protected]> Signed-off-by: Simon Horman <[email protected]>
2019-01-16dt-bindings: imx8mq: Number clocks consecutivelyGuido Günther1-13/+13
This fixes a duplicate use of 232 and numbers the clocks without holes. Fixes: 1cf3817bf1f5 ("dt-bindings: Add binding for i.MX8MQ CCM") Signed-off-by: Guido Günther <[email protected]> Reviewed-by: Lucas Stach <[email protected]> Signed-off-by: Shawn Guo <[email protected]>
2019-01-09clk: qcom: smd: Add support for MSM8998 rpm clocksJeffrey Hugo1-0/+10
Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998 for clients to vote on. Signed-off-by: Jeffrey Hugo <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2019-01-07dt-bindings: clk: meson: add ao slow clock path idsJerome Brunet2-1/+13
Add the CLKIDs for the slow clock generation path Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Jerome Brunet <[email protected]> Acked-by: Neil Armstrong <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2019-01-02Merge branch 'for-linus' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input Pull input updates from Dmitry Torokhov: "A tiny pull request this merge window unfortunately, should get more material in for the next release: - new driver for Raspberry Pi's touchscreen (firmware interface) - miscellaneous input driver fixes" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/dtor/input: Input: elan_i2c - add ACPI ID for touchpad in ASUS Aspire F5-573G Input: atmel_mxt_ts - don't try to free unallocated kernel memory Input: drv2667 - fix indentation issues Input: touchscreen - fix coding style issue Input: add official Raspberry Pi's touchscreen driver Input: nomadik-ske-keypad - fix a loop timeout test Input: rotary-encoder - don't log EPROBE_DEFER to kernel log Input: olpc_apsp - remove set but not used variable 'np' Input: olpc_apsp - enable the SP clock Input: olpc_apsp - check FIFO status on open(), not probe() Input: olpc_apsp - drop CONFIG_OLPC dependency clk: mmp2: add SP clock dt-bindings: marvell,mmp2: Add clock id for the SP clock Input: ad7879 - drop platform data support
2018-12-28clk: imx8qxp: make the name of clock ID genericAisheng Dong2-289/+289
SCU clock can be used in a similar way by IMX8QXP and IMX8QM SoCs. Let's make the name of clock ID generic to allow other SoCs to reuse the common part. This patch only changes the clock id name and file name, so no functional change. Cc: Stephen Boyd <[email protected]> Cc: Rob Herring <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Michael Turquette <[email protected]> Cc: [email protected] Signed-off-by: Dong Aisheng <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-12-14Merge branch 'clk-imx7ulp' into clk-nextStephen Boyd1-1/+8
* clk-imx7ulp: clk: imx: imx7ulp: add arm hsrun mode clocks support dt-bindings: clock: imx7ulp: add HSRUN mode related clocks
2018-12-14dt-bindings: clock: imx7ulp: add HSRUN mode related clocksAnson Huang1-1/+8
There are HSRUN mode clock mux and divider in SCG1 module, and SMC1 can control i.MX7ULP CPU to run in RUN mode or HSRUN mode, the mode switch bits are actually a clock mux, add these clocks for clock driver and dtb to use. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-12-14Merge branch 'clk-qcom-8998-resets' into clk-nextStephen Boyd1-0/+94
- Add resets and make Qualcomm MSM8998 GCC driver more functional * clk-qcom-8998-resets: clk: qcom: Drop unused 8998 clock clk: qcom: Leave mmss noc on for 8998 clk: qcom: Add missing msm8998 resets clk: qcom: gcc-msm8998: Add clkref clocks clk: qcom: gcc-msm8998: Disable halt check of UFS clocks clk: qcom: gcc-msm8998: Drop hmss_dvm and lpass_at clk: qcom: Enumerate remaining msm8998 resets clk: qcom: Add xo dummy clk on msm8998 clk: qcom: Fix MSM8998 resets
2018-12-14Merge branches 'clk-imx7ulp', 'clk-imx6-fixes', 'clk-imx-fixes', ↵Stephen Boyd4-1/+796
'clk-imx8qxp' and 'clk-imx8mq' into clk-next - NXP i.MX7ULP SoC clock support - Support for i.MX8QXP SoC clocks - Support for NXP i.MX8MQ clock controllers * clk-imx7ulp: clk: imx: add imx7ulp clk driver clk: imx: implement new clk_hw based APIs clk: imx: make mux parent strings const dt-bindings: clock: add imx7ulp clock binding doc clk: imx: add imx7ulp composite clk support clk: imx: add pfdv2 support clk: imx: add pllv4 support clk: fractional-divider: add CLK_FRAC_DIVIDER_ZERO_BASED flag support clk: imx: add gatable clock divider support * clk-imx6-fixes: clk: imx6q: handle ENET PLL bypass clk: imx6q: optionally get CCM inputs via standard clock handles clk: imx6q: reset exclusive gates on init * clk-imx-fixes: clk: imx6q: add DCICx clocks gate clk: imx6sl: ensure MMDC CH0 handshake is bypassed clk: imx7d: remove UART1 clock setting * clk-imx8qxp: clk: imx: add imx8qxp lpcg driver clk: imx: add lpcg clock support clk: imx: add imx8qxp clk driver clk: imx: add scu clock common part clk: imx: add configuration option for mmio clks dt-bindings: clock: add imx8qxp lpcg clock binding dt-bindings: clock: imx8qxp: add SCU clock IDs firmware: imx: add pm svc headfile dt-bindings: fsl: scu: update power domain binding firmware: imx: remove resource id enums dt-bindings: imx: add scu resource id headfile * clk-imx8mq: clk: imx: Make the i.MX8MQ CCM clock driver CLK_IMX8MQ dependant clk: imx: remove redundant initialization of ret to zero clk: imx: Add SCCG PLL type clk: imx: Add fractional PLL output clock clk: imx: Add clock driver for i.MX8MQ CCM clk: imx: Add imx composite clock dt-bindings: Add binding for i.MX8MQ CCM
2018-12-14Merge branches 'clk-renesas', 'clk-allwinner', 'clk-tegra', 'clk-meson' and ↵Stephen Boyd8-5/+102
'clk-rockchip' into clk-next * clk-renesas: clk: renesas: rcar-gen3: Add HS400 quirk for SD clock clk: renesas: rcar-gen3: Add documentation for SD clocks clk: renesas: rcar-gen3: Set state when registering SD clocks clk: renesas: r8a77995: Simplify PLL3 multiplier/divider clk: renesas: r8a77995: Add missing CPEX clock clk: renesas: r8a77995: Remove non-existent SSP clocks clk: renesas: r8a77995: Remove non-existent VIN5-7 module clocks clk: renesas: r8a77995: Correct parent clock of DU clk: renesas: r8a77990: Correct parent clock of DU clk: renesas: r8a77970: Add CPEX clock clk: renesas: r8a77965: Add CPEX clock clk: renesas: r8a7796: Add CPEX clock clk: renesas: r8a7795: Add CPEX clock clk: renesas: r8a774a1: Add CPEX clock dt-bindings: clock: r8a7796: Remove CSIREF clock dt-bindings: clock: r8a7795: Remove CSIREF clock clk: renesas: Mark rza2_cpg_clk_register static clk: renesas: r7s9210: Add USB clocks clk: renesas: r8a77970: Add RPC clocks clk: renesas: r7s9210: Add SDHI clocks * clk-allwinner: clk: sunxi-ng: a64: Allow parent change for VE clock clk: sunxi-ng: a33: Set CLK_SET_RATE_PARENT for all audio module clocks clk: sunxi-ng: a33: Use sigma-delta modulation for audio PLL clk: sunxi-ng: h3: Allow parent change for ve clock clk: sunxi-ng: add support for suniv F1C100s SoC dt-bindings: clock: Add Allwinner suniv F1C100s CCU clk: sunxi-ng: h3/h5: Fix CSI_MCLK parent clk: sunxi-ng: r40: Force LOSC parent to RTC LOSC output clk: sunxi-ng: sun50i: a64: Use sigma-delta modulation for audio PLL clk: sunxi-ng: a64: Fix gate bit of DSI DPHY clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I clk: sunxi-ng: Add support for H6 DE3 clocks dt-bindings: clock: sun8i-de2: Add H6 DE3 clock description clk: sunxi-ng: h6: Set video PLLs limits clk: sunxi-ng: Use u64 for calculation of NM rate clk: sunxi-ng: Adjust MP clock parent rate when allowed clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width clk: sunxi-ng: enable so-said LDOs for A64 SoC's pll-mipi clock * clk-tegra: clk: tegra: Return the exact clock rate from clk_round_rate clk: tegra30: Use Tegra CPU powergate helper function soc/tegra: pmc: Drop SMP dependency from CPU APIs clk: tegra: Fix maximum audio sync clock for Tegra124/210 clk: tegra: get rid of duplicate defines clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC clk: tegra20: Turn EMC clock gate into divider * clk-meson: (25 commits) clk: meson: axg-audio: use the clk input helper function clk: meson: add clk-input helper function clk: meson: Mark some things static clk: meson: meson8b: add the read-only video clock trees clk: meson: meson8b: add the fractional divider for vid_pll_dco clk: meson: meson8b: fix the offset of vid_pll_dco's N value clk: meson: Fix GXL HDMI PLL fractional bits width clk: meson: meson8b: add the CPU clock post divider clocks clk: meson: meson8b: rename cpu_div2/cpu_div3 to cpu_in_div2/cpu_in_div3 clk: meson: clk-regmap: add read-only gate ops clk: meson: meson8b: allow changing the CPU clock tree clk: meson: meson8b: run from the XTAL when changing the CPU frequency clk: meson: meson8b: add support for more M/N values in sys_pll clk: meson: meson8b: mark the CPU clock as CLK_IS_CRITICAL clk: meson: meson8b: do not use cpu_div3 for cpu_scale_out_sel clk: meson: clk-pll: check if the clock is already enabled clk: meson: meson8b: fix the width of the cpu_scale_div clock clk: meson: meson8b: fix incorrect divider mapping in cpu_scale_table clk: meson: meson8b: use the HHI syscon if available dt-bindings: clock: meson8b: use the registers from the HHI syscon ... * clk-rockchip: clk: rockchip: add clock-id to gate of ACODEC for rk3328 clk: rockchip: add clock ID of ACODEC for rk3328 clk: rockchip: fix ID of 8ch clock of I2S1 for rk3328 clk: rockchip: fix I2S1 clock gate register for rk3328 clk: rockchip: make rk3188 hclk_vio_bus critical clk: rockchip: fix rk3188 sclk_mac_lbtest parameter ordering clk: rockchip: fix rk3188 sclk_smc gate data clk: rockchip: fix typo in rk3188 spdif_frac parent
2018-12-14Merge branches 'clk-managed-registration', 'clk-spdx', 'clk-remove-basic' ↵Stephen Boyd2-18/+2
and 'clk-ops-const' into clk-next - Make devm_of_clk_add_hw_provider() use parent dt node if necessary - Various SPDX taggings - Mark clk_ops const when possible * clk-managed-registration: clk: bd718x7: Initial support for ROHM bd71837/bd71847 PMIC clock clk: apcs-msm8916: simplify probe cleanup by using devm clk: clk-twl6040: Free of_provider at remove clk: rk808: use managed version of of_provider registration clk: clk-hi655x: Free of_provider at remove clk: of-provider: look at parent if registered device has no provider info clk: Add kerneldoc to managed of-provider interfaces * clk-spdx: clk: Tag basic clk types with SPDX clk: Tag clk core files with SPDX clk: bcm2835: Switch to SPDX identifier * clk-remove-basic: clk: Loongson1: Remove usage of CLK_IS_BASIC clk: samsung: s3c2410: Remove usage of CLK_IS_BASIC clk: versatile: sp810: Remove usage of CLK_IS_BASIC clk: hisilicon: Remove usage of CLK_IS_BASIC clk: h8300: Remove usage of CLK_IS_BASIC clk: axm5516: Remove usage of CLK_IS_BASIC clk: st: Remove usage of CLK_IS_BASIC clk: renesas: Remove usage of CLK_IS_BASIC * clk-ops-const: clk: s2mps11: constify clk_ops structure clk: pxa: constify clk_ops structures clk: pistachio: constify clk_ops structures clk: palmas: constify clk_ops structure clk: max77686: constify clk_ops structure
2018-12-14Merge branch 'clk-qcom-sdm845-lpass' into clk-nextStephen Boyd2-0/+17
- Qualcomm SDM845 audio subsystem clks * clk-qcom-sdm845-lpass: clk: qcom: Add lpass clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM LPASS clock bindings dt-bindings: clock: Update GCC bindings for protected-clocks
2018-12-14Merge branches 'clk-qcom-kconfig', 'clk-qcom-gpucc', 'clk-qcom-qcs404-rpm', ↵Stephen Boyd2-0/+28
'clk-qcom-spi' and 'clk-qcom-videocc-binding' into clk-next - Qualcomm SDM845 GPU clock controllers - Qualcomm QCS404 RPM clk support * clk-qcom-kconfig: clk: qcom: Move to menuconfig and reduce lines * clk-qcom-gpucc: dt-bindings: clock: qcom: Fix the xo parent in gpucc example clk: qcom: gpu_cc_gmu_clk_src has 5 parents, not 6 clk: qcom: Add a dummy enable function for GX gdsc clk: qcom: gdsc: Don't override existing gdsc pd functions clk: qcom: Add graphics clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Graphics clock bindings * clk-qcom-qcs404-rpm: clk: qcom: smd: Add support for QCS404 rpm clocks * clk-qcom-spi: clk: qcom: msm8916: Additional clock rates for spi * clk-qcom-videocc-binding: dt-bindings: clock: Require #reset-cells in sdm845-videocc
2018-12-13dt-bindings: clock: add imx8qxp lpcg clock bindingAisheng Dong1-0/+153
The Low-Power Clock Gate (LPCG) modules contain a local programming model to control the clock gates for the peripherals. An LPCG module is used to locally gate the clocks for the associated peripheral. Note: This level of clock gating is provided after the clocks are generated by the SCU resources and clock controls. Thus even if the clock is enabled by these control bits, it might still not be running based on the base resource. Cc: Stephen Boyd <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: [email protected] Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-12-13dt-bindings: clock: imx8qxp: add SCU clock IDsAisheng Dong1-0/+136
Add IMX8QXP SCU clock IDs. Cc: Stephen Boyd <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Sascha Hauer <[email protected]> Cc: [email protected] Cc: [email protected] Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-12-11clk: qcom: Add missing msm8998 resetsJeffrey Hugo1-0/+2
commit c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") missed two USB2 resets. Add them. Fixes: c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets") Signed-off-by: Jeffrey Hugo <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-12-10clk: imx6q: add DCICx clocks gateAnson Huang1-1/+3
On i.MX6QP/i.MX6Q/i.MX6DL, there are DCIC1/DCIC2 clocks gate in CCM_CCGR0 register, add them into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-12-05clk: qcom: gcc-msm8998: Add clkref clocksBjorn Andersson1-0/+5
Add clkref clocks for usb3, hdmi, ufs, pcie, and usb2. They are all sourced off CXO_IN, so parent them off "xo" until a proper link to the rpmcc can be described in DT. Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-12-05clk: qcom: Enumerate remaining msm8998 resetsJeffrey Hugo1-0/+87
The current list of defined resets is incomplete compared to what the hardware implements. Enumerate the remaining resets according to the hardware documentation. Signed-off-by: Jeffrey Hugo <[email protected]> Acked-by: Bjorn Andersson <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-12-04clk: renesas: r8a77995: Add missing CPEX clockGeert Uytterhoeven1-0/+1
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Feb 28, 2018) added the CPEX clock on R-Car D3. This clock can be selected as a clock source for CMT1 (Compare Match Timer Type 1). Add the missing clock to the DT bindings header, and implement support for it in the clock driver. Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Stephen Boyd <[email protected]>
2018-12-04clk: renesas: r8a77995: Remove non-existent SSP clocksGeert Uytterhoeven1-2/+2
The R-Car Gen3 HardWare Manual Errata for Rev. 0.80 (Dec 22, 2017, and Feb 28, 2018) removed the SSPSRC, SSP1, and SSP2 clocks on R-Car D3, as this SoC does not have a Stream and Security Processor. As these definitions were never used, they can just be removed. The freed slots in the DT bindings header must not be reused, though. Fixes: 714c53aa2e2d6d60 ("clk: renesas: Add r8a77995 CPG Core Clock Definitions") Fixes: d71e851d82c6cfe5 ("clk: renesas: cpg-mssr: Add R8A77995 support") Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Stephen Boyd <[email protected]>
2018-12-04dt-bindings: clock: r8a7796: Remove CSIREF clockGeert Uytterhoeven1-1/+1
The R-Car Gen3 HardWare Manual Errata for Rev. 0.52 (Nov 30, 2016) removed the CSI reference clock on R-Car M3-W. As this definition was never used, it can just be removed. The freed slot in the DT bindings header must not be reused, though. Fixes: 972610fb23b08dd5 ("clk: renesas: Add r8a7796 CPG Core Clock Definitions") Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Stephen Boyd <[email protected]>
2018-12-04dt-bindings: clock: r8a7795: Remove CSIREF clockGeert Uytterhoeven1-1/+1
The R-Car Gen3 HardWare Manual Errata for Rev. 0.52 (Nov 30, 2016) removed the CSI reference clock on R-Car H3. As this definition was never used, it can just be removed. The freed slot in the DT bindings header must not be reused, though. Fixes: 9d0c3c682033d3f1 ("clk: shmobile: Add r8a7795 CPG Core Clock Definitions") Signed-off-by: Geert Uytterhoeven <[email protected]> Acked-by: Stephen Boyd <[email protected]>
2018-12-04dt-bindings: clock: Add Allwinner suniv F1C100s CCUMesih Kilinc1-0/+70
Add compatiple string for Allwinner suniv F1C100s CCU. Add clock and reset definitions. Signed-off-by: Mesih Kilinc <[email protected]> Acked-by: Maxime Ripard <[email protected]> Acked-by: Stephen Boyd <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2018-12-03dt-bindings: clock: add imx7ulp clock binding docA.s. Dong1-0/+109
i.MX7ULP Clock functions are under joint control of the System Clock Generation (SCG) modules, Peripheral Clock Control (PCC) modules, and Core Mode Controller (CMC)1 blocks Note IMX7ULP has two clock domains: M4 and A7. This binding doc is only for A7 clock domain. Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Stephen Boyd <[email protected]> Cc: Michael Turquette <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Anson Huang <[email protected]> Cc: Bai Ping <[email protected]> Signed-off-by: Dong Aisheng <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-12-03dt-bindings: Add binding for i.MX8MQ CCMLucas Stach1-0/+395
This adds the binding for the i.MX8MQ Clock Controller Module. Signed-off-by: Lucas Stach <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-12-03dt-bindings: clock: Introduce QCOM LPASS clock bindingsTaniya Das2-0/+17
Add device tree bindings for Low Power Audio subsystem clock controller for Qualcomm Technology Inc's SDM845 SoCs. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-11-29clk: mediatek: add clock support for MT7629 SoCRyder Lee1-0/+203
Add all supported clocks exported from every susbystem found on MT7629 SoC. Signed-off-by: Wenzhen Yu <[email protected]> Signed-off-by: Ryder Lee <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-11-27dt-bindings: clock: Introduce QCOM Graphics clock bindingsAmit Nischal1-0/+24
Add device tree bindings for graphics clock controller for Qualcomm Technology Inc's SDM845 SoCs. Signed-off-by: Amit Nischal <[email protected]> Reviewed-by: Rob Herring <[email protected]> [[email protected]: Add input clocks property] Signed-off-by: Stephen Boyd <[email protected]>
2018-11-26Merge branch 'v4.21-shared/clkids' into v4.21-clk/nextHeiko Stuebner1-0/+1
2018-11-26clk: rockchip: add clock ID of ACODEC for rk3328Katsuhiro Suzuki1-0/+1
This patch adds clock ID of audio CODEC (ACODEC) for rk3328. Signed-off-by: Katsuhiro Suzuki <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>