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2023-10-30Merge branches 'clk-renesas', 'clk-kunit', 'clk-regmap' and ↵Stephen Boyd1-0/+242
'clk-frac-divider' into clk-next - Make clk kunit tests work with lockdep - Fix clk gate kunit test for big-endian - Convert more than a handful of clk drivers to use regmap maple tree - Consider the CLK_FRAC_DIVIDER_ZERO_BASED in fractional divider clk implementation * clk-renesas: (23 commits) clk: renesas: r9a08g045: Add clock and reset support for SDHI1 and SDHI2 clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R() clk: renesas: Add minimal boot support for RZ/G3S SoC clk: renesas: rzg2l: Add divider clock for RZ/G3S clk: renesas: rzg2l: Refactor SD mux driver clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header clk: renesas: rzg2l: Add struct clk_hw_data clk: renesas: rzg2l: Add support for RZ/G3S PLL clk: renesas: rzg2l: Remove critical area clk: renesas: rzg2l: Fix computation formula clk: renesas: rzg2l: Trust value returned by hardware clk: renesas: rzg2l: Lock around writes to mux register clk: renesas: rzg2l: Wait for status bit of SD mux before continuing clk: renesas: rcar-gen3: Extend SDnH divider table dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoC clk: renesas: r8a7795: Constify r8a7795_*_clks clk: renesas: r9a06g032: Name anonymous structs clk: renesas: r9a06g032: Fix kerneldoc warning clk: renesas: rzg2l: Use u32 for flag and mux_flags clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields ... * clk-kunit: clk: Fix clk gate kunit test on big-endian CPUs clk: Parameterize clk_leaf_mux_set_rate_parent clk: Drive clk_leaf_mux_set_rate_parent test from clk_ops * clk-regmap: clk: versaclock7: Convert to use maple tree register cache clk: versaclock5: Convert to use maple tree register cache clk: versaclock3: Convert to use maple tree register cache clk: versaclock3: Remove redundant _is_writeable() clk: si570: Convert to use maple tree register cache clk: si544: Convert to use maple tree register cache clk: si5351: Convert to use maple tree register cache clk: si5341: Convert to use maple tree register cache clk: si514: Convert to use maple tree register cache clk: cdce925: Convert to use maple tree register cache * clk-frac-divider: clk: fractional-divider: tests: Add test suite for edge cases clk: fractional-divider: Improve approximation when zero based and export
2023-10-30Merge branches 'clk-debugfs', 'clk-spreadtrum', 'clk-sifive', 'clk-counted' ↵Stephen Boyd3-1/+384
and 'clk-qcom' into clk-next - Add consumer info to clk debugfs - Fix various clk drivers that have clk_hw_onecell_data not at the end of an allocation * clk-debugfs: clk: Allow phase adjustment from debugfs clk: Show active consumers of clocks in debugfs * clk-spreadtrum: clk: sprd: Composite driver support offset config * clk-sifive: clk: sifive: Allow building the driver as a module clk: analogbits: Allow building the library as a module * clk-counted: clk: socfpga: agilex: Add bounds-checking coverage for struct stratix10_clock_data clk: socfpga: Fix undefined behavior bug in struct stratix10_clock_data clk: visconti: Add bounds-checking coverage for struct visconti_pll_provider clk: visconti: Fix undefined behavior bug in struct visconti_pll_provider * clk-qcom: (36 commits) clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock provider clk: qcom: ipq5332: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq9574: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq5018: drop the CLK_SET_RATE_PARENT flag from GPLL clocks clk: qcom: ipq6018: drop the CLK_SET_RATE_PARENT flag from PLL clocks clk: qcom: ipq8074: drop the CLK_SET_RATE_PARENT flag from PLL clocks clk: qcom: gcc-ipq6018: add QUP6 I2C clock clk: qcom: apss-ipq6018: ipq5332: add safe source switch for a53pll clk: qcom: apss-ipq-pll: Fix 'l' value for ipq5332_pll_config clk: qcom: apss-ipq-pll: Use stromer plus ops for stromer plus pll clk: qcom: clk-alpha-pll: introduce stromer plus ops clk: qcom: config IPQ_APSS_6018 should depend on QCOM_SMEM clk: qcom: videocc-sm8550: switch to clk_lucid_ole_pll_configure clk: qcom: gpucc-sm8550: switch to clk_lucid_ole_pll_configure clk: qcom: Replace of_device.h with explicit includes clk: qcom: smd-rpm: Move CPUSS_GNoC clock to interconnect clk: qcom: cbf-msm8996: Convert to platform remove callback returning void clk: qcom: gcc-sm8150: Fix gcc_sdcc2_apps_clk_src clk: qcom: Add GCC driver support for SM4450 dt-bindings: clock: qcom: Add GCC clocks for SM4450 ...
2023-10-30Merge branches 'clk-doc', 'clk-amlogic', 'clk-mediatek', 'clk-twl' and ↵Stephen Boyd3-1/+279
'clk-imx' into clk-next - Add clock driver for TWL6032 * clk-doc: clk: linux/clk-provider.h: fix kernel-doc warnings and typos * clk-amlogic: clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILS clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controller clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver dt-bindings: clock: document Amlogic S4 SoC peripherals clock controller dt-bindings: clock: document Amlogic S4 SoC PLL clock controller * clk-mediatek: clk: mediatek: fix double free in mtk_clk_register_pllfh() clk: mediatek: clk-mt2701: Add check for mtk_alloc_clk_data clk: mediatek: clk-mt7629: Add check for mtk_alloc_clk_data clk: mediatek: clk-mt7629-eth: Add check for mtk_alloc_clk_data clk: mediatek: clk-mt6797: Add check for mtk_alloc_clk_data clk: mediatek: clk-mt6779: Add check for mtk_alloc_clk_data clk: mediatek: clk-mt6765: Add check for mtk_alloc_clk_data * clk-twl: clk: twl: add clock driver for TWL6032 * clk-imx: clk: imx: imx8qm/qxp: add more resources to whitelist clk: imx: scu: ignore clks not owned by Cortex-A partition clk: imx8: remove MLB support clk: imx: imx8qm-rsrc: drop VPU_UART/VPUCORE clk: imx: imx8qxp: correct the enet clocks for i.MX8DXL clk: imx: imx8qxp: Fix elcdif_pll clock clk: imx: imx8dxl-rsrc: keep sorted in the ascending order clk: imx: imx6sx: Allow a different LCDIF1 clock parent clk: imx: imx8mq: correct error handling path clk: imx8mp: Remove non-existent IMX8MP_CLK_AUDIOMIX_PDM_ROOT clk: imx: imx8: Simplify clk_imx_acm_detach_pm_domains() clk: imx: imx8: Add a message in case of devm_clk_hw_register_mux_parent_data_table() error clk: imx: imx8: Fix an error handling path in imx8_acm_clk_probe() clk: imx: imx8: Fix an error handling path if devm_clk_hw_register_mux_parent_data_table() fails clk: imx: imx8: Fix an error handling path in clk_imx_acm_attach_pm_domains() clk: imx: Select MXC_CLK for CLK_IMX8QXP
2023-10-05dt-bindings: clock: renesas,rzg2l-cpg: Document RZ/G3S SoCClaudiu Beznea1-0/+242
Add documentation for the RZ/G3S CPG. The RZ/G3S CPG module is almost identical to the one available in RZ/G2{L,UL}, the exception being some core clocks as follows: - The SD clock is composed of a mux and a divider, and the divider has some limitations (div = 1 cannot be set if mux rate is 800MHz), - There are 3 SD clocks, - The OCTA and TSU clocks are specific to RZ/G3S, - PLL1/4/6 are specific to RZ/G3S with its own computation formula. Even with this RZ/G3S could use the same bindings as RZ/G2L. Along with documentation bindings for the RZ/G3S (R9A08G045) Clock Pulse Generator (CPG) core clocks, module clocks and resets were added. Signed-off-by: Claudiu Beznea <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2023-10-04clk: imx8mp: Remove non-existent IMX8MP_CLK_AUDIOMIX_PDM_ROOTAdam Ford1-1/+0
The TRM shows there is only one AUDIOMIX PDM Root Clock Select register, and it's called IMX8MP_CLK_AUDIOMIX_PDM_SEL. That selector doesn't appear to have any more children and the MICFIL driver can reference IMX8MP_CLK_AUDIOMIX_PDM_SEL directly without the need for any other. Remove this errant clock, since it doesn't really exist. Signed-off-by: Adam Ford <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-09-27dt-bindings: clock: document Amlogic S4 SoC peripherals clock controllerYu Tu1-0/+236
Add the S4 peripherals clock controller dt-bindings in the S4 SoC family. Signed-off-by: Yu Tu <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2023-09-27dt-bindings: clock: document Amlogic S4 SoC PLL clock controllerYu Tu1-0/+43
Add the S4 PLL clock controller dt-bindings in the S4 SoC family. Signed-off-by: Yu Tu <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Jerome Brunet <[email protected]>
2023-09-20Merge branch '[email protected]' into clk-for-6.7Bjorn Andersson1-0/+197
Merge the SM4450 RPMHCC and GCC through a topic branch, to allow reuse of the defines from the DeviceTree binding in the DeviceTree source.
2023-09-20dt-bindings: clock: qcom: Add GCC clocks for SM4450Ajit Pandey1-0/+197
Add support for qcom global clock controller bindings for SM4450 platform. Signed-off-by: Ajit Pandey <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-20clk: qcom: mmcc-msm8974: remove ocmemcx_ahb_clkLuca Weiss1-1/+0
According to a commit in the 3.4 vendor kernel sources[0] the ocmemcx_ahb_clk clock "is controlled by RPM and should not be touched by APPS.". [0] https://git.codelinaro.org/clo/la/kernel/msm/-/commit/37df5f2d91b4d5768b37fcaacaeea958dd683ebc And indeed, when using MDSS+GPU+OCMEM on MSM8226 and not using clk_ignore_unused, when Linux tries to disable the clock the device crashes and reboots. And since there's also no evidence of this clock in msm8974 vendor kernel sources, remove the clock for msm8226 and msm8974. Fixes: d8b212014e69 ("clk: qcom: Add support for MSM8974's multimedia clock controller (MMCC)") Signed-off-by: Luca Weiss <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/20230902-msm8226-ocmemcx_ahb_clk-remove-v1-1-8124dbde83b9@z3ntu.xyz Signed-off-by: Bjorn Andersson <[email protected]>
2023-09-19dt-bindings: clock: qcom: Add SM8550 camera clock controllerJagadeesh Kona1-0/+187
Add device tree bindings for the camera clock controller on Qualcomm SM8550 platform. Co-developed-by: Taniya Das <[email protected]> Signed-off-by: Taniya Das <[email protected]> Signed-off-by: Jagadeesh Kona <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-30Merge tag 'clk-for-linus' of ↵Linus Torvalds31-184/+523
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk subsystem updates from Stephen Boyd: "This pull request is full of clk driver changes. In fact, there aren't any changes to the clk framework this time around. That's probably because everyone was on vacation (yours truly included). We did lose a couple clk drivers this time around because nobody was using those devices. That skews the diffstat a bit, but either way, nothing looks out of the ordinary here. The usual suspects are chugging along adding support for more SoCs and fixing bugs. If I had to choose, I'd say the theme for the past few months has been "polish". There's quite a few patches that migrate to devm_platform_ioremap_resource() in here. And there's more than a handful of patches that move the NR_CLKS define from the DT binding header to the driver. There's even patches that migrate drivers to use clk_parent_data and clk_hw to describe clk tree topology. It seems that the spring (summer?) cleaning bug got some folks, or the semiconductor shortage finally hit the software side. New Drivers: - StarFive JH7110 SoC clock drivers - Qualcomm IPQ5018 Global Clock Controller driver - Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK Removed Drivers: - Remove non-OF mmp clk drivers - Remove OXNAS clk driver Updates: - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Move defines for numbers of clks (NR_CLKS) from DT headers to drivers - Introduce kstrdup_and_replace() and use it - Add PLL rates for Rockchip rk3568 - Add the display clock tree for Rockchip rv1126 - Add Audio Clock Generator (ADG) clocks on Renesas R-Car Gen3 and RZ/G2 SoCs - Convert sun9i-mmc clock to use devm_platform_get_and_ioremap_resource() - Fix function name in a comment in ccu_mmc_timing.c - Parameter name correction for ccu_nkm_round_rate() - Implement CLK_SET_RATE_PARENT for Allwinner NKM clocks, i.e. consider alternative parent rates when determining clock rates - Set CLK_SET_RATE_PARENT for Allwinner A64 pll-mipi - Support finding closest (as opposed to closest but not higher) clock rate for NM, NKM, mux and div type clocks, as use it for Allwinner A64 pll-video0 - Prefer current parent rate if able to generate ideal clock rate for Allwinner NKM clocks - Clean up Qualcomm SMD RPM driver, with interconnect bus clocks moved out to the interconnect drivers - Fix various PM runtime bugs across many Qualcomm clk drivers - Migrate Qualcomm MDM9615 is to parent_hw and parent_data - Add network related resets on Qualcomm IPQ4019 - Add a couple missing USB related clocks to Qualcomm IPQ9574 - Add missing gpll0_sleep_clk_src to Qualcomm MSM8917 global clock controller - In the Qualcomm QDU1000 global clock controller, GDSCs, clkrefs, and GPLL1 are added, while PCIe pipe clock, SDCC rcg ops are corrected - Add missing GDSCs to and correct GDSCs for the SC8280XP global clock controller driver - Support retention for the Qualcomm SC8280XP display clock controller GDSCs. - Qualcommm's SDCC apps_clk_src is marked with CLK_OPS_PARENT_ENABLE to fix issues with missing parent clocks across sc7180, sm7150, sm6350 and sm8250, while sm8450 is corrected to use floor ops - Correct Qualcomm SM6350 GPU clock controller's clock supplies - Drop unwanted clocks from the Qualcomm IPQ5332 GCC driver - Add missing OXILICX GDSC to Qualcomm MSM8226 GCC - Change the delay in the Qualcomm reset controller to fsleep() for correctness - Extend the Qualcomm SM83550 Video clock controller to support SC8280XP - Add graphics clock support on Renesas RZ/G2M, RZ/G2N, RZ/G2E, and R-Car H3, M3-W, and M3-N SoCs - Add Clocked Serial Interface (CSI) clocks on Renesas RZ/V2M - Add PWM (MTU3) clock and reset on Renesas RZ/G2UL and RZ/Five - Add the PDM IPC clock for i.MX93 - Add 519.75MHz frequency support for i.MX9 PLL - Simplify the .determine_rate() implementation for i.MX GPR mux - Make the i.MX8QXP LPCG clock use devm_platform_ioremap_resource() - Add the audio mux clock to i.MX8 - Fix the SPLL2 MULT range for PLLv4 - Update the SPLL2 type in i.MX8ULP - Fix the SAI4 clock on i.MX8MP - Add silicon revision print for i.MX25 on clocks init - Drop the return value from __mx25_clocks_init() - Fix the clock pauses on no-op set_rate for i.MX8M composite clock - Drop restrictions for i.MX PLL14xx and fix its max prediv value - Drop the 393216000 and 361267200 from i.MX PLL14xx rate table to allow glitch free switching" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (207 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source ...
2023-08-30Merge tag 'devicetree-for-6.6' of ↵Linus Torvalds10-10/+10
git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux Pull devicetree updates from Rob Herring: "DT core: - Add support for generating DT nodes for PCI devices. This is the groundwork for applying overlays to PCI devices containing non-discoverable downstream devices. - DT unittest additions to check reverted changesets, to test for refcount issues, and to test unresolved symbols. Also, various clean-ups of the unittest along the way. - Refactor node and property manipulation functions to better share code with old API and changeset API - Refactor changeset print functions to a common implementation - Move some platform_device specific functions into of_platform.c Bindings: - Treewide fixing of typos - Treewide clean-up of SPDX tags to use 'OR' consistently - Last chunk of dropping unnecessary quotes. With that, the check for unnecessary quotes is enabled in yamllint. - Convert ftgmac100, zynqmp-genpd, pps-gpio, syna,rmi4, and qcom,ssbi bindings to DT schema format - Add Allwinner V3s xHCI USB, Saef SF-TC154B display, QCom SM8450 Inline Crypto Engine, QCom SM6115 UFS, QCom SDM670 PDC interrupt controller, Arm 2022 Cortex cores, and QCom IPQ9574 Crypto bindings - Fixes for Rockchip DWC PCI binding - Ensure all properties are evaluated on USB connector schema - Fix dt-check-compatible script to find of_device_id instances with compiler annotations" * tag 'devicetree-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (64 commits) dt-bindings: usb: Add V3s compatible string for OHCI dt-bindings: usb: Add V3s compatible string for EHCI dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B dt-bindings: vendor-prefixes: document Saef Technology dt-bindings: thermal: lmh: update maintainer address of: unittest: Fix of_unittest_pci_node() kconfig dependencies dt-bindings: crypto: ice: Document sm8450 inline crypto engine dt-bindings: ufs: qcom: Add ICE to sm8450 example dt-bindings: ufs: qcom: Add sm6115 binding dt-bindings: ufs: qcom: Add reg-names property for ICE dt-bindings: yamllint: Enable quoted string check dt-bindings: Drop remaining unneeded quotes of: unittest-data: Fix whitespace - angular brackets of: unittest-data: Fix whitespace - indentation of: unittest-data: Fix whitespace - blank lines of: unittest-data: Convert remaining overlay DTS files to sugar syntax of: overlay: unittest: Add test for unresolved symbol of: unittest: Add separators to of_unittest_overlay_high_level() of: unittest: Cleanup partially-applied overlays of: unittest: Merge of_unittest_apply{,_revert}_overlay_check() ...
2023-08-30Merge branch 'clk-qcom' into clk-nextStephen Boyd8-45/+208
* clk-qcom: (87 commits) clk: qcom: Fix SM_GPUCC_8450 dependencies clk: qcom: smd-rpm: Set XO rate and CLK_IS_CRITICAL on PCNoC clk: qcom: smd-rpm: Add a way to define bus clocks with rate and flags clk: qcom: gcc-ipq5018: change some variable static clk: qcom: gcc-ipq4019: add missing networking resets dt-bindings: clock: qcom: ipq4019: add missing networking resets clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC clk: qcom: gcc-qdu1000: Update the RCGs ops clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops clk: qcom: gcc-qdu1000: Add support for GDSCs clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock clk: qcom: gcc-qdu1000: Fix clkref clocks handling clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock clk: qcom: ipq5332: drop the mem noc clocks clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks ...
2023-08-30Merge branches 'clk-imx', 'clk-samsung', 'clk-annotate', 'clk-marvell' and ↵Stephen Boyd18-139/+31
'clk-lmk' into clk-next - Add __counted_by to struct clk_hw_onecell_data and struct spmi_pmic_div_clk_cc - Remove non-OF mmp clk drivers - Move number of clks from DT headers to drivers * clk-imx: clk: imx: pll14xx: dynamically configure PLL for 393216000/361267200Hz clk: imx: pll14xx: align pdiv with reference manual clk: imx: composite-8m: fix clock pauses when set_rate would be a no-op clk: imx25: make __mx25_clocks_init return void clk: imx25: print silicon revision during init dt-bindings: clocks: imx8mp: make sai4 a dummy clock clk: imx8mp: fix sai4 clock clk: imx: imx8ulp: update SPLL2 type clk: imx: pllv4: Fix SPLL2 MULT range clk: imx: imx8: add audio clock mux driver dt-bindings: clock: fsl,imx8-acm: Add audio clock mux support clk: imx: clk-imx8qxp-lpcg: Convert to devm_platform_ioremap_resource() clk: imx: clk-gpr-mux: Simplify .determine_rate() clk: imx: Add 519.75MHz frequency support for imx9 pll clk: imx93: Add PDM IPG clk dt-bindings: clock: imx93: Add PDM IPG clk * clk-samsung: dt-bindings: clock: samsung: remove define with number of clocks clk: samsung: exynoautov9: do not define number of clocks in bindings clk: samsung: exynos850: do not define number of clocks in bindings clk: samsung: exynos7885: do not define number of clocks in bindings clk: samsung: exynos5433: do not define number of clocks in bindings clk: samsung: exynos5420: do not define number of clocks in bindings clk: samsung: exynos5410: do not define number of clocks in bindings clk: samsung: exynos5260: do not define number of clocks in bindings clk: samsung: exynos5250: do not define number of clocks in bindings clk: samsung: exynos4: do not define number of clocks in bindings clk: samsung: exynos3250: do not define number of clocks in bindings * clk-annotate: clk: qcom: clk-spmi-pmic-div: Annotate struct spmi_pmic_div_clk_cc with __counted_by clk: Annotate struct clk_hw_onecell_data with __counted_by * clk-marvell: clk: pxa910: Move number of clocks to driver source clk: pxa1928: Move number of clocks to driver source clk: pxa168: Move number of clocks to driver source clk: mmp2: Move number of clocks to driver source clk: mmp: Remove old non-OF clock drivers * clk-lmk: clk: lmk04832: Support using PLL1_LD as SPI readback pin clk: lmk04832: Don't disable vco clock on probe fail clk: lmk04832: Set missing parent_names for output clocks
2023-08-30Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ↵Stephen Boyd8-0/+470
'clk-rockchip' into clk-next - Add Versa3 clk generator to support 48KHz playback/record with audio codec on RZ/G2L SMARC EVK - Introduce kstrdup_and_replace() and use it * clk-versa: clk: vc7: Use i2c_get_match_data() instead of device_get_match_data() clk: vc5: Use i2c_get_match_data() instead of device_get_match_data() clk: versaclock3: Switch to use i2c_driver's probe callback clk: Add support for versa3 clock driver dt-bindings: clock: Add Renesas versa3 clock generator bindings * clk-strdup: clk: ti: Replace kstrdup() + strreplace() with kstrdup_and_replace() clk: tegra: Replace kstrdup() + strreplace() with kstrdup_and_replace() driver core: Replace kstrdup() + strreplace() with kstrdup_and_replace() lib/string_helpers: Add kstrdup_and_replace() helper * clk-amlogic: (22 commits) dt-bindings: soc: amlogic: document System Control registers dt-bindings: clock: amlogic: convert amlogic,gxbb-aoclkc.txt to dt-schema dt-bindings: clock: amlogic: convert amlogic,gxbb-clkc.txt to dt-schema clk: meson: axg-audio: move bindings include to main driver clk: meson: meson8b: move bindings include to main driver clk: meson: a1: move bindings include to main driver clk: meson: eeclk: move bindings include to main driver clk: meson: aoclk: move bindings include to main driver dt-bindings: clk: axg-audio-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock ids dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock ids dt-bindings: clk: meson8b-clkc: expose all clock ids dt-bindings: clk: g12a-aoclkc: expose all clock ids dt-bindings: clk: g12a-clks: expose all clock ids dt-bindings: clk: axg-clkc: expose all clock ids dt-bindings: clk: gxbb-clkc: expose all clock ids clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKS clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKS clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKS ... * clk-allwinner: clk: sunxi-ng: nkm: Prefer current parent rate clk: sunxi-ng: a64: select closest rate for pll-video0 clk: sunxi-ng: div: Support finding closest rate clk: sunxi-ng: mux: Support finding closest rate clk: sunxi-ng: nkm: Support finding closest rate clk: sunxi-ng: nm: Support finding closest rate clk: sunxi-ng: Add helper function to find closest rate clk: sunxi-ng: Add feature to find closest rate clk: sunxi-ng: a64: allow pll-mipi to set parent's rate clk: sunxi-ng: nkm: consider alternative parent rates when determining rate clk: sunxi-ng: nkm: Use correct parameter name for parent HW clk: sunxi-ng: Modify mismatched function name clk: sunxi: sun9i-mmc: Use devm_platform_get_and_ioremap_resource() * clk-rockchip: clk: rockchip: rv1126: Add PD_VO clock tree clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHz clk: rockchip: rk3568: Add PLL rate for 101MHz
2023-08-30Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and ↵Stephen Boyd1-0/+80
'clk-cleanup' into clk-next - Remove OXNAS clk driver * clk-bindings: dt-bindings: clock: versal: Convert the xlnx,zynqmp-clk.txt to yaml dt-bindings: clock: xlnx,versal-clk: drop select:false dt-bindings: clock: versal: Add versal-net compatible string dt-bindings: clock: ast2600: Add I3C and MAC reset definitions dt-bindings: arm: hisilicon,cpuctrl: Merge "hisilicon,hix5hd2-clock" into parent binding * clk-starfive: reset: starfive: jh7110: Add StarFive STG/ISP/VOUT resets support clk: starfive: Simplify .determine_rate() clk: starfive: Add StarFive JH7110 Video-Output clock driver clk: starfive: Add StarFive JH7110 Image-Signal-Process clock driver clk: starfive: Add StarFive JH7110 System-Top-Group clock driver clk: starfive: jh7110-sys: Add PLL clocks source from DTS clk: starfive: Add StarFive JH7110 PLL clock driver dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset generator dt-bindings: clock: Add StarFive JH7110 System-Top-Group clock and reset generator dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs dt-bindings: soc: starfive: Add StarFive syscon module dt-bindings: clock: Add StarFive JH7110 PLL clock generator * clk-rm: dt-bindings: clk: oxnas: remove obsolete bindings clk: oxnas: remove obsolete clock driver * clk-renesas: clk: renesas: rcar-gen3: Add ADG clocks clk: renesas: r8a77965: Add 3DGE and ZG support clk: renesas: r8a7796: Add 3DGE and ZG support clk: renesas: r8a7795: Add 3DGE and ZG support clk: renesas: emev2: Remove obsolete clkdev registration clk: renesas: r9a07g043: Add MTU3a clock and reset entry clk: renesas: rzg2l: Simplify .determine_rate() clk: renesas: r9a09g011: Add CSI related clocks clk: renesas: r8a774b1: Add 3DGE and ZG support clk: renesas: r8a774e1: Add 3DGE and ZG support clk: renesas: r8a774a1: Add 3DGE and ZG support clk: renesas: rcar-gen3: Add support for ZG clock * clk-cleanup: clk: mvebu: Convert to devm_platform_ioremap_resource() clk: nuvoton: Convert to devm_platform_ioremap_resource() clk: socfpga: agilex: Convert to devm_platform_ioremap_resource() clk: ti: Use devm_platform_get_and_ioremap_resource() clk: mediatek: Convert to devm_platform_ioremap_resource() clk: hsdk-pll: Convert to devm_platform_ioremap_resource() clk: gemini: Convert to devm_platform_ioremap_resource() clk: fsl-sai: Convert to devm_platform_ioremap_resource() clk: bm1880: Convert to devm_platform_ioremap_resource() clk: axm5516: Convert to devm_platform_ioremap_resource() clk: actions: Convert to devm_platform_ioremap_resource() clk: cdce925: Remove redundant of_match_ptr() drivers: clk: keystone: Fix parameter judgment in _of_pll_clk_init() clk: Explicitly include correct DT includes
2023-08-23dt-bindings: use capital "OR" for multiple licenses in SPDXKrzysztof Kozlowski10-10/+10
Documentation/process/license-rules.rst and checkpatch expect the SPDX identifier syntax for multiple licenses to use capital "OR". Correct it to keep consistent format and avoid copy-paste issues. Correct also the format // -> .* in few Allwinner binding headers as pointed out by checkpatch: WARNING: Improper SPDX comment style for 'include/dt-bindings/reset/sun50i-h6-ccu.h', please use '/*' instead Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Guenter Roeck <[email protected]> Acked-by: Stephen Boyd <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Rob Herring <[email protected]>
2023-08-22clk: pxa910: Move number of clocks to driver sourceDuje Mihanović1-1/+0
The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Conor Dooley <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-08-22clk: pxa1928: Move number of clocks to driver sourceDuje Mihanović1-3/+0
The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Conor Dooley <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-08-22clk: pxa168: Move number of clocks to driver sourceDuje Mihanović1-1/+0
The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Conor Dooley <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-08-22clk: mmp2: Move number of clocks to driver sourceDuje Mihanović2-2/+0
The number of clocks should not be in the dt binding as it is not used by the respective device tree and thus needlessly bloats the ABI. Move this number of clocks into the driver source. Signed-off-by: Duje Mihanović <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Conor Dooley <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-08-21Merge tag 'socfpga_dts_updates_for_v6.6' of ↵Arnd Bergmann1-0/+100
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt SoCFPGA DTS updates for v6.6 - Fix dtbs_check warnings for usbphy, sram, rstmgr, memory, partitions - Updated "stmmaceth-ocp" reset-names to "ahb" for stmmac ethernet - Add initial support for Agilex5 * tag 'socfpga_dts_updates_for_v6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA dt-bindings: clock: add Intel Agilex5 clock manager dt-bindings: reset: add reset IDs for Agilex5 dt-bindings: intel: Add Intel Agilex5 compatible arm64: dts: socfpga: change the reset-name of "stmmaceth-ocp" to "ahb" arm64: dts: socfpga: n5x/stratix10: fix dtbs_check warning for partitions arm64: dts: agilex/stratix10: Updated QSPI Flash layout for UBIFS arm64: dts: agilex/stratix10/n5x: fix dtbs_check for rstmgr arm64: dts: stratix10/agilex/n5x: fix dtbs_check warning for memory node arm64: dts: socfpga: stratix10: fix dtbs_check warning for usbphy arm64: dts: socfpga: agilex/stratix10: fix dtbs_check warnings for sram Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2023-08-21Merge tag 'qcom-arm64-for-6.6' of ↵Arnd Bergmann4-0/+198
https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt Qualcomm ARM64 DeviceTree updates for v6.6 Initial support for the SM4450 platform and the QRD device thereon is added. The IPQ5018 platform is introduced, and the RDP432-C2 board thereon. A shared definition of the IPQ5332 RDP is introduced, as is GPIO-based LEDs and buttons. On the IPQ9574 RDP433 USB, CPU cooling maps and regulators are added. On MSM8916, the D3 camera mezzanine is improved and refactored out to its own dts. The Samsung Galaxy S4 Mini gains support for its PMIC with charger, while Samsung Galaxy J5 and E5 gains touchscreen support. A few fixes for MSM8939 are introduced, and initial support for Samsung Galaxy A7 is add. Support for scaling the cache bus fabric is introduced on MSM8996. A missing interrupt for the USB2 controller is added. The touchscreen vio supply on Xiaomi Mi 5 is corrected, and a few other cleanups are introduces across other devices. The display controller is introduced for MSM8998, a few clock fixes are introduced and missing power domains are added for the multimedia subsystem iommu. Reserved memory-regions and reserved GPIO lists are updated for the QDU/QRU1000 IDPs. USB3 PHY is added to the QCM2290, the RB1 gains regulators and GPU is enabled for the RB2. PCIe and Ethernet support is introduced on SA8775P, and enabled for the Ride board. On SC7180 the PSCI integration is refactored, to allow supporting devices with the Qualcomm firmware. BWMON is introduced, alongside the CPUfreq-based bus voting. A number of fixes are added for SC8180X, on the Primus and Lenovo Flex 5G devices pmic_glink is introduced and wired up, to provide support for external display. Missing SCM interconnect is added to SC8280XP, and the PDC is marked as wakeup-parent of TLMM. On the CRD the gpio for vreg_misc_3p3 is corrected and a few regulators are renamed to align with schematics. The Lenovo Thinkpad X13s gains camera activity LED and a set of previously reserved GPIOs are released. The SA8540P Ride platform gains RTC support. For SDM670 CPU and L3 frequency scaling is added, the PDC is introduced and wired up as wakeup-parent of the TLMM. On SDM845 the UFS controller gains interconnect path description, power-domain information is added to GCC and minimum frequency of the UFS ICE is corrected. On RB3 continuous splash memory region is described, and the camera subsystem is enabled. On the Lenovo Yoga C630 a missing power supply for the display panel is added, and the debug UART is introduced. SDX75 RPMh power-domains and SPMI controller are introduces, the PMX75 PMIC is described and added to the IDP. GPU description is added to SM6115, and together with display enabled on the Lenovo Tab P11. On SM635 BWMON is introduced for LLCC and DDR scaling. Display and GPU is added, and the PDC is registered as wakeup-parent of TLMM. L3 cache scaling is introduced on SM6375. The DSI PHY compatible and an interrupt for I2C7 are corrected for SM8150, on the Sony Xperia 1 and 5 the ramoops pmsg size is corrected. On SM8250 BWMONs are introduced for DDR and LLCC scaling, the UFS node gains interconnect paths, SMMU is marked as DMA coherent and dynamic power coefficients are updated. On Sony Xperia 1 II and 5 II GPIO line names are updated. On SM8350 missing cluster sleep states and LMH interrupts are added, the CPU compatibles are corrected and APR and LPASS pinctrl support is introduced. The HDK gains uSD card support and PMK8350 is added. For SM8450 support for RNG and RPMh stats are added, the ICE handling is extracted from the UFS node and the display subsystem gains a missing interconnect path. Thermal description is improved for the HDK. On SM8550 MTP and QRD the pmic_glink is introduced, to provide DisplayPort output. A missing regulator supply is also added. A few platforms that happens to share the RPMH power-domain resource identifier constants are migrated to new generic defines. ADC channel names are generalized on various PMICs. A variety of devices gain chassis-type, and the GIC_SPI constant is replacing the 0 across a few different platforms. * tag 'qcom-arm64-for-6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (215 commits) arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM arm64: dts: qcom: sdm670: Add PDC arm64: dts: qcom: msm8916-samsung-e5: Add touchscreen arm64: dts: qcom: sc7180: Split up TF-A related PSCI configuration arm64: dts: qcom: sc8280xp-x13s: Add camera activity LED arm64: dts: qcom: sc8280xp-x13s: Unreserve NC pins arm64: dts: qcom: msm8998: Add DPU1 nodes arm64: dts: qcom: msm8996: Fix dsi1 interrupts arm64: dts: qcom: sdx75-idp: Add regulator nodes arm64: dts: qcom: sdx75: Add rpmhpd node arm64: dts: qcom: sdx75-idp: Add pmics supported in SDX75 arm64: dts: qcom: Add pmx75 PMIC dtsi arm64: dts: qcom: Add pm7550ba PMIC dtsi arm64: dts: qcom: Add pinctrl gpio support for pm7250b arm64: dts: qcom: sdx75: Add spmi node arm64: dts: qcom: msm8998: Add missing power domain to MMSS SMMU ... Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2023-08-15dt-bindings: clock: qcom: ipq4019: add missing networking resetsRobert Marko1-0/+6
Add bindings for the missing networking resets found in IPQ4019 GCC. Signed-off-by: Robert Marko <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-15dt-bindings: clock: samsung: remove define with number of clocksKrzysztof Kozlowski10-130/+0
Number of clocks supported by Linux drivers might vary - sometimes we add new clocks, not exposed previously. Therefore these numbers of clocks should not be in the bindings, as that prevents changing them. Remove it entirely from the bindings, once Linux drivers stopped using them. Reviewed-by: Conor Dooley <[email protected]> Reviewed-by: Sam Protsenko <[email protected]> Reviewed-by: Alim Akhtar <[email protected]> Reviewed-by: Chanwoo Choi <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]>
2023-08-14dt-bindings: clocks: imx8mp: make sai4 a dummy clockMarco Felsch1-1/+1
The hardware don't have a SAI4 instance so remove the define. Use a comment to keep it as reference and to avoid confusion. Fixes: 108869144739 ("dt-bindings: imx: Add clock binding doc for i.MX8MP") Acked-by: Stephen Boyd <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Marco Felsch <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-08-14dt-bindings: clock: fsl,imx8-acm: Add audio clock mux supportShengjiu Wang1-0/+28
Add the clock dt-binding file for Audio Clock Mux. which is the IP for i.MX8QM, i.MX8QXP, i.MX8DXL. Add the clockid for clocks in header file. The Audio Clock Mux is binded with all the audio IP and audio clocks in the subsystem, so need to list the power domain of related clocks and IPs. Each clock and IP has a power domain, so there are so many power domains. Signed-off-by: Shengjiu Wang <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-08-13dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRCOtto Pflüger1-0/+1
Add the missing #define for GPLL0_SLEEP_CLK_SRC, the parent clock of GPLL0_EARLY. Signed-off-by: Otto Pflüger <[email protected]> Acked-by: Conor Dooley <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCsImran Shaik1-1/+3
Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock bindings for QDU1000 and QRU1000 SoCs. While at it, update the maintainers list. Signed-off-by: Imran Shaik <[email protected]> Acked-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-13Merge branch '[email protected]' into ↵Bjorn Andersson1-0/+3
arm64-for-6.6 Merge additional MSM8998 GCC DeviceTree binding constants for use in the MSM8998 DeviceTree source.
2023-08-13Merge branch '[email protected]' into ↵Bjorn Andersson1-0/+3
clk-for-6.6 Merge additional MSM8998 GCC DeviceTree binding constants through a topic branch to make them available to the DeviceTree source tree as well.
2023-08-13dt-bindings: clk: qcom,gcc-msm8998: Add missing GPU/MMSS GPLL0 legsKonrad Dybcio1-0/+3
GPLL0 has two separate outputs to both GPUSS and MMSS: one that's 2-divided and one that runs at the same rate as the GPLL0 itself. Add the missing ones to the binding. Acked-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Jeffrey Hugo <[email protected]> Signed-off-by: Konrad Dybcio <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-11Merge branch '[email protected]' ↵Bjorn Andersson1-0/+183
into arm64-for-6.6 Merge the IPQ5018 GCC Devicetree binding through a topic branch, in order to the the clock defines.
2023-08-11Merge branch '[email protected]' ↵Bjorn Andersson1-0/+183
into clk-for-6.6 Merge the IPQ5018 GCC Devicetree binding through a topic branch, in order to the the clock defines.
2023-08-11dt-bindings: clock: Add IPQ5018 clock and resetSricharan Ramabadhran1-0/+183
This patch adds support for the global clock controller found on the IPQ5018 based devices. Reviewed-by: Krzysztof Kozlowski <[email protected]> Co-developed-by: Varadarajan Narayanan <[email protected]> Signed-off-by: Varadarajan Narayanan <[email protected]> Signed-off-by: Sricharan Ramabadhran <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-08-08dt-bindings: clk: axg-audio-clkc: expose all clock idsNeil Armstrong1-0/+65
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every axg-audio-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-14-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: amlogic,a1-pll-clkc: expose all clock idsNeil Armstrong1-0/+5
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 pll ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Reviewed-by: Dmitry Rokosov <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-13-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: amlogic,a1-peripherals-clkc: expose all clock idsNeil Armstrong1-0/+53
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every A1 peripherals ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Reviewed-by: Dmitry Rokosov <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-12-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: meson8b-clkc: expose all clock idsNeil Armstrong1-0/+97
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every meson8b-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-11-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: g12a-aoclkc: expose all clock idsNeil Armstrong1-0/+7
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every g12a-aoclkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-10-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: g12a-clks: expose all clock idsNeil Armstrong1-0/+130
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every g12a-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-9-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: axg-clkc: expose all clock idsNeil Armstrong1-0/+48
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every axg-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-8-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clk: gxbb-clkc: expose all clock idsNeil Armstrong1-0/+65
Due to a policy change in clock ID bindings handling, expose all the "private" clock IDs to the public clock dt-bindings to move out of the previous maintenance scheme. This refers to a discussion at [1] & [2] with Krzysztof about the issue with the current maintenance. It was decided to move every gxbb-clkc ID to the public clock dt-bindings headers to be merged in a single tree so we can safely add new clocks without having merge issues. [1] https://lore.kernel.org/all/[email protected]/ [2] https://lore.kernel.org/all/[email protected]/ Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-7-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <[email protected]>
2023-08-08dt-bindings: clock: add Intel Agilex5 clock managerNiravkumar L Rabara1-0/+100
Add clock ID definitions for Intel Agilex5 SoCFPGA. The registers in Agilex5 handling the clock is named as clock manager. Signed-off-by: Teh Wen Ping <[email protected]> Reviewed-by: Dinh Nguyen <[email protected]> Reviewed-by: Conor Dooley <[email protected]> Signed-off-by: Niravkumar L Rabara <[email protected]> Signed-off-by: Dinh Nguyen <[email protected]>
2023-07-31dt-bindings: clock: drop qcom,lcc-mdm9615 header fileDmitry Baryshkov1-44/+0
The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same (as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of qcom,lcc-msm8960.h Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Bjorn Andersson <[email protected]>
2023-07-25dt-bindings: clock: imx93: Add PDM IPG clkChancel Liu1-1/+2
Add PDM IPG clk. Reviewed-by: Shengjiu Wang <[email protected]> Signed-off-by: Chancel Liu <[email protected]> Signed-off-by: Jacky Bai <[email protected]> Reviewed-by: Peng Fan <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Abel Vesa <[email protected]>
2023-07-19dt-bindings: clock: ast2600: Add I3C and MAC reset definitionsDylan Hung1-0/+12
Add reset definitions of AST2600 I3C and MAC controllers. In the case of the I3C reset, since there is no reset-line hardware available for `ASPEED_RESET_I3C_DMA`, a new macro `ASPEED_RESET_I3C` with the same ID is introduced to provide a more accurate representation of the hardware. The old macro `ASPEED_RESET_I3C_DMA` is kept to provide backward compatibility. Signed-off-by: Dylan Hung <[email protected]> Link: https://lore.kernel.org/r/[email protected] Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2023-07-19dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generatorXingyu Wu1-0/+22
Add bindings for the Video-Output clock and reset generator (VOUTCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by: Palmer Dabbelt <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Xingyu Wu <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
2023-07-19dt-bindings: clock: Add StarFive JH7110 Image-Signal-Process clock and reset ↵Xingyu Wu1-0/+18
generator Add bindings for the Image-Signal-Process clock and reset generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by: Palmer Dabbelt <[email protected]> Reviewed-by: Emil Renner Berthing <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Xingyu Wu <[email protected]> Signed-off-by: Conor Dooley <[email protected]>
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