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2018-10-16clk: qcom: Add Global Clock controller (GCC) driver for SDM660Taniya Das1-0/+156
Add support for the global clock controller found on SDM660 based devices. This should allow most non-multimedia device drivers to probe and control their clocks. Based on CAF implementation. Signed-off-by: Taniya Das <[email protected]> [craig: rename parents to fit upstream, and other cleanups] Signed-off-by: Craig Tatlor <[email protected]> Acked-by: Rob Herring <[email protected]> [[email protected]: Rename gcc_660 to gcc_sdm660 and fix numbering of defines to avoid duplicates] Signed-off-by: Stephen Boyd <[email protected]>
2018-10-16dt-bindings: clk: hisilicon: Add bindings for Hi3670 clkManivannan Sadhasivam1-0/+348
Add devicetree bindings for HiSilicon Hi3670 clock controller. Signed-off-by: Manivannan Sadhasivam <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-10-15dt-bindings: clock: samsung: Add SPDX license identifiersKrzysztof Kozlowski11-50/+17
Replace GPL license statements with SPDX license identifiers (GPL-2.0). Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Rob Herring <[email protected]>
2018-10-11clk: rockchip: add clock-id for HCLK_HDMI on rk3066Heiko Stuebner1-1/+2
RK3066 and RK3188 share most of the clock controller but the rk3066 does have an internal hdmi encoder and associated clock. Therefore add a clock-id so that this clock can be used. Signed-off-by: Heiko Stuebner <[email protected]>
2018-10-09dt-bindings: clock: Add bindings for ZynqMP clock driverRajan Vaja1-0/+116
Add documentation to describe Xilinx ZynqMP clock driver bindings. Signed-off-by: Rajan Vaja <[email protected]> Signed-off-by: Jolly Shah <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Michal Simek <[email protected]>
2018-10-05dt-bindings: clock: samsung: Add SPDX license identifiersKrzysztof Kozlowski11-50/+17
Replace GPL license statements with SPDX license identifiers (GPL-2.0). Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-05clk: samsung: Remove obsolete code for Exynos4412 ISP clocksMarek Szyprowski1-30/+0
Exynos4412 ISP clock are provided by separate Exynos4412 ISP clock driver, so support for them in Exynos4-clk driver can be removed. Signed-off-by: Marek Szyprowski <[email protected]> Acked-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Sylwester Nawrocki <[email protected]>
2018-10-03dt-bindings: clock: dra7xx: add clkctrl indices for new data layoutTero Kristo1-68/+258
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03dt-bindings: clock: am43xx: add clkctrl indices for new data layoutTero Kristo1-0/+132
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-10-03dt-bindings: clock: am33xx: add clkctrl indices for new data layoutTero Kristo1-0/+119
The new data layout will be split based on clockdomain boundaries, instead of CM boundaries. This introduces a few new clkctrl providers, that have different indices for the clkctrl data. Signed-off-by: Tero Kristo <[email protected]> Tested-by: Tony Lindgren <[email protected]>
2018-09-19clk: renesas: Add r8a774c0 CPG Core Clock DefinitionsFabrizio Castro1-0/+60
Add all RZ/G2E (a.k.a. R8A774C0) Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2g ("List of Clocks [RZ/G2E]") of the RZ/G2 Hardware User's Manual. Signed-off-by: Fabrizio Castro <[email protected]> Reviewed-by: Biju Das <[email protected]> Reviewed-by: Simon Horman <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-19clk: renesas: Add r8a7744 CPG Core Clock DefinitionsBiju Das1-0/+39
Add all RZ/G1N Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2b ("List of Clocks [RZ/G1M/N]") of the RZ/G1 Hardware User's Manual. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Fabrizio Castro <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-19dt-bindings: clock: renesas: Convert to SPDX identifiersKuninori Morimoto15-93/+30
This patch updates license to use SPDX-License-Identifier instead of verbose license text on Renesas related headers. Signed-off-by: Kuninori Morimoto <[email protected]> Reviewed-by: Simon Horman <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-11clk: renesas: cpg-mssr: Add R7S9210 supportChris Brandt1-0/+20
Add support for the R7S9210 (RZ/A2) Clock Pulse Generator and Module Standby. The Module Standby HW in the RZ/A series is very close to R-Car HW, except for how the registers are laid out. The MSTP registers are only 8-bits wide, there are no status registers (MSTPSR), and the register offsets are a little different. Since the RZ/A hardware manuals refer to these registers as the Standby Control Registers, we'll use that name to distinguish the RZ/A type from the R-Car type. Signed-off-by: Chris Brandt <[email protected]> Acked-by: Rob Herring <[email protected]> # DT bits Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-09-05dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macroJagan Teki1-0/+1
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent. Include the macro on dt-bindings so-that the same can be used while defining CCU clock phandles. Signed-off-by: Jagan Teki <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Icenowy Zheng <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2018-08-30dt-bindings: clock: Introduce QCOM Camera clock bindingsAmit Nischal1-0/+116
Add device tree bindings for camera clock controller for Qualcomm Technology Inc's SDM845 SoCs. Signed-off-by: Amit Nischal <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-08-28clk: qcom: Add qspi (Quad SPI) clock defines for sdm845 to headerDouglas Anderson1-0/+3
These clocks will need to be defined in the clock driver and referenced in device tree files. Signed-off-by: Douglas Anderson <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Taniya Das <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-08-28clk: qcom: Add some missing gcc clks for msm8996Rajendra Nayak1-0/+9
Add a few missing gcc clks for msm8996 Signed-off-by: Rajendra Nayak <[email protected]> [bjorn: omit aggre0_noc_qosgen_extref_clk] Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-08-27clk: s2mps11,s3c64xx: Add SPDX license identifiersKrzysztof Kozlowski2-9/+3
Replace GPL v2.0 and v2.0+ license statements with SPDX license identifiers. Signed-off-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-08-27clk: max77686: Add SPDX license identifiersKrzysztof Kozlowski2-8/+2
Replace GPL v2.0 and v2.0+ license statements with SPDX license identifiers. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-08-27clk: renesas: Add r8a774a1 CPG Core Clock DefinitionsBiju Das1-0/+58
Add all RZ/G2M Clock Pulse Generator Core Clock Outputs, as listed in Table 8.2b ("List of Clocks [RZ/G2M]") of the RZ/G2M Hardware User's Manual. Signed-off-by: Biju Das <[email protected]> Reviewed-by: Fabrizio Castro <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
2018-08-23Merge tag 'armsoc-drivers' of ↵Linus Torvalds2-44/+1
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Some of the larger changes this merge window: - Removal of drivers for Exynos5440, a Samsung SoC that never saw widespread use. - Uniphier support for USB3 and SPI reset handling - Syste control and SRAM drivers and bindings for Allwinner platforms - Qualcomm AOSS (Always-on subsystem) reset controller drivers - Raspberry Pi hwmon driver for voltage - Mediatek pwrap (pmic) support for MT6797 SoC" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (52 commits) drivers/firmware: psci_checker: stash and use topology_core_cpumask for hotplug tests soc: fsl: cleanup Kconfig menu soc: fsl: dpio: Convert DPIO documentation to .rst staging: fsl-mc: Remove remaining files staging: fsl-mc: Move DPIO from staging to drivers/soc/fsl staging: fsl-dpaa2: eth: move generic FD defines to DPIO soc: fsl: qe: gpio: Add qe_gpio_set_multiple usb: host: exynos: Remove support for Exynos5440 clk: samsung: Remove support for Exynos5440 soc: sunxi: Add the A13, A23 and H3 system control compatibles reset: uniphier: add reset control support for SPI cpufreq: exynos: Remove support for Exynos5440 ata: ahci-platform: Remove support for Exynos5440 soc: imx6qp: Use GENPD_FLAG_ALWAYS_ON for PU errata soc: mediatek: pwrap: add mt6351 driver for mt6797 SoCs soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs soc: mediatek: pwrap: fix cipher init setting error dt-bindings: pwrap: mediatek: add pwrap support for MT6797 reset: uniphier: add USB3 core reset control dt-bindings: reset: uniphier: add USB3 core reset support ...
2018-08-15Merge tag 'clk-for-linus' of ↵Linus Torvalds14-4/+841
git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "The new and exciting feature this time around is in the clk core. We've added duty cycle support to the clk API so that clk signal duty cycle ratios can be adjusted while taking into account things like clk dividers and clk tree hierarchy. So far only one SoC has implemented support for this, but I expect there will be more to come in the future. Outside of the core, we have the usual pile of clk driver updates and additions. The Amlogic meson driver got the most lines in the diffstat this time around because it added support for a whole bunch of hardware and duty cycle configuration. After that the Rockchip PX30, Qualcomm SDM845, and Renesas SoC drivers fill in a majority of the diff. We're left with the collection of non-critical fixes after that. Overall it looks pretty quiet this time. Core: - Clk duty cycle support - Proper CLK_SET_RATE_GATE support throughout the tree New Drivers: - Actions Semi Owl series S700 SoC clk driver - Qualcomm SDM845 display clock controller - i.MX6SX ocram_s clk support - Uniphier NAND, USB3 PHY, and SPI clk support - Qualcomm RPMh clk driver - i.MX7D mailbox clk support - Maxim 9485 Programmable Clock Generator - expose 32 kHz PLL on PXA SoCs - imx6sll GPIO clk gate support - Atmel at91 I2S audio clk support - SI544/SI514 clk on/off support - i.MX6UL GPIO clock gates in CCM CCGR - Renesas Crypto Engine clocks on R-Car H3 - Renesas clk support for the new RZ/N1D SoC - Allwinner A64 display engine clock support - support for Rockchip's PX30 SoC - Amlogic Meson axg PCIe and audio clocks - Amlogic Meson GEN CLK on gxbb, gxl and axg Updates: - remove an unused variable from Exynos4412 ISP driver - fix a thinko bug in SCMI clk division logic - add missing of_node_put()s in some i.MX clk drivers - Tegra SDMMC clk jitter improvements with high speed signaling modes - SPDX tagging for qcom and cs2000-cp drivers - stop leaking con ids in __clk_put() - fix a corner case in fixed factor clk probing where node is in DT but parent clk is registered much later - Marvell Armada 3700 clk_pm_cpu_get_parent() had an invalid return value - i.MX clk init arrays removed in place of CLK_IS_CRITICAL - convert to CLK_IS_CRITICAL for i.MX51/53 driver - fix Tegra BPMP driver oops when xlating a NULL clk - proper default configuration for vic03 and vde clks on Tegra124 - mark Tegra memory controller clks as critical - fix array bounds clamp in Tegra's emc determine_rate() op - Ingenic i2s bit update and allow UDC clk to gate - fix name of aspeed SDC clk define to have only one 'CLK' - fix i.MX6QDL video clk parent - critical clk markings for qcom SDM845 - fix Stratix10 mpu_free_clk and sdmmc_free_clk parents - mark Rockchip's pclk_rkpwm_pmu as critical clock, due to it supplying the pwm used to drive the logic supply of the rk3399 core" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (85 commits) clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 clk: cs2000-cp: convert to SPDX identifiers clk: scmi: Fix the rounding of clock rate clk: qcom: Add display clock controller driver for SDM845 clk: mvebu: armada-37xx-periph: Remove unused var num_parents clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable clk: actions: Add S700 SoC clock support dt-bindings: clock: Add S700 support for Actions Semi Soc's clk: actions: Add missing REGMAP_MMIO dependency clk: uniphier: add clock frequency support for SPI clk: uniphier: add more USB3 PHY clocks clk: uniphier: add NAND 200MHz clock clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks clk: tegra: Add sdmmc mux divider clock clk: tegra: Refactor fractional divider calculation clk: tegra: Fix includes required by fence_udelay() clk: imx6sll: fix missing of_node_put() clk: imx6ul: fix missing of_node_put() clk: imx: add ocram_s clock for i.mx6sx clk: mvebu: armada-37xx-periph: Fix wrong return value in get_parent ...
2018-08-15Merge tag 'drm-next-2018-08-15' of git://anongit.freedesktop.org/drm/drmLinus Torvalds1-0/+11
Pull drm updates from Dave Airlie: "This is the main drm pull request for 4.19. Rob has some new hardware support for new qualcomm hw that I'll send along separately. This has the display part of it, the remaining pull is for the acceleration engine. This also contains a wound-wait/wait-die mutex rework, Peter has acked it for merging via my tree. Otherwise mostly the usual level of activity. Summary: core: - Wound-wait/wait-die mutex rework - Add writeback connector type - Add "content type" property for HDMI - Move GEM bo to drm_framebuffer - Initial gpu scheduler documentation - GPU scheduler fixes for dying processes - Console deferred fbcon takeover support - Displayport support for CEC tunneling over AUX panel: - otm8009a panel driver fixes - Innolux TV123WAM and G070Y2-L01 panel driver - Ilitek ILI9881c panel driver - Rocktech RK070ER9427 LCD - EDT ETM0700G0EDH6 and EDT ETM0700G0BDH6 - DLC DLC0700YZG-1 - BOE HV070WSA-100 - newhaven, nhd-4.3-480272ef-atxl LCD - DataImage SCF0700C48GGU18 - Sharp LQ035Q7DB03 - p079zca: Refactor to support multiple panels tinydrm: - ILI9341 display panel New driver: - vkms - virtual kms driver to testing. i915: - Icelake: Display enablement DSI support IRQ support Powerwell support - GPU reset fixes and improvements - Full ppgtt support refactoring - PSR fixes and improvements - Execlist improvments - GuC related fixes amdgpu: - Initial amdgpu documentation - JPEG engine support on VCN - CIK uses powerplay by default - Move to using core PCIE functionality for gens/lanes - DC/Powerplay interface rework - Stutter mode support for RV - Vega12 Powerplay updates - GFXOFF fixes - GPUVM fault debugging - Vega12 GFXOFF - DC improvements - DC i2c/aux changes - UVD 7.2 fixes - Powerplay fixes for Polaris12, CZ/ST - command submission bo_list fixes amdkfd: - Raven support - Power management fixes udl: - Cleanups and fixes nouveau: - misc fixes and cleanups. msm: - DPU1 support display controller in sdm845 - GPU coredump support. vmwgfx: - Atomic modesetting validation fixes - Support for multisample surfaces armada: - Atomic modesetting support completed. exynos: - IPPv2 fixes - Move g2d to component framework - Suspend/resume support cleanups - Driver cleanups imx: - CSI configuration improvements - Driver cleanups - Use atomic suspend/resume helpers - ipu-v3 V4L2 XRGB32/XBGR32 support pl111: - Add Nomadik LCDC variant v3d: - GPU scheduler jobs management sun4i: - R40 display engine support - TCON TOP driver mediatek: - MT2712 SoC support rockchip: - vop fixes omapdrm: - Workaround for DRA7 errata i932 - Fix mm_list locking mali-dp: - Writeback implementation PM improvements - Internal error reporting debugfs tilcdc: - Single fix for deferred probing hdlcd: - Teardown fixes tda998x: - Converted to a bridge driver. etnaviv: - Misc fixes" * tag 'drm-next-2018-08-15' of git://anongit.freedesktop.org/drm/drm: (1506 commits) drm/amdgpu/sriov: give 8s for recover vram under RUNTIME drm/scheduler: fix param documentation drm/i2c: tda998x: correct PLL divider calculation drm/i2c: tda998x: get rid of private fill_modes function drm/i2c: tda998x: move mode_valid() to bridge drm/i2c: tda998x: register bridge outside of component helper drm/i2c: tda998x: cleanup from previous changes drm/i2c: tda998x: allocate tda998x_priv inside tda998x_create() drm/i2c: tda998x: convert to bridge driver drm/scheduler: fix timeout worker setup for out of order job completions drm/amd/display: display connected to dp-1 does not light up drm/amd/display: update clk for various HDMI color depths drm/amd/display: program display clock on cache match drm/amd/display: Add NULL check for enabling dp ss drm/amd/display: add vbios table check for enabling dp ss drm/amd/display: Don't share clk source between DP and HDMI drm/amd/display: Fix DP HBR2 Eye Diagram Pattern on Carrizo drm/amd/display: Use calculated disp_clk_khz value for dce110 drm/amd/display: Implement custom degamma lut on dcn drm/amd/display: Destroy aux_engines only once ...
2018-08-14Merge branches 'clk-actions-s700', 'clk-exynos-unused', ↵Stephen Boyd2-0/+163
'clk-qcom-dispcc-845', 'clk-scmi-round' and 'clk-cs2000-spdx' into clk-next * clk-actions-s700: : - Actions Semi Owl series S700 SoC clk driver clk: actions: Add S700 SoC clock support dt-bindings: clock: Add S700 support for Actions Semi Soc's clk: actions: Add missing REGMAP_MMIO dependency * clk-exynos-unused: : - Remove an unused variable from Exynos4412 ISP driver clk: samsung: Remove unused mout_user_aclk400_mcuisp_p4x12 variable * clk-qcom-dispcc-845: : - Qualcomm SDM845 display clock controller clk: qcom: Add display clock controller driver for SDM845 dt-bindings: clock: Introduce QCOM Display clock bindings clk: qcom: Move frequency table macro to common file * clk-scmi-round: : - Fix a thinko bug in SCMI clk division logic clk: scmi: Fix the rounding of clock rate * clk-cs2000-spdx: clk: cs2000-cp: convert to SPDX identifiers
2018-08-14Merge branches 'clk-imx6-ocram', 'clk-missing-put', ↵Stephen Boyd1-0/+4
'clk-tegra-sdmmc-jitter', 'clk-allwinner' and 'clk-uniphier' into clk-next * clk-imx6-ocram: : - i.MX6SX ocram_s clk support clk: imx: add ocram_s clock for i.mx6sx * clk-missing-put: : - Add missing of_node_put()s in some i.MX clk drivers clk: imx6sll: fix missing of_node_put() clk: imx6ul: fix missing of_node_put() * clk-tegra-sdmmc-jitter: : - Tegra SDMMC clk jitter improvements with high speed signaling modes clk: tegra: make sdmmc2 and sdmmc4 as sdmmc clocks clk: tegra: Add sdmmc mux divider clock clk: tegra: Refactor fractional divider calculation clk: tegra: Fix includes required by fence_udelay() * clk-allwinner: clk: sunxi-ng: add A64 compatible string dt-bindings: add compatible string for the A64 DE2 CCU clk: sunxi-ng: r40: Export video PLLs clk: sunxi-ng: r40: Allow setting parent rate to display related clocks clk: sunxi-ng: r40: Add minimal rate for video PLLs * clk-uniphier: : - Uniphier NAND, USB3 PHY, and SPI clk support clk: uniphier: add clock frequency support for SPI clk: uniphier: add more USB3 PHY clocks clk: uniphier: add NAND 200MHz clock
2018-08-14Merge branches 'clk-mvebu-spdx', 'clk-meson', 'clk-imx7d-mu', ↵Stephen Boyd4-0/+488
'clk-imx-init-array-cleanup' and 'clk-rockchip' into clk-next * clk-mvebu-spdx: clk: mvebu: armada-37xx-periph: switch to SPDX license identifier * clk-meson: clk: meson: add gen_clk clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition clk: meson-axg: add clocks required by pcie driver clk: meson: remove unused clk-audio-divider driver clk: meson: stop rate propagation for audio clocks clk: meson: axg: add the audio clock controller driver clk: meson: add axg audio sclk divider driver clk: meson: add triple phase clock driver clk: meson: add clk-phase clock driver clk: meson: clean-up meson clock configuration clk: meson: remove obsolete register access clk: meson: expose GEN_CLK clkid clk: meson-axg: add pcie and mipi clock bindings dt-bindings: clock: add meson axg audio clock controller bindings clk: meson: audio-divider is one based clk: meson-gxbb: set fclk_div2 as CLK_IS_CRITICAL * clk-imx7d-mu: : - i.MX7D mailbox clk support clk: imx7d: add IMX7D_MU_ROOT_CLK * clk-imx-init-array-cleanup: : - i.MX clk init arrays removed in place of CLK_IS_CRITICAL clk: imx6sx: remove clks_init_on array clk: imx6sl: remove clks_init_on array clk: imx6q: remove clks_init_on array * clk-rockchip: clk: rockchip: Add pclk_rkpwm_pmu to PMU critical clocks in rk3399 clk: rockchip: fix clk_i2sout parent selection bits on rk3399 clk: rockchip: add clock controller for px30 clk: rockchip: add support for half divider dt-bindings: add bindings for px30 clock controller clk: rockchip: add dt-binding header for px30
2018-08-14Merge branches 'clk-ingenic-fixes', 'clk-max9485', 'clk-pxa-32k-pll', ↵Stephen Boyd4-3/+29
'clk-aspeed' and 'clk-imx6sll-gpio' into clk-next * clk-ingenic-fixes: : - Ingenic i2s bit update and allow UDC clk to gate clk: ingenic: Add missing flag for UDC clock clk: ingenic: Fix incorrect data for the i2s clock * clk-max9485: : - Maxim 9485 Programmable Clock Generator clk: Add driver for MAX9485 dts: clk: add devicetree bindings for MAX9485 * clk-pxa-32k-pll: : - Expose 32 kHz PLL on PXA SoCs clk: pxa: export 32kHz PLL * clk-aspeed: : - Fix name of aspeed SDC clk define to have only one 'CLK' clk: aspeed: Fix SDCLK name * clk-imx6sll-gpio: : - imx6sll GPIO clk gate support clk: imx6sll: add GPIO LPCGs
2018-08-14Merge branches 'clk-imx6-video-parent', 'clk-qcom-sdm845-criticals', ↵Stephen Boyd2-0/+150
'clk-renesas', 'clk-stratix10-fixes' and 'clk-atmel-i2s' into clk-next * clk-imx6-video-parent: : - Fix i.MX6QDL video clk parent clk: imx6: fix video_27m parent for IMX6QDL_CLK_CKO1_SEL * clk-qcom-sdm845-criticals: : - critical clk markings for qcom SDM845 clk: qcom: Enable clocks which needs to be always on for SDM845 * clk-renesas: clk: renesas: Renesas R9A06G032 clock driver dt-bindings: clock: renesas,r9a06g032-sysctrl: documentation dt-bindings: clock: Add the r9a06g032-sysctrl.h file clk: renesas: r8a7795: Add CCREE clock clk: renesas: r8a7795: Add CR clock * clk-stratix10-fixes: : - Fix Stratix10 mpu_free_clk and sdmmc_free_clk parents clk: socfpga: stratix10: fix the sdmmc_free_clk mux clk: socfpga: stratix10: fix the parents of mpu_free_clk * clk-atmel-i2s: : - Atmel at91 I2S audio clk support clk: at91: add I2S clock mux driver dt-bindings: clk: at91: add an I2S mux clock
2018-07-30BackMerge v4.18-rc7 into drm-nextDave Airlie1-21/+19
rmk requested this for armada and I think we've had a few conflicts build up. Signed-off-by: Dave Airlie <[email protected]>
2018-07-26Merge tag 'samsung-drivers-exynos5440-4.19' of ↵Olof Johansson1-44/+0
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/drivers Exynos5440 drivers removal The Exynos5440 (quad-core A15 with GMAC, PCIe, SATA) was targeting server platforms but it did not make it to the market really. There are no development boards with it and probably there are no real products neither. The development for Exynos5440 ended in 2013 and since then the platform is in maintenance mode. Removing Exynos5440 makes our life slightly easier: less maintenance, smaller code, reduced number of quirks, no need to preserve DTB backward-compatibility. The Device Tree sources and some of the drivers for Exynos5440 were already removed. This removes remaining drivers. * tag 'samsung-drivers-exynos5440-4.19' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: usb: host: exynos: Remove support for Exynos5440 clk: samsung: Remove support for Exynos5440 cpufreq: exynos: Remove support for Exynos5440 ata: ahci-platform: Remove support for Exynos5440 Signed-off-by: Olof Johansson <[email protected]>
2018-07-25dt-bindings: clock: Add S700 support for Actions Semi Soc'sSaravanan Sekar1-0/+118
Add clock bindings constants for action S700 Maintain common clock dt-bindings for Actions Semi SoC's S700 and S900. Signed-off-by: Parthiban Nallathambi <[email protected]> Signed-off-by: Saravanan Sekar <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-24clk: samsung: Remove support for Exynos5440Krzysztof Kozlowski1-44/+0
The Exynos5440 is not actively developed, there are no development boards available and probably there are no real products with it. Remove wide-tree support for Exynos5440. Signed-off-by: Krzysztof Kozlowski <[email protected]> Acked-by: Chanwoo Choi <[email protected]> Acked-by: Stephen Boyd <[email protected]> Acked-by: Sylwester Nawrocki <[email protected]>
2018-07-18dt-bindings: clock: add rk3399 DDR3 standard speed bins.Enric Balletbo i Serra1-0/+56
DDR3 SDRAM Standard (JESD79-3F) defines some standard speed bins for DDR3 memories. The rk3399_dmc driver allows you to pass these values via the device tree. For that purpose the devfreq/rk3399_dmc.txt binding refers to a ddr.h file which does not exist. This patch adds the missing defines in a include file called rk3399-ddr.h with the definition of standard speed bins according to the ARM Trusted Firmware (ATF). Fixes: c1ceb8f7c167 (Documentation: bindings: add dt documentation for rk3399 dmc) Signed-off-by: Enric Balletbo i Serra <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: MyungJoo Ham <[email protected]>
2018-07-09clk: ti: dra7: Add clkctrl clock data for the mcan clocksFaiz Abbas1-0/+1
Add clkctrl data for the m_can clocks and register it within the clkctrl driver Acked-by: Rob Herring <[email protected]> Acked-by: Stephen Boyd <[email protected]> CC: Tero Kristo <[email protected]> Signed-off-by: Faiz Abbas <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
2018-07-09clk: meson: expose GEN_CLK clkidJerome Brunet2-0/+2
Expose GEN_CLK clock id Signed-off-by: Jerome Brunet <[email protected]>
2018-07-06dt-bindings: clock: Introduce QCOM Display clock bindingsTaniya Das1-0/+45
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SDM845 SoCs. Signed-off-by: Taniya Das <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06clk: imx6sll: add GPIO LPCGsAnson Huang1-1/+8
According to Reference Manual Rev.0, 06/2017, there are GPIO LPCGs defined in CCM CCGRs, add them into clock tree. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06clk: aspeed: Fix SDCLK nameLei YU1-1/+1
The SDCLK was named SDCLKCLK, and no one has used this yet. Fix it. Signed-off-by: Lei YU <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06clk: pxa: export 32kHz PLLRobert Jarzmik1-1/+2
This clock is especially used by the RTC driver, so export it so that devicetree users can use it. Signed-off-by: Robert Jarzmik <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-06dts: clk: add devicetree bindings for MAX9485Daniel Mack1-0/+18
This patch adds the devicetree bindings for MAX9485, a programmable audio clock generator. Signed-off-by: Daniel Mack <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-03clk: rockchip: add dt-binding header for px30Elaine Zhang1-0/+389
Add the dt-bindings header for the px30, that gets shared between the clock controller and the clock references in the dts. Add softreset ID for px30. Signed-off-by: Elaine Zhang <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
2018-07-03clk: qcom: Enable clocks which needs to be always on for SDM845Amit Nischal1-0/+2
There are certain clocks which needs to be always enabled for system operation. Add support for the same by adding 'CLK_IS_CRITICAL' flag for such clocks. Signed-off-by: Amit Nischal <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-07-03clk: meson-axg: add pcie and mipi clock bindingsYixun Lan1-0/+3
Add the pcie and mipi clock dt-bindings for the pcie driver. Since the mipi clock isalso used by the pcie driver, we add it together in this patch. Tested-by: Jianxin Qin <[email protected]> Signed-off-by: Yixun Lan <[email protected]> Signed-off-by: Jerome Brunet <[email protected]>
2018-06-29clk: imx6ul: add GPIO clock gatesAnson Huang1-1/+7
i.MX6UL has GPIO clock gates in CCM CCGR, add them into clock tree for clock management. Signed-off-by: Anson Huang <[email protected]> Reviewed-by: Fabio Estevam <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-06-29dt-bindings: clock: imx6ul: Do not change the clock definition orderFabio Estevam1-21/+19
Commit f5a4670de966 ("clk: imx: Add new clo01 and clo2 controlled by CCOSR") introduced the CLK_CLKO definitions, but didn't put them at the end of the list, which may cause dtb breakage when running an old dtb with a newer kernel. In order to avoid that, simply add the new CLK_CKO clock definitions at the end of the list. Fixes: f5a4670de966 ("clk: imx: Add new clo01 and clo2 controlled by CCOSR") Reported-by: Stefan Wahren <[email protected]> Signed-off-by: Fabio Estevam <[email protected]> Acked-by: Rob Herring <[email protected]> Reviewed-by: Stefan Agner <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
2018-06-28Merge tag 'drm-misc-next-2018-06-27' of ↵Dave Airlie1-0/+11
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 4.19: Cross-subsystem Changes: devicetree documentation dt-bindings defintions for sun8i (Jernej Skrabec) Core Changes: Consider drivers setting DRIVER_ATOMIC as atomic (Eric Anholt) Improvements for in-kernel clients (Noralf Trønnes) Export and rename drm_crtc_port_mask() (Jernej Skrabec) Driver Changes: v3d: Add looking for GPU scheduler jobs management (Eric Anholt) Add Ilitek ILI9881c panel driver(Maxime Ripard) rockchip: vop: fixup linebuffer mode calc error (Sandy Huang) tinydrm: new driver for ILI9341 display panels (David Lechner) sun4i: Add TCON TOP driver (Jernej Skrabec) Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20180628010018.GA10929@juma
2018-06-27dt-bindings: display: sunxi-drm: Add TCON TOP descriptionJernej Skrabec1-0/+11
TCON TOP main purpose is to configure whole display pipeline. It determines relationships between mixers and TCONs, selects source TCON for HDMI, muxes LCD and TV encoder GPIO output, selects TV encoder clock source and contains additional TV TCON and DSI gates. Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-06-27clk: sunxi-ng: r40: Export video PLLsJernej Skrabec1-0/+4
Video PLLs need to be referenced in R40 DT as possible HDMI PHY parent. Export them. Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Signed-off-by: Jernej Skrabec <[email protected]> Signed-off-by: Maxime Ripard <[email protected]>
2018-06-22dt-bindings: clock: Add the r9a06g032-sysctrl.h fileMichel Pollet1-0/+148
This adds the constants necessary to use the renesas,r9a06g032-sysctrl node. Signed-off-by: Michel Pollet <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]>
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