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1.The SSI clock of X1000 not like JZ4770 and JZ4780, they are not
directly derived from the output of SSIPLL, but from the clock
obtained by dividing the frequency by 2. "X1000_CLK_SSIPLL_DIV2"
is added for this purpose, it must between "X1000_CLK_SSIPLL"
and "X1000_CLK_SSIMUX", otherwise an error will occurs when
initializing the clock. These ABIs are only used for X1000, and
I'm sure that no other devicetree out there is using these ABIs,
so we should be able to reorder them.
2.Clocks of LCD, OTG, EMC, EFUSE, OST, TCU are also added.
Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add the clock bindings for the X1830 Soc from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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This describes the bindings for a controller that generates master and bit
clocks for the I2S interface.
Signed-off-by: Lubomir Rintel <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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This clocks the Audio block.
Signed-off-by: Lubomir Rintel <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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There are two of these on a MMP2.
Signed-off-by: Lubomir Rintel <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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mipi_csi_xx clocks are used by camera sensors.
Signed-off-by: Chunyan Zhang <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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We need to have clocks accessible via phandle to select them
as peripheral clock parent using assigned-clock-parents in DT.
Add support for PLLACK/PLLBCK/AUDIOPLLCK clocks where available.
Signed-off-by: Michał Mirosław <[email protected]>
Acked-by: Alexandre Belloni <[email protected]>
Link: https://lkml.kernel.org/r/fa39cc10dab8341ea4bc2b7152be9217b2cd34a5.1588630999.git.mirq-linux@rere.qmqm.pl
Signed-off-by: Stephen Boyd <[email protected]>
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This exposes PROGx clocks for use in assigned-clocks DeviceTree property
for selecting PCKx parent clock.
Signed-off-by: Michał Mirosław <[email protected]>
Link: https://lkml.kernel.org/r/0054532c00163ddf405dad658b32f0d7d97fcc8e.1588630999.git.mirq-linux@rere.qmqm.pl
Acked-by: Alexandre Belloni <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The gcc_sec_ctrl_clk_src clock is required to be controlled by the
secure controller driver.
Signed-off-by: Taniya Das <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Document the Agilex clock bindings, and add the clock header file. The
clock header is an enumeration of all the different clocks on the Agilex
platform.
Signed-off-by: Dinh Nguyen <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Clock generation unit(CGU) is a clock controller IP of Intel's Lightning
Mountain(LGM) SoC. Add DT bindings include file and document for CGU clock
controller driver of LGM.
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Rahul Tanwar <[email protected]>
Link: https://lkml.kernel.org/r/8dce2be13195aab20c6b11fca6af0fffe22d5241.1587102634.git.rahul.tanwar@linux.intel.com
Signed-off-by: Stephen Boyd <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers
media: tegra: Changes for v5.8-rc1
This contains a V4L2 video capture driver for Tegra210.
* tag 'tegra-for-5.8-media' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
media: tegra-video: Do not enable COMPILE_TEST
MAINTAINERS: correct path in TEGRA VIDEO DRIVER
media: tegra-video: Make tegra210_video_formats static
MAINTAINERS: Add Tegra Video driver section
media: tegra-video: Add Tegra210 Video input driver
dt-bindings: i2c: tegra: Document Tegra210 VI I2C
dt-bindings: tegra: Add VI and CSI bindings
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
dt-bindings: memory: tegra: Add external memory controller binding for Tegra210
dt-bindings: clock: tegra: Remove PMC clock IDs
dt-bindings: clock: tegra: Add clock ID for CSI TPG clock
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
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Use imx8m_clk_hw_composite_core to simpliy clks that belong to
core clk slice.
Reviewed-by: Leonard Crestez <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Inspried from
commit e8688fe8df7d ("clk: imx8mn: Define gates for pll1/2 fixed dividers")
On imx8mp there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.
Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.
Reviewed-by: Dong Aisheng <[email protected]>
Reviewed-by: Leonard Crestez <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add compatible strings and the include files for the MSM8939 GCC.
Cc: Andy Gross <[email protected]>
Cc: Bjorn Andersson <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Tested-by: Vincent Knecht <[email protected]>
Signed-off-by: Bryan O'Donoghue <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Reviewed-by: Rob Herring <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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Introduce the low jitter path of PLLP and PLLMB which can be used as EMC
clock source.
Signed-off-by: Joseph Lo <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock
ID for this CSI TPG clock from PLLD.
Acked-by: Rob Herring <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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clk_out_1, clk_out_2, clk_out_3, blink are part of Tegra PMC block so
these clocks should be provided by the Tegra PMC. IDs for these clocks
have been defined in dt-bindings/soc/tegra-pmc.h.
This patch removes the IDs for these clocks from the Tegra clock device
tree bindings.
Tested-by: Dmitry Osipenko <[email protected]>
Reviewed-by: Dmitry Osipenko <[email protected]>
Acked-by: Rob Herring <[email protected]>
Signed-off-by: Sowjanya Komatineni <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
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Add all the clock ids for the audiomix clocks.
Signed-off-by: Abel Vesa <[email protected]>
Acked-by: Rob Herring <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add all RZ/G1H Clock Pulse Generator Core Clock Outputs, as listed in
Table 7.2a ("List of Clocks [RZ/G1H]") of the RZ/G1 Hardware User's
Manual.
Signed-off-by: Lad Prabhakar <[email protected]>
Reviewed-by: Marian-Cristian Rotariu <[email protected]>
Link: https://lore.kernel.org/r/1587678050-23468-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <[email protected]>
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ARM clk could only source from divcore or hsrun_divcore.
Follow what we already used on i.MX7D and i.MX8M SoCs, use
imx_clk_hw_cpu API. When ARM core is running normaly,
whether divcore or hwrun_divcore will finally source
from SPLL_PFD0. However SPLL_PFD0 is marked with CLK_SET_GATE,
so we need to disable SPLL_PFD0, when configure the rate.
So add CORE and HSRUN_CORE virtual clk to make it easy to
configure the clk using imx_clk_hw_cpu API.
Since CORE and HSRUN_CORE already marked with CLK_IS_CRITICAL, no
need to set ARM as CLK_IS_CRITICAL. And when set the rate of ARM clk,
prograting it the parent with CLK_SET_RATE_PARENT will finally set
the SPLL_PFD0 clk.
Signed-off-by: Peng Fan <[email protected]>
Reviewed-by: Abel Vesa <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Export the HDMI system clock (used by the HDMI transmitter) so it can be
used in the dt-bindings.
Signed-off-by: Martin Blumenstingl <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
"This contains a handful of new features:
- Partial support for the Kendryte K210.
There are still a few outstanding issues that I have patches for,
but I don't actually have a board to test them so they're not
included yet.
- SBI v0.2 support.
- Fixes to support for building with LLVM-based toolchains. The
resulting images are known not to boot yet.
I don't anticipate a part two, but I'll probably have something early
in the RCs to finish up the K210 support"
* tag 'riscv-for-linus-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (38 commits)
riscv: create a loader.bin boot image for Kendryte SoC
riscv: Kendryte K210 default config
riscv: Add Kendryte K210 device tree
riscv: Select required drivers for Kendryte SOC
riscv: Add Kendryte K210 SoC support
riscv: Add SOC early init support
riscv: Unaligned load/store handling for M_MODE
RISC-V: Support cpu hotplug
RISC-V: Add supported for ordered booting method using HSM
RISC-V: Add SBI HSM extension definitions
RISC-V: Export SBI error to linux error mapping function
RISC-V: Add cpu_ops and modify default booting method
RISC-V: Move relocate and few other functions out of __init
RISC-V: Implement new SBI v0.2 extensions
RISC-V: Introduce a new config for SBI v0.1
RISC-V: Add SBI v0.2 extension definitions
RISC-V: Add basic support for SBI v0.2
RISC-V: Mark existing SBI as 0.1 SBI.
riscv: Use macro definition instead of magic number
riscv: Add support to dump the kernel page tables
...
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git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"There's not much to see in the core framework this time around.
Instead the majority of the diff is the normal collection of driver
additions for new SoCs and non-critical clk data fixes and updates.
The framework must be middle aged.
The two biggest directories in the diffstat show that the Qualcomm and
Unisoc support added a handful of big drivers for new SoCs but that's
not really the whole story because those new drivers tend to add large
numbers of lines of clk data. There's a handful of AT91 clk drivers
added this time around too and a bunch of improvements to drivers like
the i.MX driver. All around lots of updates and fixes in various clk
drivers which is good to see.
The core framework has only one real major change which has been
baking in next for the past couple months. It fixes the framework so
that it stops caching a clk's phase when the phase clk_op returns an
error. Before this change we would consider some negative errno as a
phase and that just doesn't make sense.
Core:
- Don't show clk phase when it is invalid
New Drivers:
- Add support for Unisoc SC9863A clks
- Qualcomm SM8250 RPMh and MSM8976 RPM clks
- Qualcomm SM8250 Global Clock Controller (GCC) support
- Qualcomm SC7180 Modem Clock Controller (MSS CC) support
- EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs
- Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and
at91sam9g45 SoCs
Updates:
- GPU GX GDSC support on Qualcomm sc7180
- Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers
- A series from Anson to convert i.MX8 clock bindings to json-schema
- Update i.MX pll14xx driver to include new frequency entries for
pll1443x table, and return error for invalid PLL type
- Add missing of_node_put() call for a number of i.MX clock drivers
- Drop flag CLK_IS_CRITICAL from 'A53_CORE' mux clock, as we already
have the flag on its child cpu clock
- Fix a53 cpu clock for i.MX8 drivers to get it source from ARM PLL
via CORE_SEL slice, and source from A53 CCM clk root when we need
to change ARM PLL frequency. Thus, we can support core running
above 1GHz safely
- Update i.MX pfdv2 driver to check zero rate and use determine_rate
for getting the best rate
- Add CLKO2 for imx8mm, SNVS clock for imx8mn, and PXP clock for
imx7d
- Remove PMC clks from Tegra clk driver
- Improved clock/reset handling for the Renesas R-Car USB2 Clock
Selector
- Conversion to json-schema of the Renesas CPG/MSSR DT bindings
- Add Crypto clocks on Renesas R-Car M3-W/W+, M3-N, E3, and D3
- Add RPC (QSPI/HyperFLASH) clocks on Renesas R-Car H3, M3-W/W+, and
M3-N
- Update Amlogic audio clock gate hierarchy for meson8 and gxbb
- Update Amlogic g12a spicc clock sources
- Support for Ingenic X1000 TCU clks"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (146 commits)
clk: sprd: fix to get a correct ibias of pll
dt-bindings: imx8mm-clock: Fix the file path
dt-bindings: imx8mq-clock: Fix the file path
clk: qcom: rpmh: Drop unnecessary semicolons
clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd()
clk: tegra: Use NULL for pointer initialization
clk: sprd: add clocks support for SC9863A
clk: sprd: support to get regmap from parent node
clk: sprd: Add macros for referencing parents without strings
clk: sprd: Add dt-bindings include file for SC9863A
dt-bindings: clk: sprd: add bindings for sc9863a clock controller
dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific
clk: sprd: add gate for pll clocks
MAINTAINERS: dt: update reference for arm-integrator.txt
clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks
clk: mmp2: Add clock for fifth SD HCI on MMP3
dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3
clk: mmp2: Add clocks for the thermal sensors
dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors
clk: mmp2: add the GPU clocks
...
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Pull ARM devicetree updates from Arnd Bergmann:
"Most of the commits are for additional hardware support and minor
fixes for existing machines for all the usual platforms: qcom,
amlogic, at91, gemini, mediatek, ti, socfpga, i.mx, layerscape,
uniphier, rockchip, exynos, ux500, mvebu, tegra, stm32, renesas,
sunxi, broadcom, omap, and versatile.
The conversion of binding files to machine-readable yaml format
continues, along with fixes found during the validation. Andre
Przywara takes over maintainership for the old Calxeda Highbank
platform and provides a number of updates.
The OMAP2+ platforms see a continued move from platform data into dts
files, for many devices that relied on a mix of auxiliary data in
addition to the DT description
A moderate number of new SoCs and machines are added, here is a full
list:
- Two new Qualcomm SoCs with their evaluation boards: Snapdragon 865
(SM8250) is the current high-end phone chip, and IPQ6018 is a new
WiFi-6 router chip.
- Mediatek MT8516 application processor SoC for voice assistants,
along with the "pumpkin" development board
- NXP i.MX8M Plus SoC, a variant of the popular i.MX8M, along with an
evaluation board.
- Kontron "sl28" board family based on NXP LS1028A
- Eleven variations of the new i.MX6 TechNexion Pico board, combining
the "dwarf", "hobbit", "nymph" and "pi" baseboards with i.MX6/i.MX7
SoM carriers
- Three additional variants of the Toradex Colibri board family, all
based on versions of the NXP i.MX7.
- The Pinebook Pro laptop based on Rockchip RK3399
- Samsung S7710 Galaxy Xcover 2, a 2013 vintage Android phone based
on the ST-Ericsson u8500 platform
- DH Electronics DHCOM SoM and PDK2 rev. 400 carrier based on
STMicroelectronics stm32mp157
- Renesas M3ULCB starter kit for R-Car M3-W+
- Hoperun HiHope development board with Renesas RZ/G2M
- Pine64 PineTab tablet and PinePhone phone, both based on Allwinner
A64
- Linutronix Testbox v2 for the Lamobo R1 router, based on Allwinner
A20
- PocketBook Touch Lux 3 ebook reader, based on Allwinner A13"
* tag 'arm-dt-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (520 commits)
ARM: dts: ux500: Fix missing node renames
arm64: dts: Revert "specify console via command line"
MAINTAINERS: Update Calxeda Highbank maintainership
arm: dts: calxeda: Group port-phys and sgpio-gpio items
arm: dts: calxeda: Fix interrupt grouping
arm: dts: calxeda: Provide UART clock
arm: dts: calxeda: Basic DT file fixes
arm64: dts: specify console via command line
ARM: dts: at91: sama5d27_wlsom1_ek: add USB device node
ARM: dts: gemini: Add thermal zone to DIR-685
ARM: dts: gemini: Rename IDE nodes
ARM: socfpga: arria10: Add ptp_ref clock to ethernet nodes
arm64: dts: ti: k3-j721e-mcu: add scm node and phy-gmii-sel nodes
arm64: dts: ti: k3-am65-mcu: add phy-gmii-sel node
arm64: dts: ti: k3-am65-mcu: Add DMA entries for ADC
arm64: dts: ti: k3-am65-main: Add DMA entries for main_spi0
arm64: dts: ti: k3-j721e-mcu-wakeup: Add DMA entries for ADC
arm64: dts: ti: k3-am65: Add clocks to dwc3 nodes
arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node
arm64: dts: khadas-vim3: add SPIFC controller node
...
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- Add support for Unisoc SC9863A clks
- GPU GX GDSC support on Qualcomm sc7180
- Qualcomm SM8250 RPMh and MSM8976 RPM clks
- Qualcomm SM8250 Global Clock Controller (GCC) support
- Qualcomm SC7180 Modem Clock Controller (MSS CC) support
* clk-unisoc:
clk: sprd: fix to get a correct ibias of pll
clk: sprd: add clocks support for SC9863A
clk: sprd: support to get regmap from parent node
clk: sprd: Add macros for referencing parents without strings
clk: sprd: Add dt-bindings include file for SC9863A
dt-bindings: clk: sprd: add bindings for sc9863a clock controller
dt-bindings: clk: sprd: rename the common file name sprd.txt to SoC specific
clk: sprd: add gate for pll clocks
* clk-tegra:
clk: tegra: Use NULL for pointer initialization
clk: tegra: Remove audio clocks configuration from clock driver
clk: tegra: Remove tegra_pmc_clk_init along with clk ids
clk: tegra: Remove CLK_M_DIV fixed clocks
clk: tegra: Fix Tegra PMC clock out parents
clk: tegra: Add Tegra OSC to clock lookup
clk: tegra: Add support for OSC_DIV fixed clocks
dt-bindings: soc: tegra-pmc: Add ID for Tegra PMC 32 kHz blink clock
dt-bindings: soc: tegra-pmc: Add Tegra PMC clock bindings
dt-bindings: tegra: Convert Tegra PMC bindings to YAML
dt-bindings: clock: tegra: Add IDs for OSC clocks
* clk-qcom: (21 commits)
clk: qcom: rpmh: Drop unnecessary semicolons
clk: qcom: rpmh: Simplify clk_rpmh_bcm_send_cmd()
clk: qcom: gcc: Add USB3 PIPE clock and GDSC for SM8150
ipq806x: gcc: Added the enable regs and mask for PRNG
clk: qcom: Add modem clock controller driver for SC7180
clk: qcom: gcc: Add support for modem clocks in GCC
dt-bindings: clock: Add YAML schemas for the QCOM MSS clock bindings
clk: qcom: clk-rpm: add missing rpm clk for ipq806x
clk: qcom: gcc: Add global clock controller driver for SM8250
dt-bindings: clock: Add SM8250 GCC clock bindings
clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs
clk: qcom: clk-alpha-pll: Refactor trion PLL
clk: qcom: clk-alpha-pll: Use common names for defines
dt-bindings: clock: rpmcc: Document msm8976 compatible
clk: qcom: smd: Add support for MSM8976 rpm clocks
clk: qcom: clk-rpmh: Wait for completion when enabling clocks
clk: qcom: rpmh: Add support for RPMH clocks on SM8250
dt-bindings: clock: Add RPMHCC bindings for SM8250
clk: qcom: alpha-pll: Make error prints more informative
clk: qcom: gpucc: Add support for GX GDSC for SC7180
...
* clk-imx: (43 commits)
dt-bindings: imx8mm-clock: Fix the file path
dt-bindings: imx8mq-clock: Fix the file path
clk: imx: clk-gate2: Pass the device to the register function
clk: imx7d: Add PXP clock
clk: imx8mq: A53 core clock no need to be critical
clk: imx8mp: A53 core clock no need to be critical
clk: imx8mm: A53 core clock no need to be critical
clk: imx8mn: A53 core clock no need to be critical
clk: imx: pllv4: use prepare/unprepare
clk: imx: pfdv2: determine best parent rate
clk: imx: pfdv2: switch to use determine_rate
clk: imx: Fix division by zero warning on pfdv2
clk: imx: clk-sscg-pll: Drop unnecessary initialization
clk: imx: pll14xx: Return error if pll type is invalid
clk: imx: imx8mp: fix a53 cpu clock
clk: imx: imx8mn: fix a53 cpu clock
clk: imx: imx8mm: fix a53 cpu clock
clk: imx: imx8mq: fix a53 cpu clock
clk: imx8mp: Rename the IMX8MP_CLK_HDMI_27M clock
clk: imx8mn: Remove unused includes
...
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and 'clk-arm-icst' into clk-next
- EHRPWM's TimeBase clock(TBCLK) for TI AM654 SoCs
- Support PMC clks on at91sam9n12, at91rm9200, sama5d3, and at91sam9g45 SoCs
- Fixes and improvements for the Marvell MMP2/MMP3 SoC clk drivers
* clk-ti:
clk: keystone: Add new driver to handle syscon based clocks
dt-bindings: clock: Add binding documentation for TI EHRPWM TBCLK
* clk-ingenic:
clk: ingenic/TCU: Fix round_rate returning error
clk: ingenic/jz4770: Exit with error if CGU init failed
clk: JZ4780: Add function for enable the second core.
clk: Ingenic: Add support for TCU of X1000.
* clk-typo:
clk: Fix trivia typo in comment exlusive => exclusive
* clk-at91:
clk: at91: add at91rm9200 pmc driver
clk: at91: add at91sam9n12 pmc driver
clk: at91: add sama5d3 pmc driver
clk: at91: add at91sam9g45 pmc driver
clk: at91: usb: introduce num_parents in driver's structure
clk: at91: usb: use proper usbs_mask
clk: at91: sam9x60: fix usb clock parents
clk: at91: usb: continue if clk_hw_round_rate() return zero
clk: at91: sam9x60: Don't use audio PLL
* clk-mmp2:
clk: mmp2: Fix bit masks for LCDC I/O and pixel clocks
clk: mmp2: Add clock for fifth SD HCI on MMP3
dt-bindings: marvell,mmp2: Add clock id for the fifth SD HCI on MMP3
clk: mmp2: Add clocks for the thermal sensors
dt-bindings: marvell,mmp2: Add clock ids for the thermal sensors
clk: mmp2: add the GPU clocks
dt-bindings: marvell,mmp2: Add clock ids for the GPU clocks
clk: mmp2: Add PLLs that are available on MMP3
dt-bindings: marvell,mmp2: Add clock ids for MMP3 PLLs
clk: mmp2: Check for MMP3
dt-bindings: clock: Add MMP3 compatible string
clk: mmp2: Stop pretending PLL outputs are constant
clk: mmp2: Add support for PLL clock sources
dt-bindings: clock: Convert marvell,mmp2-clock to json-schema
clk: mmp2: Constify some strings
clk: mmp2: Remove a unused prototype
* clk-arm-icst:
MAINTAINERS: dt: update reference for arm-integrator.txt
clk: versatile: Add device tree probing for IM-PD1 clocks
clk: versatile: Export icst_clk_setup()
dt-bindings: clock: Create YAML schema for ICST clocks
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'clk-allwinner' into clk-next
- Don't show clk phase when it is invalid
* clk-phase-errors:
clk: rockchip: fix mmc get phase
clk: Fix phase init check
clk: Bail out when calculating phase fails during clk registration
clk: Move rate and accuracy recalc to mostly consumer APIs
clk: Use 'parent' to shorten lines in __clk_core_init()
clk: Don't cache errors from clk_ops::get_phase()
* clk-amlogic:
clk: meson: meson8b: set audio output clock hierarchy
clk: meson: g12a: add support for the SPICC SCLK Source clocks
dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs
clk: meson: gxbb: set audio output clock hierarchy
clk: meson: gxbb: add the gxl internal dac gate
dt-bindings: clk: meson: add the gxl internal dac gate
* clk-renesas:
dt-bindings: clock: renesas: cpg-mssr: Convert to json-schema
clk: renesas: rcar-usb2-clock-sel: Add reset_control
clk: renesas: rcar-usb2-clock-sel: Add multiple clocks management
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add power-domains and resets properties
dt-bindings: clock: renesas: rcar-usb2-clock-sel: Fix clock[-name]s properties
clk: renesas: Remove use of ARCH_R8A7795
clk: renesas: r8a77965: Add RPC clocks
clk: renesas: r8a7796: Add RPC clocks
clk: renesas: r8a7795: Add RPC clocks
clk: renesas: rcar-gen3: Add CCREE clocks
* clk-allwinner:
clk: sunxi-ng: sun8i-de2: Sort structures
clk: sunxi-ng: sun8i-de2: Add R40 specific quirks
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A83T
clk: sunxi-ng: sun8i-de2: Don't reuse A83T resets
clk: sunxi-ng: sun8i-de2: H6 doesn't have rotate core
clk: sunxi-ng: sun8i-de2: Add rotation core clocks and reset for A64
clk: sunxi-ng: sun8i-de2: Split out H5 definitions
clk: sunxi-ng: a64: Export MBUS clock
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Pull ARM SoC updates from Arnd Bergmann:
"The code changes are mostly for 32-bit platforms and include:
- Lots of updates for the Nvidia Tegra platform, including cpuidle,
pmc, and dt-binding changes
- Microchip at91 power management updates for the recently added
sam9x60 SoC
- Treewide setup_irq deprecation by afzal mohammed
- STMicroelectronics stm32 gains earlycon support
- Renesas platforms with Cortex-A9 can now use the global timer
- Some TI OMAP2+ platforms gain cpuidle support
- Various cleanups for the i.MX6 and Orion platforms, as well as
Kconfig files across all platforms"
* tag 'arm-soc-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (75 commits)
ARM: qcom: Add support for IPQ40xx
ARM: mmp: replace setup_irq() by request_irq()
ARM: cns3xxx: replace setup_irq() by request_irq()
ARM: spear: replace setup_irq() by request_irq()
ARM: ep93xx: Replace setup_irq() by request_irq()
ARM: iop32x: replace setup_irq() by request_irq()
arm: mach-dove: Mark dove_io_desc as __maybe_unused
ARM: orion: replace setup_irq() by request_irq()
ARM: debug: stm32: add UART early console support for STM32MP1
ARM: debug: stm32: add UART early console support for STM32H7
ARM: debug: stm32: add UART early console configuration for STM32F7
ARM: debug: stm32: add UART early console configuration for STM32F4
cpuidle: tegra: Disable CC6 state if LP2 unavailable
cpuidle: tegra: Squash Tegra114 driver into the common driver
cpuidle: tegra: Squash Tegra30 driver into the common driver
cpuidle: Refactor and move out NVIDIA Tegra20 driver into drivers/cpuidle
ARM: tegra: cpuidle: Remove unnecessary memory barrier
ARM: tegra: cpuidle: Make abort_flag atomic
ARM: tegra: cpuidle: Handle case where secondary CPU hangs on entering LP2
ARM: tegra: Make outer_disable() open-coded
...
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Include originally "late" updates for OMAP and Qualcomm,
now that it's not late any more.
* arm/late: (122 commits)
ARM: OMAP2+: Drop legacy platform data for ti81xx edma
ARM: dts: Configure interconnect target module for ti816x edma
ARM: dts: Configure interconnect target module for dm814x tptc3
ARM: dts: Configure interconnect target module for dm814x tptc2
ARM: dts: Configure interconnect target module for dm814x tptc1
ARM: dts: Configure interconnect target module for dm814x tptc0
ARM: dts: Configure interconnect target module for dm814x tpcc
ARM: OMAP2+: Drop legacy platform data for dm814x cpsw
ARM: dts: Configure interconnect target module for dm814x cpsw
clk: ti: Fix dm814x clkctrl for ethernet
arm64: dts: qcom: sdm845-mtp: Relocate remoteproc firmware
arm64: dts: sdm845: add IPA information
arm64: dts: qcom: db845c: add analog audio support
arm64: dts: qcom: sdm845: add pinctrl nodes for quat i2s
arm64: dts: qcom: c630: Enable audio support
arm64: dts: qcom: sdm845: add apr nodes
arm64: dts: qcom: sdm845: add slimbus nodes
arm64: dts: qcom: sc7180: Update reg names for SDHC
arm64: dts: qcom: qcs404: Enable CQE support for eMMC
arm64: dts: msm8916: Add fastrpc node
...
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Add a generic device tree for Kendryte K210 SoC based boards. This is
for now a very simple device tree describing the core elements of the
SoC. This is suitable (and tested) for the Kendryte KD233 development
board, the Sipeed MAIX M1 Dan Dock board and the Sipeed MAIXDUINO board.
Signed-off-by: Damien Le Moal <[email protected]>
Reviewed-by: Sean Anderson <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt
arm64: dts: Amlogic updates for v5.7 (round 2)
- G12[ab]: add SPI support, enable on odroid-n2
* tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
arm64: dts: meson-g12b-odroid-n2: add SPIFC controller node
arm64: dts: khadas-vim3: add SPIFC controller node
arm64: dts: meson-g12: add the SPIFC nodes
arm64: dts: meson-g12: split emmc pins to select 4 or 8 bus width
arm64: dts: meson-g12-common: add spicc controller nodes
dt-bindings: clk: g12a-clkc: add SPICC SCLK Source clock IDs
dt-bindings: clk: meson: add the gxl internal dac gate
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
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git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt
i.MX arm64 DTS update for 5.7:
- New support for Kontron LS1028A based boards and NXP i.MX8MP EVK.
- Add Ethernet PHY reset GPIO for imx8mm-evk and imx8mq-evk board.
- Add gpio-fan, thermal and Ethernet support for imx8mq-phanbell board.
- Add SNVS clock description to pwrkey device for i.MX8 SoCs.
- A number of updates on librem5-devkit board to add audio, proximity
sensor, lsm9ds1 mount matrix support, and improve WoWWAN, DVFS, SD
devices as well.
- A series of patches from Anson Huang to update i.MX8 EVK boards
for support of I2C PCA6416, thermal, GPIO LED, OPP table etc.
- Add PCIe device nodes for LX2160A and LS1028A SoC.
- Add FSPI deivce support for LX2160A evaluation boards.
- Add EEPROM and LTC3882 regulator support for lx2160a-cex7 board.
- Other small and random updates on LS1028A and i.MX8 support.
* tag 'imx-dt64-5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (63 commits)
arm64: dts: ls1028a: disable the felix switch by default
arm64: dts: imx8mp: Add snvs clock to powerkey
arm64: dts: imx8mn: Add snvs clock to powerkey
arm64: dts: ls1028a: Add PCIe controller DT nodes
arm64: dts: ls1028a: sl28: add support for variant 2
arm64: dts: ls1028a: sl28: expose switch ports in KBox A-230-LS
arm64: dts: ls1028a: sl28: fix on-board EEPROMS
arm64: dts: freescale: sl28: add SPI flash
arm64: dts: imx8m: fix aips dts node
arm64: dts: imx8mn: Add CPU thermal zone support
arm64: dts: imx8mm: Add thermal zone support
arm64: dts: imx8mq-phanbell: Fix Ethernet PHY post-reset duration
arm64: dts: enable fspi in imx8mm dts
arm64: dts: imx8mn: align name for crypto child nodes
arm64: dts: lx2160aqds: Add FSPI node properties
arm64: dts: lx2160ardb: Update FSPI node properties
arm64: dts: imx8mq-phanbell: Add gpio-fan/thermal support
arm64: dts: layerscape: add iommu-map property to pci nodes
arm64: dts: imx8mp-evk: Enable pca6416 on i2c3 bus
arm64: dts: imx8mp-evk: Add i2c3 support
...
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Arnd Bergmann <[email protected]>
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This file defines all SC9863A clock indexes, it should be included in the
device tree in which there's device using the clocks.
Signed-off-by: Chunyan Zhang <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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There's one extra SDHCI on MMP3, used by the internal SD card on OLPC
XO-4. Add a clock for it.
Signed-off-by: Lubomir Rintel <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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There seems to be a single thermal sensor block on MMP2 and a couple
more on MMP3. Add definitions for their respective clocks.
Signed-off-by: Lubomir Rintel <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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MMP2 has a single GC860 core while MMP3 has a GC2000 and a GC300.
On both platforms there's an AXI bus interface clock that's common for
all GPUs and each GPU core has a separate clock.
Signed-off-by: Lubomir Rintel <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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MMP3 variant provides some more clocks. Add respective IDs.
Signed-off-by: Lubomir Rintel <[email protected]>
Acked-by: Rob Herring <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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This adds the USB3 PIPE clock and GDSC structures, so
that the USB driver can vote for these resources to be
enabled/disabled when required. Both are needed for SS
and HS USB paths to operate properly. The GDSC will
allow the USB system to be brought out of reset, while
the PIPE clock is needed for data transactions between
the PHY and controller.
Signed-off-by: Wesley Cheng <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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The Modem Subsystem clock provider have a bunch of generic properties
that are needed in a device tree. Add a YAML schemas for those.
Add clock ids for GCC MSS and MSS clocks which are required to bring
the modem out of reset.
Signed-off-by: Taniya Das <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Reviewed-by: Rob Herring <[email protected]>
Tested-by: Sibi Sankar <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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We are missing alwon ethernet clock for dm814x and this prevents us
from probing the CPSW with device tree only data. Looks like Ethernet
currently only works if it has been enabled in the bootloader.
Looks like relying on the bootloader clocks is not an issue with the
mainline kernel currently, but it will be an issue when configuring
CPSW Ethernet to probe with device tree data only as we will be managing
the clocks.
Fixes: 26ca2e973844 ("clk: ti: dm814: add clkctrl clock data")
Cc: [email protected]
Cc: Graeme Smecher <[email protected]>
Cc: Grygorii Strashko <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Tero Kristo <[email protected]>
Acked-by: Stephen Boyd <[email protected]>
Signed-off-by: Tony Lindgren <[email protected]>
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The PXP has a single CCGR clock gate, gating both the IPG_CLK_ROOT and
the MAIN_AXI_CLK_ROOT. Add a single clock to cover both.
Signed-off-by: Laurent Pinchart <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add missing definition of rpm clk for ipq806x soc
Signed-off-by: John Crispin <[email protected]>
Signed-off-by: Ansuel Smith <[email protected]>
Acked-by: John Crispin <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
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Add device tree bindings for global clock controller on SM8250 SoCs.
Signed-off-by: Taniya Das <[email protected]>
Signed-off-by: Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Reviewed-by: Rob Herring <[email protected]>
Reviewed-by: Bryan O'Donoghue <[email protected]>
Tested-by: Bryan O'Donoghue <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root
signoff timing is 1Ghz, however the A53 core which sources from CCM
root could run above 1GHz which voilates the CCM.
There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.
The A53 CCM clk root should only be used when need to change ARM PLL
frequency.
Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Mark arm_a53_core as critical clk
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root
signoff timing is 1Ghz, however the A53 core which sources from CCM
root could run above 1GHz which voilates the CCM.
There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.
The A53 CCM clk root should only be used when need to change ARM PLL
frequency.
Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Mark arm_a53_core as critical clk.
Fixes: 96d6392b54db ("clk: imx: Add support for i.MX8MN clock driver")
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root
signoff timing is 1Ghz, however the A53 core which sources from CCM
root could run above 1GHz which voilates the CCM.
There is a CORE_SEL slice before A53 core, we need configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.
The A53 CCM clk root should only be used when need to change ARM PLL
frequency.
Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Mark arm_a53_core as critical clock
Fixes: ba5625c3e272 ("clk: imx: Add clock driver support for imx8mm")
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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The A53 CCM clk root only accepts input up to 1GHz, CCM A53 root
signoff timing is 1Ghz, however the A53 core which sources from CCM
root could run above 1GHz which violates the CCM.
There is a CORE_SEL slice before A53 core, we need to configure the
CORE_SEL slice source from ARM PLL, not A53 CCM clk root.
The A53 CCM clk root should only be used when need to change ARM PLL
frequency.
Add arm_a53_core clk that could source from arm_a53_div and arm_pll_out.
Configure a53 ccm root sources from 800MHz sys pll
Configure a53 core sources from arm_pll_out
Mark arm_a53_core as critical clock
Fixes: db27e40b27f1 ("clk: imx8mq: Add the missing ARM clock")
Reviewed-by: Jacky Bai <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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On i.MX8MP, internal HDMI 27M clock is actually 24MHz, so rename
the IMX8MP_CLK_HDMI_27M to IMX8MP_CLK_HDMI_24M.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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Add clock ids used by the SPICC Controllers of the G12A and compatible SoCs
Signed-off-by: Neil Armstrong <[email protected]>
Signed-off-by: Jerome Brunet <[email protected]>
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