| Age | Commit message (Collapse) | Author | Files | Lines | |
|---|---|---|---|---|---|
| 2020-04-28 | clk: renesas: Add r8a7742 CPG Core Clock Definitions | Lad Prabhakar | 1 | -0/+42 | |
| Add all RZ/G1H Clock Pulse Generator Core Clock Outputs, as listed in Table 7.2a ("List of Clocks [RZ/G1H]") of the RZ/G1 Hardware User's Manual. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1587678050-23468-8-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> | |||||