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Since i.MX7ULP B0 chip, SNVS module is moved into M4
domain, so remove it from Linux clock table.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
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There are HSRUN mode clock mux and divider in SCG1 module,
and SMC1 can control i.MX7ULP CPU to run in RUN mode or
HSRUN mode, the mode switch bits are actually a clock mux,
add these clocks for clock driver and dtb to use.
Signed-off-by: Anson Huang <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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i.MX7ULP Clock functions are under joint control of the System
Clock Generation (SCG) modules, Peripheral Clock Control (PCC)
modules, and Core Mode Controller (CMC)1 blocks
Note IMX7ULP has two clock domains: M4 and A7. This binding doc
is only for A7 clock domain.
Cc: Rob Herring <[email protected]>
Cc: Mark Rutland <[email protected]>
Cc: Stephen Boyd <[email protected]>
Cc: Michael Turquette <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Anson Huang <[email protected]>
Cc: Bai Ping <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
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